43636 lines
2.8 MiB
43636 lines
2.8 MiB
; --------------------------------------------------------------------------------
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; @Title: ATSAMA7G5 On-Chip Peripherals
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; @Props: Released
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; @Author: NEJ
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; @Changelog: 2023-06-23 NEJ
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; 2023-11-07 NEJ
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; 2023-11-23 NEJ
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; @Manufacturer: MICROCHIP - Microchip Technology Inc.
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; @Doc: Generated (TRACE32, build: 164623.), based on:
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; SAMA7G54.svd (Ver. 0)
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; @Core: Cortex-A7
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; @Chip: ATSAMA7G54
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; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: peratsama7g5.per 17113 2023-11-28 15:11:41Z kwisniewski $
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AUTOINDENT.ON CENTER TREE
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ENUMDELIMITER ","
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base ad:0x0
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "Core Registers (Cortex-A7)"
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; --------------------------------------------------------------------------------
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; Identification registers
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; --------------------------------------------------------------------------------
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width 10.
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tree "ID Registers"
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group.long c15:0x0++0x0
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line.long 0x0 "MIDR,Main ID Register"
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hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
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bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 16.--19. " ARCH , Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7"
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textline " "
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hexmask.long.word 0x0 4.--15. 1. " PART ,Primary Part Number"
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bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
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rgroup.long c15:0x100++0x0
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line.long 0x0 "CTR,Cache Type Register"
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bitfld.long 0x0 29.--31. " FORMAT ,Format" "Reserved,Reserved,Reserved,Reserved,ARMv7,?..."
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bitfld.long 0x0 24.--27. " CWG ,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
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bitfld.long 0x0 20.--23. " ERG ,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
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textline " "
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bitfld.long 0x0 16.--19. " DMINLINE ,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
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bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,Reserved,Reserved,Physical"
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bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,8 words,16 words,?..."
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elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
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rgroup.long c15:0x100++0x0
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line.long 0x0 "CTR,Cache Type Register"
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bitfld.long 0x0 29.--31. " FORMAT ,Format" "Reserved,Reserved,Reserved,Reserved,ARMv7,?..."
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bitfld.long 0x0 24.--27. " CWG ,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
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bitfld.long 0x0 20.--23. " ERG ,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
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textline " "
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bitfld.long 0x0 16.--19. " DMINLINE ,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
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bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..."
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bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,8 words,?..."
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endif
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rgroup.long c15:0x300++0x0
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line.long 0x0 "TLBTR,TLB Type Register"
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bitfld.long 0x0 0. " NU ,Unified or Separate TLBs" "Unified,?..."
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rgroup.long c15:0x500++0x0
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line.long 0x0 "MPIDR,Multiprocessor Affinity Register"
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bitfld.long 0x00 31. " MPERF ,Multiprocessing Extensions register format" "Not supported,Supported"
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bitfld.long 0x00 30. " U ,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,Uniprocessor"
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bitfld.long 0x00 24. " MT ,Lowest level of affinity consist of logical processors" "Not implemented,Implemented"
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textline " "
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bitfld.long 0x00 8.--11. " CLUSTERID ,Value read in CLUSTERID configuration pins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--1. " CPUID ,Value depends on the number of configured CPUs" "1,2,3,4"
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rgroup.long c15:0x400++0x0
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line.long 0x0 "MIDR2,Main ID Register"
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hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
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bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 16.--19. " ARCH , Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7"
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textline " "
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hexmask.long.word 0x0 4.--15. 1. " PART ,Primary Part Number"
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bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.long c15:0x600++0x0
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line.long 0x0 "REVIDR,Revision ID Register"
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rgroup.long c15:0x700++0x0
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line.long 0x0 "MIDR3,Main ID Register"
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hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
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bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 16.--19. " ARCH , Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7"
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textline " "
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hexmask.long.word 0x0 4.--15. 1. " PART ,Primary Part Number"
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bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
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rgroup.long c15:0x0410++0x00
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 28.--31. " IS ,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..."
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bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Not supported,?..."
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bitfld.long 0x00 20.--23. " AR ,Auxiliary Register Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
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bitfld.long 0x00 12.--15. " SL ,Shareability levels" "Reserved,Implemented 2 levels,?..."
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bitfld.long 0x00 8.--11. " OSS ,Outer Shareable Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,PXN,64-bit,?..."
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elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
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rgroup.long c15:0x0410++0x00
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 28.--31. " IS ,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..."
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bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Not supported,?..."
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bitfld.long 0x00 20.--23. " AR ,Auxiliary Register Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
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bitfld.long 0x00 12.--15. " SL ,Shareability levels" "Reserved,Implemented 2 levels,?..."
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bitfld.long 0x00 8.--11. " OSS ,Outer Shareable Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
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endif
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if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
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rgroup.long c15:0x0510++0x00
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line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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bitfld.long 0x00 28.--31. " BTB ,Branch Predictor" "Reserved,Reserved,Required,?..."
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bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
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bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..."
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elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
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rgroup.long c15:0x0510++0x00
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line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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bitfld.long 0x00 28.--31. " BTB ,Branch Predictor" "Reserved,Reserved,Reserved,Reserved,Required,?..."
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bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
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bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..."
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endif
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rgroup.long c15:0x0610++0x00
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
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bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
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bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
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bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
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rgroup.long c15:0x0710++0x00
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line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3"
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bitfld.long 0x00 28.--31. " SS ,Supersection support" "Supported,?..."
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bitfld.long 0x00 24.--27. " PMS ,Physical memory size supported by processor caches" "Reserved,Reserved,40-bit,?..."
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bitfld.long 0x00 20.--23. " CW ,Coherent walk" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " MB ,Maintenance broadcast Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " BPM ,Invalidate Branch predictor Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache MVA Support" "Reserved,Supported,?..."
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if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
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rgroup.long c15:0x0020++0x00
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line.long 0x00 "ID_ISAR0,Instruction Set Attribute Register 0"
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bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,BKPT,?..."
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bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Not supported,?..."
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elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
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rgroup.long c15:0x0020++0x00
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line.long 0x00 "ID_ISAR0,Instruction Set Attribute Register 0"
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bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,BKPT,?..."
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bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Supported,?..."
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endif
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rgroup.long c15:0x0120++0x00
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line.long 0x00 "ID_ISAR1,Instruction Set Attribute Register 1"
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bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " INTI ,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 12.--15. " EXTI ,Extend Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " EARI ,Exception A and R Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " EXIN ,Exception in ARM Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " ENDI ,Endian Instructions Support" "Reserved,Supported,?..."
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rgroup.long c15:0x0220++0x00
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line.long 0x00 "ID_ISAR2,Instruction Set Attribute Register 2"
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bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,MUL/MLA/MLS,?..."
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bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,PLD/PLI/PLWD,?..."
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bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,LDRD/STRD,?..."
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rgroup.long c15:0x0320++0x00
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line.long 0x00 "ID_ISAR3,Instruction Set Attribute Register 3"
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bitfld.long 0x00 28.--31. " TEEEI ,Thumb-EE Extensions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,TBB/TBH,?..."
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bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " SVCI ,SVC Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
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rgroup.long c15:0x0420++0x00
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line.long 0x00 "ID_ISAR4,Instruction Set Attribute Register 4"
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bitfld.long 0x00 28.--31. " SWP_FRAC ,Memory System Locking Support" "Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " PSR_M_I ,PSR_M Instructions Support" "Not supported,?..."
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bitfld.long 0x00 20.--23. " SPRI ,Synchronization Primitive instructions" "Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,DMB/DSB/ISB,?..."
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bitfld.long 0x00 12.--15. " SMCI ,SMC Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
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rgroup.long c15:0x0010++0x00
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 12.--15. " STATE3 ,Thumb Execution Environment (Thumb-EE) Support" "Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " STATE2 ,Support for Jazelle extension" "Not supported,?..."
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
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rgroup.long c15:0x0110++0x00
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line.long 0x00 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x00 16.--19. " GT ,Generic Timer Support" "Reserved,Supported,?..."
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bitfld.long 0x00 12.--15. " VE ,Virtualization Extensions Support" "Reserved,Supported,?..."
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|
bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
|
|
rgroup.long c15:0x0210++0x00
|
|
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x00 24.--27. " PMM ,Performance Monitor Model Support" "Reserved,Reserved,ID_DFR0,?..."
|
|
bitfld.long 0x00 20.--23. " MDM_MM ,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " TM_MM ,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CTM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7.1,?..."
|
|
bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7.1/CP14,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7.1/CP14,?..."
|
|
if (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
rgroup.long c15:0x6C9++0x0
|
|
line.long 0x00 "PMCEID0,Common Event Identification Register 0"
|
|
bitfld.long 0x00 29. " PMCEID0[29] ,Bus cycle" "Not implemented,Implemented"
|
|
bitfld.long 0x00 28. " [28] ,Instruction architecturally executed. Condition code check pass, write to TTBR" "Not implemented,Implemented"
|
|
bitfld.long 0x00 27. " [27] ,Instruction speculatively executed" "Not implemented,Implemented"
|
|
bitfld.long 0x00 26. " [26] ,Local memory error" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 25. " [25] ,Bus access" "Not implemented,Implemented"
|
|
bitfld.long 0x00 24. " [24] ,Level 2 data cache write-back" "Not implemented,Implemented"
|
|
bitfld.long 0x00 23. " [23] ,Level 2 data cache refill" "Not implemented,Implemented"
|
|
bitfld.long 0x00 22. " [22] ,Level 2 data cache access" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [21] ,Level 1 instruction cache access" "Not implemented,Implemented"
|
|
bitfld.long 0x00 20. " [20] ,Level 1 instruction cache access" "Not implemented,Implemented"
|
|
bitfld.long 0x00 19. " [19] ,Data memory access" "Not implemented,Implemented"
|
|
bitfld.long 0x00 15. " [15] ,Instruction architecturally executed, condition code check pass, unaligned load or store" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 14. " [14] ,Instruction architecturally executed, condition code check pass, procedure return" "Not implemented,Implemented"
|
|
bitfld.long 0x00 13. " [13] ,Instruction architecturally executed, immediate branch" "Not implemented,Implemented"
|
|
bitfld.long 0x00 12. " [12] ,Instruction architecturally executed, condition code check pass, software change of the PC" "Not implemented,Implemented"
|
|
bitfld.long 0x00 11. " [11] ,Instruction architecturally executed, condition code check pass, write to CONTEXTIDR" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 10. " [10] ,Instruction architecturally executed, condition code check pass, exception return" "Not implemented,Implemented"
|
|
bitfld.long 0x00 9. " [9] ,Exception taken" "Not implemented,Implemented"
|
|
bitfld.long 0x00 8. " [8] ,Instruction architecturally executed" "Not implemented,Implemented"
|
|
bitfld.long 0x00 7. " [7] ,Instruction architecturally executed, condition code check pass, store" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 6. " [6] ,Instruction architecturally executed, condition code check pass, load" "Not implemented,Implemented"
|
|
bitfld.long 0x00 5. " [5] ,Level 1 data TLB refill" "Not implemented,Implemented"
|
|
bitfld.long 0x00 2. " [2] ,Level 1 instruction TLB refill" "Not implemented,Implemented"
|
|
bitfld.long 0x00 1. " [1] ,Level 1 instruction cache refill" "Not implemented,Implemented"
|
|
elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
rgroup.long c15:0x6C9++0x0
|
|
line.long 0x00 "PMCEID0,Common Event Identification Register 0"
|
|
bitfld.long 0x00 31. " PMCEID0[31] ,Level 1 instruction cache access" "Not implemented,Implemented"
|
|
bitfld.long 0x00 30. " [30] ,Level 1 data memory access" "Not implemented,Implemented"
|
|
bitfld.long 0x00 29. " [29] ,Level 1 data memory access" "Not implemented,Implemented"
|
|
bitfld.long 0x00 28. " [28] ,Level 1 data memory access" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Branches or other change in program flow that could have been predicted by the branch prediction resources of the processor" "Not implemented,Implemented"
|
|
bitfld.long 0x00 26. " [26] ,Branch mispredicted or not predicted" "Not implemented,Implemented"
|
|
bitfld.long 0x00 25. " [25] ,Unaligned access" "Not implemented,Implemented"
|
|
bitfld.long 0x00 24. " [24] ,Unaligned access" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Branch speculatively executed - Procedure return" "Not implemented,Implemented"
|
|
bitfld.long 0x00 22. " [22] ,Branch speculatively executed - Immediate branch" "Not implemented,Implemented"
|
|
bitfld.long 0x00 21. " [21] ,Instruction speculatively executed - Software change of the PC" "Not implemented,Implemented"
|
|
bitfld.long 0x00 20. " [20] ,Write to translation table register (TTBR0 or TTBR1)" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Change to ContextID retired" "Not implemented,Implemented"
|
|
bitfld.long 0x00 18. " [18] ,Exception return architecturally executed" "Not implemented,Implemented"
|
|
bitfld.long 0x00 17. " [17] ,Exception taken. Counts the number of exceptions architecturally taken" "Not implemented,Implemented"
|
|
bitfld.long 0x00 16. " [16] ,Instruction architecturally executed" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Instruction architecturally executed" "Not implemented,Implemented"
|
|
bitfld.long 0x00 14. " [14] ,Instruction architecturally executed" "Not implemented,Implemented"
|
|
bitfld.long 0x00 13. " [13] ,Instruction architecturally executed" "Not implemented,Implemented"
|
|
bitfld.long 0x00 12. " [12] ,Instruction architecturally executed" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Instruction architecturally executed" "Not implemented,Implemented"
|
|
bitfld.long 0x00 10. " [10] ,Instruction architecturally executed" "Not implemented,Implemented"
|
|
bitfld.long 0x00 9. " [9] ,Store instruction speculatively executed" "Not implemented,Implemented"
|
|
bitfld.long 0x00 8. " [8] ,Store instruction speculatively executed" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Load instruction speculatively executed" "Not implemented,Implemented"
|
|
bitfld.long 0x00 6. " [6] ,Load instruction speculatively executed" "Not implemented,Implemented"
|
|
bitfld.long 0x00 5. " [5] ,Data read or write operation that causes a TLB refill at (at least) the lowest level of TLB" "Not implemented,Implemented"
|
|
bitfld.long 0x00 4. " [4] ,Data read or write operation that causes a cache access at (at least) the lowest level of data or unified cache" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Data read or write operation that causes a cache access at (at least) the lowest level of data or unified cache" "Not implemented,Implemented"
|
|
bitfld.long 0x00 2. " [2] ,Data read or write operation that causes a refill at (at least) the lowest level of data or unified cache" "Not implemented,Implemented"
|
|
bitfld.long 0x00 1. " [1] ,Instruction fetch that causes a TLB refill at (at least) the lowest level of TLB" "Not implemented,Implemented"
|
|
bitfld.long 0x00 0. " [0] ,Instruction fetch that causes a refill at (at least) the lowest level of instruction or unified cache" "Not implemented,Implemented"
|
|
elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
rgroup.long c15:0x6C9++0x0
|
|
line.long 0x00 "PMCEID0,Common Event Identification Register 0"
|
|
bitfld.long 0x00 29. " PMCEID0[29] ,Bus cycle" "Not implemented,Implemented"
|
|
bitfld.long 0x00 28. " [28] ,Instruction architecturally executed. Condition code check pass, write to TTBR" "Not implemented,Implemented"
|
|
bitfld.long 0x00 27. " [27] ,Instruction speculatively executed" "Not implemented,Implemented"
|
|
bitfld.long 0x00 26. " [26] ,Local memory error" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 25. " [25] ,Bus access" "Not implemented,Implemented"
|
|
bitfld.long 0x00 24. " [24] ,Level 2 data cache write-back" "Not implemented,Implemented"
|
|
bitfld.long 0x00 23. " [23] ,Level 2 data cache refill" "Not implemented,Implemented"
|
|
bitfld.long 0x00 22. " [22] ,Level 2 data cache access" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [21] ,Level 1 instruction cache access" "Not implemented,Implemented"
|
|
bitfld.long 0x00 20. " [20] ,Level 1 instruction cache access" "Not implemented,Implemented"
|
|
bitfld.long 0x00 19. " [19] ,Data memory access" "Not implemented,Implemented"
|
|
bitfld.long 0x00 14. " [14] ,Instruction architecturally executed, condition code check pass, procedure return" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Instruction architecturally executed, condition code check pass, write to CONTEXTIDR" "Not implemented,Implemented"
|
|
bitfld.long 0x00 10. " [10] ,Instruction architecturally executed, condition code check pass, exception return" "Not implemented,Implemented"
|
|
bitfld.long 0x00 9. " [9] ,Exception taken" "Not implemented,Implemented"
|
|
bitfld.long 0x00 5. " [5] ,Level 1 data TLB refill" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 2. " [2] ,Level 1 instruction TLB refill" "Not implemented,Implemented"
|
|
bitfld.long 0x00 1. " [1] ,Level 1 instruction cache refill" "Not implemented,Implemented"
|
|
endif
|
|
tree.end
|
|
width 12.
|
|
tree "System Control and Configuration"
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c15:0x1++0x0
|
|
line.long 0x0 "SCTLR,Control Register"
|
|
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
|
|
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 25. " EE ,Exception endianness" "Little,Big"
|
|
textline " "
|
|
bitfld.long 0x0 20. " UWXN ,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
|
|
bitfld.long 0x0 19. " WXN ,Write permission implies PL1 Execute Never" "Not forced,Forced"
|
|
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
|
|
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 10. " SW ,SWP/SWPB Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " A ,Strict Alignment" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disabled,Enabled"
|
|
elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
group.long c15:0x1++0x0
|
|
line.long 0x0 "SCTLR,System Control Register"
|
|
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
|
|
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " EE ,Exception endianness" "Little,Big"
|
|
bitfld.long 0x0 20. " UWXN ,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
|
|
bitfld.long 0x0 19. " WXN ,Write permission implies PL1 Execute Never" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
|
|
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " A ,Alignment Fault Check enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " M ,Address translation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
group.long c15:0x0101++0x0
|
|
line.long 0x0 "ACTLR,Auxiliary Control Register"
|
|
bitfld.long 0x00 6. " SMP ,Enables coherent requests to the processor" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ASSE ,ACE STREX Signalling Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " L2PF ,Enable L2 prefetch" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " L1PF ,Enable L1 prefetch" "Disabled,Enabled"
|
|
elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c15:0x101++0x0
|
|
line.long 0x0 "ACTLR,Auxiliary Control Register"
|
|
bitfld.long 0x00 31. " SDEH ,Snoop-delayed exclusive handling" "Normal,Modified"
|
|
bitfld.long 0x00 30. " FMCEA ,Force main clock processor enable active" "Not prevented,Prevented"
|
|
bitfld.long 0x00 29. " FNVCEA ,Force NEON/VFP clock enable active" "Not prevented,Prevented"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " WSNAT ,Write streaming no-allocate threshold" "12th,128th,512th,Disabled"
|
|
bitfld.long 0x00 25.--26. " WSNL1AT ,Write streaming no L1-allocate threshold" "14th,64th,128th,Disabled"
|
|
bitfld.long 0x00 24. " NCSE ,Non-cacheable streaming enhancement" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FIORRTTSSAW ,Forces in-order requests to the same set and way" "Not forced,Forced"
|
|
bitfld.long 0x00 22. " FIOLI ,Force in-order load issue" "Not forced,Forced"
|
|
bitfld.long 0x00 21. " DL2TLBP ,Disabled L2 TLB prefetching" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " DL2TBWIPAPAC ,Disable L2 TBW IPA PA cache" "No,Yes"
|
|
bitfld.long 0x00 19. " DL2TBWS1WC ,Disable L2 TBW Stage 1 walk cache" "No,Yes"
|
|
bitfld.long 0x00 18. " DL2TBWS1L2PAC ,Disable L2 TBW stage 1 L2 PA cache" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DL2TLBPO ,Disable L2 TLB Performance Optimization" "No,Yes"
|
|
bitfld.long 0x00 16. " EFSOADLR ,Enables full Strongly-ordered and Device load replay" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " FIIBEU ,Force in-order issue in branch execution unit" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FLOIGCDPC ,Force limit of one instruction group commit/de-allocate per cycle" "Not forced,Limited"
|
|
bitfld.long 0x00 13. " FACP14WCP15 ,Flush after CP14 and CP15 writes" "Normal,Flushed"
|
|
bitfld.long 0x00 12. " FPCP14CP15 ,Force push of CP14 and CP15 registers" "Not forced,Pushed"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FOISEG ,Force one instruction to start and end a group" "Not forced,Forced"
|
|
bitfld.long 0x00 10. " FSAEIG ,Force serialization after each instruction group" "Not forced,Forced"
|
|
bitfld.long 0x00 9. " DFRO ,Disable flag renaming optimization" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 8. " EWFIIANOPI ,Executes WFI instructions as NOP instructions" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " EWFEIANOPI ,Executes WFE instructions as NOP instructions" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SMP ,Broadcast of cache and TLB maintenance operations enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EPLDIANOP ,Execute PLD and PLDW instructions as a NOP instruction" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIP ,Disable indirect predictor" "No,Yes"
|
|
bitfld.long 0x00 3. " DMBTB ,Disable micro-BTB" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LOLBDPF ,Limits to one loop buffer detect per flush" "Normal,Limited"
|
|
bitfld.long 0x00 1. " DLB ,Disable loop buffer" "No,Yes"
|
|
bitfld.long 0x00 0. " EIBTB ,Enable invalidate of BTB" "Disabled,Enabled"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c15:0x101++0x0
|
|
line.long 0x0 "ACTLR,Auxiliary Control Register"
|
|
bitfld.long 0x00 28. " DBDI ,Disable branch dual issue" "No,Yes"
|
|
bitfld.long 0x00 15. " DDVM ,Disable Distributed Virtual Memory (DVM) transactions" "No,Yes"
|
|
bitfld.long 0x00 13.--14. " L1PCTL ,L1 Data prefetch control" "Disabled,1 pre-fetch,2 pre-fetches,3 pre-fetches"
|
|
textline " "
|
|
bitfld.long 0x00 12. " L1RADIS ,L1 Data Cache read-allocate mode disable" "No,Yes"
|
|
bitfld.long 0x00 11. " L2RADIS ,L2 Data Cache read-allocate mode disable" "No,Yes"
|
|
bitfld.long 0x00 10. " DODMBS ,Disable optimised data memory barrier behaviour" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SMP ,Enables coherent requests to the processor" "Disabled,Enabled"
|
|
endif
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c15:0x140F++0x00
|
|
line.long 0x0 "ACTLR2,Auxiliary Control Register 2"
|
|
bitfld.long 0x00 31. " ECRCG ,Enable CPU regional clock gates" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EDCCADCCI ,Execute data cache clean as data cache clean/invalidate" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
hgroup.long c15:0x140F++0x00
|
|
hide.long 0x0 "ACTLR2,Auxiliary Control Register 2"
|
|
endif
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
rgroup.long c15:0x201++0x00
|
|
line.long 0x0 "CPACR,Coprocessor Access Control Register"
|
|
bitfld.long 0x0 31. " ASEDIS ,Disable Advanced SIMD Extension functionality" "No,Yes"
|
|
bitfld.long 0x0 22.--23. " CP11 ,Coprocessor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 20.--21. " CP10 ,Coprocessor access control" "Denied,Privileged,Reserved,Full"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
rgroup.long c15:0x201++0x00
|
|
line.long 0x0 "CPACR,Coprocessor Access Control Register"
|
|
bitfld.long 0x0 31. " ASEDIS ,Disable Advanced SIMD Extension functionality" "No,Yes"
|
|
bitfld.long 0x0 30. " D32DIS ,Disable use of registers D16-D31 of the VFP register file" "No,Yes"
|
|
bitfld.long 0x0 22.--23. " CP11 ,Coprocessor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 20.--21. " CP10 ,Coprocessor access control" "Denied,Privileged,Reserved,Full"
|
|
endif
|
|
group.long c15:0x11++0x0
|
|
line.long 0x0 "SCR,Secure Configuration Register"
|
|
bitfld.long 0x00 9. " SIF ,Secure Instruction Fetch" "Permitted,Not permitted"
|
|
bitfld.long 0x00 8. " HCE ,Hyp Call enable" "Undefined,Enabled"
|
|
bitfld.long 0x00 7. " SCD ,Secure Monitor Call disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 5. " AW ,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed"
|
|
bitfld.long 0x00 4. " FW ,Controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed"
|
|
bitfld.long 0x00 3. " EA ,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FIQ ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor"
|
|
bitfld.long 0x00 1. " IRQ ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor"
|
|
bitfld.long 0x00 0. " NS ,Secure mode " "Secure,Non-secure"
|
|
group.long c15:0x0111++0x00
|
|
line.long 0x00 "SDER,Secure Debug Enable Register"
|
|
bitfld.long 0x00 1. " SUNIDEN ,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted"
|
|
bitfld.long 0x00 0. " SUIDEN ,Invasive Secure User Debug Enable bit" "Denied,Permitted"
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c15:0x0211++0x00
|
|
line.long 0x00 "NSACR,Non-Secure Access Control Register"
|
|
bitfld.long 0x00 18. " NS_SMP ,Determines if the SMP bit of the Auxiliary Control Register is writeable in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " NS_L2ERR ,L2 internal asynchronous error and AXI asynchronous error writeable in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " NSASEDIS ,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CP11 ,Coprocessor 11 in the Non-secure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 10. " CP10 ,Coprocessor 10 in the Non-secure World Access Permission" "Denied,Permitted"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c15:0x0211++0x00
|
|
line.long 0x00 "NSACR,Non-Secure Access Control Register"
|
|
bitfld.long 0x00 18. " NS_SMP ,Determines if the SMP bit of the Auxiliary Control Register is writeable in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " NSASEDIS ,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes"
|
|
bitfld.long 0x00 14. " NSD32DIS ,Disable the Non-secure use of D16-D31 of the VFP register file" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CP11 ,Coprocessor 11 in the Non-secure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 10. " CP10 ,Coprocessor 10 in the Non-secure World Access Permission" "Denied,Permitted"
|
|
elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
group.long c15:0x0211++0x00
|
|
line.long 0x00 "NSACR,Non-Secure Access Control Register"
|
|
bitfld.long 0x00 18. " NS_SMP ,Determines if the SMP bit of the Auxiliary Control Register is writeable in Non-secure state" "Non-writeable,Writeable"
|
|
bitfld.long 0x00 17. " NS_L2ERR ,Determines if the L2 Extended Control Register(L2ECTLR), is writeable in Non-secure state" "Non-writeable,Writeable"
|
|
bitfld.long 0x00 16. " NS_ACTLR_PF_WRITE ,Determines if the ACTLR.L1PF and ACTLR.L2PF registers are writeable in Non-secure state" "Non-writeable,Writeable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NSASEDIS ,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes"
|
|
bitfld.long 0x00 14. " NSD32DIS ,Disable the Non-secure use of D16-D31 of the VFP register file" "No,Yes"
|
|
bitfld.long 0x00 11. " CP11 ,Coprocessor 11 in the Non-secure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CP10 ,Coprocessor 10 in the Non-secure World Access Permission" "Denied,Permitted"
|
|
endif
|
|
group.long c15:0x000C++0x00
|
|
line.long 0x00 "VBAR,Vector Base Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " VBADDR ,Vector Base Address"
|
|
group.long c15:0x010C++0x00
|
|
line.long 0x00 "MVBAR,Monitor Vector Base Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " MVBADDR ,Monitor Vector Base Address"
|
|
textline " "
|
|
rgroup.long c15:0x001C++0x00
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 8. " A ,External abort pending flag" "Not pending,Pending"
|
|
bitfld.long 0x00 7. " I ,Interrupt pending flag" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " F ,Fast interrupt pending flag" "Not pending,Pending"
|
|
textline " "
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
rgroup.long c15:0x400F++0x00
|
|
line.long 0x00 "CBAR,Configuration Base Address Register"
|
|
hexmask.long.tbyte 0x00 15.--31. 1. " PERIPHBASE[31:15] ,Periphbase[31:15]"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PERIPHBASE[39:32] ,Periphbase[39:32]"
|
|
else
|
|
hgroup.long c15:0x400F++0x00
|
|
hide.long 0x00 "CBAR,Configuration Base Address Register"
|
|
endif
|
|
if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
if (((d.l(c15:0x1609))&0x3)==0x3)
|
|
group.long c15:0x1609++0x00
|
|
line.long 0x00 "SCUCTLR,SCU Control Register"
|
|
bitfld.long 0x00 30. " PRM3 ,Disable processor 3 retention" "No,Yes"
|
|
bitfld.long 0x00 28.--29. " PPS3 ,Processor 3 power status" "Normal,Not present,Retention,Powerdown"
|
|
bitfld.long 0x00 26. " PRM2 ,Disable processor 2 retention" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " PPS2 ,Processor 2 power status" "Normal,Not present,Retention,Powerdown"
|
|
bitfld.long 0x00 22. " PRM1 ,Disable processor 1 retention" "No,Yes"
|
|
bitfld.long 0x00 20.--21. " PPS1 ,Processor 1 power status" "Normal,Not present,Retention,Powerdown"
|
|
textline " "
|
|
bitfld.long 0x00 18. " PRM0 ,Disable processor 0 retention" "No,Yes"
|
|
bitfld.long 0x00 16.--17. " PPS0 ,Processor 0 power status" "Normal,Not present,Retention,Powerdown"
|
|
bitfld.long 0x00 7. " CPSMP[3] ,Copy of the ACTLR.SMP for processor 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPSMP[2] ,Copy of the ACTLR.SMP for processor 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CPSMP[1] ,Copy of the ACTLR.SMP for processor 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CPSMP[0] ,Copy of the ACTLR.SMP for processor 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NP ,Number of processors" "1,2,3,4"
|
|
textline " "
|
|
elif (((d.l(c15:0x1609))&0x3)==0x2)
|
|
group.long c15:0x1609++0x00
|
|
line.long 0x00 "SCUCTLR,SCU Control Register"
|
|
bitfld.long 0x00 26. " PRM2 ,Disable processor 2 retention" "No,Yes"
|
|
bitfld.long 0x00 24.--25. " PPS2 ,Processor 2 power status" "Normal,Not present,Retention,Powerdown"
|
|
bitfld.long 0x00 22. " PRM1 ,Disable processor 1 retention" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " PPS1 ,Processor 1 power status" "Normal,Not present,Retention,Powerdown"
|
|
bitfld.long 0x00 18. " PRM0 ,Disable processor 0 retention" "No,Yes"
|
|
bitfld.long 0x00 16.--17. " PPS0 ,Processor 0 power status" "Normal,Not present,Retention,Powerdown"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPSMP[2] ,Copy of the ACTLR.SMP for processor 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CPSMP[1] ,Copy of the ACTLR.SMP for processor 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CPSMP[0] ,Copy of the ACTLR.SMP for processor 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NP ,Number of processors" "1,2,3,4"
|
|
textline " "
|
|
elif (((d.l(c15:0x1609))&0x3)==0x1)
|
|
group.long c15:0x1609++0x00
|
|
line.long 0x00 "SCUCTLR,SCU Control Register"
|
|
bitfld.long 0x00 22. " PRM1 ,Disable processor 1 retention" "No,Yes"
|
|
bitfld.long 0x00 20.--21. " PPS1 ,Processor 1 power status" "Normal,Not present,Retention,Powerdown"
|
|
bitfld.long 0x00 18. " PRM0 ,Disable processor 0 retention" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PPS0 ,Processor 0 power status" "Normal,Not present,Retention,Powerdown"
|
|
bitfld.long 0x00 5. " CPSMP[1] ,Copy of the ACTLR.SMP for processor 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CPSMP[0] ,Copy of the ACTLR.SMP for processor 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NP ,Number of processors" "1,2,3,4"
|
|
textline " "
|
|
elif (((d.l(c15:0x1609))&0x3)==0x0)
|
|
group.long c15:0x1609++0x00
|
|
line.long 0x00 "SCUCTLR,SCU Control Register"
|
|
bitfld.long 0x00 18. " PRM0 ,Disable processor 0 retention" "No,Yes"
|
|
bitfld.long 0x00 16.--17. " PPS0 ,Processor 0 power status" "Normal,Not present,Retention,Powerdown"
|
|
bitfld.long 0x00 4. " CPSMP[0] ,Copy of the ACTLR.SMP for processor 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NP ,Number of processors" "1,2,3,4"
|
|
textline " "
|
|
endif
|
|
group.long c15:0x410F++0x00
|
|
line.long 0x00 "FILASTARTR,Peripheral port start address register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " FLT_START_ADDR ,Start address of the peripheral port physical memory region"
|
|
bitfld.long 0x00 0. " FILT_EN ,FLT_START_ADDR and FLT_END_ADDR are valid" "Invalid,Valid"
|
|
group.long c15:0x420F++0x00
|
|
line.long 0x00 "FILAENDR,Peripheral port end address register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " FLT_END_ADDR ,End address of the peripheral port physical memory region"
|
|
elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
hgroup.long c15:0x1609++0x00
|
|
hide.long 0x00 "SCUCTLR,SCU Control Register"
|
|
hgroup.long c15:0x410F++0x00
|
|
hide.long 0x00 "FILASTARTR,Peripheral port start address register"
|
|
hgroup.long c15:0x420F++0x00
|
|
hide.long 0x00 "FILAENDR,Peripheral port end address register"
|
|
endif
|
|
tree.end
|
|
width 12.
|
|
tree "Memory Management Unit"
|
|
if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
group.long c15:0x0001++0x0
|
|
line.long 0x0 "SCTLR,System Control Register"
|
|
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
|
|
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " EE ,Exception endianness" "Little,Big"
|
|
bitfld.long 0x0 20. " UWXN ,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
|
|
bitfld.long 0x0 19. " WXN ,Write permission implies PL1 Execute Never" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
|
|
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " A ,Alignment Fault Check enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " M ,Address translation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c15:0x1++0x0
|
|
line.long 0x0 "SCTLR,Control Register"
|
|
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
|
|
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " EE ,Exception endianness" "Little,Big"
|
|
bitfld.long 0x0 20. " UWXN ,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
|
|
bitfld.long 0x0 19. " WXN ,Write permission implies PL1 Execute Never" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
|
|
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " SW ,SWP/SWPB Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " A ,Strict Alignment" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
if (((d.l(c15:0x0002))&0x2)==0x2)&&(((d.l(c15:0x0202))&0x80000000)==0x00000000)
|
|
group.long c15:0x0002++0x00
|
|
line.long 0x00 "TTBR0,Translation Table Base Register 0"
|
|
hexmask.long.tbyte 0x00 14.--31. 0x40 " TTB0_ADDR ,Translation table base 0 address"
|
|
bitfld.long 0x00 5. " NOS ,Not Outer Shareable bit" "Outer,Inner"
|
|
bitfld.long 0x00 3.--4. " RGN ,Region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IMP ,Implementation defined" "Low,High"
|
|
bitfld.long 0x00 1. " S ,Shareable bit" "Non-shareable,Shareable"
|
|
bitfld.long 0x00 0. 6. " IRGN ,Inner region bits for Multiprocessing Extensions" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
elif (((d.l(c15:0x0002))&0x2)==0x0)&&(((d.l(c15:0x0202))&0x80000000)==0x00000000)
|
|
group.long c15:0x0002++0x00
|
|
line.long 0x00 "TTBR0,Translation Table Base Register 0"
|
|
hexmask.long.tbyte 0x00 14.--31. 0x40 " TTB0_ADDR ,Translation table base 0 address"
|
|
bitfld.long 0x00 3.--4. " RGN ,Region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
bitfld.long 0x00 2. " IMP ,Implementation defined" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " S ,Shareable bit" "Non-shareable,Shareable"
|
|
bitfld.long 0x00 0. 6. " IRGN ,Inner region bits for Multiprocessing Extensions" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
elif (((d.l(c15:0x0202))&0x80000000)==0x80000000)
|
|
group.quad c15:0x10020++0x01
|
|
line.quad 0x00 "TTBR0,Translation Table Base Register 0"
|
|
hexmask.quad.byte 0x00 48.--55. 1. " ASID ,ASID for the translation table base address"
|
|
hexmask.quad 0x00 0.--39. 1. " BADDR ,Translation table base address"
|
|
endif
|
|
if (((d.l(c15:0x0102))&0x2)==0x2)&&(((d.l(c15:0x0202))&0x80000000)==0x00000000)
|
|
group.long c15:0x0102++0x00
|
|
line.long 0x00 "TTBR1,Translation Table Base Register 1"
|
|
hexmask.long.tbyte 0x00 14.--31. 0x40 " TTB1_ADDR ,Translation table base 1 address"
|
|
bitfld.long 0x00 5. " NOS ,Not Outer Shareable bit" "Outer,Inner"
|
|
bitfld.long 0x00 3.--4. " RGN ,Region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IMP ,Implementation defined" "Low,High"
|
|
bitfld.long 0x00 1. " S ,Shareable bit" "Non-shareable,Shareable"
|
|
bitfld.long 0x00 0. 6. " IRGN ,Inner region bits for Multiprocessing Extensions" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
elif (((d.l(c15:0x0102))&0x2)==0x0)&&(((d.l(c15:0x0202))&0x80000000)==0x00000000)
|
|
group.long c15:0x0102++0x00
|
|
line.long 0x00 "TTBR1,Translation Table Base Register 1"
|
|
hexmask.long.tbyte 0x00 14.--31. 0x40 " TTB1_ADDR ,Translation table base 1 address"
|
|
bitfld.long 0x00 3.--4. " RGN ,Region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
bitfld.long 0x00 2. " IMP ,Implementation defined" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " S ,Shareable bit" "Non-shareable,Shareable"
|
|
bitfld.long 0x00 0. 6. " IRGN ,Inner region bits for Multiprocessing Extensions" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
elif (((d.l(c15:0x0202))&0x80000000)==0x80000000)
|
|
group.quad c15:0x11020++0x01
|
|
line.quad 0x00 "TTBR1,Translation Table Base Register 1"
|
|
hexmask.quad.byte 0x00 48.--55. 1. " ASID ,ASID for the translation table base address"
|
|
hexmask.quad 0x00 0.--39. 1. " BADDR ,Translation table base address"
|
|
endif
|
|
if (((d.l(c15:0x0202))&0x80000000)==0x00000000)
|
|
group.long c15:0x0202++0x00
|
|
line.long 0x00 "TTBCR,Translation Table Base Control Register"
|
|
bitfld.long 0x00 31. " EAE ,Extended Address Enable" "32-bit,40-bit"
|
|
bitfld.long 0x00 5. " PD1 ,Translation table walk Disable bit for TTBR1" "No,Yes"
|
|
bitfld.long 0x00 4. " PD0 ,Translation table walk Disable bit for TTBR0" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " N ,Indicate the width of the base address held in TTBR0" "16KB,8KB,4KB,2KB,1KB,512 bytes,256 bytes,128 bytes"
|
|
else
|
|
group.long c15:0x0202++0x00
|
|
line.long 0x00 "TTBCR,Translation Table Base Control Register"
|
|
bitfld.long 0x00 31. " EAE ,Extended Address Enable" "32-bit,40-bit"
|
|
bitfld.long 0x00 30. " IMP ,IMPLEMENTATION DEFINED" "Low,High"
|
|
bitfld.long 0x00 28.--29. " SH1 ,Shareability attributes for the memory associated with the translation table walks using TTBR1" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " ORGN1 ,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
bitfld.long 0x00 24.--25. " IRGN1 ,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
bitfld.long 0x00 23. " EPD1 ,Translation table walk disable for translations using TTBR1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 22. " A1 ,Selects whether TTBR0 or TTBR1 defines the ASID" "TTBR0,TTBR1"
|
|
bitfld.long 0x00 16.--18. " T1SZ ,The Size offset of the TTBR1 addressed region" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--13. " SH0 ,Shareability attributes for the memory associated with the translation table walks using TTBR0" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " ORGN0 ,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
bitfld.long 0x00 8.--9. " IRGN0 ,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
bitfld.long 0x00 7. " EPD0 ,Translation table walk disable for translations using TTBR0" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " T0SZ ,The Size offset of the TTBR0 addressed memory region" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
group.long c15:0x0003++0x00
|
|
line.long 0x00 "DACR,Domain Access Control Register"
|
|
bitfld.long 0x0 30.--31. " D15 ,Domain Access 15" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 22.--23. " D11 ,Domain Access 11" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 14.--15. " D7 ,Domain Access 7" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 6.--7. " D3 ,Domain Access 3" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
if (((d.l(c15:0x0202))&0x80000000)==0x80000000)
|
|
group.long c15:0x0005++0x00
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " STATUS ,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/First level,Translation fault/Second level,Translation fault/Third level,Reserved,Access flag fault/First level,Access flag fault/Second level,Access flag fault/Third level,Reserved,Permission fault/First level,Permission fault/Second level,Permission fault/Third level,Synchronous external abort,Asynchronous external abort,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/First level,Synchronous external abort on translation table walk/Second level,Synchronous external abort on translation table walk/Third level,Synchronous parity error on memory access,Asynchronous parity error on memory access,Reserved,Reserved,Reserved,Synchronous parity error on memory access on translation table walk/First level,Synchronous parity error on memory access on translation table walk/Second level,Synchronous parity error on memory access on translation table walk/Third level,Reserved,Alignment fault,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Lockdown Abort,Reserved,Reserved,Reserved,Reserved,Reserved,Coprocessor Abort,?..."
|
|
else
|
|
group.long c15:0x0005++0x00
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
|
|
bitfld.long 0x00 0.--3. 10. " FS ,Fault Status" "Reserved,Alignment fault,Reserved,Reserved,Instruction cache maintenance fault,Translation fault/First level,Access flag fault/Second level,Translation fault/Second level,Synchronous external abort,Domain fault/First level,Reserved,Domain fault/Second level,Synchronous external abort/First level,Permission fault/First level,Synchronous external abort/Second level,Permission fault/Second level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external abort,Reserved,Asynchronous parity error on memory access,Synchronous parity error on memory access,Reserved,Reserved,Synchronous parity error on translation table walk/First level,Reserved,Synchronous parity error on translation table walk/Second level,Reserved"
|
|
endif
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
if (((d.l(c15:0x0202))&0x80000000)==0x80000000)
|
|
group.long c15:0x0005++0x00
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " STATUS ,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/First level,Translation fault/Second level,Translation fault/Third level,Reserved,Access flag fault/First level,Access flag fault/Second level,Access flag fault/Third level,Reserved,Permission fault/First level,Permission fault/Second level,Permission fault/Third level,Synchronous external abort,Asynchronous external abort,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/First level,Synchronous external abort on translation table walk/Second level,Synchronous external abort on translation table walk/Third level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug event,?..."
|
|
else
|
|
group.long c15:0x0005++0x00
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
|
|
bitfld.long 0x00 0.--3. 10. " FS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Non-translation/synchronous external,Domain/section,Reserved,Domain/page,L1/synchronous external,Permission/section,L2/synchronous external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
|
|
endif
|
|
elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
if (((d.l(c15:0x0202))&0x80000000)==0x00000000)
|
|
group.long c15:0x0005++0x00
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
|
|
bitfld.long 0x00 0.--3. 10. " FS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Reserved,Translation/section,Access/page,Translation/page,Reserved,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,TLB,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
|
|
else
|
|
group.long c15:0x0005++0x00
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " STATUS ,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/1st level,Translation fault/2nd level,Translation fault/3rd level,Reserved,Access flag fault/1st level,Access flag fault/2nd level,Access flag fault/3rd level,Reserved,Permission fault/1st level,Permission fault/2nd level,Permission fault/3rd level,Reserved,Asynchronous external abort,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/1st level,Synchronous external abort on translation table walk/2nd level,Synchronous external abort on translation table walk/3rd level,TLB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug event,?..."
|
|
endif
|
|
endif
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c15:0x0015++0x00
|
|
line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register"
|
|
bitfld.long 0x00 31. " VALID ,L1 or L2 ECC double bit error indicator" "No error,Error"
|
|
hexmask.long.byte 0x00 24.--30. 1. " RAMID ,RAM identifier"
|
|
bitfld.long 0x00 23. " L2E ,L2 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 18.--22. " B/W ,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " IND ,Index"
|
|
else
|
|
hgroup.long c15:0x0015++0x00
|
|
hide.long 0x00 "ADFSR,Auxiliary Data Fault Status Register"
|
|
endif
|
|
group.long c15:0x0006++0x00
|
|
line.long 0x00 "DFAR,Data Fault Address Register"
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
if (((d.l(c15:0x0202))&0x80000000)==0x80000000)
|
|
group.long c15:0x0105++0x00
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " STATUS ,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/First level,Translation fault/Second level,Translation fault/Third level,Reserved,Access flag fault/First level,Access flag fault/Second level,Access flag fault/Third level,Reserved,Permission fault/First level,Permission fault/Second level,Permission fault/Third level,Synchronous external abort,Reserved,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/First level,Synchronous external abort on translation table walk/Second level,Synchronous external abort on translation table walk/Third level,Synchronous parity error on memory access,Reserved,Reserved,Reserved,Reserved,Synchronous parity error on memory access on translation table walk/First level,Synchronous parity error on memory access on translation table walk/Second level,Synchronous parity error on memory access on translation table walk/Third level,?..."
|
|
else
|
|
group.long c15:0x0105++0x00
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. 10. " FS ,Generated Exception Type" "Reserved,Reserved,Debug event,Access flag fault/First level,Reserved,Translation fault/First level,Access flag fault/Second level,Translation fault/Second level,Non-translation/synchronous external abort,Domain fault/First level,Reserved,Domain fault/Second level,Synchronous external abort on translation table walk/First level,Permission fault/First level,Synchronous external abort on translation table walk/Second level,Permission fault/Second level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Synchronous parity error on memory access,Reserved,Reserved,Synchronous parity error on translation table walk,Reserved,Synchronous parity error on translation table walk,Reserved"
|
|
endif
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
if (((d.l(c15:0x0202))&0x80000000)==0x80000000)
|
|
group.long c15:0x0105++0x00
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " STATUS ,Generated Exception Type" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/First level,Translation fault/Second level,Translation fault/Third level,Reserved,Access fault flag/First level,Access fault flag/Second level,Access fault flag/Third level,Reserved,Permission fault/First level,Permission fault/Second level,Permission fault/Third level,Synchronous external abort,Reserved,Debug event,?..."
|
|
else
|
|
group.long c15:0x0105++0x00
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. 10. " FS ,Generated Exception Type" "Reserved,Reserved,Debug,Access/section,Reserved,Translation/section,Access/page,Translation/page,Non-translation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,?..."
|
|
endif
|
|
elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
if (((d.l(c15:0x202))&0x80000000)==0x80000000)
|
|
group.long c15:0x0105++0x00
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR"
|
|
bitfld.long 0x00 9. " LPAE ,Large physical address extension" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " STATUS ,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/1st level,Translation fault/2nd level,Translation fault/3rd level,Reserved,Access flag fault/1st level,Access flag fault/2nd level,Access flag fault/3rd level,Reserved,Permission fault/1st level,Permission fault/2nd level,Permission fault/3rd level,Reserved,Asynchronous external abort,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/1st level,Synchronous external abort on translation table walk/2nd level,Synchronous external abort on translation table walk/3rd level,TLB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug event,?..."
|
|
else
|
|
group.long c15:0x0105++0x00
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR"
|
|
bitfld.long 0x00 9. " LPAE ,Large physical address extension" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. 10. " FS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Reserved,Translation/section,Access/page,Translation/page,Reserved,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,TLB,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
|
|
endif
|
|
endif
|
|
group.long c15:0x0206++0x00
|
|
line.long 0x00 "IFAR,Instruction Fault Address Register"
|
|
if (((d.l(c15:0x202))&0x80000000)==0x80000000&&((d.q(c15:0x0047))&0x1)==0x0)
|
|
group.quad c15:0x0047++0x01
|
|
line.quad 0x00 "PAR,Physical Address Register"
|
|
hexmask.quad.byte 0x00 56.--63. 1. " ATTR ,Memory attributes for the returned PA"
|
|
hexmask.quad 0x00 12.--39. 0x1000 " PA ,Physical Address"
|
|
bitfld.quad 0x00 11. " LPAE ,Long-descriptor translation table format use" "Not used,Used"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " NS ,Non-secure" "Secure,Non-secure"
|
|
bitfld.quad 0x00 7.--8. " SH ,Shareability attribute" "Non-shareable,Unpredictable,Outer Shareable,Inner Shareable"
|
|
bitfld.quad 0x00 0. " F ,Conversion completed successfully" "Successful,Unsuccessful"
|
|
textline " "
|
|
elif (((d.l(c15:0x202))&0x80000000)==0x80000000&&((d.q(c15:0x0047))&0x1)==0x1)
|
|
group.quad c15:0x0047++0x01
|
|
line.quad 0x00 "PAR,Physical Address Register"
|
|
bitfld.quad 0x00 11. " LPAE ,Long-descriptor translation table format use" "Not used,Used"
|
|
bitfld.quad 0x00 9. " FSTAGE ,Translation stage at which the translation aborted" "Stage 1,Stage 2"
|
|
bitfld.quad 0x00 8. " S2WLK ,Stage 2 fault during a stage 1 translation table walk" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.quad 0x00 1.--6. " FS ,Fault status field" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/1st level,Translation fault/2nd level,Translation fault/3rd level,Reserved,Access flag fault/1st level,Access flag fault/2nd level,Access flag fault/3rd level,Reserved,Permission fault/1st level,Permission fault/2nd level,Permission fault/3rd level,Synchronous external abort,Asynchronous external abort,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/1st level,Synchronous external abort on translation table walk/2nd level,Synchronous external abort on translation table walk/3rd level,Synchronous parity error on memory access, Asynchronous parity error on memory access,Reserved,Reserved,Reserved,Synchronous parity error on memory access on translation table walk/1st lvl,Synchronous parity error on memory access on translation table walk/2nd lvl,Synchronous parity error on memory access on translation table walk/3rd lvl,Reserved,Alignment fault,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Domain fault/1st lvl,Domain fault/2nd lvl,Reserved"
|
|
textline " "
|
|
bitfld.quad 0x00 0. " F ,Conversion completed successfully" "Successful,Unsuccessful"
|
|
textline " "
|
|
elif (((d.l(c15:0x202))&0x80000000)==0x00&&((d.q(c15:0x0047))&0x1)==0x0)
|
|
group.long c15:0x0047++0x00
|
|
line.long 0x00 "PAR,Physical Address Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x1000 " PA ,Physical Address"
|
|
bitfld.long 0x00 11. " LPAE ,Long-descriptor translation table format use" "Not used,Used"
|
|
bitfld.long 0x00 10. " NOS ,Not Outer Shareable attribute" "Outer shareable,Not outer shareable"
|
|
textline " "
|
|
bitfld.long 0x00 9. " NS ,Non-secure" "Secure,Non-secure"
|
|
bitfld.long 0x00 7. " SH ,Shareability attribute" "Non-shareable,Shareable"
|
|
bitfld.long 0x00 4.--6. " INNER ,Inner memory attributes" "Non-cacheable,Strongly-ordered,-,Device,-,Write-Back Write-Allocate,Write-Through,Write-Back no Write-Allocate"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " OUTER ,Outer memory attributes" "Non-cacheable,Write-Back Write-Allocate,Write-Through no Write-Allocate,Write-Back no Write-Allocate"
|
|
bitfld.long 0x00 1. " SS ,Supersection" "Not a Supersection,Supersection"
|
|
bitfld.long 0x00 0. " F ,Conversion completed successfully" "Successful,Unsuccessful"
|
|
textline " "
|
|
elif (((d.l(c15:0x202))&0x80000000)==0x00&&((d.q(c15:0x0047))&0x1)==0x1)
|
|
group.long c15:0x0047++0x00
|
|
line.long 0x00 "PAR,Physical Address Register"
|
|
bitfld.long 0x00 11. " LPAE ,Long-descriptor translation table format use" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 1.--6. " FS ,Fault status" "Reserved,Alignment fault,Debug event,Access flag fault/1st lvl,Fault on instruction cache maintenance,Translation fault/1st lvl,Access flag fault/2nd lvl,Translation fault/2nd lvl,Synchronous external abort,Domain fault/1st lvl,Reserved,Domain fault/2nd lvl,Synchronous external abort on translation table walk/1st lvl,Permission fault/1st lvl,Synchronous external abort on translation table walk/2nd lvl,Permission fault/2nd lvl,TLB conflict abort,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external abort,Reserved,Asynchronous parity error on memory access,Synchronous parity error on memory access,,,Synchronous parity error on translation table walk/1st lvl,Reserved,Synchronous parity error on translation table walk/2nd lvl,Reserved,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " F ,Conversion completed successfully" "Successful,Unsuccessful"
|
|
textline " "
|
|
endif
|
|
if (((d.l(c15:0x202))&0x80000000)==0x80000000)
|
|
group.long c15:0x002A++0x00
|
|
line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTR3 ,Attribute 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTR2 ,Attribute 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTR1 ,Attribute 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTR0 ,Attribute 0"
|
|
group.long c15:0x012A++0x00
|
|
line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTR7 ,Attribute 7"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTR6 ,Attribute 6"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTR5 ,Attribute 5"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTR4 ,Attribute 4"
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c15:0x003A++0x00
|
|
line.long 0x00 "AMAIR0,Auxiliary Memory Attribute Indirection Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTR3 ,Attribute 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTR2 ,Attribute 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTR1 ,Attribute 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTR0 ,Attribute 0"
|
|
group.long c15:0x013A++0x00
|
|
line.long 0x00 "AMAIR1,Auxiliary Memory Attribute Indirection Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTR7 ,Attribute 7"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTR6 ,Attribute 6"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTR5 ,Attribute 5"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTR4 ,Attribute 4"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
hgroup.long c15:0x003A++0x00
|
|
hide.long 0x00 "AMAIR0,Auxiliary Memory Attribute Indirection Register 0"
|
|
hgroup.long c15:0x013A++0x00
|
|
hide.long 0x00 "AMAIR1,Auxiliary Memory Attribute Indirection Register 1"
|
|
endif
|
|
else
|
|
group.long c15:0x002A++0x0
|
|
line.long 0x00 "PRRR,Primary Region Remap Register"
|
|
bitfld.long 0x00 31. " NOS7 ,Outer Shareable property mapping for memory attributes" "Outer,Inner"
|
|
bitfld.long 0x00 30. " NOS6 ,Outer Shareable property mapping for memory attributes" "Outer,Inner"
|
|
bitfld.long 0x00 29. " NOS5 ,Outer Shareable property mapping for memory attributes" "Outer,Inner"
|
|
textline " "
|
|
bitfld.long 0x00 28. " NOS4 ,Outer Shareable property mapping for memory attributes" "Outer,Inner"
|
|
bitfld.long 0x00 27. " NOS3 ,Outer Shareable property mapping for memory attributes" "Outer,Inner"
|
|
bitfld.long 0x00 26. " NOS2 ,Outer Shareable property mapping for memory attributes" "Outer,Inner"
|
|
textline " "
|
|
bitfld.long 0x00 25. " NOS1 ,Outer Shareable property mapping for memory attributes" "Outer,Inner"
|
|
bitfld.long 0x00 24. " NOS0 ,Outer Shareable property mapping for memory attributes" "Outer,Inner"
|
|
bitfld.long 0x00 19. " NS1 ,Shareable Attribute Remap when S=1 for Normal Regions" "Remapped,Not remapped"
|
|
textline " "
|
|
bitfld.long 0x00 18. " NS0 ,Shareable Attribute Remap when S=0 for Normal Regions" "Not remapped,Remapped"
|
|
bitfld.long 0x00 17. " DS1 ,Shareable Attribute Remap when S=1 for Device regions" "Remapped,Not remapped"
|
|
bitfld.long 0x00 16. " DS0 ,Shareable Attribute Remap when S=0 for Device regions" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " TR7 ,{TEX[0] C B} = b111 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 12.--13. " TR6 ,{TEX[0] C B} = b110 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 10.--11. " TR5 ,{TEX[0] C B} = b101 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TR4 ,{TEX[0] C B} = b100 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 6.--7. " TR3 ,{TEX[0] C B} = b011 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 4.--5. " TR2 ,{TEX[0] C B} = b010 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " TR1 ,{TEX[0] C B} = b001 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 0.--1. " TR0 ,{TEX[0] C B} = b000 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
group.long c15:0x012A++0x0
|
|
line.long 0x00 "NMRR,Normal Memory Remap Register"
|
|
bitfld.long 0x00 30.--31. " OR7 ,Outer Attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
bitfld.long 0x00 28.--29. " OR6 ,Outer Attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
bitfld.long 0x00 26.--27. " OR5 ,Outer Attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " OR4 ,Outer Attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
bitfld.long 0x00 22.--23. " OR3 ,Outer Attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
bitfld.long 0x00 20.--21. " OR2 ,Outer Attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " OR1 ,Outer Attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
bitfld.long 0x00 16.--17. " OR0 ,Outer Attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
bitfld.long 0x00 14.--15. " IR7 ,Inner attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " IR6 ,Inner attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
bitfld.long 0x00 10.--11. " IR5 ,Inner attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
bitfld.long 0x00 8.--9. " IR4 ,Inner attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " IR3 ,Inner attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
bitfld.long 0x00 4.--5. " IR2 ,Inner attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
bitfld.long 0x00 2.--3. " IR1 ,Inner attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " IR0 ,Inner attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
textline " "
|
|
endif
|
|
if (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c15:0x400F++0x00
|
|
line.long 0x00 "CBAR,Configuration Base Address Register"
|
|
hexmask.long.tbyte 0x00 15.--31. 0x80 " PERIPHBASE[31:15] ,Periphbase[31:15]"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PERIPHBASE[39:32] ,Periphbase[39:32]"
|
|
elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
hgroup.long c15:0x400F++0x00
|
|
hide.long 0x00 "CBAR,Configuration Base Address Register"
|
|
endif
|
|
textline " "
|
|
if (((d.l(c15:0x202))&0x80000000)==0x80000000)
|
|
group.long c15:0x10d++0x00
|
|
line.long 0x0 "CONTEXTIDR,Context ID Register"
|
|
else
|
|
group.long c15:0x10d++0x00
|
|
line.long 0x0 "CONTEXTIDR,Context ID Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " PROCID ,Process identifier"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ASID ,Address space identifier"
|
|
endif
|
|
group.long c15:0x020D++0x00
|
|
line.long 0x00 "TPIDRURW,User Read/Write Thread ID Register"
|
|
group.long c15:0x030D++0x00
|
|
line.long 0x00 "TPIDRURO,User Read-Only Thread ID Register"
|
|
group.long c15:0x040D++0x00
|
|
line.long 0x00 "TPIDRPRW,EL1 only Thread ID Register"
|
|
group.long c15:0x420D++0x00
|
|
line.long 0x00 "HTPIDR,Hyp Software Thread ID Register"
|
|
tree.end
|
|
width 15.
|
|
tree "Virtualization Extensions"
|
|
group.long c15:0x4000++0x00
|
|
line.long 0x0 "VPIDR,Virtualization Processor ID Register"
|
|
group.long c15:0x4500++0x00
|
|
line.long 0x0 "VMPIDR,Virtualization Multiprocessor ID Register"
|
|
group.long c15:0x4001++0x00
|
|
line.long 0x00 "HSCTLR,System Control Register"
|
|
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
|
|
bitfld.long 0x0 25. " EE ,Exception endianness" "Little,Big"
|
|
bitfld.long 0x0 19. " WXN ,Write permission implies XN" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " A ,Strict Alignment" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " M ,Enable address translation" "Disabled,Enabled"
|
|
group.long c15:0x4011++0x00
|
|
line.long 0x00 "HCR,Hyp Configuration Register"
|
|
bitfld.long 0x00 27. " TGE ,Trap General Exceptions" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " TVM ,Trap Virtual Memory Controls" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " TTLB ,Trap TLB maintenance instructions" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " TPU ,Trap Cache maintenance instructions to point of unification" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TPC ,Trap Data/Unified cache maintenance instructions to point of coherency" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TSW ,Trap Data/Unified cache Set/Way instructions" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " TAC ,Trap Auxiliary Control Register Accesses" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TIDCP ,Trap Lockdown" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " TSC ,Trap SMC" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TID3 ,Trap ID Group 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " TID2 ,Trap ID Group 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " TID1 ,Trap ID Group 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TID0 ,Trap ID Group 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TWE ,Trap WFE" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " TWI ,Trap WFI" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DC ,Default Cacheable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " BSU ,Barrier Shareability Upgrade" "No effect,Inner,Outer,Full system"
|
|
bitfld.long 0x00 9. " FB ,Force Broadcast of TLB maintenance BPIALL and ICIALLU instructions" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " VA ,Virtual External Asynchronous Abort" "Not aborted,Aborted"
|
|
bitfld.long 0x00 7. " VI ,Virtual IRQ interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " VF ,Virtual FIQ interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " AMO ,A-bit Mask Override" "No override,Override"
|
|
bitfld.long 0x00 4. " IMO ,I-bit Mask Override" "No override,Override"
|
|
bitfld.long 0x00 3. " FMO ,F-bit Mask Override" "No override,Override"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PTW ,Protected Table Walk" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SWIO ,Set/Way Invalidation Override" "No override,Override"
|
|
bitfld.long 0x00 0. " VM ,Second Stage of Translation Enable" "Disabled,Enabled"
|
|
group.long c15:0x4111++0x00
|
|
line.long 0x00 "HDCR,Hyp Debug Control Register"
|
|
bitfld.long 0x00 11. " TDRA ,Trap Debug ROM Access" "No effect,Valid"
|
|
bitfld.long 0x00 10. " TDOSA ,Trap Debug OS-related register Access" "No effect,Valid"
|
|
bitfld.long 0x00 9. " TDA ,Trap Debug Access" "No effect,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TDE ,Trap Debug Exceptions" "No effect,Valid"
|
|
bitfld.long 0x00 7. " HPME ,Hypervisor Performance Monitors Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TPM ,Trap Performance Monitors accesses" "No effect,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TPMCR ,Trap Performance Monitor Control Register accesses" "No effect,Valid"
|
|
bitfld.long 0x00 0.--4. " HPMN ,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long c15:0x4211++0x00
|
|
line.long 0x00 "HCPTR,Hyp Coprocessor Trap Register"
|
|
bitfld.long 0x0 31. " TCPAC ,Trap Coprocessor Access Control" "Not trapped,Trapped"
|
|
bitfld.long 0x0 15. " TASE ,Trap Advanced SIMD extensions" "Not trapped,Trapped"
|
|
bitfld.long 0x0 11. " TCP11 ,Trap coprocessor 11" "Not trapped,Trapped"
|
|
textline " "
|
|
bitfld.long 0x0 10. " TCP10 ,Trap coprocessor 10" "Not trapped,Trapped"
|
|
group.long c15:0x4025++0x00
|
|
line.long 0x00 "HSR,Hyp Syndrome Register"
|
|
bitfld.long 0x00 26.--31. " EC ,Exception class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 25. " IL ,Instruction length" "16-bit,32-bit"
|
|
hexmask.long 0x00 0.--24. 1. " ISS ,Instruction specific syndrome"
|
|
group.long c15:0x4311++0x00
|
|
line.long 0x00 "HSTR,Hyp System Trap Register"
|
|
bitfld.long 0x00 17. " TJDBX ,Trap Jazelle-DBX" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " TTEE ,Trap ThumbEE" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " T15 ,Trap to Hyp mode Non-secure priv 15" "Not trapped,Trapped"
|
|
textline " "
|
|
bitfld.long 0x00 13. " T13 ,Trap to Hyp mode Non-secure priv 13" "Not trapped,Trapped"
|
|
bitfld.long 0x00 12. " T12 ,Trap to Hyp mode Non-secure priv 12" "Not trapped,Trapped"
|
|
bitfld.long 0x00 11. " T11 ,Trap to Hyp mode Non-secure priv 11" "Not trapped,Trapped"
|
|
textline " "
|
|
bitfld.long 0x00 10. " T10 ,Trap to Hyp mode Non-secure priv 10" "Not trapped,Trapped"
|
|
bitfld.long 0x00 9. " T9 ,Trap to Hyp mode Non-secure priv 9" "Not trapped,Trapped"
|
|
bitfld.long 0x00 8. " T8 ,Trap to Hyp mode Non-secure priv 8" "Not trapped,Trapped"
|
|
textline " "
|
|
bitfld.long 0x00 7. " T7 ,Trap to Hyp mode Non-secure priv 7" "Not trapped,Trapped"
|
|
bitfld.long 0x00 6. " T6 ,Trap to Hyp mode Non-secure priv 6" "Not trapped,Trapped"
|
|
bitfld.long 0x00 5. " T5 ,Trap to Hyp mode Non-secure priv 5" "Not trapped,Trapped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " T3 ,Trap to Hyp mode Non-secure priv 3" "Not trapped,Trapped"
|
|
bitfld.long 0x00 2. " T2 ,Trap to Hyp mode Non-secure priv 2" "Not trapped,Trapped"
|
|
bitfld.long 0x00 1. " T1 ,Trap to Hyp mode Non-secure priv 1" "Not trapped,Trapped"
|
|
textline " "
|
|
bitfld.long 0x00 0. " T0 ,Trap to Hyp mode Non-secure priv 0" "Not trapped,Trapped"
|
|
group.quad c15:0x14020++0x01
|
|
line.quad 0x00 "HTTBR,Hyp Translation Table Base Register"
|
|
hexmask.quad 0x00 0.--39. 1. " BADDR ,Translation table base address"
|
|
group.long c15:0x4202++0x00
|
|
line.long 0x00 "HTCR,Hyp Translation Control Register"
|
|
bitfld.long 0x00 12.--13. " SH0 ,Shareability attributes for the memory associated with the translation table walks using HTTBR" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 10.--11. " ORGN0 ,Outer Cacheability attributes for the memory associated with the translation table walks using HTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IRGN0 ,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " T0SZ ,The Size offset(four-bit signed integer) of the VTCR addressed region" "0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1"
|
|
group.quad c15:0x16020++0x01
|
|
line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register"
|
|
hexmask.quad.byte 0x00 48.--55. 1. " VMID ,VMID for the translation table"
|
|
hexmask.quad 0x00 0.--39. 1. " BADDR ,Translation table base address"
|
|
group.long c15:0x4212++0x00
|
|
line.long 0x00 "VTCR,Virtualization Translation Control Register"
|
|
bitfld.long 0x00 12.--13. " SH0 ,Shareability attributes for the memory associated with the translation table walks using VTTBR" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 10.--11. " ORGN0 ,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IRGN0 ,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " SL0 ,Starting Level for VTCR addressed region" "Second level,First level,Reserved,Reserved"
|
|
bitfld.long 0x00 4. " S ,Sign extension bit" "0,1"
|
|
bitfld.long 0x00 0.--3. " T0SZ ,The Size offset(four-bit signed integer) of the VTCR addressed region" "0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1"
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c15:0x4015++0x00
|
|
line.long 0x00 "HADFSR,Hyp Auxiliary Data Fault Status Syndrome Register"
|
|
bitfld.long 0x00 31. " VALID ,L1 or L2 ECC double bit error indicator" "No error,Error"
|
|
hexmask.long.byte 0x00 24.--30. 1. " RAMID ,RAM identifier"
|
|
bitfld.long 0x00 23. " L2E ,L2 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 18.--22. " B/W ,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " IND ,Index"
|
|
endif
|
|
group.long c15:0x4006++0x00
|
|
line.long 0x00 "HDFAR,Hyp Data Fault Address Register"
|
|
group.long c15:0x4025++0x00
|
|
line.long 0x00 "HSR,Hyp Syndrome Register"
|
|
bitfld.long 0x00 26.--31. " EC ,Exception class" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC,Trapped Jazelle instruction,Trapped BXJ,Reserved,Trapped MRRC,Reserved,Reserved,Reserved,Reserved,SVC,HVC,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hyp mode Instruction Abort,Executing within Hyp mode Instruction Abort,Reserved,Reserved,Entry into Hyp mode Data Abort,Executing within Hyp mode Data Abort,?..."
|
|
textline " "
|
|
bitfld.long 0x00 25. " IL ,Instruction length" "16-bit,32-bit"
|
|
hexmask.long 0x00 0.--24. 1. " ISS ,Instruction specific syndrome"
|
|
group.long c15:0x4206++0x00
|
|
line.long 0x00 "HIFAR,Hyp Instruction Fault Address Register"
|
|
group.long c15:0x4406++0x00
|
|
line.long 0x00 "HPFAR,Hyp IPA Fault Address Register"
|
|
hexmask.long 0x00 4.--31. 1. " FIPA ,Faulting IPA bits"
|
|
textline " "
|
|
hgroup.long c15:0x407++0x00
|
|
hide.long 0x00 "NOP,No Operation Register"
|
|
in
|
|
wgroup.long c15:0x17++0x00
|
|
line.long 0x00 "ICIALLUIS,Invalidate All Instruction Caches To PoU Inner Shareable Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x617++0x00
|
|
line.long 0x00 "BPIALLIS,Invalidate Entire Branch Predictor Array Inner Shareable Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x57++0x00
|
|
line.long 0x00 "ICIALLU,Invalidate Entire Instruction Cache Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x157++0x00
|
|
line.long 0x00 "ICIMVAU,Invalidate Instruction Cache Line by VA to Point-of-Unification Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x457++0x00
|
|
line.long 0x00 "CP15ISB,Instruction Synchronization Barrier Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x657++0x00
|
|
line.long 0x00 "BPIALL,Invalidate Entire Branch Predictor Array (NOP) Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x757++0x00
|
|
line.long 0x00 "BPIMVA,Invalidate MVA From Branch Predictors Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.word 0x00 5.--15. 1. " SET ,Cache set to invalidate or clean"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x167++0x00
|
|
line.long 0x00 "DCIMVAC,Invalidate Data Cache Line by VA to PoC Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x267++0x00
|
|
line.long 0x00 "DCISW,Invalidate Data Cache Line by Set/Way Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x0087++0x00
|
|
line.long 0x00 "ATS1CPR,Stage 1 current state PL1 read"
|
|
wgroup.long c15:0x0187++0x00
|
|
line.long 0x00 "ATS1CPW,Stage 1 current state PL1 write"
|
|
wgroup.long c15:0x0287++0x00
|
|
line.long 0x00 "ATS1CUR,Stage 1 current state unprivileged (PL0) read"
|
|
wgroup.long c15:0x0387++0x00
|
|
line.long 0x00 "ATS1CUW,Stage 1 current state unprivileged (PL0) write"
|
|
wgroup.long c15:0x0487++0x00
|
|
line.long 0x00 "ATS12NSOPR,Stages 1 and 2 Non-secure PL1 read"
|
|
wgroup.long c15:0x0587++0x00
|
|
line.long 0x00 "ATS12NSOPW,Stages 1 and 2 Non-secure PL1 write"
|
|
wgroup.long c15:0x0687++0x00
|
|
line.long 0x00 "ATS12NSOUR,Stages 1 and 2 Non-secure unprivileged (PL0) read"
|
|
wgroup.long c15:0x0787++0x00
|
|
line.long 0x00 "ATS12NSOUW,Stages 1 and 2 Non-secure unprivileged (PL0) write"
|
|
wgroup.long c15:0x1a7++0x00
|
|
line.long 0x00 "DCCMVAC,Clean Data Cache Line to PoC by VA Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x2a7++0x00
|
|
line.long 0x00 "DCCSW,Clean Data Cache Line by Set/Way Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x4a7++0x00
|
|
line.long 0x00 "CP15DSB,Data Synchronization Barrier Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDRESS ,Address to invalidate or clean"
|
|
wgroup.long c15:0x5a7++0x00
|
|
line.long 0x00 "CP15DMB,Data Memory Barrier Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDRESS ,Address to invalidate or clean"
|
|
wgroup.long c15:0x1b7++0x00
|
|
line.long 0x00 "DCCMVAU,Clean Data Or Unified Cache Line By VA To PoU Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
wgroup.long c15:0x1e7++0x00
|
|
line.long 0x00 "DCCIMVAC,Clean and Invalidate Data Cache Line by VA to PoC Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
wgroup.long c15:0x2e7++0x00
|
|
line.long 0x00 "DCCISW,Clean and Invalidate Data Cache Line by Set/Way Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
wgroup.long c15:0x4087++0x00
|
|
line.long 0x00 "ATS1HR,Address Translate Stage 1 Hyp mode Read"
|
|
wgroup.long c15:0x4187++0x00
|
|
line.long 0x00 "ATS1HW,Address Translate Stage 1 Hyp mode Write"
|
|
wgroup.long c15:0x0038++0x00
|
|
line.long 0x00 "TLBIALLIS,Invalidate entire TLB Inner Shareable"
|
|
wgroup.long c15:0x0138++0x00
|
|
line.long 0x00 "TLBIMVAIS,Invalidate unified TLB entry by MVA Inner Shareable"
|
|
wgroup.long c15:0x0238++0x00
|
|
line.long 0x00 "TLBIASIDIS,Invalidate unified TLB byASID match Inner Shareable"
|
|
wgroup.long c15:0x0338++0x00
|
|
line.long 0x00 "TLBIMVAAIS,Invalidate unified TLB by MVA all ASID Inner Shareable"
|
|
wgroup.long c15:0x0058++0x00
|
|
line.long 0x00 "ITLBIALL,Invalidate instruction TLB"
|
|
wgroup.long c15:0x0158++0x00
|
|
line.long 0x00 "ITLBIMVA,Invalidate instruction TLB entry by MVA"
|
|
wgroup.long c15:0x0258++0x00
|
|
line.long 0x00 "ITLBIASID,Invalidate instruction TLB by ASID match"
|
|
wgroup.long c15:0x0068++0x00
|
|
line.long 0x00 "DTLBIALL,Invalidate data TLB"
|
|
wgroup.long c15:0x0168++0x00
|
|
line.long 0x00 "DTLBIMVA,Invalidate data TLB entry by MVA"
|
|
wgroup.long c15:0x0268++0x00
|
|
line.long 0x00 "DTLBIASID,Invalidate data TLB by ASID match"
|
|
wgroup.long c15:0x0078++0x00
|
|
line.long 0x00 "TLBIALL,Invalidate unified TLB"
|
|
wgroup.long c15:0x0178++0x00
|
|
line.long 0x00 "TLBIMVA,Invalidate unified TLB entry by MVA"
|
|
wgroup.long c15:0x0278++0x00
|
|
line.long 0x00 "TLBIASID,Invalidate unified TLB byASID match"
|
|
wgroup.long c15:0x0378++0x00
|
|
line.long 0x00 "TLBIMVAA,Invalidate unified TLB by MVA all ASID"
|
|
wgroup.long c15:0x4038++0x00
|
|
line.long 0x00 "TLBIALLHIS,Invalidate entire Hyp unified TLB Inner Shareable"
|
|
wgroup.long c15:0x4138++0x00
|
|
line.long 0x00 "TLBIMVAHIS,Invalidate Hyp unified TLB entry by MVA Inner Shareable"
|
|
wgroup.long c15:0x4438++0x00
|
|
line.long 0x00 "TLBIALLNSNHIS,Invalidate entire Non-secure Non-Hyp unified TLB Inner Shareable"
|
|
wgroup.long c15:0x4078++0x00
|
|
line.long 0x00 "TLBIALLH,Invalidate entire Hyp unified TLB"
|
|
wgroup.long c15:0x4178++0x00
|
|
line.long 0x00 "TLBIMVAH,Invalidate Hyp unified TLB entry by MVA"
|
|
wgroup.long c15:0x4478++0x00
|
|
line.long 0x00 "TLBIALLNSNH,Invalidate entire Non-secure Non-Hyp unified TLB"
|
|
group.long c15:0x402A++0x00
|
|
line.long 0x00 "HMAIR0,Hyp Memory Attribute Indirection Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTR3 ,Attribute 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTR2 ,Attribute 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTR1 ,Attribute 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTR0 ,Attribute 0"
|
|
group.long c15:0x412A++0x00
|
|
line.long 0x00 "HMAIR1,Hyp Memory Attribute Indirection Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTR7 ,Attribute 7"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTR6 ,Attribute 6"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTR5 ,Attribute 5"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTR4 ,Attribute 4"
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c15:0x403A++0x00
|
|
line.long 0x00 "HAMAIR0,Hyp Auxiliary Memory Attribute Indirection Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTR3 ,Attribute 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTR2 ,Attribute 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTR1 ,Attribute 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTR0 ,Attribute 0"
|
|
group.long c15:0x413A++0x00
|
|
line.long 0x00 "HAMAIR1,Hyp Auxiliary Memory Attribute Indirection Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTR7 ,Attribute 7"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTR6 ,Attribute 6"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTR5 ,Attribute 5"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTR4 ,Attribute 4"
|
|
else
|
|
hgroup.long c15:0x403A++0x00
|
|
hide.long 0x00 "HAMAIR0,Hyp Auxiliary Memory Attribute Indirection Register 0"
|
|
hgroup.long c15:0x413A++0x00
|
|
hide.long 0x00 "HAMAIR1,Hyp Auxiliary Memory Attribute Indirection Register 1"
|
|
endif
|
|
group.long c15:0x400C++0x00
|
|
line.long 0x00 "HVBAR,Hyp Vector Base Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " HVBADDR ,Hyp Vector Base Address"
|
|
tree.end
|
|
width 12.
|
|
tree "Cache Control and Configuration"
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
rgroup.long c15:0x1100++0x0
|
|
line.long 0x0 "CLIDR,Cache Level ID Register"
|
|
bitfld.long 0x00 27.--29. " LOUU ,Level of Unification Uniprocessor" "Reserved,Level 2,?..."
|
|
bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Reserved,Reserved,Level 3,?..."
|
|
bitfld.long 0x00 21.--23. " LOUIS ,Level of Unification Inner Shareable" "Reserved,Level 2,?..."
|
|
bitfld.long 0x00 18.--20. " CTYPE7 ,Cache type for levels 7" "No cache,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " CTYPE6 ,Cache type for levels 6" "No cache,?..."
|
|
bitfld.long 0x00 12.--14. " CTYPE5 ,Cache type for levels 5" "No cache,?..."
|
|
bitfld.long 0x00 9.--11. " CTYPE4 ,Cache type for levels 4" "No cache,?..."
|
|
bitfld.long 0x00 6.--8. " CTYPE3 ,Cache type for levels 3" "No cache,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " CTYPE2 ,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified,?..."
|
|
bitfld.long 0x00 0.--2. " CTYPE1 ,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate I/D,?..."
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
rgroup.long c15:0x1100++0x0
|
|
line.long 0x0 "CLIDR,Cache Level ID Register"
|
|
bitfld.long 0x00 27.--29. " LOUU ,Level of Unification Uniprocessor" "Reserved,Level 2,?..."
|
|
bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Reserved,Reserved,Level 3,?..."
|
|
bitfld.long 0x00 21.--23. " LOUIS ,Level of Unification Inner Shareable" "Reserved,Level 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " CTYPE2 ,Cache type for levels 2" "Not implemented,Reserved,Reserved,Reserved,Unified,?..."
|
|
bitfld.long 0x00 0.--2. " CTYPE1 ,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate I/D,?..."
|
|
endif
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
rgroup.long c15:0x1000++0x0
|
|
line.long 0x0 "CCSIDR,Current Cache Size ID Register"
|
|
bitfld.long 0x00 31. " WT ,Write-Through" "Not Supported,Supported"
|
|
bitfld.long 0x00 30. " WB ,Write-Back" "Not Supported,Supported"
|
|
bitfld.long 0x00 29. " RA ,Read-Allocate" "Not Supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WA ,Write-Allocate" "Not Supported,Supported"
|
|
hexmask.long.word 0x00 13.--27. 1. " SETS ,Number of Sets"
|
|
hexmask.long.word 0x00 3.--12. 1. " ASSOC ,Associativity"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " LSIZE ,Line Size" "Reserved,Reserved,16 words,?..."
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
rgroup.long c15:0x1000++0x0
|
|
line.long 0x0 "CCSIDR,Current Cache Size ID Register"
|
|
bitfld.long 0x00 31. " WT ,Write-Through" "Not Supported,Supported"
|
|
bitfld.long 0x00 30. " WB ,Write-Back" "Not Supported,Supported"
|
|
bitfld.long 0x00 29. " RA ,Read-Allocate" "Not Supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WA ,Write-Allocate" "Not Supported,Supported"
|
|
hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Number of Sets"
|
|
hexmask.long.word 0x00 3.--12. 1. " ASSOC ,Associativity"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " LSIZE ,Line Size" "Reserved,8 words,16 words,?..."
|
|
endif
|
|
group.long c15:0x2000++0x0
|
|
line.long 0x0 "CSSELR,Cache Size Selection Register"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level of required cache" "Level 1,Level 2,?..."
|
|
bitfld.long 0x00 0. " IND ,Instruction/Not Data" "Data/Unified,Instruction"
|
|
if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
wgroup.long c15:0x10EF++0x00
|
|
line.long 0x00 "DCCIALL,Data Cache Clean and Invalidate All Register"
|
|
bitfld.long 0x00 1.--2. " LEVEL ,Cache level" "L1,L2,Reserved,Reserved"
|
|
else
|
|
hgroup.long c15:0x10EF++0x00
|
|
hide.long 0x00 "DCCIALL,Data Cache Clean and Invalidate All Register"
|
|
endif
|
|
tree "Level 1 memory system"
|
|
width 10.
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c15:0x000F++0x00
|
|
line.long 0x00 "IL1DATA0,Instruction L1 Data 0 Register"
|
|
group.long c15:0x010F++0x00
|
|
line.long 0x00 "IL1DATA1,Instruction L1 Data 1 Register"
|
|
group.long c15:0x020F++0x00
|
|
line.long 0x00 "IL1DATA2,Instruction L1 Data 2 Register"
|
|
group.long c15:0x001F++0x00
|
|
line.long 0x00 "DL1DATA0,Data L1 Data 0 Register"
|
|
group.long c15:0x011F++0x00
|
|
line.long 0x00 "DL1DATA1,Data L1 Data 1 Register"
|
|
group.long c15:0x021F++0x00
|
|
line.long 0x00 "DL1DATA2,Data L1 Data 2 Register"
|
|
group.long c15:0x031F++0x00
|
|
line.long 0x00 "DL1DATA3,Data L1 Data 3 Register"
|
|
wgroup.long c15:0x004F++0x00
|
|
line.long 0x00 "RAMINDEX,RAM Index Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RAMID ,RAM identifier"
|
|
bitfld.long 0x00 18.--21. " B/W ,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " IND ,Index"
|
|
textline " "
|
|
group.quad c15:0x100F0++0x01
|
|
line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register"
|
|
bitfld.quad 0x00 63. " FATAL ,Fatal bit" "0,1"
|
|
hexmask.quad.byte 0x00 40.--47. 1. " OEC ,Other error count"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " REC ,Repeat error count"
|
|
bitfld.quad 0x00 31. " VALID ,Valid bit" "Not valid,Valid"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 24.--30. 1. " RAMID ,RAM Identifier"
|
|
bitfld.quad 0x00 18.--22. " B/W ,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.quad.tbyte 0x00 0.--17. 1. " IND ,Index"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
rgroup.long c15:0x300F++0x0
|
|
line.long 0x00 "CDBGDR0,Data Register 0"
|
|
rgroup.long c15:0x310F++0x0
|
|
line.long 0x00 "CDBGDR1,Data Register 1"
|
|
rgroup.long c15:0x320F++0x0
|
|
line.long 0x00 "CDBGDR2,Data Register 2"
|
|
wgroup.long c15:0x302F++0x0
|
|
line.long 0x00 "CDBGDCT,Data Cache Tag Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3"
|
|
hexmask.long.tbyte 0x00 6.--29. 1. " SI ,Set index"
|
|
bitfld.long 0x00 3.--5. " CWDO ,Cache word data offset" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x312F++0x0
|
|
line.long 0x00 "CDBGICT,Instruction Cache Tag Read Operation Register"
|
|
bitfld.long 0x00 31. " CW ,Cache Way" "Low,High"
|
|
hexmask.long 0x00 5.--30. 1. " SI ,Set index"
|
|
bitfld.long 0x00 2.--4. " CDEO ,Cache data element offset" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x304F++0x0
|
|
line.long 0x00 "CDBGDCD,Data Cache Data Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3"
|
|
hexmask.long.tbyte 0x00 6.--29. 1. " SI ,Set index"
|
|
bitfld.long 0x00 3.--5. " CWDO ,Cache word data offset" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x314F++0x0
|
|
line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register"
|
|
bitfld.long 0x00 31. " CW ,Cache Way" "Low,High"
|
|
hexmask.long 0x00 5.--30. 1. " SI ,Set index"
|
|
bitfld.long 0x00 2.--4. " CDEO ,Cache data element offset" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x324F++0x0
|
|
line.long 0x00 "CDBGTD,TLB Data Read Operation Register"
|
|
bitfld.long 0x00 31. " TLB_WAY ,TLB Way" "Low,High"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TLB_IND ,TLB index"
|
|
elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
rgroup.long c15:0x300F++0x0
|
|
line.long 0x00 "CDBGDR0,Data Register 0"
|
|
bitfld.long 0x00 31. " PMOESID ,Partial MOESI state / Dirty" "Low,High"
|
|
bitfld.long 0x00 30. " POMA ,Partial Outer memory attribute" "Low,High"
|
|
bitfld.long 0x00 29. " PMOESIE ,Partial MOESI state / Exclusive" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " PMOESIV ,Partial MOESI state / Valid" "Low,High"
|
|
bitfld.long 0x00 27. " NS ,Non-Secure state" "Low,High"
|
|
hexmask.long 0x00 0.--26. 1. " TA ,Tag Address"
|
|
rgroup.long c15:0x310F++0x0
|
|
line.long 0x00 "CDBGDR1,Data Register 1"
|
|
bitfld.long 0x00 0. " PMOESID ,Partial MOESI state / Globally shared" "Low,High"
|
|
rgroup.long c15:0x320F++0x0
|
|
line.long 0x00 "CDBGDR2,Data Register 2"
|
|
wgroup.long c15:0x302F++0x0
|
|
line.long 0x00 "CDBGDCT,Data Cache Tag Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3"
|
|
hexmask.long.byte 0x00 6.--12. 1. " SI ,Set index"
|
|
wgroup.long c15:0x312F++0x0
|
|
line.long 0x00 "CDBGICT,Instruction Cache Tag Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3"
|
|
hexmask.long 0x00 6.--30. 1. " SI ,Set index"
|
|
wgroup.long c15:0x304F++0x0
|
|
line.long 0x00 "CDBGDCD,Data Cache Data Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3"
|
|
hexmask.long.byte 0x00 6.--12. 1. " SI ,Set index"
|
|
bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7"
|
|
if (((d.l(c15:0x1000))&0xFFFE000)==0x1DE000)
|
|
wgroup.long c15:0x314F++0x0
|
|
line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3"
|
|
hexmask.long.byte 0x00 6.--12. 1. " SI ,Set index"
|
|
bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7"
|
|
elif (((d.l(c15:0x1000))&0xFFFE000)==0x1FE000&&((d.l(c15:0x2000))&0x3)==0x1)
|
|
wgroup.long c15:0x314F++0x0
|
|
line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3"
|
|
hexmask.long.byte 0x00 6.--13. 1. " SI ,Set index"
|
|
bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7"
|
|
elif (((d.l(c15:0x1000))&0xFFFE000)==0x1FE000&&((d.l(c15:0x2000))&0x3)==0x2)
|
|
wgroup.long c15:0x314F++0x0
|
|
line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3"
|
|
hexmask.long.word 0x00 6.--15. 1. " SI ,Set index"
|
|
bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7"
|
|
elif (((d.l(c15:0x1000))&0xFFFE000)==0x3FE000)
|
|
wgroup.long c15:0x314F++0x0
|
|
line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3"
|
|
hexmask.long.word 0x00 6.--16. 1. " SI ,Set index"
|
|
bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7"
|
|
elif (((d.l(c15:0x1000))&0xFFFE000)==0x7FE000)
|
|
wgroup.long c15:0x314F++0x0
|
|
line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3"
|
|
hexmask.long.word 0x00 6.--17. 1. " SI ,Set index"
|
|
bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7"
|
|
elif (((d.l(c15:0x1000))&0xFFFE000)==0xFFE000)
|
|
wgroup.long c15:0x314F++0x0
|
|
line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3"
|
|
hexmask.long.word 0x00 6.--18. 1. " SI ,Set index"
|
|
bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7"
|
|
elif (((d.l(c15:0x1000))&0xFFFE000)==0x1FFE000)
|
|
wgroup.long c15:0x314F++0x0
|
|
line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3"
|
|
hexmask.long.word 0x00 6.--19. 1. " SI ,Set index"
|
|
bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7"
|
|
elif (((d.l(c15:0x1000))&0xFFFE000)==0x3FFE000)
|
|
wgroup.long c15:0x314F++0x0
|
|
line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3"
|
|
hexmask.long.word 0x00 6.--20. 1. " SI ,Set index"
|
|
bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7"
|
|
else
|
|
hgroup.long c15:0x314F++0x0
|
|
hide.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register"
|
|
endif
|
|
if (((d.l(c15:0x324F))&0x100)==0x100)
|
|
wgroup.long c15:0x324F++0x0
|
|
line.long 0x00 "CDBGTD,TLB Data Read Operation Register"
|
|
bitfld.long 0x00 8. " TYPE ,Type" "RAM0,RAM1"
|
|
else
|
|
wgroup.long c15:0x324F++0x0
|
|
line.long 0x00 "CDBGTD,TLB Data Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " TLB_WAY ,TLB Way" "0,1,2,3"
|
|
bitfld.long 0x00 8. " TYPE ,Type" "RAM0,RAM1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TLB_IND ,TLB index"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Level 2 memory system"
|
|
width 11.
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c15:0x1209++0x0
|
|
line.long 0x00 "L2CTLR,L2 Control Register"
|
|
rbitfld.long 0x00 31. " L2RSTDISABLE ,L2 hardware reset disable pin monitor" "No,Yes"
|
|
bitfld.long 0x00 24.--25. " NCPU , Number of CPU" "1,2,3,4"
|
|
bitfld.long 0x00 23. " IE ,Interrupt Controller" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ECCPE ,ECC and parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " TRAMS ,L2 Tag RAM setup" "0 cycle,1 cycle"
|
|
bitfld.long 0x00 10.--11. " DRAMSLICE ,Data RAM slice" "0,1,2,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TRAMS ,L2 Tag RAM setup" "0 cycle,1 cycle"
|
|
bitfld.long 0x00 6.--8. " TRAML ,L2 Tag RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,5 cycles,5 cycles,5 cycles"
|
|
bitfld.long 0x00 5. " DRAMS ,L2 Data RAM setup" "0 cycle,1 cycle"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " DRAML ,L2 Data RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c15:0x1209++0x0
|
|
line.long 0x00 "L2CTLR,L2 Control Register"
|
|
bitfld.long 0x00 24.--25. " NCPU ,Number of CPU" "1,2,3,4"
|
|
bitfld.long 0x00 23. " IE ,Interrupt Controller" "Not present,Present"
|
|
bitfld.long 0x00 0. " DRAML ,L2 data RAM latency" "2 cycles,3 cycles"
|
|
elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
group.long c15:0x1209++0x0
|
|
line.long 0x00 "L2CTLR,L2 Control Register"
|
|
rbitfld.long 0x00 31. " L2RSTDISABLE ,L2 hardware reset disable pin monitor" "No,Yes"
|
|
bitfld.long 0x00 27.--30. " IWINC ,Controls index incrementation method" "1.,1.,3.,7.,15.,31.,63.,127.,255.,511.,1023.,2047.,4095.,8191.,8191.,8191."
|
|
rbitfld.long 0x00 24.--25. " NCPU , Number of CPU" "1,2,3,4"
|
|
bitfld.long 0x00 20. " SFEN , Snoop Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " L2ECCD ,L2 ECC Disable" "No,Yes"
|
|
bitfld.long 0x00 18. " L2CD ,L2 cache disable" "No,Yes"
|
|
bitfld.long 0x00 15.--17. " TRAMSL ,Tag RAM setup latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
bitfld.long 0x00 12.--14. " TRAMRL ,Tag RAM read latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " TRAMWL ,Tag RAM write latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
bitfld.long 0x00 6.--8. " DRAMSL ,Data RAM setup latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
bitfld.long 0x00 3.--5. " DRAMRL ,Data RAM read latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
bitfld.long 0x00 0.--2. " DRAMWL ,Data RAM write latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
endif
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c15:0x1309++0x0
|
|
line.long 0x00 "L2ECTLR,L2 Extended Control Register"
|
|
bitfld.long 0x00 30. " L2INTASYNCERR ,L2 internal asynchronous error" "No error,Error"
|
|
bitfld.long 0x00 29. " AXIASYNCERR ,AXI asynchronous error" "No error,Error"
|
|
group.long c15:0x100F++0x00
|
|
line.long 0x00 "L2ACTLR,L2 Auxiliary Control Register"
|
|
bitfld.long 0x00 28. " FL2TBCEA ,Forces L2 tag bank clock enable active" "Not forced,Forced"
|
|
bitfld.long 0x00 27. " FL2LCEA ,Forces L2 logic clock enable active" "Not forced,Forced"
|
|
bitfld.long 0x00 26. " EL2GTRCG ,Enables L2 GIC and Timer regional clock gates" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ERTSI ,Enables replay threshold single issue" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " ECWRM ,Enable CPU WFI retention mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " EUCE ,Enables UniqueClean evictions with data" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DSCDT ,Disables SharedClean data transfers" "No,Yes"
|
|
bitfld.long 0x00 12. " DWCWBE ,Disable multiple outstanding WriteClean/WriteBack/Evicts using the same AWID" "No,Yes"
|
|
bitfld.long 0x00 11. " DDSB ,Disables DSB with no DVM synchronization" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DNSDAR ,Disables non-secure debug array read" "No,Yes"
|
|
bitfld.long 0x00 9. " EPF ,Enable use of Prefetch bit in L2 cache replacement algorithm" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DDVMCMOMB ,Disables Distributed Virtual Memory (DVM) transactions and cache maintenance operation message broadcast" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EHDT ,Enables hazard detect timeout" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DSTFM ,Disables shared transactions from master" "No,Yes"
|
|
bitfld.long 0x00 4. " DWUAWLUTFM ,Disables WriteUnique and WriteLineUnique transactions from master" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DCEPTE ,Disables clean/evict push to external" "No,Yes"
|
|
bitfld.long 0x00 2. " LTORPTB ,Limit to one request per tag bank" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EARTT ,Enable arbitration replay threshold timeout" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DPF ,Disable prefetch forwarding" "No,Yes"
|
|
group.long c15:0x130F++0x00
|
|
line.long 0x00 "L2PFR,L2 Prefetch Control Register"
|
|
bitfld.long 0x00 12. " DDTOLSPR ,Disable dynamic throttling of load/store prefetch requests" "No,Yes"
|
|
bitfld.long 0x00 11. " EPRFRUT ,Enable prefetch request from ReadUnique transactions" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DTWDAP ,Disable table walk descriptor access prefetch" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " L2IFPD ,L2 instruction fetch prefetch distance" "0 lines,1 line,2 lines,3 lines"
|
|
bitfld.long 0x00 4.--5. " L2LSDPD ,L2 load/store data prefetch distance" "0 lines,2 lines,4 lines,8 lines"
|
|
textline " "
|
|
group.quad c15:0x110F0++0x01
|
|
line.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register"
|
|
bitfld.quad 0x00 63. " FATAL ,Fatal bit" "0,1"
|
|
hexmask.quad.byte 0x00 40.--47. 1. " OEC ,Other error count"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " REC ,Repeat error count"
|
|
bitfld.quad 0x00 31. " VALID ,Valid bit" "Not valid,Valid"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 24.--30. 1. " RAMID ,RAM Identifier"
|
|
bitfld.quad 0x00 18.--21. " C/W ,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..."
|
|
hexmask.quad.tbyte 0x00 0.--17. 1. " IND ,Index"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c15:0x1309++0x0
|
|
line.long 0x00 "L2ECTLR,L2 Extended Control Register"
|
|
bitfld.long 0x00 29. " AXIASYNCERR ,AXI asynchronous error" "No error,Error"
|
|
hgroup.quad c15:0x110F0++0x01
|
|
hide.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register"
|
|
elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
group.long c15:0x1309++0x0
|
|
line.long 0x00 "L2ECTLR,L2 Extended Control Register"
|
|
bitfld.long 0x00 30. " ECCUNERR ,ECC uncorrectable error " "No error,Error"
|
|
bitfld.long 0x00 29. " AXIASYNCERR ,AXI asynchronous error" "No error,Error"
|
|
bitfld.long 0x00 0. " L2DRC ,Disable L2 retention" "No,Yes"
|
|
rgroup.long c15:0x1609++0x00
|
|
line.long 0x00 "L2MRERRSR,L2 Memory Error Syndrome Register"
|
|
bitfld.long 0x00 31. " FATAL ,Fatal bit" "0,1"
|
|
bitfld.long 0x00 25.--30. " OEC ,Other error count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 19.--24. " REC ,Repeat error count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 6.--18. 1. " ERRLIND ,Index Error Location"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " ERRLWAY ,Way Error Location" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " RAMID ,RAM Identifier" "TAG,DATA"
|
|
bitfld.long 0x00 0. " VALID ,Valid bit" "Not valid,Valid"
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
width 12.
|
|
tree "System Performance Monitor"
|
|
group.long c15:0xc9++0x00
|
|
line.long 0x0 "PMCR,Performance Monitor Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code"
|
|
hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code"
|
|
bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DP ,Disable CCNT when prohibited" "No,Yes"
|
|
bitfld.long 0x00 4. " X ,Export Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " D ,Clock Divider" "Every cycle,64th cycle"
|
|
textline " "
|
|
bitfld.long 0x00 2. " C ,Clock Counter Reset" "No reset,Reset"
|
|
bitfld.long 0x00 1. " P ,Performance Counter Reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " E ,All Counters Enable" "Disabled,Enabled"
|
|
group.long c15:0x1c9++0x00
|
|
line.long 0x00 "PMNCNTENSET,Count Enable Set Register "
|
|
bitfld.long 0x00 5. " P5 ,Event Counter 5 enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Event Counter 4 enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,Event Counter 3 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Event Counter 2 enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,Event Counter 1 enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Event Counter 0 enable bit" "Disabled,Enabled"
|
|
group.long c15:0x2c9++0x00
|
|
line.long 0x00 "PMCNTENCLR,Count Enable Clear Register"
|
|
eventfld.long 0x00 5. " P5 ,Event Counter 5 clear bit" "Disabled,Enabled"
|
|
eventfld.long 0x00 4. " P4 ,Event Counter 4 clear bit" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,Event Counter 3 clear bit" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 2. " P2 ,Event Counter 2 clear bit" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,Event Counter 1 clear bit" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,Event Counter 0 clear bit" "Disabled,Enabled"
|
|
group.long c15:0x3c9++0x00
|
|
line.long 0x00 "PMOVSR,Performance Monitor Overflow Status Register"
|
|
eventfld.long 0x00 5. " P5 ,PMN5 overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 4. " P4 ,PMN4 overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 3. " P3 ,PMN3 overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 2. " P2 ,PMN2 overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 overflow" "No overflow,Overflow"
|
|
group.long c15:0x4c9++0x00
|
|
line.long 0x00 "PMSWINC,Performance Monitor Software Increment"
|
|
bitfld.long 0x00 5. " P5 ,Increment PMN5" "No action,Increment"
|
|
bitfld.long 0x00 4. " P4 ,Increment PMN4" "No action,Increment"
|
|
bitfld.long 0x00 3. " P3 ,Increment PMN3" "No action,Increment"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment"
|
|
bitfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment"
|
|
bitfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment"
|
|
group.long c15:0x5c9++0x00
|
|
line.long 0x00 "PMSELR,Performance Monitor Select Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Current event counter select" "0,1,2,3,4,5,?..."
|
|
group.long c15:0xd9++0x00
|
|
line.long 0x00 "PMCCNTR,Performance Monitor Cycle Count Register"
|
|
group.long c15:0x1d9++0x00
|
|
line.long 0x00 "PMXEVTYPER,Performance Monitor Event Type Register"
|
|
bitfld.long 0x00 31. " P ,Execution at PL1 events counting disable" "No,Yes"
|
|
bitfld.long 0x00 30. " U ,Execution at PL0 events counting disable" "No,Yes"
|
|
bitfld.long 0x00 29. " NSK ,Execution in Non-secure state at PL1 events counting disable" "No,Yes"
|
|
bitfld.long 0x00 28. " NSU ,Execution in Non-secure state at PL0 events counting disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 27. " NSH ,Execution in Non-secure state at PL2 events counting enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--7. 1. " EVTCOUNT ,Event to count"
|
|
group.long c15:0x2d9++0x00
|
|
line.long 0x00 "PMXEVCNTR,Performance Monitor Event Count Register"
|
|
group.long c15:0xe9++0x00
|
|
line.long 0x00 "PMUSERENR,Performance Monitor User Enable Register"
|
|
bitfld.long 0x00 0. " EN ,User mode access enable" "Disabled,Enabled"
|
|
group.long c15:0x1e9++0x00
|
|
line.long 0x00 "PMINTENSET,Performance Monitor Interrupt Enable Set"
|
|
bitfld.long 0x00 5. " P5 ,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
group.long c15:0x2e9++0x00
|
|
line.long 0x00 "PMINTENCLR,Performance Monitor Interrupt Enable Clear"
|
|
eventfld.long 0x00 5. " P5 ,Overflow Interrupt Clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 4. " P4 ,Overflow Interrupt Clear" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,Overflow Interrupt Clear" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,Overflow Interrupt Clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 1. " P1 ,Overflow Interrupt Clear" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,Overflow Interrupt Clear" "Disabled,Enabled"
|
|
group.long c15:0x3e9++0x00
|
|
line.long 0x00 "PMOVSSET,Performance Monitor Overflow Flag Status Set Register"
|
|
bitfld.long 0x00 31. " C ,PMCCNTR overflow bit" "Not overflowed,Overflowed"
|
|
bitfld.long 0x00 30. " P30 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " P29 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Event Counter Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " P25 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Event Counter Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " P21 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Event Counter Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " P17 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Event Counter Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " P13 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Event Counter Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " P9 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Event Counter Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Event Counter Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Event Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
width 12.
|
|
tree "System Timer Register"
|
|
group.long c15:0x000E++0x00
|
|
line.long 0x00 "CNTFRQ,Counter Frequency Register"
|
|
group.long c15:0x001E++0x00
|
|
line.long 0x00 "CNTKCTL,Timer PL1 Control Register"
|
|
bitfld.long 0x00 9. " PL0PTEN ,Controls whether the physical timer registers are accessible from PL0 modes" "Not accessible,Accessible"
|
|
bitfld.long 0x00 8. " PL0VTEN ,Controls whether the virtual timer registers are accessible from PL0 modes" "Not accessible,Accessible"
|
|
bitfld.long 0x00 4.--7. " EVNTI ,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EVNTDIR ,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0"
|
|
bitfld.long 0x00 2. " EVNTEN ,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PL0VCTEN ,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from PL0 modes" "Not accessible,Accessible"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PL0PCTEN ,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from PL0 modes" "Not accessible,Accessible"
|
|
textline ""
|
|
group.quad c15:0x100E0++0x01
|
|
line.quad 0x00 "CNTPCT,Counter Physical Count Register"
|
|
group.quad c15:0x120E0++0x01
|
|
line.quad 0x00 "CNTP_CVAL,Counter PL1 Physical Compare Value Register"
|
|
group.long c15:0x002E++0x00
|
|
line.long 0x00 "CNTP_TVAL,Counter PL1 Physical Timer Value Register"
|
|
group.long c15:0x012E++0x00
|
|
line.long 0x00 "CNTP_CTL,Counter PL1 Physical Timer Control Register"
|
|
bitfld.long 0x00 2. " ISTATUS ,The status of the timer interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " IMASK ,Timer interrupt mask bit" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the timer" "Disabled,Enabled"
|
|
textline ""
|
|
group.quad c15:0x110E0++0x01
|
|
line.quad 0x00 "CNTVCT,Counter Virtual Count Register"
|
|
group.quad c15:0x130E0++0x01
|
|
line.quad 0x00 "CNTV_CVAL,Counter PL1 Virtual Compare Value Register"
|
|
group.long c15:0x003E++0x00
|
|
line.long 0x00 "CNTV_TVAL,Counter PL1 Virtual Timer Value Register"
|
|
group.long c15:0x013E++0x00
|
|
line.long 0x00 "CNTV_CTL,Counter PL1 Virtual Timer Control Register"
|
|
bitfld.long 0x00 2. " ISTATUS ,The status of the timer interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " IMASK ,Timer interrupt mask bit" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the timer" "Disabled,Enabled"
|
|
group.quad c15:0x140E0++0x01
|
|
line.quad 0x00 "CNTVOFF,Counter Virtual Offset Register"
|
|
textline ""
|
|
group.long c15:0x401E++0x00
|
|
line.long 0x00 "CNTHCTL,Counter Non-secure PL2 Control Register"
|
|
bitfld.long 0x00 4.--7. " EVNTI ,Selects which bit of CNTPCTis the trigger for the event stream generated from the physical counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 3. " EVNTDIR ,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0"
|
|
bitfld.long 0x00 2. " EVNTEN ,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PL1VCTEN ,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from PL0 modes" "Not accessible,Accessible"
|
|
bitfld.long 0x00 0. " PL1PCTEN ,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from PL0 modes" "Not accessible,Accessible"
|
|
group.quad c15:0x160E0++0x01
|
|
line.quad 0x00 "CNTHP_CVAL,Counter Non-secure PL2 Physical Compare Value Register"
|
|
group.long c15:0x402E++0x00
|
|
line.long 0x00 "CNTHP_TVAL,Counter Non-secure PL2 Physical Timer Value Register"
|
|
group.long c15:0x412E++0x00
|
|
line.long 0x00 "CNTHP_CTL,Counter Non-secure PL2 Physical Timer Control Register"
|
|
bitfld.long 0x00 2. " ISTATUS ,The status of the timer interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " IMASK ,Timer interrupt mask bit" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the timer" "Disabled,Enabled"
|
|
tree.end
|
|
width 11.
|
|
width 15.
|
|
tree "Debug Registers"
|
|
rgroup.long c14:0.++0x0
|
|
line.long 0x0 "DBGDIDR,Debug ID Register"
|
|
bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x0 20.--23. " CTX_CMP ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
hexmask.long.byte 0x0 16.--19. 1. " VERSION ,Debug Architecture Version"
|
|
bitfld.long 0x0 15. " DEVID ,Debug Device ID" "Low,High"
|
|
bitfld.long 0x0 14. " NSUHD ,Secure User halting debug-mode" "Supported,Not supported"
|
|
textline " "
|
|
bitfld.long 0x0 13. " PCSR ,PC Sample register implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x0 12. " SE ,Security Extensions implemented" "Not implemented,Implemented"
|
|
hexmask.long.byte 0x0 4.--7. 1. " VARIANT ,Implementation-defined Variant Number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--3. 1. " REVISION ,Implementation-defined Revision Number"
|
|
textline " "
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
wgroup.long c14:6.++0x0
|
|
line.long 0x00 "DBGWFAR,Watchpoint Fault Address Register"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
rgroup.long c14:1.++0x0
|
|
line.long 0x00 "DBGDSCR,Debug Status and Control Register (Internal View)"
|
|
bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full"
|
|
bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full"
|
|
bitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched"
|
|
textline " "
|
|
bitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched"
|
|
bitfld.long 0x00 25. " PIPEADV ,PIPEADV Processor Idle flag" "Not idle,Idle"
|
|
bitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC access mode field" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort"
|
|
bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "No,Yes"
|
|
bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "No,Yes"
|
|
bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced"
|
|
bitfld.long 0x00 9. " DBGNOPWRDWN ,Debug no power-down" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " ADABORT ,Asynchronous data abort" "Not aborted,Aborted"
|
|
bitfld.long 0x00 6. " SDABORT ,Synchronous data abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..."
|
|
bitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited"
|
|
bitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug"
|
|
wgroup.long c14:5.++0x0
|
|
line.long 0x00 "DBGDTRTX,Debug Transmit/Receive Register (Internal View)"
|
|
elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
if (((d.l(c14:195.))&0x1)==0x1)
|
|
group.long c14:1.++0x0
|
|
line.long 0x00 "DBGDSCR,Debug Status and Control Register (Internal View)"
|
|
bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full"
|
|
bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full"
|
|
bitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched"
|
|
textline " "
|
|
bitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched"
|
|
rbitfld.long 0x00 25. " PIPEADV ,PIPEADV Processor Idle flag" "Not idle,Idle"
|
|
rbitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC access mode field" "Non-blocking,Stall,Fast,?..."
|
|
rbitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort"
|
|
rbitfld.long 0x00 18. " NS ,Non-secure state status" "Secure,Non-secure"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "Enabled,Disabled"
|
|
rbitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced"
|
|
rbitfld.long 0x00 9. " FS ,Fault status" "No exception,Exception"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 7. " ADABORT_L ,Sticky Asynchronous Abort" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 6. " SDABORT_L ,Sticky Synchronous Data Abort" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..."
|
|
rbitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited"
|
|
rbitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug"
|
|
else
|
|
rgroup.long c14:1.++0x0
|
|
line.long 0x00 "DBGDSCR,Debug Status and Control Register (Internal View)"
|
|
rbitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full"
|
|
rbitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full"
|
|
rbitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched"
|
|
textline " "
|
|
rbitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched"
|
|
rbitfld.long 0x00 25. " PIPEADV ,PIPEADV Processor Idle flag" "Not idle,Idle"
|
|
rbitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC access mode field" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort"
|
|
rbitfld.long 0x00 18. " NS ,Non-secure state status" "Secure,Non-secure"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "Enabled,Disabled"
|
|
rbitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced"
|
|
bitfld.long 0x00 9. " FS ,Fault status" "No exception,Exception"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 7. " ADABORT_L ,Sticky Asynchronous Abort" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 6. " SDABORT_L ,Sticky Synchronous Data Abort" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..."
|
|
rbitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited"
|
|
rbitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug"
|
|
endif
|
|
wgroup.long c14:5.++0x0
|
|
line.long 0x00 "DBGDTRTX,Debug Transmit/Receive Register (Internal View)"
|
|
endif
|
|
group.long c14:0x7++0x0
|
|
line.long 0x00 "DBGVCR,Debug Vector Catch register"
|
|
bitfld.long 0x00 31. " NSF ,FIQ vector catch in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " NSI ,IRG vector catch in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " NSD ,Data Abort vector catch in Non-secure state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " NSP ,Prefetch Abort vector catch in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NSS ,SVC vector catch in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " NSU ,Undefined instruction vector catch in Non-secure state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " NSHF ,FIQ interrupt exception vector catch enable in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " NSHI ,IRQ interrupt exception vector catch enable in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " NSHE ,Hyp Trap or Hyp mode entry exception vector catch enable in Non-secure state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " NSHD ,Data Abort, from Hyp mode exception vector catch enable in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " NSHP ,Prefetch Abort, from Hyp mode exception vector catch enable in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " NSHC ,Hypervisor Call. from Hyp mode exception vector catch enable in Non-secure state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " NSHU ,Undefined Instruction, from Hyp mode exception vector catch enable in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " MF ,FIQ vector catch enable, in Secure state on Monitor mode vector" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MI ,IRQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " MD ,Data Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " MP ,Prefetch Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " MS ,SMC vector catch enable in Secure state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SF ,FIQ vector catch in Secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SI ,IRQ vector catch in Secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SD ,Data Abort vector catch in Secure state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SP ,Prefetch Abort vector catch in Secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SS ,SVC vector catch in Secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SU ,Undefined instruction vector catch in Secure state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " R ,Reset vector catch enable" "Disabled,Enabled"
|
|
group.long c14:9.++0x0
|
|
line.long 0x00 "DBGECR,Debug Event Catch Register"
|
|
bitfld.long 0x00 0. " OSUC ,OS Unlock Catch" "Disabled,Enabled"
|
|
group.long c14:32.++0x0
|
|
line.long 0x00 "DBGDTRRX,Debug Receive Register (External View)"
|
|
wgroup.long c14:33.++0x0
|
|
line.long 0x00 "DBGITR,Debug Instruction Transfer Register"
|
|
rgroup.long c14:33.++0x0
|
|
line.long 0x00 "DBGPCSR,Program Counter Sampling Register"
|
|
hexmask.long 0x00 2.--31. 1. " PCS ,Program Counter sample value"
|
|
bitfld.long 0x00 0.--1. " T ,Meaning of PC sample value" "ARM,Thumb,Reserved,Thumb"
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c14:34.++0x0
|
|
line.long 0x00 "DBGDSCR,Debug Status and Control Register (External View)"
|
|
bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full"
|
|
bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full"
|
|
bitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched"
|
|
textline " "
|
|
bitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched"
|
|
bitfld.long 0x00 25. " PIPEADC ,PIPEADV Processor Idle flag" "Not idle,Idle"
|
|
bitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC acces mode field" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort"
|
|
bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "No,Yes"
|
|
bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "No,Yes"
|
|
bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced"
|
|
bitfld.long 0x00 9. " FS ,Fault Status" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " ADABORT ,Asynchronous data abort" "Not aborted,Aborted"
|
|
bitfld.long 0x00 6. " SDABORT ,Synchronous data abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..."
|
|
bitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited"
|
|
bitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c14:34.++0x0
|
|
line.long 0x00 "DBGDSCR,Debug Status and Control Register (External View)"
|
|
bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full"
|
|
bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full"
|
|
bitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched"
|
|
textline " "
|
|
bitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched"
|
|
bitfld.long 0x00 25. " PIPEADC ,PIPEADV Processor Idle flag" "Not idle,Idle"
|
|
bitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC acces mode field" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort"
|
|
bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "No,Yes"
|
|
bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "No,Yes"
|
|
bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced"
|
|
bitfld.long 0x00 9. " DBGNOPWRDWN ,Debug no power-down" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " ADABORT ,Asynchronous data abort" "Not aborted,Aborted"
|
|
bitfld.long 0x00 6. " SDABORT ,Synchronous data abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..."
|
|
bitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited"
|
|
bitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug"
|
|
elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
if (((d.l(c14:195.))&0x1)==0x1)
|
|
group.long c14:34.++0x0
|
|
line.long 0x00 "DBGDSCR,Debug Status and Control Register (External View)"
|
|
bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full"
|
|
bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full"
|
|
bitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched"
|
|
textline " "
|
|
bitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched"
|
|
rbitfld.long 0x00 25. " PIPEADV ,Sticky Pipeline Advance bit" "Not idle,Idle"
|
|
rbitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not complete,Complete"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC acces mode field" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Discarded"
|
|
bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "Enabled,Disabled"
|
|
rbitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced"
|
|
bitfld.long 0x00 9. " FS ,Fault status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 7. " ADABORT_L ,Sticky Asynchronous Abort" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 6. " SDABORT_L ,Sticky Synchronous Data Abort" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..."
|
|
rbitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited"
|
|
rbitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug"
|
|
else
|
|
group.long c14:34.++0x0
|
|
line.long 0x00 "DBGDSCR,Debug Status and Control Register (External View)"
|
|
rbitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full"
|
|
rbitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full"
|
|
rbitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched"
|
|
textline " "
|
|
rbitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched"
|
|
rbitfld.long 0x00 25. " PIPEADV ,Sticky Pipeline Advance bit" "Not idle,Idle"
|
|
rbitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not complete,Complete"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC acces mode field" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Discarded"
|
|
bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "Enabled,Disabled"
|
|
rbitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "Enabled,Disabled"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " INTDIS ,Interrupt disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced"
|
|
bitfld.long 0x00 9. " FS ,Fault status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 7. " ADABORT_L ,Sticky Asynchronous Abort" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 6. " SDABORT_L ,Sticky Synchronous Data Abort" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..."
|
|
rbitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited"
|
|
rbitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug"
|
|
endif
|
|
endif
|
|
wgroup.long c14:35.++0x0
|
|
line.long 0x00 "DBGDTRTX,Debug Transmit Register (External View)"
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
wgroup.long c14:36.++0x0
|
|
line.long 0x00 "DBGDRCR,Debug Run Control Register"
|
|
bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance bit" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions bits" "No effect,Clear"
|
|
bitfld.long 0x00 1. " RRQ ,Restart request" "No effect,Restart"
|
|
bitfld.long 0x00 0. " HRQ ,Halt request" "No effect,Halt"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
wgroup.long c14:36.++0x0
|
|
line.long 0x00 "DBGDRCR,Debug Run Control Register"
|
|
bitfld.long 0x00 4. " CBRRQ ,CBRRQ" "Low,High"
|
|
bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance bit" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RR ,Restart request" "No effect,Restart"
|
|
bitfld.long 0x00 0. " HR ,Halt request" "No effect,Halt"
|
|
endif
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c14:37.++0x0
|
|
line.long 0x00 "DBGEACR,Debug External Auxiliary Control Register"
|
|
bitfld.long 0x00 3. " CDRS ,Core debug reset status" "No reset,Reset"
|
|
bitfld.long 0x00 2. " DECRR ,Debug extend core reset request" "No request,Request"
|
|
bitfld.long 0x00 1. " DPDO ,Debug power-down override" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DCSC ,Debug clock stop control" "Stopped,Running"
|
|
textline " "
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c14:37.++0x0
|
|
line.long 0x00 "DBGEACR,Debug External Auxiliary Control Register"
|
|
bitfld.long 0x00 3. " CDRS ,Core debug reset status" "No reset,Reset"
|
|
endif
|
|
rgroup.long c14:40.++0x0
|
|
line.long 0x00 "DBGPCSR,Program Counter Sampling Register"
|
|
hexmask.long 0x00 2.--31. 1. " PCS ,Program Counter sample value"
|
|
bitfld.long 0x00 0.--1. " T ,Meaning of PC sample value" "ARM,Thumb,?..."
|
|
rgroup.long c14:41.++0x0
|
|
line.long 0x00 "DBGCIDSR,DBGCIDSR"
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
rgroup.long c14:42.++0x0
|
|
line.long 0x00 "DBGVIDSR,Virtualization ID Sampling Register"
|
|
bitfld.long 0x00 31. " NS ,NS state sample" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " H ,Hyp mode sample" "Not associated,Associated"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VMID ,VMID sample"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
rgroup.long c14:42.++0x0
|
|
line.long 0x00 "DBGVIDSR,DBGVIDSR"
|
|
endif
|
|
width 15.
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
textline " "
|
|
wgroup.long c14:958.++0x0
|
|
line.long 0x00 "DBGITOCTRL,Debug Integration Output Control Register"
|
|
bitfld.long 0x00 3. " NPMUIRQ ,Drives the nPMUIRQ output" "Low,High"
|
|
bitfld.long 0x00 2. " CTI_PMUIRQ ,Drives the internal signal equivalent to PMUIRQ that goes from the Performance Monitor Unit (PMU) to the Cross Trigger Interface (CTI)" "Low,High"
|
|
bitfld.long 0x00 1. " CTI_DBGRESTARTED ,Drives the internal signal that goes from the Debug unit to the CTI to acknowledge success of a debug restart command" "Low,High"
|
|
bitfld.long 0x00 0. " CTI_DBGTRIGGER ,Drives the internal signal equivalent to DBGTRIGGER that goes from the Debug unit to the CTI" "Low,High"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
textline " "
|
|
wgroup.long c14:958.++0x0
|
|
line.long 0x00 "DBGITMISCOUT,Integration Miscellaneous Signals Output Register"
|
|
bitfld.long 0x00 9. " DBGRESTARTED ,Value of the DBGRESTARTED output pin" "Low,High"
|
|
bitfld.long 0x00 4. " PMUIRQ ,Value of PMUIRQ output pin" "Low,High"
|
|
bitfld.long 0x00 0. " DBGACK ,Value of the DBGACK output pin" "Low,High"
|
|
endif
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
rgroup.long c14:959.++0x0
|
|
line.long 0x00 "DBGITISR,Debug Integration Input Status Register"
|
|
bitfld.long 0x00 3. " DBGSWENABLE ,Reads the state of the DBGSWENABLE input" "Low,High"
|
|
bitfld.long 0x00 2. " CTI_DBGRESTART ,CTI debug restart" "Low,High"
|
|
bitfld.long 0x00 1. " CTI_EDBGRQ ,CTI debug request" "Low,High"
|
|
bitfld.long 0x00 0. " EDBGRQ ,Reads the state of the EDBGRQ input" "Low,High"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
textline " "
|
|
rgroup.long c14:959.++0x0
|
|
line.long 0x00 "DBGITMISCIN,Integration Miscellaneous Signals Input Register"
|
|
bitfld.long 0x00 2. " NFIQ ,Read value of nFIQ input pin" "Low,High"
|
|
bitfld.long 0x00 1. " NIRQ ,Read value of nIRQ input pin" "Low,High"
|
|
bitfld.long 0x00 0. " EDBGRQ ,Read value of EDBGRQ input pin" "Low,High"
|
|
endif
|
|
if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
if (((d.l(c15:0x202))&0x80000000)==0x80000000)
|
|
rgroup.quad c14:128.++0x1
|
|
line.quad 0x0 "DBGDRAR,Debug ROM Address Register"
|
|
hexmask.quad 0x0 12.--39. 0x1000 " ROMADDR ,ROM physical address"
|
|
bitfld.quad 0x0 0.--1. " VALID ,ROM table address valid" "Not valid,Reserved,Reserved,Valid"
|
|
rgroup.quad c14:256.++0x1
|
|
line.quad 0x0 "DBGDSAR,Debug Self Address Offset Register"
|
|
hexmask.quad 0x0 12.--39. 0x1000 " SELFOFFSET ,Debug bus self-address offset value"
|
|
bitfld.quad 0x0 0.--1. " VALID ,Debug self address offset valid" "Not valid,Reserved,Reserved,Valid"
|
|
else
|
|
rgroup.long c14:128.++0x0
|
|
line.long 0x0 "DBGDRAR,Debug ROM Address Register"
|
|
hexmask.long 0x0 12.--31. 0x1000 " ROMADDR ,ROM physical address"
|
|
bitfld.long 0x0 0.--1. " VALID ,ROM table address valid" "Not valid,Reserved,Reserved,Valid"
|
|
rgroup.long c14:256.++0x0
|
|
line.long 0x0 "DBGDSAR,Debug Self Address Offset Register"
|
|
hexmask.long 0x0 12.--31. 0x1000 " SELFOFFSET ,Debug bus self-address offset value"
|
|
bitfld.long 0x0 0.--1. " VALID ,Debug self address offset valid" "Not valid,Reserved,Reserved,Valid"
|
|
endif
|
|
group.long c14:195.++0x00
|
|
line.long 0x00 "DBGOSDLR,OS Double Lock Register"
|
|
bitfld.long 0x00 0. " DLK ,OS Double Lock control bit" "Unlocked,Locked"
|
|
else
|
|
hgroup.quad c14:128.++0x1
|
|
hide.quad 0x0 "DBGDRAR,Debug ROM Address Register"
|
|
hgroup.quad c14:256.++0x1
|
|
hide.quad 0x0 "DBGDSAR,Debug Self Address Offset Register"
|
|
hgroup.long c14:195.++0x00
|
|
hide.long 0x00 "DBGOSDLR,OS Double Lock Register"
|
|
endif
|
|
wgroup.long c14:192.++0x00
|
|
line.long 0x00 "DBGOSLAR,Operating System Lock Access Register"
|
|
rgroup.long c14:193.++0x00
|
|
line.long 0x00 "DBGOSLSR,Operating System Lock Status Register"
|
|
bitfld.long 0x00 1. " OSLK ,Status of the OS Lock" "Not locked,Locked"
|
|
bitfld.long 0x00 0. 3. " OSLM ,OS Lock Model implemented Bit" "Reserved,Reserved,W/o DBGOSSRR,?..."
|
|
group.long c14:196.++0x00
|
|
line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register"
|
|
bitfld.long 0x00 3. " COREPURQ ,Core Power Up Request" "Low,High"
|
|
bitfld.long 0x00 2. " HCWR ,Hold Core Warm Reset" "No reset,Reset"
|
|
bitfld.long 0x00 1. " CWRR ,Core Warm Reset Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CORENPDRQ ,Core No Power down Request" "Low,High"
|
|
rgroup.long c14:197.++0x0
|
|
line.long 0x00 "DBGPRSR,Device Power-down and Reset Status Register"
|
|
bitfld.long 0x00 6. " DLK ,OS Double Lock status" "Low,High"
|
|
bitfld.long 0x00 5. " OSLK ,OS Lock status" "Low,High"
|
|
bitfld.long 0x00 4. " HALTED ,Halted" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SR ,Sticky Reset Status" "Low,High"
|
|
bitfld.long 0x00 2. " RS ,Reset Status" "Low,High"
|
|
bitfld.long 0x00 1. " SPD ,Sticky Power-down Status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PU ,Power-up Status" "Low,High"
|
|
tree "Processor ID registers"
|
|
rgroup.long c14:(832.+0.)++0x00
|
|
line.long 0x00 "PIDR0,Processor ID register 0"
|
|
rgroup.long c14:(832.+1.)++0x00
|
|
line.long 0x00 "PIDR1,Processor ID register 1"
|
|
rgroup.long c14:(832.+2.)++0x00
|
|
line.long 0x00 "PIDR2,Processor ID register 2"
|
|
rgroup.long c14:(832.+3.)++0x00
|
|
line.long 0x00 "PIDR3,Processor ID register 3"
|
|
rgroup.long c14:(832.+4.)++0x00
|
|
line.long 0x00 "PIDR4,Processor ID register 4"
|
|
rgroup.long c14:(832.+5.)++0x00
|
|
line.long 0x00 "PIDR5,Processor ID register 5"
|
|
rgroup.long c14:(832.+6.)++0x00
|
|
line.long 0x00 "PIDR6,Processor ID register 6"
|
|
rgroup.long c14:(832.+7.)++0x00
|
|
line.long 0x00 "PIDR7,Processor ID register 7"
|
|
rgroup.long c14:(832.+8.)++0x00
|
|
line.long 0x00 "PIDR8,Processor ID register 8"
|
|
rgroup.long c14:(832.+9.)++0x00
|
|
line.long 0x00 "PIDR9,Processor ID register 9"
|
|
rgroup.long c14:(832.+10.)++0x00
|
|
line.long 0x00 "PIDR10,Processor ID register 10"
|
|
rgroup.long c14:(832.+11.)++0x00
|
|
line.long 0x00 "PIDR11,Processor ID register 11"
|
|
rgroup.long c14:(832.+12.)++0x00
|
|
line.long 0x00 "PIDR12,Processor ID register 12"
|
|
rgroup.long c14:(832.+13.)++0x00
|
|
line.long 0x00 "PIDR13,Processor ID register 13"
|
|
rgroup.long c14:(832.+14.)++0x00
|
|
line.long 0x00 "PIDR14,Processor ID register 14"
|
|
rgroup.long c14:(832.+15.)++0x00
|
|
line.long 0x00 "PIDR15,Processor ID register 15"
|
|
rgroup.long c14:(832.+16.)++0x00
|
|
line.long 0x00 "PIDR16,Processor ID register 16"
|
|
rgroup.long c14:(832.+17.)++0x00
|
|
line.long 0x00 "PIDR17,Processor ID register 17"
|
|
rgroup.long c14:(832.+18.)++0x00
|
|
line.long 0x00 "PIDR18,Processor ID register 18"
|
|
rgroup.long c14:(832.+19.)++0x00
|
|
line.long 0x00 "PIDR19,Processor ID register 19"
|
|
rgroup.long c14:(832.+20.)++0x00
|
|
line.long 0x00 "PIDR20,Processor ID register 20"
|
|
rgroup.long c14:(832.+21.)++0x00
|
|
line.long 0x00 "PIDR21,Processor ID register 21"
|
|
rgroup.long c14:(832.+22.)++0x00
|
|
line.long 0x00 "PIDR22,Processor ID register 22"
|
|
rgroup.long c14:(832.+23.)++0x00
|
|
line.long 0x00 "PIDR23,Processor ID register 23"
|
|
rgroup.long c14:(832.+24.)++0x00
|
|
line.long 0x00 "PIDR24,Processor ID register 24"
|
|
rgroup.long c14:(832.+25.)++0x00
|
|
line.long 0x00 "PIDR25,Processor ID register 25"
|
|
rgroup.long c14:(832.+26.)++0x00
|
|
line.long 0x00 "PIDR26,Processor ID register 26"
|
|
rgroup.long c14:(832.+27.)++0x00
|
|
line.long 0x00 "PIDR27,Processor ID register 27"
|
|
rgroup.long c14:(832.+28.)++0x00
|
|
line.long 0x00 "PIDR28,Processor ID register 28"
|
|
rgroup.long c14:(832.+29.)++0x00
|
|
line.long 0x00 "PIDR29,Processor ID register 29"
|
|
rgroup.long c14:(832.+30.)++0x00
|
|
line.long 0x00 "PIDR30,Processor ID register 30"
|
|
rgroup.long c14:(832.+31.)++0x00
|
|
line.long 0x00 "PIDR31,Processor ID register 31"
|
|
rgroup.long c14:(832.+32.)++0x00
|
|
line.long 0x00 "PIDR32,Processor ID register 32"
|
|
rgroup.long c14:(832.+33.)++0x00
|
|
line.long 0x00 "PIDR33,Processor ID register 33"
|
|
rgroup.long c14:(832.+34.)++0x00
|
|
line.long 0x00 "PIDR34,Processor ID register 34"
|
|
rgroup.long c14:(832.+35.)++0x00
|
|
line.long 0x00 "PIDR35,Processor ID register 35"
|
|
rgroup.long c14:(832.+36.)++0x00
|
|
line.long 0x00 "PIDR36,Processor ID register 36"
|
|
rgroup.long c14:(832.+37.)++0x00
|
|
line.long 0x00 "PIDR37,Processor ID register 37"
|
|
rgroup.long c14:(832.+38.)++0x00
|
|
line.long 0x00 "PIDR38,Processor ID register 38"
|
|
rgroup.long c14:(832.+39.)++0x00
|
|
line.long 0x00 "PIDR39,Processor ID register 39"
|
|
rgroup.long c14:(832.+40.)++0x00
|
|
line.long 0x00 "PIDR40,Processor ID register 40"
|
|
rgroup.long c14:(832.+41.)++0x00
|
|
line.long 0x00 "PIDR41,Processor ID register 41"
|
|
rgroup.long c14:(832.+42.)++0x00
|
|
line.long 0x00 "PIDR42,Processor ID register 42"
|
|
rgroup.long c14:(832.+43.)++0x00
|
|
line.long 0x00 "PIDR43,Processor ID register 43"
|
|
rgroup.long c14:(832.+44.)++0x00
|
|
line.long 0x00 "PIDR44,Processor ID register 44"
|
|
rgroup.long c14:(832.+45.)++0x00
|
|
line.long 0x00 "PIDR45,Processor ID register 45"
|
|
rgroup.long c14:(832.+46.)++0x00
|
|
line.long 0x00 "PIDR46,Processor ID register 46"
|
|
rgroup.long c14:(832.+47.)++0x00
|
|
line.long 0x00 "PIDR47,Processor ID register 47"
|
|
rgroup.long c14:(832.+48.)++0x00
|
|
line.long 0x00 "PIDR48,Processor ID register 48"
|
|
rgroup.long c14:(832.+49.)++0x00
|
|
line.long 0x00 "PIDR49,Processor ID register 49"
|
|
rgroup.long c14:(832.+50.)++0x00
|
|
line.long 0x00 "PIDR50,Processor ID register 50"
|
|
rgroup.long c14:(832.+51.)++0x00
|
|
line.long 0x00 "PIDR51,Processor ID register 51"
|
|
rgroup.long c14:(832.+52.)++0x00
|
|
line.long 0x00 "PIDR52,Processor ID register 52"
|
|
rgroup.long c14:(832.+53.)++0x00
|
|
line.long 0x00 "PIDR53,Processor ID register 53"
|
|
rgroup.long c14:(832.+54.)++0x00
|
|
line.long 0x00 "PIDR54,Processor ID register 54"
|
|
rgroup.long c14:(832.+55.)++0x00
|
|
line.long 0x00 "PIDR55,Processor ID register 55"
|
|
rgroup.long c14:(832.+56.)++0x00
|
|
line.long 0x00 "PIDR56,Processor ID register 56"
|
|
rgroup.long c14:(832.+57.)++0x00
|
|
line.long 0x00 "PIDR57,Processor ID register 57"
|
|
rgroup.long c14:(832.+58.)++0x00
|
|
line.long 0x00 "PIDR58,Processor ID register 58"
|
|
rgroup.long c14:(832.+59.)++0x00
|
|
line.long 0x00 "PIDR59,Processor ID register 59"
|
|
rgroup.long c14:(832.+60.)++0x00
|
|
line.long 0x00 "PIDR60,Processor ID register 60"
|
|
rgroup.long c14:(832.+61.)++0x00
|
|
line.long 0x00 "PIDR61,Processor ID register 61"
|
|
rgroup.long c14:(832.+62.)++0x00
|
|
line.long 0x00 "PIDR62,Processor ID register 62"
|
|
rgroup.long c14:(832.+63.)++0x00
|
|
line.long 0x00 "PIDR63,Processor ID register 63"
|
|
tree.end
|
|
tree "Coresight Management Registers"
|
|
group.long c14:960.++0x0
|
|
line.long 0x00 "DBGITCTRL,Debug Integration Mode Control Register"
|
|
bitfld.long 0x00 0. " IME ,Integration Mode Enable" "Disabled,Enabled"
|
|
group.long c14:1000.++0x0
|
|
line.long 0x0 "DBGCLAIMSET,Claim Tag Set Register"
|
|
bitfld.long 0x0 7. " CT7 ,Claim Tag 7 Set" "Not set,Set"
|
|
bitfld.long 0x0 6. " CT6 ,Claim Tag 6 Set" "Not set,Set"
|
|
bitfld.long 0x0 5. " CT5 ,Claim Tag 5 Set" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0 4. " CT4 ,Claim Tag 4 Set" "Not set,Set"
|
|
bitfld.long 0x0 3. " CT3 ,Claim Tag 3 Set" "Not set,Set"
|
|
bitfld.long 0x0 2. " CT2 ,Claim Tag 2 Set" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CT1 ,Claim Tag 1 Set" "Not set,Set"
|
|
bitfld.long 0x0 0. " CT0 ,Claim Tag 0 Set" "Not set,Set"
|
|
group.long c14:1001.++0x0
|
|
line.long 0x0 "DBGCLAIMCLR,Claim Tag Clear Register"
|
|
bitfld.long 0x0 7. " CT7 ,Claim Tag 7 Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x0 6. " CT6 ,Claim Tag 6 Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x0 5. " CT5 ,Claim Tag 5 Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 4. " CT4 ,Claim Tag 4 Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x0 3. " CT3 ,Claim Tag 3 Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x0 2. " CT2 ,Claim Tag 2 Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CT1 ,Claim Tag 1 Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x0 0. " CT0 ,Claim Tag 0 Clear" "Not cleared,Cleared"
|
|
wgroup.long c14:1004.++0x00
|
|
line.long 0x00 "DBGLAR,Lock Access Register"
|
|
rgroup.long c14:1005.++0x00
|
|
line.long 0x00 "DBGLSR,Lock Status Register"
|
|
bitfld.long 0x00 2. " NTT ,Not 32-bit access" "32-bit,Not 32-bit"
|
|
bitfld.long 0x00 1. " SLK ,Software Lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " SLI ,Software Lock Implemented" "Not implemented,Implemented"
|
|
textline " "
|
|
rgroup.long c14:1006.++0x0
|
|
line.long 0x0 "DBGAUTHSTATUS,Debug Authentication Status Register"
|
|
bitfld.long 0x00 7. " SNI ,Secure non-invasive debug features implementation" "No effect,Implemented"
|
|
bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enable (DBGEN OR NIDEN) AND (SPIDEN OR SPNIDEN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SI ,Secure invasive debug features implementation" "No effect,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SE ,Secure invasive debug enable (DBGEN AND SPIDEN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implementation" "Not implemented,Implemented"
|
|
bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enable (DBGEN OR NIDEN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implementation" "Not implemented,Implemented"
|
|
bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enable (DBGEN)" "Disabled,Enabled"
|
|
textline " "
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
rgroup.long c14:1009.++0x0
|
|
line.long 0x0 "DBGDEVID1,Debug Device ID Register 1"
|
|
bitfld.long 0x00 0.--3. " PCSROFFSET ,Defines the offset applied to DBGPCSR samples" "Depends on instr set state,No offset,?..."
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
rgroup.long c14:1009.++0x0
|
|
line.long 0x0 "DBGDEVID1,Debug Device ID Register 1"
|
|
bitfld.long 0x00 0.--3. " PCSROFFSET ,Defines the offset applied to DBGPCSR samples" "Reserved,No offset,?..."
|
|
endif
|
|
textline " "
|
|
rgroup.long c14:1010.++0x0
|
|
line.long 0x0 "DBGDEVID0,Debug Device ID Register 0"
|
|
bitfld.long 0x0 24.--27. " AR ,Debug External Auxiliary Control Register support status" "Reserved,Supported,?..."
|
|
bitfld.long 0x0 20.--23. " DL ,Support for Debug OS Double Lock Register" "Reserved,Supported,?..."
|
|
bitfld.long 0x0 16.--19. " VE ,Specifies implementation of Virtualization Extension" "Reserved,Implemented,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12.--15. " VC ,Form of the vector catch event implemented" "Implemented,?..."
|
|
bitfld.long 0x0 8.--11. " BPAM ,Level of support for Immediate Virtual Address matching breakpoint masking capability" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented"
|
|
bitfld.long 0x0 4.--7. " WPAM ,Level of support for the DVA matching watchpoint masking capability" "Reserved,Implemented,?..."
|
|
textline " "
|
|
bitfld.long 0x0 0.--3. " PCS ,Level of support for Program Counter sampling using debug registers 40 and 41" "Reserved,Reserved,Reserved,Implemented,?..."
|
|
textline " "
|
|
rgroup.long c14:1011.++0x00
|
|
line.long 0x00 "DBGDEVTYPE,Debug Device Type Register"
|
|
bitfld.long 0x00 4.--7. " T ,Sub type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " C ,Main class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long c14:1016.++0x00
|
|
line.long 0x00 "DBGPID0,Debug Peripheral ID 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PN[7:0] ,Part Number [7:0]"
|
|
rgroup.long c14:1017.++0x00
|
|
line.long 0x00 "DBGPID1,Debug Peripheral ID 1"
|
|
hexmask.long.byte 0x00 4.--7. 1. " JEPID[3:0] ,JEP Identity Code[3:0]"
|
|
hexmask.long.byte 0x00 0.--3. 1. " PN[11:8] ,Part Number [11:8]"
|
|
rgroup.long c14:1018.++0x00
|
|
line.long 0x00 "DBGPID2,Debug Peripheral ID 2"
|
|
hexmask.long.byte 0x00 4.--7. 1. " REV ,Revision"
|
|
bitfld.long 0x00 3. " UJEPCODE ,Uses JEP Code" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--2. 1. " JEPID[6:4] ,JEP Identity Code[6:4]"
|
|
rgroup.long c14:1019.++0x00
|
|
line.long 0x00 "DBGPID3,Debug Peripheral ID 3"
|
|
hexmask.long.byte 0x00 4.--7. 1. " REVAND ,Manufacturing revision"
|
|
hexmask.long.byte 0x00 0.--3. 1. " CM ,Customer modified"
|
|
rgroup.long c14:1012.++0x00
|
|
line.long 0x00 "DBGPID4,Debug Peripheral ID 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " 4KB_COUNT ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CONT_CODE ,JEP 106 Continuation code"
|
|
rgroup.long c14:1020.++0x00
|
|
line.long 0x00 "DBGCID0,Debug Component ID 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 0"
|
|
rgroup.long c14:1021.++0x00
|
|
line.long 0x00 "DBGCID1,Debug Component ID 1"
|
|
hexmask.long.byte 0x00 4.--7. 1. " CC ,Component class"
|
|
hexmask.long.byte 0x00 0.--3. 1. " PREAMBLE ,Preamble byte 1"
|
|
rgroup.long c14:1022.++0x00
|
|
line.long 0x00 "DBGCID2,Debug Component ID 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 2"
|
|
rgroup.long c14:1023.++0x00
|
|
line.long 0x00 "DBGCID3,Debug Component ID 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 3"
|
|
tree.end
|
|
tree.end
|
|
width 10.
|
|
tree "Breakpoint Registers"
|
|
if ((d.l(c14:80.+0.)&0x500000)==(0x500000||0x400000||0x100000||0x0))
|
|
group.long c14:(64.+0.)++0x0
|
|
line.long 0x00 "DBGBVR0,Breakpoint Value Register(Address comparison)"
|
|
hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31"
|
|
else
|
|
group.long c14:(64.+0.)++0x0
|
|
line.long 0x00 "DBGBVR0,Breakpoint Value Register(Context matching)"
|
|
endif
|
|
group.long c14:(80.+0.)++0x0
|
|
line.long 0x00 "DBGBCR0,Breakpoint Control Register"
|
|
bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..."
|
|
bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1"
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode"
|
|
bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled"
|
|
if ((d.l(c14:80.+1.)&0x500000)==(0x500000||0x400000||0x100000||0x0))
|
|
group.long c14:(64.+1.)++0x0
|
|
line.long 0x00 "DBGBVR1,Breakpoint Value Register(Address comparison)"
|
|
hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31"
|
|
else
|
|
group.long c14:(64.+1.)++0x0
|
|
line.long 0x00 "DBGBVR1,Breakpoint Value Register(Context matching)"
|
|
endif
|
|
group.long c14:(80.+1.)++0x0
|
|
line.long 0x00 "DBGBCR1,Breakpoint Control Register"
|
|
bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..."
|
|
bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1"
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode"
|
|
bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled"
|
|
if ((d.l(c14:80.+2.)&0x500000)==(0x500000||0x400000||0x100000||0x0))
|
|
group.long c14:(64.+2.)++0x0
|
|
line.long 0x00 "DBGBVR2,Breakpoint Value Register(Address comparison)"
|
|
hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31"
|
|
else
|
|
group.long c14:(64.+2.)++0x0
|
|
line.long 0x00 "DBGBVR2,Breakpoint Value Register(Context matching)"
|
|
endif
|
|
group.long c14:(80.+2.)++0x0
|
|
line.long 0x00 "DBGBCR2,Breakpoint Control Register"
|
|
bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..."
|
|
bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1"
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode"
|
|
bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled"
|
|
if ((d.l(c14:80.+3.)&0x500000)==(0x500000||0x400000||0x100000||0x0))
|
|
group.long c14:(64.+3.)++0x0
|
|
line.long 0x00 "DBGBVR3,Breakpoint Value Register(Address comparison)"
|
|
hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31"
|
|
else
|
|
group.long c14:(64.+3.)++0x0
|
|
line.long 0x00 "DBGBVR3,Breakpoint Value Register(Context matching)"
|
|
endif
|
|
group.long c14:(80.+3.)++0x0
|
|
line.long 0x00 "DBGBCR3,Breakpoint Control Register"
|
|
bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..."
|
|
bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1"
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode"
|
|
bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled"
|
|
if ((d.l(c14:80.+4.)&0x500000)==(0x500000||0x400000||0x100000||0x0))
|
|
group.long c14:(64.+4.)++0x0
|
|
line.long 0x00 "DBGBVR4,Breakpoint Value Register(Address comparison)"
|
|
hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31"
|
|
else
|
|
group.long c14:(64.+4.)++0x0
|
|
line.long 0x00 "DBGBVR4,Breakpoint Value Register(Context matching)"
|
|
endif
|
|
group.long c14:(80.+4.)++0x0
|
|
line.long 0x00 "DBGBCR4,Breakpoint Control Register"
|
|
bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..."
|
|
bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1"
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode"
|
|
bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled"
|
|
if ((d.l(c14:80.+5.)&0x500000)==(0x500000||0x400000||0x100000||0x0))
|
|
group.long c14:(64.+5.)++0x0
|
|
line.long 0x00 "DBGBVR5,Breakpoint Value Register(Address comparison)"
|
|
hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31"
|
|
else
|
|
group.long c14:(64.+5.)++0x0
|
|
line.long 0x00 "DBGBVR5,Breakpoint Value Register(Context matching)"
|
|
endif
|
|
group.long c14:(80.+5.)++0x0
|
|
line.long 0x00 "DBGBCR5,Breakpoint Control Register"
|
|
bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..."
|
|
bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1"
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode"
|
|
bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled"
|
|
group.long c14:148.++0x0
|
|
line.long 0x00 "DBGBXVR0,Debug Breakpoint Extended Value Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VMID , VMID value"
|
|
group.long c14:149.++0x0
|
|
line.long 0x00 "DBGBXVR1,Debug Breakpoint Extended Value Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VMID , VMID value"
|
|
tree.end
|
|
width 10.
|
|
tree "Watchpoint Control Registers"
|
|
group.long c14:(96.+0.)++0x00
|
|
line.long 0x00 "DBGWVR0,Watchpoint Value Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " DA ,Data address"
|
|
if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
group.long c14:(112.+0.)++0x00
|
|
line.long 0x00 "DBGWCR0,Watchpoint Control Register"
|
|
bitfld.long 0x0 24.--28. " Mask ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " WT ,Watchpoint Type" "Unlinked data addr match,Linked data addr match"
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked breakpoint number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "0,1"
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " LSC ,Load/store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Hyp,Privileged,Unprivileged,Any"
|
|
bitfld.long 0x0 0. " E ,Watchpoint enable" "Disabled,Enabled"
|
|
elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c14:(112.+0.)++0x00
|
|
line.long 0x00 "DBGWCR0,Watchpoint Control Register"
|
|
bitfld.long 0x0 24.--28. " MASK ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " WT ,Watchpoint Type" "Disabled,Enabled"
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,?..."
|
|
bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " LSC ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
endif
|
|
group.long c14:(96.+1.)++0x00
|
|
line.long 0x00 "DBGWVR1,Watchpoint Value Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " DA ,Data address"
|
|
if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
group.long c14:(112.+1.)++0x00
|
|
line.long 0x00 "DBGWCR1,Watchpoint Control Register"
|
|
bitfld.long 0x0 24.--28. " Mask ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " WT ,Watchpoint Type" "Unlinked data addr match,Linked data addr match"
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked breakpoint number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "0,1"
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " LSC ,Load/store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Hyp,Privileged,Unprivileged,Any"
|
|
bitfld.long 0x0 0. " E ,Watchpoint enable" "Disabled,Enabled"
|
|
elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c14:(112.+1.)++0x00
|
|
line.long 0x00 "DBGWCR1,Watchpoint Control Register"
|
|
bitfld.long 0x0 24.--28. " MASK ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " WT ,Watchpoint Type" "Disabled,Enabled"
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,?..."
|
|
bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " LSC ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
endif
|
|
group.long c14:(96.+2.)++0x00
|
|
line.long 0x00 "DBGWVR2,Watchpoint Value Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " DA ,Data address"
|
|
if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
group.long c14:(112.+2.)++0x00
|
|
line.long 0x00 "DBGWCR2,Watchpoint Control Register"
|
|
bitfld.long 0x0 24.--28. " Mask ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " WT ,Watchpoint Type" "Unlinked data addr match,Linked data addr match"
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked breakpoint number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "0,1"
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " LSC ,Load/store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Hyp,Privileged,Unprivileged,Any"
|
|
bitfld.long 0x0 0. " E ,Watchpoint enable" "Disabled,Enabled"
|
|
elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c14:(112.+2.)++0x00
|
|
line.long 0x00 "DBGWCR2,Watchpoint Control Register"
|
|
bitfld.long 0x0 24.--28. " MASK ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " WT ,Watchpoint Type" "Disabled,Enabled"
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,?..."
|
|
bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " LSC ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
endif
|
|
group.long c14:(96.+3.)++0x00
|
|
line.long 0x00 "DBGWVR3,Watchpoint Value Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " DA ,Data address"
|
|
if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
group.long c14:(112.+3.)++0x00
|
|
line.long 0x00 "DBGWCR3,Watchpoint Control Register"
|
|
bitfld.long 0x0 24.--28. " Mask ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " WT ,Watchpoint Type" "Unlinked data addr match,Linked data addr match"
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked breakpoint number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "0,1"
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " LSC ,Load/store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Hyp,Privileged,Unprivileged,Any"
|
|
bitfld.long 0x0 0. " E ,Watchpoint enable" "Disabled,Enabled"
|
|
elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c14:(112.+3.)++0x00
|
|
line.long 0x00 "DBGWCR3,Watchpoint Control Register"
|
|
bitfld.long 0x0 24.--28. " MASK ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " WT ,Watchpoint Type" "Disabled,Enabled"
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,?..."
|
|
bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " LSC ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
endif
|
|
tree.end
|
|
width 0xb
|
|
base AD:(per.long(c15:0x400F)&0xffff8000)
|
|
tree "Interrupt Controller"
|
|
width 20.
|
|
group.long 0x1000++0x03 "Interrupt Controller Distributor"
|
|
line.long 0x00 "GICD_CTLR,Distributor Control Register"
|
|
bitfld.long 0x00 0. " ENABLE ,Global Interrupt Enable" "Disabled,Enabled"
|
|
rgroup.long 0x1004++0x03
|
|
line.long 0x00 "GICD_ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 11.--15. " LSPI ,Locable Shared Peripheral Interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 10. " SECURITYEXTN ,Indicate whether interrupt controller implements the security extensions" "No effect,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 5.--7. " CPUNUMBER ,Indicates the number of implemented CPU interfaces" "1,2,3,4,?..."
|
|
bitfld.long 0x00 0.--4. " ITLN ,Indicates the number of interrupts that the interrupt controller supports" "up to 32/0 external,up to 64/32 external,up to 96/64 external,up to 128/96 external,up to 160/128 external,up to 192/160 external,up to 224/192 external,up to 256/224 external,up to 288/256 external,up to 320/288 external,up to 352/320 external,up to 384/352 external,up to 416/384 external,up to 438/416 external,up to 480/438 external,up to 512/480 external,?..."
|
|
rgroup.long 0x1008++0x03
|
|
line.long 0x00 "GICD_IIDR,Distributor Implementer Identfication Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRODID ,Product ID"
|
|
bitfld.long 0x00 16.--19. " VAR ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " REV ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer"
|
|
width 20.
|
|
tree "Groups Registers"
|
|
group.long 0x1080++0x03
|
|
line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0"
|
|
bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Group 0,Group 1"
|
|
group.long 0x1084++0x03
|
|
line.long 0x0 "GICD_IGROUPR1,Interrupt Group Register 1"
|
|
bitfld.long 0x00 31. " GSB63 ,Group Status Bit 63" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB62 ,Group Status Bit 62" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB61 ,Group Status Bit 61" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB60 ,Group Status Bit 60" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB59 ,Group Status Bit 59" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB58 ,Group Status Bit 58" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB57 ,Group Status Bit 57" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB56 ,Group Status Bit 56" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB55 ,Group Status Bit 55" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB54 ,Group Status Bit 54" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB53 ,Group Status Bit 53" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB52 ,Group Status Bit 52" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB51 ,Group Status Bit 51" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB50 ,Group Status Bit 50" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB49 ,Group Status Bit 49" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB48 ,Group Status Bit 48" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB47 ,Group Status Bit 47" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB46 ,Group Status Bit 46" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB45 ,Group Status Bit 45" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB44 ,Group Status Bit 44" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB43 ,Group Status Bit 43" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB42 ,Group Status Bit 42" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB41 ,Group Status Bit 41" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB40 ,Group Status Bit 40" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB39 ,Group Status Bit 39" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB38 ,Group Status Bit 38" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB37 ,Group Status Bit 37" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB36 ,Group Status Bit 36" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB35 ,Group Status Bit 35" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB34 ,Group Status Bit 34" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB33 ,Group Status Bit 33" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB32 ,Group Status Bit 32" "Group 0,Group 1"
|
|
group.long 0x1088++0x03
|
|
line.long 0x0 "GICD_IGROUPR2,Interrupt Group Register 2"
|
|
bitfld.long 0x00 31. " GSB95 ,Group Status Bit 95" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB94 ,Group Status Bit 94" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB93 ,Group Status Bit 93" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB92 ,Group Status Bit 92" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB91 ,Group Status Bit 91" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB90 ,Group Status Bit 90" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB89 ,Group Status Bit 89" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB88 ,Group Status Bit 88" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB87 ,Group Status Bit 87" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB86 ,Group Status Bit 86" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB85 ,Group Status Bit 85" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB84 ,Group Status Bit 84" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB83 ,Group Status Bit 83" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB82 ,Group Status Bit 82" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB81 ,Group Status Bit 81" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB80 ,Group Status Bit 80" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB79 ,Group Status Bit 79" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB78 ,Group Status Bit 78" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB77 ,Group Status Bit 77" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB76 ,Group Status Bit 76" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB75 ,Group Status Bit 75" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB74 ,Group Status Bit 74" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB73 ,Group Status Bit 73" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB72 ,Group Status Bit 72" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB71 ,Group Status Bit 71" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB70 ,Group Status Bit 70" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB69 ,Group Status Bit 69" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB68 ,Group Status Bit 68" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB67 ,Group Status Bit 67" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB66 ,Group Status Bit 66" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB65 ,Group Status Bit 65" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB64 ,Group Status Bit 64" "Group 0,Group 1"
|
|
group.long 0x108C++0x03
|
|
line.long 0x0 "GICD_IGROUPR3,Interrupt Group Register 3"
|
|
bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB126 ,Group Status Bit 126" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB125 ,Group Status Bit 125" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB123 ,Group Status Bit 123" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB122 ,Group Status Bit 122" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB120 ,Group Status Bit 120" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB119 ,Group Status Bit 119" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB117 ,Group Status Bit 117" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB116 ,Group Status Bit 116" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB114 ,Group Status Bit 114" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB113 ,Group Status Bit 113" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB111 ,Group Status Bit 111" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB110 ,Group Status Bit 110" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB108 ,Group Status Bit 108" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB107 ,Group Status Bit 107" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB105 ,Group Status Bit 105" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB104 ,Group Status Bit 104" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB102 ,Group Status Bit 102" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB101 ,Group Status Bit 101" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB99 ,Group Status Bit 99" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB98 ,Group Status Bit 98" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB97 ,Group Status Bit 97" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB96 ,Group Status Bit 96" "Group 0,Group 1"
|
|
group.long 0x1090++0x03
|
|
line.long 0x0 "GICD_IGROUPR4,Interrupt Group Register 4"
|
|
bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB158 ,Group Status Bit 158" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB157 ,Group Status Bit 157" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB155 ,Group Status Bit 155" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB154 ,Group Status Bit 154" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB152 ,Group Status Bit 152" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB151 ,Group Status Bit 151" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB149 ,Group Status Bit 149" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB148 ,Group Status Bit 148" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB146 ,Group Status Bit 146" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB145 ,Group Status Bit 145" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB143 ,Group Status Bit 143" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB142 ,Group Status Bit 142" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB140 ,Group Status Bit 140" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB139 ,Group Status Bit 139" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB137 ,Group Status Bit 137" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB136 ,Group Status Bit 136" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB134 ,Group Status Bit 134" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB133 ,Group Status Bit 133" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB131 ,Group Status Bit 131" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB130 ,Group Status Bit 130" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB128 ,Group Status Bit 128" "Group 0,Group 1"
|
|
group.long 0x1094++0x03
|
|
line.long 0x0 "GICD_IGROUPR5,Interrupt Group Register 5"
|
|
bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB190 ,Group Status Bit 190" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB189 ,Group Status Bit 189" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB187 ,Group Status Bit 187" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB186 ,Group Status Bit 186" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB184 ,Group Status Bit 184" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB183 ,Group Status Bit 183" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB181 ,Group Status Bit 181" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB180 ,Group Status Bit 180" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB178 ,Group Status Bit 178" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB177 ,Group Status Bit 177" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB175 ,Group Status Bit 175" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB174 ,Group Status Bit 174" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB172 ,Group Status Bit 172" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB171 ,Group Status Bit 171" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB169 ,Group Status Bit 169" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB168 ,Group Status Bit 168" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB166 ,Group Status Bit 166" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB165 ,Group Status Bit 165" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB163 ,Group Status Bit 163" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB162 ,Group Status Bit 162" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB160 ,Group Status Bit 160" "Group 0,Group 1"
|
|
group.long 0x1098++0x03
|
|
line.long 0x0 "GICD_IGROUPR6,Interrupt Group Register 6"
|
|
bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB222 ,Group Status Bit 222" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB221 ,Group Status Bit 221" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB219 ,Group Status Bit 219" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB218 ,Group Status Bit 218" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB216 ,Group Status Bit 216" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB215 ,Group Status Bit 215" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB213 ,Group Status Bit 213" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB212 ,Group Status Bit 212" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB210 ,Group Status Bit 210" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB209 ,Group Status Bit 209" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB207 ,Group Status Bit 207" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB206 ,Group Status Bit 206" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB204 ,Group Status Bit 204" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB203 ,Group Status Bit 203" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB201 ,Group Status Bit 201" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB200 ,Group Status Bit 200" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB198 ,Group Status Bit 198" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB197 ,Group Status Bit 197" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB195 ,Group Status Bit 195" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB194 ,Group Status Bit 194" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB192 ,Group Status Bit 192" "Group 0,Group 1"
|
|
group.long 0x109c++0x03
|
|
line.long 0x0 "GICD_IGROUPR7,Interrupt Group Register 7"
|
|
bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB254 ,Group Status Bit 254" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB253 ,Group Status Bit 253" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB251 ,Group Status Bit 251" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB250 ,Group Status Bit 250" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB248 ,Group Status Bit 248" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB247 ,Group Status Bit 247" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB245 ,Group Status Bit 245" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB244 ,Group Status Bit 244" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB242 ,Group Status Bit 242" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB241 ,Group Status Bit 241" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB239 ,Group Status Bit 239" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB238 ,Group Status Bit 238" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB236 ,Group Status Bit 236" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB235 ,Group Status Bit 235" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB233 ,Group Status Bit 233" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB232 ,Group Status Bit 232" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB230 ,Group Status Bit 230" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB229 ,Group Status Bit 229" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB227 ,Group Status Bit 227" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB226 ,Group Status Bit 226" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB224 ,Group Status Bit 224" "Group 0,Group 1"
|
|
group.long 0x10a0++0x03
|
|
line.long 0x0 "GICD_IGROUPR8,Interrupt Group Register 8"
|
|
bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB286 ,Group Status Bit 286" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB285 ,Group Status Bit 285" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB283 ,Group Status Bit 283" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB282 ,Group Status Bit 282" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB280 ,Group Status Bit 280" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB279 ,Group Status Bit 279" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB277 ,Group Status Bit 277" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB276 ,Group Status Bit 276" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB274 ,Group Status Bit 274" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB273 ,Group Status Bit 273" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB271 ,Group Status Bit 271" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB270 ,Group Status Bit 270" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB268 ,Group Status Bit 268" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB267 ,Group Status Bit 267" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB265 ,Group Status Bit 265" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB264 ,Group Status Bit 264" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB262 ,Group Status Bit 262" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB261 ,Group Status Bit 261" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB259 ,Group Status Bit 259" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB258 ,Group Status Bit 258" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB256 ,Group Status Bit 256" "Group 0,Group 1"
|
|
group.long 0x10a4++0x03
|
|
line.long 0x0 "GICD_IGROUPR9,Interrupt Group Register 9"
|
|
bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB318 ,Group Status Bit 318" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB317 ,Group Status Bit 317" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB315 ,Group Status Bit 315" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB314 ,Group Status Bit 314" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB312 ,Group Status Bit 312" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB311 ,Group Status Bit 311" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB309 ,Group Status Bit 309" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB308 ,Group Status Bit 308" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB306 ,Group Status Bit 306" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB305 ,Group Status Bit 305" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB303 ,Group Status Bit 303" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB302 ,Group Status Bit 302" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB300 ,Group Status Bit 300" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB299 ,Group Status Bit 299" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB297 ,Group Status Bit 297" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB296 ,Group Status Bit 296" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB294 ,Group Status Bit 294" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB293 ,Group Status Bit 293" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB291 ,Group Status Bit 291" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB290 ,Group Status Bit 290" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB288 ,Group Status Bit 288" "Group 0,Group 1"
|
|
group.long 0x10a8++0x03
|
|
line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10"
|
|
bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB350 ,Group Status Bit 350" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB349 ,Group Status Bit 349" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB347 ,Group Status Bit 347" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB346 ,Group Status Bit 346" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB344 ,Group Status Bit 344" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB343 ,Group Status Bit 343" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB341 ,Group Status Bit 341" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB340 ,Group Status Bit 340" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB338 ,Group Status Bit 338" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB337 ,Group Status Bit 337" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB335 ,Group Status Bit 335" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB334 ,Group Status Bit 334" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB332 ,Group Status Bit 332" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB331 ,Group Status Bit 331" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB329 ,Group Status Bit 329" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB328 ,Group Status Bit 328" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB326 ,Group Status Bit 326" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB325 ,Group Status Bit 325" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB323 ,Group Status Bit 323" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB322 ,Group Status Bit 322" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB320 ,Group Status Bit 320" "Group 0,Group 1"
|
|
group.long 0x10ac++0x03
|
|
line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11"
|
|
bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB382 ,Group Status Bit 382" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB381 ,Group Status Bit 381" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB379 ,Group Status Bit 379" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB378 ,Group Status Bit 378" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB376 ,Group Status Bit 376" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB375 ,Group Status Bit 375" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB373 ,Group Status Bit 373" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB372 ,Group Status Bit 372" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB370 ,Group Status Bit 370" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB369 ,Group Status Bit 369" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB367 ,Group Status Bit 367" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB366 ,Group Status Bit 366" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB364 ,Group Status Bit 364" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB363 ,Group Status Bit 363" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB361 ,Group Status Bit 361" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB360 ,Group Status Bit 360" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB358 ,Group Status Bit 358" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB357 ,Group Status Bit 357" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB355 ,Group Status Bit 355" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB354 ,Group Status Bit 354" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB352 ,Group Status Bit 352" "Group 0,Group 1"
|
|
group.long 0x10b0++0x03
|
|
line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12"
|
|
bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB414 ,Group Status Bit 414" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB413 ,Group Status Bit 413" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB411 ,Group Status Bit 411" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB410 ,Group Status Bit 410" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB408 ,Group Status Bit 408" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB407 ,Group Status Bit 407" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB405 ,Group Status Bit 405" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB404 ,Group Status Bit 404" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB402 ,Group Status Bit 402" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB401 ,Group Status Bit 401" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB399 ,Group Status Bit 399" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB398 ,Group Status Bit 398" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB396 ,Group Status Bit 396" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB395 ,Group Status Bit 395" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB393 ,Group Status Bit 393" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB392 ,Group Status Bit 392" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB390 ,Group Status Bit 390" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB389 ,Group Status Bit 389" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB387 ,Group Status Bit 387" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB386 ,Group Status Bit 386" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB384 ,Group Status Bit 384" "Group 0,Group 1"
|
|
group.long 0x10b4++0x03
|
|
line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13"
|
|
bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB446 ,Group Status Bit 446" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB445 ,Group Status Bit 445" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB443 ,Group Status Bit 443" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB442 ,Group Status Bit 442" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB440 ,Group Status Bit 440" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB439 ,Group Status Bit 439" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB437 ,Group Status Bit 437" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB436 ,Group Status Bit 436" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB434 ,Group Status Bit 434" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB433 ,Group Status Bit 433" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB431 ,Group Status Bit 431" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB430 ,Group Status Bit 430" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB428 ,Group Status Bit 428" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB427 ,Group Status Bit 427" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB425 ,Group Status Bit 425" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB424 ,Group Status Bit 424" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB422 ,Group Status Bit 422" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB421 ,Group Status Bit 421" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB419 ,Group Status Bit 419" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB418 ,Group Status Bit 418" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB416 ,Group Status Bit 416" "Group 0,Group 1"
|
|
group.long 0x10b8++0x03
|
|
line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14"
|
|
bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB478 ,Group Status Bit 478" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB477 ,Group Status Bit 477" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB475 ,Group Status Bit 475" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB474 ,Group Status Bit 474" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB472 ,Group Status Bit 472" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB471 ,Group Status Bit 471" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB469 ,Group Status Bit 469" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB468 ,Group Status Bit 468" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB466 ,Group Status Bit 466" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB465 ,Group Status Bit 465" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB463 ,Group Status Bit 463" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB462 ,Group Status Bit 462" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB460 ,Group Status Bit 460" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB459 ,Group Status Bit 459" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB457 ,Group Status Bit 457" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB456 ,Group Status Bit 456" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB454 ,Group Status Bit 454" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB453 ,Group Status Bit 453" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB451 ,Group Status Bit 451" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB450 ,Group Status Bit 450" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB448 ,Group Status Bit 448" "Group 0,Group 1"
|
|
group.long 0x10bc++0x03
|
|
line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15"
|
|
bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB510 ,Group Status Bit 510" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB509 ,Group Status Bit 509" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB507 ,Group Status Bit 507" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB506 ,Group Status Bit 506" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB504 ,Group Status Bit 504" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB503 ,Group Status Bit 503" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB501 ,Group Status Bit 501" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB500 ,Group Status Bit 500" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB498 ,Group Status Bit 498" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB497 ,Group Status Bit 497" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB495 ,Group Status Bit 495" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB494 ,Group Status Bit 494" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB492 ,Group Status Bit 492" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB491 ,Group Status Bit 491" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB489 ,Group Status Bit 489" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB488 ,Group Status Bit 488" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB486 ,Group Status Bit 486" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB485 ,Group Status Bit 485" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB483 ,Group Status Bit 483" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB482 ,Group Status Bit 482" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB480 ,Group Status Bit 480" "Group 0,Group 1"
|
|
textline " "
|
|
tree.end
|
|
tree "Set-Enable Registers"
|
|
group.long 0x1100++0x03
|
|
line.long 0x0 "GICD_ISENABLER0,Interrupt Set Enable Register 0"
|
|
bitfld.long 0x00 31. " SEB31 ,Set Enable Bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SEB30 ,Set Enable Bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SEB29 ,Set Enable Bit 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SEB28 ,Set Enable Bit 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SEB27 ,Set Enable Bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " SEB26 ,Set Enable Bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SEB25 ,Set Enable Bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " SEB24 ,Set Enable Bit 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SEB23 ,Set Enable Bit 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SEB22 ,Set Enable Bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SEB21 ,Set Enable Bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SEB20 ,Set Enable Bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SEB19 ,Set Enable Bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SEB18 ,Set Enable Bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SEB17 ,Set Enable Bit 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SEB16 ,Set Enable Bit 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SEB15 ,Set Enable Bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SEB14 ,Set Enable Bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SEB13 ,Set Enable Bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SEB12 ,Set Enable Bit 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SEB11 ,Set Enable Bit 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SEB10 ,Set Enable Bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SEB9 ,Set Enable Bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SEB8 ,Set Enable Bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SEB7 ,Set Enable Bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SEB6 ,Set Enable Bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SEB5 ,Set Enable Bit 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SEB4 ,Set Enable Bit 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SEB3 ,Set Enable Bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SEB2 ,Set Enable Bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SEB1 ,Set Enable Bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SEB0 ,Set Enable Bit 0" "Disabled,Enabled"
|
|
group.long 0x1104++0x03
|
|
line.long 0x0 "GICD_ISENABLER1,Interrupt Set Enable Register 1"
|
|
bitfld.long 0x00 31. " SEB63 ,Set Enable Bit 63" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SEB62 ,Set Enable Bit 62" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SEB61 ,Set Enable Bit 61" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SEB60 ,Set Enable Bit 60" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SEB59 ,Set Enable Bit 59" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " SEB58 ,Set Enable Bit 58" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SEB57 ,Set Enable Bit 57" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " SEB56 ,Set Enable Bit 56" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SEB55 ,Set Enable Bit 55" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SEB54 ,Set Enable Bit 54" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SEB53 ,Set Enable Bit 53" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SEB52 ,Set Enable Bit 52" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SEB51 ,Set Enable Bit 51" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SEB50 ,Set Enable Bit 50" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SEB49 ,Set Enable Bit 49" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SEB48 ,Set Enable Bit 48" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SEB47 ,Set Enable Bit 47" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SEB46 ,Set Enable Bit 46" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SEB45 ,Set Enable Bit 45" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SEB44 ,Set Enable Bit 44" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SEB43 ,Set Enable Bit 43" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SEB42 ,Set Enable Bit 42" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SEB41 ,Set Enable Bit 41" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SEB40 ,Set Enable Bit 40" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SEB39 ,Set Enable Bit 39" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SEB38 ,Set Enable Bit 38" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SEB37 ,Set Enable Bit 37" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SEB36 ,Set Enable Bit 36" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SEB35 ,Set Enable Bit 35" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SEB34 ,Set Enable Bit 34" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SEB33 ,Set Enable Bit 33" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SEB32 ,Set Enable Bit 32" "Disabled,Enabled"
|
|
group.long 0x1108++0x03
|
|
line.long 0x0 "GICD_ISENABLER2,Interrupt Set Enable Register 2"
|
|
bitfld.long 0x00 31. " SEB95 ,Set Enable Bit 95" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SEB94 ,Set Enable Bit 94" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SEB93 ,Set Enable Bit 93" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SEB92 ,Set Enable Bit 92" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SEB91 ,Set Enable Bit 91" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " SEB90 ,Set Enable Bit 90" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SEB89 ,Set Enable Bit 89" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " SEB88 ,Set Enable Bit 88" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SEB87 ,Set Enable Bit 87" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SEB86 ,Set Enable Bit 86" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SEB85 ,Set Enable Bit 85" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SEB84 ,Set Enable Bit 84" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SEB83 ,Set Enable Bit 83" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SEB82 ,Set Enable Bit 82" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SEB81 ,Set Enable Bit 81" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SEB80 ,Set Enable Bit 80" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SEB79 ,Set Enable Bit 79" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SEB78 ,Set Enable Bit 78" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SEB77 ,Set Enable Bit 77" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SEB76 ,Set Enable Bit 76" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SEB75 ,Set Enable Bit 75" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SEB74 ,Set Enable Bit 74" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SEB73 ,Set Enable Bit 73" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SEB72 ,Set Enable Bit 72" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SEB71 ,Set Enable Bit 71" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SEB70 ,Set Enable Bit 70" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SEB69 ,Set Enable Bit 69" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SEB68 ,Set Enable Bit 68" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SEB67 ,Set Enable Bit 67" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SEB66 ,Set Enable Bit 66" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SEB65 ,Set Enable Bit 65" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SEB64 ,Set Enable Bit 64" "Disabled,Enabled"
|
|
group.long 0x110C++0x03
|
|
line.long 0x0 "GICD_ISENABLER3,Interrupt Set Enable Register 3"
|
|
bitfld.long 0x00 31. " SEB127 ,Set Enable Bit 127" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SEB126 ,Set Enable Bit 126" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SEB125 ,Set Enable Bit 125" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SEB124 ,Set Enable Bit 124" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SEB123 ,Set Enable Bit 123" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " SEB122 ,Set Enable Bit 122" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SEB121 ,Set Enable Bit 121" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " SEB120 ,Set Enable Bit 120" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SEB119 ,Set Enable Bit 119" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SEB118 ,Set Enable Bit 118" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SEB117 ,Set Enable Bit 117" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SEB116 ,Set Enable Bit 116" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SEB115 ,Set Enable Bit 115" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SEB114 ,Set Enable Bit 114" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SEB113 ,Set Enable Bit 113" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SEB112 ,Set Enable Bit 112" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SEB111 ,Set Enable Bit 111" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SEB110 ,Set Enable Bit 110" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SEB109 ,Set Enable Bit 109" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SEB108 ,Set Enable Bit 108" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SEB107 ,Set Enable Bit 107" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SEB106 ,Set Enable Bit 106" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SEB105 ,Set Enable Bit 105" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SEB104 ,Set Enable Bit 104" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SEB103 ,Set Enable Bit 103" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SEB102 ,Set Enable Bit 102" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SEB101 ,Set Enable Bit 101" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SEB100 ,Set Enable Bit 100" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SEB99 ,Set Enable Bit 99" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SEB98 ,Set Enable Bit 98" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SEB97 ,Set Enable Bit 97" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SEB96 ,Set Enable Bit 96" "Disabled,Enabled"
|
|
group.long 0x1110++0x03
|
|
line.long 0x0 "GICD_ISENABLER4,Interrupt Set Enable Register 4"
|
|
bitfld.long 0x00 31. " SEB159 ,Set Enable Bit 159" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SEB158 ,Set Enable Bit 158" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SEB157 ,Set Enable Bit 157" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SEB156 ,Set Enable Bit 156" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SEB155 ,Set Enable Bit 155" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " SEB154 ,Set Enable Bit 154" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SEB153 ,Set Enable Bit 153" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " SEB152 ,Set Enable Bit 152" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SEB151 ,Set Enable Bit 151" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SEB150 ,Set Enable Bit 150" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SEB149 ,Set Enable Bit 149" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SEB148 ,Set Enable Bit 148" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SEB147 ,Set Enable Bit 147" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SEB146 ,Set Enable Bit 146" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SEB145 ,Set Enable Bit 145" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SEB144 ,Set Enable Bit 144" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SEB143 ,Set Enable Bit 143" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SEB142 ,Set Enable Bit 142" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SEB141 ,Set Enable Bit 141" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SEB140 ,Set Enable Bit 140" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SEB139 ,Set Enable Bit 139" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SEB138 ,Set Enable Bit 138" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SEB137 ,Set Enable Bit 137" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SEB136 ,Set Enable Bit 136" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SEB135 ,Set Enable Bit 135" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SEB134 ,Set Enable Bit 134" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SEB133 ,Set Enable Bit 133" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SEB132 ,Set Enable Bit 132" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SEB131 ,Set Enable Bit 131" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SEB130 ,Set Enable Bit 130" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SEB129 ,Set Enable Bit 129" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SEB128 ,Set Enable Bit 128" "Disabled,Enabled"
|
|
group.long 0x1114++0x03
|
|
line.long 0x0 "GICD_ISENABLER5,Interrupt Set Enable Register 5"
|
|
bitfld.long 0x00 31. " SEB191 ,Set Enable Bit 191" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SEB190 ,Set Enable Bit 190" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SEB189 ,Set Enable Bit 189" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SEB188 ,Set Enable Bit 188" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SEB187 ,Set Enable Bit 187" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " SEB186 ,Set Enable Bit 186" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SEB185 ,Set Enable Bit 185" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " SEB184 ,Set Enable Bit 184" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SEB183 ,Set Enable Bit 183" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SEB182 ,Set Enable Bit 182" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SEB181 ,Set Enable Bit 181" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SEB180 ,Set Enable Bit 180" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SEB179 ,Set Enable Bit 179" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SEB178 ,Set Enable Bit 178" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SEB177 ,Set Enable Bit 177" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SEB176 ,Set Enable Bit 176" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SEB175 ,Set Enable Bit 175" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SEB174 ,Set Enable Bit 174" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SEB173 ,Set Enable Bit 173" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SEB172 ,Set Enable Bit 172" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SEB171 ,Set Enable Bit 171" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SEB170 ,Set Enable Bit 170" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SEB169 ,Set Enable Bit 169" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SEB168 ,Set Enable Bit 168" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SEB167 ,Set Enable Bit 167" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SEB166 ,Set Enable Bit 166" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SEB165 ,Set Enable Bit 165" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SEB164 ,Set Enable Bit 164" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SEB163 ,Set Enable Bit 163" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SEB162 ,Set Enable Bit 162" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SEB161 ,Set Enable Bit 161" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SEB160 ,Set Enable Bit 160" "Disabled,Enabled"
|
|
group.long 0x1118++0x03
|
|
line.long 0x0 "GICD_ISENABLER6,Interrupt Set Enable Register 6"
|
|
bitfld.long 0x00 31. " SEB223 ,Set Enable Bit 223" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SEB222 ,Set Enable Bit 222" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SEB221 ,Set Enable Bit 221" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SEB220 ,Set Enable Bit 220" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SEB219 ,Set Enable Bit 219" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " SEB218 ,Set Enable Bit 218" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SEB217 ,Set Enable Bit 217" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " SEB216 ,Set Enable Bit 216" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SEB215 ,Set Enable Bit 215" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SEB214 ,Set Enable Bit 214" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SEB213 ,Set Enable Bit 213" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SEB212 ,Set Enable Bit 212" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SEB211 ,Set Enable Bit 211" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SEB210 ,Set Enable Bit 210" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SEB209 ,Set Enable Bit 209" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SEB208 ,Set Enable Bit 208" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SEB207 ,Set Enable Bit 207" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SEB206 ,Set Enable Bit 206" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SEB205 ,Set Enable Bit 205" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SEB204 ,Set Enable Bit 204" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SEB203 ,Set Enable Bit 203" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SEB202 ,Set Enable Bit 202" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SEB201 ,Set Enable Bit 201" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SEB200 ,Set Enable Bit 200" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SEB199 ,Set Enable Bit 199" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SEB198 ,Set Enable Bit 198" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SEB197 ,Set Enable Bit 197" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SEB196 ,Set Enable Bit 196" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SEB195 ,Set Enable Bit 195" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SEB194 ,Set Enable Bit 194" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SEB193 ,Set Enable Bit 193" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SEB192 ,Set Enable Bit 192" "Disabled,Enabled"
|
|
group.long 0x111C++0x03
|
|
line.long 0x0 "GICD_ISENABLER7,Interrupt Set Enable Register 7"
|
|
bitfld.long 0x00 31. " SEB255 ,Set Enable Bit 255" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SEB254 ,Set Enable Bit 254" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SEB253 ,Set Enable Bit 253" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SEB252 ,Set Enable Bit 252" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SEB251 ,Set Enable Bit 251" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " SEB250 ,Set Enable Bit 250" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SEB249 ,Set Enable Bit 249" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " SEB248 ,Set Enable Bit 248" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SEB247 ,Set Enable Bit 247" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SEB246 ,Set Enable Bit 246" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SEB245 ,Set Enable Bit 245" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SEB244 ,Set Enable Bit 244" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SEB243 ,Set Enable Bit 243" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SEB242 ,Set Enable Bit 242" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SEB241 ,Set Enable Bit 241" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SEB240 ,Set Enable Bit 240" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SEB239 ,Set Enable Bit 239" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SEB238 ,Set Enable Bit 238" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SEB237 ,Set Enable Bit 237" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SEB236 ,Set Enable Bit 236" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SEB235 ,Set Enable Bit 235" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SEB234 ,Set Enable Bit 234" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SEB233 ,Set Enable Bit 233" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SEB232 ,Set Enable Bit 232" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SEB231 ,Set Enable Bit 231" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SEB230 ,Set Enable Bit 230" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SEB229 ,Set Enable Bit 229" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SEB228 ,Set Enable Bit 228" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SEB227 ,Set Enable Bit 227" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SEB226 ,Set Enable Bit 226" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SEB225 ,Set Enable Bit 225" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SEB224 ,Set Enable Bit 224" "Disabled,Enabled"
|
|
group.long 0x1120++0x03
|
|
line.long 0x0 "GICD_ISENABLER8,Interrupt Set Enable Register 8"
|
|
bitfld.long 0x00 31. " SEB287 ,Set Enable Bit 287" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SEB286 ,Set Enable Bit 286" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SEB285 ,Set Enable Bit 285" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SEB284 ,Set Enable Bit 284" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SEB283 ,Set Enable Bit 283" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " SEB282 ,Set Enable Bit 282" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SEB281 ,Set Enable Bit 281" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " SEB280 ,Set Enable Bit 280" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SEB279 ,Set Enable Bit 279" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SEB278 ,Set Enable Bit 278" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SEB277 ,Set Enable Bit 277" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SEB276 ,Set Enable Bit 276" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SEB275 ,Set Enable Bit 275" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SEB274 ,Set Enable Bit 274" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SEB273 ,Set Enable Bit 273" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SEB272 ,Set Enable Bit 272" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SEB271 ,Set Enable Bit 271" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SEB270 ,Set Enable Bit 270" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SEB269 ,Set Enable Bit 269" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SEB268 ,Set Enable Bit 268" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SEB267 ,Set Enable Bit 267" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SEB266 ,Set Enable Bit 266" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SEB265 ,Set Enable Bit 265" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SEB264 ,Set Enable Bit 264" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SEB263 ,Set Enable Bit 263" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SEB262 ,Set Enable Bit 262" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SEB261 ,Set Enable Bit 261" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SEB260 ,Set Enable Bit 260" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SEB259 ,Set Enable Bit 259" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SEB258 ,Set Enable Bit 258" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SEB257 ,Set Enable Bit 257" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SEB256 ,Set Enable Bit 256" "Disabled,Enabled"
|
|
group.long 0x1124++0x03
|
|
line.long 0x0 "GICD_ISENABLER9,Interrupt Set Enable Register 9"
|
|
bitfld.long 0x00 31. " SEB319 ,Set Enable Bit 319" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SEB318 ,Set Enable Bit 318" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SEB317 ,Set Enable Bit 317" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SEB316 ,Set Enable Bit 316" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SEB315 ,Set Enable Bit 315" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " SEB314 ,Set Enable Bit 314" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SEB313 ,Set Enable Bit 313" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " SEB312 ,Set Enable Bit 312" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SEB311 ,Set Enable Bit 311" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SEB310 ,Set Enable Bit 310" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SEB309 ,Set Enable Bit 309" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SEB308 ,Set Enable Bit 308" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SEB307 ,Set Enable Bit 307" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SEB306 ,Set Enable Bit 306" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SEB305 ,Set Enable Bit 305" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SEB304 ,Set Enable Bit 304" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SEB303 ,Set Enable Bit 303" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SEB302 ,Set Enable Bit 302" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SEB301 ,Set Enable Bit 301" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SEB300 ,Set Enable Bit 300" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SEB299 ,Set Enable Bit 299" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SEB298 ,Set Enable Bit 298" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SEB297 ,Set Enable Bit 297" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SEB296 ,Set Enable Bit 296" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SEB295 ,Set Enable Bit 295" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SEB294 ,Set Enable Bit 294" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SEB293 ,Set Enable Bit 293" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SEB292 ,Set Enable Bit 292" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SEB291 ,Set Enable Bit 291" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SEB290 ,Set Enable Bit 290" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SEB289 ,Set Enable Bit 289" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SEB288 ,Set Enable Bit 288" "Disabled,Enabled"
|
|
group.long 0x1128++0x03
|
|
line.long 0x0 "GICD_ISENABLER10,Interrupt Set Enable Register 10"
|
|
bitfld.long 0x00 31. " SEB351 ,Set Enable Bit 351" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SEB350 ,Set Enable Bit 350" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SEB349 ,Set Enable Bit 349" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SEB348 ,Set Enable Bit 348" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SEB347 ,Set Enable Bit 347" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " SEB346 ,Set Enable Bit 346" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SEB345 ,Set Enable Bit 345" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " SEB344 ,Set Enable Bit 344" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SEB343 ,Set Enable Bit 343" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SEB342 ,Set Enable Bit 342" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SEB341 ,Set Enable Bit 341" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SEB340 ,Set Enable Bit 340" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SEB339 ,Set Enable Bit 339" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SEB338 ,Set Enable Bit 338" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SEB337 ,Set Enable Bit 337" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SEB336 ,Set Enable Bit 336" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SEB335 ,Set Enable Bit 335" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SEB334 ,Set Enable Bit 334" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SEB333 ,Set Enable Bit 333" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SEB332 ,Set Enable Bit 332" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SEB331 ,Set Enable Bit 331" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SEB330 ,Set Enable Bit 330" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SEB329 ,Set Enable Bit 329" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SEB328 ,Set Enable Bit 328" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SEB327 ,Set Enable Bit 327" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SEB326 ,Set Enable Bit 326" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SEB325 ,Set Enable Bit 325" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SEB324 ,Set Enable Bit 324" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SEB323 ,Set Enable Bit 323" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SEB322 ,Set Enable Bit 322" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SEB321 ,Set Enable Bit 321" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SEB320 ,Set Enable Bit 320" "Disabled,Enabled"
|
|
group.long 0x112c++0x03
|
|
line.long 0x0 "GICD_ISENABLER11,Interrupt Set Enable Register 11"
|
|
bitfld.long 0x00 31. " SEB383 ,Set Enable Bit 383" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SEB382 ,Set Enable Bit 382" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SEB381 ,Set Enable Bit 381" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SEB380 ,Set Enable Bit 380" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SEB379 ,Set Enable Bit 379" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " SEB378 ,Set Enable Bit 378" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SEB377 ,Set Enable Bit 377" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " SEB376 ,Set Enable Bit 376" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SEB375 ,Set Enable Bit 375" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SEB374 ,Set Enable Bit 374" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SEB373 ,Set Enable Bit 373" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SEB372 ,Set Enable Bit 372" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SEB371 ,Set Enable Bit 371" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SEB370 ,Set Enable Bit 370" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SEB369 ,Set Enable Bit 369" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SEB368 ,Set Enable Bit 368" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SEB367 ,Set Enable Bit 367" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SEB366 ,Set Enable Bit 366" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SEB365 ,Set Enable Bit 365" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SEB364 ,Set Enable Bit 364" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SEB363 ,Set Enable Bit 363" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SEB362 ,Set Enable Bit 362" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SEB361 ,Set Enable Bit 361" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SEB360 ,Set Enable Bit 360" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SEB359 ,Set Enable Bit 359" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SEB358 ,Set Enable Bit 358" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SEB357 ,Set Enable Bit 357" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SEB356 ,Set Enable Bit 356" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SEB355 ,Set Enable Bit 355" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SEB354 ,Set Enable Bit 354" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SEB353 ,Set Enable Bit 353" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SEB352 ,Set Enable Bit 352" "Disabled,Enabled"
|
|
group.long 0x1130++0x03
|
|
line.long 0x0 "GICD_ISENABLER12,Interrupt Set Enable Register 12"
|
|
bitfld.long 0x00 31. " SEB415 ,Set Enable Bit 415" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SEB414 ,Set Enable Bit 414" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SEB413 ,Set Enable Bit 413" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SEB412 ,Set Enable Bit 412" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SEB411 ,Set Enable Bit 411" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " SEB410 ,Set Enable Bit 410" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SEB409 ,Set Enable Bit 409" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " SEB408 ,Set Enable Bit 408" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SEB407 ,Set Enable Bit 407" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SEB406 ,Set Enable Bit 406" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SEB405 ,Set Enable Bit 405" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SEB404 ,Set Enable Bit 404" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SEB403 ,Set Enable Bit 403" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SEB402 ,Set Enable Bit 402" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SEB401 ,Set Enable Bit 401" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SEB400 ,Set Enable Bit 400" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SEB399 ,Set Enable Bit 399" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SEB398 ,Set Enable Bit 398" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SEB397 ,Set Enable Bit 397" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SEB396 ,Set Enable Bit 396" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SEB395 ,Set Enable Bit 395" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SEB394 ,Set Enable Bit 394" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SEB393 ,Set Enable Bit 393" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SEB392 ,Set Enable Bit 392" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SEB391 ,Set Enable Bit 391" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SEB390 ,Set Enable Bit 390" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SEB389 ,Set Enable Bit 389" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SEB388 ,Set Enable Bit 388" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SEB387 ,Set Enable Bit 387" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SEB386 ,Set Enable Bit 386" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SEB385 ,Set Enable Bit 385" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SEB384 ,Set Enable Bit 384" "Disabled,Enabled"
|
|
group.long 0x1134++0x03
|
|
line.long 0x0 "GICD_ISENABLER13,Interrupt Set Enable Register 13"
|
|
bitfld.long 0x00 31. " SEB447 ,Set Enable Bit 447" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SEB446 ,Set Enable Bit 446" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SEB445 ,Set Enable Bit 445" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SEB444 ,Set Enable Bit 444" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SEB443 ,Set Enable Bit 443" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " SEB442 ,Set Enable Bit 442" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SEB441 ,Set Enable Bit 441" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " SEB440 ,Set Enable Bit 440" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SEB439 ,Set Enable Bit 439" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SEB438 ,Set Enable Bit 438" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SEB437 ,Set Enable Bit 437" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SEB436 ,Set Enable Bit 436" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SEB435 ,Set Enable Bit 435" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SEB434 ,Set Enable Bit 434" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SEB433 ,Set Enable Bit 433" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SEB432 ,Set Enable Bit 432" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SEB431 ,Set Enable Bit 431" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SEB430 ,Set Enable Bit 430" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SEB429 ,Set Enable Bit 429" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SEB428 ,Set Enable Bit 428" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SEB427 ,Set Enable Bit 427" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SEB426 ,Set Enable Bit 426" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SEB425 ,Set Enable Bit 425" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SEB424 ,Set Enable Bit 424" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SEB423 ,Set Enable Bit 423" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SEB422 ,Set Enable Bit 422" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SEB421 ,Set Enable Bit 421" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SEB420 ,Set Enable Bit 420" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SEB419 ,Set Enable Bit 419" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SEB418 ,Set Enable Bit 418" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SEB417 ,Set Enable Bit 417" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SEB416 ,Set Enable Bit 416" "Disabled,Enabled"
|
|
group.long 0x1138++0x03
|
|
line.long 0x0 "GICD_ISENABLER14,Interrupt Set Enable Register 14"
|
|
bitfld.long 0x00 31. " SEB479 ,Set Enable Bit 479" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SEB478 ,Set Enable Bit 478" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SEB477 ,Set Enable Bit 477" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SEB476 ,Set Enable Bit 476" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SEB475 ,Set Enable Bit 475" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " SEB474 ,Set Enable Bit 474" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SEB473 ,Set Enable Bit 473" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " SEB472 ,Set Enable Bit 472" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SEB471 ,Set Enable Bit 471" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SEB470 ,Set Enable Bit 470" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SEB469 ,Set Enable Bit 469" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SEB468 ,Set Enable Bit 468" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SEB467 ,Set Enable Bit 467" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SEB466 ,Set Enable Bit 466" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SEB465 ,Set Enable Bit 465" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SEB464 ,Set Enable Bit 464" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SEB463 ,Set Enable Bit 463" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SEB462 ,Set Enable Bit 462" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SEB461 ,Set Enable Bit 461" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SEB460 ,Set Enable Bit 460" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SEB459 ,Set Enable Bit 459" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SEB458 ,Set Enable Bit 458" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SEB457 ,Set Enable Bit 457" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SEB456 ,Set Enable Bit 456" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SEB455 ,Set Enable Bit 455" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SEB454 ,Set Enable Bit 454" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SEB453 ,Set Enable Bit 453" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SEB452 ,Set Enable Bit 452" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SEB451 ,Set Enable Bit 451" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SEB450 ,Set Enable Bit 450" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SEB449 ,Set Enable Bit 449" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SEB448 ,Set Enable Bit 448" "Disabled,Enabled"
|
|
group.long 0x113c++0x03
|
|
line.long 0x0 "GICD_ISENABLER15,Interrupt Set Enable Register 15"
|
|
bitfld.long 0x00 31. " SEB511 ,Set Enable Bit 511" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SEB510 ,Set Enable Bit 510" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SEB509 ,Set Enable Bit 509" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SEB508 ,Set Enable Bit 508" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SEB507 ,Set Enable Bit 507" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " SEB506 ,Set Enable Bit 506" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SEB505 ,Set Enable Bit 505" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " SEB504 ,Set Enable Bit 504" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SEB503 ,Set Enable Bit 503" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SEB502 ,Set Enable Bit 502" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SEB501 ,Set Enable Bit 501" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SEB500 ,Set Enable Bit 500" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SEB499 ,Set Enable Bit 499" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SEB498 ,Set Enable Bit 498" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SEB497 ,Set Enable Bit 497" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SEB496 ,Set Enable Bit 496" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SEB495 ,Set Enable Bit 495" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SEB494 ,Set Enable Bit 494" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SEB493 ,Set Enable Bit 493" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SEB492 ,Set Enable Bit 492" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SEB491 ,Set Enable Bit 491" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SEB490 ,Set Enable Bit 490" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SEB489 ,Set Enable Bit 489" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SEB488 ,Set Enable Bit 488" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SEB487 ,Set Enable Bit 487" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SEB486 ,Set Enable Bit 486" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SEB485 ,Set Enable Bit 485" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SEB484 ,Set Enable Bit 484" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SEB483 ,Set Enable Bit 483" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SEB482 ,Set Enable Bit 482" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SEB481 ,Set Enable Bit 481" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SEB480 ,Set Enable Bit 480" "Disabled,Enabled"
|
|
textline " "
|
|
tree.end
|
|
tree "Clear-Enable Registers"
|
|
group.long 0x1180++0x03
|
|
line.long 0x0 "GICD_ICENABLER0,Interrupt Clear Enable Register 0"
|
|
eventfld.long 0x00 31. " CEB31 ,Clear Enable Bit 31" "Disabled,Enabled"
|
|
eventfld.long 0x00 30. " CEB30 ,Clear Enable Bit 30" "Disabled,Enabled"
|
|
eventfld.long 0x00 29. " CEB29 ,Clear Enable Bit 29" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 28. " CEB28 ,Clear Enable Bit 28" "Disabled,Enabled"
|
|
eventfld.long 0x00 27. " CEB27 ,Clear Enable Bit 27" "Disabled,Enabled"
|
|
eventfld.long 0x00 26. " CEB26 ,Clear Enable Bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 25. " CEB25 ,Clear Enable Bit 25" "Disabled,Enabled"
|
|
eventfld.long 0x00 24. " CEB24 ,Clear Enable Bit 24" "Disabled,Enabled"
|
|
eventfld.long 0x00 23. " CEB23 ,Clear Enable Bit 23" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 22. " CEB22 ,Clear Enable Bit 22" "Disabled,Enabled"
|
|
eventfld.long 0x00 21. " CEB21 ,Clear Enable Bit 21" "Disabled,Enabled"
|
|
eventfld.long 0x00 20. " CEB20 ,Clear Enable Bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 19. " CEB19 ,Clear Enable Bit 19" "Disabled,Enabled"
|
|
eventfld.long 0x00 18. " CEB18 ,Clear Enable Bit 18" "Disabled,Enabled"
|
|
eventfld.long 0x00 17. " CEB17 ,Clear Enable Bit 17" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CEB16 ,Clear Enable Bit 16" "Disabled,Enabled"
|
|
eventfld.long 0x00 15. " CEB15 ,Clear Enable Bit 15" "Disabled,Enabled"
|
|
eventfld.long 0x00 14. " CEB14 ,Clear Enable Bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 13. " CEB13 ,Clear Enable Bit 13" "Disabled,Enabled"
|
|
eventfld.long 0x00 12. " CEB12 ,Clear Enable Bit 12" "Disabled,Enabled"
|
|
eventfld.long 0x00 11. " CEB11 ,Clear Enable Bit 11" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 10. " CEB10 ,Clear Enable Bit 10" "Disabled,Enabled"
|
|
eventfld.long 0x00 9. " CEB9 ,Clear Enable Bit 9" "Disabled,Enabled"
|
|
eventfld.long 0x00 8. " CEB8 ,Clear Enable Bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CEB7 ,Clear Enable Bit 7" "Disabled,Enabled"
|
|
eventfld.long 0x00 6. " CEB6 ,Clear Enable Bit 6" "Disabled,Enabled"
|
|
eventfld.long 0x00 5. " CEB5 ,Clear Enable Bit 5" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CEB4 ,Clear Enable Bit 4" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " CEB3 ,Clear Enable Bit 3" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " CEB2 ,Clear Enable Bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CEB1 ,Clear Enable Bit 1" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " CEB0 ,Clear Enable Bit 0" "Disabled,Enabled"
|
|
group.long 0x1184++0x03
|
|
line.long 0x0 "GICD_ICENABLER1,Interrupt Clear Enable Register 1"
|
|
eventfld.long 0x00 31. " CEB63 ,Clear Enable Bit 63" "Disabled,Enabled"
|
|
eventfld.long 0x00 30. " CEB62 ,Clear Enable Bit 62" "Disabled,Enabled"
|
|
eventfld.long 0x00 29. " CEB61 ,Clear Enable Bit 61" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 28. " CEB60 ,Clear Enable Bit 60" "Disabled,Enabled"
|
|
eventfld.long 0x00 27. " CEB59 ,Clear Enable Bit 59" "Disabled,Enabled"
|
|
eventfld.long 0x00 26. " CEB58 ,Clear Enable Bit 58" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 25. " CEB57 ,Clear Enable Bit 57" "Disabled,Enabled"
|
|
eventfld.long 0x00 24. " CEB56 ,Clear Enable Bit 56" "Disabled,Enabled"
|
|
eventfld.long 0x00 23. " CEB55 ,Clear Enable Bit 55" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 22. " CEB54 ,Clear Enable Bit 54" "Disabled,Enabled"
|
|
eventfld.long 0x00 21. " CEB53 ,Clear Enable Bit 53" "Disabled,Enabled"
|
|
eventfld.long 0x00 20. " CEB52 ,Clear Enable Bit 52" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 19. " CEB51 ,Clear Enable Bit 51" "Disabled,Enabled"
|
|
eventfld.long 0x00 18. " CEB50 ,Clear Enable Bit 50" "Disabled,Enabled"
|
|
eventfld.long 0x00 17. " CEB49 ,Clear Enable Bit 49" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CEB48 ,Clear Enable Bit 48" "Disabled,Enabled"
|
|
eventfld.long 0x00 15. " CEB47 ,Clear Enable Bit 47" "Disabled,Enabled"
|
|
eventfld.long 0x00 14. " CEB46 ,Clear Enable Bit 46" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 13. " CEB45 ,Clear Enable Bit 45" "Disabled,Enabled"
|
|
eventfld.long 0x00 12. " CEB44 ,Clear Enable Bit 44" "Disabled,Enabled"
|
|
eventfld.long 0x00 11. " CEB43 ,Clear Enable Bit 43" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 10. " CEB42 ,Clear Enable Bit 42" "Disabled,Enabled"
|
|
eventfld.long 0x00 9. " CEB41 ,Clear Enable Bit 41" "Disabled,Enabled"
|
|
eventfld.long 0x00 8. " CEB40 ,Clear Enable Bit 40" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CEB39 ,Clear Enable Bit 39" "Disabled,Enabled"
|
|
eventfld.long 0x00 6. " CEB38 ,Clear Enable Bit 38" "Disabled,Enabled"
|
|
eventfld.long 0x00 5. " CEB37 ,Clear Enable Bit 37" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CEB36 ,Clear Enable Bit 36" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " CEB35 ,Clear Enable Bit 35" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " CEB34 ,Clear Enable Bit 34" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CEB33 ,Clear Enable Bit 33" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " CEB32 ,Clear Enable Bit 32" "Disabled,Enabled"
|
|
group.long 0x1188++0x03
|
|
line.long 0x0 "GICD_ICENABLER2,Interrupt Clear Enable Register 2"
|
|
eventfld.long 0x00 31. " CEB95 ,Clear Enable Bit 95" "Disabled,Enabled"
|
|
eventfld.long 0x00 30. " CEB94 ,Clear Enable Bit 94" "Disabled,Enabled"
|
|
eventfld.long 0x00 29. " CEB93 ,Clear Enable Bit 93" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 28. " CEB92 ,Clear Enable Bit 92" "Disabled,Enabled"
|
|
eventfld.long 0x00 27. " CEB91 ,Clear Enable Bit 91" "Disabled,Enabled"
|
|
eventfld.long 0x00 26. " CEB90 ,Clear Enable Bit 90" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 25. " CEB89 ,Clear Enable Bit 89" "Disabled,Enabled"
|
|
eventfld.long 0x00 24. " CEB88 ,Clear Enable Bit 88" "Disabled,Enabled"
|
|
eventfld.long 0x00 23. " CEB87 ,Clear Enable Bit 87" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 22. " CEB86 ,Clear Enable Bit 86" "Disabled,Enabled"
|
|
eventfld.long 0x00 21. " CEB85 ,Clear Enable Bit 85" "Disabled,Enabled"
|
|
eventfld.long 0x00 20. " CEB84 ,Clear Enable Bit 84" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 19. " CEB83 ,Clear Enable Bit 83" "Disabled,Enabled"
|
|
eventfld.long 0x00 18. " CEB82 ,Clear Enable Bit 82" "Disabled,Enabled"
|
|
eventfld.long 0x00 17. " CEB81 ,Clear Enable Bit 81" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CEB80 ,Clear Enable Bit 80" "Disabled,Enabled"
|
|
eventfld.long 0x00 15. " CEB79 ,Clear Enable Bit 79" "Disabled,Enabled"
|
|
eventfld.long 0x00 14. " CEB78 ,Clear Enable Bit 78" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 13. " CEB77 ,Clear Enable Bit 77" "Disabled,Enabled"
|
|
eventfld.long 0x00 12. " CEB76 ,Clear Enable Bit 76" "Disabled,Enabled"
|
|
eventfld.long 0x00 11. " CEB75 ,Clear Enable Bit 75" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 10. " CEB74 ,Clear Enable Bit 74" "Disabled,Enabled"
|
|
eventfld.long 0x00 9. " CEB73 ,Clear Enable Bit 73" "Disabled,Enabled"
|
|
eventfld.long 0x00 8. " CEB72 ,Clear Enable Bit 72" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CEB71 ,Clear Enable Bit 71" "Disabled,Enabled"
|
|
eventfld.long 0x00 6. " CEB70 ,Clear Enable Bit 70" "Disabled,Enabled"
|
|
eventfld.long 0x00 5. " CEB69 ,Clear Enable Bit 69" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CEB68 ,Clear Enable Bit 68" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " CEB67 ,Clear Enable Bit 67" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " CEB66 ,Clear Enable Bit 66" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CEB65 ,Clear Enable Bit 65" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " CEB64 ,Clear Enable Bit 64" "Disabled,Enabled"
|
|
group.long 0x118C++0x03
|
|
line.long 0x0 "GICD_ICENABLER3,Interrupt Clear Enable Register 3"
|
|
eventfld.long 0x00 31. " CEB127 ,Clear Enable Bit 127" "Disabled,Enabled"
|
|
eventfld.long 0x00 30. " CEB126 ,Clear Enable Bit 126" "Disabled,Enabled"
|
|
eventfld.long 0x00 29. " CEB125 ,Clear Enable Bit 125" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 28. " CEB124 ,Clear Enable Bit 124" "Disabled,Enabled"
|
|
eventfld.long 0x00 27. " CEB123 ,Clear Enable Bit 123" "Disabled,Enabled"
|
|
eventfld.long 0x00 26. " CEB122 ,Clear Enable Bit 122" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 25. " CEB121 ,Clear Enable Bit 121" "Disabled,Enabled"
|
|
eventfld.long 0x00 24. " CEB120 ,Clear Enable Bit 120" "Disabled,Enabled"
|
|
eventfld.long 0x00 23. " CEB119 ,Clear Enable Bit 119" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 22. " CEB118 ,Clear Enable Bit 118" "Disabled,Enabled"
|
|
eventfld.long 0x00 21. " CEB117 ,Clear Enable Bit 117" "Disabled,Enabled"
|
|
eventfld.long 0x00 20. " CEB116 ,Clear Enable Bit 116" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 19. " CEB115 ,Clear Enable Bit 115" "Disabled,Enabled"
|
|
eventfld.long 0x00 18. " CEB114 ,Clear Enable Bit 114" "Disabled,Enabled"
|
|
eventfld.long 0x00 17. " CEB113 ,Clear Enable Bit 113" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CEB112 ,Clear Enable Bit 112" "Disabled,Enabled"
|
|
eventfld.long 0x00 15. " CEB111 ,Clear Enable Bit 111" "Disabled,Enabled"
|
|
eventfld.long 0x00 14. " CEB110 ,Clear Enable Bit 110" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 13. " CEB109 ,Clear Enable Bit 109" "Disabled,Enabled"
|
|
eventfld.long 0x00 12. " CEB108 ,Clear Enable Bit 108" "Disabled,Enabled"
|
|
eventfld.long 0x00 11. " CEB107 ,Clear Enable Bit 107" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 10. " CEB106 ,Clear Enable Bit 106" "Disabled,Enabled"
|
|
eventfld.long 0x00 9. " CEB105 ,Clear Enable Bit 105" "Disabled,Enabled"
|
|
eventfld.long 0x00 8. " CEB104 ,Clear Enable Bit 104" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CEB103 ,Clear Enable Bit 103" "Disabled,Enabled"
|
|
eventfld.long 0x00 6. " CEB102 ,Clear Enable Bit 102" "Disabled,Enabled"
|
|
eventfld.long 0x00 5. " CEB101 ,Clear Enable Bit 101" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CEB100 ,Clear Enable Bit 100" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " CEB99 ,Clear Enable Bit 99" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " CEB98 ,Clear Enable Bit 98" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CEB97 ,Clear Enable Bit 97" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " CEB96 ,Clear Enable Bit 96" "Disabled,Enabled"
|
|
group.long 0x1190++0x03
|
|
line.long 0x0 "GICD_ICENABLER4,Interrupt Clear Enable Register 4"
|
|
eventfld.long 0x00 31. " CEB159 ,Clear Enable Bit 159" "Disabled,Enabled"
|
|
eventfld.long 0x00 30. " CEB158 ,Clear Enable Bit 158" "Disabled,Enabled"
|
|
eventfld.long 0x00 29. " CEB157 ,Clear Enable Bit 157" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 28. " CEB156 ,Clear Enable Bit 156" "Disabled,Enabled"
|
|
eventfld.long 0x00 27. " CEB155 ,Clear Enable Bit 155" "Disabled,Enabled"
|
|
eventfld.long 0x00 26. " CEB154 ,Clear Enable Bit 154" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 25. " CEB153 ,Clear Enable Bit 153" "Disabled,Enabled"
|
|
eventfld.long 0x00 24. " CEB152 ,Clear Enable Bit 152" "Disabled,Enabled"
|
|
eventfld.long 0x00 23. " CEB151 ,Clear Enable Bit 151" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 22. " CEB150 ,Clear Enable Bit 150" "Disabled,Enabled"
|
|
eventfld.long 0x00 21. " CEB149 ,Clear Enable Bit 149" "Disabled,Enabled"
|
|
eventfld.long 0x00 20. " CEB148 ,Clear Enable Bit 148" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 19. " CEB147 ,Clear Enable Bit 147" "Disabled,Enabled"
|
|
eventfld.long 0x00 18. " CEB146 ,Clear Enable Bit 146" "Disabled,Enabled"
|
|
eventfld.long 0x00 17. " CEB145 ,Clear Enable Bit 145" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CEB144 ,Clear Enable Bit 144" "Disabled,Enabled"
|
|
eventfld.long 0x00 15. " CEB143 ,Clear Enable Bit 143" "Disabled,Enabled"
|
|
eventfld.long 0x00 14. " CEB142 ,Clear Enable Bit 142" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 13. " CEB141 ,Clear Enable Bit 141" "Disabled,Enabled"
|
|
eventfld.long 0x00 12. " CEB140 ,Clear Enable Bit 140" "Disabled,Enabled"
|
|
eventfld.long 0x00 11. " CEB139 ,Clear Enable Bit 139" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 10. " CEB138 ,Clear Enable Bit 138" "Disabled,Enabled"
|
|
eventfld.long 0x00 9. " CEB137 ,Clear Enable Bit 137" "Disabled,Enabled"
|
|
eventfld.long 0x00 8. " CEB136 ,Clear Enable Bit 136" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CEB135 ,Clear Enable Bit 135" "Disabled,Enabled"
|
|
eventfld.long 0x00 6. " CEB134 ,Clear Enable Bit 134" "Disabled,Enabled"
|
|
eventfld.long 0x00 5. " CEB133 ,Clear Enable Bit 133" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CEB132 ,Clear Enable Bit 132" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " CEB131 ,Clear Enable Bit 131" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " CEB130 ,Clear Enable Bit 130" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CEB129 ,Clear Enable Bit 129" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " CEB128 ,Clear Enable Bit 128" "Disabled,Enabled"
|
|
group.long 0x1194++0x03
|
|
line.long 0x0 "GICD_ICENABLER5,Interrupt Clear Enable Register 5"
|
|
eventfld.long 0x00 31. " CEB191 ,Clear Enable Bit 191" "Disabled,Enabled"
|
|
eventfld.long 0x00 30. " CEB190 ,Clear Enable Bit 190" "Disabled,Enabled"
|
|
eventfld.long 0x00 29. " CEB189 ,Clear Enable Bit 189" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 28. " CEB188 ,Clear Enable Bit 188" "Disabled,Enabled"
|
|
eventfld.long 0x00 27. " CEB187 ,Clear Enable Bit 187" "Disabled,Enabled"
|
|
eventfld.long 0x00 26. " CEB186 ,Clear Enable Bit 186" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 25. " CEB185 ,Clear Enable Bit 185" "Disabled,Enabled"
|
|
eventfld.long 0x00 24. " CEB184 ,Clear Enable Bit 184" "Disabled,Enabled"
|
|
eventfld.long 0x00 23. " CEB183 ,Clear Enable Bit 183" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 22. " CEB182 ,Clear Enable Bit 182" "Disabled,Enabled"
|
|
eventfld.long 0x00 21. " CEB181 ,Clear Enable Bit 181" "Disabled,Enabled"
|
|
eventfld.long 0x00 20. " CEB180 ,Clear Enable Bit 180" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 19. " CEB179 ,Clear Enable Bit 179" "Disabled,Enabled"
|
|
eventfld.long 0x00 18. " CEB178 ,Clear Enable Bit 178" "Disabled,Enabled"
|
|
eventfld.long 0x00 17. " CEB177 ,Clear Enable Bit 177" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CEB176 ,Clear Enable Bit 176" "Disabled,Enabled"
|
|
eventfld.long 0x00 15. " CEB175 ,Clear Enable Bit 175" "Disabled,Enabled"
|
|
eventfld.long 0x00 14. " CEB174 ,Clear Enable Bit 174" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 13. " CEB173 ,Clear Enable Bit 173" "Disabled,Enabled"
|
|
eventfld.long 0x00 12. " CEB172 ,Clear Enable Bit 172" "Disabled,Enabled"
|
|
eventfld.long 0x00 11. " CEB171 ,Clear Enable Bit 171" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 10. " CEB170 ,Clear Enable Bit 170" "Disabled,Enabled"
|
|
eventfld.long 0x00 9. " CEB169 ,Clear Enable Bit 169" "Disabled,Enabled"
|
|
eventfld.long 0x00 8. " CEB168 ,Clear Enable Bit 168" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CEB167 ,Clear Enable Bit 167" "Disabled,Enabled"
|
|
eventfld.long 0x00 6. " CEB166 ,Clear Enable Bit 166" "Disabled,Enabled"
|
|
eventfld.long 0x00 5. " CEB165 ,Clear Enable Bit 165" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CEB164 ,Clear Enable Bit 164" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " CEB163 ,Clear Enable Bit 163" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " CEB162 ,Clear Enable Bit 162" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CEB161 ,Clear Enable Bit 161" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " CEB160 ,Clear Enable Bit 160" "Disabled,Enabled"
|
|
group.long 0x1198++0x03
|
|
line.long 0x0 "GICD_ICENABLER6,Interrupt Clear Enable Register 6"
|
|
eventfld.long 0x00 31. " CEB223 ,Clear Enable Bit 223" "Disabled,Enabled"
|
|
eventfld.long 0x00 30. " CEB222 ,Clear Enable Bit 222" "Disabled,Enabled"
|
|
eventfld.long 0x00 29. " CEB221 ,Clear Enable Bit 221" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 28. " CEB220 ,Clear Enable Bit 220" "Disabled,Enabled"
|
|
eventfld.long 0x00 27. " CEB219 ,Clear Enable Bit 219" "Disabled,Enabled"
|
|
eventfld.long 0x00 26. " CEB218 ,Clear Enable Bit 218" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 25. " CEB217 ,Clear Enable Bit 217" "Disabled,Enabled"
|
|
eventfld.long 0x00 24. " CEB216 ,Clear Enable Bit 216" "Disabled,Enabled"
|
|
eventfld.long 0x00 23. " CEB215 ,Clear Enable Bit 215" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 22. " CEB214 ,Clear Enable Bit 214" "Disabled,Enabled"
|
|
eventfld.long 0x00 21. " CEB213 ,Clear Enable Bit 213" "Disabled,Enabled"
|
|
eventfld.long 0x00 20. " CEB212 ,Clear Enable Bit 212" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 19. " CEB211 ,Clear Enable Bit 211" "Disabled,Enabled"
|
|
eventfld.long 0x00 18. " CEB210 ,Clear Enable Bit 210" "Disabled,Enabled"
|
|
eventfld.long 0x00 17. " CEB209 ,Clear Enable Bit 209" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CEB208 ,Clear Enable Bit 208" "Disabled,Enabled"
|
|
eventfld.long 0x00 15. " CEB207 ,Clear Enable Bit 207" "Disabled,Enabled"
|
|
eventfld.long 0x00 14. " CEB206 ,Clear Enable Bit 206" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 13. " CEB205 ,Clear Enable Bit 205" "Disabled,Enabled"
|
|
eventfld.long 0x00 12. " CEB204 ,Clear Enable Bit 204" "Disabled,Enabled"
|
|
eventfld.long 0x00 11. " CEB203 ,Clear Enable Bit 203" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 10. " CEB202 ,Clear Enable Bit 202" "Disabled,Enabled"
|
|
eventfld.long 0x00 9. " CEB201 ,Clear Enable Bit 201" "Disabled,Enabled"
|
|
eventfld.long 0x00 8. " CEB200 ,Clear Enable Bit 200" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CEB199 ,Clear Enable Bit 199" "Disabled,Enabled"
|
|
eventfld.long 0x00 6. " CEB198 ,Clear Enable Bit 198" "Disabled,Enabled"
|
|
eventfld.long 0x00 5. " CEB197 ,Clear Enable Bit 197" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CEB196 ,Clear Enable Bit 196" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " CEB195 ,Clear Enable Bit 195" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " CEB194 ,Clear Enable Bit 194" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CEB193 ,Clear Enable Bit 193" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " CEB192 ,Clear Enable Bit 192" "Disabled,Enabled"
|
|
group.long 0x119C++0x03
|
|
line.long 0x0 "GICD_ICENABLER7,Interrupt Clear Enable Register 7"
|
|
eventfld.long 0x00 31. " CEB255 ,Clear Enable Bit 255" "Disabled,Enabled"
|
|
eventfld.long 0x00 30. " CEB254 ,Clear Enable Bit 254" "Disabled,Enabled"
|
|
eventfld.long 0x00 29. " CEB253 ,Clear Enable Bit 253" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 28. " CEB252 ,Clear Enable Bit 252" "Disabled,Enabled"
|
|
eventfld.long 0x00 27. " CEB251 ,Clear Enable Bit 251" "Disabled,Enabled"
|
|
eventfld.long 0x00 26. " CEB250 ,Clear Enable Bit 250" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 25. " CEB249 ,Clear Enable Bit 249" "Disabled,Enabled"
|
|
eventfld.long 0x00 24. " CEB248 ,Clear Enable Bit 248" "Disabled,Enabled"
|
|
eventfld.long 0x00 23. " CEB247 ,Clear Enable Bit 247" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 22. " CEB246 ,Clear Enable Bit 246" "Disabled,Enabled"
|
|
eventfld.long 0x00 21. " CEB245 ,Clear Enable Bit 245" "Disabled,Enabled"
|
|
eventfld.long 0x00 20. " CEB244 ,Clear Enable Bit 244" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 19. " CEB243 ,Clear Enable Bit 243" "Disabled,Enabled"
|
|
eventfld.long 0x00 18. " CEB242 ,Clear Enable Bit 242" "Disabled,Enabled"
|
|
eventfld.long 0x00 17. " CEB241 ,Clear Enable Bit 241" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CEB240 ,Clear Enable Bit 240" "Disabled,Enabled"
|
|
eventfld.long 0x00 15. " CEB239 ,Clear Enable Bit 239" "Disabled,Enabled"
|
|
eventfld.long 0x00 14. " CEB238 ,Clear Enable Bit 238" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 13. " CEB237 ,Clear Enable Bit 237" "Disabled,Enabled"
|
|
eventfld.long 0x00 12. " CEB236 ,Clear Enable Bit 236" "Disabled,Enabled"
|
|
eventfld.long 0x00 11. " CEB235 ,Clear Enable Bit 235" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 10. " CEB234 ,Clear Enable Bit 234" "Disabled,Enabled"
|
|
eventfld.long 0x00 9. " CEB233 ,Clear Enable Bit 233" "Disabled,Enabled"
|
|
eventfld.long 0x00 8. " CEB232 ,Clear Enable Bit 232" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CEB231 ,Clear Enable Bit 231" "Disabled,Enabled"
|
|
eventfld.long 0x00 6. " CEB230 ,Clear Enable Bit 230" "Disabled,Enabled"
|
|
eventfld.long 0x00 5. " CEB229 ,Clear Enable Bit 229" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CEB228 ,Clear Enable Bit 228" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " CEB227 ,Clear Enable Bit 227" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " CEB226 ,Clear Enable Bit 226" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CEB225 ,Clear Enable Bit 225" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " CEB224 ,Clear Enable Bit 224" "Disabled,Enabled"
|
|
group.long 0x11a0++0x03
|
|
line.long 0x0 "GICD_ICENABLER8,Interrupt Clear Enable Register 8"
|
|
eventfld.long 0x00 31. " CEB287 ,Clear Enable Bit 287" "Disabled,Enabled"
|
|
eventfld.long 0x00 30. " CEB286 ,Clear Enable Bit 286" "Disabled,Enabled"
|
|
eventfld.long 0x00 29. " CEB285 ,Clear Enable Bit 285" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 28. " CEB284 ,Clear Enable Bit 284" "Disabled,Enabled"
|
|
eventfld.long 0x00 27. " CEB283 ,Clear Enable Bit 283" "Disabled,Enabled"
|
|
eventfld.long 0x00 26. " CEB282 ,Clear Enable Bit 282" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 25. " CEB281 ,Clear Enable Bit 281" "Disabled,Enabled"
|
|
eventfld.long 0x00 24. " CEB280 ,Clear Enable Bit 280" "Disabled,Enabled"
|
|
eventfld.long 0x00 23. " CEB279 ,Clear Enable Bit 279" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 22. " CEB278 ,Clear Enable Bit 278" "Disabled,Enabled"
|
|
eventfld.long 0x00 21. " CEB277 ,Clear Enable Bit 277" "Disabled,Enabled"
|
|
eventfld.long 0x00 20. " CEB276 ,Clear Enable Bit 276" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 19. " CEB275 ,Clear Enable Bit 275" "Disabled,Enabled"
|
|
eventfld.long 0x00 18. " CEB274 ,Clear Enable Bit 274" "Disabled,Enabled"
|
|
eventfld.long 0x00 17. " CEB273 ,Clear Enable Bit 273" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CEB272 ,Clear Enable Bit 272" "Disabled,Enabled"
|
|
eventfld.long 0x00 15. " CEB271 ,Clear Enable Bit 271" "Disabled,Enabled"
|
|
eventfld.long 0x00 14. " CEB270 ,Clear Enable Bit 270" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 13. " CEB269 ,Clear Enable Bit 269" "Disabled,Enabled"
|
|
eventfld.long 0x00 12. " CEB268 ,Clear Enable Bit 268" "Disabled,Enabled"
|
|
eventfld.long 0x00 11. " CEB267 ,Clear Enable Bit 267" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 10. " CEB266 ,Clear Enable Bit 266" "Disabled,Enabled"
|
|
eventfld.long 0x00 9. " CEB265 ,Clear Enable Bit 265" "Disabled,Enabled"
|
|
eventfld.long 0x00 8. " CEB264 ,Clear Enable Bit 264" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CEB263 ,Clear Enable Bit 263" "Disabled,Enabled"
|
|
eventfld.long 0x00 6. " CEB262 ,Clear Enable Bit 262" "Disabled,Enabled"
|
|
eventfld.long 0x00 5. " CEB261 ,Clear Enable Bit 261" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CEB260 ,Clear Enable Bit 260" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " CEB259 ,Clear Enable Bit 259" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " CEB258 ,Clear Enable Bit 258" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CEB257 ,Clear Enable Bit 257" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " CEB256 ,Clear Enable Bit 256" "Disabled,Enabled"
|
|
group.long 0x11a4++0x03
|
|
line.long 0x0 "GICD_ICENABLER9,Interrupt Clear Enable Register 9"
|
|
eventfld.long 0x00 31. " CEB319 ,Clear Enable Bit 319" "Disabled,Enabled"
|
|
eventfld.long 0x00 30. " CEB318 ,Clear Enable Bit 318" "Disabled,Enabled"
|
|
eventfld.long 0x00 29. " CEB317 ,Clear Enable Bit 317" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 28. " CEB316 ,Clear Enable Bit 316" "Disabled,Enabled"
|
|
eventfld.long 0x00 27. " CEB315 ,Clear Enable Bit 315" "Disabled,Enabled"
|
|
eventfld.long 0x00 26. " CEB314 ,Clear Enable Bit 314" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 25. " CEB313 ,Clear Enable Bit 313" "Disabled,Enabled"
|
|
eventfld.long 0x00 24. " CEB312 ,Clear Enable Bit 312" "Disabled,Enabled"
|
|
eventfld.long 0x00 23. " CEB311 ,Clear Enable Bit 311" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 22. " CEB310 ,Clear Enable Bit 310" "Disabled,Enabled"
|
|
eventfld.long 0x00 21. " CEB309 ,Clear Enable Bit 309" "Disabled,Enabled"
|
|
eventfld.long 0x00 20. " CEB308 ,Clear Enable Bit 308" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 19. " CEB307 ,Clear Enable Bit 307" "Disabled,Enabled"
|
|
eventfld.long 0x00 18. " CEB306 ,Clear Enable Bit 306" "Disabled,Enabled"
|
|
eventfld.long 0x00 17. " CEB305 ,Clear Enable Bit 305" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CEB304 ,Clear Enable Bit 304" "Disabled,Enabled"
|
|
eventfld.long 0x00 15. " CEB303 ,Clear Enable Bit 303" "Disabled,Enabled"
|
|
eventfld.long 0x00 14. " CEB302 ,Clear Enable Bit 302" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 13. " CEB301 ,Clear Enable Bit 301" "Disabled,Enabled"
|
|
eventfld.long 0x00 12. " CEB300 ,Clear Enable Bit 300" "Disabled,Enabled"
|
|
eventfld.long 0x00 11. " CEB299 ,Clear Enable Bit 299" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 10. " CEB298 ,Clear Enable Bit 298" "Disabled,Enabled"
|
|
eventfld.long 0x00 9. " CEB297 ,Clear Enable Bit 297" "Disabled,Enabled"
|
|
eventfld.long 0x00 8. " CEB296 ,Clear Enable Bit 296" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CEB295 ,Clear Enable Bit 295" "Disabled,Enabled"
|
|
eventfld.long 0x00 6. " CEB294 ,Clear Enable Bit 294" "Disabled,Enabled"
|
|
eventfld.long 0x00 5. " CEB293 ,Clear Enable Bit 293" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CEB292 ,Clear Enable Bit 292" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " CEB291 ,Clear Enable Bit 291" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " CEB290 ,Clear Enable Bit 290" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CEB289 ,Clear Enable Bit 289" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " CEB288 ,Clear Enable Bit 288" "Disabled,Enabled"
|
|
group.long 0x11a8++0x03
|
|
line.long 0x0 "GICD_ICENABLER10,Interrupt Clear Enable Register 10"
|
|
eventfld.long 0x00 31. " CEB351 ,Clear Enable Bit 351" "Disabled,Enabled"
|
|
eventfld.long 0x00 30. " CEB350 ,Clear Enable Bit 350" "Disabled,Enabled"
|
|
eventfld.long 0x00 29. " CEB349 ,Clear Enable Bit 349" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 28. " CEB348 ,Clear Enable Bit 348" "Disabled,Enabled"
|
|
eventfld.long 0x00 27. " CEB347 ,Clear Enable Bit 347" "Disabled,Enabled"
|
|
eventfld.long 0x00 26. " CEB346 ,Clear Enable Bit 346" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 25. " CEB345 ,Clear Enable Bit 345" "Disabled,Enabled"
|
|
eventfld.long 0x00 24. " CEB344 ,Clear Enable Bit 344" "Disabled,Enabled"
|
|
eventfld.long 0x00 23. " CEB343 ,Clear Enable Bit 343" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 22. " CEB342 ,Clear Enable Bit 342" "Disabled,Enabled"
|
|
eventfld.long 0x00 21. " CEB341 ,Clear Enable Bit 341" "Disabled,Enabled"
|
|
eventfld.long 0x00 20. " CEB340 ,Clear Enable Bit 340" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 19. " CEB339 ,Clear Enable Bit 339" "Disabled,Enabled"
|
|
eventfld.long 0x00 18. " CEB338 ,Clear Enable Bit 338" "Disabled,Enabled"
|
|
eventfld.long 0x00 17. " CEB337 ,Clear Enable Bit 337" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CEB336 ,Clear Enable Bit 336" "Disabled,Enabled"
|
|
eventfld.long 0x00 15. " CEB335 ,Clear Enable Bit 335" "Disabled,Enabled"
|
|
eventfld.long 0x00 14. " CEB334 ,Clear Enable Bit 334" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 13. " CEB333 ,Clear Enable Bit 333" "Disabled,Enabled"
|
|
eventfld.long 0x00 12. " CEB332 ,Clear Enable Bit 332" "Disabled,Enabled"
|
|
eventfld.long 0x00 11. " CEB331 ,Clear Enable Bit 331" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 10. " CEB330 ,Clear Enable Bit 330" "Disabled,Enabled"
|
|
eventfld.long 0x00 9. " CEB329 ,Clear Enable Bit 329" "Disabled,Enabled"
|
|
eventfld.long 0x00 8. " CEB328 ,Clear Enable Bit 328" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CEB327 ,Clear Enable Bit 327" "Disabled,Enabled"
|
|
eventfld.long 0x00 6. " CEB326 ,Clear Enable Bit 326" "Disabled,Enabled"
|
|
eventfld.long 0x00 5. " CEB325 ,Clear Enable Bit 325" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CEB324 ,Clear Enable Bit 324" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " CEB323 ,Clear Enable Bit 323" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " CEB322 ,Clear Enable Bit 322" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CEB321 ,Clear Enable Bit 321" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " CEB320 ,Clear Enable Bit 320" "Disabled,Enabled"
|
|
group.long 0x11ac++0x03
|
|
line.long 0x0 "GICD_ICENABLER11,Interrupt Clear Enable Register 11"
|
|
eventfld.long 0x00 31. " CEB383 ,Clear Enable Bit 383" "Disabled,Enabled"
|
|
eventfld.long 0x00 30. " CEB382 ,Clear Enable Bit 382" "Disabled,Enabled"
|
|
eventfld.long 0x00 29. " CEB381 ,Clear Enable Bit 381" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 28. " CEB380 ,Clear Enable Bit 380" "Disabled,Enabled"
|
|
eventfld.long 0x00 27. " CEB379 ,Clear Enable Bit 379" "Disabled,Enabled"
|
|
eventfld.long 0x00 26. " CEB378 ,Clear Enable Bit 378" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 25. " CEB377 ,Clear Enable Bit 377" "Disabled,Enabled"
|
|
eventfld.long 0x00 24. " CEB376 ,Clear Enable Bit 376" "Disabled,Enabled"
|
|
eventfld.long 0x00 23. " CEB375 ,Clear Enable Bit 375" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 22. " CEB374 ,Clear Enable Bit 374" "Disabled,Enabled"
|
|
eventfld.long 0x00 21. " CEB373 ,Clear Enable Bit 373" "Disabled,Enabled"
|
|
eventfld.long 0x00 20. " CEB372 ,Clear Enable Bit 372" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 19. " CEB371 ,Clear Enable Bit 371" "Disabled,Enabled"
|
|
eventfld.long 0x00 18. " CEB370 ,Clear Enable Bit 370" "Disabled,Enabled"
|
|
eventfld.long 0x00 17. " CEB369 ,Clear Enable Bit 369" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CEB368 ,Clear Enable Bit 368" "Disabled,Enabled"
|
|
eventfld.long 0x00 15. " CEB367 ,Clear Enable Bit 367" "Disabled,Enabled"
|
|
eventfld.long 0x00 14. " CEB366 ,Clear Enable Bit 366" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 13. " CEB365 ,Clear Enable Bit 365" "Disabled,Enabled"
|
|
eventfld.long 0x00 12. " CEB364 ,Clear Enable Bit 364" "Disabled,Enabled"
|
|
eventfld.long 0x00 11. " CEB363 ,Clear Enable Bit 363" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 10. " CEB362 ,Clear Enable Bit 362" "Disabled,Enabled"
|
|
eventfld.long 0x00 9. " CEB361 ,Clear Enable Bit 361" "Disabled,Enabled"
|
|
eventfld.long 0x00 8. " CEB360 ,Clear Enable Bit 360" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CEB359 ,Clear Enable Bit 359" "Disabled,Enabled"
|
|
eventfld.long 0x00 6. " CEB358 ,Clear Enable Bit 358" "Disabled,Enabled"
|
|
eventfld.long 0x00 5. " CEB357 ,Clear Enable Bit 357" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CEB356 ,Clear Enable Bit 356" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " CEB355 ,Clear Enable Bit 355" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " CEB354 ,Clear Enable Bit 354" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CEB353 ,Clear Enable Bit 353" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " CEB352 ,Clear Enable Bit 352" "Disabled,Enabled"
|
|
group.long 0x11b0++0x03
|
|
line.long 0x0 "GICD_ICENABLER12,Interrupt Clear Enable Register 12"
|
|
eventfld.long 0x00 31. " CEB415 ,Clear Enable Bit 415" "Disabled,Enabled"
|
|
eventfld.long 0x00 30. " CEB414 ,Clear Enable Bit 414" "Disabled,Enabled"
|
|
eventfld.long 0x00 29. " CEB413 ,Clear Enable Bit 413" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 28. " CEB412 ,Clear Enable Bit 412" "Disabled,Enabled"
|
|
eventfld.long 0x00 27. " CEB411 ,Clear Enable Bit 411" "Disabled,Enabled"
|
|
eventfld.long 0x00 26. " CEB410 ,Clear Enable Bit 410" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 25. " CEB409 ,Clear Enable Bit 409" "Disabled,Enabled"
|
|
eventfld.long 0x00 24. " CEB408 ,Clear Enable Bit 408" "Disabled,Enabled"
|
|
eventfld.long 0x00 23. " CEB407 ,Clear Enable Bit 407" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 22. " CEB406 ,Clear Enable Bit 406" "Disabled,Enabled"
|
|
eventfld.long 0x00 21. " CEB405 ,Clear Enable Bit 405" "Disabled,Enabled"
|
|
eventfld.long 0x00 20. " CEB404 ,Clear Enable Bit 404" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 19. " CEB403 ,Clear Enable Bit 403" "Disabled,Enabled"
|
|
eventfld.long 0x00 18. " CEB402 ,Clear Enable Bit 402" "Disabled,Enabled"
|
|
eventfld.long 0x00 17. " CEB401 ,Clear Enable Bit 401" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CEB400 ,Clear Enable Bit 400" "Disabled,Enabled"
|
|
eventfld.long 0x00 15. " CEB399 ,Clear Enable Bit 399" "Disabled,Enabled"
|
|
eventfld.long 0x00 14. " CEB398 ,Clear Enable Bit 398" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 13. " CEB397 ,Clear Enable Bit 397" "Disabled,Enabled"
|
|
eventfld.long 0x00 12. " CEB396 ,Clear Enable Bit 396" "Disabled,Enabled"
|
|
eventfld.long 0x00 11. " CEB395 ,Clear Enable Bit 395" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 10. " CEB394 ,Clear Enable Bit 394" "Disabled,Enabled"
|
|
eventfld.long 0x00 9. " CEB393 ,Clear Enable Bit 393" "Disabled,Enabled"
|
|
eventfld.long 0x00 8. " CEB392 ,Clear Enable Bit 392" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CEB391 ,Clear Enable Bit 391" "Disabled,Enabled"
|
|
eventfld.long 0x00 6. " CEB390 ,Clear Enable Bit 390" "Disabled,Enabled"
|
|
eventfld.long 0x00 5. " CEB389 ,Clear Enable Bit 389" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CEB388 ,Clear Enable Bit 388" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " CEB387 ,Clear Enable Bit 387" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " CEB386 ,Clear Enable Bit 386" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CEB385 ,Clear Enable Bit 385" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " CEB384 ,Clear Enable Bit 384" "Disabled,Enabled"
|
|
group.long 0x11b4++0x03
|
|
line.long 0x0 "GICD_ICENABLER13,Interrupt Clear Enable Register 13"
|
|
eventfld.long 0x00 31. " CEB447 ,Clear Enable Bit 447" "Disabled,Enabled"
|
|
eventfld.long 0x00 30. " CEB446 ,Clear Enable Bit 446" "Disabled,Enabled"
|
|
eventfld.long 0x00 29. " CEB445 ,Clear Enable Bit 445" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 28. " CEB444 ,Clear Enable Bit 444" "Disabled,Enabled"
|
|
eventfld.long 0x00 27. " CEB443 ,Clear Enable Bit 443" "Disabled,Enabled"
|
|
eventfld.long 0x00 26. " CEB442 ,Clear Enable Bit 442" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 25. " CEB441 ,Clear Enable Bit 441" "Disabled,Enabled"
|
|
eventfld.long 0x00 24. " CEB440 ,Clear Enable Bit 440" "Disabled,Enabled"
|
|
eventfld.long 0x00 23. " CEB439 ,Clear Enable Bit 439" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 22. " CEB438 ,Clear Enable Bit 438" "Disabled,Enabled"
|
|
eventfld.long 0x00 21. " CEB437 ,Clear Enable Bit 437" "Disabled,Enabled"
|
|
eventfld.long 0x00 20. " CEB436 ,Clear Enable Bit 436" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 19. " CEB435 ,Clear Enable Bit 435" "Disabled,Enabled"
|
|
eventfld.long 0x00 18. " CEB434 ,Clear Enable Bit 434" "Disabled,Enabled"
|
|
eventfld.long 0x00 17. " CEB433 ,Clear Enable Bit 433" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CEB432 ,Clear Enable Bit 432" "Disabled,Enabled"
|
|
eventfld.long 0x00 15. " CEB431 ,Clear Enable Bit 431" "Disabled,Enabled"
|
|
eventfld.long 0x00 14. " CEB430 ,Clear Enable Bit 430" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 13. " CEB429 ,Clear Enable Bit 429" "Disabled,Enabled"
|
|
eventfld.long 0x00 12. " CEB428 ,Clear Enable Bit 428" "Disabled,Enabled"
|
|
eventfld.long 0x00 11. " CEB427 ,Clear Enable Bit 427" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 10. " CEB426 ,Clear Enable Bit 426" "Disabled,Enabled"
|
|
eventfld.long 0x00 9. " CEB425 ,Clear Enable Bit 425" "Disabled,Enabled"
|
|
eventfld.long 0x00 8. " CEB424 ,Clear Enable Bit 424" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CEB423 ,Clear Enable Bit 423" "Disabled,Enabled"
|
|
eventfld.long 0x00 6. " CEB422 ,Clear Enable Bit 422" "Disabled,Enabled"
|
|
eventfld.long 0x00 5. " CEB421 ,Clear Enable Bit 421" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CEB420 ,Clear Enable Bit 420" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " CEB419 ,Clear Enable Bit 419" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " CEB418 ,Clear Enable Bit 418" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CEB417 ,Clear Enable Bit 417" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " CEB416 ,Clear Enable Bit 416" "Disabled,Enabled"
|
|
group.long 0x11b8++0x03
|
|
line.long 0x0 "GICD_ICENABLER14,Interrupt Clear Enable Register 14"
|
|
eventfld.long 0x00 31. " CEB479 ,Clear Enable Bit 479" "Disabled,Enabled"
|
|
eventfld.long 0x00 30. " CEB478 ,Clear Enable Bit 478" "Disabled,Enabled"
|
|
eventfld.long 0x00 29. " CEB477 ,Clear Enable Bit 477" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 28. " CEB476 ,Clear Enable Bit 476" "Disabled,Enabled"
|
|
eventfld.long 0x00 27. " CEB475 ,Clear Enable Bit 475" "Disabled,Enabled"
|
|
eventfld.long 0x00 26. " CEB474 ,Clear Enable Bit 474" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 25. " CEB473 ,Clear Enable Bit 473" "Disabled,Enabled"
|
|
eventfld.long 0x00 24. " CEB472 ,Clear Enable Bit 472" "Disabled,Enabled"
|
|
eventfld.long 0x00 23. " CEB471 ,Clear Enable Bit 471" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 22. " CEB470 ,Clear Enable Bit 470" "Disabled,Enabled"
|
|
eventfld.long 0x00 21. " CEB469 ,Clear Enable Bit 469" "Disabled,Enabled"
|
|
eventfld.long 0x00 20. " CEB468 ,Clear Enable Bit 468" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 19. " CEB467 ,Clear Enable Bit 467" "Disabled,Enabled"
|
|
eventfld.long 0x00 18. " CEB466 ,Clear Enable Bit 466" "Disabled,Enabled"
|
|
eventfld.long 0x00 17. " CEB465 ,Clear Enable Bit 465" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CEB464 ,Clear Enable Bit 464" "Disabled,Enabled"
|
|
eventfld.long 0x00 15. " CEB463 ,Clear Enable Bit 463" "Disabled,Enabled"
|
|
eventfld.long 0x00 14. " CEB462 ,Clear Enable Bit 462" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 13. " CEB461 ,Clear Enable Bit 461" "Disabled,Enabled"
|
|
eventfld.long 0x00 12. " CEB460 ,Clear Enable Bit 460" "Disabled,Enabled"
|
|
eventfld.long 0x00 11. " CEB459 ,Clear Enable Bit 459" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 10. " CEB458 ,Clear Enable Bit 458" "Disabled,Enabled"
|
|
eventfld.long 0x00 9. " CEB457 ,Clear Enable Bit 457" "Disabled,Enabled"
|
|
eventfld.long 0x00 8. " CEB456 ,Clear Enable Bit 456" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CEB455 ,Clear Enable Bit 455" "Disabled,Enabled"
|
|
eventfld.long 0x00 6. " CEB454 ,Clear Enable Bit 454" "Disabled,Enabled"
|
|
eventfld.long 0x00 5. " CEB453 ,Clear Enable Bit 453" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CEB452 ,Clear Enable Bit 452" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " CEB451 ,Clear Enable Bit 451" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " CEB450 ,Clear Enable Bit 450" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CEB449 ,Clear Enable Bit 449" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " CEB448 ,Clear Enable Bit 448" "Disabled,Enabled"
|
|
group.long 0x11bC++0x03
|
|
line.long 0x0 "GICD_ICENABLER15,Interrupt Clear Enable Register 15"
|
|
eventfld.long 0x00 31. " CEB511 ,Clear Enable Bit 511" "Disabled,Enabled"
|
|
eventfld.long 0x00 30. " CEB510 ,Clear Enable Bit 510" "Disabled,Enabled"
|
|
eventfld.long 0x00 29. " CEB509 ,Clear Enable Bit 509" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 28. " CEB508 ,Clear Enable Bit 508" "Disabled,Enabled"
|
|
eventfld.long 0x00 27. " CEB507 ,Clear Enable Bit 507" "Disabled,Enabled"
|
|
eventfld.long 0x00 26. " CEB506 ,Clear Enable Bit 506" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 25. " CEB505 ,Clear Enable Bit 505" "Disabled,Enabled"
|
|
eventfld.long 0x00 24. " CEB504 ,Clear Enable Bit 504" "Disabled,Enabled"
|
|
eventfld.long 0x00 23. " CEB503 ,Clear Enable Bit 503" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 22. " CEB502 ,Clear Enable Bit 502" "Disabled,Enabled"
|
|
eventfld.long 0x00 21. " CEB501 ,Clear Enable Bit 501" "Disabled,Enabled"
|
|
eventfld.long 0x00 20. " CEB500 ,Clear Enable Bit 500" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 19. " CEB499 ,Clear Enable Bit 499" "Disabled,Enabled"
|
|
eventfld.long 0x00 18. " CEB498 ,Clear Enable Bit 498" "Disabled,Enabled"
|
|
eventfld.long 0x00 17. " CEB497 ,Clear Enable Bit 497" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CEB496 ,Clear Enable Bit 496" "Disabled,Enabled"
|
|
eventfld.long 0x00 15. " CEB495 ,Clear Enable Bit 495" "Disabled,Enabled"
|
|
eventfld.long 0x00 14. " CEB494 ,Clear Enable Bit 494" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 13. " CEB493 ,Clear Enable Bit 493" "Disabled,Enabled"
|
|
eventfld.long 0x00 12. " CEB492 ,Clear Enable Bit 492" "Disabled,Enabled"
|
|
eventfld.long 0x00 11. " CEB491 ,Clear Enable Bit 491" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 10. " CEB490 ,Clear Enable Bit 490" "Disabled,Enabled"
|
|
eventfld.long 0x00 9. " CEB489 ,Clear Enable Bit 489" "Disabled,Enabled"
|
|
eventfld.long 0x00 8. " CEB488 ,Clear Enable Bit 488" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CEB487 ,Clear Enable Bit 487" "Disabled,Enabled"
|
|
eventfld.long 0x00 6. " CEB486 ,Clear Enable Bit 486" "Disabled,Enabled"
|
|
eventfld.long 0x00 5. " CEB485 ,Clear Enable Bit 485" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CEB484 ,Clear Enable Bit 484" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " CEB483 ,Clear Enable Bit 483" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " CEB482 ,Clear Enable Bit 482" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CEB481 ,Clear Enable Bit 481" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " CEB480 ,Clear Enable Bit 480" "Disabled,Enabled"
|
|
textline " "
|
|
tree.end
|
|
tree "Set-Pending Registers"
|
|
group.long 0x1200++0x03
|
|
line.long 0x0 "GICD_ISPENDR0,Interrupt Set Pending Register 0"
|
|
bitfld.long 0x00 31. " SPB31 ,Set Pending Bit 31" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SPB30 ,Set Pending Bit 30" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " SPB29 ,Set Pending Bit 29" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPB28 ,Set Pending Bit 28" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " SPB27 ,Set Pending Bit 27" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " SPB26 ,Set Pending Bit 26" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPB25 ,Set Pending Bit 25" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " SPB24 ,Set Pending Bit 24" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " SPB23 ,Set Pending Bit 23" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPB22 ,Set Pending Bit 22" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SPB21 ,Set Pending Bit 21" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " SPB20 ,Set Pending Bit 20" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPB19 ,Set Pending Bit 19" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " SPB18 ,Set Pending Bit 18" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " SPB17 ,Set Pending Bit 17" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPB16 ,Set Pending Bit 16" "Not pending,Pending"
|
|
bitfld.long 0x00 15. " SPB15 ,Set Pending Bit 15" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " SPB14 ,Set Pending Bit 14" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPB13 ,Set Pending Bit 13" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " SPB12 ,Set Pending Bit 12" "Not pending,Pending"
|
|
bitfld.long 0x00 11. " SPB11 ,Set Pending Bit 11" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPB10 ,Set Pending Bit 10" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " SPB9 ,Set Pending Bit 9" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " SPB8 ,Set Pending Bit 8" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPB7 ,Set Pending Bit 7" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " SPB6 ,Set Pending Bit 6" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " SPB5 ,Set Pending Bit 5" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPB4 ,Set Pending Bit 4" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " SPB3 ,Set Pending Bit 3" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " SPB2 ,Set Pending Bit 2" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPB1 ,Set Pending Bit 1" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " SPB0 ,Set Pending Bit 0" "Not pending,Pending"
|
|
group.long 0x1204++0x03
|
|
line.long 0x0 "GICD_ISPENDR1,Interrupt Set Pending Register 1"
|
|
bitfld.long 0x00 31. " SPB63 ,Set Pending Bit 63" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SPB62 ,Set Pending Bit 62" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " SPB61 ,Set Pending Bit 61" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPB60 ,Set Pending Bit 60" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " SPB59 ,Set Pending Bit 59" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " SPB58 ,Set Pending Bit 58" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPB57 ,Set Pending Bit 57" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " SPB56 ,Set Pending Bit 56" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " SPB55 ,Set Pending Bit 55" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPB54 ,Set Pending Bit 54" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SPB53 ,Set Pending Bit 53" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " SPB52 ,Set Pending Bit 52" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPB51 ,Set Pending Bit 51" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " SPB50 ,Set Pending Bit 50" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " SPB49 ,Set Pending Bit 49" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPB48 ,Set Pending Bit 48" "Not pending,Pending"
|
|
bitfld.long 0x00 15. " SPB47 ,Set Pending Bit 47" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " SPB46 ,Set Pending Bit 46" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPB45 ,Set Pending Bit 45" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " SPB44 ,Set Pending Bit 44" "Not pending,Pending"
|
|
bitfld.long 0x00 11. " SPB43 ,Set Pending Bit 43" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPB42 ,Set Pending Bit 42" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " SPB41 ,Set Pending Bit 41" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " SPB40 ,Set Pending Bit 40" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPB39 ,Set Pending Bit 39" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " SPB38 ,Set Pending Bit 38" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " SPB37 ,Set Pending Bit 37" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPB36 ,Set Pending Bit 36" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " SPB35 ,Set Pending Bit 35" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " SPB34 ,Set Pending Bit 34" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPB33 ,Set Pending Bit 33" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " SPB32 ,Set Pending Bit 32" "Not pending,Pending"
|
|
group.long 0x1208++0x03
|
|
line.long 0x0 "GICD_ISPENDR2,Interrupt Set Pending Register 2"
|
|
bitfld.long 0x00 31. " SPB95 ,Set Pending Bit 95" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SPB94 ,Set Pending Bit 94" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " SPB93 ,Set Pending Bit 93" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPB92 ,Set Pending Bit 92" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " SPB91 ,Set Pending Bit 91" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " SPB90 ,Set Pending Bit 90" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPB89 ,Set Pending Bit 89" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " SPB88 ,Set Pending Bit 88" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " SPB87 ,Set Pending Bit 87" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPB86 ,Set Pending Bit 86" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SPB85 ,Set Pending Bit 85" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " SPB84 ,Set Pending Bit 84" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPB83 ,Set Pending Bit 83" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " SPB82 ,Set Pending Bit 82" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " SPB81 ,Set Pending Bit 81" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPB80 ,Set Pending Bit 80" "Not pending,Pending"
|
|
bitfld.long 0x00 15. " SPB79 ,Set Pending Bit 79" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " SPB78 ,Set Pending Bit 78" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPB77 ,Set Pending Bit 77" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " SPB76 ,Set Pending Bit 76" "Not pending,Pending"
|
|
bitfld.long 0x00 11. " SPB75 ,Set Pending Bit 75" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPB74 ,Set Pending Bit 74" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " SPB73 ,Set Pending Bit 73" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " SPB72 ,Set Pending Bit 72" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPB71 ,Set Pending Bit 71" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " SPB70 ,Set Pending Bit 70" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " SPB69 ,Set Pending Bit 69" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPB68 ,Set Pending Bit 68" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " SPB67 ,Set Pending Bit 67" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " SPB66 ,Set Pending Bit 66" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPB65 ,Set Pending Bit 65" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " SPB64 ,Set Pending Bit 64" "Not pending,Pending"
|
|
group.long 0x120C++0x03
|
|
line.long 0x0 "GICD_ISPENDR3,Interrupt Set Pending Register 3"
|
|
bitfld.long 0x00 31. " SPB127 ,Set Pending Bit 127" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SPB126 ,Set Pending Bit 126" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " SPB125 ,Set Pending Bit 125" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPB124 ,Set Pending Bit 124" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " SPB123 ,Set Pending Bit 123" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " SPB122 ,Set Pending Bit 122" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPB121 ,Set Pending Bit 121" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " SPB120 ,Set Pending Bit 120" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " SPB119 ,Set Pending Bit 119" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPB118 ,Set Pending Bit 118" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SPB117 ,Set Pending Bit 117" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " SPB116 ,Set Pending Bit 116" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPB115 ,Set Pending Bit 115" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " SPB114 ,Set Pending Bit 114" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " SPB113 ,Set Pending Bit 113" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPB112 ,Set Pending Bit 112" "Not pending,Pending"
|
|
bitfld.long 0x00 15. " SPB111 ,Set Pending Bit 111" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " SPB110 ,Set Pending Bit 110" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPB109 ,Set Pending Bit 109" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " SPB108 ,Set Pending Bit 108" "Not pending,Pending"
|
|
bitfld.long 0x00 11. " SPB107 ,Set Pending Bit 107" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPB106 ,Set Pending Bit 106" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " SPB105 ,Set Pending Bit 105" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " SPB104 ,Set Pending Bit 104" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPB103 ,Set Pending Bit 103" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " SPB102 ,Set Pending Bit 102" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " SPB101 ,Set Pending Bit 101" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPB100 ,Set Pending Bit 100" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " SPB99 ,Set Pending Bit 99" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " SPB98 ,Set Pending Bit 98" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPB97 ,Set Pending Bit 97" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " SPB96 ,Set Pending Bit 96" "Not pending,Pending"
|
|
group.long 0x1210++0x03
|
|
line.long 0x0 "GICD_ISPENDR4,Interrupt Set Pending Register 4"
|
|
bitfld.long 0x00 31. " SPB159 ,Set Pending Bit 159" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SPB158 ,Set Pending Bit 158" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " SPB157 ,Set Pending Bit 157" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPB156 ,Set Pending Bit 156" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " SPB155 ,Set Pending Bit 155" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " SPB154 ,Set Pending Bit 154" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPB153 ,Set Pending Bit 153" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " SPB152 ,Set Pending Bit 152" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " SPB151 ,Set Pending Bit 151" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPB150 ,Set Pending Bit 150" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SPB149 ,Set Pending Bit 149" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " SPB148 ,Set Pending Bit 148" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPB147 ,Set Pending Bit 147" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " SPB146 ,Set Pending Bit 146" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " SPB145 ,Set Pending Bit 145" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPB144 ,Set Pending Bit 144" "Not pending,Pending"
|
|
bitfld.long 0x00 15. " SPB143 ,Set Pending Bit 143" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " SPB142 ,Set Pending Bit 142" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPB141 ,Set Pending Bit 141" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " SPB140 ,Set Pending Bit 140" "Not pending,Pending"
|
|
bitfld.long 0x00 11. " SPB139 ,Set Pending Bit 139" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPB138 ,Set Pending Bit 138" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " SPB137 ,Set Pending Bit 137" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " SPB136 ,Set Pending Bit 136" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPB135 ,Set Pending Bit 135" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " SPB134 ,Set Pending Bit 134" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " SPB133 ,Set Pending Bit 133" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPB132 ,Set Pending Bit 132" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " SPB131 ,Set Pending Bit 131" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " SPB130 ,Set Pending Bit 130" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPB129 ,Set Pending Bit 129" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " SPB128 ,Set Pending Bit 128" "Not pending,Pending"
|
|
group.long 0x1214++0x03
|
|
line.long 0x0 "GICD_ISPENDR5,Interrupt Set Pending Register 5"
|
|
bitfld.long 0x00 31. " SPB191 ,Set Pending Bit 191" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SPB190 ,Set Pending Bit 190" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " SPB189 ,Set Pending Bit 189" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPB188 ,Set Pending Bit 188" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " SPB187 ,Set Pending Bit 187" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " SPB186 ,Set Pending Bit 186" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPB185 ,Set Pending Bit 185" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " SPB184 ,Set Pending Bit 184" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " SPB183 ,Set Pending Bit 183" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPB182 ,Set Pending Bit 182" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SPB181 ,Set Pending Bit 181" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " SPB180 ,Set Pending Bit 180" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPB179 ,Set Pending Bit 179" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " SPB178 ,Set Pending Bit 178" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " SPB177 ,Set Pending Bit 177" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPB176 ,Set Pending Bit 176" "Not pending,Pending"
|
|
bitfld.long 0x00 15. " SPB175 ,Set Pending Bit 175" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " SPB174 ,Set Pending Bit 174" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPB173 ,Set Pending Bit 173" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " SPB172 ,Set Pending Bit 172" "Not pending,Pending"
|
|
bitfld.long 0x00 11. " SPB171 ,Set Pending Bit 171" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPB170 ,Set Pending Bit 170" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " SPB169 ,Set Pending Bit 169" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " SPB168 ,Set Pending Bit 168" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPB167 ,Set Pending Bit 167" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " SPB166 ,Set Pending Bit 166" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " SPB165 ,Set Pending Bit 165" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPB164 ,Set Pending Bit 164" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " SPB163 ,Set Pending Bit 163" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " SPB162 ,Set Pending Bit 162" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPB161 ,Set Pending Bit 161" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " SPB160 ,Set Pending Bit 160" "Not pending,Pending"
|
|
group.long 0x1218++0x03
|
|
line.long 0x0 "GICD_ISPENDR6,Interrupt Set Pending Register 6"
|
|
bitfld.long 0x00 31. " SPB223 ,Set Pending Bit 223" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SPB222 ,Set Pending Bit 222" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " SPB221 ,Set Pending Bit 221" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPB220 ,Set Pending Bit 220" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " SPB219 ,Set Pending Bit 219" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " SPB218 ,Set Pending Bit 218" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPB217 ,Set Pending Bit 217" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " SPB216 ,Set Pending Bit 216" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " SPB215 ,Set Pending Bit 215" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPB214 ,Set Pending Bit 214" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SPB213 ,Set Pending Bit 213" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " SPB212 ,Set Pending Bit 212" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPB211 ,Set Pending Bit 211" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " SPB210 ,Set Pending Bit 210" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " SPB209 ,Set Pending Bit 209" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPB208 ,Set Pending Bit 208" "Not pending,Pending"
|
|
bitfld.long 0x00 15. " SPB207 ,Set Pending Bit 207" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " SPB206 ,Set Pending Bit 206" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPB205 ,Set Pending Bit 205" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " SPB204 ,Set Pending Bit 204" "Not pending,Pending"
|
|
bitfld.long 0x00 11. " SPB203 ,Set Pending Bit 203" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPB202 ,Set Pending Bit 202" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " SPB201 ,Set Pending Bit 201" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " SPB200 ,Set Pending Bit 200" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPB199 ,Set Pending Bit 199" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " SPB198 ,Set Pending Bit 198" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " SPB197 ,Set Pending Bit 197" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPB196 ,Set Pending Bit 196" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " SPB195 ,Set Pending Bit 195" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " SPB194 ,Set Pending Bit 194" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPB193 ,Set Pending Bit 193" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " SPB192 ,Set Pending Bit 192" "Not pending,Pending"
|
|
group.long 0x121C++0x03
|
|
line.long 0x0 "GICD_ISPENDR7,Interrupt Set Pending Register 7"
|
|
bitfld.long 0x00 31. " SPB255 ,Set Pending Bit 255" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SPB254 ,Set Pending Bit 254" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " SPB253 ,Set Pending Bit 253" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPB252 ,Set Pending Bit 252" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " SPB251 ,Set Pending Bit 251" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " SPB250 ,Set Pending Bit 250" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPB249 ,Set Pending Bit 249" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " SPB248 ,Set Pending Bit 248" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " SPB247 ,Set Pending Bit 247" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPB246 ,Set Pending Bit 246" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SPB245 ,Set Pending Bit 245" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " SPB244 ,Set Pending Bit 244" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPB243 ,Set Pending Bit 243" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " SPB242 ,Set Pending Bit 242" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " SPB241 ,Set Pending Bit 241" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPB240 ,Set Pending Bit 240" "Not pending,Pending"
|
|
bitfld.long 0x00 15. " SPB239 ,Set Pending Bit 239" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " SPB238 ,Set Pending Bit 238" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPB237 ,Set Pending Bit 237" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " SPB236 ,Set Pending Bit 236" "Not pending,Pending"
|
|
bitfld.long 0x00 11. " SPB235 ,Set Pending Bit 235" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPB234 ,Set Pending Bit 234" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " SPB233 ,Set Pending Bit 233" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " SPB232 ,Set Pending Bit 232" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPB231 ,Set Pending Bit 231" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " SPB230 ,Set Pending Bit 230" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " SPB229 ,Set Pending Bit 229" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPB228 ,Set Pending Bit 228" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " SPB227 ,Set Pending Bit 227" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " SPB226 ,Set Pending Bit 226" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPB225 ,Set Pending Bit 225" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " SPB224 ,Set Pending Bit 224" "Not pending,Pending"
|
|
group.long 0x1220++0x03
|
|
line.long 0x0 "GICD_ISPENDR8,Interrupt Set Pending Register 8"
|
|
bitfld.long 0x00 31. " SPB287 ,Set Pending Bit 287" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SPB286 ,Set Pending Bit 286" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " SPB285 ,Set Pending Bit 285" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPB284 ,Set Pending Bit 284" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " SPB283 ,Set Pending Bit 283" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " SPB282 ,Set Pending Bit 282" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPB281 ,Set Pending Bit 281" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " SPB280 ,Set Pending Bit 280" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " SPB279 ,Set Pending Bit 279" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPB278 ,Set Pending Bit 278" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SPB277 ,Set Pending Bit 277" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " SPB276 ,Set Pending Bit 276" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPB275 ,Set Pending Bit 275" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " SPB274 ,Set Pending Bit 274" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " SPB273 ,Set Pending Bit 273" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPB272 ,Set Pending Bit 272" "Not pending,Pending"
|
|
bitfld.long 0x00 15. " SPB271 ,Set Pending Bit 271" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " SPB270 ,Set Pending Bit 270" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPB269 ,Set Pending Bit 269" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " SPB268 ,Set Pending Bit 268" "Not pending,Pending"
|
|
bitfld.long 0x00 11. " SPB267 ,Set Pending Bit 267" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPB266 ,Set Pending Bit 266" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " SPB265 ,Set Pending Bit 265" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " SPB264 ,Set Pending Bit 264" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPB263 ,Set Pending Bit 263" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " SPB262 ,Set Pending Bit 262" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " SPB261 ,Set Pending Bit 261" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPB260 ,Set Pending Bit 260" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " SPB259 ,Set Pending Bit 259" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " SPB258 ,Set Pending Bit 258" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPB257 ,Set Pending Bit 257" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " SPB256 ,Set Pending Bit 256" "Not pending,Pending"
|
|
group.long 0x1224++0x03
|
|
line.long 0x0 "GICD_ISPENDR9,Interrupt Set Pending Register 9"
|
|
bitfld.long 0x00 31. " SPB319 ,Set Pending Bit 319" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SPB318 ,Set Pending Bit 318" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " SPB317 ,Set Pending Bit 317" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPB316 ,Set Pending Bit 316" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " SPB315 ,Set Pending Bit 315" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " SPB314 ,Set Pending Bit 314" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPB313 ,Set Pending Bit 313" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " SPB312 ,Set Pending Bit 312" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " SPB311 ,Set Pending Bit 311" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPB310 ,Set Pending Bit 310" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SPB309 ,Set Pending Bit 309" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " SPB308 ,Set Pending Bit 308" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPB307 ,Set Pending Bit 307" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " SPB306 ,Set Pending Bit 306" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " SPB305 ,Set Pending Bit 305" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPB304 ,Set Pending Bit 304" "Not pending,Pending"
|
|
bitfld.long 0x00 15. " SPB303 ,Set Pending Bit 303" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " SPB302 ,Set Pending Bit 302" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPB301 ,Set Pending Bit 301" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " SPB300 ,Set Pending Bit 300" "Not pending,Pending"
|
|
bitfld.long 0x00 11. " SPB299 ,Set Pending Bit 299" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPB298 ,Set Pending Bit 298" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " SPB297 ,Set Pending Bit 297" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " SPB296 ,Set Pending Bit 296" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPB295 ,Set Pending Bit 295" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " SPB294 ,Set Pending Bit 294" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " SPB293 ,Set Pending Bit 293" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPB292 ,Set Pending Bit 292" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " SPB291 ,Set Pending Bit 291" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " SPB290 ,Set Pending Bit 290" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPB289 ,Set Pending Bit 289" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " SPB288 ,Set Pending Bit 288" "Not pending,Pending"
|
|
group.long 0x1228++0x03
|
|
line.long 0x0 "GICD_ISPENDR10,Interrupt Set Pending Register 10"
|
|
bitfld.long 0x00 31. " SPB351 ,Set Pending Bit 351" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SPB350 ,Set Pending Bit 350" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " SPB349 ,Set Pending Bit 349" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPB348 ,Set Pending Bit 348" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " SPB347 ,Set Pending Bit 347" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " SPB346 ,Set Pending Bit 346" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPB345 ,Set Pending Bit 345" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " SPB344 ,Set Pending Bit 344" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " SPB343 ,Set Pending Bit 343" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPB342 ,Set Pending Bit 342" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SPB341 ,Set Pending Bit 341" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " SPB340 ,Set Pending Bit 340" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPB339 ,Set Pending Bit 339" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " SPB338 ,Set Pending Bit 338" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " SPB337 ,Set Pending Bit 337" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPB336 ,Set Pending Bit 336" "Not pending,Pending"
|
|
bitfld.long 0x00 15. " SPB335 ,Set Pending Bit 335" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " SPB334 ,Set Pending Bit 334" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPB333 ,Set Pending Bit 333" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " SPB332 ,Set Pending Bit 332" "Not pending,Pending"
|
|
bitfld.long 0x00 11. " SPB331 ,Set Pending Bit 331" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPB330 ,Set Pending Bit 330" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " SPB329 ,Set Pending Bit 329" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " SPB328 ,Set Pending Bit 328" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPB327 ,Set Pending Bit 327" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " SPB326 ,Set Pending Bit 326" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " SPB325 ,Set Pending Bit 325" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPB324 ,Set Pending Bit 324" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " SPB323 ,Set Pending Bit 323" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " SPB322 ,Set Pending Bit 322" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPB321 ,Set Pending Bit 321" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " SPB320 ,Set Pending Bit 320" "Not pending,Pending"
|
|
group.long 0x122C++0x03
|
|
line.long 0x0 "GICD_ISPENDR11,Interrupt Set Pending Register 11"
|
|
bitfld.long 0x00 31. " SPB383 ,Set Pending Bit 383" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SPB382 ,Set Pending Bit 382" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " SPB381 ,Set Pending Bit 381" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPB380 ,Set Pending Bit 380" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " SPB379 ,Set Pending Bit 379" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " SPB378 ,Set Pending Bit 378" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPB377 ,Set Pending Bit 377" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " SPB376 ,Set Pending Bit 376" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " SPB375 ,Set Pending Bit 375" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPB374 ,Set Pending Bit 374" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SPB373 ,Set Pending Bit 373" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " SPB372 ,Set Pending Bit 372" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPB371 ,Set Pending Bit 371" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " SPB370 ,Set Pending Bit 370" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " SPB369 ,Set Pending Bit 369" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPB368 ,Set Pending Bit 368" "Not pending,Pending"
|
|
bitfld.long 0x00 15. " SPB367 ,Set Pending Bit 367" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " SPB366 ,Set Pending Bit 366" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPB365 ,Set Pending Bit 365" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " SPB364 ,Set Pending Bit 364" "Not pending,Pending"
|
|
bitfld.long 0x00 11. " SPB363 ,Set Pending Bit 363" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPB362 ,Set Pending Bit 362" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " SPB361 ,Set Pending Bit 361" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " SPB360 ,Set Pending Bit 360" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPB359 ,Set Pending Bit 359" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " SPB358 ,Set Pending Bit 358" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " SPB357 ,Set Pending Bit 357" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPB356 ,Set Pending Bit 356" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " SPB355 ,Set Pending Bit 355" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " SPB354 ,Set Pending Bit 354" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPB353 ,Set Pending Bit 353" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " SPB352 ,Set Pending Bit 352" "Not pending,Pending"
|
|
group.long 0x1230++0x03
|
|
line.long 0x0 "GICD_ISPENDR12,Interrupt Set Pending Register 12"
|
|
bitfld.long 0x00 31. " SPB415 ,Set Pending Bit 415" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SPB414 ,Set Pending Bit 414" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " SPB413 ,Set Pending Bit 413" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPB412 ,Set Pending Bit 412" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " SPB411 ,Set Pending Bit 411" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " SPB410 ,Set Pending Bit 410" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPB409 ,Set Pending Bit 409" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " SPB408 ,Set Pending Bit 408" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " SPB407 ,Set Pending Bit 407" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPB406 ,Set Pending Bit 406" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SPB405 ,Set Pending Bit 405" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " SPB404 ,Set Pending Bit 404" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPB403 ,Set Pending Bit 403" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " SPB402 ,Set Pending Bit 402" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " SPB401 ,Set Pending Bit 401" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPB400 ,Set Pending Bit 400" "Not pending,Pending"
|
|
bitfld.long 0x00 15. " SPB399 ,Set Pending Bit 399" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " SPB398 ,Set Pending Bit 398" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPB397 ,Set Pending Bit 397" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " SPB396 ,Set Pending Bit 396" "Not pending,Pending"
|
|
bitfld.long 0x00 11. " SPB395 ,Set Pending Bit 395" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPB394 ,Set Pending Bit 394" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " SPB393 ,Set Pending Bit 393" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " SPB392 ,Set Pending Bit 392" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPB391 ,Set Pending Bit 391" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " SPB390 ,Set Pending Bit 390" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " SPB389 ,Set Pending Bit 389" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPB388 ,Set Pending Bit 388" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " SPB387 ,Set Pending Bit 387" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " SPB386 ,Set Pending Bit 386" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPB385 ,Set Pending Bit 385" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " SPB384 ,Set Pending Bit 384" "Not pending,Pending"
|
|
group.long 0x1234++0x03
|
|
line.long 0x0 "GICD_ISPENDR13,Interrupt Set Pending Register 13"
|
|
bitfld.long 0x00 31. " SPB447 ,Set Pending Bit 447" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SPB446 ,Set Pending Bit 446" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " SPB445 ,Set Pending Bit 445" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPB444 ,Set Pending Bit 444" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " SPB443 ,Set Pending Bit 443" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " SPB442 ,Set Pending Bit 442" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPB441 ,Set Pending Bit 441" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " SPB440 ,Set Pending Bit 440" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " SPB439 ,Set Pending Bit 439" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPB438 ,Set Pending Bit 438" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SPB437 ,Set Pending Bit 437" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " SPB436 ,Set Pending Bit 436" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPB435 ,Set Pending Bit 435" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " SPB434 ,Set Pending Bit 434" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " SPB433 ,Set Pending Bit 433" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPB432 ,Set Pending Bit 432" "Not pending,Pending"
|
|
bitfld.long 0x00 15. " SPB431 ,Set Pending Bit 431" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " SPB430 ,Set Pending Bit 430" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPB429 ,Set Pending Bit 429" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " SPB428 ,Set Pending Bit 428" "Not pending,Pending"
|
|
bitfld.long 0x00 11. " SPB427 ,Set Pending Bit 427" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPB426 ,Set Pending Bit 426" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " SPB425 ,Set Pending Bit 425" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " SPB424 ,Set Pending Bit 424" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPB423 ,Set Pending Bit 423" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " SPB422 ,Set Pending Bit 422" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " SPB421 ,Set Pending Bit 421" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPB420 ,Set Pending Bit 420" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " SPB419 ,Set Pending Bit 419" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " SPB418 ,Set Pending Bit 418" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPB417 ,Set Pending Bit 417" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " SPB416 ,Set Pending Bit 416" "Not pending,Pending"
|
|
group.long 0x1238++0x03
|
|
line.long 0x0 "GICD_ISPENDR14,Interrupt Set Pending Register 14"
|
|
bitfld.long 0x00 31. " SPB479 ,Set Pending Bit 479" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SPB478 ,Set Pending Bit 478" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " SPB477 ,Set Pending Bit 477" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPB476 ,Set Pending Bit 476" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " SPB475 ,Set Pending Bit 475" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " SPB474 ,Set Pending Bit 474" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPB473 ,Set Pending Bit 473" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " SPB472 ,Set Pending Bit 472" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " SPB471 ,Set Pending Bit 471" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPB470 ,Set Pending Bit 470" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SPB469 ,Set Pending Bit 469" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " SPB468 ,Set Pending Bit 468" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPB467 ,Set Pending Bit 467" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " SPB466 ,Set Pending Bit 466" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " SPB465 ,Set Pending Bit 465" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPB464 ,Set Pending Bit 464" "Not pending,Pending"
|
|
bitfld.long 0x00 15. " SPB463 ,Set Pending Bit 463" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " SPB462 ,Set Pending Bit 462" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPB461 ,Set Pending Bit 461" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " SPB460 ,Set Pending Bit 460" "Not pending,Pending"
|
|
bitfld.long 0x00 11. " SPB459 ,Set Pending Bit 459" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPB458 ,Set Pending Bit 458" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " SPB457 ,Set Pending Bit 457" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " SPB456 ,Set Pending Bit 456" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPB455 ,Set Pending Bit 455" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " SPB454 ,Set Pending Bit 454" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " SPB453 ,Set Pending Bit 453" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPB452 ,Set Pending Bit 452" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " SPB451 ,Set Pending Bit 451" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " SPB450 ,Set Pending Bit 450" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPB449 ,Set Pending Bit 449" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " SPB448 ,Set Pending Bit 448" "Not pending,Pending"
|
|
group.long 0x123C++0x03
|
|
line.long 0x0 "GICD_ISPENDR15,Interrupt Set Pending Register 15"
|
|
bitfld.long 0x00 31. " SPB511 ,Set Pending Bit 511" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SPB510 ,Set Pending Bit 510" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " SPB509 ,Set Pending Bit 509" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPB508 ,Set Pending Bit 508" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " SPB507 ,Set Pending Bit 507" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " SPB506 ,Set Pending Bit 506" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPB505 ,Set Pending Bit 505" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " SPB504 ,Set Pending Bit 504" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " SPB503 ,Set Pending Bit 503" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPB502 ,Set Pending Bit 502" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SPB501 ,Set Pending Bit 501" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " SPB500 ,Set Pending Bit 500" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPB499 ,Set Pending Bit 499" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " SPB498 ,Set Pending Bit 498" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " SPB497 ,Set Pending Bit 497" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPB496 ,Set Pending Bit 496" "Not pending,Pending"
|
|
bitfld.long 0x00 15. " SPB495 ,Set Pending Bit 495" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " SPB494 ,Set Pending Bit 494" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPB493 ,Set Pending Bit 493" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " SPB492 ,Set Pending Bit 492" "Not pending,Pending"
|
|
bitfld.long 0x00 11. " SPB491 ,Set Pending Bit 491" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SPB490 ,Set Pending Bit 490" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " SPB489 ,Set Pending Bit 489" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " SPB488 ,Set Pending Bit 488" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPB487 ,Set Pending Bit 487" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " SPB486 ,Set Pending Bit 486" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " SPB485 ,Set Pending Bit 485" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPB484 ,Set Pending Bit 484" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " SPB483 ,Set Pending Bit 483" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " SPB482 ,Set Pending Bit 482" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPB481 ,Set Pending Bit 481" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " SPB480 ,Set Pending Bit 480" "Not pending,Pending"
|
|
textline " "
|
|
tree.end
|
|
tree "Clear-Pending Registers"
|
|
group.long 0x1280++0x03
|
|
line.long 0x0 "GICD_ICPENDR0,Interrupt Clear Pending Register 0"
|
|
eventfld.long 0x00 31. " CPB31 ,Clear Pending Bit 31" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " CPB30 ,Clear Pending Bit 30" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " CPB29 ,Clear Pending Bit 29" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 28. " CPB28 ,Clear Pending Bit 28" "Not pending,Pending"
|
|
eventfld.long 0x00 27. " CPB27 ,Clear Pending Bit 27" "Not pending,Pending"
|
|
eventfld.long 0x00 26. " CPB26 ,Clear Pending Bit 26" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 25. " CPB25 ,Clear Pending Bit 25" "Not pending,Pending"
|
|
eventfld.long 0x00 24. " CPB24 ,Clear Pending Bit 24" "Not pending,Pending"
|
|
eventfld.long 0x00 23. " CPB23 ,Clear Pending Bit 23" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 22. " CPB22 ,Clear Pending Bit 22" "Not pending,Pending"
|
|
eventfld.long 0x00 21. " CPB21 ,Clear Pending Bit 21" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " CPB20 ,Clear Pending Bit 20" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " CPB19 ,Clear Pending Bit 19" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " CPB18 ,Clear Pending Bit 18" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " CPB17 ,Clear Pending Bit 17" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CPB16 ,Clear Pending Bit 16" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " CPB15 ,Clear Pending Bit 15" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " CPB14 ,Clear Pending Bit 14" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " CPB13 ,Clear Pending Bit 13" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " CPB12 ,Clear Pending Bit 12" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " CPB11 ,Clear Pending Bit 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 10. " CPB10 ,Clear Pending Bit 10" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " CPB9 ,Clear Pending Bit 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " CPB8 ,Clear Pending Bit 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CPB7 ,Clear Pending Bit 7" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " CPB6 ,Clear Pending Bit 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " CPB5 ,Clear Pending Bit 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CPB4 ,Clear Pending Bit 4" "Not pending,Pending"
|
|
eventfld.long 0x00 3. " CPB3 ,Clear Pending Bit 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " CPB2 ,Clear Pending Bit 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CPB1 ,Clear Pending Bit 1" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " CPB0 ,Clear Pending Bit 0" "Not pending,Pending"
|
|
group.long 0x1284++0x03
|
|
line.long 0x0 "GICD_ICPENDR1,Interrupt Clear Pending Register 1"
|
|
eventfld.long 0x00 31. " CPB63 ,Clear Pending Bit 63" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " CPB62 ,Clear Pending Bit 62" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " CPB61 ,Clear Pending Bit 61" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 28. " CPB60 ,Clear Pending Bit 60" "Not pending,Pending"
|
|
eventfld.long 0x00 27. " CPB59 ,Clear Pending Bit 59" "Not pending,Pending"
|
|
eventfld.long 0x00 26. " CPB58 ,Clear Pending Bit 58" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 25. " CPB57 ,Clear Pending Bit 57" "Not pending,Pending"
|
|
eventfld.long 0x00 24. " CPB56 ,Clear Pending Bit 56" "Not pending,Pending"
|
|
eventfld.long 0x00 23. " CPB55 ,Clear Pending Bit 55" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 22. " CPB54 ,Clear Pending Bit 54" "Not pending,Pending"
|
|
eventfld.long 0x00 21. " CPB53 ,Clear Pending Bit 53" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " CPB52 ,Clear Pending Bit 52" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " CPB51 ,Clear Pending Bit 51" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " CPB50 ,Clear Pending Bit 50" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " CPB49 ,Clear Pending Bit 49" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CPB48 ,Clear Pending Bit 48" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " CPB47 ,Clear Pending Bit 47" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " CPB46 ,Clear Pending Bit 46" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " CPB45 ,Clear Pending Bit 45" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " CPB44 ,Clear Pending Bit 44" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " CPB43 ,Clear Pending Bit 43" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 10. " CPB42 ,Clear Pending Bit 42" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " CPB41 ,Clear Pending Bit 41" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " CPB40 ,Clear Pending Bit 40" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CPB39 ,Clear Pending Bit 39" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " CPB38 ,Clear Pending Bit 38" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " CPB37 ,Clear Pending Bit 37" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CPB36 ,Clear Pending Bit 36" "Not pending,Pending"
|
|
eventfld.long 0x00 3. " CPB35 ,Clear Pending Bit 35" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " CPB34 ,Clear Pending Bit 34" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CPB33 ,Clear Pending Bit 33" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " CPB32 ,Clear Pending Bit 32" "Not pending,Pending"
|
|
group.long 0x1288++0x03
|
|
line.long 0x0 "GICD_ICPENDR2,Interrupt Clear Pending Register 2"
|
|
eventfld.long 0x00 31. " CPB95 ,Clear Pending Bit 95" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " CPB94 ,Clear Pending Bit 94" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " CPB93 ,Clear Pending Bit 93" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 28. " CPB92 ,Clear Pending Bit 92" "Not pending,Pending"
|
|
eventfld.long 0x00 27. " CPB91 ,Clear Pending Bit 91" "Not pending,Pending"
|
|
eventfld.long 0x00 26. " CPB90 ,Clear Pending Bit 90" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 25. " CPB89 ,Clear Pending Bit 89" "Not pending,Pending"
|
|
eventfld.long 0x00 24. " CPB88 ,Clear Pending Bit 88" "Not pending,Pending"
|
|
eventfld.long 0x00 23. " CPB87 ,Clear Pending Bit 87" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 22. " CPB86 ,Clear Pending Bit 86" "Not pending,Pending"
|
|
eventfld.long 0x00 21. " CPB85 ,Clear Pending Bit 85" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " CPB84 ,Clear Pending Bit 84" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " CPB83 ,Clear Pending Bit 83" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " CPB82 ,Clear Pending Bit 82" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " CPB81 ,Clear Pending Bit 81" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CPB80 ,Clear Pending Bit 80" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " CPB79 ,Clear Pending Bit 79" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " CPB78 ,Clear Pending Bit 78" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " CPB77 ,Clear Pending Bit 77" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " CPB76 ,Clear Pending Bit 76" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " CPB75 ,Clear Pending Bit 75" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 10. " CPB74 ,Clear Pending Bit 74" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " CPB73 ,Clear Pending Bit 73" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " CPB72 ,Clear Pending Bit 72" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CPB71 ,Clear Pending Bit 71" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " CPB70 ,Clear Pending Bit 70" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " CPB69 ,Clear Pending Bit 69" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CPB68 ,Clear Pending Bit 68" "Not pending,Pending"
|
|
eventfld.long 0x00 3. " CPB67 ,Clear Pending Bit 67" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " CPB66 ,Clear Pending Bit 66" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CPB65 ,Clear Pending Bit 65" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " CPB64 ,Clear Pending Bit 64" "Not pending,Pending"
|
|
group.long 0x128C++0x03
|
|
line.long 0x0 "GICD_ICPENDR3,Interrupt Clear Pending Register 3"
|
|
eventfld.long 0x00 31. " CPB127 ,Clear Pending Bit 127" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " CPB126 ,Clear Pending Bit 126" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " CPB125 ,Clear Pending Bit 125" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 28. " CPB124 ,Clear Pending Bit 124" "Not pending,Pending"
|
|
eventfld.long 0x00 27. " CPB123 ,Clear Pending Bit 123" "Not pending,Pending"
|
|
eventfld.long 0x00 26. " CPB122 ,Clear Pending Bit 122" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 25. " CPB121 ,Clear Pending Bit 121" "Not pending,Pending"
|
|
eventfld.long 0x00 24. " CPB120 ,Clear Pending Bit 120" "Not pending,Pending"
|
|
eventfld.long 0x00 23. " CPB119 ,Clear Pending Bit 119" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 22. " CPB118 ,Clear Pending Bit 118" "Not pending,Pending"
|
|
eventfld.long 0x00 21. " CPB117 ,Clear Pending Bit 117" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " CPB116 ,Clear Pending Bit 116" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " CPB115 ,Clear Pending Bit 115" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " CPB114 ,Clear Pending Bit 114" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " CPB113 ,Clear Pending Bit 113" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CPB112 ,Clear Pending Bit 112" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " CPB111 ,Clear Pending Bit 111" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " CPB110 ,Clear Pending Bit 110" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " CPB109 ,Clear Pending Bit 109" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " CPB108 ,Clear Pending Bit 108" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " CPB107 ,Clear Pending Bit 107" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 10. " CPB106 ,Clear Pending Bit 106" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " CPB105 ,Clear Pending Bit 105" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " CPB104 ,Clear Pending Bit 104" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CPB103 ,Clear Pending Bit 103" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " CPB102 ,Clear Pending Bit 102" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " CPB101 ,Clear Pending Bit 101" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CPB100 ,Clear Pending Bit 100" "Not pending,Pending"
|
|
eventfld.long 0x00 3. " CPB99 ,Clear Pending Bit 99" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " CPB98 ,Clear Pending Bit 98" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CPB97 ,Clear Pending Bit 97" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " CPB96 ,Clear Pending Bit 96" "Not pending,Pending"
|
|
group.long 0x1290++0x03
|
|
line.long 0x0 "GICD_ICPENDR4,Interrupt Clear Pending Register 4"
|
|
eventfld.long 0x00 31. " CPB159 ,Clear Pending Bit 159" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " CPB158 ,Clear Pending Bit 158" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " CPB157 ,Clear Pending Bit 157" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 28. " CPB156 ,Clear Pending Bit 156" "Not pending,Pending"
|
|
eventfld.long 0x00 27. " CPB155 ,Clear Pending Bit 155" "Not pending,Pending"
|
|
eventfld.long 0x00 26. " CPB154 ,Clear Pending Bit 154" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 25. " CPB153 ,Clear Pending Bit 153" "Not pending,Pending"
|
|
eventfld.long 0x00 24. " CPB152 ,Clear Pending Bit 152" "Not pending,Pending"
|
|
eventfld.long 0x00 23. " CPB151 ,Clear Pending Bit 151" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 22. " CPB150 ,Clear Pending Bit 150" "Not pending,Pending"
|
|
eventfld.long 0x00 21. " CPB149 ,Clear Pending Bit 149" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " CPB148 ,Clear Pending Bit 148" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " CPB147 ,Clear Pending Bit 147" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " CPB146 ,Clear Pending Bit 146" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " CPB145 ,Clear Pending Bit 145" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CPB144 ,Clear Pending Bit 144" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " CPB143 ,Clear Pending Bit 143" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " CPB142 ,Clear Pending Bit 142" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " CPB141 ,Clear Pending Bit 141" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " CPB140 ,Clear Pending Bit 140" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " CPB139 ,Clear Pending Bit 139" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 10. " CPB138 ,Clear Pending Bit 138" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " CPB137 ,Clear Pending Bit 137" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " CPB136 ,Clear Pending Bit 136" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CPB135 ,Clear Pending Bit 135" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " CPB134 ,Clear Pending Bit 134" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " CPB133 ,Clear Pending Bit 133" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CPB132 ,Clear Pending Bit 132" "Not pending,Pending"
|
|
eventfld.long 0x00 3. " CPB131 ,Clear Pending Bit 131" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " CPB130 ,Clear Pending Bit 130" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CPB129 ,Clear Pending Bit 129" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " CPB128 ,Clear Pending Bit 128" "Not pending,Pending"
|
|
group.long 0x1294++0x03
|
|
line.long 0x0 "GICD_ICPENDR5,Interrupt Clear Pending Register 5"
|
|
eventfld.long 0x00 31. " CPB191 ,Clear Pending Bit 191" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " CPB190 ,Clear Pending Bit 190" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " CPB189 ,Clear Pending Bit 189" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 28. " CPB188 ,Clear Pending Bit 188" "Not pending,Pending"
|
|
eventfld.long 0x00 27. " CPB187 ,Clear Pending Bit 187" "Not pending,Pending"
|
|
eventfld.long 0x00 26. " CPB186 ,Clear Pending Bit 186" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 25. " CPB185 ,Clear Pending Bit 185" "Not pending,Pending"
|
|
eventfld.long 0x00 24. " CPB184 ,Clear Pending Bit 184" "Not pending,Pending"
|
|
eventfld.long 0x00 23. " CPB183 ,Clear Pending Bit 183" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 22. " CPB182 ,Clear Pending Bit 182" "Not pending,Pending"
|
|
eventfld.long 0x00 21. " CPB181 ,Clear Pending Bit 181" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " CPB180 ,Clear Pending Bit 180" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " CPB179 ,Clear Pending Bit 179" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " CPB178 ,Clear Pending Bit 178" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " CPB177 ,Clear Pending Bit 177" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CPB176 ,Clear Pending Bit 176" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " CPB175 ,Clear Pending Bit 175" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " CPB174 ,Clear Pending Bit 174" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " CPB173 ,Clear Pending Bit 173" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " CPB172 ,Clear Pending Bit 172" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " CPB171 ,Clear Pending Bit 171" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 10. " CPB170 ,Clear Pending Bit 170" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " CPB169 ,Clear Pending Bit 169" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " CPB168 ,Clear Pending Bit 168" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CPB167 ,Clear Pending Bit 167" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " CPB166 ,Clear Pending Bit 166" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " CPB165 ,Clear Pending Bit 165" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CPB164 ,Clear Pending Bit 164" "Not pending,Pending"
|
|
eventfld.long 0x00 3. " CPB163 ,Clear Pending Bit 163" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " CPB162 ,Clear Pending Bit 162" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CPB161 ,Clear Pending Bit 161" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " CPB160 ,Clear Pending Bit 160" "Not pending,Pending"
|
|
group.long 0x1298++0x03
|
|
line.long 0x0 "GICD_ICPENDR6,Interrupt Clear Pending Register 6"
|
|
eventfld.long 0x00 31. " CPB223 ,Clear Pending Bit 223" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " CPB222 ,Clear Pending Bit 222" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " CPB221 ,Clear Pending Bit 221" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 28. " CPB220 ,Clear Pending Bit 220" "Not pending,Pending"
|
|
eventfld.long 0x00 27. " CPB219 ,Clear Pending Bit 219" "Not pending,Pending"
|
|
eventfld.long 0x00 26. " CPB218 ,Clear Pending Bit 218" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 25. " CPB217 ,Clear Pending Bit 217" "Not pending,Pending"
|
|
eventfld.long 0x00 24. " CPB216 ,Clear Pending Bit 216" "Not pending,Pending"
|
|
eventfld.long 0x00 23. " CPB215 ,Clear Pending Bit 215" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 22. " CPB214 ,Clear Pending Bit 214" "Not pending,Pending"
|
|
eventfld.long 0x00 21. " CPB213 ,Clear Pending Bit 213" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " CPB212 ,Clear Pending Bit 212" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " CPB211 ,Clear Pending Bit 211" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " CPB210 ,Clear Pending Bit 210" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " CPB209 ,Clear Pending Bit 209" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CPB208 ,Clear Pending Bit 208" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " CPB207 ,Clear Pending Bit 207" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " CPB206 ,Clear Pending Bit 206" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " CPB205 ,Clear Pending Bit 205" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " CPB204 ,Clear Pending Bit 204" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " CPB203 ,Clear Pending Bit 203" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 10. " CPB202 ,Clear Pending Bit 202" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " CPB201 ,Clear Pending Bit 201" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " CPB200 ,Clear Pending Bit 200" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CPB199 ,Clear Pending Bit 199" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " CPB198 ,Clear Pending Bit 198" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " CPB197 ,Clear Pending Bit 197" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CPB196 ,Clear Pending Bit 196" "Not pending,Pending"
|
|
eventfld.long 0x00 3. " CPB195 ,Clear Pending Bit 195" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " CPB194 ,Clear Pending Bit 194" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CPB193 ,Clear Pending Bit 193" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " CPB192 ,Clear Pending Bit 192" "Not pending,Pending"
|
|
group.long 0x129C++0x03
|
|
line.long 0x0 "GICD_ICPENDR7,Interrupt Clear Pending Register 7"
|
|
eventfld.long 0x00 31. " CPB255 ,Clear Pending Bit 255" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " CPB254 ,Clear Pending Bit 254" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " CPB253 ,Clear Pending Bit 253" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 28. " CPB252 ,Clear Pending Bit 252" "Not pending,Pending"
|
|
eventfld.long 0x00 27. " CPB251 ,Clear Pending Bit 251" "Not pending,Pending"
|
|
eventfld.long 0x00 26. " CPB250 ,Clear Pending Bit 250" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 25. " CPB249 ,Clear Pending Bit 249" "Not pending,Pending"
|
|
eventfld.long 0x00 24. " CPB248 ,Clear Pending Bit 248" "Not pending,Pending"
|
|
eventfld.long 0x00 23. " CPB247 ,Clear Pending Bit 247" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 22. " CPB246 ,Clear Pending Bit 246" "Not pending,Pending"
|
|
eventfld.long 0x00 21. " CPB245 ,Clear Pending Bit 245" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " CPB244 ,Clear Pending Bit 244" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " CPB243 ,Clear Pending Bit 243" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " CPB242 ,Clear Pending Bit 242" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " CPB241 ,Clear Pending Bit 241" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CPB240 ,Clear Pending Bit 240" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " CPB239 ,Clear Pending Bit 239" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " CPB238 ,Clear Pending Bit 238" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " CPB237 ,Clear Pending Bit 237" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " CPB236 ,Clear Pending Bit 236" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " CPB235 ,Clear Pending Bit 235" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 10. " CPB234 ,Clear Pending Bit 234" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " CPB233 ,Clear Pending Bit 233" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " CPB232 ,Clear Pending Bit 232" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CPB231 ,Clear Pending Bit 231" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " CPB230 ,Clear Pending Bit 230" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " CPB229 ,Clear Pending Bit 229" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CPB228 ,Clear Pending Bit 228" "Not pending,Pending"
|
|
eventfld.long 0x00 3. " CPB227 ,Clear Pending Bit 227" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " CPB226 ,Clear Pending Bit 226" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CPB225 ,Clear Pending Bit 225" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " CPB224 ,Clear Pending Bit 224" "Not pending,Pending"
|
|
group.long 0x12a0++0x03
|
|
line.long 0x0 "GICD_ICPENDR8,Interrupt Clear Pending Register 8"
|
|
eventfld.long 0x00 31. " CPB287 ,Clear Pending Bit 287" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " CPB286 ,Clear Pending Bit 286" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " CPB285 ,Clear Pending Bit 285" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 28. " CPB284 ,Clear Pending Bit 284" "Not pending,Pending"
|
|
eventfld.long 0x00 27. " CPB283 ,Clear Pending Bit 283" "Not pending,Pending"
|
|
eventfld.long 0x00 26. " CPB282 ,Clear Pending Bit 282" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 25. " CPB281 ,Clear Pending Bit 281" "Not pending,Pending"
|
|
eventfld.long 0x00 24. " CPB280 ,Clear Pending Bit 280" "Not pending,Pending"
|
|
eventfld.long 0x00 23. " CPB279 ,Clear Pending Bit 279" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 22. " CPB278 ,Clear Pending Bit 278" "Not pending,Pending"
|
|
eventfld.long 0x00 21. " CPB277 ,Clear Pending Bit 277" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " CPB276 ,Clear Pending Bit 276" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " CPB275 ,Clear Pending Bit 275" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " CPB274 ,Clear Pending Bit 274" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " CPB273 ,Clear Pending Bit 273" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CPB272 ,Clear Pending Bit 272" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " CPB271 ,Clear Pending Bit 271" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " CPB270 ,Clear Pending Bit 270" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " CPB269 ,Clear Pending Bit 269" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " CPB268 ,Clear Pending Bit 268" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " CPB267 ,Clear Pending Bit 267" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 10. " CPB266 ,Clear Pending Bit 266" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " CPB265 ,Clear Pending Bit 265" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " CPB264 ,Clear Pending Bit 264" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CPB263 ,Clear Pending Bit 263" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " CPB262 ,Clear Pending Bit 262" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " CPB261 ,Clear Pending Bit 261" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CPB260 ,Clear Pending Bit 260" "Not pending,Pending"
|
|
eventfld.long 0x00 3. " CPB259 ,Clear Pending Bit 259" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " CPB258 ,Clear Pending Bit 258" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CPB257 ,Clear Pending Bit 257" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " CPB256 ,Clear Pending Bit 256" "Not pending,Pending"
|
|
group.long 0x12a4++0x03
|
|
line.long 0x0 "GICD_ICPENDR9,Interrupt Clear Pending Register 9"
|
|
eventfld.long 0x00 31. " CPB319 ,Clear Pending Bit 319" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " CPB318 ,Clear Pending Bit 318" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " CPB317 ,Clear Pending Bit 317" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 28. " CPB316 ,Clear Pending Bit 316" "Not pending,Pending"
|
|
eventfld.long 0x00 27. " CPB315 ,Clear Pending Bit 315" "Not pending,Pending"
|
|
eventfld.long 0x00 26. " CPB314 ,Clear Pending Bit 314" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 25. " CPB313 ,Clear Pending Bit 313" "Not pending,Pending"
|
|
eventfld.long 0x00 24. " CPB312 ,Clear Pending Bit 312" "Not pending,Pending"
|
|
eventfld.long 0x00 23. " CPB311 ,Clear Pending Bit 311" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 22. " CPB310 ,Clear Pending Bit 310" "Not pending,Pending"
|
|
eventfld.long 0x00 21. " CPB309 ,Clear Pending Bit 309" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " CPB308 ,Clear Pending Bit 308" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " CPB307 ,Clear Pending Bit 307" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " CPB306 ,Clear Pending Bit 306" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " CPB305 ,Clear Pending Bit 305" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CPB304 ,Clear Pending Bit 304" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " CPB303 ,Clear Pending Bit 303" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " CPB302 ,Clear Pending Bit 302" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " CPB301 ,Clear Pending Bit 301" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " CPB300 ,Clear Pending Bit 300" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " CPB299 ,Clear Pending Bit 299" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 10. " CPB298 ,Clear Pending Bit 298" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " CPB297 ,Clear Pending Bit 297" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " CPB296 ,Clear Pending Bit 296" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CPB295 ,Clear Pending Bit 295" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " CPB294 ,Clear Pending Bit 294" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " CPB293 ,Clear Pending Bit 293" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CPB292 ,Clear Pending Bit 292" "Not pending,Pending"
|
|
eventfld.long 0x00 3. " CPB291 ,Clear Pending Bit 291" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " CPB290 ,Clear Pending Bit 290" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CPB289 ,Clear Pending Bit 289" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " CPB288 ,Clear Pending Bit 288" "Not pending,Pending"
|
|
group.long 0x12a8++0x03
|
|
line.long 0x0 "GICD_ICPENDR10,Interrupt Clear Pending Register 10"
|
|
eventfld.long 0x00 31. " CPB351 ,Clear Pending Bit 351" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " CPB350 ,Clear Pending Bit 350" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " CPB349 ,Clear Pending Bit 349" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 28. " CPB348 ,Clear Pending Bit 348" "Not pending,Pending"
|
|
eventfld.long 0x00 27. " CPB347 ,Clear Pending Bit 347" "Not pending,Pending"
|
|
eventfld.long 0x00 26. " CPB346 ,Clear Pending Bit 346" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 25. " CPB345 ,Clear Pending Bit 345" "Not pending,Pending"
|
|
eventfld.long 0x00 24. " CPB344 ,Clear Pending Bit 344" "Not pending,Pending"
|
|
eventfld.long 0x00 23. " CPB343 ,Clear Pending Bit 343" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 22. " CPB342 ,Clear Pending Bit 342" "Not pending,Pending"
|
|
eventfld.long 0x00 21. " CPB341 ,Clear Pending Bit 341" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " CPB340 ,Clear Pending Bit 340" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " CPB339 ,Clear Pending Bit 339" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " CPB338 ,Clear Pending Bit 338" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " CPB337 ,Clear Pending Bit 337" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CPB336 ,Clear Pending Bit 336" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " CPB335 ,Clear Pending Bit 335" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " CPB334 ,Clear Pending Bit 334" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " CPB333 ,Clear Pending Bit 333" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " CPB332 ,Clear Pending Bit 332" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " CPB331 ,Clear Pending Bit 331" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 10. " CPB330 ,Clear Pending Bit 330" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " CPB329 ,Clear Pending Bit 329" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " CPB328 ,Clear Pending Bit 328" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CPB327 ,Clear Pending Bit 327" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " CPB326 ,Clear Pending Bit 326" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " CPB325 ,Clear Pending Bit 325" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CPB324 ,Clear Pending Bit 324" "Not pending,Pending"
|
|
eventfld.long 0x00 3. " CPB323 ,Clear Pending Bit 323" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " CPB322 ,Clear Pending Bit 322" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CPB321 ,Clear Pending Bit 321" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " CPB320 ,Clear Pending Bit 320" "Not pending,Pending"
|
|
group.long 0x12ac++0x03
|
|
line.long 0x0 "GICD_ICPENDR11,Interrupt Clear Pending Register 11"
|
|
eventfld.long 0x00 31. " CPB383 ,Clear Pending Bit 383" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " CPB382 ,Clear Pending Bit 382" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " CPB381 ,Clear Pending Bit 381" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 28. " CPB380 ,Clear Pending Bit 380" "Not pending,Pending"
|
|
eventfld.long 0x00 27. " CPB379 ,Clear Pending Bit 379" "Not pending,Pending"
|
|
eventfld.long 0x00 26. " CPB378 ,Clear Pending Bit 378" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 25. " CPB377 ,Clear Pending Bit 377" "Not pending,Pending"
|
|
eventfld.long 0x00 24. " CPB376 ,Clear Pending Bit 376" "Not pending,Pending"
|
|
eventfld.long 0x00 23. " CPB375 ,Clear Pending Bit 375" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 22. " CPB374 ,Clear Pending Bit 374" "Not pending,Pending"
|
|
eventfld.long 0x00 21. " CPB373 ,Clear Pending Bit 373" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " CPB372 ,Clear Pending Bit 372" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " CPB371 ,Clear Pending Bit 371" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " CPB370 ,Clear Pending Bit 370" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " CPB369 ,Clear Pending Bit 369" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CPB368 ,Clear Pending Bit 368" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " CPB367 ,Clear Pending Bit 367" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " CPB366 ,Clear Pending Bit 366" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " CPB365 ,Clear Pending Bit 365" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " CPB364 ,Clear Pending Bit 364" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " CPB363 ,Clear Pending Bit 363" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 10. " CPB362 ,Clear Pending Bit 362" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " CPB361 ,Clear Pending Bit 361" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " CPB360 ,Clear Pending Bit 360" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CPB359 ,Clear Pending Bit 359" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " CPB358 ,Clear Pending Bit 358" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " CPB357 ,Clear Pending Bit 357" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CPB356 ,Clear Pending Bit 356" "Not pending,Pending"
|
|
eventfld.long 0x00 3. " CPB355 ,Clear Pending Bit 355" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " CPB354 ,Clear Pending Bit 354" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CPB353 ,Clear Pending Bit 353" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " CPB352 ,Clear Pending Bit 352" "Not pending,Pending"
|
|
group.long 0x12b0++0x03
|
|
line.long 0x0 "GICD_ICPENDR12,Interrupt Clear Pending Register 12"
|
|
eventfld.long 0x00 31. " CPB415 ,Clear Pending Bit 415" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " CPB414 ,Clear Pending Bit 414" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " CPB413 ,Clear Pending Bit 413" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 28. " CPB412 ,Clear Pending Bit 412" "Not pending,Pending"
|
|
eventfld.long 0x00 27. " CPB411 ,Clear Pending Bit 411" "Not pending,Pending"
|
|
eventfld.long 0x00 26. " CPB410 ,Clear Pending Bit 410" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 25. " CPB409 ,Clear Pending Bit 409" "Not pending,Pending"
|
|
eventfld.long 0x00 24. " CPB408 ,Clear Pending Bit 408" "Not pending,Pending"
|
|
eventfld.long 0x00 23. " CPB407 ,Clear Pending Bit 407" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 22. " CPB406 ,Clear Pending Bit 406" "Not pending,Pending"
|
|
eventfld.long 0x00 21. " CPB405 ,Clear Pending Bit 405" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " CPB404 ,Clear Pending Bit 404" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " CPB403 ,Clear Pending Bit 403" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " CPB402 ,Clear Pending Bit 402" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " CPB401 ,Clear Pending Bit 401" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CPB400 ,Clear Pending Bit 400" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " CPB399 ,Clear Pending Bit 399" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " CPB398 ,Clear Pending Bit 398" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " CPB397 ,Clear Pending Bit 397" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " CPB396 ,Clear Pending Bit 396" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " CPB395 ,Clear Pending Bit 395" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 10. " CPB394 ,Clear Pending Bit 394" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " CPB393 ,Clear Pending Bit 393" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " CPB392 ,Clear Pending Bit 392" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CPB391 ,Clear Pending Bit 391" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " CPB390 ,Clear Pending Bit 390" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " CPB389 ,Clear Pending Bit 389" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CPB388 ,Clear Pending Bit 388" "Not pending,Pending"
|
|
eventfld.long 0x00 3. " CPB387 ,Clear Pending Bit 387" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " CPB386 ,Clear Pending Bit 386" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CPB385 ,Clear Pending Bit 385" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " CPB384 ,Clear Pending Bit 384" "Not pending,Pending"
|
|
group.long 0x12b4++0x03
|
|
line.long 0x0 "GICD_ICPENDR13,Interrupt Clear Pending Register 13"
|
|
eventfld.long 0x00 31. " CPB447 ,Clear Pending Bit 447" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " CPB446 ,Clear Pending Bit 446" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " CPB445 ,Clear Pending Bit 445" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 28. " CPB444 ,Clear Pending Bit 444" "Not pending,Pending"
|
|
eventfld.long 0x00 27. " CPB443 ,Clear Pending Bit 443" "Not pending,Pending"
|
|
eventfld.long 0x00 26. " CPB442 ,Clear Pending Bit 442" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 25. " CPB441 ,Clear Pending Bit 441" "Not pending,Pending"
|
|
eventfld.long 0x00 24. " CPB440 ,Clear Pending Bit 440" "Not pending,Pending"
|
|
eventfld.long 0x00 23. " CPB439 ,Clear Pending Bit 439" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 22. " CPB438 ,Clear Pending Bit 438" "Not pending,Pending"
|
|
eventfld.long 0x00 21. " CPB437 ,Clear Pending Bit 437" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " CPB436 ,Clear Pending Bit 436" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " CPB435 ,Clear Pending Bit 435" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " CPB434 ,Clear Pending Bit 434" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " CPB433 ,Clear Pending Bit 433" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CPB432 ,Clear Pending Bit 432" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " CPB431 ,Clear Pending Bit 431" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " CPB430 ,Clear Pending Bit 430" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " CPB429 ,Clear Pending Bit 429" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " CPB428 ,Clear Pending Bit 428" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " CPB427 ,Clear Pending Bit 427" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 10. " CPB426 ,Clear Pending Bit 426" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " CPB425 ,Clear Pending Bit 425" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " CPB424 ,Clear Pending Bit 424" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CPB423 ,Clear Pending Bit 423" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " CPB422 ,Clear Pending Bit 422" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " CPB421 ,Clear Pending Bit 421" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CPB420 ,Clear Pending Bit 420" "Not pending,Pending"
|
|
eventfld.long 0x00 3. " CPB419 ,Clear Pending Bit 419" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " CPB418 ,Clear Pending Bit 418" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CPB417 ,Clear Pending Bit 417" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " CPB416 ,Clear Pending Bit 416" "Not pending,Pending"
|
|
group.long 0x12b8++0x03
|
|
line.long 0x0 "GICD_ICPENDR14,Interrupt Clear Pending Register 14"
|
|
eventfld.long 0x00 31. " CPB479 ,Clear Pending Bit 479" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " CPB478 ,Clear Pending Bit 478" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " CPB477 ,Clear Pending Bit 477" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 28. " CPB476 ,Clear Pending Bit 476" "Not pending,Pending"
|
|
eventfld.long 0x00 27. " CPB475 ,Clear Pending Bit 475" "Not pending,Pending"
|
|
eventfld.long 0x00 26. " CPB474 ,Clear Pending Bit 474" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 25. " CPB473 ,Clear Pending Bit 473" "Not pending,Pending"
|
|
eventfld.long 0x00 24. " CPB472 ,Clear Pending Bit 472" "Not pending,Pending"
|
|
eventfld.long 0x00 23. " CPB471 ,Clear Pending Bit 471" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 22. " CPB470 ,Clear Pending Bit 470" "Not pending,Pending"
|
|
eventfld.long 0x00 21. " CPB469 ,Clear Pending Bit 469" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " CPB468 ,Clear Pending Bit 468" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " CPB467 ,Clear Pending Bit 467" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " CPB466 ,Clear Pending Bit 466" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " CPB465 ,Clear Pending Bit 465" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CPB464 ,Clear Pending Bit 464" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " CPB463 ,Clear Pending Bit 463" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " CPB462 ,Clear Pending Bit 462" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " CPB461 ,Clear Pending Bit 461" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " CPB460 ,Clear Pending Bit 460" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " CPB459 ,Clear Pending Bit 459" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 10. " CPB458 ,Clear Pending Bit 458" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " CPB457 ,Clear Pending Bit 457" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " CPB456 ,Clear Pending Bit 456" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CPB455 ,Clear Pending Bit 455" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " CPB454 ,Clear Pending Bit 454" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " CPB453 ,Clear Pending Bit 453" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CPB452 ,Clear Pending Bit 452" "Not pending,Pending"
|
|
eventfld.long 0x00 3. " CPB451 ,Clear Pending Bit 451" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " CPB450 ,Clear Pending Bit 450" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CPB449 ,Clear Pending Bit 449" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " CPB448 ,Clear Pending Bit 448" "Not pending,Pending"
|
|
group.long 0x12bC++0x03
|
|
line.long 0x0 "GICD_ICPENDR15,Interrupt Clear Pending Register 15"
|
|
eventfld.long 0x00 31. " CPB511 ,Clear Pending Bit 511" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " CPB510 ,Clear Pending Bit 510" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " CPB509 ,Clear Pending Bit 509" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 28. " CPB508 ,Clear Pending Bit 508" "Not pending,Pending"
|
|
eventfld.long 0x00 27. " CPB507 ,Clear Pending Bit 507" "Not pending,Pending"
|
|
eventfld.long 0x00 26. " CPB506 ,Clear Pending Bit 506" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 25. " CPB505 ,Clear Pending Bit 505" "Not pending,Pending"
|
|
eventfld.long 0x00 24. " CPB504 ,Clear Pending Bit 504" "Not pending,Pending"
|
|
eventfld.long 0x00 23. " CPB503 ,Clear Pending Bit 503" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 22. " CPB502 ,Clear Pending Bit 502" "Not pending,Pending"
|
|
eventfld.long 0x00 21. " CPB501 ,Clear Pending Bit 501" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " CPB500 ,Clear Pending Bit 500" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " CPB499 ,Clear Pending Bit 499" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " CPB498 ,Clear Pending Bit 498" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " CPB497 ,Clear Pending Bit 497" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CPB496 ,Clear Pending Bit 496" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " CPB495 ,Clear Pending Bit 495" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " CPB494 ,Clear Pending Bit 494" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " CPB493 ,Clear Pending Bit 493" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " CPB492 ,Clear Pending Bit 492" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " CPB491 ,Clear Pending Bit 491" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 10. " CPB490 ,Clear Pending Bit 490" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " CPB489 ,Clear Pending Bit 489" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " CPB488 ,Clear Pending Bit 488" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CPB487 ,Clear Pending Bit 487" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " CPB486 ,Clear Pending Bit 486" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " CPB485 ,Clear Pending Bit 485" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CPB484 ,Clear Pending Bit 484" "Not pending,Pending"
|
|
eventfld.long 0x00 3. " CPB483 ,Clear Pending Bit 483" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " CPB482 ,Clear Pending Bit 482" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CPB481 ,Clear Pending Bit 481" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " CPB480 ,Clear Pending Bit 480" "Not pending,Pending"
|
|
textline " "
|
|
tree.end
|
|
width 20.
|
|
tree "Set/Clear Active Registers"
|
|
group.long 0x1300++0x03
|
|
line.long 0x0 "GICD_ISACTIVER0,Interrupt Set Active Register 0"
|
|
group.long 0x1304++0x03
|
|
line.long 0x0 "GICD_ISACTIVER1,Interrupt Set Active Register 1"
|
|
group.long 0x1308++0x03
|
|
line.long 0x0 "GICD_ISACTIVER2,Interrupt Set Active Register 2"
|
|
group.long 0x130C++0x03
|
|
line.long 0x0 "GICD_ISACTIVER3,Interrupt Set Active Register 3"
|
|
group.long 0x1310++0x03
|
|
line.long 0x0 "GICD_ISACTIVER4,Interrupt Set Active Register 4"
|
|
group.long 0x1314++0x03
|
|
line.long 0x0 "GICD_ISACTIVER5,Interrupt Set Active Register 5"
|
|
group.long 0x1318++0x03
|
|
line.long 0x0 "GICD_ISACTIVER6,Interrupt Set Active Register 6"
|
|
group.long 0x131C++0x03
|
|
line.long 0x0 "GICD_ISACTIVER7,Interrupt Set Active Register 7"
|
|
group.long 0x1320++0x03
|
|
line.long 0x0 "GICD_ISACTIVER8,Interrupt Set Active Register 8"
|
|
group.long 0x1324++0x03
|
|
line.long 0x0 "GICD_ISACTIVER9,Interrupt Set Active Register 9"
|
|
group.long 0x1328++0x03
|
|
line.long 0x0 "GICD_ISACTIVER10,Interrupt Set Active Register 10"
|
|
group.long 0x132C++0x03
|
|
line.long 0x0 "GICD_ISACTIVER11,Interrupt Set Active Register 11"
|
|
group.long 0x1330++0x03
|
|
line.long 0x0 "GICD_ISACTIVER12,Interrupt Set Active Register 12"
|
|
group.long 0x1334++0x03
|
|
line.long 0x0 "GICD_ISACTIVER13,Interrupt Set Active Register 13"
|
|
group.long 0x1338++0x03
|
|
line.long 0x0 "GICD_ISACTIVER14,Interrupt Set Active Register 14"
|
|
group.long 0x133C++0x03
|
|
line.long 0x0 "GICD_ISACTIVER15,Interrupt Set Active Register 15"
|
|
textline " "
|
|
group.long 0x1380++0x03
|
|
line.long 0x0 "GICD_ICACTIVER0,Interrupt Clear Active Register 0"
|
|
group.long 0x1384++0x03
|
|
line.long 0x0 "GICD_ICACTIVER1,Interrupt Clear Active Register 1"
|
|
group.long 0x1388++0x03
|
|
line.long 0x0 "GICD_ICACTIVER2,Interrupt Clear Active Register 2"
|
|
group.long 0x138C++0x03
|
|
line.long 0x0 "GICD_ICACTIVER3,Interrupt Clear Active Register 3"
|
|
group.long 0x1390++0x03
|
|
line.long 0x0 "GICD_ICACTIVER4,Interrupt Clear Active Register 4"
|
|
group.long 0x1394++0x03
|
|
line.long 0x0 "GICD_ICACTIVER5,Interrupt Clear Active Register 5"
|
|
group.long 0x1398++0x03
|
|
line.long 0x0 "GICD_ICACTIVER6,Interrupt Clear Active Register 6"
|
|
group.long 0x139C++0x03
|
|
line.long 0x0 "GICD_ICACTIVER7,Interrupt Clear Active Register 7"
|
|
group.long 0x13A0++0x03
|
|
line.long 0x0 "GICD_ICACTIVER8,Interrupt Clear Active Register 8"
|
|
group.long 0x13A4++0x03
|
|
line.long 0x0 "GICD_ICACTIVER9,Interrupt Clear Active Register 9"
|
|
group.long 0x13A8++0x03
|
|
line.long 0x0 "GICD_ICACTIVER10,Interrupt Clear Active Register 10"
|
|
group.long 0x13AC++0x03
|
|
line.long 0x0 "GICD_ICACTIVER11,Interrupt Clear Active Register 11"
|
|
group.long 0x13B0++0x03
|
|
line.long 0x0 "GICD_ICACTIVER12,Interrupt Clear Active Register 12"
|
|
group.long 0x13B4++0x03
|
|
line.long 0x0 "GICD_ICACTIVER13,Interrupt Clear Active Register 13"
|
|
group.long 0x13B8++0x03
|
|
line.long 0x0 "GICD_ICACTIVER14,Interrupt Clear Active Register 14"
|
|
group.long 0x13BC++0x03
|
|
line.long 0x0 "GICD_ICACTIVER15,Interrupt Clear Active Register 15"
|
|
textline " "
|
|
tree.end
|
|
tree "Priority Registers"
|
|
group.long 0x1400++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR0,Interrupt Priority Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1404++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR1,Interrupt Priority Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1408++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR2,Interrupt Priority Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x140C++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR3,Interrupt Priority Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1410++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR4,Interrupt Priority Register 4"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1414++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR5,Interrupt Priority Register 5"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1418++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR6,Interrupt Priority Register 6"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x141C++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR7,Interrupt Priority Register 7"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1420++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR8,Interrupt Priority Register 8"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1424++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR9,Interrupt Priority Register 9"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1428++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR10,Interrupt Priority Register 10"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x142C++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR11,Interrupt Priority Register 11"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1430++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR12,Interrupt Priority Register 12"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1434++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR13,Interrupt Priority Register 13"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1438++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR14,Interrupt Priority Register 14"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x143C++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR15,Interrupt Priority Register 15"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1440++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR16,Interrupt Priority Register 16"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1444++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR17,Interrupt Priority Register 17"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1448++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR18,Interrupt Priority Register 18"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x144C++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR19,Interrupt Priority Register 19"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1450++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR20,Interrupt Priority Register 20"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1454++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR21,Interrupt Priority Register 21"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1458++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR22,Interrupt Priority Register 22"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x145C++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR23,Interrupt Priority Register 23"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1460++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR24,Interrupt Priority Register 24"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1464++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR25,Interrupt Priority Register 25"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1468++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR26,Interrupt Priority Register 26"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x146C++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR27,Interrupt Priority Register 27"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1470++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR28,Interrupt Priority Register 28"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1474++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR29,Interrupt Priority Register 29"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1478++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR30,Interrupt Priority Register 30"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x147C++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR31,Interrupt Priority Register 31"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1480++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR32,Interrupt Priority Register 32"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1484++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR33,Interrupt Priority Register 33"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1488++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR34,Interrupt Priority Register 34"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x148C++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR35,Interrupt Priority Register 35"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1490++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR36,Interrupt Priority Register 36"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1494++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR37,Interrupt Priority Register 37"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1498++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR38,Interrupt Priority Register 38"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x149C++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR39,Interrupt Priority Register 39"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x14A0++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR40,Interrupt Priority Register 40"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x14A4++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR41,Interrupt Priority Register 41"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x14A8++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR42,Interrupt Priority Register 42"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x14AC++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR43,Interrupt Priority Register 43"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x14B0++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR44,Interrupt Priority Register 44"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x14B4++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR45,Interrupt Priority Register 45"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x14B8++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR46,Interrupt Priority Register 46"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x14BC++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR47,Interrupt Priority Register 47"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x14C0++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR48,Interrupt Priority Register 48"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x14C4++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR49,Interrupt Priority Register 49"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x14C8++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR50,Interrupt Priority Register 50"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x14CC++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR51,Interrupt Priority Register 51"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x14D0++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR52,Interrupt Priority Register 52"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x14D4++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR53,Interrupt Priority Register 53"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x14D8++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR54,Interrupt Priority Register 54"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x14DC++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR55,Interrupt Priority Register 55"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x14E0++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR56,Interrupt Priority Register 56"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x14E4++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR57,Interrupt Priority Register 57"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x14E8++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR58,Interrupt Priority Register 58"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x14EC++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR59,Interrupt Priority Register 59"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x14F0++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR60,Interrupt Priority Register 60"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x14F4++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR61,Interrupt Priority Register 61"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x14F8++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR62,Interrupt Priority Register 62"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x14FC++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR63,Interrupt Priority Register 63"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1500++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR64,Interrupt Priority Register 64"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1504++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR65,Interrupt Priority Register 65"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1508++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR66,Interrupt Priority Register 66"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x150C++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR67,Interrupt Priority Register 67"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1510++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR68,Interrupt Priority Register 68"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1514++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR69,Interrupt Priority Register 69"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1518++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR70,Interrupt Priority Register 70"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x151C++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR71,Interrupt Priority Register 71"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1520++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR72,Interrupt Priority Register 72"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1524++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR73,Interrupt Priority Register 73"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1528++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR74,Interrupt Priority Register 74"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x152C++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR75,Interrupt Priority Register 75"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1530++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR76,Interrupt Priority Register 76"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1534++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR77,Interrupt Priority Register 77"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1538++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR78,Interrupt Priority Register 78"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x153C++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR79,Interrupt Priority Register 79"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1540++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR80,Interrupt Priority Register 80"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1544++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR81,Interrupt Priority Register 81"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1548++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR82,Interrupt Priority Register 82"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x154C++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR83,Interrupt Priority Register 83"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1550++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR84,Interrupt Priority Register 84"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1554++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR85,Interrupt Priority Register 85"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1558++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR86,Interrupt Priority Register 86"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x155C++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR87,Interrupt Priority Register 87"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1560++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR88,Interrupt Priority Register 88"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1564++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR89,Interrupt Priority Register 89"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1568++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR90,Interrupt Priority Register 90"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x156C++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR91,Interrupt Priority Register 91"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1570++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR92,Interrupt Priority Register 92"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1574++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR93,Interrupt Priority Register 93"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1578++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR94,Interrupt Priority Register 94"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x157C++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR95,Interrupt Priority Register 95"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1580++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR96,Interrupt Priority Register 96"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1584++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR97,Interrupt Priority Register 97"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1588++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR98,Interrupt Priority Register 98"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x158C++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR99,Interrupt Priority Register 99"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1590++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR100,Interrupt Priority Register 100"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1594++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR101,Interrupt Priority Register 101"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x1598++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR102,Interrupt Priority Register 102"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x159C++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR103,Interrupt Priority Register 103"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x15A0++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR104,Interrupt Priority Register 104"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x15A4++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR105,Interrupt Priority Register 105"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x15A8++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR106,Interrupt Priority Register 106"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x15AC++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR107,Interrupt Priority Register 107"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x15B0++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR108,Interrupt Priority Register 108"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x15B4++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR109,Interrupt Priority Register 109"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x15B8++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR110,Interrupt Priority Register 110"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x15BC++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR111,Interrupt Priority Register 111"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x15C0++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR112,Interrupt Priority Register 112"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x15C4++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR113,Interrupt Priority Register 113"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x15C8++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR114,Interrupt Priority Register 114"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x15CC++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR115,Interrupt Priority Register 115"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x15D0++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR116,Interrupt Priority Register 116"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x15D4++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR117,Interrupt Priority Register 117"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x15D8++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR118,Interrupt Priority Register 118"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x15DC++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR119,Interrupt Priority Register 119"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x15E0++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR120,Interrupt Priority Register 120"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x15E4++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR121,Interrupt Priority Register 121"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x15E8++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR122,Interrupt Priority Register 122"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x15EC++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR123,Interrupt Priority Register 123"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x15F0++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR124,Interrupt Priority Register 124"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x15F4++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR125,Interrupt Priority Register 125"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x15F8++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR126,Interrupt Priority Register 126"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
group.long 0x15FC++0x03
|
|
line.long 0x0 "GICD_IPRIORITYR127,Interrupt Priority Register 127"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0"
|
|
textline " "
|
|
tree.end
|
|
tree "Processor Targets Registers"
|
|
rgroup.long 0x1800++0x03
|
|
line.long 0x0 "GICD_ITARGETSR0,Interrupt Processor Targets Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
rgroup.long 0x1804++0x03
|
|
line.long 0x0 "GICD_ITARGETSR1,Interrupt Processor Targets Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
rgroup.long 0x1808++0x03
|
|
line.long 0x0 "GICD_ITARGETSR2,Interrupt Processor Targets Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
rgroup.long 0x180C++0x03
|
|
line.long 0x0 "GICD_ITARGETSR3,Interrupt Processor Targets Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
rgroup.long 0x1810++0x03
|
|
line.long 0x0 "GICD_ITARGETSR4,Interrupt Processor Targets Register 4"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
rgroup.long 0x1814++0x03
|
|
line.long 0x0 "GICD_ITARGETSR5,Interrupt Processor Targets Register 5"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
rgroup.long 0x1818++0x03
|
|
line.long 0x0 "GICD_ITARGETSR6,Interrupt Processor Targets Register 6"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
rgroup.long 0x181C++0x03
|
|
line.long 0x0 "GICD_ITARGETSR7,Interrupt Processor Targets Register 7"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1820++0x03
|
|
line.long 0x0 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1824++0x03
|
|
line.long 0x0 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1828++0x03
|
|
line.long 0x0 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x182C++0x03
|
|
line.long 0x0 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1830++0x03
|
|
line.long 0x0 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1834++0x03
|
|
line.long 0x0 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1838++0x03
|
|
line.long 0x0 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x183C++0x03
|
|
line.long 0x0 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1840++0x03
|
|
line.long 0x0 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1844++0x03
|
|
line.long 0x0 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1848++0x03
|
|
line.long 0x0 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x184C++0x03
|
|
line.long 0x0 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1850++0x03
|
|
line.long 0x0 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1854++0x03
|
|
line.long 0x0 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1858++0x03
|
|
line.long 0x0 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x185C++0x03
|
|
line.long 0x0 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1860++0x03
|
|
line.long 0x0 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1864++0x03
|
|
line.long 0x0 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1868++0x03
|
|
line.long 0x0 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x186C++0x03
|
|
line.long 0x0 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1870++0x03
|
|
line.long 0x0 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1874++0x03
|
|
line.long 0x0 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1878++0x03
|
|
line.long 0x0 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x187C++0x03
|
|
line.long 0x0 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1880++0x03
|
|
line.long 0x0 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1884++0x03
|
|
line.long 0x0 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1888++0x03
|
|
line.long 0x0 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x188C++0x03
|
|
line.long 0x0 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1890++0x03
|
|
line.long 0x0 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1894++0x03
|
|
line.long 0x0 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1898++0x03
|
|
line.long 0x0 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x189C++0x03
|
|
line.long 0x0 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x18A0++0x03
|
|
line.long 0x0 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x18A4++0x03
|
|
line.long 0x0 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x18A8++0x03
|
|
line.long 0x0 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x18AC++0x03
|
|
line.long 0x0 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x18B0++0x03
|
|
line.long 0x0 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x18B4++0x03
|
|
line.long 0x0 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x18B8++0x03
|
|
line.long 0x0 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x18BC++0x03
|
|
line.long 0x0 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x18C0++0x03
|
|
line.long 0x0 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x18C4++0x03
|
|
line.long 0x0 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x18C8++0x03
|
|
line.long 0x0 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x18CC++0x03
|
|
line.long 0x0 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x18D0++0x03
|
|
line.long 0x0 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x18D4++0x03
|
|
line.long 0x0 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x18D8++0x03
|
|
line.long 0x0 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x18DC++0x03
|
|
line.long 0x0 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x18E0++0x03
|
|
line.long 0x0 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x18E4++0x03
|
|
line.long 0x0 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x18E8++0x03
|
|
line.long 0x0 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x18EC++0x03
|
|
line.long 0x0 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x18F0++0x03
|
|
line.long 0x0 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x18F4++0x03
|
|
line.long 0x0 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x18F8++0x03
|
|
line.long 0x0 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x18FC++0x03
|
|
line.long 0x0 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1900++0x03
|
|
line.long 0x0 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1904++0x03
|
|
line.long 0x0 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1908++0x03
|
|
line.long 0x0 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x190C++0x03
|
|
line.long 0x0 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1910++0x03
|
|
line.long 0x0 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1914++0x03
|
|
line.long 0x0 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1918++0x03
|
|
line.long 0x0 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x191C++0x03
|
|
line.long 0x0 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1920++0x03
|
|
line.long 0x0 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1924++0x03
|
|
line.long 0x0 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1928++0x03
|
|
line.long 0x0 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x192C++0x03
|
|
line.long 0x0 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1930++0x03
|
|
line.long 0x0 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1934++0x03
|
|
line.long 0x0 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1938++0x03
|
|
line.long 0x0 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x193C++0x03
|
|
line.long 0x0 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1940++0x03
|
|
line.long 0x0 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1944++0x03
|
|
line.long 0x0 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1948++0x03
|
|
line.long 0x0 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x194C++0x03
|
|
line.long 0x0 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1950++0x03
|
|
line.long 0x0 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1954++0x03
|
|
line.long 0x0 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1958++0x03
|
|
line.long 0x0 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x195C++0x03
|
|
line.long 0x0 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1960++0x03
|
|
line.long 0x0 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1964++0x03
|
|
line.long 0x0 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1968++0x03
|
|
line.long 0x0 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x196C++0x03
|
|
line.long 0x0 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1970++0x03
|
|
line.long 0x0 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1974++0x03
|
|
line.long 0x0 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1978++0x03
|
|
line.long 0x0 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x197C++0x03
|
|
line.long 0x0 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1980++0x03
|
|
line.long 0x0 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1984++0x03
|
|
line.long 0x0 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1988++0x03
|
|
line.long 0x0 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x198C++0x03
|
|
line.long 0x0 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1990++0x03
|
|
line.long 0x0 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1994++0x03
|
|
line.long 0x0 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x1998++0x03
|
|
line.long 0x0 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x199C++0x03
|
|
line.long 0x0 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x19A0++0x03
|
|
line.long 0x0 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x19A4++0x03
|
|
line.long 0x0 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x19A8++0x03
|
|
line.long 0x0 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x19AC++0x03
|
|
line.long 0x0 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x19B0++0x03
|
|
line.long 0x0 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x19B4++0x03
|
|
line.long 0x0 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x19B8++0x03
|
|
line.long 0x0 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x19BC++0x03
|
|
line.long 0x0 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x19C0++0x03
|
|
line.long 0x0 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x19C4++0x03
|
|
line.long 0x0 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x19C8++0x03
|
|
line.long 0x0 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x19CC++0x03
|
|
line.long 0x0 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x19D0++0x03
|
|
line.long 0x0 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x19D4++0x03
|
|
line.long 0x0 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x19D8++0x03
|
|
line.long 0x0 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x19DC++0x03
|
|
line.long 0x0 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x19E0++0x03
|
|
line.long 0x0 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x19E4++0x03
|
|
line.long 0x0 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x19E8++0x03
|
|
line.long 0x0 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x19EC++0x03
|
|
line.long 0x0 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x19F0++0x03
|
|
line.long 0x0 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x19F4++0x03
|
|
line.long 0x0 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x19F8++0x03
|
|
line.long 0x0 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
group.long 0x19FC++0x03
|
|
line.long 0x0 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0"
|
|
textline " "
|
|
tree.end
|
|
tree "Configuration Registers"
|
|
rgroup.long 0x1C00++0x03
|
|
line.long 0x00 "GICD_ICFGR0,Interrupt Configuration Register"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level"
|
|
rgroup.long 0x1C04++0x03
|
|
line.long 0x00 "GICD_ICFGR1,Interrupt Configuration Register"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level"
|
|
textline " "
|
|
group.long 0x1C08++0x03
|
|
line.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 0x1C08"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level"
|
|
textline " "
|
|
group.long 0x1C0C++0x03
|
|
line.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 0x1C0C"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level"
|
|
textline " "
|
|
group.long 0x1C10++0x03
|
|
line.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 0x1C10"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level"
|
|
textline " "
|
|
group.long 0x1C14++0x03
|
|
line.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 0x1C14"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level"
|
|
textline " "
|
|
group.long 0x1C18++0x03
|
|
line.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 0x1C18"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level"
|
|
textline " "
|
|
group.long 0x1C1C++0x03
|
|
line.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 0x1C1C"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level"
|
|
textline " "
|
|
group.long 0x1C20++0x03
|
|
line.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 0x1C20"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level"
|
|
textline " "
|
|
group.long 0x1C24++0x03
|
|
line.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 0x1C24"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level"
|
|
textline " "
|
|
group.long 0x1C28++0x03
|
|
line.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 0x1C28"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level"
|
|
textline " "
|
|
group.long 0x1C2C++0x03
|
|
line.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 0x1C2C"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level"
|
|
textline " "
|
|
group.long 0x1C30++0x03
|
|
line.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 0x1C30"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level"
|
|
textline " "
|
|
group.long 0x1C34++0x03
|
|
line.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 0x1C34"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level"
|
|
textline " "
|
|
group.long 0x1C38++0x03
|
|
line.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 0x1C38"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level"
|
|
textline " "
|
|
group.long 0x1C3C++0x03
|
|
line.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 0x1C3C"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level"
|
|
textline " "
|
|
group.long 0x1C40++0x03
|
|
line.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 0x1C40"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level"
|
|
textline " "
|
|
group.long 0x1C44++0x03
|
|
line.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 0x1C44"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level"
|
|
textline " "
|
|
group.long 0x1C48++0x03
|
|
line.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 0x1C48"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level"
|
|
textline " "
|
|
group.long 0x1C4C++0x03
|
|
line.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 0x1C4C"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level"
|
|
textline " "
|
|
group.long 0x1C50++0x03
|
|
line.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 0x1C50"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level"
|
|
textline " "
|
|
group.long 0x1C54++0x03
|
|
line.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 0x1C54"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level"
|
|
textline " "
|
|
group.long 0x1C58++0x03
|
|
line.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 0x1C58"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level"
|
|
textline " "
|
|
group.long 0x1C5C++0x03
|
|
line.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 0x1C5C"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level"
|
|
textline " "
|
|
group.long 0x1C60++0x03
|
|
line.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 0x1C60"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level"
|
|
textline " "
|
|
group.long 0x1C64++0x03
|
|
line.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 0x1C64"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level"
|
|
textline " "
|
|
group.long 0x1C68++0x03
|
|
line.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 0x1C68"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level"
|
|
textline " "
|
|
group.long 0x1C6C++0x03
|
|
line.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 0x1C6C"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level"
|
|
textline " "
|
|
group.long 0x1C70++0x03
|
|
line.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 0x1C70"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level"
|
|
textline " "
|
|
group.long 0x1C74++0x03
|
|
line.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 0x1C74"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level"
|
|
textline " "
|
|
group.long 0x1C78++0x03
|
|
line.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 0x1C78"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level"
|
|
textline " "
|
|
group.long 0x1C7C++0x03
|
|
line.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 0x1C7C"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level"
|
|
textline " "
|
|
tree.end
|
|
width 20.
|
|
tree "Private/Shared Peripheral Interrupt Status Registers"
|
|
rgroup.long 0x1D00++0x03
|
|
line.long 0x00 "GICD_PPISR,Private Peripheral Interrupt Status Register"
|
|
bitfld.long 0x00 15. " PPI3S ,nIRQ pin status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " PPI2S ,Non-secure Physical Timer event status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PPI1S ,Secure Physical Timer event status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " PPI0S ,nFIQ pin status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PPI4S ,Virtual Timer event status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " PPI5S ,Hypervisor Timer event status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PPI6S ,Virtual Maintenance Status" "No interrupt,Interrupt"
|
|
rgroup.long 0x1D04++0x03
|
|
line.long 0x00 "GICD_SPISR0,Shared Peripheral Interrupt Status Register"
|
|
bitfld.long 0x00 31. " IRQS[31] ,IRQS[31] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " IRQS[30] ,IRQS[30] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " IRQS[29] ,IRQS[29] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " IRQS[28] ,IRQS[28] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " IRQS[27] ,IRQS[27] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " IRQS[26] ,IRQS[26] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " IRQS[25] ,IRQS[25] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " IRQS[24] ,IRQS[24] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " IRQS[23] ,IRQS[23] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " IRQS[22] ,IRQS[22] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " IRQS[21] ,IRQS[21] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " IRQS[20] ,IRQS[20] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS[19] ,IRQS[19] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " IRQS[18] ,IRQS[18] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " IRQS[17] ,IRQS[17] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " IRQS[16] ,IRQS[16] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " IRQS[15] ,IRQS[15] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " IRQS[14] ,IRQS[14] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " IRQS[13] ,IRQS[13] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " IRQS[12] ,IRQS[12] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IRQS[11] ,IRQS[11] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " IRQS[10] ,IRQS[10] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " IRQS[9] ,IRQS[9] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " IRQS[8] ,IRQS[8] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS[7] ,IRQS[7] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " IRQS[6] ,IRQS[6] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " IRQS[5] ,IRQS[5] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " IRQS[4] ,IRQS[4] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IRQS[3] ,IRQS[3] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " IRQS[2] ,IRQS[2] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " IRQS[1] ,IRQS[1] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " IRQS[0] ,IRQS[0] status" "No interrupt,Interrupt"
|
|
rgroup.long 0x1D08++0x03
|
|
line.long 0x00 "GICD_SPISR1,Shared Peripheral Interrupt Status Register"
|
|
bitfld.long 0x00 31. " IRQS[63] ,IRQS[63] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " IRQS[62] ,IRQS[62] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " IRQS[61] ,IRQS[61] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " IRQS[60] ,IRQS[60] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " IRQS[59] ,IRQS[59] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " IRQS[58] ,IRQS[58] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " IRQS[57] ,IRQS[57] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " IRQS[56] ,IRQS[56] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " IRQS[55] ,IRQS[55] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " IRQS[54] ,IRQS[54] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " IRQS[53] ,IRQS[53] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " IRQS[52] ,IRQS[52] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS[51] ,IRQS[51] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " IRQS[50] ,IRQS[50] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " IRQS[49] ,IRQS[49] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " IRQS[48] ,IRQS[48] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " IRQS[47] ,IRQS[47] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " IRQS[46] ,IRQS[46] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " IRQS[45] ,IRQS[45] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " IRQS[44] ,IRQS[44] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IRQS[43] ,IRQS[43] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " IRQS[42] ,IRQS[42] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " IRQS[41] ,IRQS[41] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " IRQS[40] ,IRQS[40] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS[39] ,IRQS[39] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " IRQS[38] ,IRQS[38] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " IRQS[37] ,IRQS[37] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " IRQS[36] ,IRQS[36] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IRQS[35] ,IRQS[35] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " IRQS[34] ,IRQS[34] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " IRQS[33] ,IRQS[33] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " IRQS[32] ,IRQS[32] status" "No interrupt,Interrupt"
|
|
rgroup.long 0x1D0C++0x03
|
|
line.long 0x00 "GICD_SPISR2,Shared Peripheral Interrupt Status Register"
|
|
bitfld.long 0x00 31. " IRQS[95] ,IRQS[95] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " IRQS[94] ,IRQS[94] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " IRQS[93] ,IRQS[93] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " IRQS[92] ,IRQS[92] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " IRQS[91] ,IRQS[91] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " IRQS[90] ,IRQS[90] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " IRQS[89] ,IRQS[89] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " IRQS[88] ,IRQS[88] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " IRQS[87] ,IRQS[87] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " IRQS[86] ,IRQS[86] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " IRQS[85] ,IRQS[85] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " IRQS[84] ,IRQS[84] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS[83] ,IRQS[83] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " IRQS[82] ,IRQS[82] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " IRQS[81] ,IRQS[81] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " IRQS[80] ,IRQS[80] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " IRQS[79] ,IRQS[79] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " IRQS[78] ,IRQS[78] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " IRQS[77] ,IRQS[77] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " IRQS[76] ,IRQS[76] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IRQS[75] ,IRQS[75] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " IRQS[74] ,IRQS[74] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " IRQS[73] ,IRQS[73] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " IRQS[72] ,IRQS[72] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS[71] ,IRQS[71] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " IRQS[70] ,IRQS[70] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " IRQS[69] ,IRQS[69] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " IRQS[68] ,IRQS[68] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IRQS[67] ,IRQS[67] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " IRQS[66] ,IRQS[66] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " IRQS[65] ,IRQS[65] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " IRQS[64] ,IRQS[64] status" "No interrupt,Interrupt"
|
|
rgroup.long 0x1D10++0x03
|
|
line.long 0x00 "GICD_SPISR3,Shared Peripheral Interrupt Status Register"
|
|
bitfld.long 0x00 31. " IRQS[127] ,IRQS[127] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " IRQS[126] ,IRQS[126] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " IRQS[125] ,IRQS[125] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " IRQS[124] ,IRQS[124] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " IRQS[123] ,IRQS[123] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " IRQS[122] ,IRQS[122] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " IRQS[121] ,IRQS[121] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " IRQS[120] ,IRQS[120] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " IRQS[119] ,IRQS[119] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " IRQS[118] ,IRQS[118] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " IRQS[117] ,IRQS[117] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " IRQS[116] ,IRQS[116] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS[115] ,IRQS[115] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " IRQS[114] ,IRQS[114] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " IRQS[113] ,IRQS[113] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " IRQS[112] ,IRQS[112] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " IRQS[111] ,IRQS[111] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " IRQS[110] ,IRQS[110] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " IRQS[109] ,IRQS[109] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " IRQS[108] ,IRQS[108] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IRQS[107] ,IRQS[107] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " IRQS[106] ,IRQS[106] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " IRQS[105] ,IRQS[105] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " IRQS[104] ,IRQS[104] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS[103] ,IRQS[103] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " IRQS[102] ,IRQS[102] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " IRQS[101] ,IRQS[101] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " IRQS[100] ,IRQS[100] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IRQS[99] ,IRQS[99] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " IRQS[98] ,IRQS[98] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " IRQS[97] ,IRQS[97] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " IRQS[96] ,IRQS[96] status" "No interrupt,Interrupt"
|
|
rgroup.long 0x1D14++0x03
|
|
line.long 0x00 "GICD_SPISR4,Shared Peripheral Interrupt Status Register"
|
|
bitfld.long 0x00 31. " IRQS[159] ,IRQS[159] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " IRQS[158] ,IRQS[158] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " IRQS[157] ,IRQS[157] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " IRQS[156] ,IRQS[156] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " IRQS[155] ,IRQS[155] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " IRQS[154] ,IRQS[154] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " IRQS[153] ,IRQS[153] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " IRQS[152] ,IRQS[152] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " IRQS[151] ,IRQS[151] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " IRQS[150] ,IRQS[150] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " IRQS[149] ,IRQS[149] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " IRQS[148] ,IRQS[148] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS[147] ,IRQS[147] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " IRQS[146] ,IRQS[146] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " IRQS[145] ,IRQS[145] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " IRQS[144] ,IRQS[144] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " IRQS[143] ,IRQS[143] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " IRQS[142] ,IRQS[142] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " IRQS[141] ,IRQS[141] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " IRQS[140] ,IRQS[140] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IRQS[139] ,IRQS[139] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " IRQS[138] ,IRQS[138] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " IRQS[137] ,IRQS[137] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " IRQS[136] ,IRQS[136] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS[135] ,IRQS[135] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " IRQS[134] ,IRQS[134] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " IRQS[133] ,IRQS[133] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " IRQS[132] ,IRQS[132] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IRQS[131] ,IRQS[131] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " IRQS[130] ,IRQS[130] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " IRQS[129] ,IRQS[129] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " IRQS[128] ,IRQS[128] status" "No interrupt,Interrupt"
|
|
rgroup.long 0x1D18++0x03
|
|
line.long 0x00 "GICD_SPISR5,Shared Peripheral Interrupt Status Register"
|
|
bitfld.long 0x00 31. " IRQS[191] ,IRQS[191] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " IRQS[190] ,IRQS[190] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " IRQS[189] ,IRQS[189] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " IRQS[188] ,IRQS[188] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " IRQS[187] ,IRQS[187] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " IRQS[186] ,IRQS[186] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " IRQS[185] ,IRQS[185] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " IRQS[184] ,IRQS[184] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " IRQS[183] ,IRQS[183] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " IRQS[182] ,IRQS[182] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " IRQS[181] ,IRQS[181] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " IRQS[180] ,IRQS[180] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS[179] ,IRQS[179] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " IRQS[178] ,IRQS[178] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " IRQS[177] ,IRQS[177] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " IRQS[176] ,IRQS[176] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " IRQS[175] ,IRQS[175] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " IRQS[174] ,IRQS[174] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " IRQS[173] ,IRQS[173] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " IRQS[172] ,IRQS[172] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IRQS[171] ,IRQS[171] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " IRQS[170] ,IRQS[170] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " IRQS[169] ,IRQS[169] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " IRQS[168] ,IRQS[168] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS[167] ,IRQS[167] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " IRQS[166] ,IRQS[166] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " IRQS[165] ,IRQS[165] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " IRQS[164] ,IRQS[164] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IRQS[163] ,IRQS[163] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " IRQS[162] ,IRQS[162] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " IRQS[161] ,IRQS[161] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " IRQS[160] ,IRQS[160] status" "No interrupt,Interrupt"
|
|
rgroup.long 0x1D1C++0x03
|
|
line.long 0x00 "GICD_SPISR6,Shared Peripheral Interrupt Status Register"
|
|
bitfld.long 0x00 31. " IRQS[223] ,IRQS[223] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " IRQS[222] ,IRQS[222] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " IRQS[221] ,IRQS[221] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " IRQS[220] ,IRQS[220] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " IRQS[219] ,IRQS[219] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " IRQS[218] ,IRQS[218] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " IRQS[217] ,IRQS[217] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " IRQS[216] ,IRQS[216] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " IRQS[215] ,IRQS[215] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " IRQS[214] ,IRQS[214] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " IRQS[213] ,IRQS[213] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " IRQS[212] ,IRQS[212] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS[211] ,IRQS[211] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " IRQS[210] ,IRQS[210] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " IRQS[209] ,IRQS[209] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " IRQS[208] ,IRQS[208] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " IRQS[207] ,IRQS[207] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " IRQS[206] ,IRQS[206] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " IRQS[205] ,IRQS[205] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " IRQS[204] ,IRQS[204] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IRQS[203] ,IRQS[203] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " IRQS[202] ,IRQS[202] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " IRQS[201] ,IRQS[201] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " IRQS[200] ,IRQS[200] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS[199] ,IRQS[199] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " IRQS[198] ,IRQS[198] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " IRQS[197] ,IRQS[197] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " IRQS[196] ,IRQS[196] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IRQS[195] ,IRQS[195] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " IRQS[194] ,IRQS[194] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " IRQS[193] ,IRQS[193] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " IRQS[192] ,IRQS[192] status" "No interrupt,Interrupt"
|
|
rgroup.long 0x1D20++0x03
|
|
line.long 0x00 "GICD_SPISR7,Shared Peripheral Interrupt Status Register"
|
|
bitfld.long 0x00 31. " IRQS[255] ,IRQS[255] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " IRQS[254] ,IRQS[254] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " IRQS[253] ,IRQS[253] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " IRQS[252] ,IRQS[252] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " IRQS[251] ,IRQS[251] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " IRQS[250] ,IRQS[250] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " IRQS[249] ,IRQS[249] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " IRQS[248] ,IRQS[248] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " IRQS[247] ,IRQS[247] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " IRQS[246] ,IRQS[246] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " IRQS[245] ,IRQS[245] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " IRQS[244] ,IRQS[244] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS[243] ,IRQS[243] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " IRQS[242] ,IRQS[242] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " IRQS[241] ,IRQS[241] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " IRQS[240] ,IRQS[240] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " IRQS[239] ,IRQS[239] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " IRQS[238] ,IRQS[238] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " IRQS[237] ,IRQS[237] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " IRQS[236] ,IRQS[236] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IRQS[235] ,IRQS[235] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " IRQS[234] ,IRQS[234] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " IRQS[233] ,IRQS[233] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " IRQS[232] ,IRQS[232] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS[231] ,IRQS[231] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " IRQS[230] ,IRQS[230] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " IRQS[229] ,IRQS[229] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " IRQS[228] ,IRQS[228] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IRQS[227] ,IRQS[227] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " IRQS[226] ,IRQS[226] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " IRQS[225] ,IRQS[225] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " IRQS[224] ,IRQS[224] status" "No interrupt,Interrupt"
|
|
rgroup.long 0x1D24++0x03
|
|
line.long 0x00 "GICD_SPISR8,Shared Peripheral Interrupt Status Register"
|
|
bitfld.long 0x00 31. " IRQS[287] ,IRQS[287] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " IRQS[286] ,IRQS[286] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " IRQS[285] ,IRQS[285] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " IRQS[284] ,IRQS[284] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " IRQS[283] ,IRQS[283] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " IRQS[282] ,IRQS[282] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " IRQS[281] ,IRQS[281] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " IRQS[280] ,IRQS[280] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " IRQS[279] ,IRQS[279] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " IRQS[278] ,IRQS[278] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " IRQS[277] ,IRQS[277] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " IRQS[276] ,IRQS[276] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS[275] ,IRQS[275] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " IRQS[274] ,IRQS[274] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " IRQS[273] ,IRQS[273] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " IRQS[272] ,IRQS[272] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " IRQS[271] ,IRQS[271] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " IRQS[270] ,IRQS[270] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " IRQS[269] ,IRQS[269] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " IRQS[268] ,IRQS[268] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IRQS[267] ,IRQS[267] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " IRQS[266] ,IRQS[266] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " IRQS[265] ,IRQS[265] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " IRQS[264] ,IRQS[264] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS[263] ,IRQS[263] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " IRQS[262] ,IRQS[262] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " IRQS[261] ,IRQS[261] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " IRQS[260] ,IRQS[260] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IRQS[259] ,IRQS[259] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " IRQS[258] ,IRQS[258] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " IRQS[257] ,IRQS[257] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " IRQS[256] ,IRQS[256] status" "No interrupt,Interrupt"
|
|
rgroup.long 0x1D28++0x03
|
|
line.long 0x00 "GICD_SPISR9,Shared Peripheral Interrupt Status Register"
|
|
bitfld.long 0x00 31. " IRQS[319] ,IRQS[319] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " IRQS[318] ,IRQS[318] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " IRQS[317] ,IRQS[317] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " IRQS[316] ,IRQS[316] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " IRQS[315] ,IRQS[315] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " IRQS[314] ,IRQS[314] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " IRQS[313] ,IRQS[313] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " IRQS[312] ,IRQS[312] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " IRQS[311] ,IRQS[311] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " IRQS[310] ,IRQS[310] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " IRQS[309] ,IRQS[309] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " IRQS[308] ,IRQS[308] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS[307] ,IRQS[307] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " IRQS[306] ,IRQS[306] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " IRQS[305] ,IRQS[305] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " IRQS[304] ,IRQS[304] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " IRQS[303] ,IRQS[303] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " IRQS[302] ,IRQS[302] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " IRQS[301] ,IRQS[301] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " IRQS[300] ,IRQS[300] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IRQS[299] ,IRQS[299] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " IRQS[298] ,IRQS[298] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " IRQS[297] ,IRQS[297] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " IRQS[296] ,IRQS[296] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS[295] ,IRQS[295] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " IRQS[294] ,IRQS[294] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " IRQS[293] ,IRQS[293] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " IRQS[292] ,IRQS[292] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IRQS[291] ,IRQS[291] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " IRQS[290] ,IRQS[290] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " IRQS[289] ,IRQS[289] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " IRQS[288] ,IRQS[288] status" "No interrupt,Interrupt"
|
|
rgroup.long 0x1D2c++0x03
|
|
line.long 0x00 "GICD_SPISR10,Shared Peripheral Interrupt Status Register"
|
|
bitfld.long 0x00 31. " IRQS[351] ,IRQS[351] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " IRQS[350] ,IRQS[350] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " IRQS[349] ,IRQS[349] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " IRQS[348] ,IRQS[348] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " IRQS[347] ,IRQS[347] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " IRQS[346] ,IRQS[346] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " IRQS[345] ,IRQS[345] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " IRQS[344] ,IRQS[344] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " IRQS[343] ,IRQS[343] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " IRQS[342] ,IRQS[342] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " IRQS[341] ,IRQS[341] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " IRQS[340] ,IRQS[340] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS[339] ,IRQS[339] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " IRQS[338] ,IRQS[338] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " IRQS[337] ,IRQS[337] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " IRQS[336] ,IRQS[336] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " IRQS[335] ,IRQS[335] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " IRQS[334] ,IRQS[334] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " IRQS[333] ,IRQS[333] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " IRQS[332] ,IRQS[332] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IRQS[331] ,IRQS[331] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " IRQS[330] ,IRQS[330] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " IRQS[329] ,IRQS[329] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " IRQS[328] ,IRQS[328] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS[327] ,IRQS[327] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " IRQS[326] ,IRQS[326] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " IRQS[325] ,IRQS[325] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " IRQS[324] ,IRQS[324] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IRQS[323] ,IRQS[323] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " IRQS[322] ,IRQS[322] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " IRQS[321] ,IRQS[321] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " IRQS[320] ,IRQS[320] status" "No interrupt,Interrupt"
|
|
rgroup.long 0x1D30++0x03
|
|
line.long 0x00 "GICD_SPISR11,Shared Peripheral Interrupt Status Register"
|
|
bitfld.long 0x00 31. " IRQS[383] ,IRQS[383] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " IRQS[382] ,IRQS[382] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " IRQS[381] ,IRQS[381] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " IRQS[380] ,IRQS[380] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " IRQS[379] ,IRQS[379] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " IRQS[378] ,IRQS[378] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " IRQS[377] ,IRQS[377] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " IRQS[376] ,IRQS[376] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " IRQS[375] ,IRQS[375] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " IRQS[374] ,IRQS[374] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " IRQS[373] ,IRQS[373] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " IRQS[372] ,IRQS[372] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS[371] ,IRQS[371] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " IRQS[370] ,IRQS[370] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " IRQS[369] ,IRQS[369] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " IRQS[368] ,IRQS[368] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " IRQS[367] ,IRQS[367] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " IRQS[366] ,IRQS[366] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " IRQS[365] ,IRQS[365] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " IRQS[364] ,IRQS[364] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IRQS[363] ,IRQS[363] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " IRQS[362] ,IRQS[362] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " IRQS[361] ,IRQS[361] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " IRQS[360] ,IRQS[360] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS[359] ,IRQS[359] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " IRQS[358] ,IRQS[358] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " IRQS[357] ,IRQS[357] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " IRQS[356] ,IRQS[356] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IRQS[355] ,IRQS[355] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " IRQS[354] ,IRQS[354] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " IRQS[353] ,IRQS[353] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " IRQS[352] ,IRQS[352] status" "No interrupt,Interrupt"
|
|
rgroup.long 0x1D34++0x03
|
|
line.long 0x00 "GICD_SPISR12,Shared Peripheral Interrupt Status Register"
|
|
bitfld.long 0x00 31. " IRQS[415] ,IRQS[415] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " IRQS[414] ,IRQS[414] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " IRQS[413] ,IRQS[413] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " IRQS[412] ,IRQS[412] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " IRQS[411] ,IRQS[411] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " IRQS[410] ,IRQS[410] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " IRQS[409] ,IRQS[409] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " IRQS[408] ,IRQS[408] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " IRQS[407] ,IRQS[407] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " IRQS[406] ,IRQS[406] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " IRQS[405] ,IRQS[405] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " IRQS[404] ,IRQS[404] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS[403] ,IRQS[403] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " IRQS[402] ,IRQS[402] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " IRQS[401] ,IRQS[401] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " IRQS[400] ,IRQS[400] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " IRQS[399] ,IRQS[399] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " IRQS[398] ,IRQS[398] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " IRQS[397] ,IRQS[397] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " IRQS[396] ,IRQS[396] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IRQS[395] ,IRQS[395] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " IRQS[394] ,IRQS[394] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " IRQS[393] ,IRQS[393] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " IRQS[392] ,IRQS[392] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS[391] ,IRQS[391] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " IRQS[390] ,IRQS[390] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " IRQS[389] ,IRQS[389] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " IRQS[388] ,IRQS[388] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IRQS[387] ,IRQS[387] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " IRQS[386] ,IRQS[386] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " IRQS[385] ,IRQS[385] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " IRQS[384] ,IRQS[384] status" "No interrupt,Interrupt"
|
|
rgroup.long 0x1D38++0x03
|
|
line.long 0x00 "GICD_SPISR13,Shared Peripheral Interrupt Status Register"
|
|
bitfld.long 0x00 31. " IRQS[447] ,IRQS[447] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " IRQS[446] ,IRQS[446] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " IRQS[445] ,IRQS[445] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " IRQS[444] ,IRQS[444] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " IRQS[443] ,IRQS[443] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " IRQS[442] ,IRQS[442] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " IRQS[441] ,IRQS[441] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " IRQS[440] ,IRQS[440] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " IRQS[439] ,IRQS[439] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " IRQS[438] ,IRQS[438] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " IRQS[437] ,IRQS[437] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " IRQS[436] ,IRQS[436] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS[435] ,IRQS[435] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " IRQS[434] ,IRQS[434] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " IRQS[433] ,IRQS[433] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " IRQS[432] ,IRQS[432] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " IRQS[431] ,IRQS[431] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " IRQS[430] ,IRQS[430] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " IRQS[429] ,IRQS[429] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " IRQS[428] ,IRQS[428] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IRQS[427] ,IRQS[427] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " IRQS[426] ,IRQS[426] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " IRQS[425] ,IRQS[425] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " IRQS[424] ,IRQS[424] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS[423] ,IRQS[423] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " IRQS[422] ,IRQS[422] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " IRQS[421] ,IRQS[421] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " IRQS[420] ,IRQS[420] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IRQS[419] ,IRQS[419] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " IRQS[418] ,IRQS[418] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " IRQS[417] ,IRQS[417] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " IRQS[416] ,IRQS[416] status" "No interrupt,Interrupt"
|
|
rgroup.long 0x1D3c++0x03
|
|
line.long 0x00 "GICD_SPISR14,Shared Peripheral Interrupt Status Register"
|
|
bitfld.long 0x00 31. " IRQS[479] ,IRQS[479] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " IRQS[478] ,IRQS[478] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " IRQS[477] ,IRQS[477] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " IRQS[476] ,IRQS[476] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " IRQS[475] ,IRQS[475] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " IRQS[474] ,IRQS[474] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " IRQS[473] ,IRQS[473] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " IRQS[472] ,IRQS[472] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " IRQS[471] ,IRQS[471] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " IRQS[470] ,IRQS[470] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " IRQS[469] ,IRQS[469] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " IRQS[468] ,IRQS[468] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS[467] ,IRQS[467] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " IRQS[466] ,IRQS[466] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " IRQS[465] ,IRQS[465] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " IRQS[464] ,IRQS[464] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " IRQS[463] ,IRQS[463] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " IRQS[462] ,IRQS[462] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " IRQS[461] ,IRQS[461] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " IRQS[460] ,IRQS[460] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IRQS[459] ,IRQS[459] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " IRQS[458] ,IRQS[458] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " IRQS[457] ,IRQS[457] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " IRQS[456] ,IRQS[456] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS[455] ,IRQS[455] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " IRQS[454] ,IRQS[454] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " IRQS[453] ,IRQS[453] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " IRQS[452] ,IRQS[452] status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IRQS[451] ,IRQS[451] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " IRQS[450] ,IRQS[450] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " IRQS[449] ,IRQS[449] status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " IRQS[448] ,IRQS[448] status" "No interrupt,Interrupt"
|
|
tree.end
|
|
textline " "
|
|
width 20.
|
|
wgroup.long 0x1F00++0x03
|
|
line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register"
|
|
bitfld.long 0x00 24.--25. " TLF ,Target List Filter" "Send to specified,Send to all,Send to interrupt,?..."
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTL ,CPU Target List"
|
|
bitfld.long 0x00 15. " NSATT ,NSATT" "Secure,Non-secure"
|
|
bitfld.long 0x00 0.--3. " SGINTID ,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1F10++0x03
|
|
line.long 0x00 "GICD_CPENDSGIR0,SGI Clear Pending Registers"
|
|
group.long 0x1F14++0x03
|
|
line.long 0x00 "GICD_CPENDSGIR1,SGI Clear Pending Registers"
|
|
group.long 0x1F18++0x03
|
|
line.long 0x00 "GICD_CPENDSGIR2,SGI Clear Pending Registers"
|
|
group.long 0x1F1C++0x03
|
|
line.long 0x00 "GICD_CPENDSGIR3,SGI Clear Pending Registers"
|
|
textline " "
|
|
group.long 0x1F20++0x03
|
|
line.long 0x00 "GICD_SPENDSGIR0,SGI Set Pending Registers"
|
|
group.long 0x1F24++0x03
|
|
line.long 0x00 "GICD_SPENDSGIR1,SGI Set Pending Registers"
|
|
group.long 0x1F28++0x03
|
|
line.long 0x00 "GICD_SPENDSGIR2,SGI Set Pending Registers"
|
|
group.long 0x1F2C++0x03
|
|
line.long 0x00 "GICD_SPENDSGIR3,SGI Set Pending Registers"
|
|
textline " "
|
|
rgroup.long 0x1FE0++0x03 "Peripheral/Component ID Registers"
|
|
line.long 0x00 "GICD_PIDR0,Peripheral ID0 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DEVID ,DevID field"
|
|
rgroup.long 0x1FE4++0x03
|
|
line.long 0x00 "GICD_PIDR1,Peripheral ID1 Register"
|
|
bitfld.long 0x00 4.--7. " ARCHID ,ArchID field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DEVID ,DevID field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1FE8++0x03
|
|
line.long 0x00 "GICD_PIDR2,Peripheral ID2 Register"
|
|
bitfld.long 0x00 4.--7. " ARCHID ,ArchID field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 3. " UJEPCODE ,UsesJEPcode field" "Low,High"
|
|
bitfld.long 0x00 0.--2. " DEVID ,DevID field" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x1FEC++0x03
|
|
line.long 0x00 "GICD_PIDR3,Peripheral ID3 Register"
|
|
bitfld.long 0x00 4.--7. " REVID ,Revision field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1FD0++0x03
|
|
line.long 0x00 "GICD_PIDR4,Peripheral ID4 Register"
|
|
bitfld.long 0x00 0.--3. " CC ,ContinuationCode field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hgroup.long 0x1FD4++0x03
|
|
hide.long 0x00 "GICD_PIDR5,Peripheral ID5 Register"
|
|
hgroup.long 0x1FD8++0x03
|
|
hide.long 0x00 "GICD_PIDR6,Peripheral ID6 Register"
|
|
hgroup.long 0x1FDC++0x03
|
|
hide.long 0x00 "GICD_PIDR7,Peripheral ID7 Register"
|
|
textline " "
|
|
rgroup.long 0x1FF0++0x03
|
|
line.long 0x00 "GICD_CIDR0,Component ID0 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery"
|
|
rgroup.long 0x1FF4++0x03
|
|
line.long 0x00 "GICD_CIDR1,Component ID1 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery"
|
|
rgroup.long 0x1FF8++0x03
|
|
line.long 0x00 "GICD_CIDR2,Component ID2 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery"
|
|
rgroup.long 0x1FFC++0x03
|
|
line.long 0x00 "GICD_CIDR3,Component ID3 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery"
|
|
width 20.
|
|
group.long 0x2000++0x03 "Interrupt Controller Physical CPU Interface"
|
|
line.long 0x00 "GICC_CTLR,CPU Interface Control Register"
|
|
bitfld.long 0x00 4. " SBPR ,Secure/Non-secure Binary Point Register for preemption control" "SBPR for Secure/Non-SBPR for Non-Secure,SBPR for Both"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FIQEN ,Indicates using of FIQ or IRQ signal for interrupts" "IRQ,FIQ"
|
|
bitfld.long 0x00 2. " ACKCTL ,Interrupt acknowledge control" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENABLENS ,Global Enable for signalling of Non-secure interrupts" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLES ,Global Enable for signalling of Secure interrupts" "Disabled,Enabled"
|
|
group.long 0x2004++0x03
|
|
line.long 0x00 "GICC_PMR,Interrupt Priority Mask Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority mask level for CPU interface"
|
|
group.long 0x2008++0x03
|
|
line.long 0x00 "GICC_BPR,Binary Point Register"
|
|
bitfld.long 0x00 0.--2. " BP ,Binary point" "0,1,2,3,4,5,6,7"
|
|
hgroup.long 0x200C++0x03
|
|
hide.long 0x00 "GICC_IAR,Interrupt Acknowledge Register"
|
|
in
|
|
wgroup.long 0x2010++0x03
|
|
line.long 0x00 "GICC_EOIR,End Of Interrupt Register"
|
|
bitfld.long 0x00 10.--12. " CPUID ,CPU ID" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--9. 1. " EOIINTID ,ACKINTID value from the corresponding ICCIAR access"
|
|
rgroup.long 0x2014++0x03
|
|
line.long 0x00 "GICC_RPR,Running Priority Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority value of highest priority interrupt"
|
|
rgroup.long 0x2018++0x03
|
|
line.long 0x00 "GICC_HPIR,Highest Pending Interrupt Register"
|
|
bitfld.long 0x00 10.--12. " CPUID ,CPU ID" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--9. 1. " PENDINTID ,Interrupt ID of the highest priority pending interrupt"
|
|
group.long 0x201C++0x03
|
|
line.long 0x00 "GICC_ABPR,Aliased Binary Point Register"
|
|
rgroup.long 0x2020++0x03
|
|
line.long 0x00 "GICC_AIAR,Aliased Interrupt Acknowledge Register"
|
|
bitfld.long 0x00 10.--12. " CPUID ,Number of the CPU interface that made the request" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--9. 1. " INT_ID ,Interrupt ID"
|
|
wgroup.long 0x2024++0x03
|
|
line.long 0x00 "GICC_AEOIR,Aliased End of Interrupt Register"
|
|
bitfld.long 0x00 10.--12. " CPUID ,Number of the CPU interface that made the request" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--9. 1. " INT_ID ,Interrupt ID"
|
|
rgroup.long 0x2028++0x03
|
|
line.long 0x00 "GICC_AHPPIR,Aliased Highest Priority Pending Interrupt Register"
|
|
bitfld.long 0x00 10.--12. " CPUID ,Number of the CPU interface that made the request" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--9. 1. " INT_ID ,Interrupt ID"
|
|
group.long 0x20D0++0x03
|
|
line.long 0x00 "GICC_APR0,Active Priorities Register"
|
|
group.long 0x20E0++0x03
|
|
line.long 0x00 "GICC_NSAPR0,Non-Secure Active Priorities Register"
|
|
rgroup.long 0x20FC++0x03
|
|
line.long 0x00 "GICC_IIDR,CPU and Virtual CPU Interface Identification Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " PRODID ,Product ID"
|
|
bitfld.long 0x00 16.--19. " ARCH_VER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer"
|
|
wgroup.long 0x3000++0x03
|
|
line.long 0x00 "GICC_DIR,Deactivate Interrupt Register"
|
|
bitfld.long 0x00 10.--12. " CPUID ,Number of the CPU interface that made the request" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--9. 1. " INT_ID ,Interrupt ID"
|
|
width 20.
|
|
group.long 0x4000++0x03 "Interrupt Controller Virtual CPU Interface (Hypervisor view)"
|
|
line.long 0x00 "GICH_HCR,Hypervisor Control Register"
|
|
rgroup.long 0x4004++0x03
|
|
line.long 0x00 "GICH_VTR,VGIC Type Register"
|
|
bitfld.long 0x00 29.--31. " PRIBITS ,Number of priority bits" "Reserved,Reserved,Reserved,Reserved,5 bits 32 PRI levels,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26.--28. " PREBITS ,Number of pre-emption bits" "Reserved,Reserved,Reserved,Reserved,5 bits 32 PRE levels,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " LISTREGS ,List regs number" "Reserved,Reserved,Reserved,4 lists,?..."
|
|
group.long 0x4008++0x03
|
|
line.long 0x00 "GICH_VMCR,Virtual Machine Control Register"
|
|
rgroup.long 0x4010++0x03
|
|
line.long 0x00 "GICH_MISR,Maintenance Interrupt Status Register"
|
|
rgroup.long 0x4020++0x03
|
|
line.long 0x00 "GICH_EISR0,End of Interrupt Status Register"
|
|
rgroup.long 0x4030++0x03
|
|
line.long 0x00 "GICH_ELSR0,Empty List register Status Register"
|
|
group.long 0x40F0++0x03
|
|
line.long 0x00 "GICH_APR0,Active Priorities Register"
|
|
group.long 0x4100++0x03
|
|
line.long 0x00 "GICH_LR0,List Register 0"
|
|
group.long 0x4104++0x03
|
|
line.long 0x00 "GICH_LR1,List Register 1"
|
|
group.long 0x4108++0x03
|
|
line.long 0x00 "GICH_LR2,List Register 2"
|
|
group.long 0x410C++0x03
|
|
line.long 0x00 "GICH_LR3,List Register 3"
|
|
width 20.
|
|
group.long 0x6000++0x03 "Interrupt Controller Virtual CPU Interface (Virtual Machine View)"
|
|
line.long 0x00 "GICV_CTLR,VM Control Register"
|
|
group.long 0x6004++0x03
|
|
line.long 0x00 "GICV_PMR,VM Priority Mask Register"
|
|
group.long 0x6008++0x03
|
|
line.long 0x00 "GICV_BPR,VM Binary Point Register"
|
|
hgroup.long 0x600C++0x03
|
|
hide.long 0x00 "GICV_IAR,VM Interrupt Acknowledge Register"
|
|
in
|
|
wgroup.long 0x6010++0x03
|
|
line.long 0x00 "GICV_EOIR,VM End Of Interrupt Register"
|
|
rgroup.long 0x6014++0x03
|
|
line.long 0x00 "GICV_RPR,VM Running Priority Register"
|
|
rgroup.long 0x6018++0x03
|
|
line.long 0x00 "GICV_HPPIR,VM Highest Priority Pending Interrupt Register"
|
|
group.long 0x601C++0x03
|
|
line.long 0x00 "GICV_ABPR,VM Aliased Binary Point Register"
|
|
rgroup.long 0x6020++0x03
|
|
line.long 0x00 "GICV_AIAR,VM Aliased Interrupt Acknowledge Register"
|
|
wgroup.long 0x6024++0x03
|
|
line.long 0x00 "GICV_AEOIR,VM Aliased End of Interrupt Register"
|
|
rgroup.long 0x6028++0x03
|
|
line.long 0x00 "GICV_AHPPIR,VM Aliased Highest Priority Pending Interrupt Register"
|
|
group.long 0x60D0++0x03
|
|
line.long 0x00 "GICV_APR0,VM Active Priority Register"
|
|
rgroup.long 0x60FC++0x03
|
|
line.long 0x00 "GICV_IIDR,Virtual Machine CPU Interface Identification Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " PRODID ,Product ID"
|
|
bitfld.long 0x00 16.--19. " ARCH_VER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " REV ,Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer"
|
|
wgroup.long 0x7000++0x03
|
|
line.long 0x00 "GICV_DIR,VM Deactivate Interrupt Register"
|
|
tree.end
|
|
width 0x0b
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree "ACC (Analog Comparator Controller)"
|
|
base ad:0xE1600000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0: No effect.,1: Resets the module."
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 14. "FE,Fault Enable" "0: The FAULT output is tied to 0.,1: The FAULT output is driven by the signal defined.."
|
|
bitfld.long 0x0 13. "SELFS,Selection Of Fault Source" "0: The CE flag is used to drive the FAULT output.,1: The output of the analog comparator flag is used.."
|
|
newline
|
|
bitfld.long 0x0 12. "INV,Invert Comparator Output" "0: Analog comparator output is directly processed.,1: Analog comparator output is inverted prior to.."
|
|
bitfld.long 0x0 9.--10. "EDGETYP,Edge Type" "0: Only rising edge of comparator output,1: Falling edge of comparator output,2: Any edge of comparator output,?"
|
|
newline
|
|
bitfld.long 0x0 8. "ACEN,Analog Comparator Enable" "0: Analog comparator disabled.,1: Analog comparator enabled."
|
|
bitfld.long 0x0 4.--6. "SELPLUS,Selection For Plus Comparator Input" "0: Selects ACC_INP0,1: Selects ACC_INP1,2: Selects ACC_INP2,3: Selects ACC_INP3,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "SELMINUS,Selection for Minus Comparator Input" "0: Selects VBG,1: Selects ACC_INN1,2: Selects ACC_INN2,3: Selects ACC_INN3,?,?,?,?"
|
|
wgroup.long 0x24++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 0. "CE,Comparison Edge" "0: No effect.,1: Enables the interrupt when the selected edge.."
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 0. "CE,Comparison Edge" "0: No effect.,1: Disables the interrupt when the selected edge.."
|
|
rgroup.long 0x2C++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 0. "CE,Comparison Edge" "0: The interrupt is disabled.,1: The interrupt is enabled."
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 31. "MASK,Flag Mask" "0: The CE flag and SCO value are valid.,1: The CE flag and SCO value are invalid."
|
|
bitfld.long 0x4 1. "SCO,Synchronized Comparator Output" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CE,Comparison Edge (cleared on read)" "0: No edge occurred (defined by EDGETYP) on analog..,1: A selected edge (defined by EDGETYP) on analog.."
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "ACR,Analog Control Register"
|
|
bitfld.long 0x0 0. "MSEL,Masking Period Selection" "0: Masks AC output for 16 peripheral clock periods..,1: Masks AC output for 128 peripheral clock periods.."
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Configuration Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0: No write protection violation has occurred since..,1: A write protection violation (WPEN = 1) has.."
|
|
tree.end
|
|
tree "ADC (Analog-to-Digital Converter)"
|
|
base ad:0xE1000000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 4. "CMPRST,Comparison Restart" "0: No effect.,1: Stops the conversion result storage until the.."
|
|
bitfld.long 0x0 3. "SWFIFO,Software FIFO Reset" "0: No effect.,1: Resets the internal FIFO simulating a hardware.."
|
|
newline
|
|
bitfld.long 0x0 1. "START,Start Conversion" "0: No effect.,1: Begins analog-to-digital conversion."
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0: No effect.,1: Resets the ADC simulating a hardware reset."
|
|
group.long 0x4++0xB
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 31. "USEQ,User Sequence Enable" "0: Normal mode: The controller converts channels in..,1: User Sequence mode: The sequence respects what.."
|
|
bitfld.long 0x0 28.--29. "TRANSFER,Transfer Time" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--27. 1. "TRACKTIM,Tracking Time"
|
|
bitfld.long 0x0 23. "ANACH,Analog Change" "0: No analog change on channel switching: DIFF0 is..,1: Allows different analog settings for each.."
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "STARTUP,Startup Time"
|
|
hexmask.long.byte 0x0 8.--15. 1. "PRESCAL,Prescaler Rate Selection"
|
|
newline
|
|
bitfld.long 0x0 6. "FWUP,Fast Wakeup" "0: If SLEEP is 1 then both ADC core and reference..,1: If SLEEP is 1 then Fast Wakeup Sleep mode: The.."
|
|
bitfld.long 0x0 5. "SLEEP,Sleep Mode" "0: Normal mode: The ADC core and reference voltage..,1: Sleep mode: The wakeup time can be modified by.."
|
|
newline
|
|
bitfld.long 0x0 1.--3. "TRGSEL,Trigger Selection" "0: ADTRG,1: TIOA0 TC0,2: TIOA1 TC0,3: TIOA2 TC0,4: PWM event line 0,5: PWM event line 1,6: TIOA3/ACC,7: RTCOUT0"
|
|
line.long 0x4 "SEQR1,Channel Sequence Register 1"
|
|
hexmask.long.byte 0x4 28.--31. 1. "USCH8,User Sequence Number 8"
|
|
hexmask.long.byte 0x4 24.--27. 1. "USCH7,User Sequence Number 7"
|
|
newline
|
|
hexmask.long.byte 0x4 20.--23. 1. "USCH6,User Sequence Number 6"
|
|
hexmask.long.byte 0x4 16.--19. 1. "USCH5,User Sequence Number 5"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "USCH4,User Sequence Number 4"
|
|
hexmask.long.byte 0x4 8.--11. 1. "USCH3,User Sequence Number 3"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "USCH2,User Sequence Number 2"
|
|
hexmask.long.byte 0x4 0.--3. 1. "USCH1,User Sequence Number 1"
|
|
line.long 0x8 "SEQR2,Channel Sequence Register 2"
|
|
hexmask.long.byte 0x8 28.--31. 1. "USCH16,User Sequence Number 16"
|
|
hexmask.long.byte 0x8 24.--27. 1. "USCH15,User Sequence Number 15"
|
|
newline
|
|
hexmask.long.byte 0x8 20.--23. 1. "USCH14,User Sequence Number 14"
|
|
hexmask.long.byte 0x8 16.--19. 1. "USCH13,User Sequence Number 13"
|
|
newline
|
|
hexmask.long.byte 0x8 12.--15. 1. "USCH12,User Sequence Number 12"
|
|
hexmask.long.byte 0x8 8.--11. 1. "USCH11,User Sequence Number 11"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--7. 1. "USCH10,User Sequence Number 10"
|
|
hexmask.long.byte 0x8 0.--3. 1. "USCH9,User Sequence Number 9"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "CHER,Channel Enable Register"
|
|
bitfld.long 0x0 31. "CH31,Channel 31 Enable" "0: No effect.,1: Enables the corresponding channel."
|
|
bitfld.long 0x0 30. "CH30,Channel 30 Enable" "0: No effect.,1: Enables the corresponding channel."
|
|
newline
|
|
bitfld.long 0x0 15. "CH15,Channel 15 Enable" "0: No effect.,1: Enables the corresponding channel."
|
|
bitfld.long 0x0 14. "CH14,Channel 14 Enable" "0: No effect.,1: Enables the corresponding channel."
|
|
newline
|
|
bitfld.long 0x0 13. "CH13,Channel 13 Enable" "0: No effect.,1: Enables the corresponding channel."
|
|
bitfld.long 0x0 12. "CH12,Channel 12 Enable" "0: No effect.,1: Enables the corresponding channel."
|
|
newline
|
|
bitfld.long 0x0 11. "CH11,Channel 11 Enable" "0: No effect.,1: Enables the corresponding channel."
|
|
bitfld.long 0x0 10. "CH10,Channel 10 Enable" "0: No effect.,1: Enables the corresponding channel."
|
|
newline
|
|
bitfld.long 0x0 9. "CH9,Channel 9 Enable" "0: No effect.,1: Enables the corresponding channel."
|
|
bitfld.long 0x0 8. "CH8,Channel 8 Enable" "0: No effect.,1: Enables the corresponding channel."
|
|
newline
|
|
bitfld.long 0x0 7. "CH7,Channel 7 Enable" "0: No effect.,1: Enables the corresponding channel."
|
|
bitfld.long 0x0 6. "CH6,Channel 6 Enable" "0: No effect.,1: Enables the corresponding channel."
|
|
newline
|
|
bitfld.long 0x0 5. "CH5,Channel 5 Enable" "0: No effect.,1: Enables the corresponding channel."
|
|
bitfld.long 0x0 4. "CH4,Channel 4 Enable" "0: No effect.,1: Enables the corresponding channel."
|
|
newline
|
|
bitfld.long 0x0 3. "CH3,Channel 3 Enable" "0: No effect.,1: Enables the corresponding channel."
|
|
bitfld.long 0x0 2. "CH2,Channel 2 Enable" "0: No effect.,1: Enables the corresponding channel."
|
|
newline
|
|
bitfld.long 0x0 1. "CH1,Channel 1 Enable" "0: No effect.,1: Enables the corresponding channel."
|
|
bitfld.long 0x0 0. "CH0,Channel 0 Enable" "0: No effect.,1: Enables the corresponding channel."
|
|
line.long 0x4 "CHDR,Channel Disable Register"
|
|
bitfld.long 0x4 31. "CH31,Channel 31 Disable" "0: No effect.,1: Disables the corresponding channel."
|
|
bitfld.long 0x4 30. "CH30,Channel 30 Disable" "0: No effect.,1: Disables the corresponding channel."
|
|
newline
|
|
bitfld.long 0x4 15. "CH15,Channel 15 Disable" "0: No effect.,1: Disables the corresponding channel."
|
|
bitfld.long 0x4 14. "CH14,Channel 14 Disable" "0: No effect.,1: Disables the corresponding channel."
|
|
newline
|
|
bitfld.long 0x4 13. "CH13,Channel 13 Disable" "0: No effect.,1: Disables the corresponding channel."
|
|
bitfld.long 0x4 12. "CH12,Channel 12 Disable" "0: No effect.,1: Disables the corresponding channel."
|
|
newline
|
|
bitfld.long 0x4 11. "CH11,Channel 11 Disable" "0: No effect.,1: Disables the corresponding channel."
|
|
bitfld.long 0x4 10. "CH10,Channel 10 Disable" "0: No effect.,1: Disables the corresponding channel."
|
|
newline
|
|
bitfld.long 0x4 9. "CH9,Channel 9 Disable" "0: No effect.,1: Disables the corresponding channel."
|
|
bitfld.long 0x4 8. "CH8,Channel 8 Disable" "0: No effect.,1: Disables the corresponding channel."
|
|
newline
|
|
bitfld.long 0x4 7. "CH7,Channel 7 Disable" "0: No effect.,1: Disables the corresponding channel."
|
|
bitfld.long 0x4 6. "CH6,Channel 6 Disable" "0: No effect.,1: Disables the corresponding channel."
|
|
newline
|
|
bitfld.long 0x4 5. "CH5,Channel 5 Disable" "0: No effect.,1: Disables the corresponding channel."
|
|
bitfld.long 0x4 4. "CH4,Channel 4 Disable" "0: No effect.,1: Disables the corresponding channel."
|
|
newline
|
|
bitfld.long 0x4 3. "CH3,Channel 3 Disable" "0: No effect.,1: Disables the corresponding channel."
|
|
bitfld.long 0x4 2. "CH2,Channel 2 Disable" "0: No effect.,1: Disables the corresponding channel."
|
|
newline
|
|
bitfld.long 0x4 1. "CH1,Channel 1 Disable" "0: No effect.,1: Disables the corresponding channel."
|
|
bitfld.long 0x4 0. "CH0,Channel 0 Disable" "0: No effect.,1: Disables the corresponding channel."
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "CHSR,Channel Status Register"
|
|
bitfld.long 0x0 31. "CH31,Channel 31 Status" "0: The corresponding channel (or part of sequence..,1: The corresponding channel (or part of sequence.."
|
|
bitfld.long 0x0 30. "CH30,Channel 30 Status" "0: The corresponding channel (or part of sequence..,1: The corresponding channel (or part of sequence.."
|
|
newline
|
|
bitfld.long 0x0 15. "CH15,Channel 15 Status" "0: The corresponding channel (or part of sequence..,1: The corresponding channel (or part of sequence.."
|
|
bitfld.long 0x0 14. "CH14,Channel 14 Status" "0: The corresponding channel (or part of sequence..,1: The corresponding channel (or part of sequence.."
|
|
newline
|
|
bitfld.long 0x0 13. "CH13,Channel 13 Status" "0: The corresponding channel (or part of sequence..,1: The corresponding channel (or part of sequence.."
|
|
bitfld.long 0x0 12. "CH12,Channel 12 Status" "0: The corresponding channel (or part of sequence..,1: The corresponding channel (or part of sequence.."
|
|
newline
|
|
bitfld.long 0x0 11. "CH11,Channel 11 Status" "0: The corresponding channel (or part of sequence..,1: The corresponding channel (or part of sequence.."
|
|
bitfld.long 0x0 10. "CH10,Channel 10 Status" "0: The corresponding channel (or part of sequence..,1: The corresponding channel (or part of sequence.."
|
|
newline
|
|
bitfld.long 0x0 9. "CH9,Channel 9 Status" "0: The corresponding channel (or part of sequence..,1: The corresponding channel (or part of sequence.."
|
|
bitfld.long 0x0 8. "CH8,Channel 8 Status" "0: The corresponding channel (or part of sequence..,1: The corresponding channel (or part of sequence.."
|
|
newline
|
|
bitfld.long 0x0 7. "CH7,Channel 7 Status" "0: The corresponding channel (or part of sequence..,1: The corresponding channel (or part of sequence.."
|
|
bitfld.long 0x0 6. "CH6,Channel 6 Status" "0: The corresponding channel (or part of sequence..,1: The corresponding channel (or part of sequence.."
|
|
newline
|
|
bitfld.long 0x0 5. "CH5,Channel 5 Status" "0: The corresponding channel (or part of sequence..,1: The corresponding channel (or part of sequence.."
|
|
bitfld.long 0x0 4. "CH4,Channel 4 Status" "0: The corresponding channel (or part of sequence..,1: The corresponding channel (or part of sequence.."
|
|
newline
|
|
bitfld.long 0x0 3. "CH3,Channel 3 Status" "0: The corresponding channel (or part of sequence..,1: The corresponding channel (or part of sequence.."
|
|
bitfld.long 0x0 2. "CH2,Channel 2 Status" "0: The corresponding channel (or part of sequence..,1: The corresponding channel (or part of sequence.."
|
|
newline
|
|
bitfld.long 0x0 1. "CH1,Channel 1 Status" "0: The corresponding channel (or part of sequence..,1: The corresponding channel (or part of sequence.."
|
|
bitfld.long 0x0 0. "CH0,Channel 0 Status" "0: The corresponding channel (or part of sequence..,1: The corresponding channel (or part of sequence.."
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "LCDR,Last Converted Data Register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "CHNBOSR,Channel Number in Oversampling Mode"
|
|
hexmask.long.word 0x0 0.--15. 1. "LDATA,Last Data Converted"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "LCDR_NO_OSR_MODE,Last Converted Data Register"
|
|
hexmask.long.byte 0x0 12.--15. 1. "NO_OSR_CHNB,Channel Number when No Oversampling"
|
|
hexmask.long.word 0x0 0.--11. 1. "NO_OSR_LDATA,Last Data Converted when No Oversampling"
|
|
wgroup.long 0x24++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 26. "COMPE,Comparison Event Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 25. "GOVRE,General Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "DRDY,Data Ready Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 19. "TEMPCHG,Temperature Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "EOS,End Of Sequence Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 5. "RXOVR,Receive Over Flow Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXUDR,Receive Under Flow Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 3. "RXCHUNK,Receive FIFO Chunk Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXFULL,Receive FIFO Full Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "RXEMPTY,Receive FIFO Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,Receive Ready Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 26. "COMPE,Comparison Event Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 25. "GOVRE,General Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "DRDY,Data Ready Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 19. "TEMPCHG,Temperature Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "EOS,End Of Sequence Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 5. "RXOVR,Receive Over Flow Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXUDR,Receive Under Flow Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 3. "RXCHUNK,Receive FIFO Chunk Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXFULL,Receive FIFO Full Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 1. "RXEMPTY,Receive FIFO Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,Receive Ready Interrupt Disable" "0,1"
|
|
rgroup.long 0x2C++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 26. "COMPE,Comparison Event Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 25. "GOVRE,General Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "DRDY,Data Ready Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 19. "TEMPCHG,Temperature Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "EOS,End Of Sequence Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 5. "RXOVR,Receive Over Flow Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXUDR,Receive Under Flow Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 3. "RXCHUNK,Receive FIFO Chunk Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXFULL,Receive FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 1. "RXEMPTY,Receive FIFO Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,Receive Ready Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 26. "COMPE,Comparison Event (cleared on read)" "0: No comparison event occurred since the last read..,1: At least one comparison event (defined in.."
|
|
bitfld.long 0x4 25. "GOVRE,General Overrun Error (cleared on read)" "0: No general overrun error occurred since the last..,1: At least one general overrun error has occurred.."
|
|
newline
|
|
bitfld.long 0x4 24. "DRDY,Data Ready (automatically set / cleared)" "0: No data has been converted since the last read..,1: At least one data has been converted and is.."
|
|
bitfld.long 0x4 19. "TEMPCHG,Temperature Change (cleared on read)" "0: There is no comparison match (defined in the..,1: The temperature value reported on ADC_CDRmax.."
|
|
newline
|
|
bitfld.long 0x4 18. "EOS,End Of Sequence (cleared on read)" "0: No sequence is in progress or the sequence is..,1: The sequence is complete."
|
|
bitfld.long 0x4 5. "RXOVR,Receive Over Flow (cleared on read)" "0: No general overrun error occurred since the last..,1: At least one general overrun error has occurred.."
|
|
newline
|
|
bitfld.long 0x4 4. "RXUDR,Receive Under Flow (cleared on read)" "0: No general underrun error occurred since the..,1: At least one general underrun error has occurred.."
|
|
bitfld.long 0x4 3. "RXCHUNK,Receive FIFO Chunk (cleared on read)" "0: The number of written elements in the FIFO has..,1: The number of written elements in the FIFO has.."
|
|
newline
|
|
bitfld.long 0x4 2. "RXFULL,Receive FIFO Full (cleared on read)" "0: FIFO has not been full since the last read of..,1: FIFO has been full since the last read of ADC_ISR."
|
|
bitfld.long 0x4 1. "RXEMPTY,Receive FIFO Empty (cleared on read)" "0: FIFO has not been empty since the last read of..,1: FIFO has been empty since the last read of.."
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,Receive Ready (cleared on read)" "0: FIFO has been empty since the last read of..,1: One element has been written since the last read.."
|
|
wgroup.long 0x34++0x7
|
|
line.long 0x0 "EOC_IER,End Of Conversion Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "EOC31,End of Conversion Interrupt Enable 31" "0: No effect.,1: Enables the corresponding interrupt."
|
|
bitfld.long 0x0 30. "EOC30,End of Conversion Interrupt Enable 30" "0: No effect.,1: Enables the corresponding interrupt."
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bitfld.long 0x0 15. "EOC15,End of Conversion Interrupt Enable 15" "0: No effect.,1: Enables the corresponding interrupt."
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bitfld.long 0x0 14. "EOC14,End of Conversion Interrupt Enable 14" "0: No effect.,1: Enables the corresponding interrupt."
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bitfld.long 0x0 13. "EOC13,End of Conversion Interrupt Enable 13" "0: No effect.,1: Enables the corresponding interrupt."
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bitfld.long 0x0 12. "EOC12,End of Conversion Interrupt Enable 12" "0: No effect.,1: Enables the corresponding interrupt."
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bitfld.long 0x0 11. "EOC11,End of Conversion Interrupt Enable 11" "0: No effect.,1: Enables the corresponding interrupt."
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bitfld.long 0x0 10. "EOC10,End of Conversion Interrupt Enable 10" "0: No effect.,1: Enables the corresponding interrupt."
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bitfld.long 0x0 9. "EOC9,End of Conversion Interrupt Enable 9" "0: No effect.,1: Enables the corresponding interrupt."
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bitfld.long 0x0 8. "EOC8,End of Conversion Interrupt Enable 8" "0: No effect.,1: Enables the corresponding interrupt."
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bitfld.long 0x0 7. "EOC7,End of Conversion Interrupt Enable 7" "0: No effect.,1: Enables the corresponding interrupt."
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bitfld.long 0x0 6. "EOC6,End of Conversion Interrupt Enable 6" "0: No effect.,1: Enables the corresponding interrupt."
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bitfld.long 0x0 5. "EOC5,End of Conversion Interrupt Enable 5" "0: No effect.,1: Enables the corresponding interrupt."
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bitfld.long 0x0 4. "EOC4,End of Conversion Interrupt Enable 4" "0: No effect.,1: Enables the corresponding interrupt."
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bitfld.long 0x0 3. "EOC3,End of Conversion Interrupt Enable 3" "0: No effect.,1: Enables the corresponding interrupt."
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bitfld.long 0x0 2. "EOC2,End of Conversion Interrupt Enable 2" "0: No effect.,1: Enables the corresponding interrupt."
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bitfld.long 0x0 1. "EOC1,End of Conversion Interrupt Enable 1" "0: No effect.,1: Enables the corresponding interrupt."
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|
bitfld.long 0x0 0. "EOC0,End of Conversion Interrupt Enable 0" "0: No effect.,1: Enables the corresponding interrupt."
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line.long 0x4 "EOC_IDR,End Of Conversion Interrupt Disable Register"
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|
bitfld.long 0x4 31. "EOC31,End of Conversion Interrupt Disable 31" "0: No effect.,1: Disables the corresponding interrupt."
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bitfld.long 0x4 30. "EOC30,End of Conversion Interrupt Disable 30" "0: No effect.,1: Disables the corresponding interrupt."
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bitfld.long 0x4 15. "EOC15,End of Conversion Interrupt Disable 15" "0: No effect.,1: Disables the corresponding interrupt."
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bitfld.long 0x4 14. "EOC14,End of Conversion Interrupt Disable 14" "0: No effect.,1: Disables the corresponding interrupt."
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bitfld.long 0x4 13. "EOC13,End of Conversion Interrupt Disable 13" "0: No effect.,1: Disables the corresponding interrupt."
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bitfld.long 0x4 12. "EOC12,End of Conversion Interrupt Disable 12" "0: No effect.,1: Disables the corresponding interrupt."
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newline
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bitfld.long 0x4 11. "EOC11,End of Conversion Interrupt Disable 11" "0: No effect.,1: Disables the corresponding interrupt."
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bitfld.long 0x4 10. "EOC10,End of Conversion Interrupt Disable 10" "0: No effect.,1: Disables the corresponding interrupt."
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newline
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bitfld.long 0x4 9. "EOC9,End of Conversion Interrupt Disable 9" "0: No effect.,1: Disables the corresponding interrupt."
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bitfld.long 0x4 8. "EOC8,End of Conversion Interrupt Disable 8" "0: No effect.,1: Disables the corresponding interrupt."
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bitfld.long 0x4 7. "EOC7,End of Conversion Interrupt Disable 7" "0: No effect.,1: Disables the corresponding interrupt."
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bitfld.long 0x4 6. "EOC6,End of Conversion Interrupt Disable 6" "0: No effect.,1: Disables the corresponding interrupt."
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newline
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bitfld.long 0x4 5. "EOC5,End of Conversion Interrupt Disable 5" "0: No effect.,1: Disables the corresponding interrupt."
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bitfld.long 0x4 4. "EOC4,End of Conversion Interrupt Disable 4" "0: No effect.,1: Disables the corresponding interrupt."
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bitfld.long 0x4 3. "EOC3,End of Conversion Interrupt Disable 3" "0: No effect.,1: Disables the corresponding interrupt."
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bitfld.long 0x4 2. "EOC2,End of Conversion Interrupt Disable 2" "0: No effect.,1: Disables the corresponding interrupt."
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bitfld.long 0x4 1. "EOC1,End of Conversion Interrupt Disable 1" "0: No effect.,1: Disables the corresponding interrupt."
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bitfld.long 0x4 0. "EOC0,End of Conversion Interrupt Disable 0" "0: No effect.,1: Disables the corresponding interrupt."
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rgroup.long 0x3C++0x7
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line.long 0x0 "EOC_IMR,End Of Conversion Interrupt Mask Register"
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bitfld.long 0x0 31. "EOC31,End of Conversion Interrupt Mask 31" "0: The corresponding interrupt is disabled.,1: The corresponding interrupt is enabled."
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bitfld.long 0x0 30. "EOC30,End of Conversion Interrupt Mask 30" "0: The corresponding interrupt is disabled.,1: The corresponding interrupt is enabled."
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bitfld.long 0x0 15. "EOC15,End of Conversion Interrupt Mask 15" "0: The corresponding interrupt is disabled.,1: The corresponding interrupt is enabled."
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bitfld.long 0x0 14. "EOC14,End of Conversion Interrupt Mask 14" "0: The corresponding interrupt is disabled.,1: The corresponding interrupt is enabled."
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bitfld.long 0x0 13. "EOC13,End of Conversion Interrupt Mask 13" "0: The corresponding interrupt is disabled.,1: The corresponding interrupt is enabled."
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bitfld.long 0x0 12. "EOC12,End of Conversion Interrupt Mask 12" "0: The corresponding interrupt is disabled.,1: The corresponding interrupt is enabled."
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bitfld.long 0x0 11. "EOC11,End of Conversion Interrupt Mask 11" "0: The corresponding interrupt is disabled.,1: The corresponding interrupt is enabled."
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bitfld.long 0x0 10. "EOC10,End of Conversion Interrupt Mask 10" "0: The corresponding interrupt is disabled.,1: The corresponding interrupt is enabled."
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bitfld.long 0x0 9. "EOC9,End of Conversion Interrupt Mask 9" "0: The corresponding interrupt is disabled.,1: The corresponding interrupt is enabled."
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bitfld.long 0x0 8. "EOC8,End of Conversion Interrupt Mask 8" "0: The corresponding interrupt is disabled.,1: The corresponding interrupt is enabled."
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bitfld.long 0x0 7. "EOC7,End of Conversion Interrupt Mask 7" "0: The corresponding interrupt is disabled.,1: The corresponding interrupt is enabled."
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bitfld.long 0x0 6. "EOC6,End of Conversion Interrupt Mask 6" "0: The corresponding interrupt is disabled.,1: The corresponding interrupt is enabled."
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bitfld.long 0x0 5. "EOC5,End of Conversion Interrupt Mask 5" "0: The corresponding interrupt is disabled.,1: The corresponding interrupt is enabled."
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bitfld.long 0x0 4. "EOC4,End of Conversion Interrupt Mask 4" "0: The corresponding interrupt is disabled.,1: The corresponding interrupt is enabled."
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bitfld.long 0x0 3. "EOC3,End of Conversion Interrupt Mask 3" "0: The corresponding interrupt is disabled.,1: The corresponding interrupt is enabled."
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bitfld.long 0x0 2. "EOC2,End of Conversion Interrupt Mask 2" "0: The corresponding interrupt is disabled.,1: The corresponding interrupt is enabled."
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newline
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bitfld.long 0x0 1. "EOC1,End of Conversion Interrupt Mask 1" "0: The corresponding interrupt is disabled.,1: The corresponding interrupt is enabled."
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bitfld.long 0x0 0. "EOC0,End of Conversion Interrupt Mask 0" "0: The corresponding interrupt is disabled.,1: The corresponding interrupt is enabled."
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line.long 0x4 "EOC_ISR,End Of Conversion Interrupt Status Register"
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bitfld.long 0x4 31. "EOC31,End of Conversion 31 (automatically set / cleared)" "0: The corresponding analog channel is disabled or..,1: The corresponding analog channel is enabled and.."
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bitfld.long 0x4 30. "EOC30,End of Conversion 30 (automatically set / cleared)" "0: The corresponding analog channel is disabled or..,1: The corresponding analog channel is enabled and.."
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newline
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bitfld.long 0x4 15. "EOC15,End of Conversion 15 (automatically set / cleared)" "0: The corresponding analog channel is disabled or..,1: The corresponding analog channel is enabled and.."
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bitfld.long 0x4 14. "EOC14,End of Conversion 14 (automatically set / cleared)" "0: The corresponding analog channel is disabled or..,1: The corresponding analog channel is enabled and.."
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newline
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bitfld.long 0x4 13. "EOC13,End of Conversion 13 (automatically set / cleared)" "0: The corresponding analog channel is disabled or..,1: The corresponding analog channel is enabled and.."
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|
bitfld.long 0x4 12. "EOC12,End of Conversion 12 (automatically set / cleared)" "0: The corresponding analog channel is disabled or..,1: The corresponding analog channel is enabled and.."
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bitfld.long 0x4 11. "EOC11,End of Conversion 11 (automatically set / cleared)" "0: The corresponding analog channel is disabled or..,1: The corresponding analog channel is enabled and.."
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|
bitfld.long 0x4 10. "EOC10,End of Conversion 10 (automatically set / cleared)" "0: The corresponding analog channel is disabled or..,1: The corresponding analog channel is enabled and.."
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bitfld.long 0x4 9. "EOC9,End of Conversion 9 (automatically set / cleared)" "0: The corresponding analog channel is disabled or..,1: The corresponding analog channel is enabled and.."
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|
bitfld.long 0x4 8. "EOC8,End of Conversion 8 (automatically set / cleared)" "0: The corresponding analog channel is disabled or..,1: The corresponding analog channel is enabled and.."
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bitfld.long 0x4 7. "EOC7,End of Conversion 7 (automatically set / cleared)" "0: The corresponding analog channel is disabled or..,1: The corresponding analog channel is enabled and.."
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bitfld.long 0x4 6. "EOC6,End of Conversion 6 (automatically set / cleared)" "0: The corresponding analog channel is disabled or..,1: The corresponding analog channel is enabled and.."
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bitfld.long 0x4 5. "EOC5,End of Conversion 5 (automatically set / cleared)" "0: The corresponding analog channel is disabled or..,1: The corresponding analog channel is enabled and.."
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bitfld.long 0x4 4. "EOC4,End of Conversion 4 (automatically set / cleared)" "0: The corresponding analog channel is disabled or..,1: The corresponding analog channel is enabled and.."
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bitfld.long 0x4 3. "EOC3,End of Conversion 3 (automatically set / cleared)" "0: The corresponding analog channel is disabled or..,1: The corresponding analog channel is enabled and.."
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bitfld.long 0x4 2. "EOC2,End of Conversion 2 (automatically set / cleared)" "0: The corresponding analog channel is disabled or..,1: The corresponding analog channel is enabled and.."
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newline
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bitfld.long 0x4 1. "EOC1,End of Conversion 1 (automatically set / cleared)" "0: The corresponding analog channel is disabled or..,1: The corresponding analog channel is enabled and.."
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bitfld.long 0x4 0. "EOC0,End of Conversion 0 (automatically set / cleared)" "0: The corresponding analog channel is disabled or..,1: The corresponding analog channel is enabled and.."
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group.long 0x44++0x7
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line.long 0x0 "TEMPMR,Temperature Sensor Mode Register"
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bitfld.long 0x0 4.--5. "TEMPCMPMOD,Temperature Comparison Mode" "0: Generates the TEMPCHG flag in ADC_ISR when the..,1: Generates the TEMPCHG flag in ADC_ISR when the..,2: Generates the TEMPCHG flag in ADC_ISR when the..,3: Generates the TEMPCHG flag in ADC_ISR when the.."
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bitfld.long 0x0 0. "TEMPON,Temperature Sensor On" "0: The temperature sensor is not enabled.,1: The temperature sensor is enabled and the.."
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line.long 0x4 "TEMPCWR,Temperature Compare Window Register"
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hexmask.long.word 0x4 16.--27. 1. "THIGHTHRES,Temperature High Threshold"
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hexmask.long.word 0x4 0.--11. 1. "TLOWTHRES,Temperature Low Threshold"
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rgroup.long 0x4C++0x3
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line.long 0x0 "OVER,Overrun Status Register"
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bitfld.long 0x0 31. "OVRE31,Overrun Error 31" "0: No overrun error has occurred on the..,1: An overrun error has occurred on the.."
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bitfld.long 0x0 30. "OVRE30,Overrun Error 30" "0: No overrun error has occurred on the..,1: An overrun error has occurred on the.."
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newline
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bitfld.long 0x0 15. "OVRE15,Overrun Error 15" "0: No overrun error has occurred on the..,1: An overrun error has occurred on the.."
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bitfld.long 0x0 14. "OVRE14,Overrun Error 14" "0: No overrun error has occurred on the..,1: An overrun error has occurred on the.."
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newline
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bitfld.long 0x0 13. "OVRE13,Overrun Error 13" "0: No overrun error has occurred on the..,1: An overrun error has occurred on the.."
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bitfld.long 0x0 12. "OVRE12,Overrun Error 12" "0: No overrun error has occurred on the..,1: An overrun error has occurred on the.."
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newline
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bitfld.long 0x0 11. "OVRE11,Overrun Error 11" "0: No overrun error has occurred on the..,1: An overrun error has occurred on the.."
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bitfld.long 0x0 10. "OVRE10,Overrun Error 10" "0: No overrun error has occurred on the..,1: An overrun error has occurred on the.."
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newline
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bitfld.long 0x0 9. "OVRE9,Overrun Error 9" "0: No overrun error has occurred on the..,1: An overrun error has occurred on the.."
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bitfld.long 0x0 8. "OVRE8,Overrun Error 8" "0: No overrun error has occurred on the..,1: An overrun error has occurred on the.."
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newline
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bitfld.long 0x0 7. "OVRE7,Overrun Error 7" "0: No overrun error has occurred on the..,1: An overrun error has occurred on the.."
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bitfld.long 0x0 6. "OVRE6,Overrun Error 6" "0: No overrun error has occurred on the..,1: An overrun error has occurred on the.."
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newline
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bitfld.long 0x0 5. "OVRE5,Overrun Error 5" "0: No overrun error has occurred on the..,1: An overrun error has occurred on the.."
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bitfld.long 0x0 4. "OVRE4,Overrun Error 4" "0: No overrun error has occurred on the..,1: An overrun error has occurred on the.."
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newline
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bitfld.long 0x0 3. "OVRE3,Overrun Error 3" "0: No overrun error has occurred on the..,1: An overrun error has occurred on the.."
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bitfld.long 0x0 2. "OVRE2,Overrun Error 2" "0: No overrun error has occurred on the..,1: An overrun error has occurred on the.."
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newline
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bitfld.long 0x0 1. "OVRE1,Overrun Error 1" "0: No overrun error has occurred on the..,1: An overrun error has occurred on the.."
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bitfld.long 0x0 0. "OVRE0,Overrun Error 0" "0: No overrun error has occurred on the..,1: An overrun error has occurred on the.."
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group.long 0x50++0x7
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line.long 0x0 "EMR,Extended Mode Register"
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bitfld.long 0x0 30. "ALTCH,Alternate Channel Selection (Safety)" "0: The regular channels are selected.,1: The alternate channels are selected."
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bitfld.long 0x0 28.--29. "ADCMODE,ADC Running Mode" "0: Normal mode of operation.,1: Offset Error mode to measure the offset error.,2: Gain Error mode to measure the gain error. See..,3: Gain Error mode to measure the gain error. See.."
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newline
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bitfld.long 0x0 25.--26. "SIGNMODE,Sign Mode" "0: Single-ended channels: unsigned conversions..,1: Single-ended channels: signed conversions..,2: All channels: unsigned conversions,3: All channels: signed conversions"
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bitfld.long 0x0 24. "TAG,ADC_LCDR Tag" "0: Sets ADC_LCDR.NO_OSR_CHNB/CHNBOSR to zero.,1: Appends the channel number to the conversion.."
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newline
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bitfld.long 0x0 22.--23. "TRACKX,Tracking Time x4 x8 or x16" "0: ADC_MR.TRACKTIM effect is multiplied by 1.,1: ADC_MR.TRACKTIM effect is multiplied by 4.,2: ADC_MR.TRACKTIM effect is multiplied by 8,3: ADC_MR.TRACKTIM effect is multiplied by 16."
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bitfld.long 0x0 21. "SRCCLK,External Clock Selection" "0: The peripheral clock is the source for the ADC..,1: GCLK is the source clock for the ADC prescaler.."
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newline
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bitfld.long 0x0 20. "ASTE,Averaging on Single Trigger Event" "0: The average requests several trigger events.,1: The average requests only one trigger event."
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bitfld.long 0x0 16.--18. "OSR,Over Sampling Rate" "0: No averaging. ADC sample rate is maximum.,1: 1-bit enhanced resolution by averaging. ADC..,2: 2-bit enhanced resolution by averaging. ADC..,3: 1-bit enhanced resolution by averaging. ADC..,4: 2-bit enhanced resolution by averaging. ADC..,?,?,?"
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newline
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bitfld.long 0x0 12.--13. "CMPFILTER,Compare Event Filtering" "0,1,2,3"
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bitfld.long 0x0 9. "CMPALL,Compare All Channels" "0: Only the channel indicated in CMPSEL is compared.,1: All channels are compared."
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newline
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hexmask.long.byte 0x0 4.--8. 1. "CMPSEL,Comparison Selected Channel"
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bitfld.long 0x0 2. "CMPTYPE,Comparison Type" "0: Any conversion is performed and comparison..,1: Comparison conditions must be met to start the.."
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newline
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bitfld.long 0x0 0.--1. "CMPMODE,Comparison Mode" "0: When the converted data is lower than the low..,1: When the converted data is higher than the high..,2: When the converted data is in the comparison..,3: When the converted data is out of the comparison.."
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line.long 0x4 "CWR,Compare Window Register"
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hexmask.long.word 0x4 16.--31. 1. "HIGHTHRES,High Threshold"
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hexmask.long.word 0x4 0.--15. 1. "LOWTHRES,Low Threshold"
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group.long 0x5C++0x3
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line.long 0x0 "CCR,Channel Configuration Register"
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bitfld.long 0x0 15. "DIFF15,Differential Inputs for Channel 15" "0: Corresponding channel is set in Single-ended mode.,1: Corresponding channel is set in Differential mode."
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bitfld.long 0x0 14. "DIFF14,Differential Inputs for Channel 14" "0: Corresponding channel is set in Single-ended mode.,1: Corresponding channel is set in Differential mode."
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newline
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bitfld.long 0x0 13. "DIFF13,Differential Inputs for Channel 13" "0: Corresponding channel is set in Single-ended mode.,1: Corresponding channel is set in Differential mode."
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bitfld.long 0x0 12. "DIFF12,Differential Inputs for Channel 12" "0: Corresponding channel is set in Single-ended mode.,1: Corresponding channel is set in Differential mode."
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newline
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bitfld.long 0x0 11. "DIFF11,Differential Inputs for Channel 11" "0: Corresponding channel is set in Single-ended mode.,1: Corresponding channel is set in Differential mode."
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bitfld.long 0x0 10. "DIFF10,Differential Inputs for Channel 10" "0: Corresponding channel is set in Single-ended mode.,1: Corresponding channel is set in Differential mode."
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newline
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bitfld.long 0x0 9. "DIFF9,Differential Inputs for Channel 9" "0: Corresponding channel is set in Single-ended mode.,1: Corresponding channel is set in Differential mode."
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bitfld.long 0x0 8. "DIFF8,Differential Inputs for Channel 8" "0: Corresponding channel is set in Single-ended mode.,1: Corresponding channel is set in Differential mode."
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newline
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bitfld.long 0x0 7. "DIFF7,Differential Inputs for Channel 7" "0: Corresponding channel is set in Single-ended mode.,1: Corresponding channel is set in Differential mode."
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bitfld.long 0x0 6. "DIFF6,Differential Inputs for Channel 6" "0: Corresponding channel is set in Single-ended mode.,1: Corresponding channel is set in Differential mode."
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newline
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bitfld.long 0x0 5. "DIFF5,Differential Inputs for Channel 5" "0: Corresponding channel is set in Single-ended mode.,1: Corresponding channel is set in Differential mode."
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bitfld.long 0x0 4. "DIFF4,Differential Inputs for Channel 4" "0: Corresponding channel is set in Single-ended mode.,1: Corresponding channel is set in Differential mode."
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newline
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bitfld.long 0x0 3. "DIFF3,Differential Inputs for Channel 3" "0: Corresponding channel is set in Single-ended mode.,1: Corresponding channel is set in Differential mode."
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|
bitfld.long 0x0 2. "DIFF2,Differential Inputs for Channel 2" "0: Corresponding channel is set in Single-ended mode.,1: Corresponding channel is set in Differential mode."
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newline
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bitfld.long 0x0 1. "DIFF1,Differential Inputs for Channel 1" "0: Corresponding channel is set in Single-ended mode.,1: Corresponding channel is set in Differential mode."
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|
bitfld.long 0x0 0. "DIFF0,Differential Inputs for Channel 0" "0: Corresponding channel is set in Single-ended mode.,1: Corresponding channel is set in Differential mode."
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|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x60)++0x3
|
|
line.long 0x0 "CDR[$1],Channel Data Register x"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,Converted Data"
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|
repeat.end
|
|
group.long 0xE0++0x7
|
|
line.long 0x0 "ACR,Analog Control Register"
|
|
bitfld.long 0x0 16. "SRCLCH,Source Last Channel." "0: The highest index channel is driven by the..,1: The highest index channel is driven by the.."
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|
line.long 0x4 "FMR,FIFO Mode Register"
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|
hexmask.long.byte 0x4 16.--23. 1. "FIFOCNT,FIFO Count (read-only)"
|
|
hexmask.long.byte 0x4 4.--7. 1. "CHUNK,Chunk Size"
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newline
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bitfld.long 0x4 1. "ENLEVEL,Enable Level" "0: Request to DMA is generated as soon as one data..,1: Request to DMA is generated as soon as the.."
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bitfld.long 0x4 0. "ENFIFO,Enable FIFO" "0: FIFO is disabled.,1: FIFO is enabled."
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|
group.long 0x100++0xF
|
|
line.long 0x0 "TRGR,Trigger Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "TRGPER,Trigger Period"
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|
bitfld.long 0x0 0.--2. "TRGMOD,Trigger Mode" "0: No hardware trigger only software trigger can..,1: Rising edge of the selected trigger event..,2: Falling edge of the selected trigger event,3: Any edge of the selected trigger event,?,5: ADC internal periodic trigger (see TRGPER),6: Continuous mode free run mode,?"
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|
line.long 0x4 "COSR,Correction Select Register"
|
|
hexmask.long.byte 0x4 0.--4. 1. "CSEL,Channel Correction Select"
|
|
line.long 0x8 "CVR,Correction Values Register"
|
|
hexmask.long.word 0x8 16.--31. 1. "GAINCORR,Gain Correction"
|
|
hexmask.long.word 0x8 0.--15. 1. "OFFSETCORR,Offset Correction"
|
|
line.long 0xC "CECR,Channel Error Correction Register"
|
|
bitfld.long 0xC 31. "ECORR31,Error Correction Enable for Channel 31" "0: Automatic error correction is disabled for..,1: Automatic error correction is enabled for.."
|
|
bitfld.long 0xC 30. "ECORR30,Error Correction Enable for Channel 30" "0: Automatic error correction is disabled for..,1: Automatic error correction is enabled for.."
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bitfld.long 0xC 15. "ECORR15,Error Correction Enable for Channel 15" "0: Automatic error correction is disabled for..,1: Automatic error correction is enabled for.."
|
|
bitfld.long 0xC 14. "ECORR14,Error Correction Enable for Channel 14" "0: Automatic error correction is disabled for..,1: Automatic error correction is enabled for.."
|
|
newline
|
|
bitfld.long 0xC 13. "ECORR13,Error Correction Enable for Channel 13" "0: Automatic error correction is disabled for..,1: Automatic error correction is enabled for.."
|
|
bitfld.long 0xC 12. "ECORR12,Error Correction Enable for Channel 12" "0: Automatic error correction is disabled for..,1: Automatic error correction is enabled for.."
|
|
newline
|
|
bitfld.long 0xC 11. "ECORR11,Error Correction Enable for Channel 11" "0: Automatic error correction is disabled for..,1: Automatic error correction is enabled for.."
|
|
bitfld.long 0xC 10. "ECORR10,Error Correction Enable for Channel 10" "0: Automatic error correction is disabled for..,1: Automatic error correction is enabled for.."
|
|
newline
|
|
bitfld.long 0xC 9. "ECORR9,Error Correction Enable for Channel 9" "0: Automatic error correction is disabled for..,1: Automatic error correction is enabled for.."
|
|
bitfld.long 0xC 8. "ECORR8,Error Correction Enable for Channel 8" "0: Automatic error correction is disabled for..,1: Automatic error correction is enabled for.."
|
|
newline
|
|
bitfld.long 0xC 7. "ECORR7,Error Correction Enable for Channel 7" "0: Automatic error correction is disabled for..,1: Automatic error correction is enabled for.."
|
|
bitfld.long 0xC 6. "ECORR6,Error Correction Enable for Channel 6" "0: Automatic error correction is disabled for..,1: Automatic error correction is enabled for.."
|
|
newline
|
|
bitfld.long 0xC 5. "ECORR5,Error Correction Enable for Channel 5" "0: Automatic error correction is disabled for..,1: Automatic error correction is enabled for.."
|
|
bitfld.long 0xC 4. "ECORR4,Error Correction Enable for Channel 4" "0: Automatic error correction is disabled for..,1: Automatic error correction is enabled for.."
|
|
newline
|
|
bitfld.long 0xC 3. "ECORR3,Error Correction Enable for Channel 3" "0: Automatic error correction is disabled for..,1: Automatic error correction is enabled for.."
|
|
bitfld.long 0xC 2. "ECORR2,Error Correction Enable for Channel 2" "0: Automatic error correction is disabled for..,1: Automatic error correction is enabled for.."
|
|
newline
|
|
bitfld.long 0xC 1. "ECORR1,Error Correction Enable for Channel 1" "0: Automatic error correction is disabled for..,1: Automatic error correction is enabled for.."
|
|
bitfld.long 0xC 0. "ECORR0,Error Correction Enable for Channel 0" "0: Automatic error correction is disabled for..,1: Automatic error correction is enabled for.."
|
|
group.long 0x118++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Register Enable" "0: Disables the write protection on control..,1: Enables the write protection on control.."
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables write protection if WPKEY corresponds..,1: Enables write protection if WPKEY corresponds to.."
|
|
rgroup.long 0x11C++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
|
|
tree.end
|
|
tree "AES (Advanced Encryption Standard)"
|
|
base ad:0xE1810000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 24. "UNLOCK,Unlock Processing" "0: No effect.,1: Unlocks the processing in case of abnormal event.."
|
|
bitfld.long 0x0 8. "SWRST,Software Reset" "0: No effect.,1: Resets the AES. A software-triggered reset of.."
|
|
newline
|
|
bitfld.long 0x0 0. "START,Start Processing" "0: No effect.,1: Starts manual encryption/decryption process."
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 31. "TAMPCLR,Tamper Clear Enable" "0: A tamper detection event has no effect on the..,1: A tamper detection event immediately clears the.."
|
|
hexmask.long.byte 0x0 20.--23. 1. "CKEY,Key"
|
|
newline
|
|
bitfld.long 0x0 16.--18. "CFBS,Cipher Feedback Data Size" "0: 128-bit,1: 64-bit,2: 32-bit,3: 16-bit,4: 8-bit,?,?,?"
|
|
bitfld.long 0x0 15. "LOD,Last Output Data Mode" "0: No effect.,1: The DATRDY flag is cleared when at least one of.."
|
|
newline
|
|
bitfld.long 0x0 12.--14. "OPMOD,Operating Mode" "0: ECB: Electronic Codebook mode,1: CBC: Cipher Block Chaining mode,2: OFB: Output Feedback mode,3: CFB: Cipher Feedback mode,4: CTR: Counter mode (16-bit internal counter),5: GCM: Galois/Counter mode,6: XTS: XEX-based tweaked-codebook mode,?"
|
|
bitfld.long 0x0 10.--11. "KEYSIZE,Key Size" "0: AES Key Size is 128 bits,1: AES Key Size is 192 bits,2: AES Key Size is 256 bits,?"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "SMOD,Start Mode" "0: Manual Mode,1: Auto Mode,2: AES_IDATAR0 access only Auto Mode (DMA),?"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PROCDLY,Processing Delay"
|
|
newline
|
|
bitfld.long 0x0 3. "DUALBUFF,Dual Input Buffer" "0: AES_IDATARx cannot be written during processing..,1: AES_IDATARx can be written during processing of.."
|
|
bitfld.long 0x0 1. "GTAGEN,GCM Automatic Tag Generation Enable" "0: Automatic GCM Tag generation disabled.,1: Automatic GCM Tag generation enabled."
|
|
newline
|
|
bitfld.long 0x0 0. "CIPHER,Processing Mode" "0: Decrypts data.,1: Encrypts data."
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 19. "SECE,Security and/or Safety Event Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 18. "PLENERR,Padding Length Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "EOPAD,End of Padding Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 16. "TAGRDY,GCM Tag Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "URAD,Unspecified Register Access Detection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 19. "SECE,Security and/or Safety Event Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 18. "PLENERR,Padding Length Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "EOPAD,End of Padding Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 16. "TAGRDY,GCM Tag Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "URAD,Unspecified Register Access Detection Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "DATRDY,Data Ready Interrupt Disable" "0,1"
|
|
rgroup.long 0x18++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 19. "SECE,Security and/or Safety Event Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 18. "PLENERR,Padding Length Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "EOPAD,End of Padding Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 16. "TAGRDY,GCM Tag Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "URAD,Unspecified Register Access Detection Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 19. "SECE,Security and/or Safety Event (cleared on read)" "0: There is no security report in AES_WPSR.,1: One security flag is set in AES_WPSR."
|
|
bitfld.long 0x4 18. "PLENERR,Padding Length Error" "0: No Padding Length Error occurred.,1: Padding Length Error detected."
|
|
newline
|
|
bitfld.long 0x4 17. "EOPAD,End of Padding" "0: Padding is not over.,1: Padding phase is over."
|
|
bitfld.long 0x4 16. "TAGRDY,GCM Tag Ready" "0: GCM Tag is not valid.,1: GCM Tag generation is complete (cleared by.."
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "URAT,Unspecified Register Access (cleared by writing SWRST in AES_CR)"
|
|
bitfld.long 0x4 8. "URAD,Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR)" "0: No unspecified register access has been detected..,1: At least one unspecified register access has.."
|
|
newline
|
|
bitfld.long 0x4 0. "DATRDY,Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx)" "0: Output data not valid.,1: Encryption or decryption process is completed."
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "KEYWR[$1],Key Word Register x"
|
|
hexmask.long 0x0 0.--31. 1. "KEYW,Key Word"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x40)++0x3
|
|
line.long 0x0 "IDATAR[$1],Input Data Register x"
|
|
hexmask.long 0x0 0.--31. 1. "IDATA,Input Data Word"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x50)++0x3
|
|
line.long 0x0 "ODATAR[$1],Output Data Register x"
|
|
hexmask.long 0x0 0.--31. 1. "ODATA,Output Data"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x60)++0x3
|
|
line.long 0x0 "IVR[$1],Initialization Vector Register x"
|
|
hexmask.long 0x0 0.--31. 1. "IV,Initialization Vector"
|
|
repeat.end
|
|
group.long 0x70++0x7
|
|
line.long 0x0 "AADLENR,Additional Authenticated Data Length Register"
|
|
hexmask.long 0x0 0.--31. 1. "AADLEN,Additional Authenticated Data Length"
|
|
line.long 0x4 "CLENR,Plaintext/Ciphertext Length Register"
|
|
hexmask.long 0x4 0.--31. 1. "CLEN,Plaintext/Ciphertext Length"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x78)++0x3
|
|
line.long 0x0 "GHASHR[$1],GCM Intermediate Hash Word Register x"
|
|
hexmask.long 0x0 0.--31. 1. "GHASH,Intermediate GCM Hash Word"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x88)++0x3
|
|
line.long 0x0 "TAGR[$1],GCM Authentication Tag Word Register x"
|
|
hexmask.long 0x0 0.--31. 1. "TAG,GCM Authentication Tag"
|
|
repeat.end
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x0 "CTRR,GCM Encryption Counter Value Register"
|
|
hexmask.long 0x0 0.--31. 1. "CTR,GCM Encryption Counter"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x9C)++0x3
|
|
line.long 0x0 "GCMHR[$1],GCM H Word Register x"
|
|
hexmask.long 0x0 0.--31. 1. "H,GCM H Word"
|
|
repeat.end
|
|
group.long 0xB0++0x7
|
|
line.long 0x0 "EMR,Extended Mode Register"
|
|
bitfld.long 0x0 31. "BPE,Block Processing End" "0: AES_ISR.DATRDY flag reports only the end message..,1: AES_ISR.DATRDY flag reports each end of block.."
|
|
hexmask.long.byte 0x0 16.--23. 1. "NHEAD,IPSEC Next Header"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "PADLEN,Auto Padding Length"
|
|
bitfld.long 0x0 7. "PKRS,Private Key Internal Register Select" "0: The key used by the AES is in the AES_KEYWRx..,1: The key used by the AES is in the Private Key.."
|
|
newline
|
|
bitfld.long 0x0 6. "PKWL,Private Key Write Lock" "0: The Private Key internal registers can be..,1: The Private Key internal registers can be.."
|
|
bitfld.long 0x0 5. "PLIPD,Protocol Layer Improved Performance Decipher" "0: Protocol layer improved performance is in..,1: Protocol layer improved performance is in.."
|
|
newline
|
|
bitfld.long 0x0 4. "PLIPEN,Protocol Layer Improved Performance Enable" "0: Protocol layer improved performance is disabled.,1: Protocol layer improved performance is enabled."
|
|
bitfld.long 0x0 1. "APM,Auto Padding Mode" "0: Auto Padding performed according to IPSEC..,1: Auto Padding performed according to SSL standard."
|
|
newline
|
|
bitfld.long 0x0 0. "APEN,Auto Padding Enable" "0: Auto Padding feature is disabled.,1: Auto Padding feature is enabled."
|
|
line.long 0x4 "BCNT,Byte Counter Register"
|
|
hexmask.long 0x4 0.--31. 1. "BCNT,Auto Padding Byte Counter"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xC0)++0x3
|
|
line.long 0x0 "TWR[$1],Tweak Word Register x"
|
|
hexmask.long 0x0 0.--31. 1. "TWEAK,Tweak Word"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0xD0)++0x3
|
|
line.long 0x0 "ALPHAR[$1],Alpha Word Register x"
|
|
hexmask.long 0x0 0.--31. 1. "ALPHA,Alpha Word"
|
|
repeat.end
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 5.--7. "ACTION,Action on Abnormal Event Detection" "0: No action (stop or clear key) is performed when..,1: If a processing is in progress when the..,2: If a processing is in progress when the..,3: If a processing is in progress when the..,4: If a processing is in progress when the..,5: If a processing is in progress when the..,6: If a processing is in progress when the..,?"
|
|
newline
|
|
bitfld.long 0x0 4. "FIRSTE,First Error Report Enable" "0: The last write protection violation source is..,1: Only the first write protection violation source.."
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interruption Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Configuration Enable" "0: Disables the write protection on configuration..,1: Enables the write protection on configuration.."
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
bitfld.long 0x0 31. "ECLASS,Software Error Class (cleared on read)" "0: An abnormal access that does not affect system..,1: An access is performed into key input data.."
|
|
hexmask.long.byte 0x0 24.--27. 1. "SWETYP,Software Error Type (cleared on read)"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 4. "PKRPVS,Private Key Internal Register Protection Violation Status (cleared on read)" "0: No Private Key internal register access..,1: A Private Key internal register access violation.."
|
|
newline
|
|
bitfld.long 0x0 3. "SWE,Software Control Error (cleared on read)" "0: No software error has occurred since the last..,1: A software error has occurred since the last.."
|
|
bitfld.long 0x0 2. "SEQE,Internal Sequencer Error (cleared on read)" "0: No peripheral internal sequencer error has..,1: A peripheral internal sequencer error has.."
|
|
newline
|
|
bitfld.long 0x0 1. "CGD,Clock Glitch Detected (cleared on read)" "0: The clock monitoring circuitry has not been..,1: The clock monitoring circuitry has been.."
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status (cleared on read)" "0: No write protect violation has occurred since..,1: A write protect violation has occurred since the.."
|
|
tree.end
|
|
tree "ASRC (Asynchronous Sample Rate Converter)"
|
|
base ad:0xE1610000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0: No effect.,1: Resets the ASRC."
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 12. "GT96K,Frequency Sampling Greater Than 96 kHz" "0: Up to 4 DSP with up to 96 kHz as the upper bound..,1: Up to 2 DSP with up to 192 kHz as the upper.."
|
|
bitfld.long 0x0 3. "ASRCEN3,ASRC Stereo Channel 3 Enable" "0: DSPx is disabled.,1: DSPx is enabled."
|
|
newline
|
|
bitfld.long 0x0 2. "ASRCEN2,ASRC Stereo Channel 2 Enable" "0: DSPx is disabled.,1: DSPx is enabled."
|
|
bitfld.long 0x0 1. "ASRCEN1,ASRC Stereo Channel 1 Enable" "0: DSPx is disabled.,1: DSPx is enabled."
|
|
newline
|
|
bitfld.long 0x0 0. "ASRCEN0,ASRC Stereo Channel 0 Enable" "0: DSPx is disabled.,1: DSPx is enabled."
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x8)++0x3
|
|
line.long 0x0 "RATIO[$1],Ratio Register of Stereo Channel x"
|
|
hexmask.long.word 0x0 16.--31. 1. "OUTRATIO,Output Internal Sampling Rate Ratio"
|
|
hexmask.long.word 0x0 0.--15. 1. "INRATIO,Input Internal Sampling Rate Ratio"
|
|
repeat.end
|
|
group.long 0x18++0xF
|
|
line.long 0x0 "VBPS_IN,Valid Bit Per Sample In Register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "VBPS_IN3,Valid Bit Per Sample In of DSP 3"
|
|
hexmask.long.byte 0x0 16.--19. 1. "VBPS_IN2,Valid Bit Per Sample In of DSP 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "VBPS_IN1,Valid Bit Per Sample In of DSP 1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "VBPS_IN0,Valid Bit Per Sample In of DSP 0"
|
|
line.long 0x4 "VBPS_OUT,Valid Bit Per Sample Out Register"
|
|
hexmask.long.byte 0x4 24.--27. 1. "VBPS_OUT3,Valid Bit Per Sample Out of DSP 3"
|
|
hexmask.long.byte 0x4 16.--19. 1. "VBPS_OUT2,Valid Bit Per Sample Out of DSP 2"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "VBPS_OUT1,Valid Bit Per Sample Out of DSP 1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "VBPS_OUT0,Valid Bit Per Sample Out of DSP 0"
|
|
line.long 0x8 "CH_CONF,Channel Configuration Register"
|
|
bitfld.long 0x8 28.--30. "CHUNK3,DMA DSP 3 CHUNK Size" "0: The DMA chunk size must be configured to..,1: The DMA chunk size must be configured to..,2: The DMA chunk size must be configured to..,3: The DMA chunk size must be configured to..,4: The DMA chunk size must be configured to..,?,?,?"
|
|
bitfld.long 0x8 24.--26. "CHUNK2,DMA DSP 2 CHUNK Size" "0: The DMA chunk size must be configured to..,1: The DMA chunk size must be configured to..,2: The DMA chunk size must be configured to..,3: The DMA chunk size must be configured to..,4: The DMA chunk size must be configured to..,?,?,?"
|
|
newline
|
|
bitfld.long 0x8 20.--22. "CHUNK1,DMA DSP 1 CHUNK Size" "0: The DMA chunk size must be configured to..,1: The DMA chunk size must be configured to..,2: The DMA chunk size must be configured to..,3: The DMA chunk size must be configured to..,4: The DMA chunk size must be configured to..,?,?,?"
|
|
bitfld.long 0x8 16.--18. "CHUNK0,DMA DSP 0 CHUNK Size" "0: The DMA chunk size must be configured to..,1: The DMA chunk size must be configured to..,2: The DMA chunk size must be configured to..,3: The DMA chunk size must be configured to..,4: The DMA chunk size must be configured to..,?,?,?"
|
|
newline
|
|
bitfld.long 0x8 11. "MONO3,DSP 3 Mono Operating Mode" "0: DSP operates in Stereo mode.,1: DSP operates in Mono mode."
|
|
bitfld.long 0x8 10. "MONO2,DSP 2 Mono Operating Mode" "0: DSP operates in Stereo mode.,1: DSP operates in Mono mode."
|
|
newline
|
|
bitfld.long 0x8 9. "MONO1,DSP 1 Mono Operating Mode" "0: DSP operates in Stereo mode.,1: DSP operates in Mono mode."
|
|
bitfld.long 0x8 8. "MONO0,DSP 0 Mono Operating Mode" "0: DSP operates in Stereo mode.,1: DSP operates in Mono mode."
|
|
newline
|
|
bitfld.long 0x8 4.--6. "RHROPMODE,Receive Holding Registers Operating Mode" "0: The ASRC_RHRx can receive up to 2 audio streams..,1: The ASRC_RHR0 can receive up to 4 audio streams..,2: The ASRC_RHR0 can receive up to 4 audio streams..,3: The ASRC_RHR0 can receive up to 6 audio streams..,4: The ASRC_RHR0 can receive up to 8 audio streams..,?,?,?"
|
|
bitfld.long 0x8 0.--2. "THROPMODE,Transmit Holding Registers Operating Mode" "0: The ASRC_THRx can receive up to 2 audio streams..,1: The ASRC_THR0 can receive up to 4 audio streams..,2: The ASRC_THR0 can receive up to 4 audio streams..,3: The ASRC_THR0 can receive up to 6 audio streams..,4: The ASRC_THR0 can receive up to 8 audio streams..,?,?,?"
|
|
line.long 0xC "TRIG,Trigger Selection Register"
|
|
hexmask.long.byte 0xC 28.--31. 1. "TRIGSELOUT3,Output Trigger Source Selection of Channel 3"
|
|
hexmask.long.byte 0xC 24.--27. 1. "TRIGSELOUT2,Output Trigger Source Selection of Channel 2"
|
|
newline
|
|
hexmask.long.byte 0xC 20.--23. 1. "TRIGSELOUT1,Output Trigger Source Selection of Channel 1"
|
|
hexmask.long.byte 0xC 16.--19. 1. "TRIGSELOUT0,Output Trigger Source Selection of Channel 0"
|
|
newline
|
|
hexmask.long.byte 0xC 12.--15. 1. "TRIGSELIN3,Input Trigger Source Selection of Channel 3"
|
|
hexmask.long.byte 0xC 8.--11. 1. "TRIGSELIN2,Input Trigger Source Selection of Channel 2"
|
|
newline
|
|
hexmask.long.byte 0xC 4.--7. 1. "TRIGSELIN1,Input Trigger Source Selection of Channel 1"
|
|
hexmask.long.byte 0xC 0.--3. 1. "TRIGSELIN0,Input Trigger Source Selection of Channel 0"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x28)++0x3
|
|
line.long 0x0 "RHR[$1],Receive Holding Register x"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Converted Data"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x48)++0x3
|
|
line.long 0x0 "THR[$1],Transmit Holding Register x"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data to Convert"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x68)++0x3
|
|
line.long 0x0 "IER[$1],Interrupt Enable Register x"
|
|
bitfld.long 0x0 31. "UNLOCK,DPLL Unlocked Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 30. "LOCK,DPLL locked Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "SECE,Security/Safety Report Enable" "0,1"
|
|
bitfld.long 0x0 13. "TXOVR,Transmit Over Flow Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "TXUDR,Transmit Under Flow Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 11. "TXCHUNK,Transmit FIFO Chunk Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "TXFULL,Transmit FIFO Full Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmit FIFO Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXRDY,Transmit Ready Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 5. "RXOVR,Receive Over Flow Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXUDR,Receive Under Flow Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 3. "RXCHUNK,Receive FIFO Chunk Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXFULL,Receive FIFO Full Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "RXEMPTY,Receive FIFO Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,Receive Ready Interrupt Enable" "0,1"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x78)++0x3
|
|
line.long 0x0 "IDR[$1],Interrupt Disable Register x"
|
|
bitfld.long 0x0 31. "UNLOCK,DPLL Unlocked Interrupt Disable" "0,1"
|
|
bitfld.long 0x0 30. "LOCK,DPLL locked Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "SECE,Security/Safety Report Disable" "0,1"
|
|
bitfld.long 0x0 13. "TXOVR,Transmit Over Flow Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "TXUDR,Transmit Under Flow Interrupt Disable" "0,1"
|
|
bitfld.long 0x0 11. "TXCHUNK,Transmit FIFO Chunk Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "TXFULL,Transmit FIFO Full Interrupt Disable" "0,1"
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmit FIFO Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXRDY,Transmit Ready Interrupt Disable" "0,1"
|
|
bitfld.long 0x0 5. "RXOVR,Receive Over Flow Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXUDR,Receive Under Flow Interrupt Disable" "0,1"
|
|
bitfld.long 0x0 3. "RXCHUNK,Receive FIFO Chunk Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXFULL,Receive FIFO Full Interrupt Disable" "0,1"
|
|
bitfld.long 0x0 1. "RXEMPTY,Receive FIFO Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,Receive Ready Interrupt Disable" "0,1"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x88)++0x3
|
|
line.long 0x0 "IMR[$1],Interrupt Mask Register x"
|
|
bitfld.long 0x0 31. "UNLOCK,DPLL Unlocked Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 30. "LOCK,DPLL locked Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "SECE,Security/Safety Report Mask" "0,1"
|
|
bitfld.long 0x0 13. "TXOVR,Transmit Over Flow Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "TXUDR,Transmit Under Flow Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 11. "TXCHUNK,Transmit FIFO Chunk Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "TXFULL,Transmit FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmit FIFO Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXRDY,Transmit Ready Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 5. "RXOVR,Receive Over Flow Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXUDR,Receive Under Flow Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 3. "RXCHUNK,Receive FIFO Chunk Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXFULL,Receive FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 1. "RXEMPTY,Receive FIFO Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,Receive Ready Interrupt Mask" "0,1"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x98)++0x3
|
|
line.long 0x0 "ISR[$1],Interrupt Status Register x"
|
|
bitfld.long 0x0 31. "UNLOCK,DPLL Unlocked Interrupt Status" "0,1"
|
|
bitfld.long 0x0 30. "LOCK,DPLL locked Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "SECE,Security and/or Safety Event (cleared on read)" "0: No security or safety event has occurred since..,1: One or more safety or security events has.."
|
|
bitfld.long 0x0 13. "TXOVR,Transmit Over Flow Interrupt Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "TXUDR,Transmit Under Flow Interrupt Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 11. "TXCHUNK,Transmit FIFO Chunk Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "TXFULL,Transmit FIFO Full Interrupt Status" "0,1"
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmit FIFO Empty Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXRDY,Transmit Ready Interrupt Status" "0,1"
|
|
bitfld.long 0x0 5. "RXOVR,Receive Over Flow Interrupt Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXUDR,Receive Under Flow Interrupt Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 3. "RXCHUNK,Receive FIFO Chunk Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXFULL,Receive FIFO Full Interrupt Status" "0,1"
|
|
bitfld.long 0x0 1. "RXEMPTY,Receive FIFO Empty Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,Receive Ready Interrupt Status" "0,1"
|
|
repeat.end
|
|
rgroup.long 0xA8++0x3
|
|
line.long 0x0 "ESR,Error Status Register"
|
|
bitfld.long 0x0 15. "DERR,DSP Overflow Error" "0: No DSP overflow error detected.,1: The sampling frequency overpasses the value.."
|
|
hexmask.long.byte 0x0 8.--12. 1. "OUTCFGERR,Output Configuration Error"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "INCFGERR,Input Configuration Error"
|
|
group.long 0xE4++0x7
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Register Enable" "0: The write protection of interrupts is disabled,1: The write protection of interrupts is enabled."
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: The write protection of interrupt registers is..,1: The write protection of interrupt registers is.."
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: The write protection is disabled,1: The write protection is enabled. All write.."
|
|
line.long 0x4 "WPSR,Write Protection Status Register"
|
|
bitfld.long 0x4 24.--25. "SWETYP,Software Error Type (cleared on read)" "0: A Write-only register has been read.,1: A write access has been performed on a Read-only..,2: Access to an undefined address.,?"
|
|
hexmask.long.word 0x4 8.--23. 1. "WPSRC,Write Protection Source (cleared on read)"
|
|
newline
|
|
bitfld.long 0x4 3. "SWE,Software Control Error (cleared on read)" "0: No software error has occurred since the last..,1: A software error has occurred since the last.."
|
|
bitfld.long 0x4 2. "SEQE,Internal Sequencer Error (cleared on read)" "0: No peripheral internal sequencer error has..,1: A peripheral internal sequencer error has.."
|
|
newline
|
|
bitfld.long 0x4 0. "WPVS,Write Protection Violation Status (cleared on read)" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
|
|
tree.end
|
|
tree "BSC (Boot Sequence Controller)"
|
|
base ad:0xE001D054
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR,Boot Sequence Controller Configuration Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "WPKEY,Write Protection Key (Write-only)"
|
|
hexmask.long.word 0x0 0.--15. 1. "BOOT,Boot Media Sequence"
|
|
tree.end
|
|
tree "CHIPID (Chip Identifier)"
|
|
base ad:0xE0020000
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "CIDR,Chip ID Register"
|
|
bitfld.long 0x0 31. "EXT,Extension Flag" "0: Chip ID has a single register definition without..,1: An extended Chip ID exists."
|
|
hexmask.long.tbyte 0x0 5.--27. 1. "ID,Product ID"
|
|
bitfld.long 0x0 4. "ONE,Must be at '1'" "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "VERSION,Version of the Device"
|
|
line.long 0x4 "EXID,Chip ID Extension Register"
|
|
hexmask.long 0x4 0.--31. 1. "EXID,Chip ID Extension"
|
|
tree.end
|
|
tree "CPKCC (Classic Public Key Cryptography Controller)"
|
|
base ad:0xE000C000
|
|
group.long 0x0++0x2B
|
|
line.long 0x0 "R,R Parameter Register"
|
|
hexmask.long 0x0 0.--31. 1. "VALUE,CPKCC_R value"
|
|
line.long 0x4 "X,X Parameter Register"
|
|
hexmask.long 0x4 0.--31. 1. "VALUE,CPKCC_X value"
|
|
line.long 0x8 "Y,Y Parameter Register"
|
|
hexmask.long 0x8 0.--31. 1. "VALUE,CPKCC_Y value"
|
|
line.long 0xC "Z,Z Parameter Register"
|
|
hexmask.long 0xC 0.--31. 1. "VALUE,CPKCC_Z value"
|
|
line.long 0x10 "J,J Parameter Register"
|
|
hexmask.long 0x10 0.--31. 1. "VALUE,CPKCC_J value"
|
|
line.long 0x14 "K,K Parameter Register"
|
|
hexmask.long 0x14 0.--31. 1. "VALUE,CPKCC_K value"
|
|
line.long 0x18 "N,N Parameter Register"
|
|
hexmask.long 0x18 0.--31. 1. "VALUE,CPKCC_N value"
|
|
line.long 0x1C "SMULA,SMULA Register"
|
|
hexmask.long 0x1C 0.--31. 1. "VALUE,CPKCC_SMULA value"
|
|
line.long 0x20 "SMULB,SMULB Register"
|
|
hexmask.long 0x20 0.--31. 1. "VALUE,CPKCC_SMULB value"
|
|
line.long 0x24 "SMULRL,SMULRL Register"
|
|
hexmask.long 0x24 0.--31. 1. "VALUE,CPKCC_SMULRL value"
|
|
line.long 0x28 "SMULRH,SMULRH Register"
|
|
hexmask.long 0x28 0.--31. 1. "VALUE,CPKCC_SMULRH value"
|
|
group.byte 0x2C++0x1
|
|
line.byte 0x0 "IDLE,IDLE Register"
|
|
hexmask.byte 0x0 0.--7. 1. "VALUE,CPKCC_IDLE value"
|
|
line.byte 0x1 "IDLECACHE,IDLECACHE Register"
|
|
hexmask.byte 0x1 0.--7. 1. "VALUE,CPKCC_IDLECACHE value"
|
|
group.long 0x30++0x13
|
|
line.long 0x0 "CR_C,CR_C Register"
|
|
hexmask.long 0x0 0.--31. 1. "VALUE,CPKCC_CR_C value"
|
|
line.long 0x4 "CR_S,CR_S Register"
|
|
hexmask.long 0x4 0.--31. 1. "VALUE,CPKCC_CR_S value"
|
|
line.long 0x8 "CR,CR Register"
|
|
hexmask.long.tbyte 0x8 9.--31. 1. "VALUE,CPKCC_CR value"
|
|
bitfld.long 0x8 8. "CLRRAM,CLRRAM value" "0,1"
|
|
bitfld.long 0x8 7. "ITEN,ITEN value" "0,1"
|
|
bitfld.long 0x8 6. "PKCCIRQ,CPKCC_IRQ value" "0,1"
|
|
bitfld.long 0x8 5. "AWAKE,AWAKE value" "0,1"
|
|
bitfld.long 0x8 4. "SPILLW,Spill Word register bit" "0,1"
|
|
bitfld.long 0x8 3. "ABORT,ABORT value" "0,1"
|
|
bitfld.long 0x8 2. "ONEMUL,ONEMUL value" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "CARRYIN,CARRYIN value" "0,1"
|
|
bitfld.long 0x8 0. "GF2N,GF(2n) mode" "0,1"
|
|
line.long 0xC "OR,Operation Register"
|
|
hexmask.long.tbyte 0xC 11.--31. 1. "VALUE,CPKCC_OR value"
|
|
bitfld.long 0xC 10. "CARRYMUL,CARRYMUL value" "0,1"
|
|
bitfld.long 0xC 7. "OPTC1,OPTC1 value" "0,1"
|
|
bitfld.long 0xC 6. "OPTC0,OPTC0 value" "0,1"
|
|
bitfld.long 0xC 5. "OPTM1,OPTM1 value" "0,1"
|
|
bitfld.long 0xC 4. "OPTM0,OPTM0 value" "0,1"
|
|
bitfld.long 0xC 3. "CMD3,CMD3 value" "0,1"
|
|
bitfld.long 0xC 2. "CMD2,CMD2 value" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "CMD1,CMD1 value" "0,1"
|
|
bitfld.long 0xC 0. "CMD0,CMD0 value" "0,1"
|
|
line.long 0x10 "SR,SR Register"
|
|
hexmask.long 0x10 7.--31. 1. "VALUE,CPKCC_SR value"
|
|
bitfld.long 0x10 6. "CLRRAM_BUSY,CLRRAM_BUSY value" "0,1"
|
|
bitfld.long 0x10 5. "SHAREV,SHAREV value" "0,1"
|
|
bitfld.long 0x10 4. "RAMV,RAM violation" "0,1"
|
|
bitfld.long 0x10 3. "ZERO,ZERO value" "0,1"
|
|
bitfld.long 0x10 2. "CARRY,CARRY value" "0,1"
|
|
bitfld.long 0x10 1. "CACHE,CACHE value" "0,1"
|
|
bitfld.long 0x10 0. "BUSY,BUSY value" "0,1"
|
|
group.long 0xEC++0x3
|
|
line.long 0x0 "ADDRSIZE,ADDRSIZE Register"
|
|
hexmask.long 0x0 0.--31. 1. "VALUE,CPKCC_ADDRSIZE value"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xF0)++0x3
|
|
line.long 0x0 "IPNAME[$1],IPNAME1 Register"
|
|
hexmask.long 0x0 0.--31. 1. "VALUE,CPKCC_IPNAME1 value"
|
|
repeat.end
|
|
group.long 0xF8++0x3
|
|
line.long 0x0 "FEATURES,FEATURES Register"
|
|
hexmask.long 0x0 0.--31. 1. "VALUE,CPKCC_FEATURES value"
|
|
tree.end
|
|
tree "CSI (Camera Serial Interface)"
|
|
base ad:0xE1400000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "VERSION,Read-only register Contains the version of DWC_mipi_csi2_host coded in 32-bit ASCII code."
|
|
hexmask.long 0x0 0.--31. 1. "VERSION,This field indicates the version of the DWC_mipi_csi2_host."
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "N_LANES,Static read and write register Configures the number of active lanes that the DWC_mipi_csi2_host uses to receive the camera device data."
|
|
bitfld.long 0x0 0.--2. "N_LANES,Number of active data lanes: -000: 1 Data Lane -001: 2 Data Lanes -010: 3 Data Lanes -011: 4 Data Lanes - Only on D-PHY -100: 5 Data Lanes - Only on D-PHY -101: 6 Data Lanes - Only on D-PHY -110: 7 Data Lanes - Only on D-PHY -111: 8 Data.." "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "CSI2_RESETN,Static read and write register Controls the DWC_mipi_csi2_host logic reset state. When activated. the internal logic of the controller goes into the reset state. The configuration is not reset to default values with this register. instead..."
|
|
bitfld.long 0x4 0. "CSI2_RESETN,DWC_mipi_csi2_host reset output. Active Low." "0,1"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "INT_ST_MAIN,Clear on read register Contains the status of individual interrupt sources. regardless of the contents of the associated interrupt mask registers. so it is possible to service the interrupt status registers by polling. Reading INT_ST_MAIN.."
|
|
bitfld.long 0x0 18. "STATUS_INT_LINE,Status of int_st_line" "0,1"
|
|
bitfld.long 0x0 17. "STATUS_INT_PKT,Status of int_st_pkt." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "STATUS_INT_PHY,Status of int_st_phy." "0,1"
|
|
bitfld.long 0x0 2. "STATUS_INT_FRAME_FATAL,Status of int_st_frame_fatal." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STATUS_INT_PKT_FATAL,Status of int_st_pkt_fatal." "0,1"
|
|
bitfld.long 0x0 0. "STATUS_INT_PHY_FATAL,Status of int_st_phy_fatal." "0,1"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "DATA_IDS_1,Static read and write register Programs the data Ids for matching line error reporting. Enables up to eight different data Ids that can be identified simultaneously."
|
|
bitfld.long 0x0 30.--31. "DI3_VC,Virtual channel for programmed data Id 3." "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--29. 1. "DI3_DT,Data type for programmed data Id 3."
|
|
newline
|
|
bitfld.long 0x0 22.--23. "DI2_VC,Virtual channel for programmed data Id 2." "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--21. 1. "DI2_DT,Data type for programmed Data ID 2."
|
|
newline
|
|
bitfld.long 0x0 14.--15. "DI1_VC,Virtual channel for programmed data Id 1." "0,1,2,3"
|
|
hexmask.long.byte 0x0 8.--13. 1. "DI1_DT,Data type for programmed data Id 1."
|
|
newline
|
|
bitfld.long 0x0 6.--7. "DI0_VC,Virtual channel for programmed data Id 0." "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DI0_DT,Data type for programmed data Id 0."
|
|
line.long 0x4 "DATA_IDS_2,Static read and write register Programs the data Ids for matching line error reporting. Configures Data ID definition for four additional pairs of data types and virtual channel identifiers."
|
|
bitfld.long 0x4 30.--31. "DI7_VC,Virtual channel for programmed data Id 7." "0,1,2,3"
|
|
hexmask.long.byte 0x4 24.--29. 1. "DI7_DT,Data type for programmed data Id 7."
|
|
newline
|
|
bitfld.long 0x4 22.--23. "DI6_VC,Virtual channel for programmed data Id 6." "0,1,2,3"
|
|
hexmask.long.byte 0x4 16.--21. 1. "DI6_DT,Data type for programmed data Id 6."
|
|
newline
|
|
bitfld.long 0x4 14.--15. "DI5_VC,Virtual channel for programmed data Id 5." "0,1,2,3"
|
|
hexmask.long.byte 0x4 8.--13. 1. "DI5_DT,Data type for programmed data Id 5."
|
|
newline
|
|
bitfld.long 0x4 6.--7. "DI4_VC,Virtual channel for programmed data Id 4." "0,1,2,3"
|
|
hexmask.long.byte 0x4 0.--5. 1. "DI4_DT,Data type for programmed data Id 4."
|
|
group.long 0x40++0x7
|
|
line.long 0x0 "PHY_SHUTDOWNZ,Active low Controls the PHY Shutdown mode. In this state. the PHY sets the analog and digital circuitry in the Reset state."
|
|
bitfld.long 0x0 0. "PHY_SHUTDOWNZ,Shutdown input. This line is used to place the complete macro in power down. All analog blocks are in power down mode and digital logic is cleared. Active Low." "0,1"
|
|
line.long 0x4 "DPHY_RSTZ,Active low Controls the PHY Reset mode. in this state. the PHY sets the digital circuitry in the Reset State."
|
|
bitfld.long 0x4 0. "DPHY_RSTZ,PHY reset output. Active Low." "0,1"
|
|
rgroup.long 0x48++0x7
|
|
line.long 0x0 "PHY_RX,Read-only register Contains the status of RX-related signals from PHY: RXULPSESC* RXCLKACTIVEHS (D-PHY) It contains information such as. if the clock lane is receiving high-speed clock signal. or if the data and clock lanes are in Ultra Low.."
|
|
bitfld.long 0x0 17. "PHY_RXCLKACTIVEHS,Indicates that D-PHY clock lane is actively receiving a DDR clock" "0,1"
|
|
bitfld.long 0x0 16. "PHY_RXULPSCLKNOT,Active Low. This signal indicates that D-PHY Clock Lane module has entered the Ultra Low Power state" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PHY_RXULPSESC_1,Lane module 1 has entered the Ultra Low Power mode" "0,1"
|
|
bitfld.long 0x0 0. "PHY_RXULPSESC_0,Lane module 0 has entered the Ultra Low Power mode." "0,1"
|
|
line.long 0x4 "PHY_STOPSTATE,Read-only register Contains the STOPSTATE signal status from PHY."
|
|
bitfld.long 0x4 16. "PHY_STOPSTATECLK,D-PHY Clock lane in Stop state" "0,1"
|
|
bitfld.long 0x4 1. "PHY_STOPSTATEDATA_1,Data lane 1 in Stop state" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "PHY_STOPSTATEDATA_0,Data lane 0 in Stop state." "0,1"
|
|
group.long 0x50++0x7
|
|
line.long 0x0 "PHY_TEST_CTRL0,Dynamic register Control for vendor specific interface in the PHY. Controls the Synopsys D-PHY Test and Control interface. This register controls the TESTCLR and TESTCLK signals."
|
|
bitfld.long 0x0 1. "PHY_TESTCLK,Clock to capture testdin bus contents into the macro with testen signal controlling the operation selection." "0,1"
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|
bitfld.long 0x0 0. "PHY_TESTCLR,When active performs vendor specific interface initialization. Active High. Note: This line needs an initial high pulse after power up for analog programmability default values to be preset." "0,1"
|
|
line.long 0x4 "PHY_TEST_CTRL1,Dynamic register Control for vendor specific interface in the PHY. Controls the Synopsys D-PHY Test and Control interface. This register controls the TESTENABLE signal and the TESTDIN bus. Reading from this register retrieves the value.."
|
|
bitfld.long 0x4 16. "PHY_TESTEN,When asserted high it configures an address write operation on the falling edge of testclk. When asserted low it configures a data write operation on the rising edge of testclk." "0,1"
|
|
hexmask.long.byte 0x4 8.--15. 1. "PHY_TESTDOUT,Vendor-specific 8-bit data output for reading data and other probing functionalities."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "PHY_TESTDIN,Test interface 8-bit data input for programming internal registers and accessing test functionalities."
|
|
group.long 0x80++0x1F
|
|
line.long 0x0 "IPI_MODE,This register selects how the IPI interface generates the video frame"
|
|
bitfld.long 0x0 8. "IPI_COLOR_COM,This field indicates if color mode components are delivered as follows: - 0: 48 bits interface - 1: 16 bits interface" "0,1"
|
|
bitfld.long 0x0 0. "IPI_MODE,This field indicates the video mode transmission type as follows: - 0: Camera timing - 1: Controller timing" "0: Camera timing,1: Controller timing"
|
|
line.long 0x4 "IPI_VCID,This register selects the virtual channel processed by IPI"
|
|
bitfld.long 0x4 0.--1. "IP_VCID,Virtual channel of data to be processed by pixel interface" "0,1,2,3"
|
|
line.long 0x8 "IPI_DATA_TYPE,This register selects the data type processed by IPI"
|
|
hexmask.long.byte 0x8 0.--5. 1. "IPI_DATA_TYPE,Data type of data to be processed by pixel interface"
|
|
line.long 0xC "IPI_MEM_FLUSH,This register control the flush of IPI memory"
|
|
bitfld.long 0xC 8. "IPI_AUTO_FLUSH,Memory is automatically flushed at each vsync" "0,1"
|
|
bitfld.long 0xC 0. "IPI_FLUSH,Flush IPI memory. This bit is auto clear" "0,1"
|
|
line.long 0x10 "IPI_HSA_TIME,This register configures the video Horizontal Synchronism Active (HSA) time"
|
|
hexmask.long.word 0x10 0.--11. 1. "IPI_HSA_TIME,This field configures the Horizontal Synchronism Active period in pixclk cycles"
|
|
line.long 0x14 "IPI_HBP_TIME,This register configures the video Horizontal Back Porch (HBP) time"
|
|
hexmask.long.word 0x14 0.--11. 1. "IPI_HBP_TIME,This field configures the Horizontal Back Porch period in pixclk cycles"
|
|
line.long 0x18 "IPI_HSD_TIME,This register configures the video Horizontal Sync Delay (HSD) time"
|
|
hexmask.long.word 0x18 0.--11. 1. "IPI_HSD_TIME,This field configures the Horizontal Sync Porch delay period in pixclk cycles"
|
|
line.long 0x1C "IPI_HLINE_TIME,This register configures the overall time for each video line"
|
|
hexmask.long.word 0x1C 0.--14. 1. "IPI_HLINE_TIME,This field configures the size of the line time counted in pixclk cycles"
|
|
group.long 0xB0++0xF
|
|
line.long 0x0 "IPI_VSA_LINES,This register configures the Vertical Synchronism Active (VSA) period"
|
|
hexmask.long.word 0x0 0.--9. 1. "IPI_VSA_LINES,This field configures the Vertical Synchronism Active period measured in number of horizontal lines"
|
|
line.long 0x4 "IPI_VBP_LINES,This register configures the Vertical Back Porch (VBP) period"
|
|
hexmask.long.word 0x4 0.--9. 1. "IPI_VBP_LINES,This field configures the Vertical Back Porch period measured in number of horizontal lines"
|
|
line.long 0x8 "IPI_VFP_LINES,This register configures the Vertical Front Porch (VFP) period"
|
|
hexmask.long.word 0x8 0.--9. 1. "IPI_VFP_LINES,This field configures the Vertical Front Porch period measured in number of horizontal lines"
|
|
line.long 0xC "IPI_VACTIVE_LINES,This register configures the vertical resolution of the video"
|
|
hexmask.long.word 0xC 0.--13. 1. "IPI_VACTIVE_LINES,This field configures the Vertical Active period measured in number of horizontal lines"
|
|
rgroup.long 0xCC++0x3
|
|
line.long 0x0 "PHY_CAL,Clear on read register Contains the CALIBRATION signal status from Synopsys D-PHY."
|
|
bitfld.long 0x0 0. "RXSKEWCALHS,A low-to-high transition on rxskewcalhs signal means that the PHY has initiated the de-skew calibration.." "0,1"
|
|
rgroup.long 0xE0++0x3
|
|
line.long 0x0 "INT_ST_PHY_FATAL,Clear on read register Groups the fatal interruptions caused by PHY Packet discarded. Stores the source of the error. Reading INT_ST_PHY_FATAL register does not clear the interrupt pin."
|
|
bitfld.long 0x0 1. "PHY_ERRSOTSYNCHS_1,Start of transmission error on data lane 1 (no synchronization achieved)" "0,1"
|
|
bitfld.long 0x0 0. "PHY_ERRSOTSYNCHS_0,Start of transmission error on data lane 0 (no synchronization achieved)." "0,1"
|
|
group.long 0xE4++0x7
|
|
line.long 0x0 "INT_MSK_PHY_FATAL,Static read and write register Interrupt mask for INT_ST_PHY_FATAL controls which interrupt status bits will trigger the interrupt pin. Bit at 1 - Enable the interrupt source. Bit at 0 - Interrupt source is masked."
|
|
bitfld.long 0x0 1. "MASK_PHY_ERRSOTSYNCHS_1,Mask for phy_errsotsynchs_1" "0,1"
|
|
bitfld.long 0x0 0. "MASK_PHY_ERRSOTSYNCHS_0,Mask for phy_errsotsynchs_0." "0,1"
|
|
line.long 0x4 "INT_FORCE_PHY_FATAL,Static read and write register Interrupt Force register is used for test purposes. and allows triggering INT_ST_PHY_FATAL interrupt events individually. without the need to activate the conditions that trigger the interrupt.."
|
|
bitfld.long 0x4 1. "FORCE_PHY_ERRSOTSYNCHS_1,Force phy_errsotsynchs_1" "0,1"
|
|
bitfld.long 0x4 0. "FORCE_PHY_ERRSOTSYNCHS_0,Force phy_errsotsynchs_0." "0,1"
|
|
rgroup.long 0xF0++0x3
|
|
line.long 0x0 "INT_ST_PKT_FATAL,Clear on read register Groups the fatal interruption related with Packet construction. Packet discarded. Notifies which interruption bit has caused the interruption. Stores the source of the error. Reading INT_ST_PKT_FATAL.."
|
|
bitfld.long 0x0 16. "ERR_ECC_DOUBLE,D-PHY mode : Header ECC contains at least 2 errors unrecoverable. C-PHY mode : Header CRC unrecoverable." "0,1"
|
|
bitfld.long 0x0 3. "VC3_ERR_CRC,Payload Checksum error detected on virtual channel 3." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "VC2_ERR_CRC,Payload Checksum error detected on virtual channel 2." "0,1"
|
|
bitfld.long 0x0 1. "VC1_ERR_CRC,Payload Checksum error detected on virtual channel 1." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "VC0_ERR_CRC,Payload Checksum error detected on virtual channel 0." "0,1"
|
|
group.long 0xF4++0x7
|
|
line.long 0x0 "INT_MSK_PKT_FATAL,Static read and write register Interrupt mask for INT_ST_PKT_FATAL controls which interrupt status bits will trigger the interrupt pin. Bit at 1 - Enable the interrupt source. Bit at 0 - Interrupt source is masked."
|
|
bitfld.long 0x0 16. "MASK_ERR_ECC_DOUBLE,Mask for err_ecc_double." "0,1"
|
|
bitfld.long 0x0 3. "MASK_VC3_ERR_CRC,Mask for vc3_err_crc." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MASK_VC2_ERR_CRC,Mask for vc2_err_crc." "0,1"
|
|
bitfld.long 0x0 1. "MASK_VC1_ERR_CRC,Mask for vc1_err_crc." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MASK_VC0_ERR_CRC,Mask for vc0_err_crc." "0,1"
|
|
line.long 0x4 "INT_FORCE_PKT_FATAL,Static read and write register Interrupt force register is used for test purposes. and allows triggering INT_ST_PKT_FATAL interrupt events individually. without the need to activate the conditions that trigger the interrupt sources..."
|
|
bitfld.long 0x4 16. "FORCE_ERR_ECC_DOUBLE,Force err_ecc_double." "0,1"
|
|
bitfld.long 0x4 3. "FORCE_VC3_ERR_CRC,Force vc3_err_crc." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "FORCE_VC2_ERR_CRC,Force vc2_err_crc." "0,1"
|
|
bitfld.long 0x4 1. "FORCE_VC1_ERR_CRC,Force vc1_err_crc." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "FORCE_VC0_ERR_CRC,Force vc0_err_crc." "0,1"
|
|
rgroup.long 0x100++0x3
|
|
line.long 0x0 "INT_ST_FRAME_FATAL,Clear on read register Fatal interruption related with Frame construction. Packet discarded. Groups and notifies which interruption bits caused the interruption. Stores the source of the error. Reading INT_ST_FRAME_FATAL.."
|
|
bitfld.long 0x0 19. "ERR_FRAME_DATA_VC3,Last received Frame in virtual channel 3 had at least one CRC error." "0,1"
|
|
bitfld.long 0x0 18. "ERR_FRAME_DATA_VC2,Last received Frame in virtual channel 2 had at least one CRC error." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ERR_FRAME_DATA_VC1,Last received Frame in virtual channel 1 had at least one CRC error." "0,1"
|
|
bitfld.long 0x0 16. "ERR_FRAME_DATA_VC0,Last received Frame in virtual channel 0 had at least one CRC error." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "ERR_F_SEQ_VC3,Incorrect Frame sequence detected in Virtual Channel 3." "0,1"
|
|
bitfld.long 0x0 10. "ERR_F_SEQ_VC2,Incorrect Frame sequence detected in Virtual Channel 2." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ERR_F_SEQ_VC1,Incorrect Frame sequence detected in Virtual Channel 1." "0,1"
|
|
bitfld.long 0x0 8. "ERR_F_SEQ_VC0,Incorrect Frame sequence detected in Virtual Channel 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ERR_F_BNDRY_MATCH_VC3,Error matching Frame Start with Frame End for virtual channel 3." "0,1"
|
|
bitfld.long 0x0 2. "ERR_F_BNDRY_MATCH_VC2,Error matching Frame Start with Frame End for virtual channel 2." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ERR_F_BNDRY_MATCH_VC1,Error matching Frame Start with Frame End for virtual channel 1." "0,1"
|
|
bitfld.long 0x0 0. "ERR_F_BNDRY_MATCH_VC0,Error matching Frame Start with Frame End for virtual channel 0." "0,1"
|
|
group.long 0x104++0x7
|
|
line.long 0x0 "INT_MSK_FRAME_FATAL,Static read and write register Interrupt mask for INT_ST_FRAME_FATAL controls which interrupt status bits will trigger the interrupt pin. Bit at 1 - Enable the interrupt source. Bit at 0 - Interrupt source is masked."
|
|
bitfld.long 0x0 19. "MASK_ERR_FRAME_DATA_VC3,Mask for err_frame_data_vc3." "0,1"
|
|
bitfld.long 0x0 18. "MASK_ERR_FRAME_DATA_VC2,Mask for err_frame_data_vc2." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MASK_ERR_FRAME_DATA_VC1,Mask for err_frame_data_vc1." "0,1"
|
|
bitfld.long 0x0 16. "MASK_ERR_FRAME_DATA_VC0,Mask for err_frame_data_vc0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "MASK_ERR_F_SEQ_VC3,Mask for err_f_seq_vc3." "0,1"
|
|
bitfld.long 0x0 10. "MASK_ERR_F_SEQ_VC2,Mask for err_f_seq_vc2." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "MASK_ERR_F_SEQ_VC1,Mask for err_f_seq_vc1." "0,1"
|
|
bitfld.long 0x0 8. "MASK_ERR_F_SEQ_VC0,Mask for err_f_seq_vc0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MASK_ERR_F_BNDRY_MATCH_VC3,Mask for err_f_bndry_match_vc3." "0,1"
|
|
bitfld.long 0x0 2. "MASK_ERR_F_BNDRY_MATCH_VC2,Mask for err_f_bndry_match_vc2." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MASK_ERR_F_BNDRY_MATCH_VC1,Mask for err_f_bndry_match_vc1." "0,1"
|
|
bitfld.long 0x0 0. "MASK_ERR_F_BNDRY_MATCH_VC0,Mask for err_f_bndry_match_vc0." "0,1"
|
|
line.long 0x4 "INT_FORCE_FRAME_FATAL,Static read and write register Interrupt force register is used for test purposes. and allows triggering INT_ST_FRAME_FATAL interrupt events individually. without the need to activate the conditions that trigger the interrupt.."
|
|
bitfld.long 0x4 19. "FORCE_ERR_FRAME_DATA_VC3,Force err_frame_data_vc3." "0,1"
|
|
bitfld.long 0x4 18. "FORCE_ERR_FRAME_DATA_VC2,Force err_frame_data_vc2." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "FORCE_ERR_FRAME_DATA_VC1,Force err_frame_data_vc1." "0,1"
|
|
bitfld.long 0x4 16. "FORCE_ERR_FRAME_DATA_VC0,Force err_frame_data_vc0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "FORCE_ERR_F_SEQ_VC3,Force err_f_seq_vc3." "0,1"
|
|
bitfld.long 0x4 10. "FORCE_ERR_F_SEQ_VC2,Force err_f_seq_vc2." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "FORCE_ERR_F_SEQ_VC1,Force err_f_seq_vc1." "0,1"
|
|
bitfld.long 0x4 8. "FORCE_ERR_F_SEQ_VC0,Force err_f_seq_vc0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FORCE_ERR_F_BNDRY_MATCH_VC3,Force err_f_bndry_match_vc3." "0,1"
|
|
bitfld.long 0x4 2. "FORCE_ERR_F_BNDRY_MATCH_VC2,Force err_f_bndry_match_vc2." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "FORCE_ERR_F_BNDRY_MATCH_VC1,Force err_f_bndry_match_vc1." "0,1"
|
|
bitfld.long 0x4 0. "FORCE_ERR_F_BNDRY_MATCH_VC0,Force err_f_bndry_match_vc0." "0,1"
|
|
rgroup.long 0x110++0x3
|
|
line.long 0x0 "INT_ST_PHY,Clear on read register Interruption caused by PHY. Groups and notifies which interruption bits caused the interruption. Stores the source of the error. Reading INT_ST_PHY register does not clear the interrupt pin."
|
|
bitfld.long 0x0 17. "PHY_ERRESC_1,Start of Transmission Error on data lane 1 (no synchronization achieved)" "0,1"
|
|
bitfld.long 0x0 16. "PHY_ERRESC_0,Start of Transmission Error on data lane 0 (no synchronization achieved)." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PHY_ERRSOTHS_1,Start of transmission error on data lane 1 (synchronization can still be achieved)" "0,1"
|
|
bitfld.long 0x0 0. "PHY_ERRSOTHS_0,Start of transmission error on data lane 0 (synchronization can still be achieved)." "0,1"
|
|
group.long 0x114++0x7
|
|
line.long 0x0 "INT_MSK_PHY,Static read and write register Interrupt mask for INT_ST_PHY controls which interrupt status bits will trigger the interrupt pin. Bit at 1 - Enable the interrupt source. Bit at 0 - Interrupt source is masked."
|
|
bitfld.long 0x0 17. "MASK_PHY_ERRESC_1,Mask for phy_erresc_1" "0,1"
|
|
bitfld.long 0x0 16. "MASK_PHY_ERRESC_0,Mask for phy_erresc_0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MASK_PHY_ERRSOTHS_1,Mask for phy_errsoths_1" "0,1"
|
|
bitfld.long 0x0 0. "MASK_PHY_ERRSOTHS_0,Mask for phy_errsoths_0." "0,1"
|
|
line.long 0x4 "INT_FORCE_PHY,Static read and write register Interrupt force register is used for test purposes. and allows triggering INT_ST_PHY interrupt events individually. without the need to activate the conditions that trigger the interrupt sources. because it.."
|
|
bitfld.long 0x4 17. "FORCE_PHY_ERRESC_1,Force phy_erresc_1" "0,1"
|
|
bitfld.long 0x4 16. "FORCE_PHY_ERRESC_0,Force phy_erresc_0" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "FORCE_PHY_ERRSOTHS_1,Force phy_errsoths_1" "0,1"
|
|
bitfld.long 0x4 0. "FORCE_PHY_ERRSOTHS_0,Force phy_errsoths_0." "0,1"
|
|
rgroup.long 0x120++0x3
|
|
line.long 0x0 "INT_ST_PKT,Clear on read register Interruption related with Packet construction. Packet discarded. Groups and notifies which interruption bits caused the interruption. Stores the source of the error. Reading INT_ST_PKT register does not clear.."
|
|
bitfld.long 0x0 19. "VC3_ERR_ECC_CORRECTED,D-PHY mode : Header error detected and corrected on virtual channel 3. C-PHY mode : Header CRC recoverable on virtual channel 3." "0,1"
|
|
bitfld.long 0x0 18. "VC2_ERR_ECC_CORRECTED,D-PHY mode : Header error detected and corrected on virtual channel 2. C-PHY mode : Header CRC recoverable on virtual channel 2." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "VC1_ERR_ECC_CORRECTED,D-PHY mode : Header error detected and corrected on virtual channel 1. C-PHY mode : Header CRC recoverable on virtual channel 1." "0,1"
|
|
bitfld.long 0x0 16. "VC0_ERR_ECC_CORRECTED,D-PHY mode : Header error detected and corrected on virtual channel 0. C-PHY mode : Header CRC recoverable on virtual channel 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ERR_ID_VC3,Unrecognized or unimplemented data type detected in virtual channel 3." "0,1"
|
|
bitfld.long 0x0 2. "ERR_ID_VC2,Unrecognized or unimplemented data type detected in virtual channel 2." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ERR_ID_VC1,Unrecognized or unimplemented data type detected in virtual channel 1." "0,1"
|
|
bitfld.long 0x0 0. "ERR_ID_VC0,Unrecognized or unimplemented data type detected in virtual channel 0." "0,1"
|
|
group.long 0x124++0x7
|
|
line.long 0x0 "INT_MSK_PKT,Static read and write register Interrupt mask for INT_ST_PKT controls which interrupt status bits will trigger the interrupt pin. Bit at 1 - Enable the interrupt source. Bit at 0 - Interrupt source is masked."
|
|
bitfld.long 0x0 19. "MASK_VC3_ERR_ECC_CORRECTED,Mask for vc3_err_ecc_corrected." "0,1"
|
|
bitfld.long 0x0 18. "MASK_VC2_ERR_ECC_CORRECTED,Mask for vc2_err_ecc_corrected." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MASK_VC1_ERR_ECC_CORRECTED,Mask for vc1_err_ecc_corrected." "0,1"
|
|
bitfld.long 0x0 16. "MASK_VC0_ERR_ECC_CORRECTED,Mask for vc0_err_ecc_corrected." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MASK_ERR_ID_VC3,Mask for err_id_vc3." "0,1"
|
|
bitfld.long 0x0 2. "MASK_ERR_ID_VC2,Mask for err_id_vc2." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MASK_ERR_ID_VC1,Mask for err_id_vc1." "0,1"
|
|
bitfld.long 0x0 0. "MASK_ERR_ID_VC0,Mask for err_id_vc0." "0,1"
|
|
line.long 0x4 "INT_FORCE_PKT,Static read and write register Interrupt force register is used for test purposes. and allows triggering INT_ST_PKT interrupt events individually. without the need to activate the conditions that trigger the interrupt sources. because it.."
|
|
bitfld.long 0x4 19. "FORCE_VC3_ERR_ECC_CORRECTED,Force vc3_err_ecc_corrected." "0,1"
|
|
bitfld.long 0x4 18. "FORCE_VC2_ERR_ECC_CORRECTED,Force vc2_err_ecc_corrected." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "FORCE_VC1_ERR_ECC_CORRECTED,Force vc1_err_ecc_corrected." "0,1"
|
|
bitfld.long 0x4 16. "FORCE_VC0_ERR_ECC_CORRECTED,Force vc0_err_ecc_corrected." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FORCE_ERR_ID_VC3,Force err_id_vc3." "0,1"
|
|
bitfld.long 0x4 2. "FORCE_ERR_ID_VC2,Force err_id_vc2." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "FORCE_ERR_ID_VC1,Force err_id_vc1." "0,1"
|
|
bitfld.long 0x4 0. "FORCE_ERR_ID_VC0,Force err_id_vc0." "0,1"
|
|
rgroup.long 0x130++0x3
|
|
line.long 0x0 "INT_ST_LINE,Clear on read register Interruption related with Line construction. Groups and notifies which interruption bits caused the interruption. Stores the source of the error. Reading INT_ST_LINE register does not clear the interrupt pin."
|
|
bitfld.long 0x0 23. "ERR_L_SEQ_DI7,Error in the sequence of lines for vc7 and dt7" "0,1"
|
|
bitfld.long 0x0 22. "ERR_L_SEQ_DI6,Error in the sequence of lines for vc6 and dt6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "ERR_L_SEQ_DI5,Error in the sequence of lines for vc5 and dt5" "0,1"
|
|
bitfld.long 0x0 20. "ERR_L_SEQ_DI4,Error in the sequence of lines for vc4 and dt4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "ERR_L_SEQ_DI3,Error in the sequence of lines for vc3 and dt3" "0,1"
|
|
bitfld.long 0x0 18. "ERR_L_SEQ_DI2,Error in the sequence of lines for vc2 and dt2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ERR_L_SEQ_DI1,Error in the sequence of lines for vc1 and dt1" "0,1"
|
|
bitfld.long 0x0 16. "ERR_L_SEQ_DI0,Error in the sequence of lines for vc0 and dt0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "ERR_L_BNDRY_MATCH_DI7,Error matching line start with line end for vc7 and dt7" "0,1"
|
|
bitfld.long 0x0 6. "ERR_L_BNDRY_MATCH_DI6,Error matching line start with line end for vc6 and dt6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ERR_L_BNDRY_MATCH_DI5,Error matching line start with line end for vc5 and dt5" "0,1"
|
|
bitfld.long 0x0 4. "ERR_L_BNDRY_MATCH_DI4,Error matching line start with line end for vc4 and dt4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ERR_L_BNDRY_MATCH_DI3,Error matching line start with line end for vc3 and dt3" "0,1"
|
|
bitfld.long 0x0 2. "ERR_L_BNDRY_MATCH_DI2,Error matching line start with line end for vc2 and dt2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ERR_L_BNDRY_MATCH_DI1,Error matching line start with line end for vc1 and dt1" "0,1"
|
|
bitfld.long 0x0 0. "ERR_L_BNDRY_MATCH_DI0,Error matching line start with line end for vc0 and dt0" "0,1"
|
|
group.long 0x134++0x7
|
|
line.long 0x0 "INT_MSK_LINE,Static read and write register Interrupt mask for INT_ST_LINE controls which interrupt status bits will trigger the interrupt pin. Bit at 1 - Enable the interrupt source. Bit at 0 - Interrupt source is masked."
|
|
bitfld.long 0x0 23. "MASK_ERR_L_SEQ_DI7,Mask for err_l_seq_di7" "0,1"
|
|
bitfld.long 0x0 22. "MASK_ERR_L_SEQ_DI6,Mask for err_l_seq_di6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "MASK_ERR_L_SEQ_DI5,Mask for err_l_seq_di5" "0,1"
|
|
bitfld.long 0x0 20. "MASK_ERR_L_SEQ_DI4,Mask for err_l_seq_di4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "MASK_ERR_L_SEQ_DI3,Mask for err_l_seq_di3" "0,1"
|
|
bitfld.long 0x0 18. "MASK_ERR_L_SEQ_DI2,Mask for err_l_seq_di2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MASK_ERR_L_SEQ_DI1,Mask for err_l_seq_di1" "0,1"
|
|
bitfld.long 0x0 16. "MASK_ERR_L_SEQ_DI0,Mask for err_l_seq_di0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "MASK_ERR_L_BNDRY_MATCH_DI7,Mask for err_l_bndry_match_di7" "0,1"
|
|
bitfld.long 0x0 6. "MASK_ERR_L_BNDRY_MATCH_DI6,Mask for err_l_bndry_match_di6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MASK_ERR_L_BNDRY_MATCH_DI5,Mask for err_l_bndry_match_di5" "0,1"
|
|
bitfld.long 0x0 4. "MASK_ERR_L_BNDRY_MATCH_DI4,Mask for err_l_bndry_match_di4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MASK_ERR_L_BNDRY_MATCH_DI3,Mask for err_l_bndry_match_di3" "0,1"
|
|
bitfld.long 0x0 2. "MASK_ERR_L_BNDRY_MATCH_DI2,Mask for err_l_bndry_match_di2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MASK_ERR_L_BNDRY_MATCH_DI1,Mask for err_l_bndry_match_di1" "0,1"
|
|
bitfld.long 0x0 0. "MASK_ERR_L_BNDRY_MATCH_DI0,Mask for err_l_bndry_match_di0" "0,1"
|
|
line.long 0x4 "INT_FORCE_LINE,Static read and write register Interrupt force register is used for test purposes. and allows triggering INT_ST_LINE interrupt events individually. without the need to activate the conditions that trigger the interrupt sources. because.."
|
|
bitfld.long 0x4 23. "FORCE_ERR_L_SEQ_DI7,Force err_l_seq_di7" "0,1"
|
|
bitfld.long 0x4 22. "FORCE_ERR_L_SEQ_DI6,Force err_l_seq_di6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "FORCE_ERR_L_SEQ_DI5,Force err_l_seq_di5" "0,1"
|
|
bitfld.long 0x4 20. "FORCE_ERR_L_SEQ_DI4,Force err_l_seq_di4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "FORCE_ERR_L_SEQ_DI3,Force err_l_seq_di3" "0,1"
|
|
bitfld.long 0x4 18. "FORCE_ERR_L_SEQ_DI2,Force err_l_seq_di2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "FORCE_ERR_L_SEQ_DI1,Force err_l_seq_di1" "0,1"
|
|
bitfld.long 0x4 16. "FORCE_ERR_L_SEQ_DI0,Force err_l_seq_di0" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "FORCE_ERR_L_BNDRY_MATCH_DI7,Force err_l_bndry_match_di7" "0,1"
|
|
bitfld.long 0x4 6. "FORCE_ERR_L_BNDRY_MATCH_DI6,Force err_l_bndry_match_di6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "FORCE_ERR_L_BNDRY_MATCH_DI5,Force err_l_bndry_match_di5" "0,1"
|
|
bitfld.long 0x4 4. "FORCE_ERR_L_BNDRY_MATCH_DI4,Force err_l_bndry_match_di4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FORCE_ERR_L_BNDRY_MATCH_DI3,Force err_l_bndry_match_di3" "0,1"
|
|
bitfld.long 0x4 2. "FORCE_ERR_L_BNDRY_MATCH_DI2,Force err_l_bndry_match_di2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "FORCE_ERR_L_BNDRY_MATCH_DI1,Force err_l_bndry_match_di1" "0,1"
|
|
bitfld.long 0x4 0. "FORCE_ERR_L_BNDRY_MATCH_DI0,Force err_l_bndry_match_di0" "0,1"
|
|
rgroup.long 0x140++0x3
|
|
line.long 0x0 "INT_ST_IPI,Clear on read register Fatal Interruption caused by IPI interface. Groups and notifies which interruption bits caused the interruption. Stores the source of the error. Reading INT_ST_IPI register does not clear the interrupt pin"
|
|
bitfld.long 0x0 4. "PIXEL_IF_HLINE_ERR,Horizontal line time error (only available in controller mode)" "0,1"
|
|
bitfld.long 0x0 3. "PIXEL_IF_FIFO_NEMPTY_FS,The FIFO of pixel interface is not empty at the start of a new frame. If this is expected this interrupt should be masked" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "PIXEL_IF_FRAME_SYNC_ERR,New frame is received but previous has not been completed" "0,1"
|
|
bitfld.long 0x0 1. "PIXEL_IF_FIFO_OVERFLOW,The FIFO of pixel interface has lost information because some more data arrived when it was full" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PIXEL_IF_FIFO_UNDERFLOW,The FIFO has become empty before the expected number of pixels (calculated from the packet's header) could be extracted to the pixel interface" "0,1"
|
|
group.long 0x144++0x7
|
|
line.long 0x0 "INT_MSK_IPI,Static read and write register Each bit of this register masks the interruption from INT_ST_IPI from generating an interruption event. Once a bit of the mask is active. the respective error of the INT_ST_ IPI register is masked preventing the.."
|
|
bitfld.long 0x0 4. "MSK_PIXEL_IF_HLINE_ERR,Mask pixel_if_hline_err" "0,1"
|
|
bitfld.long 0x0 3. "MSK_PIXEL_IF_FIFO_NEMPTY_FS,Mask pixel_if_fifo_nempty_fs" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSK_FRAME_SYNC_ERR,Mask for pixel_if_frame_sync_err" "0,1"
|
|
bitfld.long 0x0 1. "MSK_PIXEL_IF_FIFO_OVERFLOW,Mask for pixel_if_fifo_overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MSK_PIXEL_IF_FIFO_UNDERFLOW,Mask for pixel_if_fifo_underflow" "0,1"
|
|
line.long 0x4 "INT_FORCE_IPI,Static read and write register Interrupt force register is used for test purposes. and allows triggering INT_ST_IPI interrupt events individually. without the need to activate the conditions that trigger the interrupt sources. because it.."
|
|
bitfld.long 0x4 4. "FORCE_PIXEL_IF_HLINE_ERR,Force pixel_if_hline_err" "0,1"
|
|
bitfld.long 0x4 3. "FORCE_PIXEL_IF_FIFO_NEMPTY_FS,Force pixel_if_fifo_nempty_fs" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "FORCE_FRAME_SYNC_ERR,Force for frame_sync_err" "0,1"
|
|
bitfld.long 0x4 1. "FORCE_PIXEL_IF_FIFO_OVERFLOW,Force for pixel_if_fifo_overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "FORCE_PIXEL_IF_FIFO_UNDERFLOW,Force for pixel_if_fifo_underflow" "0,1"
|
|
group.long 0x300++0xB
|
|
line.long 0x0 "SCRAMBLING,This register configures the De-scrambler block."
|
|
bitfld.long 0x0 0. "SCRAMBLE_ENABLE,Enables data de-scrambling on the controller side." "0,1"
|
|
line.long 0x4 "SCRAMBLING_SEED1,This register configures the seed used by De-scrambler block for lane 1"
|
|
hexmask.long.word 0x4 0.--15. 1. "SCRAMBLE_SEED_LANE1,Seed used by De-scrambler block for lane 1"
|
|
line.long 0x8 "SCRAMBLING_SEED2,This register configures the seed used by De-scrambler block for lane 2"
|
|
hexmask.long.word 0x8 0.--15. 1. "SCRAMBLE_SEED_LANE2,Seed used by De-scrambler block for lane 2"
|
|
tree.end
|
|
tree "CSI2DC (CSI-2 Demultiplexer Controller)"
|
|
base ad:0xE1404000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "GCFGR,Global Configuration Register"
|
|
hexmask.long.byte 0x0 4.--7. 1. "HLC,CSI2DC Output Waveform Inter-line Minimum Delay"
|
|
bitfld.long 0x0 3. "SECDEDN,Single Error Correction Double Error Detection Enable" "0: Packet header error correction is activated.,1: Packet header error correction is disabled."
|
|
newline
|
|
bitfld.long 0x0 2. "ULC,Use Optional Line Packet Delimiter" "0: Line packets are not used to define the line..,1: Line Start and Line End optional packets are.."
|
|
bitfld.long 0x0 1. "GPIOSEL,GPIO Parallel Interface Selection" "0: The MIPI CSI-2 serial interface is activated.,1: The GPIO parallel interface is selected and.."
|
|
newline
|
|
bitfld.long 0x0 0. "MIPIFRN,MIPI Interface Free Running Clock" "0: The sensor MIPI clock is free-running.,1: The sensor MIPI clock is gated."
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "GCTLR,Global Control Register"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0: No effect.,1: Starts a software reset operation."
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "GSR,Global Status Register"
|
|
bitfld.long 0x0 1. "ARSTIP,Asynchronous Reset in Progress" "0: No reset in progress for the asynchronous domain.,1: Asynchronous domain is being reset."
|
|
bitfld.long 0x0 0. "RSTIP,Reset in Progress" "0: No reset in progress for the synchronous domain.,1: Synchronous domain is being reset."
|
|
wgroup.long 0xC++0x7
|
|
line.long 0x0 "GIER,Global Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "DED,Packet Header Double Bit Error Detected Enable" "0,1"
|
|
bitfld.long 0x0 6. "SEC,Packet Header Single Bit Error Corrected Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "DP,Data Pipe Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "VP,Video Pipe Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "IDS,Image Data Packet Snoop Controller Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "GLP,Generic Long Packet Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "GSP,Generic Short Packet Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "SSP,Synchronization Short Packet Interrupt Enable" "0,1"
|
|
line.long 0x4 "GIDR,Global Interrupt Disable Register"
|
|
bitfld.long 0x4 7. "DED,Double Bit Error Detected Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 6. "SEC,Single Bit Error Corrected Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "DP,Data Pipe Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 4. "VP,Video Pipe Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "IDS,Image Data Packet Snoop Controller Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 2. "GLP,Generic Long Packet Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "GSP,Generic Short Packet Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "SSP,Synchronization Short Packet Interrupt Disable" "0,1"
|
|
rgroup.long 0x14++0x7
|
|
line.long 0x0 "GIMR,Global Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "DED,Double Error Detected Interrupt Disable Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 6. "SEC,Single Error Corrected Interrupt Disable Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "DP,Data Pipe Interrupt Disable Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 4. "VP,Video Pipe Interrupt Disable Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "IDS,Image Data Packet Snoop Controller Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "GLP,Generic Long Packet Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "GSP,Generic Short Packet Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "SSP,Synchronization Short Packet Interrupt Mask" "0,1"
|
|
line.long 0x4 "GISR,Global Interrupt Status Register"
|
|
bitfld.long 0x4 7. "DED,Double Bit Error Detected Interrupt Status" "0: No double bit error detected is pending.,1: A double bit error has been detected in the.."
|
|
bitfld.long 0x4 6. "SEC,Single Bit Error Corrected Interrupt Status" "0: No Single Bit Error Corrected interrupt is..,1: A single bit error has been detected and.."
|
|
newline
|
|
bitfld.long 0x4 5. "DP,Data Pipe Interrupt Status" "0: Either the interrupt source is masked at the DP..,1: A Data Pipe interrupt is pending."
|
|
bitfld.long 0x4 4. "VP,Video Pipe Interrupt Status" "0: Either the interrupt source is masked at the VP..,1: A Video Pipe interrupt is pending."
|
|
newline
|
|
bitfld.long 0x4 3. "IDS,Image Data Packet Snoop Controller Interrupt Status" "0: Either the interrupt source is masked at the IDS..,1: A new Image Data Packet interrupt is pending."
|
|
bitfld.long 0x4 2. "GLP,Generic Long Packet Interrupt Status" "0: Either the interrupt source is masked at the GLP..,1: A Generic Long Packet interrupt is pending."
|
|
newline
|
|
bitfld.long 0x4 1. "GSP,Generic Short Packet Interrupt Status" "0: Either the interrupt source is masked at the GSP..,1: A Generic Short Packet interrupt is pending."
|
|
bitfld.long 0x4 0. "SSP,Synchronization Short Packet Interrupt Status" "0: Either the interrupt source is masked at the SSP..,1: A Synchronization Short Packet interrupt is.."
|
|
wgroup.long 0x1C++0x7
|
|
line.long 0x0 "SSPIER,SSP Interrupt Enable Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "RE,"
|
|
hexmask.long.byte 0x0 12.--15. 1. "LE,Line End Interrupt Enable"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "LS,Line Start Interrupt Enable"
|
|
hexmask.long.byte 0x0 4.--7. 1. "FE,Frame End Interrupt Enable"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "FS,Frame Start Interrupt Enable"
|
|
line.long 0x4 "SSPIDR,SSP Interrupt Disable Register"
|
|
hexmask.long.byte 0x4 16.--19. 1. "RE,"
|
|
hexmask.long.byte 0x4 12.--15. 1. "LE,Line End Interrupt Disable"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "LS,Line Start Interrupt Disable"
|
|
hexmask.long.byte 0x4 4.--7. 1. "FE,Frame End Interrupt Disable"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "FS,Frame Start Interrupt Disable"
|
|
rgroup.long 0x24++0x27
|
|
line.long 0x0 "SSPIMR,SSP Interrupt Mask Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "RE,"
|
|
hexmask.long.byte 0x0 12.--15. 1. "LE,Line End Interrupt Mask"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "LS,Line Start Interrupt Mask"
|
|
hexmask.long.byte 0x0 4.--7. 1. "FE,Frame End Interrupt Mask"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "FS,Frame Start Interrupt Mask"
|
|
line.long 0x4 "SSPISR,SSP Interrupt Status Register"
|
|
hexmask.long.byte 0x4 16.--19. 1. "RE,"
|
|
hexmask.long.byte 0x4 12.--15. 1. "LE,Line End Interrupt Mask"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "LS,Line Start Interrupt Mask"
|
|
hexmask.long.byte 0x4 4.--7. 1. "FE,Frame End Interrupt Mask"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "FS,Frame Start Interrupt Mask"
|
|
line.long 0x8 "FNVC0R,Frame Number VC0 Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "FN,Frame Number for Virtual Channel 0"
|
|
line.long 0xC "FNVC1R,Frame Number VC0 Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "FN,Frame Number for Virtual Channel 0"
|
|
line.long 0x10 "FNVC2R,Frame Number VC0 Register"
|
|
hexmask.long.word 0x10 0.--15. 1. "FN,Frame Number for Virtual Channel 0"
|
|
line.long 0x14 "FNVC3R,Frame Number VC0 Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "FN,Frame Number for Virtual Channel 0"
|
|
line.long 0x18 "LNVC0R,Line Number VC0 Register"
|
|
hexmask.long.word 0x18 0.--15. 1. "LN,Line Number for Virtual Channel 0"
|
|
line.long 0x1C "LNVC1R,Line Number VC0 Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. "LN,Line Number for Virtual Channel 0"
|
|
line.long 0x20 "LNVC2R,Line Number VC0 Register"
|
|
hexmask.long.word 0x20 0.--15. 1. "LN,Line Number for Virtual Channel 0"
|
|
line.long 0x24 "LNVC3R,Line Number VC0 Register"
|
|
hexmask.long.word 0x24 0.--15. 1. "LN,Line Number for Virtual Channel 0"
|
|
wgroup.long 0x5C++0x7
|
|
line.long 0x0 "GSPIER,GSP Interrupt Enable Register"
|
|
hexmask.long.byte 0x0 4.--7. 1. "GSPERR,Generic Short Packet Error Interrupt Enable"
|
|
hexmask.long.byte 0x0 0.--3. 1. "GSPRDY,Generic Short Packet Ready Interrupt Enable"
|
|
line.long 0x4 "GSPIDR,GSP Interrupt Disable Register"
|
|
hexmask.long.byte 0x4 4.--7. 1. "GSPERR,Generic Short Packet Error Interrupt Disable"
|
|
hexmask.long.byte 0x4 0.--3. 1. "GSPRDY,Generic Short Packet Ready Interrupt Disable"
|
|
rgroup.long 0x64++0x17
|
|
line.long 0x0 "GSPIMR,GSP Interrupt Mask Register"
|
|
hexmask.long.byte 0x0 4.--7. 1. "GSPERR,Generic Short Packet Error Interrupt Mask bit"
|
|
hexmask.long.byte 0x0 0.--3. 1. "GSPRDY,Generic Short Packet Ready Interrupt Mask bit"
|
|
line.long 0x4 "GSPISR,GSP Interrupt Status Register"
|
|
hexmask.long.byte 0x4 4.--7. 1. "GSPERR,Generic Short Packet Error Interrupt Status Bit"
|
|
hexmask.long.byte 0x4 0.--3. 1. "GSPRDY,Generic Short Packet Ready Interrupt Status Bit"
|
|
line.long 0x8 "GSPS0R,GSP Status 0 Register"
|
|
hexmask.long.byte 0x8 16.--21. 1. "TYPE,Generic Short Packet Type Value for Virtual Channel 0"
|
|
hexmask.long.word 0x8 0.--15. 1. "VALUE,Generic Short Packet 16-bit Data Value for Virtual Channel 0"
|
|
line.long 0xC "GSPS1R,GSP Status 1 Register"
|
|
hexmask.long.byte 0xC 16.--21. 1. "TYPE,Generic Short Packet Type Value for Virtual Channel 0"
|
|
hexmask.long.word 0xC 0.--15. 1. "VALUE,Generic Short Packet 16-bit Data Value for Virtual Channel 0"
|
|
line.long 0x10 "GSPS2R,GSP Status 2 Register"
|
|
hexmask.long.byte 0x10 16.--21. 1. "TYPE,Generic Short Packet Type Value for Virtual Channel 0"
|
|
hexmask.long.word 0x10 0.--15. 1. "VALUE,Generic Short Packet 16-bit Data Value for Virtual Channel 0"
|
|
line.long 0x14 "GSPS3R,GSP Status 3 Register"
|
|
hexmask.long.byte 0x14 16.--21. 1. "TYPE,Generic Short Packet Type Value for Virtual Channel 0"
|
|
hexmask.long.word 0x14 0.--15. 1. "VALUE,Generic Short Packet 16-bit Data Value for Virtual Channel 0"
|
|
wgroup.long 0x7C++0x7
|
|
line.long 0x0 "GLPIER,GLP Interrupt Enable Register"
|
|
hexmask.long.byte 0x0 12.--15. 1. "RE,"
|
|
hexmask.long.byte 0x0 8.--11. 1. "EB,Embedded 8-bit Non-Image Data Interrupt Enable Bit"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "BL,Blanking Data Interrupt Enable Bit"
|
|
hexmask.long.byte 0x0 0.--3. 1. "NU,Null Interrupt Enable Bit"
|
|
line.long 0x4 "GLPIDR,GLP Interrupt Disable Register"
|
|
hexmask.long.byte 0x4 12.--15. 1. "RE,"
|
|
hexmask.long.byte 0x4 8.--11. 1. "EB,Embedded 8-bit Non-Image Data Interrupt Disable Bit"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "BL,Blanking Data Interrupt Disable Bit"
|
|
hexmask.long.byte 0x4 0.--3. 1. "NU,Null Interrupt Disable Bit"
|
|
rgroup.long 0x84++0x7
|
|
line.long 0x0 "GLPIMR,GLP Interrupt Mask Register"
|
|
hexmask.long.byte 0x0 12.--15. 1. "RE,"
|
|
hexmask.long.byte 0x0 8.--11. 1. "EB,Embedded 8-bit Non-Image Data Packet Interrupt Mask Bit"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "BL,Blanking Data Packet Interrupt Mask Bit"
|
|
hexmask.long.byte 0x0 0.--3. 1. "NU,Null Packet Interrupt Mask Bit"
|
|
line.long 0x4 "GLPISR,GLP Interrupt Status Register"
|
|
hexmask.long.byte 0x4 12.--15. 1. "RE,"
|
|
hexmask.long.byte 0x4 8.--11. 1. "EB,Embedded 8-bit data Generic Long Packet Ready Interrupt Status Bit"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "BL,Blanking Data Generic Long Packet Ready Interrupt Status Bit"
|
|
hexmask.long.byte 0x4 0.--3. 1. "NU,Null Generic Long Packet Ready Interrupt Status Bit"
|
|
wgroup.long 0x8C++0xB
|
|
line.long 0x0 "IDSCR,IDS Control Register"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0: No effect.,1: Performs an IDS software reset of the table."
|
|
line.long 0x4 "IDSIER,IDS Interrupt Enable Register"
|
|
bitfld.long 0x4 4. "OVF,Image Data Snoop Overflow Interrupt Enable" "0: No effect.,1: Enables the Image Data Snoop Overflow interrupt."
|
|
hexmask.long.byte 0x4 0.--3. 1. "IDS,Image Data Snoop Interrupt Enable"
|
|
line.long 0x8 "IDSIDR,IDS Interrupt Disable Register"
|
|
bitfld.long 0x8 4. "OVF,Image Data Snoop Overflow Interrupt Disable" "0: No effect.,1: Disables the Image Data Snoop Overflow interrupt."
|
|
hexmask.long.byte 0x8 0.--3. 1. "IDS,Image Data Snoop Interrupt Disable"
|
|
rgroup.long 0x98++0x7
|
|
line.long 0x0 "IDSIMR,IDS Interrupt Mask Register"
|
|
bitfld.long 0x0 4. "OVF,Image Data Snoop Overflow Interrupt Mask" "0: No effect.,1: Indicates that the Image Data Snoop Overflow.."
|
|
hexmask.long.byte 0x0 0.--3. 1. "IDS,Image Data Snoop Interrupt Mask Bit"
|
|
line.long 0x4 "IDSISR,IDS Interrupt Status Register"
|
|
bitfld.long 0x4 4. "OVF,Image Data Snoop Overflow Interrupt Status" "0: No effect.,1: Indicates that the IDS controller captured more.."
|
|
hexmask.long.byte 0x4 0.--3. 1. "IDS,Image Data Snoop Interrupt Status Bit"
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0xE14040A0 ad:0xE14040A8 ad:0xE14040B0 ad:0xE14040B8)
|
|
tree "CSI2DC_IDSEW[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "IDSEW0R,IDS Entry Word 0 Register"
|
|
bitfld.long 0x0 6.--7. "VC,Virtual Channel Identifier" "0: Virtual Channel 0,1: Virtual Channel 1,2: Virtual Channel 2,3: Virtual Channel 3"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DT,Data Type"
|
|
line.long 0x4 "IDSEW1R,IDS Entry Word 1 Register"
|
|
hexmask.long.word 0x4 16.--31. 1. "RC,Row Count for Image Data Packet Captured"
|
|
hexmask.long.word 0x4 0.--15. 1. "WC,Word Count for Image Data Packet Captured"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0xE1404000
|
|
wgroup.long 0xC0++0x3
|
|
line.long 0x0 "PUR,Pipe Update Register"
|
|
bitfld.long 0x0 1. "DP,Data Pipe Attributes Update" "0: No effect.,1: Transfers current configuration to Data Pipe.."
|
|
bitfld.long 0x0 0. "VP,Video Pipe Attributes Update" "0: No effect.,1: Transfers current configuration to Video Pipe.."
|
|
rgroup.long 0xC4++0x3
|
|
line.long 0x0 "PUSR,Pipe Update Status Register"
|
|
bitfld.long 0x0 31. "SIP,Synchronization In Progress" "0: No synchronization pending.,1: Synchronization across clock domain boundary is.."
|
|
bitfld.long 0x0 1. "DP,Data Pipe Update" "0: No data pipe in progress.,1: Data pipe configuration is in progress. This bit.."
|
|
newline
|
|
bitfld.long 0x0 0. "VP,Video Pipe Update" "0: No video pipe in progress.,1: Video pipe configuration is in progress. This.."
|
|
wgroup.long 0xC8++0x7
|
|
line.long 0x0 "DPIER,Data Pipe Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "LTE,Longer Than Expected Packet Received Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 6. "STE,Shorter Than Expected Packet Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "DATOVF,Data Pipe Overflow Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "RXOVF1,Bank 1 Packet Overflow Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXOVF0,Bank 0 Packet Overflow Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "RXRDY1,Bank 1 Packet Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY0,Bank 0 Packet Received Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "CAPTURE,Data Pipe Capture Done Interrupt Enable" "0,1"
|
|
line.long 0x4 "DPIDR,Data Pipe Interrupt Disable Register"
|
|
bitfld.long 0x4 7. "LTE,Longer Than Expected Packet Received Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 6. "STE,Shorter Than Expected Packet Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "DATOVF,Data Pipe Overflow Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 4. "RXOVF1,Bank 1 Packet Overflow Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXOVF0,Bank 0 Packet Overflow Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 2. "RXRDY1,Bank 1 Packet Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RXRDY0,Bank 0 Packet Received Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "CAPTURE,Data Pipe Capture Done Interrupt Disable" "0,1"
|
|
rgroup.long 0xD0++0x7
|
|
line.long 0x0 "DPIMR,Data Pipe Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "LTE,Longer Than Expected Packet Received Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 6. "STE,Shorter Than Expected Packet Received Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "DATOVF,Data Pipe Overflow Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 4. "RXOVF1,Bank 1 Packet Overflow Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXOVF0,Bank 0 Packet Overflow Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "RXRDY1,Bank 1 Packet Received Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY0,Bank 0 Packet Received Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "CAPTURE,Data Pipe Capture Done Interrupt Mask" "0,1"
|
|
line.long 0x4 "DPISR,Data Pipe Interrupt Status Register"
|
|
bitfld.long 0x4 7. "LTE,Packet Longer Than Expected" "0: No LTE packet detected.,1: A packet has been received but the actual length.."
|
|
bitfld.long 0x4 6. "STE,Packet Shorter Than Expected" "0: No STE packet detected.,1: A packet has been received but the actual length.."
|
|
newline
|
|
bitfld.long 0x4 5. "DATOVF,Data Overflow" "0: No overflow detected.,1: Data overflow in the clock domain crossing FIFO."
|
|
bitfld.long 0x4 4. "RXOVF1,Bank 1 Overflow" "0: No overflow detected.,1: An overflow occurred in bank 1."
|
|
newline
|
|
bitfld.long 0x4 3. "RXOVF0,Bank 0 Overflow" "0: No overflow detected.,1: An overflow occurred in bank 0."
|
|
bitfld.long 0x4 2. "RXRDY1,Bank 1 Packet Received" "0: No packet received in bank 1 since the last..,1: A new packet has been captured in the data pipe."
|
|
newline
|
|
bitfld.long 0x4 1. "RXRDY0,Bank 0 Packet Received" "0: No packet received in bank 0 since the last..,1: A new packet has been captured in the data pipe."
|
|
bitfld.long 0x4 0. "CAPTURE,Captured Frame" "0: No frame captured on the data pipe interface..,1: A new frame has been captured in the data pipe."
|
|
wgroup.long 0xD8++0x3
|
|
line.long 0x0 "DPICR,Data Pipe Interrupt Clear Register"
|
|
bitfld.long 0x0 7. "LTE,Packet Longer Than Expected Interrupt Clear Register" "0: No effect.,1: Clears the LTE interrupt."
|
|
bitfld.long 0x0 6. "STE,Packet Shorter Than Expected Interrupt Clear Register" "0: No effect.,1: Clears the STE interrupt."
|
|
newline
|
|
bitfld.long 0x0 5. "DATOVF,Data Overflow Interrupt Clear Register" "0: No effect.,1: Clears the Data Overflow interrupt."
|
|
bitfld.long 0x0 4. "RXOVF1,Bank 1 Packet Overflow Interrupt Clear Register" "0: No effect.,1: Clears the Bank 1 Packet Overflow interrupt."
|
|
newline
|
|
bitfld.long 0x0 3. "RXOVF0,Bank 0 Packet Overflow Interrupt Clear Register" "0: No effect.,1: Clears the Bank 0 Packet Overflow interrupt."
|
|
bitfld.long 0x0 2. "RXRDY1,Bank 1 Packet Received Interrupt Clear Register" "0: No effect.,1: Clears the Bank 1 Packet Received interrupt."
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY0,Bank 0 Packet Received Interrupt Clear Register" "0: No effect.,1: Clears the Bank 0 Packet Received interrupt."
|
|
bitfld.long 0x0 0. "CAPTURE,Captured Frame Interrupt Clear Register" "0: No effect.,1: Clears the Captured Frame interrupt."
|
|
group.long 0xDC++0xB
|
|
line.long 0x0 "DPER,Data Pipe Enable Register"
|
|
bitfld.long 0x0 0. "ENABLE,Data Pipe Enable" "0: Data pipe disabled.,1: Data pipe enabled."
|
|
line.long 0x4 "DPCFGR,Data Pipe Configuration Register"
|
|
hexmask.long.word 0x4 16.--26. 1. "BO,Bank Offset"
|
|
bitfld.long 0x4 6.--7. "VC,Virtual Channel for Data Pipe" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--5. 1. "DT,Data Type for Data Pipe"
|
|
line.long 0x8 "DPDCR,Data Pipe DMA Configuration Register"
|
|
hexmask.long.word 0x8 16.--31. 1. "TC,DMA Transfer Count"
|
|
bitfld.long 0x8 4.--6. "CSIZE,DMA Chunk Size" "0: 1 data transferred,1: 2 data transferred,2: 4 data transferred,3: 8 data transferred,4: 16 data transferred,?,?,?"
|
|
newline
|
|
bitfld.long 0x8 0. "DMA,DMA Mode Enabled" "0: DMA slave interface is disabled.,1: DMA slave interface is enabled."
|
|
wgroup.long 0xE8++0x7
|
|
line.long 0x0 "VPIER,Video Pipe Interrupt Enable Register"
|
|
bitfld.long 0x0 5. "PKTOVF,Packet Overflow For Video Pipe Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "LTE,Packet Longer Than Expected Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STE,Packet Shorter Than Expected Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "CTLOVF,Control Buffer Overflow Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RATEOVF,Rate Buffer Overflow Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "CAPTURE,Video Pipeline Capture Interrupt Enable" "0,1"
|
|
line.long 0x4 "VPIDR,Video Pipe Interrupt Disable Register"
|
|
bitfld.long 0x4 5. "PKTOVF,Packet Overflow For Video Pipe Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 4. "LTE,Packet Longer Than Expected Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "STE,Packet Shorter Than Expected Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 2. "CTLOVF,Control Buffer Overflow Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RATEOVF,Rate Buffer Overflow Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "CAPTURE,Video Pipeline Capture Interrupt Disable" "0,1"
|
|
rgroup.long 0xF0++0x7
|
|
line.long 0x0 "VPIMR,Video Pipe Interrupt Mask Register"
|
|
bitfld.long 0x0 5. "PKTOVF,Packet Overflow For Video Pipe Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 4. "LTE,Packet Longer Than Expected Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STE,Packet Shorter Than Expected Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "CTLOVF,Control Buffer Overflow Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RATEOVF,Rate Buffer Overflow Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "CAPTURE,Video Pipeline Capture Interrupt Mask" "0,1"
|
|
line.long 0x4 "VPISR,Video Pipe Interrupt Status Register"
|
|
bitfld.long 0x4 5. "PKTOVF,Packet Overflow For Video Pipe Interrupt Mask" "0: Packet Overflow For Video Pipe interrupt is..,1: Packet Overflow For Video Pipe interrupt is.."
|
|
bitfld.long 0x4 4. "LTE,Packet Longer Than Expected Interrupt Mask" "0: Packet Longer Than Expected interrupt is masked.,1: Packet Longer Than Expected interrupt is.."
|
|
newline
|
|
bitfld.long 0x4 3. "STE,Packet Shorter Than Expected Interrupt Mask" "0: No packet shorter than expected since the last..,1: The Packet Shorter Than Expected interrupt is.."
|
|
bitfld.long 0x4 2. "CTLOVF,Control Buffer Overflow Interrupt Mask" "0: No Control Buffer Overflow since the last read..,1: A Control Buffer Overflow has been detected."
|
|
newline
|
|
bitfld.long 0x4 1. "RATEOVF,Rate Buffer Overflow Interrupt Mask" "0: No Rate Buffer Overflow since the last read of..,1: A Rate Buffer Overflow has been detected."
|
|
bitfld.long 0x4 0. "CAPTURE,Video Pipeline Capture Status" "0: No frame capture since the last read of the..,1: A frame has been captured in the video pipeline."
|
|
group.long 0xF8++0x7
|
|
line.long 0x0 "VPER,Video Pipe Enable Register"
|
|
bitfld.long 0x0 0. "ENABLE,Video Pipe Enable" "0: Video pipe disabled.,1: Video pipe enabled."
|
|
line.long 0x4 "VPCFGR,Video Pipe Configuration Register"
|
|
bitfld.long 0x4 15. "RGB36MAP,RGB Mapping" "0: RGB data is packed and written to the output bus.,1: The RGB pixel is mapped onto the 36-bit bus.."
|
|
bitfld.long 0x4 14. "PA,ISC Post Adjustment" "0: Post adjustment is disabled. Video pipe output..,1: Post adjustment is enabled. Video pipe output.."
|
|
newline
|
|
bitfld.long 0x4 13. "RMS,Recommended Memory Storage" "0: CSI2DC outputs 1 pixel per component per clock..,1: CSI2DC generates a byte stream compliant with.."
|
|
bitfld.long 0x4 12. "DP2,Decoder Predictor 2 Selection" "0: Predictor 1 is selected.,1: Predictor 2 is selected."
|
|
newline
|
|
bitfld.long 0x4 9.--11. "DM,Decoder Mode" "0: Use the 8-bit to 12-bit decoding operation,1: Use the 7-bit to 12-bit decoding operation,2: Use the 6-bit to 12-bit decoding operation,3: Use the 8-bit to 10-bit decoding operation,4: Use the 7-bit to 10-bit decoding operation,5: Use the 6-bit to 10-bit decoding operation,?,?"
|
|
bitfld.long 0x4 8. "DE,Decompression Enable" "0: Decompression disabled.,1: Decompression enabled."
|
|
newline
|
|
bitfld.long 0x4 6.--7. "VC,Virtual Channel Identifier" "0,1,2,3"
|
|
hexmask.long.byte 0x4 0.--5. 1. "DT,Data Type"
|
|
rgroup.long 0x100++0x7
|
|
line.long 0x0 "VPCOLR,Video Pipe Column Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "COL,Column Number"
|
|
line.long 0x4 "VPROWR,Video Pipe Row Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "ROW,Row Number"
|
|
group.long 0x108++0x3
|
|
line.long 0x0 "VPDTRR,Video Pipe Data Type Remap Register"
|
|
bitfld.long 0x0 6. "DTRE,Data Type Remap Enable" "0: Data type remap is disabled.,1: Data type remap is enabled."
|
|
hexmask.long.byte 0x0 0.--5. 1. "ADT,Alternate Data Type"
|
|
tree.end
|
|
tree "DDR3PHY (DDR SDRAM PHY Utility Block Lite)"
|
|
base ad:0xE3804000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "RIDR,Revision Identification Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "UDRID,User-Defined Revision ID: General purpose revision identification set by the user."
|
|
hexmask.long.byte 0x0 20.--23. 1. "PHYMJR,PHY Major Revision: Indicates major revision of the PHY such addition of the features that make the new version not compatible with previous versions."
|
|
hexmask.long.byte 0x0 16.--19. 1. "PHYMDR,PHY Moderate Revision: Indicates moderate revision of the PHY such as addition of new features. Normally the new version is still compatible with previous versions."
|
|
hexmask.long.byte 0x0 12.--15. 1. "PHYMNR,PHY Minor Revision: Indicates minor update of the PHY such as bug fixes. Normally no new features are included."
|
|
hexmask.long.byte 0x0 8.--11. 1. "PUBMJR,PUB Major Revision: Indicates major revision of the PUB such addition of the features that make the new version not compatible with previous versions."
|
|
hexmask.long.byte 0x0 4.--7. 1. "PUBMDR,PUB Moderate Revision: Indicates moderate revision of the PUB such as addition of new features. Normally the new version is still compatible with previous versions."
|
|
hexmask.long.byte 0x0 0.--3. 1. "PUBMNR,PUB Minor Revision: Indicates minor update of the PUB such as bug fixes. Normally no new features are included."
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "PIR,PHY Initialization Register"
|
|
bitfld.long 0x0 31. "INITBYP,Initialization Bypass: Bypasses or stops if set all initialization routines currently running including PHY initialization DRAM initialization and PHY training." "0,1"
|
|
bitfld.long 0x0 30. "ZCALBYP,Impedance Calibration Bypass: Bypasses or stops if set impedance calibration of all ZQ control blocks that automatically triggers after reset. Impedance calibration may be triggered manually using INIT and ZCAL bits of the PIR register. This.." "0,1"
|
|
bitfld.long 0x0 29. "LOCKBYP,DLL Lock Bypass: Bypasses or stops if set the waiting of DLLs to lock. DLL lock wait is automatically triggers after reset. DLL lock wait may be triggered manually using INIT and DLLLOCK bits of the PIR register. This bit is self-clearing." "0,1"
|
|
bitfld.long 0x0 28. "CLRSR,Clear Status Registers" "0,1"
|
|
bitfld.long 0x0 18. "CTLDINIT,Controller DRAM Initialization: Indicates if set that DRAM initialization will be performed by the controller. Otherwise if not set it indicates that DRAM initialization will be performed using the built-in initialization sequence or using.." "0,1"
|
|
bitfld.long 0x0 17. "DLLBYP,DLL Bypass: A setting of 1 on this bit will put all PHY DLLs in bypass mode. A bypassed DLL is also powered down (disabled)." "0,1"
|
|
bitfld.long 0x0 16. "ICPC,Initialization Complete Pin Configuration: Specifies how the DFI 2.1 initialization complete output pin should be used to indicate the status of initialization." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RVTRN,Read DQS gate training (QSTRN) and RV training (RVTRN) should normally be run together. It is expected RVTRN is normally be set whenever PIR.QSTRN is set." "0,1"
|
|
bitfld.long 0x0 7. "QSTRN,Read DQS Training: Executes a PUBL training routine to determine the optimum position of the read data DQS strobe for maximum system timing margins." "0,1"
|
|
bitfld.long 0x0 6. "DRAMINIT,DRAM Initialization: Executes the DRAM initialization sequence." "0,1"
|
|
bitfld.long 0x0 5. "DRAMRST,DRAM Reset (DDR3 Only): Issues a reset to the DRAM (by driving the DRAM reset pin low) and wait 200us. This can be triggered in isolation or with the full DRAM initialization (DRAMINIT). For the latter case the reset is issued and 200us is.." "0,1"
|
|
bitfld.long 0x0 4. "ITMSRST,Interface Timing Module Soft Reset: Soft resets the interface timing modules for the data and data strobes i.e. it asserts the ITM soft reset (srstb) signal." "0,1"
|
|
bitfld.long 0x0 3. "ZCAL,Impedance Calibrate: Performs PHY impedance calibration." "0,1"
|
|
bitfld.long 0x0 2. "DLLLOCK,DLL Lock: Waits for the PHY DLLs to lock." "0,1"
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bitfld.long 0x0 1. "DLLSRST,DLL Soft Rest: Soft resets all PHY DLLs by driving the DLL soft reset pin." "0,1"
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bitfld.long 0x0 0. "INIT,Initialization Trigger: A write of '1' to this bit triggers the DDR system initialization including PHY initialization DRAM initialization and PHY training. The exact initialization steps to be executes are specified in bits 1 to 6 of this.." "0,1"
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line.long 0x4 "PGCR,PHY General Configuration Register"
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bitfld.long 0x4 31. "LBMODE,Loopback Mode: Indicates if set that the PHY/PUB is in loopback mode" "0,1"
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bitfld.long 0x4 30. "LBGDQS,Loopback DQS Gating: Selects the DQS gating mode that should be used when the PHY is in loopback mode including BIST loopback mode." "0,1"
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bitfld.long 0x4 29. "LBDQSS,Loopback DQS Shift: Selects how the read DQS is shifted during loopback to ensure that the read DQS is centered into the read data eye." "0,1"
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hexmask.long.byte 0x4 25.--28. 1. "RFSHDT,Refresh During Training: A non-zero value specifies that a burst of refreshes equal to the number specified in this field should be sent to the SDRAM after training each rank except the last rank."
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bitfld.long 0x4 24. "PDDISDX,Power Down Disabled Byte: Indicates if set that the DLL and I/Os of a disabled byte should be powered down." "0,1"
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bitfld.long 0x4 22.--23. "ZCKSEL,Impedance Clock Divider Select: Impedance Clock Divider Select: Selects the divide ratio for the clock used by the impedance control logic. The source clock for the divider is the configuration port clock signal (cfg_clk or pclk) depending on.." "0,1,2,3"
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hexmask.long.byte 0x4 18.--21. 1. "RANKEN,Rank Enable: Specifies the ranks that are enabled for data-training. Bit 0 controls rank 0 bit 1 controls rank 1 bit 2 controls rank 2 and bit 3 controls rank 3. Setting the bit to '1' enables the rank and setting it to '0' disables the rank."
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bitfld.long 0x4 16.--17. "IODDRM,I/O DDR Mode (D3F I/O Only): Selects the DDR mode for the I/Os." "0,1,2,3"
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bitfld.long 0x4 15. "IOLB,I/O Loop-Back Select: Selects where inside the I/O the loop-back of signals happens. Not applicable to D3A I/Os." "0,1"
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bitfld.long 0x4 14. "CKINV,CK Invert: Specifies if set that CK/CK# should be inverted. Otherwise CK/CK# toggles with normal polarity." "0,1"
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bitfld.long 0x4 12.--13. "CKDV,CK Disable Value: Specifies the static value that should be driven on CK/CK# pair(s) when the pair(s) is disabled. CKDV[0] specifies the value for CK and CKDV[1] specifies the value for CK#." "0,1,2,3"
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bitfld.long 0x4 9.--11. "CKEN,CK Enable: Controls whether the CK going to the SDRAM is enabled (toggling) or disabled (static value defined by CKDV). One bit for each of the three CK pairs." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x4 5.--8. 1. "DTOSEL,Digital Test Output Select: Selects the PHY digital test output that should be driven onto PHY digital test output (phy_dto) pin."
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bitfld.long 0x4 3.--4. "DFTLMT,DQS Drift Limit: Specifies the expected limit of drift on read data strobes. A drift of this value or greater is reported as a drift error through the host port error flag." "0,1,2,3"
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bitfld.long 0x4 2. "DFTCMP,DQS Drift Compensation: Enables or disables DQS drift compensation." "0,1"
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bitfld.long 0x4 1. "DQSCFG,DQS Gating Configuration: Selects one of the two DQS gating schemes." "0,1"
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bitfld.long 0x4 0. "ITMDMD,ITM DDR Mode: Selects whether ITMS uses DQS and DQS# or it only uses DQS." "0,1"
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rgroup.long 0xC++0x3
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line.long 0x0 "PGSR,PHY General Status Register"
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bitfld.long 0x0 31. "TQ,Temperature Output (LPDDR Only): Connected to the DRAM TQ pin which is defined to go high when the LPDDR device temperature equals to or exceeds 85oC otherwise it is low." "0,1"
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bitfld.long 0x0 9. "RVEIRR,Read Valid Training Intermittent Error: If set indicates that there was an intermittent error during read valid training such as a pass was followed by a fail then followed by another pass." "0,1"
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bitfld.long 0x0 8. "RVERR,Read Valid Training Error: If set indicates that a valid read valid placement could not be found during read valid training." "0,1"
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bitfld.long 0x0 7. "DFTERR,DQS Drift Error: If set indicates that at least one of the read data strobes has drifted by more than or equal to the drift limit set in the PHY General Configuration Register (PGCR)." "0,1"
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bitfld.long 0x0 6. "DTIERR,DQS Gate Training Intermittent Error: If set indicates that there was an intermittent error during DQS gate training such as a pass was followed by a fail then followed by another pass." "0,1"
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bitfld.long 0x0 5. "DTERR,DQS GateTraining Error: If set indicates that a valid DQS gating window could not be found during DQS gate training." "0,1"
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bitfld.long 0x0 4. "DTDONE,Data Training Done: Indicates if set that the PHY has finished doing data training." "0,1"
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bitfld.long 0x0 3. "DIDONE,DRAM Initialization Done: Indicates if set that DRAM initialization has completed." "0,1"
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bitfld.long 0x0 2. "ZCDONE,Impedance Calibration Done: Indicates if set that impedance calibration has completed." "0,1"
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bitfld.long 0x0 1. "DLDONE,DLL Lock Done: Indicates if set that DLL locking has completed." "0,1"
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bitfld.long 0x0 0. "IDONE,Initialization Done: Indicates if set that the DDR system initialization has completed. This bit is set after all the selected initialization routines in PIR register have completed." "0,1"
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group.long 0x10++0x4F
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line.long 0x0 "DLLGCR,DLL General Control Register"
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bitfld.long 0x0 30.--31. "DLLRSVD2,DLL Reserved Control: This bit is connected to the DLL control bus and is reserved for future use." "0,1,2,3"
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bitfld.long 0x0 29. "LOCKDET,Master lock detector enable." "0,1"
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bitfld.long 0x0 27.--28. "FDTRM_SL,Slave Bypass Fixed Delay Trim" "0,1,2,3"
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bitfld.long 0x0 24.--26. "SBIAS_5_3,Slave Bias Trim: Used to trim the bias for the slave DLL." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 23. "BPS200,Bypass Mode Frequency Range" "0,1"
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bitfld.long 0x0 20.--22. "SBIAS_2_0,Slave Bias Trim: Used to trim the bias for the slave DLL." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x0 12.--19. 1. "MBIAS,Master Bias Trim: Used to trim the bias for the master DLL."
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bitfld.long 0x0 11. "TESTSW,Test Switch: Selects the test signals of either the master DLL set to 0 or the slave DLL set to 1." "0,1"
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bitfld.long 0x0 9.--10. "ATC,Analog Test Control: Selects the analog signal to be output on the DLL analog test output (test_out_a) when TESTEN is high (Output is Vss when TESTEN is low). The test output either comes from the master DLL or the slave DLL depending on the setting.." "0,1,2,3"
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bitfld.long 0x0 6.--8. "DTC,Digital Test Control: Selects the digital signal to be output on the DLL digital test output (test_out_d[1]) when TESTEN is high (Output is '0' when TESTEN is low)." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 5. "TESTEN,Test Enable: Enables digital and analog test outputs selected by DTC and ATC respectively." "0,1"
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bitfld.long 0x0 2.--4. "IPUMP,Charge Pump Current Trim: Used to trim charge pump current." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 0.--1. "DRES,Delta Resistor Trim: Used to trim reference current versus resistor value variation." "0,1,2,3"
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line.long 0x4 "ACDLLCR,AC DLL Control Register"
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bitfld.long 0x4 31. "DLLDIS,DLL Disable: A disabled DLL is bypassed. Default ('0') is DLL enabled." "0,1"
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bitfld.long 0x4 30. "DLLSRST,DLL Soft Rest: Soft resets the AC DLL by driving the DLL soft reset pin." "0,1"
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bitfld.long 0x4 18. "ATESTEN,Analog Test Enable: Enables the analog test signal to be output on the DLL analog test output (test_out_a). The DLL analog test output is tri-stated when this bit is '0'." "0,1"
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bitfld.long 0x4 9.--11. "MFWDLY,Master Feed-Forward Delay Trim: Used to trim the delay in the master DLL feedforward path." "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 6.--8. "MFBDLY,Master Feed-Back Delay Trim: Used to trim the delay in the master DLL feedback path." "0,1,2,3,4,5,6,7"
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line.long 0x8 "PTR0,PHY Timing Register 0"
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hexmask.long.byte 0x8 18.--21. 1. "TITMSRST,ITM Soft Reset Time: Number of configuration clock cycles that the ITM soft reset pin must remain asserted when the soft reset is applied to the ITMs. This must correspond to a value that is equal to or more than 8 controller clock cycles."
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hexmask.long.word 0x8 6.--17. 1. "TDLLLOCK,DLL Lock Time: Number of configuration clock cycles for the DLL to stabilize and lock i.e. number of clock cycles from when the DLL reset pin is de-asserted to when the DLL has locked and is ready for use. Refer to the PHY databook for the DLL.."
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hexmask.long.byte 0x8 0.--5. 1. "TDLLSRST,DLL Soft Reset Time: Number of configuration clock cycles that the DLL soft reset pin must remain asserted when the soft reset is triggered through the PHY"
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line.long 0xC "PTR1,PHY Timing Register 1"
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hexmask.long.byte 0xC 19.--26. 1. "TDINIT1,DRAM Initialization Time 1."
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hexmask.long.tbyte 0xC 0.--18. 1. "TDINIT0,DRAM Initialization Time 0."
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line.long 0x10 "PTR2,PHY Timing Register 2"
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hexmask.long.word 0x10 17.--26. 1. "TDINIT3,DRAM Initialization Time 3."
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hexmask.long.tbyte 0x10 0.--16. 1. "TDINIT2,DRAM Initialization Time 2."
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line.long 0x14 "ACIOCR,AC I/O Configuration Register"
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bitfld.long 0x14 30.--31. "ACSR,Address/Command Slew Rate (D3F I/O Only): Selects slew rate of the I/O for all address and command pins as well as the optional DIMM PAR_IN pin and LPDDR TPD pin." "0,1,2,3"
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bitfld.long 0x14 29. "RSTIOM,SDRAM Reset I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for SDRAM Reset." "0,1"
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bitfld.long 0x14 28. "RSTPDR,SDRAM Reset Power Down Receiver: Powers down when set the input receiver on the I/O for SDRAM RST# pin." "0,1"
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bitfld.long 0x14 27. "RSTPDD,SDRAM Reset Power Down Driver: Powers down when set the output driver on the I/O for SDRAM RST# pin." "0,1"
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bitfld.long 0x14 26. "RSTODT,SDRAM Reset On-Die Termination: Enables when set the on-die termination on the I/O for SDRAM RST# pin." "0,1"
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hexmask.long.byte 0x14 22.--25. 1. "RANKPDR,Rank Power Down Receiver: Powers down when set the input receiver on the I/O"
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hexmask.long.byte 0x14 18.--21. 1. "CSPDD,CS# Power Down Driver: Powers down when set the output driver on the I/O for CS#[3:0] pins. PDD[0] controls the power down for CS#[0] PDD[1] controls the power down for CS#[1] and so on. CKE and ODT driver power down is controlled by DSGCR.."
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hexmask.long.byte 0x14 14.--17. 1. "RANKODT,Rank On-Die Termination: Enables when set the on-die termination on the I/O for CKE[3:0] ODT[3:0] and CS#[3:0] pins. RANKODT[0] controls the on-die termination for CKE[0] ODT[0] and CS#[0] RANKODT[1] controls the on-die termination for.."
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bitfld.long 0x14 11.--13. "CKPDR,CK Power Down Receiver: Powers down when set the input receiver on the I/O for CK[0] CK[1] and CK[2] pins respectively." "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 8.--10. "CKPDD,CK Power Down Driver: Powers down when set the output driver on the I/O for CK[0] CK[1] and CK[2] pins respectively." "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 5.--7. "CKODT,CK On-Die Termination: Enables when set the on-die termination on the I/O for CK[0] CK[1] and CK[2] pins respectively." "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 4. "ACPDR,AC Power Down Receiver: Powers down when set the input receiver on the I/O for RAS# CAS# WE# BA[2:0] and A[15:0] pins as well as the optional DIMM PAR_IN pin and LPDDR TPD pin." "0,1"
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bitfld.long 0x14 3. "ACPDD,AC Power Down Driver: Powers down when set the output driver on the I/O for RAS# CAS# WE# BA[2:0] and A[15:0] pins as well as the optional DIMM PAR_IN pin." "0,1"
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bitfld.long 0x14 2. "ACODT,Address/Command On-Die Termination: Enables when set the on-die termination on the I/O for RAS# CAS# WE# BA[2:0] and A[15:0] pins as well as the optional DIMM PAR_IN pin and LPDDR TPD pin." "0,1"
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bitfld.long 0x14 1. "ACOE,Address/Command Output Enable: Enables when set the output driver on the I/O for all address and command pins as well as the optional DIMM PAR_IN pin and LPDDR TPD pin." "0,1"
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bitfld.long 0x14 0. "ACIOM,Address/Command I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for all address and command pins as well as the optional DIMM PAR_IN pin and LPDDR TPD pin." "0,1"
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line.long 0x18 "DXCCR,DATX8 I/O Configuration Register"
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bitfld.long 0x18 16. "AWDT,Active Window Data Train: Indicates if set that data training (DQS gate training and read valid training) should be performed with active DQS gate window. This is just for debug purposes. The default is to perform training with passive windowing." "0,1"
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bitfld.long 0x18 15. "RVSEL,ITMD Read Valid Select: Selects the scheme used for ITMD read valid." "0,1"
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bitfld.long 0x18 14. "DQSNRST,DQS# Reset: Indicates if set that the ITMS of DQS# should always be put in reset such that its output enable is always '1' and its data output is always '0'. This is done by driving the oe_set_b and do_rst_b pins of this ITMS to '0' in order to.." "0,1"
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bitfld.long 0x18 12.--13. "DXSR,Data Slew Rate (D3F I/O Only): Selects slew rate of the I/O for DQ DM and DQS/DQS# pins of all DATX8 macros." "0,1,2,3"
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hexmask.long.byte 0x18 8.--11. 1. "DQSNRES,DQS# Resistor: Selects the on-die pull-up/pull-down resistor for DQS# pins. Same encoding as DQSRES."
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hexmask.long.byte 0x18 4.--7. 1. "DQSRES,DQS Resistor: Selects the on-die pull-down/pull-up resistor for DQS pins."
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bitfld.long 0x18 3. "DXPDR,Data Power Down Receiver: Powers down when set the input receiver on I/O for" "0,1"
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bitfld.long 0x18 2. "DXPDD,Data Power Down Driver: Powers down when set the output driver on I/O for DQ DM and DQS/DQS# pins of all DATX8 macros. This bit is ORed with the PDD configuration bit of the individual DATX8" "0,1"
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bitfld.long 0x18 1. "DXIOM,Data I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for DQ DM and DQS/DQS# pins of all DATX8 macros. This bit is ORed with the IOM configuration bit of the individual DATX8" "0,1"
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bitfld.long 0x18 0. "DXODT,Data On-Die Termination: Enables when set the on-die termination on the I/O for DQ DM and DQS/DQS# pins of all DATX8 macros. This bit is ORed with the ODT configuration bit of the individual DATX8" "0,1"
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line.long 0x1C "DSGCR,DFI Configuration Register"
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bitfld.long 0x1C 31. "CKEOE,SDRAM CKE Output Enable: Enables when set the output driver on the I/O for SDRAM CKE pins." "0,1"
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bitfld.long 0x1C 30. "RSTOE,SDRAM Reset Output Enable: Enables when set the output driver on the I/O for SDRAM RST# pin." "0,1"
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bitfld.long 0x1C 29. "ODTOE,SDRAM ODT Output Enable: Enables when set the output driver on the I/O for SDRAM ODT pins." "0,1"
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bitfld.long 0x1C 28. "CKOE,SDRAM CK Output Enable: Enables when set the output driver on the I/O for SDRAM CK/CK# pins." "0,1"
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bitfld.long 0x1C 27. "TPDOE,SDRAM TPD Output Enable (LPDDR Only): Enables when set the output driver on the I/O for SDRAM TPD pin." "0,1"
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bitfld.long 0x1C 26. "TPDPD,SDRAM TPD Power Down Driver (LPDDR Only): Powers down when set the output driver on the I/O for SDRAM TPD pin. Note that the power down of the receiver on the I/O for SDRAM TPD pin is controlled by ACIOCR[ACPDR] register bit." "0,1"
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bitfld.long 0x1C 25. "NL2OE,Non-LPDDR2/LPDDR3 Output Enable: Enables when set the output driver on the I/O for non-LPDDR2/LPDDR3 (ODT RAS# CAS# WE# and BA) pins. This may be used when a chip that is designed for both LPDDR2/LPDDR3 and other DDR modes is being used in.." "0,1"
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bitfld.long 0x1C 24. "NL2PD,Non-LPDDR2/LPDDR3 Power Down: Powers down when set the output driver and the input receiver on the I/O for non-LPDDR2/LPDDR3 (ODT RAS# CAS# WE# " "0,1"
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hexmask.long.byte 0x1C 20.--23. 1. "ODTPDD,ODT Power Down Driver: Powers down when set the output driver on the I/O for ODT[3:0] pins. ODTPDD[0] controls the power down for ODT[0] ODTPDD[1] controls the power down for ODT[1] and so on."
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hexmask.long.byte 0x1C 16.--19. 1. "CKEPDD,CKE Power Down Driver: Powers down when set the output driver on the I/O for CKE[3:0] pins. CKEPDD[0] controls the power down for CKE[0] CKEPDD[1] controls the power down for CKE[1] and so on."
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bitfld.long 0x1C 12. "FXDLAT,Fixed Latency: Specified whether all reads should be returned to the controller with a fixed read latency. Enabling fixed read latency increases the read latency." "0,1"
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bitfld.long 0x1C 11. "NOBUB,No Bubbles: Specified whether reads should be returned to the controller with no bubbles. Enabling no-bubble reads increases the read latency." "0,1"
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bitfld.long 0x1C 8.--10. "DQSGE,DQS Gate Early: Specifies the number of clock cycles for which the DQS gating must be enabled earlier than its normal position. Only applicable when using PDQSR I/O cell passive DQS gating and no drift compensation. This field is recommended to be.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C 5.--7. "DQSGX,DQS Gate Extension: Specifies the number of clock cycles for which the DQS gating must be extended beyond the normal burst length width. Only applicable when using PDQSR I/O cell passive DQS gating and no drift compensation. This field is.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C 4. "LPDLLPD,Low Power DLL Power Down: Specifies if set that the PHY should respond to the DFI low power opportunity request and power down the DLL of the PHY if the wakeup time request satisfies the DLL lock time." "0,1"
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bitfld.long 0x1C 3. "LPIOPD,Low Power I/O Power Down: Specifies if set that the PHY should respond to the DFI low power opportunity request and power down the I/Os of the PHY." "0,1"
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bitfld.long 0x1C 2. "ZUEN,Impedance Update Enable: Specifies if set that the PHY should perform impedance calibration (update) whenever there is a controller initiated DFI update request." "0,1"
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bitfld.long 0x1C 1. "BDISEN,Byte Disable Enable: Specifies if set that the PHY should respond to DFI byte disable request. Otherwise the byte disable from the DFI is ignored in which case bytes can only be disabled using the DXnGCR register." "0,1"
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bitfld.long 0x1C 0. "PUREN,PHY Update Request Enable: Specifies if set that the PHY should issue PHYinitiated DFI update request when there is DQS drift of more than 3/4 of a clock cycle within one continuous (back-to-back) read burst. By default the PHY issues PHYinitiated.." "0,1"
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line.long 0x20 "DCR,DRAM Configuration Register"
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bitfld.long 0x20 31. "TPD,Test Power Down (LPDDR Only): If set will place the DRAM in deep power down mode." "0,1"
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bitfld.long 0x20 30. "RDIMM,Registered DIMM: Indicates if set that a registered DIMM is used. In this case the PUB increases the SDRAM write and read latencies (WL/RL) by 1. This only applies to PUB internal SDRAM transactions. Transactions generated by the controller must.." "0,1"
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bitfld.long 0x20 29. "UDIMM,Un-buffered DIMM Address Mirroring: Indicates if set that there is address mirroring on the second rank of an un-buffered DIMM (the rank connected to CS#[1]). In this case the PUB re-scrambles the bank and address when sending mode register.." "0,1"
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bitfld.long 0x20 28. "DDR2T,DDR 2T Timing: Indicates if set that 2T timing should be used by PUB internally generated SDRAM transactions." "0,1"
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bitfld.long 0x20 27. "NOSRA,No Simultaneous Rank Access: Specifies if set that simultaneous rank access on the same clock cycle is not allowed. This means that multiple chip select signals should not be asserted at the same time. This may be required on some DIMM systems." "0,1"
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bitfld.long 0x20 8.--9. "DDRTYPE,DDR Type: Selects the DDR type for the specified LPDDR mode." "0,1,2,3"
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bitfld.long 0x20 7. "MPRDQ,Multi-Purpose Register (MPR) DQ (DDR3 Only): Specifies the value that is driven on non-primary DQ pins during MPR reads." "0,1"
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bitfld.long 0x20 4.--6. "PDQ,Primary DQ (DDR3 Only): Specifies the DQ pin in a byte that is designated as a primary pin for Multi-Purpose Register (MPR) reads. Valid values are 0 to 7 for DQ[0] to DQ[7] respectively." "0,1,2,3,4,5,6,7"
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bitfld.long 0x20 3. "DDR8BNK,DDR 8-Bank: Indicates if set that the SDRAM used has 8 banks. tRPA = tRP+1 and tFAW are used for 8-bank DRAMs other tRPA = tRP and no tFAW is used. Note that" "0,1"
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bitfld.long 0x20 0.--2. "DDRMD,DDR Mode: SDRAM DDR mode." "0,1,2,3,4,5,6,7"
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line.long 0x24 "DTPR0,SDRAM Timing Parameters Register 0"
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bitfld.long 0x24 31. "TCCD,Read to read and write to write command delay." "0,1"
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hexmask.long.byte 0x24 25.--30. 1. "TRC,Activate to activate command delay (same bank). Valid values are 2 to 42."
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hexmask.long.byte 0x24 21.--24. 1. "TRRD,Activate to activate command delay (different banks). Valid values are 1 to 8."
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hexmask.long.byte 0x24 16.--20. 1. "TRAS,Activate to precharge command delay. Valid values are 2 to 31."
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hexmask.long.byte 0x24 12.--15. 1. "TRCD,Activate to read or write delay. Minimum time from when an activate command is issued to when a read or write to the activated row can be issued. Valid values are 2 to 11."
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hexmask.long.byte 0x24 8.--11. 1. "TRP,Precharge command period: The minimum time between a precharge command and any other command. Note that the Controller automatically derives tRPA for 8bank DDR2 devices by adding 1 to tRP. Valid values are 2 to 11."
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bitfld.long 0x24 5.--7. "TWTR,Internal write to read command delay. Valid values are 1 to 6." "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x24 2.--4. "TRTP,Internal read to precharge command delay. Valid values are 2 to 6. Note that even though RTP does not apply to JEDEC DDR devices this parameter must still be set to a minimum value of 2 for DDR because the Controller always uses the DDR2 equation .." "0,1,2,3,4,5,6,7"
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bitfld.long 0x24 0.--1. "TMRD,Load mode cycle time: The minimum time between a load mode register command and any other command. For DDR3 this is the minimum time between two load mode register commands. Valid values for DDR2 are 2 to 3. For DDR3 the value used for tMRD is 4.." "0,1,2,3"
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line.long 0x28 "DTPR1,SDRAM Timing Parameters Register 1"
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bitfld.long 0x28 27.--29. "TDQSCKMAX,Maximum DQS output access time from CK/CK# (LPDDR2 only). This value is used for implementing read-to-write spacing. Valid values are 1 to 7." "0,1,2,3,4,5,6,7"
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bitfld.long 0x28 24.--26. "TDQSCKMIN,DQS output access time from CK/CK# (LPDDR2/3 only). This value is used for computing the read latency. Valid values are 0 to 7. This value is derived from the corresponding parameter in the SDRAM datasheet divided by the clock cycle time.." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x28 16.--23. 1. "TRFC,Refresh-to-Refresh: Indicates the minimum time in clock cycles between two refresh commands or between a refresh and an active command. This is derived from the minimum refresh interval from the datasheet tRFC(min) divided by the clock cycle.."
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bitfld.long 0x28 11. "TRTODT,Read to ODT delay (DDR3 only). Specifies whether ODT can be enabled immediately after the read post-amble or one clock delay has to be added." "0,1"
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bitfld.long 0x28 9.--10. "TMOD,Load mode update delay (DDR3 only). The minimum time between a load mode register command and a non-load mode register command." "0,1,2,3"
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hexmask.long.byte 0x28 3.--8. 1. "TFAW,4-bank activate period. No more than 4-bank activate commands may be issued in a given tFAW period. Only applies to 8-bank devices. Valid values are 2 to 31."
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bitfld.long 0x28 2. "TRTW,Read to Write command delay." "0,1"
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newline
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bitfld.long 0x28 0.--1. "TAOND,ODT turn-on/turn-off delays (DDR2 only). The delays are in clock cycles. Valid values are: 00 = 2/2.5" "0,1,2,3"
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line.long 0x2C "DTPR2,SDRAM Timing Parameters Register 2"
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hexmask.long.word 0x2C 19.--28. 1. "TDLLK,DLL locking time. Valid values are 2 to 1023."
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hexmask.long.byte 0x2C 15.--18. 1. "TCKE,CKE minimum pulse width. Also specifies the minimum time that the SDRAM must remain in power down or self refresh mode. For DDR3 this parameter must be set to the value of tCKESR which is usually bigger than the value of tCKE. Valid values are 2 to.."
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hexmask.long.byte 0x2C 10.--14. 1. "TXP,Power down exit delay. The minimum time between a power down exit command and any other command. This parameter must be set to the maximum of the various minimum power down exit delay parameters specified in the SDRAM datasheet i.e. max(tXP tXARD .."
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hexmask.long.word 0x2C 0.--9. 1. "TXS,Self refresh exit delay. The minimum time between a self refresh exit command and any other command. This parameter must be set to the maximum of the various minimum self refresh exit delay parameters specified in the SDRAM datasheet i.e. max(tXSNR .."
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line.long 0x30 "MR0,Mode Register"
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line.long 0x34 "MR1,Extended Mode Register"
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line.long 0x38 "MR2,Extended Mode Register 2"
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line.long 0x3C "MR3,Extended Mode Register 3"
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line.long 0x40 "ODTCR,ODT Configuration Register"
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hexmask.long.byte 0x40 28.--31. 1. "WRODT3,"
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hexmask.long.byte 0x40 24.--27. 1. "WRODT2,"
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hexmask.long.byte 0x40 20.--23. 1. "WRODT1,"
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hexmask.long.byte 0x40 16.--19. 1. "WRODT0,Write ODT: Specifies whether ODT should be enabled ('1') or disabled ('0') on each of the up to four ranks when a write command is sent to rank n. WRODT0 "
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hexmask.long.byte 0x40 12.--15. 1. "RDODT3,"
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hexmask.long.byte 0x40 8.--11. 1. "RDODT2,"
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hexmask.long.byte 0x40 4.--7. 1. "RDODT1,"
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newline
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hexmask.long.byte 0x40 0.--3. 1. "RDODT0,"
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line.long 0x44 "DTAR,Data Training Address Register"
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bitfld.long 0x44 31. "DTMPR,Data Training Using MPR (DDR3 Only): Specifies if set that data-training should use the SDRAM Multi-Purpose Register (MPR) register. Otherwise data-training is performed by first writing to some locations in the SDRAM and then reading them back." "0,1"
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bitfld.long 0x44 28.--30. "DTBANK,Data Training Bank Address: Selects the SDRAM bank address to be used during data training." "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x44 12.--27. 1. "DTROW,Data Training Row Address: Selects the SDRAM row address to be used during data training."
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hexmask.long.word 0x44 0.--11. 1. "DTCOL,Data Training Column Address: Selects the SDRAM column address to be used during data training. The lower four bits of this address must always be '0000'."
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line.long 0x48 "DTDR0,Data Training Data Register 0"
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hexmask.long.byte 0x48 24.--31. 1. "DTBYTE3,Data Training Data: The first 4 bytes of data used during data training. This same data byte is used for each Byte Lane. Default sequence is a walking 1 while toggling data every data cycle."
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hexmask.long.byte 0x48 16.--23. 1. "DTBYTE2,Data Training Data: The first 4 bytes of data used during data training. This same data byte is used for each Byte Lane. Default sequence is a walking 1 while toggling data every data cycle."
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hexmask.long.byte 0x48 8.--15. 1. "DTBYTE1,Data Training Data: The first 4 bytes of data used during data training. This same data byte is used for each Byte Lane. Default sequence is a walking 1 while toggling data every data cycle."
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line.long 0x4C "DTDR1,Data Training Data Register 1"
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hexmask.long.byte 0x4C 24.--31. 1. "DTBYTE7,Data Training Data: The second 4 bytes of data used during data training. This same data byte is used for each Byte Lane. Default sequence is a walking 1 while toggling data every data cycle."
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hexmask.long.byte 0x4C 16.--23. 1. "DTBYTE6,Data Training Data: The second 4 bytes of data used during data training. This same data byte is used for each Byte Lane. Default sequence is a walking 1 while toggling data every data cycle."
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hexmask.long.byte 0x4C 8.--15. 1. "DTBYTE5,Data Training Data: The second 4 bytes of data used during data training. This same data byte is used for each Byte Lane. Default sequence is a walking 1 while toggling data every data cycle."
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hexmask.long.byte 0x4C 0.--7. 1. "DTBYTE4,Data Training Data: The second 4 bytes of data used during data training. This same data byte is used for each Byte Lane. Default sequence is a walking 1 while toggling data every data cycle."
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rgroup.long 0x60++0x3
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line.long 0x0 "DTPSL,Data Training Phase shift Log"
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group.long 0x64++0x3
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line.long 0x0 "ACODLY,Data Training AC Ouput delay"
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group.long 0xC0++0x1F
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line.long 0x0 "DCUAR,DCU Address Register"
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bitfld.long 0x0 11. "ATYPE,Access Type: Specifies the type of access to be performed using this address. Valid values are: 0 = Write access" "0: Write access,?"
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bitfld.long 0x0 10. "INCA,Increment Address: Specifies if set that the cache address specified in WADDR and SADDR should be automatically incremented after each access of the cache. The increment happens in such a way that all the slices of a selected word are first.." "0,1"
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bitfld.long 0x0 8.--9. "CSEL,Cache Select: Selects the cache to be accessed." "0,1,2,3"
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hexmask.long.byte 0x0 4.--7. 1. "CSADDR,Cache Slice Address: Address of the cache slice to be accessed."
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hexmask.long.byte 0x0 0.--3. 1. "CWADDR,Cache Word Address: Address of the cache word to be accessed."
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line.long 0x4 "DCUDR,DCU Data Register"
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hexmask.long 0x4 0.--31. 1. "CDATA,Cache Data: Data to be written to or read from a cache. This data corresponds to the cache word slice specified by the DCU Address Register."
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line.long 0x8 "DCURR,DCU Run Register"
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bitfld.long 0x8 23. "XCEN,Expected Compare Enable: Indicates if set that read data coming back from the SDRAM should be should be compared with the expected data." "0,1"
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bitfld.long 0x8 22. "RCEN,Read Capture Enable: Indicates if set that read data coming back from the SDRAM should be captured into the read data cache." "0,1"
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bitfld.long 0x8 21. "SCOF,Stop Capture On Full: Specifies if set that the capture of read data should stop when the capture cache is full." "0,1"
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bitfld.long 0x8 20. "SONF,Stop On Nth Fail: Specifies if set that the execution of commands and the capture of read data should stop when there are N read data failures. The number of failures is specified by NFAIL. Otherwise commands execute until the end of the program or.." "0,1"
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hexmask.long.byte 0x8 12.--19. 1. "NFAIL,Number of Failures: Specifies the number of failures after which the execution of commands and the capture of read data should stop if SONF bit of this register is set. Execution of commands and the capture of read data will stop after (NFAIL+1).."
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hexmask.long.byte 0x8 8.--11. 1. "EADDR,End Address: Cache word address where the execution of command should end."
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hexmask.long.byte 0x8 4.--7. 1. "SADDR,Start Address: Cache word address where the execution of commands should begin."
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newline
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hexmask.long.byte 0x8 0.--3. 1. "DINST,DCU Instruction: Selects the DCU command to be executed."
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line.long 0xC "DCULR,DCU Loop Register"
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hexmask.long.byte 0xC 28.--31. 1. "XLEADDR,Expected Data Loop End Address: The last expected data cache word address that contains valid expected data. Expected data should looped between 0 and this address."
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bitfld.long 0xC 17. "IDA,Increment DRAM Address: Indicates if set that DRAM addresses should be incremented every time a DRAM read/write command inside the loop is executed." "0,1"
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bitfld.long 0xC 16. "LINF,Loop Infinite: Indicates if set that the loop should be executed indefinitely until stopped by the STOP command. Otherwise the loop is execute LCNT times." "0,1"
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hexmask.long.byte 0xC 8.--15. 1. "LCNT,Loop Count: The number of times that the loop should be executed if LINF is not set."
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hexmask.long.byte 0xC 4.--7. 1. "LEADDR,Loop End Address: Command cache word address where the loop should end."
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hexmask.long.byte 0xC 0.--3. 1. "LSADDR,Loop Start Address: Command cache word address where the loop should start."
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line.long 0x10 "DCUGCR,DCU General Configuration Register"
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hexmask.long.word 0x10 0.--15. 1. "RCSW,Read Capture Start Word: The capture and compare of read data should start after Nth word. For example setting this value to 12 will skip the first 12 read data."
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line.long 0x14 "DCUTPR,DCU Timing Parameter Register"
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hexmask.long.byte 0x14 24.--31. 1. "TDCUT3,DCU Generic Timing Parameter 3."
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hexmask.long.byte 0x14 16.--23. 1. "TDCUT2,DCU Generic Timing Parameter 2."
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hexmask.long.byte 0x14 8.--15. 1. "TDCUT1,DCU Generic Timing Parameter 1."
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hexmask.long.byte 0x14 0.--7. 1. "TDCUT0,DCU Generic Timing Parameter 0."
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line.long 0x18 "DCUSR0,DCU Status-0 Register"
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bitfld.long 0x18 2. "CFULL,Capture Full: Indicates if set that the capture cache is full." "0,1"
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bitfld.long 0x18 1. "CFAIL,Capture Fail: Indicates if set that at least one read data word has failed." "0,1"
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bitfld.long 0x18 0. "RDONE,Run Done: Indicates if set that the DCU has finished executing the commands in the command cache. This bit is also set to indicate that a STOP command has successfully been executed and command execution has stopped." "0,1"
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line.long 0x1C "DCUSR1,DCU Status-1 Register"
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hexmask.long.byte 0x1C 24.--31. 1. "LPCNT,Loop Count: Indicates the value of the loop count. This is useful when the program has stooped because of failures to assess how many reads were executed before first fail."
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hexmask.long.byte 0x1C 16.--23. 1. "FLCND,Fail Count: Number of read words that have failed."
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hexmask.long.word 0x1C 0.--15. 1. "RDCNT,Read Count: Number of read words returned from the SDRAM."
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group.long 0x100++0x43
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line.long 0x0 "BISTRR,BIST Run Register"
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line.long 0x4 "BISTMSKR0,BIST Mask 0 Register"
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line.long 0x8 "BISTMSKR1,BIST Mask 1 Register"
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line.long 0xC "BISTWCR,BIST Word Count Register"
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line.long 0x10 "BISTLSR,BIST LFSR Seed Register"
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line.long 0x14 "BISTAR0,BIST Address 0 Register"
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line.long 0x18 "BISTAR1,BIST Address 1 Register"
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line.long 0x1C "BISTAR2,BIST Address 2 Register"
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line.long 0x20 "BISTUDPR,BIST User Data Pattern Register"
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line.long 0x24 "BISTGSR,BIST General Status Register"
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line.long 0x28 "BISTWER,BIST Word Error Register"
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line.long 0x2C "BISTBER0,BIST Bit Error 0 Register"
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line.long 0x30 "BISTBER1,BIST Bit Error 1 Register"
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line.long 0x34 "BISTBER2,BIST Bit Error 2 Register"
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line.long 0x38 "BISTWCSR,BIST Word Count Status Register"
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line.long 0x3C "BISTFWR0,BIST Fail Word 0 Register"
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line.long 0x40 "BISTFWR1,BIST Fail Word 1 Register"
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group.long 0x178++0xF
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line.long 0x0 "GPR0,General Purpose Register 0"
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line.long 0x4 "GPR1,General Purpose Register 1"
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line.long 0x8 "ZQ0CR0,ZQ Impedence Control Register 0"
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line.long 0xC "ZQ0CR1,ZQ Impedence Control Register 1"
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rgroup.long 0x188++0x7
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line.long 0x0 "ZQ0SR0,ZQ Impedence Control Status Register 0"
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line.long 0x4 "ZQ0SR1,ZQ Impedence Control Status Register 1"
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group.long 0x190++0x7
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line.long 0x0 "ZQ1CR0,ZQ Impedence Control Register 0"
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line.long 0x4 "ZQ1CR1,ZQ Impedence Control Register 1"
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rgroup.long 0x198++0x7
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line.long 0x0 "ZQ1SR0,ZQ Impedence Control Status Register 0"
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line.long 0x4 "ZQ1SR1,ZQ Impedence Control Status Register 1"
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group.long 0x1A0++0x7
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line.long 0x0 "ZQ2CR0,ZQ Impedence Control Register 0"
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line.long 0x4 "ZQ2CR1,ZQ Impedence Control Register 1"
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rgroup.long 0x1A8++0x7
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line.long 0x0 "ZQ2SR0,ZQ Impedence Control Status Register 0"
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line.long 0x4 "ZQ2SR1,ZQ Impedence Control Status Register 1"
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group.long 0x1B0++0x7
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line.long 0x0 "ZQ3CR0,ZQ Impedence Control Register 0"
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line.long 0x4 "ZQ3CR1,ZQ Impedence Control Register 1"
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rgroup.long 0x1B8++0x7
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line.long 0x0 "ZQ3SR0,ZQ Impedence Control Status Register 0"
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line.long 0x4 "ZQ3SR1,ZQ Impedence Control Status Register 1"
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group.long 0x1C0++0x3
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line.long 0x0 "DX0GCR,DATX8 General Configuration Register"
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rgroup.long 0x1C4++0x7
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line.long 0x0 "DX0GSR0,DATX8 General Status Register 0"
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line.long 0x4 "DX0GSR1,DATX8 General Status Register 1"
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group.long 0x1CC++0x1B
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line.long 0x0 "DX0DLLCR,DATX8 DLL Control Register"
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line.long 0x4 "DX0DQTR,DATX8 DQ Timing Register"
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line.long 0x8 "DX0DQSTR,DATX8 DQS Timing Register"
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line.long 0xC "DX0DQIDLY,DATX8 DQ Input Delay"
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line.long 0x10 "DX0DQODLY,DATX8 DQ Output Delay"
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line.long 0x14 "DX0DQSIDLY,DATX8 DQS Input Delay"
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line.long 0x18 "DX0DQSODLY,DATX8 DQS Output Delay"
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group.long 0x200++0x3
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line.long 0x0 "DX1GCR,DATX8 General Configuration Register"
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rgroup.long 0x204++0x7
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line.long 0x0 "DX1GSR0,DATX8 General Status Register 0"
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line.long 0x4 "DX1GSR1,DATX8 General Status Register 1"
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group.long 0x20C++0x1B
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line.long 0x0 "DX1DLLCR,DATX8 DLL Control Register"
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line.long 0x4 "DX1DQTR,DATX8 DQ Timing Register"
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line.long 0x8 "DX1DQSTR,DATX8 DQS Timing Register"
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line.long 0xC "DX1DQIDLY,DATX8 DQ Input Delay"
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line.long 0x10 "DX1DQODLY,DATX8 DQ Output Delay"
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line.long 0x14 "DX1DQSIDLY,DATX8 DQS Input Delay"
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line.long 0x18 "DX1DQSODLY,DATX8 DQS Output Delay"
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group.long 0x240++0x3
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line.long 0x0 "DX2GCR,DATX8 General Configuration Register"
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|
rgroup.long 0x244++0x7
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line.long 0x0 "DX2GSR0,DATX8 General Status Register 0"
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line.long 0x4 "DX2GSR1,DATX8 General Status Register 1"
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group.long 0x24C++0x1B
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line.long 0x0 "DX2DLLCR,DATX8 DLL Control Register"
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|
line.long 0x4 "DX2DQTR,DATX8 DQ Timing Register"
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line.long 0x8 "DX2DQSTR,DATX8 DQS Timing Register"
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line.long 0xC "DX2DQIDLY,DATX8 DQ Input Delay"
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line.long 0x10 "DX2DQODLY,DATX8 DQ Output Delay"
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line.long 0x14 "DX2DQSIDLY,DATX8 DQS Input Delay"
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|
line.long 0x18 "DX2DQSODLY,DATX8 DQS Output Delay"
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|
group.long 0x280++0x3
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|
line.long 0x0 "DX3GCR,DATX8 General Configuration Register"
|
|
rgroup.long 0x284++0x7
|
|
line.long 0x0 "DX3GSR0,DATX8 General Status Register 0"
|
|
line.long 0x4 "DX3GSR1,DATX8 General Status Register 1"
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|
group.long 0x28C++0x1B
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|
line.long 0x0 "DX3DLLCR,DATX8 DLL Control Register"
|
|
line.long 0x4 "DX3DQTR,DATX8 DQ Timing Register"
|
|
line.long 0x8 "DX3DQSTR,DATX8 DQS Timing Register"
|
|
line.long 0xC "DX3DQIDLY,DATX8 DQ Input Delay"
|
|
line.long 0x10 "DX3DQODLY,DATX8 DQ Output Delay"
|
|
line.long 0x14 "DX3DQSIDLY,DATX8 DQS Input Delay"
|
|
line.long 0x18 "DX3DQSODLY,DATX8 DQS Output Delay"
|
|
group.long 0x2C0++0x3
|
|
line.long 0x0 "DX4GCR,DATX8 General Configuration Register"
|
|
rgroup.long 0x2C4++0x7
|
|
line.long 0x0 "DX4GSR0,DATX8 General Status Register 0"
|
|
line.long 0x4 "DX4GSR1,DATX8 General Status Register 1"
|
|
group.long 0x2CC++0x1B
|
|
line.long 0x0 "DX4DLLCR,DATX8 DLL Control Register"
|
|
line.long 0x4 "DX4DQTR,DATX8 DQ Timing Register"
|
|
line.long 0x8 "DX4DQSTR,DATX8 DQS Timing Register"
|
|
line.long 0xC "DX4DQIDLY,DATX8 DQ Input Delay"
|
|
line.long 0x10 "DX4DQODLY,DATX8 DQ Output Delay"
|
|
line.long 0x14 "DX4DQSIDLY,DATX8 DQS Input Delay"
|
|
line.long 0x18 "DX4DQSODLY,DATX8 DQS Output Delay"
|
|
group.long 0x300++0x3
|
|
line.long 0x0 "DX5GCR,DATX8 General Configuration Register"
|
|
rgroup.long 0x304++0x7
|
|
line.long 0x0 "DX5GSR0,DATX8 General Status Register 0"
|
|
line.long 0x4 "DX5GSR1,DATX8 General Status Register 1"
|
|
group.long 0x30C++0x1B
|
|
line.long 0x0 "DX5DLLCR,DATX8 DLL Control Register"
|
|
line.long 0x4 "DX5DQTR,DATX8 DQ Timing Register"
|
|
line.long 0x8 "DX5DQSTR,DATX8 DQS Timing Register"
|
|
line.long 0xC "DX5DQIDLY,DATX8 DQ Input Delay"
|
|
line.long 0x10 "DX5DQODLY,DATX8 DQ Output Delay"
|
|
line.long 0x14 "DX5DQSIDLY,DATX8 DQS Input Delay"
|
|
line.long 0x18 "DX5DQSODLY,DATX8 DQS Output Delay"
|
|
group.long 0x340++0x3
|
|
line.long 0x0 "DX6GCR,DATX8 General Configuration Register"
|
|
rgroup.long 0x344++0x7
|
|
line.long 0x0 "DX6GSR0,DATX8 General Status Register 0"
|
|
line.long 0x4 "DX6GSR1,DATX8 General Status Register 1"
|
|
group.long 0x34C++0x1B
|
|
line.long 0x0 "DX6DLLCR,DATX8 DLL Control Register"
|
|
line.long 0x4 "DX6DQTR,DATX8 DQ Timing Register"
|
|
line.long 0x8 "DX6DQSTR,DATX8 DQS Timing Register"
|
|
line.long 0xC "DX6DQIDLY,DATX8 DQ Input Delay"
|
|
line.long 0x10 "DX6DQODLY,DATX8 DQ Output Delay"
|
|
line.long 0x14 "DX6DQSIDLY,DATX8 DQS Input Delay"
|
|
line.long 0x18 "DX6DQSODLY,DATX8 DQS Output Delay"
|
|
group.long 0x380++0x3
|
|
line.long 0x0 "DX7GCR,DATX8 General Configuration Register"
|
|
rgroup.long 0x384++0x7
|
|
line.long 0x0 "DX7GSR0,DATX8 General Status Register 0"
|
|
line.long 0x4 "DX7GSR1,DATX8 General Status Register 1"
|
|
group.long 0x38C++0x1B
|
|
line.long 0x0 "DX7DLLCR,DATX8 DLL Control Register"
|
|
line.long 0x4 "DX7DQTR,DATX8 DQ Timing Register"
|
|
line.long 0x8 "DX7DQSTR,DATX8 DQS Timing Register"
|
|
line.long 0xC "DX7DQIDLY,DATX8 DQ Input Delay"
|
|
line.long 0x10 "DX7DQODLY,DATX8 DQ Output Delay"
|
|
line.long 0x14 "DX7DQSIDLY,DATX8 DQS Input Delay"
|
|
line.long 0x18 "DX7DQSODLY,DATX8 DQS Output Delay"
|
|
group.long 0x3C0++0x3
|
|
line.long 0x0 "DX8GCR,DATX8 General Configuration Register"
|
|
rgroup.long 0x3C4++0x7
|
|
line.long 0x0 "DX8GSR0,DATX8 General Status Register 0"
|
|
line.long 0x4 "DX8GSR1,DATX8 General Status Register 1"
|
|
group.long 0x3CC++0x1B
|
|
line.long 0x0 "DX8DLLCR,DATX8 DLL Control Register"
|
|
line.long 0x4 "DX8DQTR,DATX8 DQ Timing Register"
|
|
line.long 0x8 "DX8DQSTR,DATX8 DQS Timing Register"
|
|
line.long 0xC "DX8DQIDLY,DATX8 DQ Input Delay"
|
|
line.long 0x10 "DX8DQODLY,DATX8 DQ Output Delay"
|
|
line.long 0x14 "DX8DQSIDLY,DATX8 DQS Input Delay"
|
|
line.long 0x18 "DX8DQSODLY,DATX8 DQS Output Delay"
|
|
tree.end
|
|
tree "DWDT (Dual Watchdog Timer)"
|
|
base ad:0xE001C000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "NS_WDT_CR,Never Secure Control Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "KEY,Password"
|
|
bitfld.long 0x0 4. "LOCKMR,Lock Mode Register Write Access" "0: No effect.,1: Locks the configuration registers if KEY is.."
|
|
newline
|
|
bitfld.long 0x0 0. "WDRSTT,Watchdog Restart" "0: No effect.,1: Restarts the watchdog if KEY is written to 0xA5."
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "NS_WDT_MR,Never Secure Mode Register"
|
|
bitfld.long 0x0 29. "WDIDLEHLT,Watchdog Idle Halt" "0: The watchdog runs when the system is in Idle..,1: The watchdog stops when the system is in Idle.."
|
|
bitfld.long 0x0 28. "WDDBGHLT,Watchdog Debug Halt" "0: The watchdog runs when the processor is in Debug..,1: The watchdog stops when the processor is in.."
|
|
newline
|
|
bitfld.long 0x0 12. "WDDIS,Watchdog Disable" "0: Enables the Watchdog Timer.,1: Disables the Watchdog Timer."
|
|
bitfld.long 0x0 5. "RPTHALM,Repeat Threshold Alarm" "0: No alarm is sent to the security module if the..,1: An alarm is sent to the security module if the.."
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "NS_WDT_VR,Never Secure Value Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "COUNTER,Watchdog Down Counter Value"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "NS_WDT_WL,Never Secure Window Level Register"
|
|
hexmask.long.word 0x0 16.--27. 1. "RPTH,Repeat Threshold"
|
|
hexmask.long.word 0x0 0.--11. 1. "PERIOD,Watchdog Period"
|
|
line.long 0x4 "NS_WDT_IL,Never Secure Interrupt Level Register"
|
|
hexmask.long.word 0x4 0.--11. 1. "LVLTH,Level Threshold"
|
|
wgroup.long 0x14++0x7
|
|
line.long 0x0 "NS_WDT_IER,Never Secure Interrupt Enable Register"
|
|
bitfld.long 0x0 2. "LVLINT,Interrupt Level Threshold Interrupt Enable" "0: No effect.,1: The never secure interrupt threshold failure.."
|
|
bitfld.long 0x0 1. "RPTHINT,Repeat Threshold Interrupt Enable" "0: No effect.,1: The never secure repeat threshold failure.."
|
|
newline
|
|
bitfld.long 0x0 0. "PERINT,Period Interrupt Enable" "0: No effect.,1: The never secure period failure interrupt is.."
|
|
line.long 0x4 "NS_WDT_IDR,Never Secure Interrupt Disable Register"
|
|
bitfld.long 0x4 2. "LVLINT,Interrupt Level Threshold Interrupt Disable" "0: No effect.,1: The never secure interrupt threshold failure.."
|
|
bitfld.long 0x4 1. "RPTHINT,Repeat Threshold Interrupt Disable" "0: No effect.,1: The never secure repeat threshold failure.."
|
|
newline
|
|
bitfld.long 0x4 0. "PERINT,Period Interrupt Disable" "0: No effect.,1: The never secure period failure interrupt is.."
|
|
rgroup.long 0x1C++0x7
|
|
line.long 0x0 "NS_WDT_ISR,Never Secure Interrupt Status Register"
|
|
bitfld.long 0x0 2. "LVLINT,Interrupt Level Threshold Interrupt Enable" "0: No level threshold failure has occurred in the..,1: At least one level threshold failure has.."
|
|
bitfld.long 0x0 1. "RPTHINT,Repeat Threshold Interrupt Enable" "0: No repeat threshold failure has occurred in the..,1: At least one repeat threshold failure has.."
|
|
newline
|
|
bitfld.long 0x0 0. "PERINT,Period Interrupt Status" "0: No period failure has occurred in the never..,1: At least one period failure has occurred in the.."
|
|
line.long 0x4 "NS_WDT_IMR,Never Secure Interrupt Mask Register"
|
|
bitfld.long 0x4 2. "LVLINT,Interrupt Level Threshold Interrupt Mask" "0: Interrupt on LVLINT is disabled.,1: Interrupt on LVLINT is enabled."
|
|
bitfld.long 0x4 1. "RPTHINT,Repeat Threshold Interrupt Mask" "0: Interrupt on RPTHINT is disabled.,1: Interrupt on RPTHINT is enabled."
|
|
newline
|
|
bitfld.long 0x4 0. "PERINT,Period Interrupt Mask" "0: Interrupt on PERINT is disabled.,1: Interrupt on PERINT is enabled."
|
|
wgroup.long 0x1180++0x3
|
|
line.long 0x0 "PS_WDT_CR,Programmable Secure Control Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "KEY,Password"
|
|
bitfld.long 0x0 4. "LOCKMR,Lock Mode Register Write Access" "0: No effect.,1: Locks the configuration registers if KEY is.."
|
|
newline
|
|
bitfld.long 0x0 0. "WDRSTT,Watchdog Restart" "0: No effect.,1: Restarts the watchdog if KEY is written to 0xA5."
|
|
group.long 0x1184++0x3
|
|
line.long 0x0 "PS_WDT_MR,Programmable Secure Mode Register"
|
|
bitfld.long 0x0 29. "WDIDLEHLT,Watchdog Idle Halt" "0: The watchdog runs when the system is in Idle..,1: The watchdog stops when the system is in Idle.."
|
|
bitfld.long 0x0 28. "WDDBGHLT,Watchdog Debug Halt" "0: The watchdog runs when the processor is in Debug..,1: The watchdog stops when the processor is in.."
|
|
newline
|
|
bitfld.long 0x0 12. "WDDIS,Watchdog Disable" "0: Enables the Watchdog Timer.,1: Disables the Watchdog Timer."
|
|
bitfld.long 0x0 5. "RPTHRST,Repeat Threshold Reset" "0: No reset is generated if the watchdog is..,1: A reset is generated if the watchdog is.."
|
|
newline
|
|
bitfld.long 0x0 4. "PERIODRST,Period Reset" "0: No reset is generated if the watchdog down..,1: A reset is generated once the watchdog down.."
|
|
rgroup.long 0x1188++0x3
|
|
line.long 0x0 "PS_WDT_VR,Programmable Secure Value Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "COUNTER,Watchdog Down Counter Value"
|
|
group.long 0x118C++0x7
|
|
line.long 0x0 "PS_WDT_WL,Programmable Secure Window Level"
|
|
hexmask.long.word 0x0 16.--27. 1. "RPTH,Repeat Threshold"
|
|
hexmask.long.word 0x0 0.--11. 1. "PERIOD,Watchdog Period"
|
|
line.long 0x4 "PS_WDT_IL,Programmable Secure Interrupt Level"
|
|
hexmask.long.word 0x4 0.--11. 1. "LVLTH,Level Threshold"
|
|
wgroup.long 0x1194++0x7
|
|
line.long 0x0 "PS_WDT_IER,Programmable Secure Interrupt Enable Register"
|
|
bitfld.long 0x0 4. "NSRPTHINT,Never Secure Repeat Threshold Interrupt Enable" "0: No effect.,1: A never secure repeat threshold failure.."
|
|
bitfld.long 0x0 3. "NSPERINT,Never Secure Period Interrupt Enable" "0: No effect.,1: A never secure period failure generates an.."
|
|
newline
|
|
bitfld.long 0x0 2. "LVLINT,Interrupt Level Threshold Interrupt Enable" "0: No effect.,1: The programmable secure interrupt threshold.."
|
|
bitfld.long 0x0 1. "RPTHINT,Repeat Threshold Interrupt Enable" "0: No effect.,1: The programmable secure repeat threshold failure.."
|
|
newline
|
|
bitfld.long 0x0 0. "PERINT,Period Interrupt Enable" "0: No effect.,1: The programmable secure period failure interrupt.."
|
|
line.long 0x4 "PS_WDT_IDR,Programmable Secure Interrupt Disable Register"
|
|
bitfld.long 0x4 4. "NSRPTHINT,Never Secure Repeat Threshold Interrupt Disable" "0: No effect.,1: A never secure repeat threshold failure does not.."
|
|
bitfld.long 0x4 3. "NSPERINT,Never Secure Period Interrupt Disable" "0: No effect.,1: A never secure period failure does not generate.."
|
|
newline
|
|
bitfld.long 0x4 2. "LVLINT,Interrupt Level Threshold Interrupt Disable" "0: No effect.,1: The Programmable secure interrupt threshold.."
|
|
bitfld.long 0x4 1. "RPTHINT,Repeat Threshold Interrupt Disable" "0: No effect.,1: The Programmable secure repeat threshold failure.."
|
|
newline
|
|
bitfld.long 0x4 0. "PERINT,Period Interrupt Disable" "0: No effect.,1: The Programmable secure period failure interrupt.."
|
|
rgroup.long 0x119C++0x7
|
|
line.long 0x0 "PS_WDT_ISR,Programmable Secure Interrupt Status Register"
|
|
bitfld.long 0x0 4. "NSRPTHINT,Never Secure Repeat Threshold Interrupt Status" "0: No never secure repeat threshold failure has..,1: At least one never secure repeat threshold.."
|
|
bitfld.long 0x0 3. "NSPERINT,Never Secure Period Interrupt Status" "0: No never secure period failure has occurred in..,1: At least one never secure period failure.."
|
|
newline
|
|
bitfld.long 0x0 2. "LVLINT,Interrupt Level Threshold Interrupt Status" "0: No level threshold failure has occurred in the..,1: At least one level threshold failure has.."
|
|
bitfld.long 0x0 1. "RPTHINT,Repeat Threshold Interrupt Status" "0: No repeat threshold failure has occurred in the..,1: At least one repeat threshold failure has.."
|
|
newline
|
|
bitfld.long 0x0 0. "PERINT,Period Interrupt Status" "0: No period failure has occurred in the..,1: At least one period failure has occurred in the.."
|
|
line.long 0x4 "PS_WDT_IMR,Programmable Secure Interrupt Mask Register"
|
|
bitfld.long 0x4 4. "NSRPTHINT,Never Secure Repeat Threshold Interrupt Mask" "0: Programmable secure interrupt on never secure..,1: Programmable secure interrupt on never secure.."
|
|
bitfld.long 0x4 3. "NSPERINT,Never Secure Period Interrupt Mask" "0: Programmable secure interrupt on never secure..,1: Programmable secure interrupt on never secure.."
|
|
newline
|
|
bitfld.long 0x4 2. "LVLINT,Interrupt Level Threshold Interrupt Mask" "0: Interrupt on LVLINT is disabled.,1: Interrupt on LVLINT is enabled."
|
|
bitfld.long 0x4 1. "RPTHINT,Repeat Threshold Interrupt Mask" "0: Interrupt on RPTHINT is disabled.,1: Interrupt on RPTHINT is enabled."
|
|
newline
|
|
bitfld.long 0x4 0. "PERINT,Period Interrupt Mask" "0: Interrupt on PERINT is disabled.,1: Interrupt on PERINT is enabled."
|
|
group.long 0x11A4++0xB
|
|
line.long 0x0 "NS_WDT_LVLLIM,Never Secure Level Limits Register"
|
|
hexmask.long.word 0x0 16.--27. 1. "LVLMAX,Level Maximum"
|
|
hexmask.long.word 0x0 0.--11. 1. "LVLMIN,Level Minimum"
|
|
line.long 0x4 "NS_WDT_RLIM,Never Secure Repeat Limits Register"
|
|
hexmask.long.word 0x4 16.--27. 1. "RPTHMAX,Repeat Threshold Maximum"
|
|
hexmask.long.word 0x4 0.--11. 1. "RPTHMIN,Repeat Threshold Minimum"
|
|
line.long 0x8 "NS_WDT_PLIM,Never Secure Period Limits Register"
|
|
hexmask.long.word 0x8 16.--27. 1. "PERMAX,Period Maximum"
|
|
hexmask.long.word 0x8 0.--11. 1. "PERMIN,Period Minimum"
|
|
tree.end
|
|
tree "EIC (External Interrupt Controller)"
|
|
base ad:0xE1628000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "GFCS,Glitch Filter Configuration Status Register"
|
|
bitfld.long 0x0 1. "RDY1,Filter 1 Configuration Ready" "0: The interrupt line x glitch filter is not yet..,1: The interrupt line x glitch filter configuration.."
|
|
bitfld.long 0x0 0. "RDY0,Filter 0 Configuration Ready" "0: The interrupt line x glitch filter is not yet..,1: The interrupt line x glitch filter configuration.."
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "SCFG0R,Source Configuration Register 0"
|
|
bitfld.long 0x0 31. "FRZ,Interrupt Line Freeze" "0: No effect.,1: EIC_SCFGxR is frozen until hardware reset."
|
|
bitfld.long 0x0 16. "EN,Source Enable" "0: The EIC source x is disabled. Any source edge or..,1: The EIC source x is enabled."
|
|
newline
|
|
bitfld.long 0x0 9. "LVL,Level Detection" "0: The EIC source x interrupt status is set on a..,1: The EIC source x interrupt status is set on a.."
|
|
bitfld.long 0x0 8. "POL,Polarity" "0: The EIC source x is active low if LVL is set or..,1: The EIC source x is active high if LVL is set or.."
|
|
newline
|
|
bitfld.long 0x0 4. "GFEN,Glitch Filter Enable" "0: The glitch filter is disabled or not implemented..,1: The glitch filter is enabled for EIC source x."
|
|
bitfld.long 0x0 0.--1. "GFSEL,Glitch Filter Selector" "0,1,2,3"
|
|
line.long 0x4 "SCFG1R,Source Configuration Register 1"
|
|
bitfld.long 0x4 31. "FRZ,Interrupt Line Freeze" "0: No effect.,1: EIC_SCFGxR is frozen until hardware reset."
|
|
bitfld.long 0x4 16. "EN,Source Enable" "0: The EIC source x is disabled. Any source edge or..,1: The EIC source x is enabled."
|
|
newline
|
|
bitfld.long 0x4 9. "LVL,Level Detection" "0: The EIC source x interrupt status is set on a..,1: The EIC source x interrupt status is set on a.."
|
|
bitfld.long 0x4 8. "POL,Polarity" "0: The EIC source x is active low if LVL is set or..,1: The EIC source x is active high if LVL is set or.."
|
|
newline
|
|
bitfld.long 0x4 4. "GFEN,Glitch Filter Enable" "0: The glitch filter is disabled or not implemented..,1: The glitch filter is enabled for EIC source x."
|
|
bitfld.long 0x4 0.--1. "GFSEL,Glitch Filter Selector" "0,1,2,3"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPCFEN,Write Protection Configuration Enable" "0: Disables the write protection of the..,1: Enables the write protection of the.."
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WVSRC,Write Violation Source"
|
|
bitfld.long 0x0 2. "BSWVS,Busy Register Write Violation Status" "0: No write access violation of a busy register has..,1: A write access violation of a busy register has.."
|
|
newline
|
|
bitfld.long 0x0 1. "FZWVS,Frozen Register Write Violation Status" "0: No write access violation of a frozen register..,1: A write access violation of a frozen register.."
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Register Violation Status" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
|
|
tree.end
|
|
tree "FLEXCOM (Flexible Serial Communication Controller)"
|
|
base ad:0x0
|
|
tree "FLEXCOM0"
|
|
base ad:0xE1818000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
|
|
bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected. USART/TWI..,3: All TWI related protocols are selected (TWI.."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
|
|
wgroup.long 0x200++0x3
|
|
line.long 0x0 "FLEX_US_CR,USART Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0: No effect.,1: Disables the Transmit and Receive FIFOs."
|
|
newline
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0: No effect.,1: Enables the Transmit and Receive FIFOs."
|
|
newline
|
|
bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0: No effect.,1: Restarts the comparison trigger to enable.."
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0: No effect.,1: Clears the Transmit FIFO Lock"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0: No effect.,1: Empties the Receive FIFO."
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0: No effect.,1: Empties the Transmit FIFO."
|
|
newline
|
|
bitfld.long 0x0 21. "LINWKUP,Send LIN Wakeup Signal" "0: No effect:,1: Sends a wakeup signal on the LIN bus."
|
|
newline
|
|
bitfld.long 0x0 20. "LINABT,Abort LIN Transmission" "0: No effect.,1: Aborts the current LIN transmission."
|
|
newline
|
|
bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0: No effect.,1: Drives the RTS pin to 0 if FLEX_US_MR.USART_MODE.."
|
|
newline
|
|
bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0: No effect.,1: Drives the RTS pin to 1 if FLEX_US_MR.USART_MODE.."
|
|
newline
|
|
bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0: No effect,1: Immediately restarts timeout period."
|
|
newline
|
|
bitfld.long 0x0 14. "RSTNACK,Reset Non Acknowledge" "0: No effect,1: Resets FLEX_US_CSR.NACK."
|
|
newline
|
|
bitfld.long 0x0 13. "RSTIT,Reset Iterations" "0: No effect.,1: Resets FLEX_US_CSR.ITER. No effect if the.."
|
|
newline
|
|
bitfld.long 0x0 12. "SENDA,Send Address" "0: No effect.,1: In Multidrop mode only the next character.."
|
|
newline
|
|
bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0: No effect.,1: Starts waiting for a character before clocking.."
|
|
newline
|
|
bitfld.long 0x0 10. "STPBRK,Stop Break" "0: No effect.,1: Stops transmission of the break after a minimum.."
|
|
newline
|
|
bitfld.long 0x0 9. "STTBRK,Start Break" "0: No effect.,1: Starts transmission of a break after the.."
|
|
newline
|
|
bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0: No effect.,1: Resets the status bits PARE FRAME OVRE MANE.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0: No effect.,1: Disables the transmitter."
|
|
newline
|
|
bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0: No effect.,1: Enables the transmitter if TXDIS is 0."
|
|
newline
|
|
bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0: No effect.,1: Disables the receiver."
|
|
newline
|
|
bitfld.long 0x0 4. "RXEN,Receiver Enable" "0: No effect.,1: Enables the receiver if RXDIS is 0."
|
|
newline
|
|
bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0: No effect.,1: Resets the transmitter."
|
|
newline
|
|
bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0: No effect.,1: Resets the receiver."
|
|
group.long 0x204++0x3
|
|
line.long 0x0 "FLEX_US_MR,USART Mode Register"
|
|
bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0: Start frame delimiter is COMMAND or DATA SYNC.,1: Start frame delimiter is one bit."
|
|
newline
|
|
bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0: The Manchester start bit is a 0 to 1 transition,1: The Manchester start bit is a 1 to 0 transition."
|
|
newline
|
|
bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0: Manchester encoder/decoder are disabled.,1: Manchester encoder/decoder are enabled."
|
|
newline
|
|
bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0: The USART does not filter the receive line.,1: The USART filters the receive line using a.."
|
|
newline
|
|
bitfld.long 0x0 24.--26. "MAX_ITERATION,Maximum Number of Automatic Iteration" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 23. "INVDATA,Inverted Data" "0: The data field transmitted on TXD line is the..,1: The data field transmitted on TXD line is.."
|
|
newline
|
|
bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0: User defined configuration of command or data..,1: The sync field is updated when a character is.."
|
|
newline
|
|
bitfld.long 0x0 21. "DSNACK,Disable Successive NACK" "0: NACK is sent on the ISO line as soon as a parity..,1: Successive parity errors are counted up to the.."
|
|
newline
|
|
bitfld.long 0x0 20. "INACK,Inhibit Non Acknowledge" "0: The NACK is generated.,1: The NACK is not generated."
|
|
newline
|
|
bitfld.long 0x0 19. "OVER,Oversampling Mode" "0: 16x Oversampling.,1: 8x Oversampling."
|
|
newline
|
|
bitfld.long 0x0 18. "CLKO,Clock Output Select" "0: The USART does not drive the SCK pin..,1: The USART drives the SCK pin if USCLKS does not.."
|
|
newline
|
|
bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0: CHRL defines character length.,1: 9-bit character length."
|
|
newline
|
|
bitfld.long 0x0 16. "MSBF,Bit Order" "0: Least significant bit is sent/received first.,1: Most significant bit is sent/received first."
|
|
newline
|
|
bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
|
|
newline
|
|
bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
|
|
newline
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bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
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newline
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bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0: USART operates in Asynchronous mode (UART).,1: USART operates in Synchronous mode."
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newline
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bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
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bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
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hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
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wgroup.long 0x208++0x3
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line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Enable" "0,1"
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bitfld.long 0x0 10. "ITER,Max number of Repetitions Reached Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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wgroup.long 0x208++0x7
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line.long 0x0 "FLEX_US_IER_LIN_MODE,USART Interrupt Enable Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Enable" "0,1"
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Enable" "0,1"
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Enable" "0,1"
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
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bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt Disable" "0,1"
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bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached Interrupt Disable" "0,1"
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bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
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bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
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bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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wgroup.long 0x20C++0x3
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line.long 0x0 "FLEX_US_IDR_LIN_MODE,USART Interrupt Disable Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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rgroup.long 0x210++0x3
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line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 10. "ITER,Max Number of Repetitions Reached Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
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rgroup.long 0x210++0x7
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line.long 0x0 "FLEX_US_IMR_LIN_MODE,USART Interrupt Mask Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
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bitfld.long 0x4 24. "MANE,Manchester Error" "0: No Manchester error has been detected since the..,1: At least one Manchester error has been detected.."
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newline
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bitfld.long 0x4 23. "CTS,Image of CTS Input" "0: CTS input is driven low.,1: CTS input is driven high."
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newline
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bitfld.long 0x4 22. "CMP,Comparison Status" "0: No received character matched the comparison..,1: A received character matched the comparison.."
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newline
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0: No input change has been detected on the CTS pin..,1: At least one input change has been detected on.."
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newline
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt" "0: Non acknowledge has not been detected since the..,1: At least one non acknowledge has been detected.."
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newline
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bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached" "0: Maximum number of repetitions has not been..,1: Maximum number of repetitions has been reached.."
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newline
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bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0: There are characters in either FLEX_US_THR or..,1: There are no characters in FLEX_US_THR nor in.."
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newline
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bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0: There has not been a timeout since the last..,1: There has been a timeout since the last Start.."
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newline
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bitfld.long 0x4 7. "PARE,Parity Error" "0: No parity error has been detected since the last..,1: At least one parity error has been detected.."
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newline
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bitfld.long 0x4 6. "FRAME,Framing Error" "0: No stop bit has been detected low since the last..,1: At least one stop bit has been detected low.."
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newline
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bitfld.long 0x4 5. "OVRE,Overrun Error" "0: No overrun error has occurred since the last..,1: At least one overrun error has occurred since.."
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newline
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bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0: No break received or end of break detected since..,1: Break received or end of break detected since.."
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newline
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bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0: Transmit FIFO is full and cannot accept more data,1: Transmit FIFO is not full; one or more data can.."
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newline
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bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0: Receive FIFO is empty; no data to read,1: At least one unread data is in the Receive FIFO"
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rgroup.long 0x214++0x7
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line.long 0x0 "FLEX_US_CSR_LIN_MODE,USART Channel Status Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error" "0: No LIN header timeout error has been detected..,1: A LIN header timeout error has been detected.."
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newline
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error" "0: No LIN synch tolerance error has been detected..,1: A LIN synch tolerance error has been detected.."
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newline
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error" "0: No LIN slave not responding error has been..,1: A LIN slave not responding error has been.."
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newline
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error" "0: No LIN checksum error has been detected since..,1: A LIN checksum error has been detected since the.."
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newline
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Error" "0: No LIN identifier parity error has been detected..,1: A LIN identifier parity error has been detected.."
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newline
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error" "0: No LIN inconsistent synch field error has been..,1: The USART is configured as a slave node and a.."
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newline
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bitfld.long 0x0 25. "LINBE,LIN Bit Error" "0: No bit error has been detected since the last..,1: A bit error has been detected since the last.."
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newline
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bitfld.long 0x0 23. "LINBLS,LIN Bus Line Status" "0: LIN bus line is set to 0.,1: LIN bus line is set to 1."
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newline
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed" "0: The USART is idle or a LIN transfer is ongoing.,1: A LIN transfer has been completed since the last.."
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newline
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received" "0: No LIN identifier has been received since the..,1: At least one LIN identifier has been received.."
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newline
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received" "0: No LIN break has received sent since the last..,1: At least one LIN break has been received since.."
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newline
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bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0: There are characters in either FLEX_US_THR or..,1: There are no characters in FLEX_US_THR nor in.."
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newline
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bitfld.long 0x0 8. "TIMEOUT,Receiver Timeout" "0: There has not been a timeout since the last..,1: There has been a timeout since the last start.."
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newline
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bitfld.long 0x0 7. "PARE,Parity Error" "0: No parity error has been detected since the last..,1: At least one parity error has been detected.."
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error" "0: No stop bit has been detected low since the last..,1: At least one stop bit has been detected low.."
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error" "0: No overrun error has occurred since the last..,1: At least one overrun error has occurred since.."
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newline
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bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0: A character in FLEX_US_THR is waiting to be..,1: There is no character in FLEX_US_THR."
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newline
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bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0: No complete character has been received since..,1: At least one complete character has been.."
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line.long 0x4 "FLEX_US_RHR,USART Receive Holding Register"
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bitfld.long 0x4 15. "RXSYNH,Received Sync" "0: Last character received is a data.,1: Last character received is a command."
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newline
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hexmask.long.word 0x4 0.--8. 1. "RXCHR,Received Character"
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rgroup.long 0x218++0x3
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line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Characters"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Characters"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Characters"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Characters"
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wgroup.long 0x21C++0x3
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line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
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bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0: The next character sent is encoded as a data.,1: The next character sent is encoded as a command."
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newline
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hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
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wgroup.long 0x21C++0x3
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line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
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group.long 0x220++0xB
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line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
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bitfld.long 0x0 16.--18. "FP,Fractional Part" "0: Fractional divider is disabled.,?,?,?,?,?,?,?"
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newline
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hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
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line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
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hexmask.long.tbyte 0x4 0.--16. 1. "TO,Timeout Value"
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line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
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hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
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group.long 0x240++0x3
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line.long 0x0 "FLEX_US_FIDI,USART FI DI Ratio Register"
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hexmask.long.word 0x0 0.--15. 1. "FI_DI_RATIO,FI Over DI Ratio Value"
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rgroup.long 0x244++0x3
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line.long 0x0 "FLEX_US_NER,USART Number of Errors Register"
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hexmask.long.byte 0x0 0.--7. 1. "NB_ERRORS,Number of Errors"
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group.long 0x24C++0xF
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line.long 0x0 "FLEX_US_IF,USART IrDA Filter Register"
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hexmask.long.byte 0x0 0.--7. 1. "IRDA_FILTER,IrDA Filter"
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line.long 0x4 "FLEX_US_MAN,USART Manchester Configuration Register"
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bitfld.long 0x4 31. "RXIDLEV,Receiver Idle Value" "0: Receiver line idle value is 0.,1: Receiver line idle value is 1."
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newline
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bitfld.long 0x4 30. "DRIFT,Drift Compensation" "0: The USART cannot recover from an important clock..,1: The USART can recover from clock drift. The 16X.."
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newline
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bitfld.long 0x4 29. "ONE,Must Be Set to 1" "0,1"
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newline
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bitfld.long 0x4 28. "RX_MPOL,Receiver Manchester Polarity" "0: Logic zero is coded as a zero-to-one transition..,1: Logic zero is coded as a one-to-zero transition.."
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bitfld.long 0x4 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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hexmask.long.byte 0x4 16.--19. 1. "RX_PL,Receiver Preamble Length"
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bitfld.long 0x4 12. "TX_MPOL,Transmitter Manchester Polarity" "0: Logic zero is coded as a zero-to-one transition..,1: Logic zero is coded as a one-to-zero transition.."
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bitfld.long 0x4 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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hexmask.long.byte 0x4 0.--3. 1. "TX_PL,Transmitter Preamble Length"
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line.long 0x8 "FLEX_US_LINMR,USART LIN Mode Register"
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bitfld.long 0x8 17. "SYNCDIS,Synchronization Disable" "0: The synchronization procedure is performed in..,1: The synchronization procedure is not performed.."
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bitfld.long 0x8 16. "PDCM,DMAC Mode" "0: The LIN mode register FLEX_US_LINMR is not..,1: The LIN mode register FLEX_US_LINMR (excepting.."
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hexmask.long.byte 0x8 8.--15. 1. "DLC,Data Length Control"
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bitfld.long 0x8 7. "WKUPTYP,Wakeup Signal Type" "0: Setting the LINWKUP bit in the control register..,1: Setting the LINWKUP bit in the control register.."
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bitfld.long 0x8 6. "FSDIS,Frame Slot Mode Disable" "0: The Frame Slot mode is enabled.,1: The Frame Slot mode is disabled."
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bitfld.long 0x8 5. "DLM,Data Length Mode" "0: The response data length is defined by the DLC..,1: The response data length is defined by the bits.."
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bitfld.long 0x8 4. "CHKTYP,Checksum Type" "0: LIN 2.0 'enhanced' checksum,1: LIN 1.3 'classic' checksum"
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bitfld.long 0x8 3. "CHKDIS,Checksum Disable" "0: In master node configuration the checksum is..,1: Whatever the node configuration is the checksum.."
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bitfld.long 0x8 2. "PARDIS,Parity Disable" "0: In master node configuration the identifier..,1: Whatever the node configuration is the.."
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bitfld.long 0x8 0.--1. "NACT,LIN Node Action" "0: The USART transmits the response.,1: The USART receives the response.,2: The USART does not transmit and does not receive..,?"
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line.long 0xC "FLEX_US_LINIR,USART LIN Identifier Register"
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hexmask.long.byte 0xC 0.--7. 1. "IDCHR,Identifier Character"
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rgroup.long 0x25C++0x3
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line.long 0x0 "FLEX_US_LINBRR,USART LIN Baud Rate Register"
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bitfld.long 0x0 16.--18. "LINFP,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x0 0.--15. 1. "LINCD,Clock Divider after Synchronization"
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group.long 0x290++0x3
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line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
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hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
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bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0: The parity is not checked and a bad parity..,1: The parity is checked and a matching condition.."
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bitfld.long 0x0 12.--13. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start..,2: Comparison must be met to receive the current..,?"
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hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
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group.long 0x2A0++0x3
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line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
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hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
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hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
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bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0: RTS pin is not controlled by Receive FIFO..,1: RTS pin is controlled by Receive FIFO thresholds."
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bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x2A4++0x3
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line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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wgroup.long 0x2A8++0x7
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line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
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bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
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rgroup.long 0x2B0++0x7
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line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
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bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Number of unread data in Receive FIFO is above..,1: Number of unread data in Receive FIFO has.."
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bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0: The Transmit FIFO is not locked.,1: The Transmit FIFO is locked."
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bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0: No Receive FIFO pointer occurred,1: Receive FIFO pointer error occurred. Receiver.."
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bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0: No Transmit FIFO pointer occurred,1: Transmit FIFO pointer error occurred."
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bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Number of unread data in Receive FIFO is below..,1: Number of unread data in Receive FIFO has.."
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bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Receive FIFO is not empty.,1: Receive FIFO has been filled since the last.."
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bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Receive FIFO is not empty.,1: Receive FIFO has been emptied since the last.."
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bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Number of data in Transmit FIFO is above..,1: Number of data in Transmit FIFO has reached.."
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bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Transmit FIFO is not full.,1: Transmit FIFO has been filled since the last.."
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bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Transmit FIFO is not empty.,1: Transmit FIFO has been emptied since the last.."
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group.long 0x2E4++0x3
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line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection on configuration..,1: Enables the write protection on configuration.."
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rgroup.long 0x2E8++0x3
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line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
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hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
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wgroup.long 0x400++0x3
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line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
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bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0: No effect.,1: Disables the Transmit and Receive FIFOs"
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0: No effect.,1: Enables the Transmit and Receive FIFOs"
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bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0: No effect.,1: The current NPCS will be de-asserted after the.."
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bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0: No effect.,1: Empties the Receive FIFO."
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bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0: No effect.,1: Empties the Transmit FIFO."
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bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0: No effect.,1: Restarts the comparison trigger to enable.."
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bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0: No effect.,1: Reset the SPI. A software-triggered hardware.."
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bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0: No effect.,1: Disables the SPI."
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bitfld.long 0x0 0. "SPIEN,SPI Enable" "0: No effect.,1: Enables the SPI to transfer and receive data."
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group.long 0x404++0x3
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line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
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hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
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bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0: Local loopback path disabled.,1: Local loopback path enabled."
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bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0: No Effect. In Master mode a transfer can be..,1: In Master mode a transfer can start only if.."
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bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0: Mode fault detection is enabled.,1: Mode fault detection is disabled."
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bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
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bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0: The chip selects are directly connected to a..,1: The four NPCS chip select lines are connected to.."
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bitfld.long 0x0 1. "PS,Peripheral Select" "0: Fixed Peripheral Select,1: Variable Peripheral Select"
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bitfld.long 0x0 0. "MSTR,Master/Slave Mode" "0: SPI is in Slave mode.,1: SPI is in Master mode."
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rgroup.long 0x408++0x3
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line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
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rgroup.long 0x408++0x3
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line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
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hexmask.long.word 0x0 16.--31. 1. "RD1,Receive Data"
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hexmask.long.word 0x0 0.--15. 1. "RD0,Receive Data"
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rgroup.long 0x408++0x3
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line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
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hexmask.long.byte 0x0 24.--31. 1. "RD3,Receive Data"
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hexmask.long.byte 0x0 16.--23. 1. "RD2,Receive Data"
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hexmask.long.byte 0x0 8.--15. 1. "RD1,Receive Data"
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hexmask.long.byte 0x0 0.--7. 1. "RD0,Receive Data"
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wgroup.long 0x40C++0x3
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line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
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bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0: No effect.,1: The current NPCS is de-asserted after the.."
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
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wgroup.long 0x40C++0x3
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line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
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hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
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hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
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rgroup.long 0x410++0x3
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line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
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bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0: No Receive FIFO pointer occurred,1: Receive FIFO pointer error occurred. Receiver.."
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bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0: No Transmit FIFO pointer occurred,1: Transmit FIFO pointer error occurred."
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bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0: Number of unread data in Receive FIFO is below..,1: Number of unread data in Receive FIFO has.."
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bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0: Receive FIFO is not empty or RXFE flag has been..,1: Receive FIFO has been filled (changing states.."
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bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0: Receive FIFO is not empty or RXFE flag has been..,1: Receive FIFO has been emptied (changing states.."
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bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0: Number of data in Transmit FIFO is above..,1: Number of data in Transmit FIFO has reached.."
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bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0: Transmit FIFO is not full or TXFF flag has been..,1: Transmit FIFO has been filled since the last.."
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bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0: Transmit FIFO is not empty.,1: Transmit FIFO has been emptied since the last.."
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bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0: SPI is disabled.,1: SPI is enabled."
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bitfld.long 0x0 12. "SFERR,Slave Frame Error (cleared on read)" "0: There is no frame error detected for a slave..,1: In Slave mode the chip select raised while the.."
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bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0: No received character matched the comparison..,1: A received character matched the comparison.."
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bitfld.long 0x0 10. "UNDES,Underrun Error Status (Slave mode only) (cleared on read)" "0: No underrun has been detected since the last..,1: A transfer starts whereas no data has been.."
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0: As soon as data is written in FLEX_SPI_TDR.,1: FLEX_SPI_TDR and internal shift register are.."
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bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0: No rising edge detected on NSS pin since the..,1: A rising edge occurred on NSS pin since the last.."
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bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0: No overrun has been detected since the last read..,1: An overrun has occurred since the last read of.."
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bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0: No mode fault has been detected since the last..,1: A mode fault occurred since the last read of.."
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bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0: Transmit FIFO cannot accept more data.,1: Transmit FIFO can accept data; one or more data.."
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0: Receive FIFO is empty; no data to read,1: At least one unread data is in the Receive FIFO"
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wgroup.long 0x414++0x7
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line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
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bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
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bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
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newline
|
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bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
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bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
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newline
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bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
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rgroup.long 0x41C++0x3
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line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
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bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
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newline
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bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
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repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
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group.long ($2+0x430)++0x3
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line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register x"
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hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
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newline
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hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
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newline
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bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0: The Peripheral Chip Select Line rises as soon as..,1: The Peripheral Chip Select does not rise after.."
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newline
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bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0: The Peripheral Chip Select does not rise between..,1: The Peripheral Chip Select rises systematically.."
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newline
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bitfld.long 0x0 1. "NCPHA,Clock Phase" "0: Data are changed on the leading edge of SPCK and..,1: Data are captured on the leading edge of SPCK.."
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newline
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bitfld.long 0x0 0. "CPOL,Clock Polarity" "0: The inactive state value of SPCK is logic level..,1: The inactive state value of SPCK is logic level.."
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repeat.end
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group.long 0x440++0x3
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line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
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newline
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hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
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newline
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bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
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newline
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bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
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rgroup.long 0x444++0x3
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line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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newline
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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group.long 0x448++0x3
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line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
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hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
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newline
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hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
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group.long 0x4E4++0x3
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line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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newline
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
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|
newline
|
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
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newline
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
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rgroup.long 0x4E8++0x3
|
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line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
|
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hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
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newline
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0: No write protect violation has occurred since..,1: A write protect violation has occurred since the.."
|
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wgroup.long 0x600++0x3
|
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line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
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bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0: No effect.,1: Disable the Transmit and Receive FIFOs"
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newline
|
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bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0: No effect.,1: Enable the Transmit and Receive FIFOs"
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newline
|
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bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0: No effect.,1: Clear the TWI FSM lock."
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newline
|
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bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0: No effect.,1: Clear the Transmit Holding Register and set.."
|
|
newline
|
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bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0: No effect.,1: Alternative Command mode disabled."
|
|
newline
|
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bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0: No effect.,1: Alternative Command mode enabled."
|
|
newline
|
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bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0: No effect.,1: If Master mode is enabled send a bus clear.."
|
|
newline
|
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bitfld.long 0x0 14. "PECRQ,PEC Request" "0: No effect.,1: A PEC check or transmission is requested."
|
|
newline
|
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bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0: No effect.,1: SMBus PEC (CRC) generation and check disabled."
|
|
newline
|
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bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0: No effect.,1: SMBus PEC (CRC) generation and check enabled."
|
|
newline
|
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bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0: No effect.,1: SMBus mode disabled."
|
|
newline
|
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bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0: No effect.,1: If SMBDIS = 0 SMBus mode enabled."
|
|
newline
|
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bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0: No effect.,1: High-speed mode disabled."
|
|
newline
|
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bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0: No effect.,1: High-speed mode enabled."
|
|
newline
|
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bitfld.long 0x0 7. "SWRST,Software Reset" "0: No effect.,1: Equivalent to a system reset."
|
|
newline
|
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bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0: No effect.,1: If Master mode is enabled a SMBus Quick Command.."
|
|
newline
|
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bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0: No effect.,1: The Slave mode is disabled. The shifter and.."
|
|
newline
|
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bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0: No effect.,1: Enables the Slave mode (SVDIS must be written to.."
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0: No effect.,1: The Master mode is disabled all pending data is.."
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0: No effect.,1: Enables the Master mode (MSDIS must be written.."
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0: No effect.,1: STOP condition is sent just after completing the.."
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0: No effect.,1: A frame beginning with a START bit is.."
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0: No effect.,1: Disable the Transmit and Receive FIFOs."
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0: No effect.,1: Enable the Transmit and Receive FIFOs."
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0: No effect.,1: Clears the Transmit FIFO Lock."
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0: No effect.,1: Empties the Receive FIFO."
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0: No effect.,1: Empties the Transmit FIFO."
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0: No effect.,1: Alternative Command mode disabled."
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0: No effect.,1: Alternative Command mode enabled."
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0: No effect.,1: If Master mode is enabled send a bus clear.."
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0: No effect.,1: A PEC check or transmission is requested."
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0: No effect.,1: SMBus PEC (CRC) generation and check disabled."
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0: No effect.,1: SMBus PEC (CRC) generation and check enabled."
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0: No effect.,1: SMBus mode disabled."
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0: No effect.,1: If SMBDIS = 0 SMBus mode enabled."
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0: No effect.,1: High-speed mode disabled."
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0: No effect.,1: High-speed mode enabled."
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0: No effect.,1: Equivalent to a system reset."
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0: No effect.,1: If Master mode is enabled a SMBus Quick Command.."
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0: No effect.,1: The Slave mode is disabled. The shifter and.."
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0: No effect.,1: Enables the Slave mode (SVDIS must be written to.."
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0: No effect.,1: The Master mode is disabled all pending data is.."
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0: No effect.,1: Enables the Master mode (MSDIS must be written.."
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0: No effect.,1: STOP condition is sent just after completing the.."
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0: No effect.,1: A frame beginning with a START bit is.."
|
|
group.long 0x604++0xF
|
|
line.long 0x0 "FLEX_TWI_MMR,TWI Master Mode Register"
|
|
bitfld.long 0x0 24. "NOAP,No Auto-Stop On NACK Error" "0: A stop condition is sent automatically upon..,1: No automatic action is performed upon.."
|
|
newline
|
|
hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
|
|
newline
|
|
bitfld.long 0x0 13.--14. "SCLRBL,SCL Rise Boost Level" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 12. "MREAD,Master Read Direction" "0: Master write direction.,1: Master read direction."
|
|
newline
|
|
bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
|
|
line.long 0x4 "FLEX_TWI_SMR,TWI Slave Mode Register"
|
|
bitfld.long 0x4 31. "DATAMEN,Data Matching Enable" "0: Data matching on first received data is disabled.,1: Data matching on first received data is enabled."
|
|
newline
|
|
bitfld.long 0x4 30. "SADR3EN,Slave Address 3 Enable" "0: Slave address 3 matching is disabled.,1: Slave address 3 matching is enabled."
|
|
newline
|
|
bitfld.long 0x4 29. "SADR2EN,Slave Address 2 Enable" "0: Slave address 2 matching is disabled.,1: Slave address 2 matching is enabled."
|
|
newline
|
|
bitfld.long 0x4 28. "SADR1EN,Slave Address 1 Enable" "0: Slave address 1 matching is disabled.,1: Slave address 1 matching is enabled."
|
|
newline
|
|
hexmask.long.byte 0x4 16.--22. 1. "SADR,Slave Address"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--14. 1. "MASK,Slave Address Mask"
|
|
newline
|
|
bitfld.long 0x4 7. "SNIFF,Slave Sniffer Mode" "0: Slave Sniffer mode is disabled.,1: Slave Sniffer mode is enabled."
|
|
newline
|
|
bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0: No effect.,1: Clock stretching disabled in Slave mode OVRE and.."
|
|
newline
|
|
bitfld.long 0x4 5. "BSEL,TWI Bus Selection" "0: TWI analyzes the TWCK and TWD pins from its TWI..,1: TWI analyzes the TWCK pins TWD from consecutive.."
|
|
newline
|
|
bitfld.long 0x4 4. "SADAT,Slave Address Treated as Data" "0: Slave address is handled normally (will not trig..,1: Slave address is handled as data field RXRDY.."
|
|
newline
|
|
bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0: Acknowledge of the SMBus Host Header disabled.,1: Acknowledge of the SMBus Host Header enabled."
|
|
newline
|
|
bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0: Acknowledge of the SMBus Default Address disabled.,1: Acknowledge of the SMBus Default Address enabled."
|
|
newline
|
|
bitfld.long 0x4 0. "NACKEN,Slave Receiver Data Phase NACK Enable" "0: Normal value to be returned in the ACK cycle of..,1: NACK value to be returned in the ACK cycle of.."
|
|
line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
|
|
line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
hexmask.long.byte 0xC 24.--29. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
|
|
newline
|
|
bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0: No repeated start has been detected since last..,1: At least one repeated start has been detected.."
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0: SDA line sampled value is '0'.,1: SDA line sampled value is '1'."
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0: SCL line sampled value is '0'.,1: SCL line sampled value is '1.'"
|
|
newline
|
|
bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0: The TWI is not locked.,1: The TWI is locked due to frame errors (see.."
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0: No SMBus Host Header Address received.,1: A SMBus Host Header Address was received."
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0: No SMBus Default Address received.,1: A SMBus Default Address was received."
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0: No SMBus PEC error occurred.,1: A SMBus PEC error occurred."
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0: No SMBus timeout occurred.,1: SMBus timeout occurred."
|
|
newline
|
|
bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag" "0: No SMBus slave drives the SMBALERT line.,1: At least one SMBus slave drives the SMBALERT line."
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0: No master code has been received.,1: A master code has been received."
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0: A slave access is being performing.,1: The Slave Access is finished. End Of Slave.."
|
|
newline
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bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0: The clock is not stretched.,1: The clock is stretched. FLEX_TWI_THR /.."
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0: Arbitration won.,1: Arbitration lost. Another master of the TWI bus.."
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bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0: Each data byte has been correctly received by..,1: In Read mode a data byte has not been.."
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bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0: FLEX_TWI_THR has been filled on time.,1: FLEX_TWI_THR has not been filled on time."
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bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0: FLEX_TWI_RHR has not been loaded while RXRDY was..,1: FLEX_TWI_RHR has been loaded while RXRDY was.."
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bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0: No general call has been detected.,1: A general call has been detected. After the.."
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bitfld.long 0x0 4. "SVACC,Slave Access" "0: TWI is not addressed. SVACC is automatically..,1: Indicates that the address decoding sequence has.."
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bitfld.long 0x0 3. "SVREAD,Slave Read" "0: Indicates that a write access is performed by a..,1: Indicates that a read access is performed by a.."
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0: Transmit FIFO is full and cannot accept more data,1: Transmit FIFO is not full; one or more data can.."
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0: Receive FIFO is empty; no data to read,1: At least one unread data is in the Receive FIFO"
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0: As soon as a Start is detected.,1: After a Stop or a Repeated Start + an address.."
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rgroup.long 0x620++0x3
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line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
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bitfld.long 0x0 26. "SR,Start Repeated" "0: No repeated start has been detected since last..,1: At least one repeated start has been detected.."
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bitfld.long 0x0 25. "SDA,SDA Line Value" "0: SDA line sampled value is '0'.,1: SDA line sampled value is '1'."
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bitfld.long 0x0 24. "SCL,SCL Line Value" "0: SCL line sampled value is '0'.,1: SCL line sampled value is '1.'"
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bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0: The Transmit FIFO is not locked.,1: The Transmit FIFO is locked."
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0: No SMBus Host Header Address received.,1: A SMBus Host Header Address was received."
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0: No SMBus Default Address received.,1: A SMBus Default Address was received."
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bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0: No SMBus PEC error occurred.,1: A SMBus PEC error occurred."
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bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0: No SMBus timeout occurred.,1: SMBus timeout occurred."
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bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag" "0: No SMBus slave drives the SMBALERT line.,1: At least one SMBus slave drives the SMBALERT line."
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0: No master code has been received.,1: A master code has been received."
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0: A slave access is being performing.,1: The Slave Access is finished. End Of Slave.."
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bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0: The clock is not stretched.,1: The clock is stretched. FLEX_TWI_THR /.."
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0: Arbitration won.,1: Arbitration lost. Another master of the TWI bus.."
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bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0: Each data byte has been correctly received by..,1: In Read mode a data byte has not been.."
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bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0: FLEX_TWI_THR has been filled on time.,1: FLEX_TWI_THR has not been filled on time."
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bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0: FLEX_TWI_RHR has not been loaded while RXRDY was..,1: FLEX_TWI_RHR has been loaded while RXRDY was.."
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bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0: No general call has been detected.,1: A general call has been detected. After the.."
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bitfld.long 0x0 4. "SVACC,Slave Access" "0: TWI is not addressed. SVACC is automatically..,1: Indicates that the address decoding sequence has.."
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bitfld.long 0x0 3. "SVREAD,Slave Read" "0: Indicates that a write access is performed by a..,1: Indicates that a read access is performed by a.."
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0: Transmit FIFO is full and cannot accept more data.,1: Transmit FIFO is not full; one or more data can.."
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0: Receive FIFO is empty; no data to read.,1: At least one unread data is in the Receive FIFO."
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0: As soon as a Start is detected.,1: After a Stop or a Repeated Start + an address.."
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wgroup.long 0x624++0x7
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line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
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bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
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bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Enable" "0,1"
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bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
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bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
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bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
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bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Enable" "0,1"
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bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
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bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
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bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
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bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
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bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
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bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
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bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
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bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
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bitfld.long 0x4 16. "MCACK,Master Code Acknowledge Interrupt Disable" "0,1"
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bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
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bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
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bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
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bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
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bitfld.long 0x4 11. "EOSACC,End Of Slave Access Interrupt Disable" "0,1"
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bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
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bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
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bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
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bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
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bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
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bitfld.long 0x4 4. "SVACC,Slave Access Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
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rgroup.long 0x62C++0x7
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line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
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bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
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bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Mask" "0,1"
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bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
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bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
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bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
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bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Mask" "0,1"
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bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
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bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
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bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
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bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Mask" "0,1"
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
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bitfld.long 0x4 11.--12. "ASTATE,Acknowledge State (Slave Sniffer Mode only)" "0: No Acknowledge or Nacknowledge detected after..,1: Acknowledge (A) detected after previously logged..,2: Nacknowledge (NA) detected after previously..,3: Not defined"
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bitfld.long 0x4 10. "PSTATE,Stop State (Slave Sniffer Mode only)" "0: No STOP (P) detected after previous logged data.,1: Stop detected (P) after previous logged data."
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bitfld.long 0x4 8.--9. "SSTATE,Start State (Slave Sniffer Mode only)" "0: No START detected with the logged data,1: START (S) detected with the logged data,2: Repeated START (Sr) detected with the logged data,3: Not defined"
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hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Master or Slave Receive Holding Data"
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rgroup.long 0x630++0x3
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line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Master or Slave Receive Holding Data 3"
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hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Master or Slave Receive Holding Data 2"
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hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Master or Slave Receive Holding Data 1"
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hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Master or Slave Receive Holding Data 0"
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wgroup.long 0x634++0x3
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line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Master or Slave Transmit Holding Data"
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wgroup.long 0x634++0x3
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line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Master or Slave Transmit Holding Data 3"
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hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Master or Slave Transmit Holding Data 2"
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hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Master or Slave Transmit Holding Data 1"
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Master or Slave Transmit Holding Data 0"
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group.long 0x638++0x1B
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line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
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hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
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hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Master Clock Stretch Maximum Cycles"
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hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Slave Clock Stretch Maximum Cycles"
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hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
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line.long 0x4 "FLEX_TWI_HSR,TWI High Speed Register"
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hexmask.long.byte 0x4 0.--7. 1. "MCODE,TWI High Speed Master Code"
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line.long 0x8 "FLEX_TWI_ACR,TWI Alternative Command Register"
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bitfld.long 0x8 25. "NPEC,Next PEC Request (SMBus Mode only)" "0: The next transfer does not use a PEC byte.,1: The next transfer uses a PEC byte."
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bitfld.long 0x8 24. "NDIR,Next Transfer Direction" "0: Write direction.,1: Read direction."
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hexmask.long.byte 0x8 16.--23. 1. "NDATAL,Next Data Length"
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bitfld.long 0x8 9. "PEC,PEC Request (SMBus Mode only)" "0: The transfer does not use a PEC byte.,1: The transfer uses a PEC byte."
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bitfld.long 0x8 8. "DIR,Transfer Direction" "0: Write direction.,1: Read direction."
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hexmask.long.byte 0x8 0.--7. 1. "DATAL,Data Length"
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line.long 0xC "FLEX_TWI_FILTR,TWI Filter Register"
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bitfld.long 0xC 8.--10. "THRES,Digital Filter Threshold" "0: No filtering applied on TWI inputs.,?,?,?,?,?,?,?"
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bitfld.long 0xC 1. "PADFEN,PAD Filter Enable" "0: PAD analog filter is disabled.,1: PAD analog filter is enabled. (The analog filter.."
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bitfld.long 0xC 0. "FILT,RX Digital Filter" "0: No filtering applied on TWI inputs.,1: TWI input filtering is active. (Only in Standard.."
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line.long 0x10 "FLEX_TWI_HSCWGR,TWI High Speed Clock Waveform Generator Register"
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bitfld.long 0x10 16.--18. "HSCKDIV,High Speed Clock Divider" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x10 8.--15. 1. "HSCHDIV,High Speed Clock High Divider"
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hexmask.long.byte 0x10 0.--7. 1. "HSCLDIV,High Speed Clock Low Divider"
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line.long 0x14 "FLEX_TWI_SWMR,TWI Matching Register"
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hexmask.long.byte 0x14 24.--31. 1. "DATAM,Data Match"
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hexmask.long.byte 0x14 16.--22. 1. "SADR3,Slave Address 3"
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hexmask.long.byte 0x14 8.--14. 1. "SADR2,Slave Address 2"
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hexmask.long.byte 0x14 0.--6. 1. "SADR1,Slave Address 1"
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line.long 0x18 "FLEX_TWI_FMR,TWI FIFO Mode Register"
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hexmask.long.byte 0x18 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
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hexmask.long.byte 0x18 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
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bitfld.long 0x18 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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bitfld.long 0x18 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x654++0x3
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line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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rgroup.long 0x660++0x3
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line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
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bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0: No Receive FIFO pointer occurred,1: Receive FIFO pointer error occurred. Receiver.."
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bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0: No Transmit FIFO pointer occurred,1: Transmit FIFO pointer error occurred."
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bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0: Number of unread data in Receive FIFO is below..,1: Number of unread data in Receive FIFO has.."
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bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0: Receive FIFO is not empty.,1: Receive FIFO has been filled since the last read.."
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bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0: Receive FIFO is not empty.,1: Receive FIFO has been emptied since the last.."
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bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0: Number of data in Transmit FIFO is above..,1: Number of data in Transmit FIFO has reached.."
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bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0: Transmit FIFO is not full.,1: Transmit FIFO has been filled since the last.."
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bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0: Transmit FIFO is not empty.,1: Transmit FIFO has been emptied since the last.."
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wgroup.long 0x664++0x7
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line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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|
newline
|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
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|
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|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
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line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
|
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
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rgroup.long 0x66C++0x3
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line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
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group.long 0x6E4++0x3
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line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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newline
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
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newline
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
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newline
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
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rgroup.long 0x6E8++0x3
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line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
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newline
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bitfld.long 0x0 0. "WPVS,Write Protect Violation Status" "0: No Write Protection Violation has occurred since..,1: A Write Protection Violation has occurred since.."
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tree.end
|
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tree "FLEXCOM1"
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base ad:0xE181C000
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group.long 0x0++0x3
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line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
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bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected. USART/TWI..,3: All TWI related protocols are selected (TWI.."
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rgroup.long 0x10++0x3
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line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
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hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
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group.long 0x20++0x3
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line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
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wgroup.long 0x200++0x3
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line.long 0x0 "FLEX_US_CR,USART Control Register"
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bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0: No effect.,1: Disables the Transmit and Receive FIFOs."
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newline
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0: No effect.,1: Enables the Transmit and Receive FIFOs."
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newline
|
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bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0: No effect.,1: Restarts the comparison trigger to enable.."
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newline
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bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0: No effect.,1: Clears the Transmit FIFO Lock"
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newline
|
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bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0: No effect.,1: Empties the Receive FIFO."
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newline
|
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bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0: No effect.,1: Empties the Transmit FIFO."
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newline
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bitfld.long 0x0 21. "LINWKUP,Send LIN Wakeup Signal" "0: No effect:,1: Sends a wakeup signal on the LIN bus."
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newline
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bitfld.long 0x0 20. "LINABT,Abort LIN Transmission" "0: No effect.,1: Aborts the current LIN transmission."
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newline
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bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0: No effect.,1: Drives the RTS pin to 0 if FLEX_US_MR.USART_MODE.."
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newline
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bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0: No effect.,1: Drives the RTS pin to 1 if FLEX_US_MR.USART_MODE.."
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newline
|
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bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0: No effect,1: Immediately restarts timeout period."
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|
newline
|
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bitfld.long 0x0 14. "RSTNACK,Reset Non Acknowledge" "0: No effect,1: Resets FLEX_US_CSR.NACK."
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newline
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bitfld.long 0x0 13. "RSTIT,Reset Iterations" "0: No effect.,1: Resets FLEX_US_CSR.ITER. No effect if the.."
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newline
|
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bitfld.long 0x0 12. "SENDA,Send Address" "0: No effect.,1: In Multidrop mode only the next character.."
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newline
|
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bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0: No effect.,1: Starts waiting for a character before clocking.."
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newline
|
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bitfld.long 0x0 10. "STPBRK,Stop Break" "0: No effect.,1: Stops transmission of the break after a minimum.."
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newline
|
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bitfld.long 0x0 9. "STTBRK,Start Break" "0: No effect.,1: Starts transmission of a break after the.."
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newline
|
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bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0: No effect.,1: Resets the status bits PARE FRAME OVRE MANE.."
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|
newline
|
|
bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0: No effect.,1: Disables the transmitter."
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|
newline
|
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bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0: No effect.,1: Enables the transmitter if TXDIS is 0."
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|
newline
|
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bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0: No effect.,1: Disables the receiver."
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newline
|
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bitfld.long 0x0 4. "RXEN,Receiver Enable" "0: No effect.,1: Enables the receiver if RXDIS is 0."
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newline
|
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bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0: No effect.,1: Resets the transmitter."
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newline
|
|
bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0: No effect.,1: Resets the receiver."
|
|
group.long 0x204++0x3
|
|
line.long 0x0 "FLEX_US_MR,USART Mode Register"
|
|
bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0: Start frame delimiter is COMMAND or DATA SYNC.,1: Start frame delimiter is one bit."
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newline
|
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bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0: The Manchester start bit is a 0 to 1 transition,1: The Manchester start bit is a 1 to 0 transition."
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newline
|
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bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0: Manchester encoder/decoder are disabled.,1: Manchester encoder/decoder are enabled."
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newline
|
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bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0: The USART does not filter the receive line.,1: The USART filters the receive line using a.."
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newline
|
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bitfld.long 0x0 24.--26. "MAX_ITERATION,Maximum Number of Automatic Iteration" "0,1,2,3,4,5,6,7"
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newline
|
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bitfld.long 0x0 23. "INVDATA,Inverted Data" "0: The data field transmitted on TXD line is the..,1: The data field transmitted on TXD line is.."
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newline
|
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bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0: User defined configuration of command or data..,1: The sync field is updated when a character is.."
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newline
|
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bitfld.long 0x0 21. "DSNACK,Disable Successive NACK" "0: NACK is sent on the ISO line as soon as a parity..,1: Successive parity errors are counted up to the.."
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newline
|
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bitfld.long 0x0 20. "INACK,Inhibit Non Acknowledge" "0: The NACK is generated.,1: The NACK is not generated."
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newline
|
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bitfld.long 0x0 19. "OVER,Oversampling Mode" "0: 16x Oversampling.,1: 8x Oversampling."
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|
newline
|
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bitfld.long 0x0 18. "CLKO,Clock Output Select" "0: The USART does not drive the SCK pin..,1: The USART drives the SCK pin if USCLKS does not.."
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newline
|
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bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0: CHRL defines character length.,1: 9-bit character length."
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|
newline
|
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bitfld.long 0x0 16. "MSBF,Bit Order" "0: Least significant bit is sent/received first.,1: Most significant bit is sent/received first."
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|
newline
|
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bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
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newline
|
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bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
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|
newline
|
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bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
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newline
|
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bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0: USART operates in Asynchronous mode (UART).,1: USART operates in Synchronous mode."
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|
newline
|
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bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
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newline
|
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bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
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newline
|
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hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
|
|
wgroup.long 0x208++0x3
|
|
line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
|
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
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|
newline
|
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
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|
newline
|
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
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|
newline
|
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Enable" "0,1"
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|
newline
|
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bitfld.long 0x0 10. "ITER,Max number of Repetitions Reached Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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|
newline
|
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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|
newline
|
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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|
newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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|
newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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|
newline
|
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
wgroup.long 0x208++0x7
|
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line.long 0x0 "FLEX_US_IER_LIN_MODE,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Enable" "0,1"
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|
newline
|
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
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line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
|
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newline
|
|
bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
wgroup.long 0x20C++0x3
|
|
line.long 0x0 "FLEX_US_IDR_LIN_MODE,USART Interrupt Disable Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
rgroup.long 0x210++0x3
|
|
line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ITER,Max Number of Repetitions Reached Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
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newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
rgroup.long 0x210++0x7
|
|
line.long 0x0 "FLEX_US_IMR_LIN_MODE,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Mask" "0,1"
|
|
newline
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Mask" "0,1"
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Mask" "0,1"
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Mask" "0,1"
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Mask" "0,1"
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Mask" "0,1"
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Mask" "0,1"
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Mask" "0,1"
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "0,1"
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Mask" "0,1"
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
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bitfld.long 0x4 24. "MANE,Manchester Error" "0: No Manchester error has been detected since the..,1: At least one Manchester error has been detected.."
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bitfld.long 0x4 23. "CTS,Image of CTS Input" "0: CTS input is driven low.,1: CTS input is driven high."
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bitfld.long 0x4 22. "CMP,Comparison Status" "0: No received character matched the comparison..,1: A received character matched the comparison.."
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0: No input change has been detected on the CTS pin..,1: At least one input change has been detected on.."
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt" "0: Non acknowledge has not been detected since the..,1: At least one non acknowledge has been detected.."
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bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached" "0: Maximum number of repetitions has not been..,1: Maximum number of repetitions has been reached.."
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bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0: There are characters in either FLEX_US_THR or..,1: There are no characters in FLEX_US_THR nor in.."
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bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0: There has not been a timeout since the last..,1: There has been a timeout since the last Start.."
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bitfld.long 0x4 7. "PARE,Parity Error" "0: No parity error has been detected since the last..,1: At least one parity error has been detected.."
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bitfld.long 0x4 6. "FRAME,Framing Error" "0: No stop bit has been detected low since the last..,1: At least one stop bit has been detected low.."
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bitfld.long 0x4 5. "OVRE,Overrun Error" "0: No overrun error has occurred since the last..,1: At least one overrun error has occurred since.."
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bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0: No break received or end of break detected since..,1: Break received or end of break detected since.."
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bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0: Transmit FIFO is full and cannot accept more data,1: Transmit FIFO is not full; one or more data can.."
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bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0: Receive FIFO is empty; no data to read,1: At least one unread data is in the Receive FIFO"
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rgroup.long 0x214++0x7
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line.long 0x0 "FLEX_US_CSR_LIN_MODE,USART Channel Status Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error" "0: No LIN header timeout error has been detected..,1: A LIN header timeout error has been detected.."
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error" "0: No LIN synch tolerance error has been detected..,1: A LIN synch tolerance error has been detected.."
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error" "0: No LIN slave not responding error has been..,1: A LIN slave not responding error has been.."
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error" "0: No LIN checksum error has been detected since..,1: A LIN checksum error has been detected since the.."
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Error" "0: No LIN identifier parity error has been detected..,1: A LIN identifier parity error has been detected.."
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error" "0: No LIN inconsistent synch field error has been..,1: The USART is configured as a slave node and a.."
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bitfld.long 0x0 25. "LINBE,LIN Bit Error" "0: No bit error has been detected since the last..,1: A bit error has been detected since the last.."
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bitfld.long 0x0 23. "LINBLS,LIN Bus Line Status" "0: LIN bus line is set to 0.,1: LIN bus line is set to 1."
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed" "0: The USART is idle or a LIN transfer is ongoing.,1: A LIN transfer has been completed since the last.."
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received" "0: No LIN identifier has been received since the..,1: At least one LIN identifier has been received.."
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received" "0: No LIN break has received sent since the last..,1: At least one LIN break has been received since.."
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bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0: There are characters in either FLEX_US_THR or..,1: There are no characters in FLEX_US_THR nor in.."
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bitfld.long 0x0 8. "TIMEOUT,Receiver Timeout" "0: There has not been a timeout since the last..,1: There has been a timeout since the last start.."
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bitfld.long 0x0 7. "PARE,Parity Error" "0: No parity error has been detected since the last..,1: At least one parity error has been detected.."
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bitfld.long 0x0 6. "FRAME,Framing Error" "0: No stop bit has been detected low since the last..,1: At least one stop bit has been detected low.."
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bitfld.long 0x0 5. "OVRE,Overrun Error" "0: No overrun error has occurred since the last..,1: At least one overrun error has occurred since.."
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bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0: A character in FLEX_US_THR is waiting to be..,1: There is no character in FLEX_US_THR."
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bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0: No complete character has been received since..,1: At least one complete character has been.."
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line.long 0x4 "FLEX_US_RHR,USART Receive Holding Register"
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bitfld.long 0x4 15. "RXSYNH,Received Sync" "0: Last character received is a data.,1: Last character received is a command."
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hexmask.long.word 0x4 0.--8. 1. "RXCHR,Received Character"
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rgroup.long 0x218++0x3
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line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Characters"
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hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Characters"
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hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Characters"
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hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Characters"
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wgroup.long 0x21C++0x3
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line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
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bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0: The next character sent is encoded as a data.,1: The next character sent is encoded as a command."
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hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
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wgroup.long 0x21C++0x3
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line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
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hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
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hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
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hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
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group.long 0x220++0xB
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line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
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bitfld.long 0x0 16.--18. "FP,Fractional Part" "0: Fractional divider is disabled.,?,?,?,?,?,?,?"
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hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
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line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
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hexmask.long.tbyte 0x4 0.--16. 1. "TO,Timeout Value"
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line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
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hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
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group.long 0x240++0x3
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line.long 0x0 "FLEX_US_FIDI,USART FI DI Ratio Register"
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hexmask.long.word 0x0 0.--15. 1. "FI_DI_RATIO,FI Over DI Ratio Value"
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rgroup.long 0x244++0x3
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line.long 0x0 "FLEX_US_NER,USART Number of Errors Register"
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hexmask.long.byte 0x0 0.--7. 1. "NB_ERRORS,Number of Errors"
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group.long 0x24C++0xF
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line.long 0x0 "FLEX_US_IF,USART IrDA Filter Register"
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hexmask.long.byte 0x0 0.--7. 1. "IRDA_FILTER,IrDA Filter"
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line.long 0x4 "FLEX_US_MAN,USART Manchester Configuration Register"
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bitfld.long 0x4 31. "RXIDLEV,Receiver Idle Value" "0: Receiver line idle value is 0.,1: Receiver line idle value is 1."
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bitfld.long 0x4 30. "DRIFT,Drift Compensation" "0: The USART cannot recover from an important clock..,1: The USART can recover from clock drift. The 16X.."
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bitfld.long 0x4 29. "ONE,Must Be Set to 1" "0,1"
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bitfld.long 0x4 28. "RX_MPOL,Receiver Manchester Polarity" "0: Logic zero is coded as a zero-to-one transition..,1: Logic zero is coded as a one-to-zero transition.."
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bitfld.long 0x4 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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hexmask.long.byte 0x4 16.--19. 1. "RX_PL,Receiver Preamble Length"
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bitfld.long 0x4 12. "TX_MPOL,Transmitter Manchester Polarity" "0: Logic zero is coded as a zero-to-one transition..,1: Logic zero is coded as a one-to-zero transition.."
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bitfld.long 0x4 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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hexmask.long.byte 0x4 0.--3. 1. "TX_PL,Transmitter Preamble Length"
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line.long 0x8 "FLEX_US_LINMR,USART LIN Mode Register"
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bitfld.long 0x8 17. "SYNCDIS,Synchronization Disable" "0: The synchronization procedure is performed in..,1: The synchronization procedure is not performed.."
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bitfld.long 0x8 16. "PDCM,DMAC Mode" "0: The LIN mode register FLEX_US_LINMR is not..,1: The LIN mode register FLEX_US_LINMR (excepting.."
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hexmask.long.byte 0x8 8.--15. 1. "DLC,Data Length Control"
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bitfld.long 0x8 7. "WKUPTYP,Wakeup Signal Type" "0: Setting the LINWKUP bit in the control register..,1: Setting the LINWKUP bit in the control register.."
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bitfld.long 0x8 6. "FSDIS,Frame Slot Mode Disable" "0: The Frame Slot mode is enabled.,1: The Frame Slot mode is disabled."
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bitfld.long 0x8 5. "DLM,Data Length Mode" "0: The response data length is defined by the DLC..,1: The response data length is defined by the bits.."
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bitfld.long 0x8 4. "CHKTYP,Checksum Type" "0: LIN 2.0 'enhanced' checksum,1: LIN 1.3 'classic' checksum"
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bitfld.long 0x8 3. "CHKDIS,Checksum Disable" "0: In master node configuration the checksum is..,1: Whatever the node configuration is the checksum.."
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bitfld.long 0x8 2. "PARDIS,Parity Disable" "0: In master node configuration the identifier..,1: Whatever the node configuration is the.."
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bitfld.long 0x8 0.--1. "NACT,LIN Node Action" "0: The USART transmits the response.,1: The USART receives the response.,2: The USART does not transmit and does not receive..,?"
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line.long 0xC "FLEX_US_LINIR,USART LIN Identifier Register"
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hexmask.long.byte 0xC 0.--7. 1. "IDCHR,Identifier Character"
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rgroup.long 0x25C++0x3
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line.long 0x0 "FLEX_US_LINBRR,USART LIN Baud Rate Register"
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bitfld.long 0x0 16.--18. "LINFP,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x0 0.--15. 1. "LINCD,Clock Divider after Synchronization"
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group.long 0x290++0x3
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line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
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hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
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bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0: The parity is not checked and a bad parity..,1: The parity is checked and a matching condition.."
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bitfld.long 0x0 12.--13. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start..,2: Comparison must be met to receive the current..,?"
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hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
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group.long 0x2A0++0x3
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line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
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hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
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hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
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bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0: RTS pin is not controlled by Receive FIFO..,1: RTS pin is controlled by Receive FIFO thresholds."
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bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x2A4++0x3
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line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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wgroup.long 0x2A8++0x7
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line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
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bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
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rgroup.long 0x2B0++0x7
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line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
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bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Number of unread data in Receive FIFO is above..,1: Number of unread data in Receive FIFO has.."
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bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0: The Transmit FIFO is not locked.,1: The Transmit FIFO is locked."
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bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0: No Receive FIFO pointer occurred,1: Receive FIFO pointer error occurred. Receiver.."
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bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0: No Transmit FIFO pointer occurred,1: Transmit FIFO pointer error occurred."
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bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Number of unread data in Receive FIFO is below..,1: Number of unread data in Receive FIFO has.."
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bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Receive FIFO is not empty.,1: Receive FIFO has been filled since the last.."
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newline
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bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Receive FIFO is not empty.,1: Receive FIFO has been emptied since the last.."
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newline
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bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Number of data in Transmit FIFO is above..,1: Number of data in Transmit FIFO has reached.."
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newline
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bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Transmit FIFO is not full.,1: Transmit FIFO has been filled since the last.."
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newline
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bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Transmit FIFO is not empty.,1: Transmit FIFO has been emptied since the last.."
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group.long 0x2E4++0x3
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line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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newline
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
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newline
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
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newline
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection on configuration..,1: Enables the write protection on configuration.."
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rgroup.long 0x2E8++0x3
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line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
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hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
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newline
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
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wgroup.long 0x400++0x3
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line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
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bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0: No effect.,1: Disables the Transmit and Receive FIFOs"
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newline
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0: No effect.,1: Enables the Transmit and Receive FIFOs"
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newline
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bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0: No effect.,1: The current NPCS will be de-asserted after the.."
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newline
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bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0: No effect.,1: Empties the Receive FIFO."
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newline
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bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0: No effect.,1: Empties the Transmit FIFO."
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newline
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bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0: No effect.,1: Restarts the comparison trigger to enable.."
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newline
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bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0: No effect.,1: Reset the SPI. A software-triggered hardware.."
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newline
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bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0: No effect.,1: Disables the SPI."
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newline
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bitfld.long 0x0 0. "SPIEN,SPI Enable" "0: No effect.,1: Enables the SPI to transfer and receive data."
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group.long 0x404++0x3
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line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
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hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
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newline
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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newline
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bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
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newline
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bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0: Local loopback path disabled.,1: Local loopback path enabled."
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newline
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bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0: No Effect. In Master mode a transfer can be..,1: In Master mode a transfer can start only if.."
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newline
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bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0: Mode fault detection is enabled.,1: Mode fault detection is disabled."
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newline
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bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
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newline
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bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0: The chip selects are directly connected to a..,1: The four NPCS chip select lines are connected to.."
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newline
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bitfld.long 0x0 1. "PS,Peripheral Select" "0: Fixed Peripheral Select,1: Variable Peripheral Select"
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newline
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bitfld.long 0x0 0. "MSTR,Master/Slave Mode" "0: SPI is in Slave mode.,1: SPI is in Master mode."
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rgroup.long 0x408++0x3
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line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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newline
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hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
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rgroup.long 0x408++0x3
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line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
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hexmask.long.word 0x0 16.--31. 1. "RD1,Receive Data"
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newline
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hexmask.long.word 0x0 0.--15. 1. "RD0,Receive Data"
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rgroup.long 0x408++0x3
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line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
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hexmask.long.byte 0x0 24.--31. 1. "RD3,Receive Data"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "RD2,Receive Data"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "RD1,Receive Data"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "RD0,Receive Data"
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wgroup.long 0x40C++0x3
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line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
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bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0: No effect.,1: The current NPCS is de-asserted after the.."
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newline
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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newline
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hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
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wgroup.long 0x40C++0x3
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line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
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hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
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newline
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hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
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rgroup.long 0x410++0x3
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line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
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bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0: No Receive FIFO pointer occurred,1: Receive FIFO pointer error occurred. Receiver.."
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newline
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bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0: No Transmit FIFO pointer occurred,1: Transmit FIFO pointer error occurred."
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newline
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bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0: Number of unread data in Receive FIFO is below..,1: Number of unread data in Receive FIFO has.."
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newline
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bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0: Receive FIFO is not empty or RXFE flag has been..,1: Receive FIFO has been filled (changing states.."
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newline
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bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0: Receive FIFO is not empty or RXFE flag has been..,1: Receive FIFO has been emptied (changing states.."
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newline
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bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0: Number of data in Transmit FIFO is above..,1: Number of data in Transmit FIFO has reached.."
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newline
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bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0: Transmit FIFO is not full or TXFF flag has been..,1: Transmit FIFO has been filled since the last.."
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newline
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bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0: Transmit FIFO is not empty.,1: Transmit FIFO has been emptied since the last.."
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newline
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bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0: SPI is disabled.,1: SPI is enabled."
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newline
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bitfld.long 0x0 12. "SFERR,Slave Frame Error (cleared on read)" "0: There is no frame error detected for a slave..,1: In Slave mode the chip select raised while the.."
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newline
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bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0: No received character matched the comparison..,1: A received character matched the comparison.."
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newline
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bitfld.long 0x0 10. "UNDES,Underrun Error Status (Slave mode only) (cleared on read)" "0: No underrun has been detected since the last..,1: A transfer starts whereas no data has been.."
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newline
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0: As soon as data is written in FLEX_SPI_TDR.,1: FLEX_SPI_TDR and internal shift register are.."
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newline
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bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0: No rising edge detected on NSS pin since the..,1: A rising edge occurred on NSS pin since the last.."
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newline
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bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0: No overrun has been detected since the last read..,1: An overrun has occurred since the last read of.."
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newline
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bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0: No mode fault has been detected since the last..,1: A mode fault occurred since the last read of.."
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newline
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bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0: Transmit FIFO cannot accept more data.,1: Transmit FIFO can accept data; one or more data.."
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newline
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0: Receive FIFO is empty; no data to read,1: At least one unread data is in the Receive FIFO"
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wgroup.long 0x414++0x7
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line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
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bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
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newline
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bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
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bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
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newline
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bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
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rgroup.long 0x41C++0x3
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line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
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bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
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newline
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bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
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repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
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group.long ($2+0x430)++0x3
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line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register x"
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hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
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newline
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hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
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newline
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bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0: The Peripheral Chip Select Line rises as soon as..,1: The Peripheral Chip Select does not rise after.."
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newline
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bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0: The Peripheral Chip Select does not rise between..,1: The Peripheral Chip Select rises systematically.."
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newline
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bitfld.long 0x0 1. "NCPHA,Clock Phase" "0: Data are changed on the leading edge of SPCK and..,1: Data are captured on the leading edge of SPCK.."
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newline
|
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bitfld.long 0x0 0. "CPOL,Clock Polarity" "0: The inactive state value of SPCK is logic level..,1: The inactive state value of SPCK is logic level.."
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repeat.end
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group.long 0x440++0x3
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line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
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newline
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hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
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newline
|
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bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
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newline
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bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
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rgroup.long 0x444++0x3
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line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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newline
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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group.long 0x448++0x3
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line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
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hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
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newline
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hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
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group.long 0x4E4++0x3
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line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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newline
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
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newline
|
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
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newline
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
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rgroup.long 0x4E8++0x3
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line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
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|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0: No write protect violation has occurred since..,1: A write protect violation has occurred since the.."
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wgroup.long 0x600++0x3
|
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line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0: No effect.,1: Disable the Transmit and Receive FIFOs"
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newline
|
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bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0: No effect.,1: Enable the Transmit and Receive FIFOs"
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newline
|
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bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0: No effect.,1: Clear the TWI FSM lock."
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newline
|
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bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0: No effect.,1: Clear the Transmit Holding Register and set.."
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newline
|
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bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0: No effect.,1: Alternative Command mode disabled."
|
|
newline
|
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bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0: No effect.,1: Alternative Command mode enabled."
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newline
|
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bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0: No effect.,1: If Master mode is enabled send a bus clear.."
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newline
|
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bitfld.long 0x0 14. "PECRQ,PEC Request" "0: No effect.,1: A PEC check or transmission is requested."
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bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0: No effect.,1: SMBus PEC (CRC) generation and check disabled."
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bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0: No effect.,1: SMBus PEC (CRC) generation and check enabled."
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bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0: No effect.,1: SMBus mode disabled."
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bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0: No effect.,1: If SMBDIS = 0 SMBus mode enabled."
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bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0: No effect.,1: High-speed mode disabled."
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bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0: No effect.,1: High-speed mode enabled."
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bitfld.long 0x0 7. "SWRST,Software Reset" "0: No effect.,1: Equivalent to a system reset."
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bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0: No effect.,1: If Master mode is enabled a SMBus Quick Command.."
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bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0: No effect.,1: The Slave mode is disabled. The shifter and.."
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bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0: No effect.,1: Enables the Slave mode (SVDIS must be written to.."
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bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0: No effect.,1: The Master mode is disabled all pending data is.."
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bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0: No effect.,1: Enables the Master mode (MSDIS must be written.."
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bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0: No effect.,1: STOP condition is sent just after completing the.."
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bitfld.long 0x0 0. "START,Send a START Condition" "0: No effect.,1: A frame beginning with a START bit is.."
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wgroup.long 0x600++0x3
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line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
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bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0: No effect.,1: Disable the Transmit and Receive FIFOs."
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bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0: No effect.,1: Enable the Transmit and Receive FIFOs."
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bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0: No effect.,1: Clears the Transmit FIFO Lock."
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bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0: No effect.,1: Empties the Receive FIFO."
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bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0: No effect.,1: Empties the Transmit FIFO."
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bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0: No effect.,1: Alternative Command mode disabled."
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bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0: No effect.,1: Alternative Command mode enabled."
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bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0: No effect.,1: If Master mode is enabled send a bus clear.."
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bitfld.long 0x0 14. "PECRQ,PEC Request" "0: No effect.,1: A PEC check or transmission is requested."
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bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0: No effect.,1: SMBus PEC (CRC) generation and check disabled."
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bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0: No effect.,1: SMBus PEC (CRC) generation and check enabled."
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bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0: No effect.,1: SMBus mode disabled."
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bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0: No effect.,1: If SMBDIS = 0 SMBus mode enabled."
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bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0: No effect.,1: High-speed mode disabled."
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bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0: No effect.,1: High-speed mode enabled."
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bitfld.long 0x0 7. "SWRST,Software Reset" "0: No effect.,1: Equivalent to a system reset."
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bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0: No effect.,1: If Master mode is enabled a SMBus Quick Command.."
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bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0: No effect.,1: The Slave mode is disabled. The shifter and.."
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bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0: No effect.,1: Enables the Slave mode (SVDIS must be written to.."
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bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0: No effect.,1: The Master mode is disabled all pending data is.."
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bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0: No effect.,1: Enables the Master mode (MSDIS must be written.."
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bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0: No effect.,1: STOP condition is sent just after completing the.."
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bitfld.long 0x0 0. "START,Send a START Condition" "0: No effect.,1: A frame beginning with a START bit is.."
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group.long 0x604++0xF
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line.long 0x0 "FLEX_TWI_MMR,TWI Master Mode Register"
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bitfld.long 0x0 24. "NOAP,No Auto-Stop On NACK Error" "0: A stop condition is sent automatically upon..,1: No automatic action is performed upon.."
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hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
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bitfld.long 0x0 13.--14. "SCLRBL,SCL Rise Boost Level" "0,1,2,3"
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bitfld.long 0x0 12. "MREAD,Master Read Direction" "0: Master write direction.,1: Master read direction."
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bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
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line.long 0x4 "FLEX_TWI_SMR,TWI Slave Mode Register"
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bitfld.long 0x4 31. "DATAMEN,Data Matching Enable" "0: Data matching on first received data is disabled.,1: Data matching on first received data is enabled."
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bitfld.long 0x4 30. "SADR3EN,Slave Address 3 Enable" "0: Slave address 3 matching is disabled.,1: Slave address 3 matching is enabled."
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bitfld.long 0x4 29. "SADR2EN,Slave Address 2 Enable" "0: Slave address 2 matching is disabled.,1: Slave address 2 matching is enabled."
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bitfld.long 0x4 28. "SADR1EN,Slave Address 1 Enable" "0: Slave address 1 matching is disabled.,1: Slave address 1 matching is enabled."
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hexmask.long.byte 0x4 16.--22. 1. "SADR,Slave Address"
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hexmask.long.byte 0x4 8.--14. 1. "MASK,Slave Address Mask"
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bitfld.long 0x4 7. "SNIFF,Slave Sniffer Mode" "0: Slave Sniffer mode is disabled.,1: Slave Sniffer mode is enabled."
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bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0: No effect.,1: Clock stretching disabled in Slave mode OVRE and.."
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bitfld.long 0x4 5. "BSEL,TWI Bus Selection" "0: TWI analyzes the TWCK and TWD pins from its TWI..,1: TWI analyzes the TWCK pins TWD from consecutive.."
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bitfld.long 0x4 4. "SADAT,Slave Address Treated as Data" "0: Slave address is handled normally (will not trig..,1: Slave address is handled as data field RXRDY.."
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bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0: Acknowledge of the SMBus Host Header disabled.,1: Acknowledge of the SMBus Host Header enabled."
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bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0: Acknowledge of the SMBus Default Address disabled.,1: Acknowledge of the SMBus Default Address enabled."
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bitfld.long 0x4 0. "NACKEN,Slave Receiver Data Phase NACK Enable" "0: Normal value to be returned in the ACK cycle of..,1: NACK value to be returned in the ACK cycle of.."
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line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
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hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
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line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
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hexmask.long.byte 0xC 24.--29. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
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bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
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bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
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hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
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rgroup.long 0x620++0x3
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line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
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bitfld.long 0x0 26. "SR,Start Repeated" "0: No repeated start has been detected since last..,1: At least one repeated start has been detected.."
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bitfld.long 0x0 25. "SDA,SDA Line Value" "0: SDA line sampled value is '0'.,1: SDA line sampled value is '1'."
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bitfld.long 0x0 24. "SCL,SCL Line Value" "0: SCL line sampled value is '0'.,1: SCL line sampled value is '1.'"
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bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0: The TWI is not locked.,1: The TWI is locked due to frame errors (see.."
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0: No SMBus Host Header Address received.,1: A SMBus Host Header Address was received."
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0: No SMBus Default Address received.,1: A SMBus Default Address was received."
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bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0: No SMBus PEC error occurred.,1: A SMBus PEC error occurred."
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bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0: No SMBus timeout occurred.,1: SMBus timeout occurred."
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bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag" "0: No SMBus slave drives the SMBALERT line.,1: At least one SMBus slave drives the SMBALERT line."
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0: No master code has been received.,1: A master code has been received."
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0: A slave access is being performing.,1: The Slave Access is finished. End Of Slave.."
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bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0: The clock is not stretched.,1: The clock is stretched. FLEX_TWI_THR /.."
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0: Arbitration won.,1: Arbitration lost. Another master of the TWI bus.."
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bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0: Each data byte has been correctly received by..,1: In Read mode a data byte has not been.."
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bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0: FLEX_TWI_THR has been filled on time.,1: FLEX_TWI_THR has not been filled on time."
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bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0: FLEX_TWI_RHR has not been loaded while RXRDY was..,1: FLEX_TWI_RHR has been loaded while RXRDY was.."
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bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0: No general call has been detected.,1: A general call has been detected. After the.."
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newline
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bitfld.long 0x0 4. "SVACC,Slave Access" "0: TWI is not addressed. SVACC is automatically..,1: Indicates that the address decoding sequence has.."
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bitfld.long 0x0 3. "SVREAD,Slave Read" "0: Indicates that a write access is performed by a..,1: Indicates that a read access is performed by a.."
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0: Transmit FIFO is full and cannot accept more data,1: Transmit FIFO is not full; one or more data can.."
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0: Receive FIFO is empty; no data to read,1: At least one unread data is in the Receive FIFO"
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0: As soon as a Start is detected.,1: After a Stop or a Repeated Start + an address.."
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rgroup.long 0x620++0x3
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line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
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bitfld.long 0x0 26. "SR,Start Repeated" "0: No repeated start has been detected since last..,1: At least one repeated start has been detected.."
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bitfld.long 0x0 25. "SDA,SDA Line Value" "0: SDA line sampled value is '0'.,1: SDA line sampled value is '1'."
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bitfld.long 0x0 24. "SCL,SCL Line Value" "0: SCL line sampled value is '0'.,1: SCL line sampled value is '1.'"
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bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0: The Transmit FIFO is not locked.,1: The Transmit FIFO is locked."
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0: No SMBus Host Header Address received.,1: A SMBus Host Header Address was received."
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0: No SMBus Default Address received.,1: A SMBus Default Address was received."
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bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0: No SMBus PEC error occurred.,1: A SMBus PEC error occurred."
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bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0: No SMBus timeout occurred.,1: SMBus timeout occurred."
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bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag" "0: No SMBus slave drives the SMBALERT line.,1: At least one SMBus slave drives the SMBALERT line."
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0: No master code has been received.,1: A master code has been received."
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0: A slave access is being performing.,1: The Slave Access is finished. End Of Slave.."
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bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0: The clock is not stretched.,1: The clock is stretched. FLEX_TWI_THR /.."
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newline
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0: Arbitration won.,1: Arbitration lost. Another master of the TWI bus.."
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bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0: Each data byte has been correctly received by..,1: In Read mode a data byte has not been.."
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newline
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bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0: FLEX_TWI_THR has been filled on time.,1: FLEX_TWI_THR has not been filled on time."
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newline
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bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0: FLEX_TWI_RHR has not been loaded while RXRDY was..,1: FLEX_TWI_RHR has been loaded while RXRDY was.."
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newline
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bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0: No general call has been detected.,1: A general call has been detected. After the.."
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newline
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bitfld.long 0x0 4. "SVACC,Slave Access" "0: TWI is not addressed. SVACC is automatically..,1: Indicates that the address decoding sequence has.."
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newline
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bitfld.long 0x0 3. "SVREAD,Slave Read" "0: Indicates that a write access is performed by a..,1: Indicates that a read access is performed by a.."
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0: Transmit FIFO is full and cannot accept more data.,1: Transmit FIFO is not full; one or more data can.."
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0: Receive FIFO is empty; no data to read.,1: At least one unread data is in the Receive FIFO."
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0: As soon as a Start is detected.,1: After a Stop or a Repeated Start + an address.."
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wgroup.long 0x624++0x7
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line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
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bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
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bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Enable" "0,1"
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bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
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bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
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bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
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bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Enable" "0,1"
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bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
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bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
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bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
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bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
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bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
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bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
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bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
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bitfld.long 0x4 16. "MCACK,Master Code Acknowledge Interrupt Disable" "0,1"
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bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
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bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
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bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 11. "EOSACC,End Of Slave Access Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
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bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
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bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
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bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
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bitfld.long 0x4 4. "SVACC,Slave Access Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
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rgroup.long 0x62C++0x7
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line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
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bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
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bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Mask" "0,1"
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bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
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bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
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bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
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bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Mask" "0,1"
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bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
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bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
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bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
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bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Mask" "0,1"
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
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bitfld.long 0x4 11.--12. "ASTATE,Acknowledge State (Slave Sniffer Mode only)" "0: No Acknowledge or Nacknowledge detected after..,1: Acknowledge (A) detected after previously logged..,2: Nacknowledge (NA) detected after previously..,3: Not defined"
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bitfld.long 0x4 10. "PSTATE,Stop State (Slave Sniffer Mode only)" "0: No STOP (P) detected after previous logged data.,1: Stop detected (P) after previous logged data."
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bitfld.long 0x4 8.--9. "SSTATE,Start State (Slave Sniffer Mode only)" "0: No START detected with the logged data,1: START (S) detected with the logged data,2: Repeated START (Sr) detected with the logged data,3: Not defined"
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hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Master or Slave Receive Holding Data"
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rgroup.long 0x630++0x3
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line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Master or Slave Receive Holding Data 3"
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hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Master or Slave Receive Holding Data 2"
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hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Master or Slave Receive Holding Data 1"
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hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Master or Slave Receive Holding Data 0"
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wgroup.long 0x634++0x3
|
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line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Master or Slave Transmit Holding Data"
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wgroup.long 0x634++0x3
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line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Master or Slave Transmit Holding Data 3"
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hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Master or Slave Transmit Holding Data 2"
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hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Master or Slave Transmit Holding Data 1"
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Master or Slave Transmit Holding Data 0"
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group.long 0x638++0x1B
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line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
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hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
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hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Master Clock Stretch Maximum Cycles"
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hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Slave Clock Stretch Maximum Cycles"
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hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
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line.long 0x4 "FLEX_TWI_HSR,TWI High Speed Register"
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hexmask.long.byte 0x4 0.--7. 1. "MCODE,TWI High Speed Master Code"
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line.long 0x8 "FLEX_TWI_ACR,TWI Alternative Command Register"
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bitfld.long 0x8 25. "NPEC,Next PEC Request (SMBus Mode only)" "0: The next transfer does not use a PEC byte.,1: The next transfer uses a PEC byte."
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bitfld.long 0x8 24. "NDIR,Next Transfer Direction" "0: Write direction.,1: Read direction."
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hexmask.long.byte 0x8 16.--23. 1. "NDATAL,Next Data Length"
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bitfld.long 0x8 9. "PEC,PEC Request (SMBus Mode only)" "0: The transfer does not use a PEC byte.,1: The transfer uses a PEC byte."
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bitfld.long 0x8 8. "DIR,Transfer Direction" "0: Write direction.,1: Read direction."
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hexmask.long.byte 0x8 0.--7. 1. "DATAL,Data Length"
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line.long 0xC "FLEX_TWI_FILTR,TWI Filter Register"
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bitfld.long 0xC 8.--10. "THRES,Digital Filter Threshold" "0: No filtering applied on TWI inputs.,?,?,?,?,?,?,?"
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bitfld.long 0xC 1. "PADFEN,PAD Filter Enable" "0: PAD analog filter is disabled.,1: PAD analog filter is enabled. (The analog filter.."
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bitfld.long 0xC 0. "FILT,RX Digital Filter" "0: No filtering applied on TWI inputs.,1: TWI input filtering is active. (Only in Standard.."
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line.long 0x10 "FLEX_TWI_HSCWGR,TWI High Speed Clock Waveform Generator Register"
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bitfld.long 0x10 16.--18. "HSCKDIV,High Speed Clock Divider" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x10 8.--15. 1. "HSCHDIV,High Speed Clock High Divider"
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hexmask.long.byte 0x10 0.--7. 1. "HSCLDIV,High Speed Clock Low Divider"
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line.long 0x14 "FLEX_TWI_SWMR,TWI Matching Register"
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hexmask.long.byte 0x14 24.--31. 1. "DATAM,Data Match"
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hexmask.long.byte 0x14 16.--22. 1. "SADR3,Slave Address 3"
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hexmask.long.byte 0x14 8.--14. 1. "SADR2,Slave Address 2"
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hexmask.long.byte 0x14 0.--6. 1. "SADR1,Slave Address 1"
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line.long 0x18 "FLEX_TWI_FMR,TWI FIFO Mode Register"
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hexmask.long.byte 0x18 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
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hexmask.long.byte 0x18 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
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bitfld.long 0x18 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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newline
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bitfld.long 0x18 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x654++0x3
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line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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newline
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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rgroup.long 0x660++0x3
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line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
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bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0: No Receive FIFO pointer occurred,1: Receive FIFO pointer error occurred. Receiver.."
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bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0: No Transmit FIFO pointer occurred,1: Transmit FIFO pointer error occurred."
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newline
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bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0: Number of unread data in Receive FIFO is below..,1: Number of unread data in Receive FIFO has.."
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newline
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bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0: Receive FIFO is not empty.,1: Receive FIFO has been filled since the last read.."
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newline
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bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0: Receive FIFO is not empty.,1: Receive FIFO has been emptied since the last.."
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newline
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bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0: Number of data in Transmit FIFO is above..,1: Number of data in Transmit FIFO has reached.."
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newline
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bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0: Transmit FIFO is not full.,1: Transmit FIFO has been filled since the last.."
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newline
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bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0: Transmit FIFO is not empty.,1: Transmit FIFO has been emptied since the last.."
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wgroup.long 0x664++0x7
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line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
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|
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
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|
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bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
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rgroup.long 0x66C++0x3
|
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line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
|
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
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group.long 0x6E4++0x3
|
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line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
|
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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newline
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
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newline
|
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
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newline
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
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rgroup.long 0x6E8++0x3
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line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
|
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hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
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newline
|
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bitfld.long 0x0 0. "WPVS,Write Protect Violation Status" "0: No Write Protection Violation has occurred since..,1: A Write Protection Violation has occurred since.."
|
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tree.end
|
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tree "FLEXCOM2"
|
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base ad:0xE1820000
|
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group.long 0x0++0x3
|
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line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
|
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bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected. USART/TWI..,3: All TWI related protocols are selected (TWI.."
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rgroup.long 0x10++0x3
|
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line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
|
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hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
|
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group.long 0x20++0x3
|
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line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
|
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
|
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wgroup.long 0x200++0x3
|
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line.long 0x0 "FLEX_US_CR,USART Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0: No effect.,1: Disables the Transmit and Receive FIFOs."
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newline
|
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0: No effect.,1: Enables the Transmit and Receive FIFOs."
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newline
|
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bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0: No effect.,1: Restarts the comparison trigger to enable.."
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newline
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bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0: No effect.,1: Clears the Transmit FIFO Lock"
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newline
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bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0: No effect.,1: Empties the Receive FIFO."
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newline
|
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bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0: No effect.,1: Empties the Transmit FIFO."
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newline
|
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bitfld.long 0x0 21. "LINWKUP,Send LIN Wakeup Signal" "0: No effect:,1: Sends a wakeup signal on the LIN bus."
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newline
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bitfld.long 0x0 20. "LINABT,Abort LIN Transmission" "0: No effect.,1: Aborts the current LIN transmission."
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newline
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bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0: No effect.,1: Drives the RTS pin to 0 if FLEX_US_MR.USART_MODE.."
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newline
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bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0: No effect.,1: Drives the RTS pin to 1 if FLEX_US_MR.USART_MODE.."
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bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0: No effect,1: Immediately restarts timeout period."
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|
newline
|
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bitfld.long 0x0 14. "RSTNACK,Reset Non Acknowledge" "0: No effect,1: Resets FLEX_US_CSR.NACK."
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|
newline
|
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bitfld.long 0x0 13. "RSTIT,Reset Iterations" "0: No effect.,1: Resets FLEX_US_CSR.ITER. No effect if the.."
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|
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bitfld.long 0x0 12. "SENDA,Send Address" "0: No effect.,1: In Multidrop mode only the next character.."
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|
newline
|
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bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0: No effect.,1: Starts waiting for a character before clocking.."
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newline
|
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bitfld.long 0x0 10. "STPBRK,Stop Break" "0: No effect.,1: Stops transmission of the break after a minimum.."
|
|
newline
|
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bitfld.long 0x0 9. "STTBRK,Start Break" "0: No effect.,1: Starts transmission of a break after the.."
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|
newline
|
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bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0: No effect.,1: Resets the status bits PARE FRAME OVRE MANE.."
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|
newline
|
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bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0: No effect.,1: Disables the transmitter."
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|
newline
|
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bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0: No effect.,1: Enables the transmitter if TXDIS is 0."
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|
newline
|
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bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0: No effect.,1: Disables the receiver."
|
|
newline
|
|
bitfld.long 0x0 4. "RXEN,Receiver Enable" "0: No effect.,1: Enables the receiver if RXDIS is 0."
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|
newline
|
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bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0: No effect.,1: Resets the transmitter."
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|
newline
|
|
bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0: No effect.,1: Resets the receiver."
|
|
group.long 0x204++0x3
|
|
line.long 0x0 "FLEX_US_MR,USART Mode Register"
|
|
bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0: Start frame delimiter is COMMAND or DATA SYNC.,1: Start frame delimiter is one bit."
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|
newline
|
|
bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0: The Manchester start bit is a 0 to 1 transition,1: The Manchester start bit is a 1 to 0 transition."
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|
newline
|
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bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0: Manchester encoder/decoder are disabled.,1: Manchester encoder/decoder are enabled."
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|
newline
|
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bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0: The USART does not filter the receive line.,1: The USART filters the receive line using a.."
|
|
newline
|
|
bitfld.long 0x0 24.--26. "MAX_ITERATION,Maximum Number of Automatic Iteration" "0,1,2,3,4,5,6,7"
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|
newline
|
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bitfld.long 0x0 23. "INVDATA,Inverted Data" "0: The data field transmitted on TXD line is the..,1: The data field transmitted on TXD line is.."
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|
newline
|
|
bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0: User defined configuration of command or data..,1: The sync field is updated when a character is.."
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|
newline
|
|
bitfld.long 0x0 21. "DSNACK,Disable Successive NACK" "0: NACK is sent on the ISO line as soon as a parity..,1: Successive parity errors are counted up to the.."
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|
newline
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bitfld.long 0x0 20. "INACK,Inhibit Non Acknowledge" "0: The NACK is generated.,1: The NACK is not generated."
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newline
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bitfld.long 0x0 19. "OVER,Oversampling Mode" "0: 16x Oversampling.,1: 8x Oversampling."
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newline
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bitfld.long 0x0 18. "CLKO,Clock Output Select" "0: The USART does not drive the SCK pin..,1: The USART drives the SCK pin if USCLKS does not.."
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bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0: CHRL defines character length.,1: 9-bit character length."
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bitfld.long 0x0 16. "MSBF,Bit Order" "0: Least significant bit is sent/received first.,1: Most significant bit is sent/received first."
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bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
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bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
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bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
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bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0: USART operates in Asynchronous mode (UART).,1: USART operates in Synchronous mode."
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bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
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bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
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hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
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wgroup.long 0x208++0x3
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line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Enable" "0,1"
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bitfld.long 0x0 10. "ITER,Max number of Repetitions Reached Interrupt Enable" "0,1"
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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wgroup.long 0x208++0x7
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line.long 0x0 "FLEX_US_IER_LIN_MODE,USART Interrupt Enable Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Enable" "0,1"
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Enable" "0,1"
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Enable" "0,1"
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Enable" "0,1"
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Enable" "0,1"
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Enable" "0,1"
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Enable" "0,1"
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Enable" "0,1"
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Enable" "0,1"
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
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bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt Disable" "0,1"
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bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
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bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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wgroup.long 0x20C++0x3
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line.long 0x0 "FLEX_US_IDR_LIN_MODE,USART Interrupt Disable Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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rgroup.long 0x210++0x3
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line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 10. "ITER,Max Number of Repetitions Reached Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
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rgroup.long 0x210++0x7
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line.long 0x0 "FLEX_US_IMR_LIN_MODE,USART Interrupt Mask Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
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bitfld.long 0x4 24. "MANE,Manchester Error" "0: No Manchester error has been detected since the..,1: At least one Manchester error has been detected.."
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newline
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bitfld.long 0x4 23. "CTS,Image of CTS Input" "0: CTS input is driven low.,1: CTS input is driven high."
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newline
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bitfld.long 0x4 22. "CMP,Comparison Status" "0: No received character matched the comparison..,1: A received character matched the comparison.."
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newline
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0: No input change has been detected on the CTS pin..,1: At least one input change has been detected on.."
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newline
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt" "0: Non acknowledge has not been detected since the..,1: At least one non acknowledge has been detected.."
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newline
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bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached" "0: Maximum number of repetitions has not been..,1: Maximum number of repetitions has been reached.."
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newline
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bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0: There are characters in either FLEX_US_THR or..,1: There are no characters in FLEX_US_THR nor in.."
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newline
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bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0: There has not been a timeout since the last..,1: There has been a timeout since the last Start.."
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newline
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bitfld.long 0x4 7. "PARE,Parity Error" "0: No parity error has been detected since the last..,1: At least one parity error has been detected.."
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newline
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bitfld.long 0x4 6. "FRAME,Framing Error" "0: No stop bit has been detected low since the last..,1: At least one stop bit has been detected low.."
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newline
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bitfld.long 0x4 5. "OVRE,Overrun Error" "0: No overrun error has occurred since the last..,1: At least one overrun error has occurred since.."
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newline
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bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0: No break received or end of break detected since..,1: Break received or end of break detected since.."
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newline
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bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0: Transmit FIFO is full and cannot accept more data,1: Transmit FIFO is not full; one or more data can.."
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newline
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bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0: Receive FIFO is empty; no data to read,1: At least one unread data is in the Receive FIFO"
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rgroup.long 0x214++0x7
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line.long 0x0 "FLEX_US_CSR_LIN_MODE,USART Channel Status Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error" "0: No LIN header timeout error has been detected..,1: A LIN header timeout error has been detected.."
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newline
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error" "0: No LIN synch tolerance error has been detected..,1: A LIN synch tolerance error has been detected.."
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newline
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error" "0: No LIN slave not responding error has been..,1: A LIN slave not responding error has been.."
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newline
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error" "0: No LIN checksum error has been detected since..,1: A LIN checksum error has been detected since the.."
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newline
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Error" "0: No LIN identifier parity error has been detected..,1: A LIN identifier parity error has been detected.."
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newline
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error" "0: No LIN inconsistent synch field error has been..,1: The USART is configured as a slave node and a.."
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newline
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bitfld.long 0x0 25. "LINBE,LIN Bit Error" "0: No bit error has been detected since the last..,1: A bit error has been detected since the last.."
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newline
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bitfld.long 0x0 23. "LINBLS,LIN Bus Line Status" "0: LIN bus line is set to 0.,1: LIN bus line is set to 1."
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newline
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed" "0: The USART is idle or a LIN transfer is ongoing.,1: A LIN transfer has been completed since the last.."
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newline
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received" "0: No LIN identifier has been received since the..,1: At least one LIN identifier has been received.."
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newline
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received" "0: No LIN break has received sent since the last..,1: At least one LIN break has been received since.."
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newline
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bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0: There are characters in either FLEX_US_THR or..,1: There are no characters in FLEX_US_THR nor in.."
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newline
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bitfld.long 0x0 8. "TIMEOUT,Receiver Timeout" "0: There has not been a timeout since the last..,1: There has been a timeout since the last start.."
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newline
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bitfld.long 0x0 7. "PARE,Parity Error" "0: No parity error has been detected since the last..,1: At least one parity error has been detected.."
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error" "0: No stop bit has been detected low since the last..,1: At least one stop bit has been detected low.."
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error" "0: No overrun error has occurred since the last..,1: At least one overrun error has occurred since.."
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newline
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bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0: A character in FLEX_US_THR is waiting to be..,1: There is no character in FLEX_US_THR."
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newline
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bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0: No complete character has been received since..,1: At least one complete character has been.."
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line.long 0x4 "FLEX_US_RHR,USART Receive Holding Register"
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bitfld.long 0x4 15. "RXSYNH,Received Sync" "0: Last character received is a data.,1: Last character received is a command."
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newline
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hexmask.long.word 0x4 0.--8. 1. "RXCHR,Received Character"
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rgroup.long 0x218++0x3
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line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Characters"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Characters"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Characters"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Characters"
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wgroup.long 0x21C++0x3
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line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
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bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0: The next character sent is encoded as a data.,1: The next character sent is encoded as a command."
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newline
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hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
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wgroup.long 0x21C++0x3
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line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
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group.long 0x220++0xB
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line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
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bitfld.long 0x0 16.--18. "FP,Fractional Part" "0: Fractional divider is disabled.,?,?,?,?,?,?,?"
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newline
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hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
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line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
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hexmask.long.tbyte 0x4 0.--16. 1. "TO,Timeout Value"
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line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
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hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
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group.long 0x240++0x3
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line.long 0x0 "FLEX_US_FIDI,USART FI DI Ratio Register"
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hexmask.long.word 0x0 0.--15. 1. "FI_DI_RATIO,FI Over DI Ratio Value"
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rgroup.long 0x244++0x3
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line.long 0x0 "FLEX_US_NER,USART Number of Errors Register"
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hexmask.long.byte 0x0 0.--7. 1. "NB_ERRORS,Number of Errors"
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group.long 0x24C++0xF
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line.long 0x0 "FLEX_US_IF,USART IrDA Filter Register"
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hexmask.long.byte 0x0 0.--7. 1. "IRDA_FILTER,IrDA Filter"
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line.long 0x4 "FLEX_US_MAN,USART Manchester Configuration Register"
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bitfld.long 0x4 31. "RXIDLEV,Receiver Idle Value" "0: Receiver line idle value is 0.,1: Receiver line idle value is 1."
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bitfld.long 0x4 30. "DRIFT,Drift Compensation" "0: The USART cannot recover from an important clock..,1: The USART can recover from clock drift. The 16X.."
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bitfld.long 0x4 29. "ONE,Must Be Set to 1" "0,1"
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bitfld.long 0x4 28. "RX_MPOL,Receiver Manchester Polarity" "0: Logic zero is coded as a zero-to-one transition..,1: Logic zero is coded as a one-to-zero transition.."
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bitfld.long 0x4 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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hexmask.long.byte 0x4 16.--19. 1. "RX_PL,Receiver Preamble Length"
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bitfld.long 0x4 12. "TX_MPOL,Transmitter Manchester Polarity" "0: Logic zero is coded as a zero-to-one transition..,1: Logic zero is coded as a one-to-zero transition.."
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bitfld.long 0x4 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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hexmask.long.byte 0x4 0.--3. 1. "TX_PL,Transmitter Preamble Length"
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line.long 0x8 "FLEX_US_LINMR,USART LIN Mode Register"
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bitfld.long 0x8 17. "SYNCDIS,Synchronization Disable" "0: The synchronization procedure is performed in..,1: The synchronization procedure is not performed.."
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bitfld.long 0x8 16. "PDCM,DMAC Mode" "0: The LIN mode register FLEX_US_LINMR is not..,1: The LIN mode register FLEX_US_LINMR (excepting.."
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hexmask.long.byte 0x8 8.--15. 1. "DLC,Data Length Control"
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bitfld.long 0x8 7. "WKUPTYP,Wakeup Signal Type" "0: Setting the LINWKUP bit in the control register..,1: Setting the LINWKUP bit in the control register.."
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bitfld.long 0x8 6. "FSDIS,Frame Slot Mode Disable" "0: The Frame Slot mode is enabled.,1: The Frame Slot mode is disabled."
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bitfld.long 0x8 5. "DLM,Data Length Mode" "0: The response data length is defined by the DLC..,1: The response data length is defined by the bits.."
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bitfld.long 0x8 4. "CHKTYP,Checksum Type" "0: LIN 2.0 'enhanced' checksum,1: LIN 1.3 'classic' checksum"
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bitfld.long 0x8 3. "CHKDIS,Checksum Disable" "0: In master node configuration the checksum is..,1: Whatever the node configuration is the checksum.."
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bitfld.long 0x8 2. "PARDIS,Parity Disable" "0: In master node configuration the identifier..,1: Whatever the node configuration is the.."
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bitfld.long 0x8 0.--1. "NACT,LIN Node Action" "0: The USART transmits the response.,1: The USART receives the response.,2: The USART does not transmit and does not receive..,?"
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line.long 0xC "FLEX_US_LINIR,USART LIN Identifier Register"
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hexmask.long.byte 0xC 0.--7. 1. "IDCHR,Identifier Character"
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rgroup.long 0x25C++0x3
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line.long 0x0 "FLEX_US_LINBRR,USART LIN Baud Rate Register"
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bitfld.long 0x0 16.--18. "LINFP,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x0 0.--15. 1. "LINCD,Clock Divider after Synchronization"
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group.long 0x290++0x3
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line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
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hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
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bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0: The parity is not checked and a bad parity..,1: The parity is checked and a matching condition.."
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bitfld.long 0x0 12.--13. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start..,2: Comparison must be met to receive the current..,?"
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hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
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group.long 0x2A0++0x3
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line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
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hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
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hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
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bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0: RTS pin is not controlled by Receive FIFO..,1: RTS pin is controlled by Receive FIFO thresholds."
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bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x2A4++0x3
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line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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wgroup.long 0x2A8++0x7
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line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
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bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
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rgroup.long 0x2B0++0x7
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line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
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bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Number of unread data in Receive FIFO is above..,1: Number of unread data in Receive FIFO has.."
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bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0: The Transmit FIFO is not locked.,1: The Transmit FIFO is locked."
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bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0: No Receive FIFO pointer occurred,1: Receive FIFO pointer error occurred. Receiver.."
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bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0: No Transmit FIFO pointer occurred,1: Transmit FIFO pointer error occurred."
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bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Number of unread data in Receive FIFO is below..,1: Number of unread data in Receive FIFO has.."
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bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Receive FIFO is not empty.,1: Receive FIFO has been filled since the last.."
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bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Receive FIFO is not empty.,1: Receive FIFO has been emptied since the last.."
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bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Number of data in Transmit FIFO is above..,1: Number of data in Transmit FIFO has reached.."
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bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Transmit FIFO is not full.,1: Transmit FIFO has been filled since the last.."
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bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Transmit FIFO is not empty.,1: Transmit FIFO has been emptied since the last.."
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group.long 0x2E4++0x3
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line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection on configuration..,1: Enables the write protection on configuration.."
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rgroup.long 0x2E8++0x3
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line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
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hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
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wgroup.long 0x400++0x3
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line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
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bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0: No effect.,1: Disables the Transmit and Receive FIFOs"
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0: No effect.,1: Enables the Transmit and Receive FIFOs"
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bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0: No effect.,1: The current NPCS will be de-asserted after the.."
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bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0: No effect.,1: Empties the Receive FIFO."
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bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0: No effect.,1: Empties the Transmit FIFO."
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bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0: No effect.,1: Restarts the comparison trigger to enable.."
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bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0: No effect.,1: Reset the SPI. A software-triggered hardware.."
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bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0: No effect.,1: Disables the SPI."
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bitfld.long 0x0 0. "SPIEN,SPI Enable" "0: No effect.,1: Enables the SPI to transfer and receive data."
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group.long 0x404++0x3
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line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
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hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
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bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0: Local loopback path disabled.,1: Local loopback path enabled."
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bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0: No Effect. In Master mode a transfer can be..,1: In Master mode a transfer can start only if.."
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bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0: Mode fault detection is enabled.,1: Mode fault detection is disabled."
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bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
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bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0: The chip selects are directly connected to a..,1: The four NPCS chip select lines are connected to.."
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bitfld.long 0x0 1. "PS,Peripheral Select" "0: Fixed Peripheral Select,1: Variable Peripheral Select"
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bitfld.long 0x0 0. "MSTR,Master/Slave Mode" "0: SPI is in Slave mode.,1: SPI is in Master mode."
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rgroup.long 0x408++0x3
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line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
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rgroup.long 0x408++0x3
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line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
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hexmask.long.word 0x0 16.--31. 1. "RD1,Receive Data"
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hexmask.long.word 0x0 0.--15. 1. "RD0,Receive Data"
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rgroup.long 0x408++0x3
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line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
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hexmask.long.byte 0x0 24.--31. 1. "RD3,Receive Data"
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hexmask.long.byte 0x0 16.--23. 1. "RD2,Receive Data"
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hexmask.long.byte 0x0 8.--15. 1. "RD1,Receive Data"
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hexmask.long.byte 0x0 0.--7. 1. "RD0,Receive Data"
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wgroup.long 0x40C++0x3
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line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
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bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0: No effect.,1: The current NPCS is de-asserted after the.."
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
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wgroup.long 0x40C++0x3
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line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
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hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
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hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
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rgroup.long 0x410++0x3
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line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
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bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0: No Receive FIFO pointer occurred,1: Receive FIFO pointer error occurred. Receiver.."
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bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0: No Transmit FIFO pointer occurred,1: Transmit FIFO pointer error occurred."
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bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0: Number of unread data in Receive FIFO is below..,1: Number of unread data in Receive FIFO has.."
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bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0: Receive FIFO is not empty or RXFE flag has been..,1: Receive FIFO has been filled (changing states.."
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bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0: Receive FIFO is not empty or RXFE flag has been..,1: Receive FIFO has been emptied (changing states.."
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bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0: Number of data in Transmit FIFO is above..,1: Number of data in Transmit FIFO has reached.."
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bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0: Transmit FIFO is not full or TXFF flag has been..,1: Transmit FIFO has been filled since the last.."
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bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0: Transmit FIFO is not empty.,1: Transmit FIFO has been emptied since the last.."
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bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0: SPI is disabled.,1: SPI is enabled."
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bitfld.long 0x0 12. "SFERR,Slave Frame Error (cleared on read)" "0: There is no frame error detected for a slave..,1: In Slave mode the chip select raised while the.."
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bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0: No received character matched the comparison..,1: A received character matched the comparison.."
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bitfld.long 0x0 10. "UNDES,Underrun Error Status (Slave mode only) (cleared on read)" "0: No underrun has been detected since the last..,1: A transfer starts whereas no data has been.."
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0: As soon as data is written in FLEX_SPI_TDR.,1: FLEX_SPI_TDR and internal shift register are.."
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bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0: No rising edge detected on NSS pin since the..,1: A rising edge occurred on NSS pin since the last.."
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bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0: No overrun has been detected since the last read..,1: An overrun has occurred since the last read of.."
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bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0: No mode fault has been detected since the last..,1: A mode fault occurred since the last read of.."
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bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0: Transmit FIFO cannot accept more data.,1: Transmit FIFO can accept data; one or more data.."
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newline
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0: Receive FIFO is empty; no data to read,1: At least one unread data is in the Receive FIFO"
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wgroup.long 0x414++0x7
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line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
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bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
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newline
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bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
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bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
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newline
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bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
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rgroup.long 0x41C++0x3
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line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
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bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
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newline
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bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
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repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
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group.long ($2+0x430)++0x3
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line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register x"
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hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
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newline
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hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
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newline
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bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0: The Peripheral Chip Select Line rises as soon as..,1: The Peripheral Chip Select does not rise after.."
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newline
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bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0: The Peripheral Chip Select does not rise between..,1: The Peripheral Chip Select rises systematically.."
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newline
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bitfld.long 0x0 1. "NCPHA,Clock Phase" "0: Data are changed on the leading edge of SPCK and..,1: Data are captured on the leading edge of SPCK.."
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newline
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bitfld.long 0x0 0. "CPOL,Clock Polarity" "0: The inactive state value of SPCK is logic level..,1: The inactive state value of SPCK is logic level.."
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repeat.end
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group.long 0x440++0x3
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line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
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newline
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hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
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newline
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bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
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newline
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bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
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rgroup.long 0x444++0x3
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line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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newline
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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group.long 0x448++0x3
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line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
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hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
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newline
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hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
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group.long 0x4E4++0x3
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line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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newline
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
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newline
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
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newline
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
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rgroup.long 0x4E8++0x3
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line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
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hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
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newline
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0: No write protect violation has occurred since..,1: A write protect violation has occurred since the.."
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wgroup.long 0x600++0x3
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line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
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bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0: No effect.,1: Disable the Transmit and Receive FIFOs"
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newline
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bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0: No effect.,1: Enable the Transmit and Receive FIFOs"
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newline
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bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0: No effect.,1: Clear the TWI FSM lock."
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newline
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bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0: No effect.,1: Clear the Transmit Holding Register and set.."
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newline
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bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0: No effect.,1: Alternative Command mode disabled."
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newline
|
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bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0: No effect.,1: Alternative Command mode enabled."
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newline
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bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0: No effect.,1: If Master mode is enabled send a bus clear.."
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newline
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bitfld.long 0x0 14. "PECRQ,PEC Request" "0: No effect.,1: A PEC check or transmission is requested."
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newline
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bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0: No effect.,1: SMBus PEC (CRC) generation and check disabled."
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newline
|
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bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0: No effect.,1: SMBus PEC (CRC) generation and check enabled."
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newline
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bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0: No effect.,1: SMBus mode disabled."
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newline
|
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bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0: No effect.,1: If SMBDIS = 0 SMBus mode enabled."
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newline
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bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0: No effect.,1: High-speed mode disabled."
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newline
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bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0: No effect.,1: High-speed mode enabled."
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newline
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bitfld.long 0x0 7. "SWRST,Software Reset" "0: No effect.,1: Equivalent to a system reset."
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newline
|
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bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0: No effect.,1: If Master mode is enabled a SMBus Quick Command.."
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newline
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bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0: No effect.,1: The Slave mode is disabled. The shifter and.."
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|
newline
|
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bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0: No effect.,1: Enables the Slave mode (SVDIS must be written to.."
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|
newline
|
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bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0: No effect.,1: The Master mode is disabled all pending data is.."
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|
newline
|
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bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0: No effect.,1: Enables the Master mode (MSDIS must be written.."
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|
newline
|
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bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0: No effect.,1: STOP condition is sent just after completing the.."
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|
newline
|
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bitfld.long 0x0 0. "START,Send a START Condition" "0: No effect.,1: A frame beginning with a START bit is.."
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wgroup.long 0x600++0x3
|
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line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
|
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bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0: No effect.,1: Disable the Transmit and Receive FIFOs."
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0: No effect.,1: Enable the Transmit and Receive FIFOs."
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0: No effect.,1: Clears the Transmit FIFO Lock."
|
|
newline
|
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bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0: No effect.,1: Empties the Receive FIFO."
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0: No effect.,1: Empties the Transmit FIFO."
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0: No effect.,1: Alternative Command mode disabled."
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0: No effect.,1: Alternative Command mode enabled."
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0: No effect.,1: If Master mode is enabled send a bus clear.."
|
|
newline
|
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bitfld.long 0x0 14. "PECRQ,PEC Request" "0: No effect.,1: A PEC check or transmission is requested."
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0: No effect.,1: SMBus PEC (CRC) generation and check disabled."
|
|
newline
|
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bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0: No effect.,1: SMBus PEC (CRC) generation and check enabled."
|
|
newline
|
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bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0: No effect.,1: SMBus mode disabled."
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0: No effect.,1: If SMBDIS = 0 SMBus mode enabled."
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0: No effect.,1: High-speed mode disabled."
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0: No effect.,1: High-speed mode enabled."
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0: No effect.,1: Equivalent to a system reset."
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0: No effect.,1: If Master mode is enabled a SMBus Quick Command.."
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0: No effect.,1: The Slave mode is disabled. The shifter and.."
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0: No effect.,1: Enables the Slave mode (SVDIS must be written to.."
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0: No effect.,1: The Master mode is disabled all pending data is.."
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0: No effect.,1: Enables the Master mode (MSDIS must be written.."
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0: No effect.,1: STOP condition is sent just after completing the.."
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0: No effect.,1: A frame beginning with a START bit is.."
|
|
group.long 0x604++0xF
|
|
line.long 0x0 "FLEX_TWI_MMR,TWI Master Mode Register"
|
|
bitfld.long 0x0 24. "NOAP,No Auto-Stop On NACK Error" "0: A stop condition is sent automatically upon..,1: No automatic action is performed upon.."
|
|
newline
|
|
hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
|
|
newline
|
|
bitfld.long 0x0 13.--14. "SCLRBL,SCL Rise Boost Level" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 12. "MREAD,Master Read Direction" "0: Master write direction.,1: Master read direction."
|
|
newline
|
|
bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
|
|
line.long 0x4 "FLEX_TWI_SMR,TWI Slave Mode Register"
|
|
bitfld.long 0x4 31. "DATAMEN,Data Matching Enable" "0: Data matching on first received data is disabled.,1: Data matching on first received data is enabled."
|
|
newline
|
|
bitfld.long 0x4 30. "SADR3EN,Slave Address 3 Enable" "0: Slave address 3 matching is disabled.,1: Slave address 3 matching is enabled."
|
|
newline
|
|
bitfld.long 0x4 29. "SADR2EN,Slave Address 2 Enable" "0: Slave address 2 matching is disabled.,1: Slave address 2 matching is enabled."
|
|
newline
|
|
bitfld.long 0x4 28. "SADR1EN,Slave Address 1 Enable" "0: Slave address 1 matching is disabled.,1: Slave address 1 matching is enabled."
|
|
newline
|
|
hexmask.long.byte 0x4 16.--22. 1. "SADR,Slave Address"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--14. 1. "MASK,Slave Address Mask"
|
|
newline
|
|
bitfld.long 0x4 7. "SNIFF,Slave Sniffer Mode" "0: Slave Sniffer mode is disabled.,1: Slave Sniffer mode is enabled."
|
|
newline
|
|
bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0: No effect.,1: Clock stretching disabled in Slave mode OVRE and.."
|
|
newline
|
|
bitfld.long 0x4 5. "BSEL,TWI Bus Selection" "0: TWI analyzes the TWCK and TWD pins from its TWI..,1: TWI analyzes the TWCK pins TWD from consecutive.."
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|
newline
|
|
bitfld.long 0x4 4. "SADAT,Slave Address Treated as Data" "0: Slave address is handled normally (will not trig..,1: Slave address is handled as data field RXRDY.."
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|
newline
|
|
bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0: Acknowledge of the SMBus Host Header disabled.,1: Acknowledge of the SMBus Host Header enabled."
|
|
newline
|
|
bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0: Acknowledge of the SMBus Default Address disabled.,1: Acknowledge of the SMBus Default Address enabled."
|
|
newline
|
|
bitfld.long 0x4 0. "NACKEN,Slave Receiver Data Phase NACK Enable" "0: Normal value to be returned in the ACK cycle of..,1: NACK value to be returned in the ACK cycle of.."
|
|
line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
|
|
line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
hexmask.long.byte 0xC 24.--29. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
|
|
newline
|
|
bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0: No repeated start has been detected since last..,1: At least one repeated start has been detected.."
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|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0: SDA line sampled value is '0'.,1: SDA line sampled value is '1'."
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0: SCL line sampled value is '0'.,1: SCL line sampled value is '1.'"
|
|
newline
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bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0: The TWI is not locked.,1: The TWI is locked due to frame errors (see.."
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0: No SMBus Host Header Address received.,1: A SMBus Host Header Address was received."
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0: No SMBus Default Address received.,1: A SMBus Default Address was received."
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bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0: No SMBus PEC error occurred.,1: A SMBus PEC error occurred."
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bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0: No SMBus timeout occurred.,1: SMBus timeout occurred."
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bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag" "0: No SMBus slave drives the SMBALERT line.,1: At least one SMBus slave drives the SMBALERT line."
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0: No master code has been received.,1: A master code has been received."
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0: A slave access is being performing.,1: The Slave Access is finished. End Of Slave.."
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bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0: The clock is not stretched.,1: The clock is stretched. FLEX_TWI_THR /.."
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0: Arbitration won.,1: Arbitration lost. Another master of the TWI bus.."
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bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0: Each data byte has been correctly received by..,1: In Read mode a data byte has not been.."
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bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0: FLEX_TWI_THR has been filled on time.,1: FLEX_TWI_THR has not been filled on time."
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bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0: FLEX_TWI_RHR has not been loaded while RXRDY was..,1: FLEX_TWI_RHR has been loaded while RXRDY was.."
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bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0: No general call has been detected.,1: A general call has been detected. After the.."
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bitfld.long 0x0 4. "SVACC,Slave Access" "0: TWI is not addressed. SVACC is automatically..,1: Indicates that the address decoding sequence has.."
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bitfld.long 0x0 3. "SVREAD,Slave Read" "0: Indicates that a write access is performed by a..,1: Indicates that a read access is performed by a.."
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0: Transmit FIFO is full and cannot accept more data,1: Transmit FIFO is not full; one or more data can.."
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0: Receive FIFO is empty; no data to read,1: At least one unread data is in the Receive FIFO"
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0: As soon as a Start is detected.,1: After a Stop or a Repeated Start + an address.."
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rgroup.long 0x620++0x3
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line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
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bitfld.long 0x0 26. "SR,Start Repeated" "0: No repeated start has been detected since last..,1: At least one repeated start has been detected.."
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bitfld.long 0x0 25. "SDA,SDA Line Value" "0: SDA line sampled value is '0'.,1: SDA line sampled value is '1'."
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bitfld.long 0x0 24. "SCL,SCL Line Value" "0: SCL line sampled value is '0'.,1: SCL line sampled value is '1.'"
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bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0: The Transmit FIFO is not locked.,1: The Transmit FIFO is locked."
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0: No SMBus Host Header Address received.,1: A SMBus Host Header Address was received."
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0: No SMBus Default Address received.,1: A SMBus Default Address was received."
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bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0: No SMBus PEC error occurred.,1: A SMBus PEC error occurred."
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bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0: No SMBus timeout occurred.,1: SMBus timeout occurred."
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bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag" "0: No SMBus slave drives the SMBALERT line.,1: At least one SMBus slave drives the SMBALERT line."
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0: No master code has been received.,1: A master code has been received."
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0: A slave access is being performing.,1: The Slave Access is finished. End Of Slave.."
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bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0: The clock is not stretched.,1: The clock is stretched. FLEX_TWI_THR /.."
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0: Arbitration won.,1: Arbitration lost. Another master of the TWI bus.."
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bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0: Each data byte has been correctly received by..,1: In Read mode a data byte has not been.."
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bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0: FLEX_TWI_THR has been filled on time.,1: FLEX_TWI_THR has not been filled on time."
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bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0: FLEX_TWI_RHR has not been loaded while RXRDY was..,1: FLEX_TWI_RHR has been loaded while RXRDY was.."
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bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0: No general call has been detected.,1: A general call has been detected. After the.."
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bitfld.long 0x0 4. "SVACC,Slave Access" "0: TWI is not addressed. SVACC is automatically..,1: Indicates that the address decoding sequence has.."
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bitfld.long 0x0 3. "SVREAD,Slave Read" "0: Indicates that a write access is performed by a..,1: Indicates that a read access is performed by a.."
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0: Transmit FIFO is full and cannot accept more data.,1: Transmit FIFO is not full; one or more data can.."
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0: Receive FIFO is empty; no data to read.,1: At least one unread data is in the Receive FIFO."
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0: As soon as a Start is detected.,1: After a Stop or a Repeated Start + an address.."
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wgroup.long 0x624++0x7
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line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
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bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
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bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Enable" "0,1"
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bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
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bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
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bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
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bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Enable" "0,1"
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bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
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bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
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bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
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bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
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bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
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bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
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bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
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bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
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bitfld.long 0x4 16. "MCACK,Master Code Acknowledge Interrupt Disable" "0,1"
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bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
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bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
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bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
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bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 11. "EOSACC,End Of Slave Access Interrupt Disable" "0,1"
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bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
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bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
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bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
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bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
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bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
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bitfld.long 0x4 4. "SVACC,Slave Access Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
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rgroup.long 0x62C++0x7
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line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
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bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
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bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Mask" "0,1"
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bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
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bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
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bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
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bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Mask" "0,1"
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bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
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bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
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bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
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bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Mask" "0,1"
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
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bitfld.long 0x4 11.--12. "ASTATE,Acknowledge State (Slave Sniffer Mode only)" "0: No Acknowledge or Nacknowledge detected after..,1: Acknowledge (A) detected after previously logged..,2: Nacknowledge (NA) detected after previously..,3: Not defined"
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bitfld.long 0x4 10. "PSTATE,Stop State (Slave Sniffer Mode only)" "0: No STOP (P) detected after previous logged data.,1: Stop detected (P) after previous logged data."
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bitfld.long 0x4 8.--9. "SSTATE,Start State (Slave Sniffer Mode only)" "0: No START detected with the logged data,1: START (S) detected with the logged data,2: Repeated START (Sr) detected with the logged data,3: Not defined"
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hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Master or Slave Receive Holding Data"
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rgroup.long 0x630++0x3
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line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Master or Slave Receive Holding Data 3"
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hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Master or Slave Receive Holding Data 2"
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hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Master or Slave Receive Holding Data 1"
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hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Master or Slave Receive Holding Data 0"
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wgroup.long 0x634++0x3
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line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Master or Slave Transmit Holding Data"
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wgroup.long 0x634++0x3
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line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Master or Slave Transmit Holding Data 3"
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hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Master or Slave Transmit Holding Data 2"
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hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Master or Slave Transmit Holding Data 1"
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Master or Slave Transmit Holding Data 0"
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group.long 0x638++0x1B
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line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
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hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
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hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Master Clock Stretch Maximum Cycles"
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hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Slave Clock Stretch Maximum Cycles"
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hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
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line.long 0x4 "FLEX_TWI_HSR,TWI High Speed Register"
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hexmask.long.byte 0x4 0.--7. 1. "MCODE,TWI High Speed Master Code"
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line.long 0x8 "FLEX_TWI_ACR,TWI Alternative Command Register"
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bitfld.long 0x8 25. "NPEC,Next PEC Request (SMBus Mode only)" "0: The next transfer does not use a PEC byte.,1: The next transfer uses a PEC byte."
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bitfld.long 0x8 24. "NDIR,Next Transfer Direction" "0: Write direction.,1: Read direction."
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hexmask.long.byte 0x8 16.--23. 1. "NDATAL,Next Data Length"
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bitfld.long 0x8 9. "PEC,PEC Request (SMBus Mode only)" "0: The transfer does not use a PEC byte.,1: The transfer uses a PEC byte."
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bitfld.long 0x8 8. "DIR,Transfer Direction" "0: Write direction.,1: Read direction."
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hexmask.long.byte 0x8 0.--7. 1. "DATAL,Data Length"
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line.long 0xC "FLEX_TWI_FILTR,TWI Filter Register"
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bitfld.long 0xC 8.--10. "THRES,Digital Filter Threshold" "0: No filtering applied on TWI inputs.,?,?,?,?,?,?,?"
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bitfld.long 0xC 1. "PADFEN,PAD Filter Enable" "0: PAD analog filter is disabled.,1: PAD analog filter is enabled. (The analog filter.."
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bitfld.long 0xC 0. "FILT,RX Digital Filter" "0: No filtering applied on TWI inputs.,1: TWI input filtering is active. (Only in Standard.."
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line.long 0x10 "FLEX_TWI_HSCWGR,TWI High Speed Clock Waveform Generator Register"
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bitfld.long 0x10 16.--18. "HSCKDIV,High Speed Clock Divider" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x10 8.--15. 1. "HSCHDIV,High Speed Clock High Divider"
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hexmask.long.byte 0x10 0.--7. 1. "HSCLDIV,High Speed Clock Low Divider"
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line.long 0x14 "FLEX_TWI_SWMR,TWI Matching Register"
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hexmask.long.byte 0x14 24.--31. 1. "DATAM,Data Match"
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hexmask.long.byte 0x14 16.--22. 1. "SADR3,Slave Address 3"
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hexmask.long.byte 0x14 8.--14. 1. "SADR2,Slave Address 2"
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hexmask.long.byte 0x14 0.--6. 1. "SADR1,Slave Address 1"
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line.long 0x18 "FLEX_TWI_FMR,TWI FIFO Mode Register"
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hexmask.long.byte 0x18 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
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hexmask.long.byte 0x18 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
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bitfld.long 0x18 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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bitfld.long 0x18 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x654++0x3
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line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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rgroup.long 0x660++0x3
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line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
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bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0: No Receive FIFO pointer occurred,1: Receive FIFO pointer error occurred. Receiver.."
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bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0: No Transmit FIFO pointer occurred,1: Transmit FIFO pointer error occurred."
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bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0: Number of unread data in Receive FIFO is below..,1: Number of unread data in Receive FIFO has.."
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bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0: Receive FIFO is not empty.,1: Receive FIFO has been filled since the last read.."
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bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0: Receive FIFO is not empty.,1: Receive FIFO has been emptied since the last.."
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bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0: Number of data in Transmit FIFO is above..,1: Number of data in Transmit FIFO has reached.."
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bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0: Transmit FIFO is not full.,1: Transmit FIFO has been filled since the last.."
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bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0: Transmit FIFO is not empty.,1: Transmit FIFO has been emptied since the last.."
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wgroup.long 0x664++0x7
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line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
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rgroup.long 0x66C++0x3
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line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
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group.long 0x6E4++0x3
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line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
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rgroup.long 0x6E8++0x3
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line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
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newline
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bitfld.long 0x0 0. "WPVS,Write Protect Violation Status" "0: No Write Protection Violation has occurred since..,1: A Write Protection Violation has occurred since.."
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tree.end
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tree "FLEXCOM3"
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base ad:0xE1824000
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group.long 0x0++0x3
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line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
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bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected. USART/TWI..,3: All TWI related protocols are selected (TWI.."
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rgroup.long 0x10++0x3
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line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
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hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
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group.long 0x20++0x3
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line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
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wgroup.long 0x200++0x3
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line.long 0x0 "FLEX_US_CR,USART Control Register"
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bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0: No effect.,1: Disables the Transmit and Receive FIFOs."
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newline
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0: No effect.,1: Enables the Transmit and Receive FIFOs."
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bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0: No effect.,1: Restarts the comparison trigger to enable.."
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bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0: No effect.,1: Clears the Transmit FIFO Lock"
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bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0: No effect.,1: Empties the Receive FIFO."
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bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0: No effect.,1: Empties the Transmit FIFO."
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bitfld.long 0x0 21. "LINWKUP,Send LIN Wakeup Signal" "0: No effect:,1: Sends a wakeup signal on the LIN bus."
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bitfld.long 0x0 20. "LINABT,Abort LIN Transmission" "0: No effect.,1: Aborts the current LIN transmission."
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bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0: No effect.,1: Drives the RTS pin to 0 if FLEX_US_MR.USART_MODE.."
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bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0: No effect.,1: Drives the RTS pin to 1 if FLEX_US_MR.USART_MODE.."
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bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0: No effect,1: Immediately restarts timeout period."
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bitfld.long 0x0 14. "RSTNACK,Reset Non Acknowledge" "0: No effect,1: Resets FLEX_US_CSR.NACK."
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bitfld.long 0x0 13. "RSTIT,Reset Iterations" "0: No effect.,1: Resets FLEX_US_CSR.ITER. No effect if the.."
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bitfld.long 0x0 12. "SENDA,Send Address" "0: No effect.,1: In Multidrop mode only the next character.."
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newline
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bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0: No effect.,1: Starts waiting for a character before clocking.."
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newline
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bitfld.long 0x0 10. "STPBRK,Stop Break" "0: No effect.,1: Stops transmission of the break after a minimum.."
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newline
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bitfld.long 0x0 9. "STTBRK,Start Break" "0: No effect.,1: Starts transmission of a break after the.."
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newline
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bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0: No effect.,1: Resets the status bits PARE FRAME OVRE MANE.."
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newline
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bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0: No effect.,1: Disables the transmitter."
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newline
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bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0: No effect.,1: Enables the transmitter if TXDIS is 0."
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newline
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bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0: No effect.,1: Disables the receiver."
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newline
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bitfld.long 0x0 4. "RXEN,Receiver Enable" "0: No effect.,1: Enables the receiver if RXDIS is 0."
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newline
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bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0: No effect.,1: Resets the transmitter."
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newline
|
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bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0: No effect.,1: Resets the receiver."
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group.long 0x204++0x3
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line.long 0x0 "FLEX_US_MR,USART Mode Register"
|
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bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0: Start frame delimiter is COMMAND or DATA SYNC.,1: Start frame delimiter is one bit."
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newline
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bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0: The Manchester start bit is a 0 to 1 transition,1: The Manchester start bit is a 1 to 0 transition."
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newline
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bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0: Manchester encoder/decoder are disabled.,1: Manchester encoder/decoder are enabled."
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newline
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bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0: The USART does not filter the receive line.,1: The USART filters the receive line using a.."
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newline
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bitfld.long 0x0 24.--26. "MAX_ITERATION,Maximum Number of Automatic Iteration" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x0 23. "INVDATA,Inverted Data" "0: The data field transmitted on TXD line is the..,1: The data field transmitted on TXD line is.."
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bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0: User defined configuration of command or data..,1: The sync field is updated when a character is.."
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bitfld.long 0x0 21. "DSNACK,Disable Successive NACK" "0: NACK is sent on the ISO line as soon as a parity..,1: Successive parity errors are counted up to the.."
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newline
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bitfld.long 0x0 20. "INACK,Inhibit Non Acknowledge" "0: The NACK is generated.,1: The NACK is not generated."
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newline
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bitfld.long 0x0 19. "OVER,Oversampling Mode" "0: 16x Oversampling.,1: 8x Oversampling."
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bitfld.long 0x0 18. "CLKO,Clock Output Select" "0: The USART does not drive the SCK pin..,1: The USART drives the SCK pin if USCLKS does not.."
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bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0: CHRL defines character length.,1: 9-bit character length."
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bitfld.long 0x0 16. "MSBF,Bit Order" "0: Least significant bit is sent/received first.,1: Most significant bit is sent/received first."
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newline
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bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
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newline
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bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
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newline
|
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bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
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newline
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bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0: USART operates in Asynchronous mode (UART).,1: USART operates in Synchronous mode."
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newline
|
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bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
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newline
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bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
|
|
wgroup.long 0x208++0x3
|
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line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
|
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 10. "ITER,Max number of Repetitions Reached Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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wgroup.long 0x208++0x7
|
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line.long 0x0 "FLEX_US_IER_LIN_MODE,USART Interrupt Enable Register"
|
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
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line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
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|
newline
|
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
wgroup.long 0x20C++0x3
|
|
line.long 0x0 "FLEX_US_IDR_LIN_MODE,USART Interrupt Disable Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
rgroup.long 0x210++0x3
|
|
line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Mask" "0,1"
|
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newline
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bitfld.long 0x0 10. "ITER,Max Number of Repetitions Reached Interrupt Mask" "0,1"
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
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rgroup.long 0x210++0x7
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line.long 0x0 "FLEX_US_IMR_LIN_MODE,USART Interrupt Mask Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Mask" "0,1"
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Mask" "0,1"
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Mask" "0,1"
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Mask" "0,1"
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Mask" "0,1"
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Mask" "0,1"
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Mask" "0,1"
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Mask" "0,1"
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "0,1"
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Mask" "0,1"
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
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bitfld.long 0x4 24. "MANE,Manchester Error" "0: No Manchester error has been detected since the..,1: At least one Manchester error has been detected.."
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bitfld.long 0x4 23. "CTS,Image of CTS Input" "0: CTS input is driven low.,1: CTS input is driven high."
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bitfld.long 0x4 22. "CMP,Comparison Status" "0: No received character matched the comparison..,1: A received character matched the comparison.."
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0: No input change has been detected on the CTS pin..,1: At least one input change has been detected on.."
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt" "0: Non acknowledge has not been detected since the..,1: At least one non acknowledge has been detected.."
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bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached" "0: Maximum number of repetitions has not been..,1: Maximum number of repetitions has been reached.."
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bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0: There are characters in either FLEX_US_THR or..,1: There are no characters in FLEX_US_THR nor in.."
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bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0: There has not been a timeout since the last..,1: There has been a timeout since the last Start.."
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bitfld.long 0x4 7. "PARE,Parity Error" "0: No parity error has been detected since the last..,1: At least one parity error has been detected.."
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bitfld.long 0x4 6. "FRAME,Framing Error" "0: No stop bit has been detected low since the last..,1: At least one stop bit has been detected low.."
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bitfld.long 0x4 5. "OVRE,Overrun Error" "0: No overrun error has occurred since the last..,1: At least one overrun error has occurred since.."
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bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0: No break received or end of break detected since..,1: Break received or end of break detected since.."
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bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0: Transmit FIFO is full and cannot accept more data,1: Transmit FIFO is not full; one or more data can.."
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bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0: Receive FIFO is empty; no data to read,1: At least one unread data is in the Receive FIFO"
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rgroup.long 0x214++0x7
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line.long 0x0 "FLEX_US_CSR_LIN_MODE,USART Channel Status Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error" "0: No LIN header timeout error has been detected..,1: A LIN header timeout error has been detected.."
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error" "0: No LIN synch tolerance error has been detected..,1: A LIN synch tolerance error has been detected.."
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error" "0: No LIN slave not responding error has been..,1: A LIN slave not responding error has been.."
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error" "0: No LIN checksum error has been detected since..,1: A LIN checksum error has been detected since the.."
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Error" "0: No LIN identifier parity error has been detected..,1: A LIN identifier parity error has been detected.."
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error" "0: No LIN inconsistent synch field error has been..,1: The USART is configured as a slave node and a.."
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bitfld.long 0x0 25. "LINBE,LIN Bit Error" "0: No bit error has been detected since the last..,1: A bit error has been detected since the last.."
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bitfld.long 0x0 23. "LINBLS,LIN Bus Line Status" "0: LIN bus line is set to 0.,1: LIN bus line is set to 1."
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed" "0: The USART is idle or a LIN transfer is ongoing.,1: A LIN transfer has been completed since the last.."
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received" "0: No LIN identifier has been received since the..,1: At least one LIN identifier has been received.."
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received" "0: No LIN break has received sent since the last..,1: At least one LIN break has been received since.."
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bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0: There are characters in either FLEX_US_THR or..,1: There are no characters in FLEX_US_THR nor in.."
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bitfld.long 0x0 8. "TIMEOUT,Receiver Timeout" "0: There has not been a timeout since the last..,1: There has been a timeout since the last start.."
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bitfld.long 0x0 7. "PARE,Parity Error" "0: No parity error has been detected since the last..,1: At least one parity error has been detected.."
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bitfld.long 0x0 6. "FRAME,Framing Error" "0: No stop bit has been detected low since the last..,1: At least one stop bit has been detected low.."
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bitfld.long 0x0 5. "OVRE,Overrun Error" "0: No overrun error has occurred since the last..,1: At least one overrun error has occurred since.."
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bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0: A character in FLEX_US_THR is waiting to be..,1: There is no character in FLEX_US_THR."
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bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0: No complete character has been received since..,1: At least one complete character has been.."
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line.long 0x4 "FLEX_US_RHR,USART Receive Holding Register"
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bitfld.long 0x4 15. "RXSYNH,Received Sync" "0: Last character received is a data.,1: Last character received is a command."
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hexmask.long.word 0x4 0.--8. 1. "RXCHR,Received Character"
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rgroup.long 0x218++0x3
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line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Characters"
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hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Characters"
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hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Characters"
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hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Characters"
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wgroup.long 0x21C++0x3
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line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
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bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0: The next character sent is encoded as a data.,1: The next character sent is encoded as a command."
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hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
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wgroup.long 0x21C++0x3
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line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
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hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
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hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
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hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
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group.long 0x220++0xB
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line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
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bitfld.long 0x0 16.--18. "FP,Fractional Part" "0: Fractional divider is disabled.,?,?,?,?,?,?,?"
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hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
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line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
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hexmask.long.tbyte 0x4 0.--16. 1. "TO,Timeout Value"
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line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
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hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
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group.long 0x240++0x3
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line.long 0x0 "FLEX_US_FIDI,USART FI DI Ratio Register"
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hexmask.long.word 0x0 0.--15. 1. "FI_DI_RATIO,FI Over DI Ratio Value"
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rgroup.long 0x244++0x3
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line.long 0x0 "FLEX_US_NER,USART Number of Errors Register"
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hexmask.long.byte 0x0 0.--7. 1. "NB_ERRORS,Number of Errors"
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group.long 0x24C++0xF
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line.long 0x0 "FLEX_US_IF,USART IrDA Filter Register"
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hexmask.long.byte 0x0 0.--7. 1. "IRDA_FILTER,IrDA Filter"
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line.long 0x4 "FLEX_US_MAN,USART Manchester Configuration Register"
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bitfld.long 0x4 31. "RXIDLEV,Receiver Idle Value" "0: Receiver line idle value is 0.,1: Receiver line idle value is 1."
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bitfld.long 0x4 30. "DRIFT,Drift Compensation" "0: The USART cannot recover from an important clock..,1: The USART can recover from clock drift. The 16X.."
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bitfld.long 0x4 29. "ONE,Must Be Set to 1" "0,1"
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bitfld.long 0x4 28. "RX_MPOL,Receiver Manchester Polarity" "0: Logic zero is coded as a zero-to-one transition..,1: Logic zero is coded as a one-to-zero transition.."
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bitfld.long 0x4 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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hexmask.long.byte 0x4 16.--19. 1. "RX_PL,Receiver Preamble Length"
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bitfld.long 0x4 12. "TX_MPOL,Transmitter Manchester Polarity" "0: Logic zero is coded as a zero-to-one transition..,1: Logic zero is coded as a one-to-zero transition.."
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bitfld.long 0x4 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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hexmask.long.byte 0x4 0.--3. 1. "TX_PL,Transmitter Preamble Length"
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line.long 0x8 "FLEX_US_LINMR,USART LIN Mode Register"
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bitfld.long 0x8 17. "SYNCDIS,Synchronization Disable" "0: The synchronization procedure is performed in..,1: The synchronization procedure is not performed.."
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bitfld.long 0x8 16. "PDCM,DMAC Mode" "0: The LIN mode register FLEX_US_LINMR is not..,1: The LIN mode register FLEX_US_LINMR (excepting.."
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hexmask.long.byte 0x8 8.--15. 1. "DLC,Data Length Control"
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bitfld.long 0x8 7. "WKUPTYP,Wakeup Signal Type" "0: Setting the LINWKUP bit in the control register..,1: Setting the LINWKUP bit in the control register.."
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bitfld.long 0x8 6. "FSDIS,Frame Slot Mode Disable" "0: The Frame Slot mode is enabled.,1: The Frame Slot mode is disabled."
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bitfld.long 0x8 5. "DLM,Data Length Mode" "0: The response data length is defined by the DLC..,1: The response data length is defined by the bits.."
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bitfld.long 0x8 4. "CHKTYP,Checksum Type" "0: LIN 2.0 'enhanced' checksum,1: LIN 1.3 'classic' checksum"
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bitfld.long 0x8 3. "CHKDIS,Checksum Disable" "0: In master node configuration the checksum is..,1: Whatever the node configuration is the checksum.."
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bitfld.long 0x8 2. "PARDIS,Parity Disable" "0: In master node configuration the identifier..,1: Whatever the node configuration is the.."
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bitfld.long 0x8 0.--1. "NACT,LIN Node Action" "0: The USART transmits the response.,1: The USART receives the response.,2: The USART does not transmit and does not receive..,?"
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line.long 0xC "FLEX_US_LINIR,USART LIN Identifier Register"
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hexmask.long.byte 0xC 0.--7. 1. "IDCHR,Identifier Character"
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rgroup.long 0x25C++0x3
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line.long 0x0 "FLEX_US_LINBRR,USART LIN Baud Rate Register"
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bitfld.long 0x0 16.--18. "LINFP,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x0 0.--15. 1. "LINCD,Clock Divider after Synchronization"
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group.long 0x290++0x3
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line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
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hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
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bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0: The parity is not checked and a bad parity..,1: The parity is checked and a matching condition.."
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bitfld.long 0x0 12.--13. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start..,2: Comparison must be met to receive the current..,?"
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hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
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group.long 0x2A0++0x3
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line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
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hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
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hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
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bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0: RTS pin is not controlled by Receive FIFO..,1: RTS pin is controlled by Receive FIFO thresholds."
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bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x2A4++0x3
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line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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wgroup.long 0x2A8++0x7
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line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
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bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
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rgroup.long 0x2B0++0x7
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line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
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bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Number of unread data in Receive FIFO is above..,1: Number of unread data in Receive FIFO has.."
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newline
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bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0: The Transmit FIFO is not locked.,1: The Transmit FIFO is locked."
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newline
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bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0: No Receive FIFO pointer occurred,1: Receive FIFO pointer error occurred. Receiver.."
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newline
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bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0: No Transmit FIFO pointer occurred,1: Transmit FIFO pointer error occurred."
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newline
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bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Number of unread data in Receive FIFO is below..,1: Number of unread data in Receive FIFO has.."
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newline
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bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Receive FIFO is not empty.,1: Receive FIFO has been filled since the last.."
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newline
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bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Receive FIFO is not empty.,1: Receive FIFO has been emptied since the last.."
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newline
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bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Number of data in Transmit FIFO is above..,1: Number of data in Transmit FIFO has reached.."
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newline
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bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Transmit FIFO is not full.,1: Transmit FIFO has been filled since the last.."
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newline
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bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Transmit FIFO is not empty.,1: Transmit FIFO has been emptied since the last.."
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group.long 0x2E4++0x3
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line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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newline
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
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newline
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
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newline
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection on configuration..,1: Enables the write protection on configuration.."
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rgroup.long 0x2E8++0x3
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line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
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hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
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newline
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
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wgroup.long 0x400++0x3
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line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
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bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0: No effect.,1: Disables the Transmit and Receive FIFOs"
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newline
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0: No effect.,1: Enables the Transmit and Receive FIFOs"
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newline
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bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0: No effect.,1: The current NPCS will be de-asserted after the.."
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newline
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bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0: No effect.,1: Empties the Receive FIFO."
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newline
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bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0: No effect.,1: Empties the Transmit FIFO."
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newline
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bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0: No effect.,1: Restarts the comparison trigger to enable.."
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newline
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bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0: No effect.,1: Reset the SPI. A software-triggered hardware.."
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newline
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bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0: No effect.,1: Disables the SPI."
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newline
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bitfld.long 0x0 0. "SPIEN,SPI Enable" "0: No effect.,1: Enables the SPI to transfer and receive data."
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group.long 0x404++0x3
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line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
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hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
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newline
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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newline
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bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
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newline
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bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0: Local loopback path disabled.,1: Local loopback path enabled."
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newline
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bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0: No Effect. In Master mode a transfer can be..,1: In Master mode a transfer can start only if.."
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newline
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bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0: Mode fault detection is enabled.,1: Mode fault detection is disabled."
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newline
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bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
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newline
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bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0: The chip selects are directly connected to a..,1: The four NPCS chip select lines are connected to.."
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newline
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bitfld.long 0x0 1. "PS,Peripheral Select" "0: Fixed Peripheral Select,1: Variable Peripheral Select"
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newline
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bitfld.long 0x0 0. "MSTR,Master/Slave Mode" "0: SPI is in Slave mode.,1: SPI is in Master mode."
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rgroup.long 0x408++0x3
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line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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newline
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hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
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rgroup.long 0x408++0x3
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line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
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hexmask.long.word 0x0 16.--31. 1. "RD1,Receive Data"
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newline
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hexmask.long.word 0x0 0.--15. 1. "RD0,Receive Data"
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rgroup.long 0x408++0x3
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line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
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hexmask.long.byte 0x0 24.--31. 1. "RD3,Receive Data"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "RD2,Receive Data"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "RD1,Receive Data"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "RD0,Receive Data"
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wgroup.long 0x40C++0x3
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line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
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bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0: No effect.,1: The current NPCS is de-asserted after the.."
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newline
|
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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newline
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hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
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wgroup.long 0x40C++0x3
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line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
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hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
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newline
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hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
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rgroup.long 0x410++0x3
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line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
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bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0: No Receive FIFO pointer occurred,1: Receive FIFO pointer error occurred. Receiver.."
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newline
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bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0: No Transmit FIFO pointer occurred,1: Transmit FIFO pointer error occurred."
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newline
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bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0: Number of unread data in Receive FIFO is below..,1: Number of unread data in Receive FIFO has.."
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newline
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bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0: Receive FIFO is not empty or RXFE flag has been..,1: Receive FIFO has been filled (changing states.."
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newline
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bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0: Receive FIFO is not empty or RXFE flag has been..,1: Receive FIFO has been emptied (changing states.."
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newline
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bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0: Number of data in Transmit FIFO is above..,1: Number of data in Transmit FIFO has reached.."
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newline
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bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0: Transmit FIFO is not full or TXFF flag has been..,1: Transmit FIFO has been filled since the last.."
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newline
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bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0: Transmit FIFO is not empty.,1: Transmit FIFO has been emptied since the last.."
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newline
|
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bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0: SPI is disabled.,1: SPI is enabled."
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newline
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bitfld.long 0x0 12. "SFERR,Slave Frame Error (cleared on read)" "0: There is no frame error detected for a slave..,1: In Slave mode the chip select raised while the.."
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newline
|
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bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0: No received character matched the comparison..,1: A received character matched the comparison.."
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newline
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bitfld.long 0x0 10. "UNDES,Underrun Error Status (Slave mode only) (cleared on read)" "0: No underrun has been detected since the last..,1: A transfer starts whereas no data has been.."
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newline
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0: As soon as data is written in FLEX_SPI_TDR.,1: FLEX_SPI_TDR and internal shift register are.."
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newline
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bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0: No rising edge detected on NSS pin since the..,1: A rising edge occurred on NSS pin since the last.."
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newline
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bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0: No overrun has been detected since the last read..,1: An overrun has occurred since the last read of.."
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newline
|
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bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0: No mode fault has been detected since the last..,1: A mode fault occurred since the last read of.."
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newline
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bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0: Transmit FIFO cannot accept more data.,1: Transmit FIFO can accept data; one or more data.."
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newline
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0: Receive FIFO is empty; no data to read,1: At least one unread data is in the Receive FIFO"
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wgroup.long 0x414++0x7
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line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
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bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
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newline
|
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bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
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line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
|
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bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
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|
newline
|
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bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x41C++0x3
|
|
line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
|
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bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
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newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
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|
newline
|
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x430)++0x3
|
|
line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register x"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
|
|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
|
|
newline
|
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hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
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|
newline
|
|
bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0: The Peripheral Chip Select Line rises as soon as..,1: The Peripheral Chip Select does not rise after.."
|
|
newline
|
|
bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0: The Peripheral Chip Select does not rise between..,1: The Peripheral Chip Select rises systematically.."
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|
newline
|
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bitfld.long 0x0 1. "NCPHA,Clock Phase" "0: Data are changed on the leading edge of SPCK and..,1: Data are captured on the leading edge of SPCK.."
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|
newline
|
|
bitfld.long 0x0 0. "CPOL,Clock Polarity" "0: The inactive state value of SPCK is logic level..,1: The inactive state value of SPCK is logic level.."
|
|
repeat.end
|
|
group.long 0x440++0x3
|
|
line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
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hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
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newline
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bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
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|
rgroup.long 0x444++0x3
|
|
line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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|
newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
group.long 0x448++0x3
|
|
line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0x4E4++0x3
|
|
line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
|
|
rgroup.long 0x4E8++0x3
|
|
line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0: No write protect violation has occurred since..,1: A write protect violation has occurred since the.."
|
|
wgroup.long 0x600++0x3
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line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
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bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0: No effect.,1: Disable the Transmit and Receive FIFOs"
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bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0: No effect.,1: Enable the Transmit and Receive FIFOs"
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bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0: No effect.,1: Clear the TWI FSM lock."
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bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0: No effect.,1: Clear the Transmit Holding Register and set.."
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bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0: No effect.,1: Alternative Command mode disabled."
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bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0: No effect.,1: Alternative Command mode enabled."
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bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0: No effect.,1: If Master mode is enabled send a bus clear.."
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bitfld.long 0x0 14. "PECRQ,PEC Request" "0: No effect.,1: A PEC check or transmission is requested."
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bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0: No effect.,1: SMBus PEC (CRC) generation and check disabled."
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bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0: No effect.,1: SMBus PEC (CRC) generation and check enabled."
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bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0: No effect.,1: SMBus mode disabled."
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bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0: No effect.,1: If SMBDIS = 0 SMBus mode enabled."
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bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0: No effect.,1: High-speed mode disabled."
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bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0: No effect.,1: High-speed mode enabled."
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bitfld.long 0x0 7. "SWRST,Software Reset" "0: No effect.,1: Equivalent to a system reset."
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bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0: No effect.,1: If Master mode is enabled a SMBus Quick Command.."
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bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0: No effect.,1: The Slave mode is disabled. The shifter and.."
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bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0: No effect.,1: Enables the Slave mode (SVDIS must be written to.."
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bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0: No effect.,1: The Master mode is disabled all pending data is.."
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bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0: No effect.,1: Enables the Master mode (MSDIS must be written.."
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bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0: No effect.,1: STOP condition is sent just after completing the.."
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bitfld.long 0x0 0. "START,Send a START Condition" "0: No effect.,1: A frame beginning with a START bit is.."
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wgroup.long 0x600++0x3
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line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
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bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0: No effect.,1: Disable the Transmit and Receive FIFOs."
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bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0: No effect.,1: Enable the Transmit and Receive FIFOs."
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bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0: No effect.,1: Clears the Transmit FIFO Lock."
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bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0: No effect.,1: Empties the Receive FIFO."
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bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0: No effect.,1: Empties the Transmit FIFO."
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bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0: No effect.,1: Alternative Command mode disabled."
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bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0: No effect.,1: Alternative Command mode enabled."
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bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0: No effect.,1: If Master mode is enabled send a bus clear.."
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bitfld.long 0x0 14. "PECRQ,PEC Request" "0: No effect.,1: A PEC check or transmission is requested."
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bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0: No effect.,1: SMBus PEC (CRC) generation and check disabled."
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bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0: No effect.,1: SMBus PEC (CRC) generation and check enabled."
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bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0: No effect.,1: SMBus mode disabled."
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bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0: No effect.,1: If SMBDIS = 0 SMBus mode enabled."
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bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0: No effect.,1: High-speed mode disabled."
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bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0: No effect.,1: High-speed mode enabled."
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bitfld.long 0x0 7. "SWRST,Software Reset" "0: No effect.,1: Equivalent to a system reset."
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bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0: No effect.,1: If Master mode is enabled a SMBus Quick Command.."
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bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0: No effect.,1: The Slave mode is disabled. The shifter and.."
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bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0: No effect.,1: Enables the Slave mode (SVDIS must be written to.."
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bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0: No effect.,1: The Master mode is disabled all pending data is.."
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bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0: No effect.,1: Enables the Master mode (MSDIS must be written.."
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bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0: No effect.,1: STOP condition is sent just after completing the.."
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bitfld.long 0x0 0. "START,Send a START Condition" "0: No effect.,1: A frame beginning with a START bit is.."
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group.long 0x604++0xF
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line.long 0x0 "FLEX_TWI_MMR,TWI Master Mode Register"
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bitfld.long 0x0 24. "NOAP,No Auto-Stop On NACK Error" "0: A stop condition is sent automatically upon..,1: No automatic action is performed upon.."
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hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
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bitfld.long 0x0 13.--14. "SCLRBL,SCL Rise Boost Level" "0,1,2,3"
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bitfld.long 0x0 12. "MREAD,Master Read Direction" "0: Master write direction.,1: Master read direction."
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bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
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line.long 0x4 "FLEX_TWI_SMR,TWI Slave Mode Register"
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bitfld.long 0x4 31. "DATAMEN,Data Matching Enable" "0: Data matching on first received data is disabled.,1: Data matching on first received data is enabled."
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bitfld.long 0x4 30. "SADR3EN,Slave Address 3 Enable" "0: Slave address 3 matching is disabled.,1: Slave address 3 matching is enabled."
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bitfld.long 0x4 29. "SADR2EN,Slave Address 2 Enable" "0: Slave address 2 matching is disabled.,1: Slave address 2 matching is enabled."
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bitfld.long 0x4 28. "SADR1EN,Slave Address 1 Enable" "0: Slave address 1 matching is disabled.,1: Slave address 1 matching is enabled."
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hexmask.long.byte 0x4 16.--22. 1. "SADR,Slave Address"
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hexmask.long.byte 0x4 8.--14. 1. "MASK,Slave Address Mask"
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bitfld.long 0x4 7. "SNIFF,Slave Sniffer Mode" "0: Slave Sniffer mode is disabled.,1: Slave Sniffer mode is enabled."
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bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0: No effect.,1: Clock stretching disabled in Slave mode OVRE and.."
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bitfld.long 0x4 5. "BSEL,TWI Bus Selection" "0: TWI analyzes the TWCK and TWD pins from its TWI..,1: TWI analyzes the TWCK pins TWD from consecutive.."
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bitfld.long 0x4 4. "SADAT,Slave Address Treated as Data" "0: Slave address is handled normally (will not trig..,1: Slave address is handled as data field RXRDY.."
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bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0: Acknowledge of the SMBus Host Header disabled.,1: Acknowledge of the SMBus Host Header enabled."
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bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0: Acknowledge of the SMBus Default Address disabled.,1: Acknowledge of the SMBus Default Address enabled."
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bitfld.long 0x4 0. "NACKEN,Slave Receiver Data Phase NACK Enable" "0: Normal value to be returned in the ACK cycle of..,1: NACK value to be returned in the ACK cycle of.."
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line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
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hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
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line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
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hexmask.long.byte 0xC 24.--29. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
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bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
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bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
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hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
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rgroup.long 0x620++0x3
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line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
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bitfld.long 0x0 26. "SR,Start Repeated" "0: No repeated start has been detected since last..,1: At least one repeated start has been detected.."
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bitfld.long 0x0 25. "SDA,SDA Line Value" "0: SDA line sampled value is '0'.,1: SDA line sampled value is '1'."
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bitfld.long 0x0 24. "SCL,SCL Line Value" "0: SCL line sampled value is '0'.,1: SCL line sampled value is '1.'"
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bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0: The TWI is not locked.,1: The TWI is locked due to frame errors (see.."
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0: No SMBus Host Header Address received.,1: A SMBus Host Header Address was received."
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0: No SMBus Default Address received.,1: A SMBus Default Address was received."
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bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0: No SMBus PEC error occurred.,1: A SMBus PEC error occurred."
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bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0: No SMBus timeout occurred.,1: SMBus timeout occurred."
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bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag" "0: No SMBus slave drives the SMBALERT line.,1: At least one SMBus slave drives the SMBALERT line."
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0: No master code has been received.,1: A master code has been received."
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0: A slave access is being performing.,1: The Slave Access is finished. End Of Slave.."
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bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0: The clock is not stretched.,1: The clock is stretched. FLEX_TWI_THR /.."
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0: Arbitration won.,1: Arbitration lost. Another master of the TWI bus.."
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bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0: Each data byte has been correctly received by..,1: In Read mode a data byte has not been.."
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bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0: FLEX_TWI_THR has been filled on time.,1: FLEX_TWI_THR has not been filled on time."
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bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0: FLEX_TWI_RHR has not been loaded while RXRDY was..,1: FLEX_TWI_RHR has been loaded while RXRDY was.."
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bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0: No general call has been detected.,1: A general call has been detected. After the.."
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bitfld.long 0x0 4. "SVACC,Slave Access" "0: TWI is not addressed. SVACC is automatically..,1: Indicates that the address decoding sequence has.."
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bitfld.long 0x0 3. "SVREAD,Slave Read" "0: Indicates that a write access is performed by a..,1: Indicates that a read access is performed by a.."
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0: Transmit FIFO is full and cannot accept more data,1: Transmit FIFO is not full; one or more data can.."
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0: Receive FIFO is empty; no data to read,1: At least one unread data is in the Receive FIFO"
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0: As soon as a Start is detected.,1: After a Stop or a Repeated Start + an address.."
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rgroup.long 0x620++0x3
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line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
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bitfld.long 0x0 26. "SR,Start Repeated" "0: No repeated start has been detected since last..,1: At least one repeated start has been detected.."
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bitfld.long 0x0 25. "SDA,SDA Line Value" "0: SDA line sampled value is '0'.,1: SDA line sampled value is '1'."
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bitfld.long 0x0 24. "SCL,SCL Line Value" "0: SCL line sampled value is '0'.,1: SCL line sampled value is '1.'"
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bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0: The Transmit FIFO is not locked.,1: The Transmit FIFO is locked."
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0: No SMBus Host Header Address received.,1: A SMBus Host Header Address was received."
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0: No SMBus Default Address received.,1: A SMBus Default Address was received."
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bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0: No SMBus PEC error occurred.,1: A SMBus PEC error occurred."
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bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0: No SMBus timeout occurred.,1: SMBus timeout occurred."
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bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag" "0: No SMBus slave drives the SMBALERT line.,1: At least one SMBus slave drives the SMBALERT line."
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0: No master code has been received.,1: A master code has been received."
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0: A slave access is being performing.,1: The Slave Access is finished. End Of Slave.."
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bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0: The clock is not stretched.,1: The clock is stretched. FLEX_TWI_THR /.."
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0: Arbitration won.,1: Arbitration lost. Another master of the TWI bus.."
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bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0: Each data byte has been correctly received by..,1: In Read mode a data byte has not been.."
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bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0: FLEX_TWI_THR has been filled on time.,1: FLEX_TWI_THR has not been filled on time."
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bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0: FLEX_TWI_RHR has not been loaded while RXRDY was..,1: FLEX_TWI_RHR has been loaded while RXRDY was.."
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bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0: No general call has been detected.,1: A general call has been detected. After the.."
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bitfld.long 0x0 4. "SVACC,Slave Access" "0: TWI is not addressed. SVACC is automatically..,1: Indicates that the address decoding sequence has.."
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bitfld.long 0x0 3. "SVREAD,Slave Read" "0: Indicates that a write access is performed by a..,1: Indicates that a read access is performed by a.."
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0: Transmit FIFO is full and cannot accept more data.,1: Transmit FIFO is not full; one or more data can.."
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0: Receive FIFO is empty; no data to read.,1: At least one unread data is in the Receive FIFO."
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0: As soon as a Start is detected.,1: After a Stop or a Repeated Start + an address.."
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wgroup.long 0x624++0x7
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line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
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bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
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bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Enable" "0,1"
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bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
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bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
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bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
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bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Enable" "0,1"
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bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
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bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
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bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
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bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
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bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
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bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
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bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
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bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
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bitfld.long 0x4 16. "MCACK,Master Code Acknowledge Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
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bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
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bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
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bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
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bitfld.long 0x4 11. "EOSACC,End Of Slave Access Interrupt Disable" "0,1"
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bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
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bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
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bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
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bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
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bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
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|
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bitfld.long 0x4 4. "SVACC,Slave Access Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
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rgroup.long 0x62C++0x7
|
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line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
|
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
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bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
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|
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bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
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|
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
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bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
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bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
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bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
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|
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Mask" "0,1"
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|
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bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
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|
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
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|
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bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
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bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Mask" "0,1"
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
|
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bitfld.long 0x4 11.--12. "ASTATE,Acknowledge State (Slave Sniffer Mode only)" "0: No Acknowledge or Nacknowledge detected after..,1: Acknowledge (A) detected after previously logged..,2: Nacknowledge (NA) detected after previously..,3: Not defined"
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bitfld.long 0x4 10. "PSTATE,Stop State (Slave Sniffer Mode only)" "0: No STOP (P) detected after previous logged data.,1: Stop detected (P) after previous logged data."
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bitfld.long 0x4 8.--9. "SSTATE,Start State (Slave Sniffer Mode only)" "0: No START detected with the logged data,1: START (S) detected with the logged data,2: Repeated START (Sr) detected with the logged data,3: Not defined"
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hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Master or Slave Receive Holding Data"
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rgroup.long 0x630++0x3
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line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Master or Slave Receive Holding Data 3"
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hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Master or Slave Receive Holding Data 2"
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hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Master or Slave Receive Holding Data 1"
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hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Master or Slave Receive Holding Data 0"
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wgroup.long 0x634++0x3
|
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line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Master or Slave Transmit Holding Data"
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wgroup.long 0x634++0x3
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line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Master or Slave Transmit Holding Data 3"
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hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Master or Slave Transmit Holding Data 2"
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hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Master or Slave Transmit Holding Data 1"
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Master or Slave Transmit Holding Data 0"
|
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group.long 0x638++0x1B
|
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line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
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hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
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hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Master Clock Stretch Maximum Cycles"
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hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Slave Clock Stretch Maximum Cycles"
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hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
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line.long 0x4 "FLEX_TWI_HSR,TWI High Speed Register"
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hexmask.long.byte 0x4 0.--7. 1. "MCODE,TWI High Speed Master Code"
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line.long 0x8 "FLEX_TWI_ACR,TWI Alternative Command Register"
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bitfld.long 0x8 25. "NPEC,Next PEC Request (SMBus Mode only)" "0: The next transfer does not use a PEC byte.,1: The next transfer uses a PEC byte."
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bitfld.long 0x8 24. "NDIR,Next Transfer Direction" "0: Write direction.,1: Read direction."
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hexmask.long.byte 0x8 16.--23. 1. "NDATAL,Next Data Length"
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bitfld.long 0x8 9. "PEC,PEC Request (SMBus Mode only)" "0: The transfer does not use a PEC byte.,1: The transfer uses a PEC byte."
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bitfld.long 0x8 8. "DIR,Transfer Direction" "0: Write direction.,1: Read direction."
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hexmask.long.byte 0x8 0.--7. 1. "DATAL,Data Length"
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line.long 0xC "FLEX_TWI_FILTR,TWI Filter Register"
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bitfld.long 0xC 8.--10. "THRES,Digital Filter Threshold" "0: No filtering applied on TWI inputs.,?,?,?,?,?,?,?"
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newline
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bitfld.long 0xC 1. "PADFEN,PAD Filter Enable" "0: PAD analog filter is disabled.,1: PAD analog filter is enabled. (The analog filter.."
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newline
|
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bitfld.long 0xC 0. "FILT,RX Digital Filter" "0: No filtering applied on TWI inputs.,1: TWI input filtering is active. (Only in Standard.."
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line.long 0x10 "FLEX_TWI_HSCWGR,TWI High Speed Clock Waveform Generator Register"
|
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bitfld.long 0x10 16.--18. "HSCKDIV,High Speed Clock Divider" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.byte 0x10 8.--15. 1. "HSCHDIV,High Speed Clock High Divider"
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newline
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hexmask.long.byte 0x10 0.--7. 1. "HSCLDIV,High Speed Clock Low Divider"
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line.long 0x14 "FLEX_TWI_SWMR,TWI Matching Register"
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hexmask.long.byte 0x14 24.--31. 1. "DATAM,Data Match"
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newline
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hexmask.long.byte 0x14 16.--22. 1. "SADR3,Slave Address 3"
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hexmask.long.byte 0x14 8.--14. 1. "SADR2,Slave Address 2"
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hexmask.long.byte 0x14 0.--6. 1. "SADR1,Slave Address 1"
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line.long 0x18 "FLEX_TWI_FMR,TWI FIFO Mode Register"
|
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hexmask.long.byte 0x18 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
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newline
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hexmask.long.byte 0x18 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
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newline
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bitfld.long 0x18 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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newline
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bitfld.long 0x18 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x654++0x3
|
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line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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rgroup.long 0x660++0x3
|
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line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
|
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bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0: No Receive FIFO pointer occurred,1: Receive FIFO pointer error occurred. Receiver.."
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newline
|
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bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0: No Transmit FIFO pointer occurred,1: Transmit FIFO pointer error occurred."
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newline
|
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bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0: Number of unread data in Receive FIFO is below..,1: Number of unread data in Receive FIFO has.."
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newline
|
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bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0: Receive FIFO is not empty.,1: Receive FIFO has been filled since the last read.."
|
|
newline
|
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bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0: Receive FIFO is not empty.,1: Receive FIFO has been emptied since the last.."
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|
newline
|
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bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0: Number of data in Transmit FIFO is above..,1: Number of data in Transmit FIFO has reached.."
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newline
|
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bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0: Transmit FIFO is not full.,1: Transmit FIFO has been filled since the last.."
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newline
|
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bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0: Transmit FIFO is not empty.,1: Transmit FIFO has been emptied since the last.."
|
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wgroup.long 0x664++0x7
|
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line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
|
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
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line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
|
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x66C++0x3
|
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line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
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group.long 0x6E4++0x3
|
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line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
|
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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newline
|
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
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newline
|
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
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newline
|
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
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rgroup.long 0x6E8++0x3
|
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line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
|
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hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
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|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protect Violation Status" "0: No Write Protection Violation has occurred since..,1: A Write Protection Violation has occurred since.."
|
|
tree.end
|
|
tree "FLEXCOM4"
|
|
base ad:0xE2018000
|
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group.long 0x0++0x3
|
|
line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
|
|
bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected. USART/TWI..,3: All TWI related protocols are selected (TWI.."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
|
|
wgroup.long 0x200++0x3
|
|
line.long 0x0 "FLEX_US_CR,USART Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0: No effect.,1: Disables the Transmit and Receive FIFOs."
|
|
newline
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0: No effect.,1: Enables the Transmit and Receive FIFOs."
|
|
newline
|
|
bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0: No effect.,1: Restarts the comparison trigger to enable.."
|
|
newline
|
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bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0: No effect.,1: Clears the Transmit FIFO Lock"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0: No effect.,1: Empties the Receive FIFO."
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0: No effect.,1: Empties the Transmit FIFO."
|
|
newline
|
|
bitfld.long 0x0 21. "LINWKUP,Send LIN Wakeup Signal" "0: No effect:,1: Sends a wakeup signal on the LIN bus."
|
|
newline
|
|
bitfld.long 0x0 20. "LINABT,Abort LIN Transmission" "0: No effect.,1: Aborts the current LIN transmission."
|
|
newline
|
|
bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0: No effect.,1: Drives the RTS pin to 0 if FLEX_US_MR.USART_MODE.."
|
|
newline
|
|
bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0: No effect.,1: Drives the RTS pin to 1 if FLEX_US_MR.USART_MODE.."
|
|
newline
|
|
bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0: No effect,1: Immediately restarts timeout period."
|
|
newline
|
|
bitfld.long 0x0 14. "RSTNACK,Reset Non Acknowledge" "0: No effect,1: Resets FLEX_US_CSR.NACK."
|
|
newline
|
|
bitfld.long 0x0 13. "RSTIT,Reset Iterations" "0: No effect.,1: Resets FLEX_US_CSR.ITER. No effect if the.."
|
|
newline
|
|
bitfld.long 0x0 12. "SENDA,Send Address" "0: No effect.,1: In Multidrop mode only the next character.."
|
|
newline
|
|
bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0: No effect.,1: Starts waiting for a character before clocking.."
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|
newline
|
|
bitfld.long 0x0 10. "STPBRK,Stop Break" "0: No effect.,1: Stops transmission of the break after a minimum.."
|
|
newline
|
|
bitfld.long 0x0 9. "STTBRK,Start Break" "0: No effect.,1: Starts transmission of a break after the.."
|
|
newline
|
|
bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0: No effect.,1: Resets the status bits PARE FRAME OVRE MANE.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0: No effect.,1: Disables the transmitter."
|
|
newline
|
|
bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0: No effect.,1: Enables the transmitter if TXDIS is 0."
|
|
newline
|
|
bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0: No effect.,1: Disables the receiver."
|
|
newline
|
|
bitfld.long 0x0 4. "RXEN,Receiver Enable" "0: No effect.,1: Enables the receiver if RXDIS is 0."
|
|
newline
|
|
bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0: No effect.,1: Resets the transmitter."
|
|
newline
|
|
bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0: No effect.,1: Resets the receiver."
|
|
group.long 0x204++0x3
|
|
line.long 0x0 "FLEX_US_MR,USART Mode Register"
|
|
bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0: Start frame delimiter is COMMAND or DATA SYNC.,1: Start frame delimiter is one bit."
|
|
newline
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bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0: The Manchester start bit is a 0 to 1 transition,1: The Manchester start bit is a 1 to 0 transition."
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bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0: Manchester encoder/decoder are disabled.,1: Manchester encoder/decoder are enabled."
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bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0: The USART does not filter the receive line.,1: The USART filters the receive line using a.."
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bitfld.long 0x0 24.--26. "MAX_ITERATION,Maximum Number of Automatic Iteration" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 23. "INVDATA,Inverted Data" "0: The data field transmitted on TXD line is the..,1: The data field transmitted on TXD line is.."
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bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0: User defined configuration of command or data..,1: The sync field is updated when a character is.."
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bitfld.long 0x0 21. "DSNACK,Disable Successive NACK" "0: NACK is sent on the ISO line as soon as a parity..,1: Successive parity errors are counted up to the.."
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bitfld.long 0x0 20. "INACK,Inhibit Non Acknowledge" "0: The NACK is generated.,1: The NACK is not generated."
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bitfld.long 0x0 19. "OVER,Oversampling Mode" "0: 16x Oversampling.,1: 8x Oversampling."
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bitfld.long 0x0 18. "CLKO,Clock Output Select" "0: The USART does not drive the SCK pin..,1: The USART drives the SCK pin if USCLKS does not.."
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bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0: CHRL defines character length.,1: 9-bit character length."
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bitfld.long 0x0 16. "MSBF,Bit Order" "0: Least significant bit is sent/received first.,1: Most significant bit is sent/received first."
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bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
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bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
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bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
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bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0: USART operates in Asynchronous mode (UART).,1: USART operates in Synchronous mode."
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bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
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bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
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hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
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wgroup.long 0x208++0x3
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line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Enable" "0,1"
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bitfld.long 0x0 10. "ITER,Max number of Repetitions Reached Interrupt Enable" "0,1"
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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wgroup.long 0x208++0x7
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line.long 0x0 "FLEX_US_IER_LIN_MODE,USART Interrupt Enable Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Enable" "0,1"
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Enable" "0,1"
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Enable" "0,1"
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Enable" "0,1"
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Enable" "0,1"
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Enable" "0,1"
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Enable" "0,1"
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Enable" "0,1"
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Enable" "0,1"
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Enable" "0,1"
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
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bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
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bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt Disable" "0,1"
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bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached Interrupt Disable" "0,1"
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bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
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bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
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bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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wgroup.long 0x20C++0x3
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line.long 0x0 "FLEX_US_IDR_LIN_MODE,USART Interrupt Disable Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Disable" "0,1"
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Disable" "0,1"
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Disable" "0,1"
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Disable" "0,1"
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Disable" "0,1"
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Disable" "0,1"
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Disable" "0,1"
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Disable" "0,1"
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Disable" "0,1"
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Disable" "0,1"
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Disable" "0,1"
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Disable" "0,1"
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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rgroup.long 0x210++0x3
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line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Mask" "0,1"
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bitfld.long 0x0 10. "ITER,Max Number of Repetitions Reached Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
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rgroup.long 0x210++0x7
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line.long 0x0 "FLEX_US_IMR_LIN_MODE,USART Interrupt Mask Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Mask" "0,1"
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Mask" "0,1"
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Mask" "0,1"
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Mask" "0,1"
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Mask" "0,1"
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Mask" "0,1"
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Mask" "0,1"
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
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bitfld.long 0x4 24. "MANE,Manchester Error" "0: No Manchester error has been detected since the..,1: At least one Manchester error has been detected.."
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bitfld.long 0x4 23. "CTS,Image of CTS Input" "0: CTS input is driven low.,1: CTS input is driven high."
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bitfld.long 0x4 22. "CMP,Comparison Status" "0: No received character matched the comparison..,1: A received character matched the comparison.."
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0: No input change has been detected on the CTS pin..,1: At least one input change has been detected on.."
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newline
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt" "0: Non acknowledge has not been detected since the..,1: At least one non acknowledge has been detected.."
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bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached" "0: Maximum number of repetitions has not been..,1: Maximum number of repetitions has been reached.."
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newline
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bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0: There are characters in either FLEX_US_THR or..,1: There are no characters in FLEX_US_THR nor in.."
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bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0: There has not been a timeout since the last..,1: There has been a timeout since the last Start.."
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newline
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bitfld.long 0x4 7. "PARE,Parity Error" "0: No parity error has been detected since the last..,1: At least one parity error has been detected.."
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newline
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bitfld.long 0x4 6. "FRAME,Framing Error" "0: No stop bit has been detected low since the last..,1: At least one stop bit has been detected low.."
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newline
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bitfld.long 0x4 5. "OVRE,Overrun Error" "0: No overrun error has occurred since the last..,1: At least one overrun error has occurred since.."
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newline
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bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0: No break received or end of break detected since..,1: Break received or end of break detected since.."
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bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0: Transmit FIFO is full and cannot accept more data,1: Transmit FIFO is not full; one or more data can.."
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bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0: Receive FIFO is empty; no data to read,1: At least one unread data is in the Receive FIFO"
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rgroup.long 0x214++0x7
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line.long 0x0 "FLEX_US_CSR_LIN_MODE,USART Channel Status Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error" "0: No LIN header timeout error has been detected..,1: A LIN header timeout error has been detected.."
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error" "0: No LIN synch tolerance error has been detected..,1: A LIN synch tolerance error has been detected.."
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error" "0: No LIN slave not responding error has been..,1: A LIN slave not responding error has been.."
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error" "0: No LIN checksum error has been detected since..,1: A LIN checksum error has been detected since the.."
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Error" "0: No LIN identifier parity error has been detected..,1: A LIN identifier parity error has been detected.."
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error" "0: No LIN inconsistent synch field error has been..,1: The USART is configured as a slave node and a.."
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newline
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bitfld.long 0x0 25. "LINBE,LIN Bit Error" "0: No bit error has been detected since the last..,1: A bit error has been detected since the last.."
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bitfld.long 0x0 23. "LINBLS,LIN Bus Line Status" "0: LIN bus line is set to 0.,1: LIN bus line is set to 1."
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newline
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed" "0: The USART is idle or a LIN transfer is ongoing.,1: A LIN transfer has been completed since the last.."
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newline
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received" "0: No LIN identifier has been received since the..,1: At least one LIN identifier has been received.."
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received" "0: No LIN break has received sent since the last..,1: At least one LIN break has been received since.."
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bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0: There are characters in either FLEX_US_THR or..,1: There are no characters in FLEX_US_THR nor in.."
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bitfld.long 0x0 8. "TIMEOUT,Receiver Timeout" "0: There has not been a timeout since the last..,1: There has been a timeout since the last start.."
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newline
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bitfld.long 0x0 7. "PARE,Parity Error" "0: No parity error has been detected since the last..,1: At least one parity error has been detected.."
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error" "0: No stop bit has been detected low since the last..,1: At least one stop bit has been detected low.."
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error" "0: No overrun error has occurred since the last..,1: At least one overrun error has occurred since.."
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newline
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bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0: A character in FLEX_US_THR is waiting to be..,1: There is no character in FLEX_US_THR."
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bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0: No complete character has been received since..,1: At least one complete character has been.."
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line.long 0x4 "FLEX_US_RHR,USART Receive Holding Register"
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bitfld.long 0x4 15. "RXSYNH,Received Sync" "0: Last character received is a data.,1: Last character received is a command."
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newline
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hexmask.long.word 0x4 0.--8. 1. "RXCHR,Received Character"
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rgroup.long 0x218++0x3
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line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Characters"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Characters"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Characters"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Characters"
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wgroup.long 0x21C++0x3
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line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
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bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0: The next character sent is encoded as a data.,1: The next character sent is encoded as a command."
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newline
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hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
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wgroup.long 0x21C++0x3
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line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
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hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
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hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
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hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
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group.long 0x220++0xB
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line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
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bitfld.long 0x0 16.--18. "FP,Fractional Part" "0: Fractional divider is disabled.,?,?,?,?,?,?,?"
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hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
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line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
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hexmask.long.tbyte 0x4 0.--16. 1. "TO,Timeout Value"
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line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
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hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
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group.long 0x240++0x3
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line.long 0x0 "FLEX_US_FIDI,USART FI DI Ratio Register"
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hexmask.long.word 0x0 0.--15. 1. "FI_DI_RATIO,FI Over DI Ratio Value"
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rgroup.long 0x244++0x3
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line.long 0x0 "FLEX_US_NER,USART Number of Errors Register"
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hexmask.long.byte 0x0 0.--7. 1. "NB_ERRORS,Number of Errors"
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group.long 0x24C++0xF
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line.long 0x0 "FLEX_US_IF,USART IrDA Filter Register"
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hexmask.long.byte 0x0 0.--7. 1. "IRDA_FILTER,IrDA Filter"
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line.long 0x4 "FLEX_US_MAN,USART Manchester Configuration Register"
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bitfld.long 0x4 31. "RXIDLEV,Receiver Idle Value" "0: Receiver line idle value is 0.,1: Receiver line idle value is 1."
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bitfld.long 0x4 30. "DRIFT,Drift Compensation" "0: The USART cannot recover from an important clock..,1: The USART can recover from clock drift. The 16X.."
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bitfld.long 0x4 29. "ONE,Must Be Set to 1" "0,1"
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bitfld.long 0x4 28. "RX_MPOL,Receiver Manchester Polarity" "0: Logic zero is coded as a zero-to-one transition..,1: Logic zero is coded as a one-to-zero transition.."
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bitfld.long 0x4 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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hexmask.long.byte 0x4 16.--19. 1. "RX_PL,Receiver Preamble Length"
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bitfld.long 0x4 12. "TX_MPOL,Transmitter Manchester Polarity" "0: Logic zero is coded as a zero-to-one transition..,1: Logic zero is coded as a one-to-zero transition.."
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bitfld.long 0x4 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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hexmask.long.byte 0x4 0.--3. 1. "TX_PL,Transmitter Preamble Length"
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line.long 0x8 "FLEX_US_LINMR,USART LIN Mode Register"
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bitfld.long 0x8 17. "SYNCDIS,Synchronization Disable" "0: The synchronization procedure is performed in..,1: The synchronization procedure is not performed.."
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bitfld.long 0x8 16. "PDCM,DMAC Mode" "0: The LIN mode register FLEX_US_LINMR is not..,1: The LIN mode register FLEX_US_LINMR (excepting.."
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hexmask.long.byte 0x8 8.--15. 1. "DLC,Data Length Control"
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bitfld.long 0x8 7. "WKUPTYP,Wakeup Signal Type" "0: Setting the LINWKUP bit in the control register..,1: Setting the LINWKUP bit in the control register.."
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bitfld.long 0x8 6. "FSDIS,Frame Slot Mode Disable" "0: The Frame Slot mode is enabled.,1: The Frame Slot mode is disabled."
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bitfld.long 0x8 5. "DLM,Data Length Mode" "0: The response data length is defined by the DLC..,1: The response data length is defined by the bits.."
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bitfld.long 0x8 4. "CHKTYP,Checksum Type" "0: LIN 2.0 'enhanced' checksum,1: LIN 1.3 'classic' checksum"
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bitfld.long 0x8 3. "CHKDIS,Checksum Disable" "0: In master node configuration the checksum is..,1: Whatever the node configuration is the checksum.."
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bitfld.long 0x8 2. "PARDIS,Parity Disable" "0: In master node configuration the identifier..,1: Whatever the node configuration is the.."
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bitfld.long 0x8 0.--1. "NACT,LIN Node Action" "0: The USART transmits the response.,1: The USART receives the response.,2: The USART does not transmit and does not receive..,?"
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line.long 0xC "FLEX_US_LINIR,USART LIN Identifier Register"
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hexmask.long.byte 0xC 0.--7. 1. "IDCHR,Identifier Character"
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rgroup.long 0x25C++0x3
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line.long 0x0 "FLEX_US_LINBRR,USART LIN Baud Rate Register"
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bitfld.long 0x0 16.--18. "LINFP,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x0 0.--15. 1. "LINCD,Clock Divider after Synchronization"
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group.long 0x290++0x3
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line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
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hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
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bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0: The parity is not checked and a bad parity..,1: The parity is checked and a matching condition.."
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bitfld.long 0x0 12.--13. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start..,2: Comparison must be met to receive the current..,?"
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hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
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group.long 0x2A0++0x3
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line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
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hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
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hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
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bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0: RTS pin is not controlled by Receive FIFO..,1: RTS pin is controlled by Receive FIFO thresholds."
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bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x2A4++0x3
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line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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wgroup.long 0x2A8++0x7
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line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
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bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
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rgroup.long 0x2B0++0x7
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line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
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bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Number of unread data in Receive FIFO is above..,1: Number of unread data in Receive FIFO has.."
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bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0: The Transmit FIFO is not locked.,1: The Transmit FIFO is locked."
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bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0: No Receive FIFO pointer occurred,1: Receive FIFO pointer error occurred. Receiver.."
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bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0: No Transmit FIFO pointer occurred,1: Transmit FIFO pointer error occurred."
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bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Number of unread data in Receive FIFO is below..,1: Number of unread data in Receive FIFO has.."
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bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Receive FIFO is not empty.,1: Receive FIFO has been filled since the last.."
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bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Receive FIFO is not empty.,1: Receive FIFO has been emptied since the last.."
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bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Number of data in Transmit FIFO is above..,1: Number of data in Transmit FIFO has reached.."
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bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Transmit FIFO is not full.,1: Transmit FIFO has been filled since the last.."
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bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Transmit FIFO is not empty.,1: Transmit FIFO has been emptied since the last.."
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group.long 0x2E4++0x3
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line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection on configuration..,1: Enables the write protection on configuration.."
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rgroup.long 0x2E8++0x3
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line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
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hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
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wgroup.long 0x400++0x3
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line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
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bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0: No effect.,1: Disables the Transmit and Receive FIFOs"
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0: No effect.,1: Enables the Transmit and Receive FIFOs"
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bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0: No effect.,1: The current NPCS will be de-asserted after the.."
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bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0: No effect.,1: Empties the Receive FIFO."
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bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0: No effect.,1: Empties the Transmit FIFO."
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bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0: No effect.,1: Restarts the comparison trigger to enable.."
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bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0: No effect.,1: Reset the SPI. A software-triggered hardware.."
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bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0: No effect.,1: Disables the SPI."
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bitfld.long 0x0 0. "SPIEN,SPI Enable" "0: No effect.,1: Enables the SPI to transfer and receive data."
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group.long 0x404++0x3
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line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
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hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
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bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0: Local loopback path disabled.,1: Local loopback path enabled."
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bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0: No Effect. In Master mode a transfer can be..,1: In Master mode a transfer can start only if.."
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bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0: Mode fault detection is enabled.,1: Mode fault detection is disabled."
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bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
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bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0: The chip selects are directly connected to a..,1: The four NPCS chip select lines are connected to.."
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bitfld.long 0x0 1. "PS,Peripheral Select" "0: Fixed Peripheral Select,1: Variable Peripheral Select"
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bitfld.long 0x0 0. "MSTR,Master/Slave Mode" "0: SPI is in Slave mode.,1: SPI is in Master mode."
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rgroup.long 0x408++0x3
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line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
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rgroup.long 0x408++0x3
|
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line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
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hexmask.long.word 0x0 16.--31. 1. "RD1,Receive Data"
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hexmask.long.word 0x0 0.--15. 1. "RD0,Receive Data"
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rgroup.long 0x408++0x3
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line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
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hexmask.long.byte 0x0 24.--31. 1. "RD3,Receive Data"
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hexmask.long.byte 0x0 16.--23. 1. "RD2,Receive Data"
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hexmask.long.byte 0x0 8.--15. 1. "RD1,Receive Data"
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hexmask.long.byte 0x0 0.--7. 1. "RD0,Receive Data"
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wgroup.long 0x40C++0x3
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line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
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bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0: No effect.,1: The current NPCS is de-asserted after the.."
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
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wgroup.long 0x40C++0x3
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line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
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hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
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hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
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rgroup.long 0x410++0x3
|
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line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
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bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0: No Receive FIFO pointer occurred,1: Receive FIFO pointer error occurred. Receiver.."
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bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0: No Transmit FIFO pointer occurred,1: Transmit FIFO pointer error occurred."
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bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0: Number of unread data in Receive FIFO is below..,1: Number of unread data in Receive FIFO has.."
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bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0: Receive FIFO is not empty or RXFE flag has been..,1: Receive FIFO has been filled (changing states.."
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bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0: Receive FIFO is not empty or RXFE flag has been..,1: Receive FIFO has been emptied (changing states.."
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bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0: Number of data in Transmit FIFO is above..,1: Number of data in Transmit FIFO has reached.."
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bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0: Transmit FIFO is not full or TXFF flag has been..,1: Transmit FIFO has been filled since the last.."
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bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0: Transmit FIFO is not empty.,1: Transmit FIFO has been emptied since the last.."
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bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0: SPI is disabled.,1: SPI is enabled."
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bitfld.long 0x0 12. "SFERR,Slave Frame Error (cleared on read)" "0: There is no frame error detected for a slave..,1: In Slave mode the chip select raised while the.."
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bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0: No received character matched the comparison..,1: A received character matched the comparison.."
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newline
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bitfld.long 0x0 10. "UNDES,Underrun Error Status (Slave mode only) (cleared on read)" "0: No underrun has been detected since the last..,1: A transfer starts whereas no data has been.."
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newline
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0: As soon as data is written in FLEX_SPI_TDR.,1: FLEX_SPI_TDR and internal shift register are.."
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newline
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bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0: No rising edge detected on NSS pin since the..,1: A rising edge occurred on NSS pin since the last.."
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newline
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bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0: No overrun has been detected since the last read..,1: An overrun has occurred since the last read of.."
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newline
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bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0: No mode fault has been detected since the last..,1: A mode fault occurred since the last read of.."
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newline
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bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0: Transmit FIFO cannot accept more data.,1: Transmit FIFO can accept data; one or more data.."
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newline
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0: Receive FIFO is empty; no data to read,1: At least one unread data is in the Receive FIFO"
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wgroup.long 0x414++0x7
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line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
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bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
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bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
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newline
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bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
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bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
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newline
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bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
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rgroup.long 0x41C++0x3
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line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
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bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
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newline
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bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
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repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
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group.long ($2+0x430)++0x3
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line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register x"
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hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
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newline
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hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
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newline
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bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0: The Peripheral Chip Select Line rises as soon as..,1: The Peripheral Chip Select does not rise after.."
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newline
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bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0: The Peripheral Chip Select does not rise between..,1: The Peripheral Chip Select rises systematically.."
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newline
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bitfld.long 0x0 1. "NCPHA,Clock Phase" "0: Data are changed on the leading edge of SPCK and..,1: Data are captured on the leading edge of SPCK.."
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newline
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bitfld.long 0x0 0. "CPOL,Clock Polarity" "0: The inactive state value of SPCK is logic level..,1: The inactive state value of SPCK is logic level.."
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repeat.end
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group.long 0x440++0x3
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line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
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newline
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hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
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newline
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bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
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newline
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bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
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rgroup.long 0x444++0x3
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line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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newline
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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group.long 0x448++0x3
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line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
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hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
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newline
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hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
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group.long 0x4E4++0x3
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line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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newline
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
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newline
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
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newline
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
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rgroup.long 0x4E8++0x3
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line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
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hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
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newline
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0: No write protect violation has occurred since..,1: A write protect violation has occurred since the.."
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wgroup.long 0x600++0x3
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line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
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bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0: No effect.,1: Disable the Transmit and Receive FIFOs"
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newline
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bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0: No effect.,1: Enable the Transmit and Receive FIFOs"
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newline
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bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0: No effect.,1: Clear the TWI FSM lock."
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newline
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bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0: No effect.,1: Clear the Transmit Holding Register and set.."
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newline
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bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0: No effect.,1: Alternative Command mode disabled."
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newline
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bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0: No effect.,1: Alternative Command mode enabled."
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newline
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bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0: No effect.,1: If Master mode is enabled send a bus clear.."
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newline
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bitfld.long 0x0 14. "PECRQ,PEC Request" "0: No effect.,1: A PEC check or transmission is requested."
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newline
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bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0: No effect.,1: SMBus PEC (CRC) generation and check disabled."
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newline
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bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0: No effect.,1: SMBus PEC (CRC) generation and check enabled."
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newline
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bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0: No effect.,1: SMBus mode disabled."
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newline
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bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0: No effect.,1: If SMBDIS = 0 SMBus mode enabled."
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newline
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bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0: No effect.,1: High-speed mode disabled."
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newline
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bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0: No effect.,1: High-speed mode enabled."
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newline
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bitfld.long 0x0 7. "SWRST,Software Reset" "0: No effect.,1: Equivalent to a system reset."
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newline
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bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0: No effect.,1: If Master mode is enabled a SMBus Quick Command.."
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newline
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bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0: No effect.,1: The Slave mode is disabled. The shifter and.."
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newline
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bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0: No effect.,1: Enables the Slave mode (SVDIS must be written to.."
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newline
|
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bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0: No effect.,1: The Master mode is disabled all pending data is.."
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newline
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bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0: No effect.,1: Enables the Master mode (MSDIS must be written.."
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newline
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bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0: No effect.,1: STOP condition is sent just after completing the.."
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newline
|
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bitfld.long 0x0 0. "START,Send a START Condition" "0: No effect.,1: A frame beginning with a START bit is.."
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wgroup.long 0x600++0x3
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line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
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bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0: No effect.,1: Disable the Transmit and Receive FIFOs."
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newline
|
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bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0: No effect.,1: Enable the Transmit and Receive FIFOs."
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newline
|
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bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0: No effect.,1: Clears the Transmit FIFO Lock."
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newline
|
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bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0: No effect.,1: Empties the Receive FIFO."
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newline
|
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bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0: No effect.,1: Empties the Transmit FIFO."
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|
newline
|
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bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0: No effect.,1: Alternative Command mode disabled."
|
|
newline
|
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bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0: No effect.,1: Alternative Command mode enabled."
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newline
|
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bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0: No effect.,1: If Master mode is enabled send a bus clear.."
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|
newline
|
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bitfld.long 0x0 14. "PECRQ,PEC Request" "0: No effect.,1: A PEC check or transmission is requested."
|
|
newline
|
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bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0: No effect.,1: SMBus PEC (CRC) generation and check disabled."
|
|
newline
|
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bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0: No effect.,1: SMBus PEC (CRC) generation and check enabled."
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newline
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bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0: No effect.,1: SMBus mode disabled."
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newline
|
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bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0: No effect.,1: If SMBDIS = 0 SMBus mode enabled."
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newline
|
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bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0: No effect.,1: High-speed mode disabled."
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|
newline
|
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bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0: No effect.,1: High-speed mode enabled."
|
|
newline
|
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bitfld.long 0x0 7. "SWRST,Software Reset" "0: No effect.,1: Equivalent to a system reset."
|
|
newline
|
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bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0: No effect.,1: If Master mode is enabled a SMBus Quick Command.."
|
|
newline
|
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bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0: No effect.,1: The Slave mode is disabled. The shifter and.."
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|
newline
|
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bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0: No effect.,1: Enables the Slave mode (SVDIS must be written to.."
|
|
newline
|
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bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0: No effect.,1: The Master mode is disabled all pending data is.."
|
|
newline
|
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bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0: No effect.,1: Enables the Master mode (MSDIS must be written.."
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0: No effect.,1: STOP condition is sent just after completing the.."
|
|
newline
|
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bitfld.long 0x0 0. "START,Send a START Condition" "0: No effect.,1: A frame beginning with a START bit is.."
|
|
group.long 0x604++0xF
|
|
line.long 0x0 "FLEX_TWI_MMR,TWI Master Mode Register"
|
|
bitfld.long 0x0 24. "NOAP,No Auto-Stop On NACK Error" "0: A stop condition is sent automatically upon..,1: No automatic action is performed upon.."
|
|
newline
|
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hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
|
|
newline
|
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bitfld.long 0x0 13.--14. "SCLRBL,SCL Rise Boost Level" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 12. "MREAD,Master Read Direction" "0: Master write direction.,1: Master read direction."
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|
newline
|
|
bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
|
|
line.long 0x4 "FLEX_TWI_SMR,TWI Slave Mode Register"
|
|
bitfld.long 0x4 31. "DATAMEN,Data Matching Enable" "0: Data matching on first received data is disabled.,1: Data matching on first received data is enabled."
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|
newline
|
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bitfld.long 0x4 30. "SADR3EN,Slave Address 3 Enable" "0: Slave address 3 matching is disabled.,1: Slave address 3 matching is enabled."
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|
newline
|
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bitfld.long 0x4 29. "SADR2EN,Slave Address 2 Enable" "0: Slave address 2 matching is disabled.,1: Slave address 2 matching is enabled."
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|
newline
|
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bitfld.long 0x4 28. "SADR1EN,Slave Address 1 Enable" "0: Slave address 1 matching is disabled.,1: Slave address 1 matching is enabled."
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|
newline
|
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hexmask.long.byte 0x4 16.--22. 1. "SADR,Slave Address"
|
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newline
|
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hexmask.long.byte 0x4 8.--14. 1. "MASK,Slave Address Mask"
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|
newline
|
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bitfld.long 0x4 7. "SNIFF,Slave Sniffer Mode" "0: Slave Sniffer mode is disabled.,1: Slave Sniffer mode is enabled."
|
|
newline
|
|
bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0: No effect.,1: Clock stretching disabled in Slave mode OVRE and.."
|
|
newline
|
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bitfld.long 0x4 5. "BSEL,TWI Bus Selection" "0: TWI analyzes the TWCK and TWD pins from its TWI..,1: TWI analyzes the TWCK pins TWD from consecutive.."
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|
newline
|
|
bitfld.long 0x4 4. "SADAT,Slave Address Treated as Data" "0: Slave address is handled normally (will not trig..,1: Slave address is handled as data field RXRDY.."
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|
newline
|
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bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0: Acknowledge of the SMBus Host Header disabled.,1: Acknowledge of the SMBus Host Header enabled."
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|
newline
|
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bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0: Acknowledge of the SMBus Default Address disabled.,1: Acknowledge of the SMBus Default Address enabled."
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|
newline
|
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bitfld.long 0x4 0. "NACKEN,Slave Receiver Data Phase NACK Enable" "0: Normal value to be returned in the ACK cycle of..,1: NACK value to be returned in the ACK cycle of.."
|
|
line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
|
|
line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
hexmask.long.byte 0xC 24.--29. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
|
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newline
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bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
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bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
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hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
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rgroup.long 0x620++0x3
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line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
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bitfld.long 0x0 26. "SR,Start Repeated" "0: No repeated start has been detected since last..,1: At least one repeated start has been detected.."
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bitfld.long 0x0 25. "SDA,SDA Line Value" "0: SDA line sampled value is '0'.,1: SDA line sampled value is '1'."
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bitfld.long 0x0 24. "SCL,SCL Line Value" "0: SCL line sampled value is '0'.,1: SCL line sampled value is '1.'"
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bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0: The TWI is not locked.,1: The TWI is locked due to frame errors (see.."
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0: No SMBus Host Header Address received.,1: A SMBus Host Header Address was received."
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0: No SMBus Default Address received.,1: A SMBus Default Address was received."
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bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0: No SMBus PEC error occurred.,1: A SMBus PEC error occurred."
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bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0: No SMBus timeout occurred.,1: SMBus timeout occurred."
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bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag" "0: No SMBus slave drives the SMBALERT line.,1: At least one SMBus slave drives the SMBALERT line."
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0: No master code has been received.,1: A master code has been received."
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0: A slave access is being performing.,1: The Slave Access is finished. End Of Slave.."
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bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0: The clock is not stretched.,1: The clock is stretched. FLEX_TWI_THR /.."
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0: Arbitration won.,1: Arbitration lost. Another master of the TWI bus.."
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bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0: Each data byte has been correctly received by..,1: In Read mode a data byte has not been.."
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bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0: FLEX_TWI_THR has been filled on time.,1: FLEX_TWI_THR has not been filled on time."
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bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0: FLEX_TWI_RHR has not been loaded while RXRDY was..,1: FLEX_TWI_RHR has been loaded while RXRDY was.."
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bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0: No general call has been detected.,1: A general call has been detected. After the.."
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bitfld.long 0x0 4. "SVACC,Slave Access" "0: TWI is not addressed. SVACC is automatically..,1: Indicates that the address decoding sequence has.."
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bitfld.long 0x0 3. "SVREAD,Slave Read" "0: Indicates that a write access is performed by a..,1: Indicates that a read access is performed by a.."
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0: Transmit FIFO is full and cannot accept more data,1: Transmit FIFO is not full; one or more data can.."
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0: Receive FIFO is empty; no data to read,1: At least one unread data is in the Receive FIFO"
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0: As soon as a Start is detected.,1: After a Stop or a Repeated Start + an address.."
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rgroup.long 0x620++0x3
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line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
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bitfld.long 0x0 26. "SR,Start Repeated" "0: No repeated start has been detected since last..,1: At least one repeated start has been detected.."
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bitfld.long 0x0 25. "SDA,SDA Line Value" "0: SDA line sampled value is '0'.,1: SDA line sampled value is '1'."
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bitfld.long 0x0 24. "SCL,SCL Line Value" "0: SCL line sampled value is '0'.,1: SCL line sampled value is '1.'"
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bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0: The Transmit FIFO is not locked.,1: The Transmit FIFO is locked."
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0: No SMBus Host Header Address received.,1: A SMBus Host Header Address was received."
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0: No SMBus Default Address received.,1: A SMBus Default Address was received."
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bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0: No SMBus PEC error occurred.,1: A SMBus PEC error occurred."
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bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0: No SMBus timeout occurred.,1: SMBus timeout occurred."
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bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag" "0: No SMBus slave drives the SMBALERT line.,1: At least one SMBus slave drives the SMBALERT line."
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0: No master code has been received.,1: A master code has been received."
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0: A slave access is being performing.,1: The Slave Access is finished. End Of Slave.."
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bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0: The clock is not stretched.,1: The clock is stretched. FLEX_TWI_THR /.."
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0: Arbitration won.,1: Arbitration lost. Another master of the TWI bus.."
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bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0: Each data byte has been correctly received by..,1: In Read mode a data byte has not been.."
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bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0: FLEX_TWI_THR has been filled on time.,1: FLEX_TWI_THR has not been filled on time."
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bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0: FLEX_TWI_RHR has not been loaded while RXRDY was..,1: FLEX_TWI_RHR has been loaded while RXRDY was.."
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bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0: No general call has been detected.,1: A general call has been detected. After the.."
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bitfld.long 0x0 4. "SVACC,Slave Access" "0: TWI is not addressed. SVACC is automatically..,1: Indicates that the address decoding sequence has.."
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bitfld.long 0x0 3. "SVREAD,Slave Read" "0: Indicates that a write access is performed by a..,1: Indicates that a read access is performed by a.."
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0: Transmit FIFO is full and cannot accept more data.,1: Transmit FIFO is not full; one or more data can.."
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0: Receive FIFO is empty; no data to read.,1: At least one unread data is in the Receive FIFO."
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0: As soon as a Start is detected.,1: After a Stop or a Repeated Start + an address.."
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wgroup.long 0x624++0x7
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line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
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bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
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bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Enable" "0,1"
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bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
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bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
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bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
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bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Enable" "0,1"
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bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
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bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
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bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
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bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
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bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
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bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
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bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
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bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
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bitfld.long 0x4 16. "MCACK,Master Code Acknowledge Interrupt Disable" "0,1"
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bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
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bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
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bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
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bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
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bitfld.long 0x4 11. "EOSACC,End Of Slave Access Interrupt Disable" "0,1"
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bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
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bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
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bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
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bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
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bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
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bitfld.long 0x4 4. "SVACC,Slave Access Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
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rgroup.long 0x62C++0x7
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line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
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bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
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bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Mask" "0,1"
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bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
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bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
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bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
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bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Mask" "0,1"
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bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
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bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
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bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
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bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Mask" "0,1"
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
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bitfld.long 0x4 11.--12. "ASTATE,Acknowledge State (Slave Sniffer Mode only)" "0: No Acknowledge or Nacknowledge detected after..,1: Acknowledge (A) detected after previously logged..,2: Nacknowledge (NA) detected after previously..,3: Not defined"
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bitfld.long 0x4 10. "PSTATE,Stop State (Slave Sniffer Mode only)" "0: No STOP (P) detected after previous logged data.,1: Stop detected (P) after previous logged data."
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bitfld.long 0x4 8.--9. "SSTATE,Start State (Slave Sniffer Mode only)" "0: No START detected with the logged data,1: START (S) detected with the logged data,2: Repeated START (Sr) detected with the logged data,3: Not defined"
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hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Master or Slave Receive Holding Data"
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rgroup.long 0x630++0x3
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line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Master or Slave Receive Holding Data 3"
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hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Master or Slave Receive Holding Data 2"
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hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Master or Slave Receive Holding Data 1"
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hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Master or Slave Receive Holding Data 0"
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wgroup.long 0x634++0x3
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line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Master or Slave Transmit Holding Data"
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wgroup.long 0x634++0x3
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line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Master or Slave Transmit Holding Data 3"
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hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Master or Slave Transmit Holding Data 2"
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hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Master or Slave Transmit Holding Data 1"
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Master or Slave Transmit Holding Data 0"
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group.long 0x638++0x1B
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line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
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hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
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hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Master Clock Stretch Maximum Cycles"
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hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Slave Clock Stretch Maximum Cycles"
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hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
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line.long 0x4 "FLEX_TWI_HSR,TWI High Speed Register"
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hexmask.long.byte 0x4 0.--7. 1. "MCODE,TWI High Speed Master Code"
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line.long 0x8 "FLEX_TWI_ACR,TWI Alternative Command Register"
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bitfld.long 0x8 25. "NPEC,Next PEC Request (SMBus Mode only)" "0: The next transfer does not use a PEC byte.,1: The next transfer uses a PEC byte."
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bitfld.long 0x8 24. "NDIR,Next Transfer Direction" "0: Write direction.,1: Read direction."
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hexmask.long.byte 0x8 16.--23. 1. "NDATAL,Next Data Length"
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bitfld.long 0x8 9. "PEC,PEC Request (SMBus Mode only)" "0: The transfer does not use a PEC byte.,1: The transfer uses a PEC byte."
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bitfld.long 0x8 8. "DIR,Transfer Direction" "0: Write direction.,1: Read direction."
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hexmask.long.byte 0x8 0.--7. 1. "DATAL,Data Length"
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line.long 0xC "FLEX_TWI_FILTR,TWI Filter Register"
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bitfld.long 0xC 8.--10. "THRES,Digital Filter Threshold" "0: No filtering applied on TWI inputs.,?,?,?,?,?,?,?"
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bitfld.long 0xC 1. "PADFEN,PAD Filter Enable" "0: PAD analog filter is disabled.,1: PAD analog filter is enabled. (The analog filter.."
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bitfld.long 0xC 0. "FILT,RX Digital Filter" "0: No filtering applied on TWI inputs.,1: TWI input filtering is active. (Only in Standard.."
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line.long 0x10 "FLEX_TWI_HSCWGR,TWI High Speed Clock Waveform Generator Register"
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bitfld.long 0x10 16.--18. "HSCKDIV,High Speed Clock Divider" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x10 8.--15. 1. "HSCHDIV,High Speed Clock High Divider"
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hexmask.long.byte 0x10 0.--7. 1. "HSCLDIV,High Speed Clock Low Divider"
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line.long 0x14 "FLEX_TWI_SWMR,TWI Matching Register"
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hexmask.long.byte 0x14 24.--31. 1. "DATAM,Data Match"
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hexmask.long.byte 0x14 16.--22. 1. "SADR3,Slave Address 3"
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hexmask.long.byte 0x14 8.--14. 1. "SADR2,Slave Address 2"
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hexmask.long.byte 0x14 0.--6. 1. "SADR1,Slave Address 1"
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line.long 0x18 "FLEX_TWI_FMR,TWI FIFO Mode Register"
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hexmask.long.byte 0x18 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
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hexmask.long.byte 0x18 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
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bitfld.long 0x18 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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bitfld.long 0x18 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x654++0x3
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line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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rgroup.long 0x660++0x3
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line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
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bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0: No Receive FIFO pointer occurred,1: Receive FIFO pointer error occurred. Receiver.."
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bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0: No Transmit FIFO pointer occurred,1: Transmit FIFO pointer error occurred."
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bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0: Number of unread data in Receive FIFO is below..,1: Number of unread data in Receive FIFO has.."
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bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0: Receive FIFO is not empty.,1: Receive FIFO has been filled since the last read.."
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bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0: Receive FIFO is not empty.,1: Receive FIFO has been emptied since the last.."
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bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0: Number of data in Transmit FIFO is above..,1: Number of data in Transmit FIFO has reached.."
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bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0: Transmit FIFO is not full.,1: Transmit FIFO has been filled since the last.."
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bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0: Transmit FIFO is not empty.,1: Transmit FIFO has been emptied since the last.."
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wgroup.long 0x664++0x7
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line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
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rgroup.long 0x66C++0x3
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line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
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group.long 0x6E4++0x3
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line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
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rgroup.long 0x6E8++0x3
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line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
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bitfld.long 0x0 0. "WPVS,Write Protect Violation Status" "0: No Write Protection Violation has occurred since..,1: A Write Protection Violation has occurred since.."
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tree.end
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tree "FLEXCOM5"
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base ad:0xE201C000
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group.long 0x0++0x3
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line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
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bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected. USART/TWI..,3: All TWI related protocols are selected (TWI.."
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rgroup.long 0x10++0x3
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line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
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hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
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group.long 0x20++0x3
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line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
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wgroup.long 0x200++0x3
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line.long 0x0 "FLEX_US_CR,USART Control Register"
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bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0: No effect.,1: Disables the Transmit and Receive FIFOs."
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0: No effect.,1: Enables the Transmit and Receive FIFOs."
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bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0: No effect.,1: Restarts the comparison trigger to enable.."
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bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0: No effect.,1: Clears the Transmit FIFO Lock"
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bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0: No effect.,1: Empties the Receive FIFO."
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bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0: No effect.,1: Empties the Transmit FIFO."
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bitfld.long 0x0 21. "LINWKUP,Send LIN Wakeup Signal" "0: No effect:,1: Sends a wakeup signal on the LIN bus."
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bitfld.long 0x0 20. "LINABT,Abort LIN Transmission" "0: No effect.,1: Aborts the current LIN transmission."
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bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0: No effect.,1: Drives the RTS pin to 0 if FLEX_US_MR.USART_MODE.."
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bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0: No effect.,1: Drives the RTS pin to 1 if FLEX_US_MR.USART_MODE.."
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bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0: No effect,1: Immediately restarts timeout period."
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bitfld.long 0x0 14. "RSTNACK,Reset Non Acknowledge" "0: No effect,1: Resets FLEX_US_CSR.NACK."
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bitfld.long 0x0 13. "RSTIT,Reset Iterations" "0: No effect.,1: Resets FLEX_US_CSR.ITER. No effect if the.."
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bitfld.long 0x0 12. "SENDA,Send Address" "0: No effect.,1: In Multidrop mode only the next character.."
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bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0: No effect.,1: Starts waiting for a character before clocking.."
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bitfld.long 0x0 10. "STPBRK,Stop Break" "0: No effect.,1: Stops transmission of the break after a minimum.."
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bitfld.long 0x0 9. "STTBRK,Start Break" "0: No effect.,1: Starts transmission of a break after the.."
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bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0: No effect.,1: Resets the status bits PARE FRAME OVRE MANE.."
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bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0: No effect.,1: Disables the transmitter."
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bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0: No effect.,1: Enables the transmitter if TXDIS is 0."
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bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0: No effect.,1: Disables the receiver."
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bitfld.long 0x0 4. "RXEN,Receiver Enable" "0: No effect.,1: Enables the receiver if RXDIS is 0."
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bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0: No effect.,1: Resets the transmitter."
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bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0: No effect.,1: Resets the receiver."
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group.long 0x204++0x3
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line.long 0x0 "FLEX_US_MR,USART Mode Register"
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bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0: Start frame delimiter is COMMAND or DATA SYNC.,1: Start frame delimiter is one bit."
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bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0: The Manchester start bit is a 0 to 1 transition,1: The Manchester start bit is a 1 to 0 transition."
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bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0: Manchester encoder/decoder are disabled.,1: Manchester encoder/decoder are enabled."
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bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0: The USART does not filter the receive line.,1: The USART filters the receive line using a.."
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bitfld.long 0x0 24.--26. "MAX_ITERATION,Maximum Number of Automatic Iteration" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 23. "INVDATA,Inverted Data" "0: The data field transmitted on TXD line is the..,1: The data field transmitted on TXD line is.."
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bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0: User defined configuration of command or data..,1: The sync field is updated when a character is.."
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bitfld.long 0x0 21. "DSNACK,Disable Successive NACK" "0: NACK is sent on the ISO line as soon as a parity..,1: Successive parity errors are counted up to the.."
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bitfld.long 0x0 20. "INACK,Inhibit Non Acknowledge" "0: The NACK is generated.,1: The NACK is not generated."
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bitfld.long 0x0 19. "OVER,Oversampling Mode" "0: 16x Oversampling.,1: 8x Oversampling."
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bitfld.long 0x0 18. "CLKO,Clock Output Select" "0: The USART does not drive the SCK pin..,1: The USART drives the SCK pin if USCLKS does not.."
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bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0: CHRL defines character length.,1: 9-bit character length."
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bitfld.long 0x0 16. "MSBF,Bit Order" "0: Least significant bit is sent/received first.,1: Most significant bit is sent/received first."
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bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
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bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
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bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
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bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0: USART operates in Asynchronous mode (UART).,1: USART operates in Synchronous mode."
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bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
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bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
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hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
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wgroup.long 0x208++0x3
|
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line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
|
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 10. "ITER,Max number of Repetitions Reached Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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wgroup.long 0x208++0x7
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line.long 0x0 "FLEX_US_IER_LIN_MODE,USART Interrupt Enable Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Enable" "0,1"
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Enable" "0,1"
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
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bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
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|
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bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
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|
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
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|
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt Disable" "0,1"
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|
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bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached Interrupt Disable" "0,1"
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|
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bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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|
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bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
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|
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bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
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|
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bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
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|
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bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
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|
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bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
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|
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bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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|
wgroup.long 0x20C++0x3
|
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line.long 0x0 "FLEX_US_IDR_LIN_MODE,USART Interrupt Disable Register"
|
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Disable" "0,1"
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Disable" "0,1"
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|
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Disable" "0,1"
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|
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Disable" "0,1"
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|
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Disable" "0,1"
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|
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Disable" "0,1"
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|
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Disable" "0,1"
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|
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Disable" "0,1"
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|
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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|
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Disable" "0,1"
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Disable" "0,1"
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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rgroup.long 0x210++0x3
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line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Mask" "0,1"
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bitfld.long 0x0 10. "ITER,Max Number of Repetitions Reached Interrupt Mask" "0,1"
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
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rgroup.long 0x210++0x7
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line.long 0x0 "FLEX_US_IMR_LIN_MODE,USART Interrupt Mask Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Mask" "0,1"
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Mask" "0,1"
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Mask" "0,1"
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Mask" "0,1"
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Mask" "0,1"
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Mask" "0,1"
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Mask" "0,1"
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Mask" "0,1"
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "0,1"
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Mask" "0,1"
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
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bitfld.long 0x4 24. "MANE,Manchester Error" "0: No Manchester error has been detected since the..,1: At least one Manchester error has been detected.."
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bitfld.long 0x4 23. "CTS,Image of CTS Input" "0: CTS input is driven low.,1: CTS input is driven high."
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bitfld.long 0x4 22. "CMP,Comparison Status" "0: No received character matched the comparison..,1: A received character matched the comparison.."
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0: No input change has been detected on the CTS pin..,1: At least one input change has been detected on.."
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt" "0: Non acknowledge has not been detected since the..,1: At least one non acknowledge has been detected.."
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bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached" "0: Maximum number of repetitions has not been..,1: Maximum number of repetitions has been reached.."
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bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0: There are characters in either FLEX_US_THR or..,1: There are no characters in FLEX_US_THR nor in.."
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bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0: There has not been a timeout since the last..,1: There has been a timeout since the last Start.."
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bitfld.long 0x4 7. "PARE,Parity Error" "0: No parity error has been detected since the last..,1: At least one parity error has been detected.."
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bitfld.long 0x4 6. "FRAME,Framing Error" "0: No stop bit has been detected low since the last..,1: At least one stop bit has been detected low.."
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bitfld.long 0x4 5. "OVRE,Overrun Error" "0: No overrun error has occurred since the last..,1: At least one overrun error has occurred since.."
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bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0: No break received or end of break detected since..,1: Break received or end of break detected since.."
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bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0: Transmit FIFO is full and cannot accept more data,1: Transmit FIFO is not full; one or more data can.."
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bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0: Receive FIFO is empty; no data to read,1: At least one unread data is in the Receive FIFO"
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rgroup.long 0x214++0x7
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line.long 0x0 "FLEX_US_CSR_LIN_MODE,USART Channel Status Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error" "0: No LIN header timeout error has been detected..,1: A LIN header timeout error has been detected.."
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error" "0: No LIN synch tolerance error has been detected..,1: A LIN synch tolerance error has been detected.."
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error" "0: No LIN slave not responding error has been..,1: A LIN slave not responding error has been.."
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error" "0: No LIN checksum error has been detected since..,1: A LIN checksum error has been detected since the.."
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Error" "0: No LIN identifier parity error has been detected..,1: A LIN identifier parity error has been detected.."
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error" "0: No LIN inconsistent synch field error has been..,1: The USART is configured as a slave node and a.."
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newline
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bitfld.long 0x0 25. "LINBE,LIN Bit Error" "0: No bit error has been detected since the last..,1: A bit error has been detected since the last.."
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bitfld.long 0x0 23. "LINBLS,LIN Bus Line Status" "0: LIN bus line is set to 0.,1: LIN bus line is set to 1."
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newline
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed" "0: The USART is idle or a LIN transfer is ongoing.,1: A LIN transfer has been completed since the last.."
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newline
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received" "0: No LIN identifier has been received since the..,1: At least one LIN identifier has been received.."
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received" "0: No LIN break has received sent since the last..,1: At least one LIN break has been received since.."
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bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0: There are characters in either FLEX_US_THR or..,1: There are no characters in FLEX_US_THR nor in.."
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bitfld.long 0x0 8. "TIMEOUT,Receiver Timeout" "0: There has not been a timeout since the last..,1: There has been a timeout since the last start.."
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newline
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bitfld.long 0x0 7. "PARE,Parity Error" "0: No parity error has been detected since the last..,1: At least one parity error has been detected.."
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error" "0: No stop bit has been detected low since the last..,1: At least one stop bit has been detected low.."
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error" "0: No overrun error has occurred since the last..,1: At least one overrun error has occurred since.."
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newline
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bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0: A character in FLEX_US_THR is waiting to be..,1: There is no character in FLEX_US_THR."
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bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0: No complete character has been received since..,1: At least one complete character has been.."
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line.long 0x4 "FLEX_US_RHR,USART Receive Holding Register"
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bitfld.long 0x4 15. "RXSYNH,Received Sync" "0: Last character received is a data.,1: Last character received is a command."
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newline
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hexmask.long.word 0x4 0.--8. 1. "RXCHR,Received Character"
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rgroup.long 0x218++0x3
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line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Characters"
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hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Characters"
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hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Characters"
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hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Characters"
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wgroup.long 0x21C++0x3
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line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
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bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0: The next character sent is encoded as a data.,1: The next character sent is encoded as a command."
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newline
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hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
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wgroup.long 0x21C++0x3
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line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
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hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
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hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
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group.long 0x220++0xB
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line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
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bitfld.long 0x0 16.--18. "FP,Fractional Part" "0: Fractional divider is disabled.,?,?,?,?,?,?,?"
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newline
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hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
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line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
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hexmask.long.tbyte 0x4 0.--16. 1. "TO,Timeout Value"
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line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
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hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
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group.long 0x240++0x3
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line.long 0x0 "FLEX_US_FIDI,USART FI DI Ratio Register"
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hexmask.long.word 0x0 0.--15. 1. "FI_DI_RATIO,FI Over DI Ratio Value"
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rgroup.long 0x244++0x3
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line.long 0x0 "FLEX_US_NER,USART Number of Errors Register"
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hexmask.long.byte 0x0 0.--7. 1. "NB_ERRORS,Number of Errors"
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group.long 0x24C++0xF
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line.long 0x0 "FLEX_US_IF,USART IrDA Filter Register"
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hexmask.long.byte 0x0 0.--7. 1. "IRDA_FILTER,IrDA Filter"
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line.long 0x4 "FLEX_US_MAN,USART Manchester Configuration Register"
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bitfld.long 0x4 31. "RXIDLEV,Receiver Idle Value" "0: Receiver line idle value is 0.,1: Receiver line idle value is 1."
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newline
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bitfld.long 0x4 30. "DRIFT,Drift Compensation" "0: The USART cannot recover from an important clock..,1: The USART can recover from clock drift. The 16X.."
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bitfld.long 0x4 29. "ONE,Must Be Set to 1" "0,1"
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bitfld.long 0x4 28. "RX_MPOL,Receiver Manchester Polarity" "0: Logic zero is coded as a zero-to-one transition..,1: Logic zero is coded as a one-to-zero transition.."
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bitfld.long 0x4 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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hexmask.long.byte 0x4 16.--19. 1. "RX_PL,Receiver Preamble Length"
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bitfld.long 0x4 12. "TX_MPOL,Transmitter Manchester Polarity" "0: Logic zero is coded as a zero-to-one transition..,1: Logic zero is coded as a one-to-zero transition.."
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bitfld.long 0x4 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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newline
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hexmask.long.byte 0x4 0.--3. 1. "TX_PL,Transmitter Preamble Length"
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line.long 0x8 "FLEX_US_LINMR,USART LIN Mode Register"
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bitfld.long 0x8 17. "SYNCDIS,Synchronization Disable" "0: The synchronization procedure is performed in..,1: The synchronization procedure is not performed.."
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bitfld.long 0x8 16. "PDCM,DMAC Mode" "0: The LIN mode register FLEX_US_LINMR is not..,1: The LIN mode register FLEX_US_LINMR (excepting.."
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newline
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hexmask.long.byte 0x8 8.--15. 1. "DLC,Data Length Control"
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newline
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bitfld.long 0x8 7. "WKUPTYP,Wakeup Signal Type" "0: Setting the LINWKUP bit in the control register..,1: Setting the LINWKUP bit in the control register.."
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newline
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bitfld.long 0x8 6. "FSDIS,Frame Slot Mode Disable" "0: The Frame Slot mode is enabled.,1: The Frame Slot mode is disabled."
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newline
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bitfld.long 0x8 5. "DLM,Data Length Mode" "0: The response data length is defined by the DLC..,1: The response data length is defined by the bits.."
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newline
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bitfld.long 0x8 4. "CHKTYP,Checksum Type" "0: LIN 2.0 'enhanced' checksum,1: LIN 1.3 'classic' checksum"
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newline
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bitfld.long 0x8 3. "CHKDIS,Checksum Disable" "0: In master node configuration the checksum is..,1: Whatever the node configuration is the checksum.."
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bitfld.long 0x8 2. "PARDIS,Parity Disable" "0: In master node configuration the identifier..,1: Whatever the node configuration is the.."
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newline
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bitfld.long 0x8 0.--1. "NACT,LIN Node Action" "0: The USART transmits the response.,1: The USART receives the response.,2: The USART does not transmit and does not receive..,?"
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line.long 0xC "FLEX_US_LINIR,USART LIN Identifier Register"
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hexmask.long.byte 0xC 0.--7. 1. "IDCHR,Identifier Character"
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rgroup.long 0x25C++0x3
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line.long 0x0 "FLEX_US_LINBRR,USART LIN Baud Rate Register"
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bitfld.long 0x0 16.--18. "LINFP,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.word 0x0 0.--15. 1. "LINCD,Clock Divider after Synchronization"
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group.long 0x290++0x3
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line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
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hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
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newline
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bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0: The parity is not checked and a bad parity..,1: The parity is checked and a matching condition.."
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newline
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bitfld.long 0x0 12.--13. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start..,2: Comparison must be met to receive the current..,?"
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hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
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group.long 0x2A0++0x3
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line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
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hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
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hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
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newline
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bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0: RTS pin is not controlled by Receive FIFO..,1: RTS pin is controlled by Receive FIFO thresholds."
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bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x2A4++0x3
|
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line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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wgroup.long 0x2A8++0x7
|
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line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
|
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
|
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bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
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rgroup.long 0x2B0++0x7
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line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
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bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Number of unread data in Receive FIFO is above..,1: Number of unread data in Receive FIFO has.."
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newline
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bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0: The Transmit FIFO is not locked.,1: The Transmit FIFO is locked."
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newline
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bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0: No Receive FIFO pointer occurred,1: Receive FIFO pointer error occurred. Receiver.."
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newline
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bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0: No Transmit FIFO pointer occurred,1: Transmit FIFO pointer error occurred."
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newline
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bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Number of unread data in Receive FIFO is below..,1: Number of unread data in Receive FIFO has.."
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newline
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bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Receive FIFO is not empty.,1: Receive FIFO has been filled since the last.."
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newline
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bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Receive FIFO is not empty.,1: Receive FIFO has been emptied since the last.."
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newline
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bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Number of data in Transmit FIFO is above..,1: Number of data in Transmit FIFO has reached.."
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newline
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bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Transmit FIFO is not full.,1: Transmit FIFO has been filled since the last.."
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newline
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bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Transmit FIFO is not empty.,1: Transmit FIFO has been emptied since the last.."
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group.long 0x2E4++0x3
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line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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newline
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
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newline
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
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newline
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection on configuration..,1: Enables the write protection on configuration.."
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rgroup.long 0x2E8++0x3
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line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
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hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
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newline
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
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wgroup.long 0x400++0x3
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line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
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bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0: No effect.,1: Disables the Transmit and Receive FIFOs"
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newline
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0: No effect.,1: Enables the Transmit and Receive FIFOs"
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newline
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bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0: No effect.,1: The current NPCS will be de-asserted after the.."
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newline
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bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0: No effect.,1: Empties the Receive FIFO."
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newline
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bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0: No effect.,1: Empties the Transmit FIFO."
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newline
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bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0: No effect.,1: Restarts the comparison trigger to enable.."
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newline
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bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0: No effect.,1: Reset the SPI. A software-triggered hardware.."
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newline
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bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0: No effect.,1: Disables the SPI."
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newline
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bitfld.long 0x0 0. "SPIEN,SPI Enable" "0: No effect.,1: Enables the SPI to transfer and receive data."
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group.long 0x404++0x3
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line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
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hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
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newline
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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newline
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bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
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newline
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bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0: Local loopback path disabled.,1: Local loopback path enabled."
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newline
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bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0: No Effect. In Master mode a transfer can be..,1: In Master mode a transfer can start only if.."
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newline
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bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0: Mode fault detection is enabled.,1: Mode fault detection is disabled."
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newline
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bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
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newline
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bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0: The chip selects are directly connected to a..,1: The four NPCS chip select lines are connected to.."
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newline
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bitfld.long 0x0 1. "PS,Peripheral Select" "0: Fixed Peripheral Select,1: Variable Peripheral Select"
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newline
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bitfld.long 0x0 0. "MSTR,Master/Slave Mode" "0: SPI is in Slave mode.,1: SPI is in Master mode."
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rgroup.long 0x408++0x3
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line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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newline
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hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
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rgroup.long 0x408++0x3
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line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
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hexmask.long.word 0x0 16.--31. 1. "RD1,Receive Data"
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newline
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hexmask.long.word 0x0 0.--15. 1. "RD0,Receive Data"
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rgroup.long 0x408++0x3
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line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
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hexmask.long.byte 0x0 24.--31. 1. "RD3,Receive Data"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "RD2,Receive Data"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "RD1,Receive Data"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "RD0,Receive Data"
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wgroup.long 0x40C++0x3
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line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
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bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0: No effect.,1: The current NPCS is de-asserted after the.."
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newline
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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newline
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hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
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wgroup.long 0x40C++0x3
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line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
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hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
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newline
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hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
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rgroup.long 0x410++0x3
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line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
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bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0: No Receive FIFO pointer occurred,1: Receive FIFO pointer error occurred. Receiver.."
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newline
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bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0: No Transmit FIFO pointer occurred,1: Transmit FIFO pointer error occurred."
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newline
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bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0: Number of unread data in Receive FIFO is below..,1: Number of unread data in Receive FIFO has.."
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newline
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bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0: Receive FIFO is not empty or RXFE flag has been..,1: Receive FIFO has been filled (changing states.."
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newline
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bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0: Receive FIFO is not empty or RXFE flag has been..,1: Receive FIFO has been emptied (changing states.."
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newline
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bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0: Number of data in Transmit FIFO is above..,1: Number of data in Transmit FIFO has reached.."
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newline
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bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0: Transmit FIFO is not full or TXFF flag has been..,1: Transmit FIFO has been filled since the last.."
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newline
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bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0: Transmit FIFO is not empty.,1: Transmit FIFO has been emptied since the last.."
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newline
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bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0: SPI is disabled.,1: SPI is enabled."
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newline
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bitfld.long 0x0 12. "SFERR,Slave Frame Error (cleared on read)" "0: There is no frame error detected for a slave..,1: In Slave mode the chip select raised while the.."
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newline
|
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bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0: No received character matched the comparison..,1: A received character matched the comparison.."
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newline
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bitfld.long 0x0 10. "UNDES,Underrun Error Status (Slave mode only) (cleared on read)" "0: No underrun has been detected since the last..,1: A transfer starts whereas no data has been.."
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newline
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0: As soon as data is written in FLEX_SPI_TDR.,1: FLEX_SPI_TDR and internal shift register are.."
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newline
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bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0: No rising edge detected on NSS pin since the..,1: A rising edge occurred on NSS pin since the last.."
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newline
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bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0: No overrun has been detected since the last read..,1: An overrun has occurred since the last read of.."
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newline
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bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0: No mode fault has been detected since the last..,1: A mode fault occurred since the last read of.."
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newline
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bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0: Transmit FIFO cannot accept more data.,1: Transmit FIFO can accept data; one or more data.."
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newline
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0: Receive FIFO is empty; no data to read,1: At least one unread data is in the Receive FIFO"
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wgroup.long 0x414++0x7
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line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
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bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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|
newline
|
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bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
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|
newline
|
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
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newline
|
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bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
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|
newline
|
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bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
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bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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|
newline
|
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bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
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|
newline
|
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bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
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|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
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|
newline
|
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bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
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|
newline
|
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bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
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|
newline
|
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bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
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|
newline
|
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bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x41C++0x3
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line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
|
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bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
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|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
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newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
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|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x430)++0x3
|
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line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register x"
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|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
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|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
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newline
|
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hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
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newline
|
|
bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0: The Peripheral Chip Select Line rises as soon as..,1: The Peripheral Chip Select does not rise after.."
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|
newline
|
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bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0: The Peripheral Chip Select does not rise between..,1: The Peripheral Chip Select rises systematically.."
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newline
|
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bitfld.long 0x0 1. "NCPHA,Clock Phase" "0: Data are changed on the leading edge of SPCK and..,1: Data are captured on the leading edge of SPCK.."
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newline
|
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bitfld.long 0x0 0. "CPOL,Clock Polarity" "0: The inactive state value of SPCK is logic level..,1: The inactive state value of SPCK is logic level.."
|
|
repeat.end
|
|
group.long 0x440++0x3
|
|
line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
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newline
|
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hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
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newline
|
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bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
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newline
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bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
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|
rgroup.long 0x444++0x3
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|
line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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|
group.long 0x448++0x3
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|
line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
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newline
|
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hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
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group.long 0x4E4++0x3
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line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
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rgroup.long 0x4E8++0x3
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line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
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hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
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newline
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0: No write protect violation has occurred since..,1: A write protect violation has occurred since the.."
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wgroup.long 0x600++0x3
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line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
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bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0: No effect.,1: Disable the Transmit and Receive FIFOs"
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bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0: No effect.,1: Enable the Transmit and Receive FIFOs"
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bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0: No effect.,1: Clear the TWI FSM lock."
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bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0: No effect.,1: Clear the Transmit Holding Register and set.."
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bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0: No effect.,1: Alternative Command mode disabled."
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bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0: No effect.,1: Alternative Command mode enabled."
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bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0: No effect.,1: If Master mode is enabled send a bus clear.."
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bitfld.long 0x0 14. "PECRQ,PEC Request" "0: No effect.,1: A PEC check or transmission is requested."
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bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0: No effect.,1: SMBus PEC (CRC) generation and check disabled."
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bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0: No effect.,1: SMBus PEC (CRC) generation and check enabled."
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bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0: No effect.,1: SMBus mode disabled."
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bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0: No effect.,1: If SMBDIS = 0 SMBus mode enabled."
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bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0: No effect.,1: High-speed mode disabled."
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bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0: No effect.,1: High-speed mode enabled."
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bitfld.long 0x0 7. "SWRST,Software Reset" "0: No effect.,1: Equivalent to a system reset."
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newline
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bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0: No effect.,1: If Master mode is enabled a SMBus Quick Command.."
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newline
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bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0: No effect.,1: The Slave mode is disabled. The shifter and.."
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newline
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bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0: No effect.,1: Enables the Slave mode (SVDIS must be written to.."
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newline
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bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0: No effect.,1: The Master mode is disabled all pending data is.."
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newline
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bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0: No effect.,1: Enables the Master mode (MSDIS must be written.."
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bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0: No effect.,1: STOP condition is sent just after completing the.."
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newline
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bitfld.long 0x0 0. "START,Send a START Condition" "0: No effect.,1: A frame beginning with a START bit is.."
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wgroup.long 0x600++0x3
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line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
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bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0: No effect.,1: Disable the Transmit and Receive FIFOs."
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bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0: No effect.,1: Enable the Transmit and Receive FIFOs."
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bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0: No effect.,1: Clears the Transmit FIFO Lock."
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newline
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bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0: No effect.,1: Empties the Receive FIFO."
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newline
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bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0: No effect.,1: Empties the Transmit FIFO."
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bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0: No effect.,1: Alternative Command mode disabled."
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newline
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bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0: No effect.,1: Alternative Command mode enabled."
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newline
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bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0: No effect.,1: If Master mode is enabled send a bus clear.."
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bitfld.long 0x0 14. "PECRQ,PEC Request" "0: No effect.,1: A PEC check or transmission is requested."
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newline
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bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0: No effect.,1: SMBus PEC (CRC) generation and check disabled."
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newline
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bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0: No effect.,1: SMBus PEC (CRC) generation and check enabled."
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newline
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bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0: No effect.,1: SMBus mode disabled."
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newline
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bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0: No effect.,1: If SMBDIS = 0 SMBus mode enabled."
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newline
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bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0: No effect.,1: High-speed mode disabled."
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newline
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bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0: No effect.,1: High-speed mode enabled."
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newline
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bitfld.long 0x0 7. "SWRST,Software Reset" "0: No effect.,1: Equivalent to a system reset."
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newline
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bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0: No effect.,1: If Master mode is enabled a SMBus Quick Command.."
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newline
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bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0: No effect.,1: The Slave mode is disabled. The shifter and.."
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newline
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bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0: No effect.,1: Enables the Slave mode (SVDIS must be written to.."
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newline
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bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0: No effect.,1: The Master mode is disabled all pending data is.."
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newline
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bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0: No effect.,1: Enables the Master mode (MSDIS must be written.."
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newline
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bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0: No effect.,1: STOP condition is sent just after completing the.."
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newline
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bitfld.long 0x0 0. "START,Send a START Condition" "0: No effect.,1: A frame beginning with a START bit is.."
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group.long 0x604++0xF
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line.long 0x0 "FLEX_TWI_MMR,TWI Master Mode Register"
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bitfld.long 0x0 24. "NOAP,No Auto-Stop On NACK Error" "0: A stop condition is sent automatically upon..,1: No automatic action is performed upon.."
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newline
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hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
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newline
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bitfld.long 0x0 13.--14. "SCLRBL,SCL Rise Boost Level" "0,1,2,3"
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newline
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bitfld.long 0x0 12. "MREAD,Master Read Direction" "0: Master write direction.,1: Master read direction."
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newline
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bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
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line.long 0x4 "FLEX_TWI_SMR,TWI Slave Mode Register"
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bitfld.long 0x4 31. "DATAMEN,Data Matching Enable" "0: Data matching on first received data is disabled.,1: Data matching on first received data is enabled."
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newline
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bitfld.long 0x4 30. "SADR3EN,Slave Address 3 Enable" "0: Slave address 3 matching is disabled.,1: Slave address 3 matching is enabled."
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newline
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bitfld.long 0x4 29. "SADR2EN,Slave Address 2 Enable" "0: Slave address 2 matching is disabled.,1: Slave address 2 matching is enabled."
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newline
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bitfld.long 0x4 28. "SADR1EN,Slave Address 1 Enable" "0: Slave address 1 matching is disabled.,1: Slave address 1 matching is enabled."
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newline
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hexmask.long.byte 0x4 16.--22. 1. "SADR,Slave Address"
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newline
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hexmask.long.byte 0x4 8.--14. 1. "MASK,Slave Address Mask"
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newline
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bitfld.long 0x4 7. "SNIFF,Slave Sniffer Mode" "0: Slave Sniffer mode is disabled.,1: Slave Sniffer mode is enabled."
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newline
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bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0: No effect.,1: Clock stretching disabled in Slave mode OVRE and.."
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newline
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bitfld.long 0x4 5. "BSEL,TWI Bus Selection" "0: TWI analyzes the TWCK and TWD pins from its TWI..,1: TWI analyzes the TWCK pins TWD from consecutive.."
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newline
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bitfld.long 0x4 4. "SADAT,Slave Address Treated as Data" "0: Slave address is handled normally (will not trig..,1: Slave address is handled as data field RXRDY.."
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newline
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bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0: Acknowledge of the SMBus Host Header disabled.,1: Acknowledge of the SMBus Host Header enabled."
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newline
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bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0: Acknowledge of the SMBus Default Address disabled.,1: Acknowledge of the SMBus Default Address enabled."
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newline
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bitfld.long 0x4 0. "NACKEN,Slave Receiver Data Phase NACK Enable" "0: Normal value to be returned in the ACK cycle of..,1: NACK value to be returned in the ACK cycle of.."
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line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
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hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
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line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
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hexmask.long.byte 0xC 24.--29. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
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newline
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bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
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newline
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bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
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newline
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hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
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rgroup.long 0x620++0x3
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line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
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bitfld.long 0x0 26. "SR,Start Repeated" "0: No repeated start has been detected since last..,1: At least one repeated start has been detected.."
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bitfld.long 0x0 25. "SDA,SDA Line Value" "0: SDA line sampled value is '0'.,1: SDA line sampled value is '1'."
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newline
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bitfld.long 0x0 24. "SCL,SCL Line Value" "0: SCL line sampled value is '0'.,1: SCL line sampled value is '1.'"
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newline
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bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0: The TWI is not locked.,1: The TWI is locked due to frame errors (see.."
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newline
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0: No SMBus Host Header Address received.,1: A SMBus Host Header Address was received."
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newline
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0: No SMBus Default Address received.,1: A SMBus Default Address was received."
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newline
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bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0: No SMBus PEC error occurred.,1: A SMBus PEC error occurred."
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newline
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bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0: No SMBus timeout occurred.,1: SMBus timeout occurred."
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newline
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bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag" "0: No SMBus slave drives the SMBALERT line.,1: At least one SMBus slave drives the SMBALERT line."
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newline
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0: No master code has been received.,1: A master code has been received."
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newline
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0: A slave access is being performing.,1: The Slave Access is finished. End Of Slave.."
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newline
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bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0: The clock is not stretched.,1: The clock is stretched. FLEX_TWI_THR /.."
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newline
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0: Arbitration won.,1: Arbitration lost. Another master of the TWI bus.."
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newline
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bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0: Each data byte has been correctly received by..,1: In Read mode a data byte has not been.."
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newline
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bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0: FLEX_TWI_THR has been filled on time.,1: FLEX_TWI_THR has not been filled on time."
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newline
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bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0: FLEX_TWI_RHR has not been loaded while RXRDY was..,1: FLEX_TWI_RHR has been loaded while RXRDY was.."
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newline
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bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0: No general call has been detected.,1: A general call has been detected. After the.."
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newline
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bitfld.long 0x0 4. "SVACC,Slave Access" "0: TWI is not addressed. SVACC is automatically..,1: Indicates that the address decoding sequence has.."
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newline
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bitfld.long 0x0 3. "SVREAD,Slave Read" "0: Indicates that a write access is performed by a..,1: Indicates that a read access is performed by a.."
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newline
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0: Transmit FIFO is full and cannot accept more data,1: Transmit FIFO is not full; one or more data can.."
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newline
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0: Receive FIFO is empty; no data to read,1: At least one unread data is in the Receive FIFO"
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newline
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0: As soon as a Start is detected.,1: After a Stop or a Repeated Start + an address.."
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rgroup.long 0x620++0x3
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line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
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bitfld.long 0x0 26. "SR,Start Repeated" "0: No repeated start has been detected since last..,1: At least one repeated start has been detected.."
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newline
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bitfld.long 0x0 25. "SDA,SDA Line Value" "0: SDA line sampled value is '0'.,1: SDA line sampled value is '1'."
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newline
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bitfld.long 0x0 24. "SCL,SCL Line Value" "0: SCL line sampled value is '0'.,1: SCL line sampled value is '1.'"
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newline
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bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0: The Transmit FIFO is not locked.,1: The Transmit FIFO is locked."
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newline
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0: No SMBus Host Header Address received.,1: A SMBus Host Header Address was received."
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newline
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0: No SMBus Default Address received.,1: A SMBus Default Address was received."
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newline
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bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0: No SMBus PEC error occurred.,1: A SMBus PEC error occurred."
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newline
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bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0: No SMBus timeout occurred.,1: SMBus timeout occurred."
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newline
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bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag" "0: No SMBus slave drives the SMBALERT line.,1: At least one SMBus slave drives the SMBALERT line."
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newline
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0: No master code has been received.,1: A master code has been received."
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newline
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0: A slave access is being performing.,1: The Slave Access is finished. End Of Slave.."
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newline
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bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0: The clock is not stretched.,1: The clock is stretched. FLEX_TWI_THR /.."
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newline
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0: Arbitration won.,1: Arbitration lost. Another master of the TWI bus.."
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newline
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bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0: Each data byte has been correctly received by..,1: In Read mode a data byte has not been.."
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newline
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bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0: FLEX_TWI_THR has been filled on time.,1: FLEX_TWI_THR has not been filled on time."
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newline
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bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0: FLEX_TWI_RHR has not been loaded while RXRDY was..,1: FLEX_TWI_RHR has been loaded while RXRDY was.."
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newline
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bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0: No general call has been detected.,1: A general call has been detected. After the.."
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newline
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bitfld.long 0x0 4. "SVACC,Slave Access" "0: TWI is not addressed. SVACC is automatically..,1: Indicates that the address decoding sequence has.."
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newline
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bitfld.long 0x0 3. "SVREAD,Slave Read" "0: Indicates that a write access is performed by a..,1: Indicates that a read access is performed by a.."
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newline
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0: Transmit FIFO is full and cannot accept more data.,1: Transmit FIFO is not full; one or more data can.."
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newline
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0: Receive FIFO is empty; no data to read.,1: At least one unread data is in the Receive FIFO."
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newline
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0: As soon as a Start is detected.,1: After a Stop or a Repeated Start + an address.."
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wgroup.long 0x624++0x7
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line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
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bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
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bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
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bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
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bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
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bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
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bitfld.long 0x4 16. "MCACK,Master Code Acknowledge Interrupt Disable" "0,1"
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bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
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bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
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bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
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bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
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bitfld.long 0x4 11. "EOSACC,End Of Slave Access Interrupt Disable" "0,1"
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bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
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bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
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bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
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bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
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bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
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bitfld.long 0x4 4. "SVACC,Slave Access Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
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rgroup.long 0x62C++0x7
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line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
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bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
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bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Mask" "0,1"
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bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
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bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
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bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
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bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Mask" "0,1"
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bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
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bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
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bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
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bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Mask" "0,1"
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
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bitfld.long 0x4 11.--12. "ASTATE,Acknowledge State (Slave Sniffer Mode only)" "0: No Acknowledge or Nacknowledge detected after..,1: Acknowledge (A) detected after previously logged..,2: Nacknowledge (NA) detected after previously..,3: Not defined"
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bitfld.long 0x4 10. "PSTATE,Stop State (Slave Sniffer Mode only)" "0: No STOP (P) detected after previous logged data.,1: Stop detected (P) after previous logged data."
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bitfld.long 0x4 8.--9. "SSTATE,Start State (Slave Sniffer Mode only)" "0: No START detected with the logged data,1: START (S) detected with the logged data,2: Repeated START (Sr) detected with the logged data,3: Not defined"
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hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Master or Slave Receive Holding Data"
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rgroup.long 0x630++0x3
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line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Master or Slave Receive Holding Data 3"
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hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Master or Slave Receive Holding Data 2"
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hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Master or Slave Receive Holding Data 1"
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hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Master or Slave Receive Holding Data 0"
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wgroup.long 0x634++0x3
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line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Master or Slave Transmit Holding Data"
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wgroup.long 0x634++0x3
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line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Master or Slave Transmit Holding Data 3"
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hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Master or Slave Transmit Holding Data 2"
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hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Master or Slave Transmit Holding Data 1"
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Master or Slave Transmit Holding Data 0"
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group.long 0x638++0x1B
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line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
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hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
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hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Master Clock Stretch Maximum Cycles"
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hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Slave Clock Stretch Maximum Cycles"
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hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
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line.long 0x4 "FLEX_TWI_HSR,TWI High Speed Register"
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hexmask.long.byte 0x4 0.--7. 1. "MCODE,TWI High Speed Master Code"
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line.long 0x8 "FLEX_TWI_ACR,TWI Alternative Command Register"
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bitfld.long 0x8 25. "NPEC,Next PEC Request (SMBus Mode only)" "0: The next transfer does not use a PEC byte.,1: The next transfer uses a PEC byte."
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bitfld.long 0x8 24. "NDIR,Next Transfer Direction" "0: Write direction.,1: Read direction."
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hexmask.long.byte 0x8 16.--23. 1. "NDATAL,Next Data Length"
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bitfld.long 0x8 9. "PEC,PEC Request (SMBus Mode only)" "0: The transfer does not use a PEC byte.,1: The transfer uses a PEC byte."
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bitfld.long 0x8 8. "DIR,Transfer Direction" "0: Write direction.,1: Read direction."
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hexmask.long.byte 0x8 0.--7. 1. "DATAL,Data Length"
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line.long 0xC "FLEX_TWI_FILTR,TWI Filter Register"
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bitfld.long 0xC 8.--10. "THRES,Digital Filter Threshold" "0: No filtering applied on TWI inputs.,?,?,?,?,?,?,?"
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newline
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bitfld.long 0xC 1. "PADFEN,PAD Filter Enable" "0: PAD analog filter is disabled.,1: PAD analog filter is enabled. (The analog filter.."
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newline
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bitfld.long 0xC 0. "FILT,RX Digital Filter" "0: No filtering applied on TWI inputs.,1: TWI input filtering is active. (Only in Standard.."
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line.long 0x10 "FLEX_TWI_HSCWGR,TWI High Speed Clock Waveform Generator Register"
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bitfld.long 0x10 16.--18. "HSCKDIV,High Speed Clock Divider" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x10 8.--15. 1. "HSCHDIV,High Speed Clock High Divider"
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newline
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hexmask.long.byte 0x10 0.--7. 1. "HSCLDIV,High Speed Clock Low Divider"
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line.long 0x14 "FLEX_TWI_SWMR,TWI Matching Register"
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hexmask.long.byte 0x14 24.--31. 1. "DATAM,Data Match"
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hexmask.long.byte 0x14 16.--22. 1. "SADR3,Slave Address 3"
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hexmask.long.byte 0x14 8.--14. 1. "SADR2,Slave Address 2"
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hexmask.long.byte 0x14 0.--6. 1. "SADR1,Slave Address 1"
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line.long 0x18 "FLEX_TWI_FMR,TWI FIFO Mode Register"
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hexmask.long.byte 0x18 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
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newline
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hexmask.long.byte 0x18 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
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newline
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bitfld.long 0x18 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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newline
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bitfld.long 0x18 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x654++0x3
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line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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newline
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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rgroup.long 0x660++0x3
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line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
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bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0: No Receive FIFO pointer occurred,1: Receive FIFO pointer error occurred. Receiver.."
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newline
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bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0: No Transmit FIFO pointer occurred,1: Transmit FIFO pointer error occurred."
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newline
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bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0: Number of unread data in Receive FIFO is below..,1: Number of unread data in Receive FIFO has.."
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newline
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bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0: Receive FIFO is not empty.,1: Receive FIFO has been filled since the last read.."
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newline
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bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0: Receive FIFO is not empty.,1: Receive FIFO has been emptied since the last.."
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newline
|
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bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0: Number of data in Transmit FIFO is above..,1: Number of data in Transmit FIFO has reached.."
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newline
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bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0: Transmit FIFO is not full.,1: Transmit FIFO has been filled since the last.."
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newline
|
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bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0: Transmit FIFO is not empty.,1: Transmit FIFO has been emptied since the last.."
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wgroup.long 0x664++0x7
|
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line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
|
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
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rgroup.long 0x66C++0x3
|
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line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
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group.long 0x6E4++0x3
|
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line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
|
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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newline
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
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newline
|
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
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newline
|
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
|
|
rgroup.long 0x6E8++0x3
|
|
line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
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|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protect Violation Status" "0: No Write Protection Violation has occurred since..,1: A Write Protection Violation has occurred since.."
|
|
tree.end
|
|
tree "FLEXCOM6"
|
|
base ad:0xE2020000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
|
|
bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected. USART/TWI..,3: All TWI related protocols are selected (TWI.."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
|
|
wgroup.long 0x200++0x3
|
|
line.long 0x0 "FLEX_US_CR,USART Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0: No effect.,1: Disables the Transmit and Receive FIFOs."
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|
newline
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0: No effect.,1: Enables the Transmit and Receive FIFOs."
|
|
newline
|
|
bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0: No effect.,1: Restarts the comparison trigger to enable.."
|
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newline
|
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bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0: No effect.,1: Clears the Transmit FIFO Lock"
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|
newline
|
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bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0: No effect.,1: Empties the Receive FIFO."
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|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0: No effect.,1: Empties the Transmit FIFO."
|
|
newline
|
|
bitfld.long 0x0 21. "LINWKUP,Send LIN Wakeup Signal" "0: No effect:,1: Sends a wakeup signal on the LIN bus."
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|
newline
|
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bitfld.long 0x0 20. "LINABT,Abort LIN Transmission" "0: No effect.,1: Aborts the current LIN transmission."
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|
newline
|
|
bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0: No effect.,1: Drives the RTS pin to 0 if FLEX_US_MR.USART_MODE.."
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|
newline
|
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bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0: No effect.,1: Drives the RTS pin to 1 if FLEX_US_MR.USART_MODE.."
|
|
newline
|
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bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0: No effect,1: Immediately restarts timeout period."
|
|
newline
|
|
bitfld.long 0x0 14. "RSTNACK,Reset Non Acknowledge" "0: No effect,1: Resets FLEX_US_CSR.NACK."
|
|
newline
|
|
bitfld.long 0x0 13. "RSTIT,Reset Iterations" "0: No effect.,1: Resets FLEX_US_CSR.ITER. No effect if the.."
|
|
newline
|
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bitfld.long 0x0 12. "SENDA,Send Address" "0: No effect.,1: In Multidrop mode only the next character.."
|
|
newline
|
|
bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0: No effect.,1: Starts waiting for a character before clocking.."
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|
newline
|
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bitfld.long 0x0 10. "STPBRK,Stop Break" "0: No effect.,1: Stops transmission of the break after a minimum.."
|
|
newline
|
|
bitfld.long 0x0 9. "STTBRK,Start Break" "0: No effect.,1: Starts transmission of a break after the.."
|
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newline
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bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0: No effect.,1: Resets the status bits PARE FRAME OVRE MANE.."
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bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0: No effect.,1: Disables the transmitter."
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bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0: No effect.,1: Enables the transmitter if TXDIS is 0."
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bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0: No effect.,1: Disables the receiver."
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bitfld.long 0x0 4. "RXEN,Receiver Enable" "0: No effect.,1: Enables the receiver if RXDIS is 0."
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bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0: No effect.,1: Resets the transmitter."
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bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0: No effect.,1: Resets the receiver."
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group.long 0x204++0x3
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line.long 0x0 "FLEX_US_MR,USART Mode Register"
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bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0: Start frame delimiter is COMMAND or DATA SYNC.,1: Start frame delimiter is one bit."
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bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0: The Manchester start bit is a 0 to 1 transition,1: The Manchester start bit is a 1 to 0 transition."
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bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0: Manchester encoder/decoder are disabled.,1: Manchester encoder/decoder are enabled."
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bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0: The USART does not filter the receive line.,1: The USART filters the receive line using a.."
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bitfld.long 0x0 24.--26. "MAX_ITERATION,Maximum Number of Automatic Iteration" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 23. "INVDATA,Inverted Data" "0: The data field transmitted on TXD line is the..,1: The data field transmitted on TXD line is.."
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bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0: User defined configuration of command or data..,1: The sync field is updated when a character is.."
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bitfld.long 0x0 21. "DSNACK,Disable Successive NACK" "0: NACK is sent on the ISO line as soon as a parity..,1: Successive parity errors are counted up to the.."
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bitfld.long 0x0 20. "INACK,Inhibit Non Acknowledge" "0: The NACK is generated.,1: The NACK is not generated."
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bitfld.long 0x0 19. "OVER,Oversampling Mode" "0: 16x Oversampling.,1: 8x Oversampling."
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bitfld.long 0x0 18. "CLKO,Clock Output Select" "0: The USART does not drive the SCK pin..,1: The USART drives the SCK pin if USCLKS does not.."
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bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0: CHRL defines character length.,1: 9-bit character length."
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bitfld.long 0x0 16. "MSBF,Bit Order" "0: Least significant bit is sent/received first.,1: Most significant bit is sent/received first."
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bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
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bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
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bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
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bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0: USART operates in Asynchronous mode (UART).,1: USART operates in Synchronous mode."
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bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
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bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
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hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
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wgroup.long 0x208++0x3
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line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Enable" "0,1"
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bitfld.long 0x0 10. "ITER,Max number of Repetitions Reached Interrupt Enable" "0,1"
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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wgroup.long 0x208++0x7
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line.long 0x0 "FLEX_US_IER_LIN_MODE,USART Interrupt Enable Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Enable" "0,1"
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Enable" "0,1"
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Enable" "0,1"
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Enable" "0,1"
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Enable" "0,1"
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Enable" "0,1"
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Enable" "0,1"
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Enable" "0,1"
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Enable" "0,1"
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Enable" "0,1"
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
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bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
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bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt Disable" "0,1"
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bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached Interrupt Disable" "0,1"
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bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
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bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
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bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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wgroup.long 0x20C++0x3
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line.long 0x0 "FLEX_US_IDR_LIN_MODE,USART Interrupt Disable Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Disable" "0,1"
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Disable" "0,1"
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Disable" "0,1"
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Disable" "0,1"
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Disable" "0,1"
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Disable" "0,1"
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Disable" "0,1"
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Disable" "0,1"
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Disable" "0,1"
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Disable" "0,1"
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Disable" "0,1"
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Disable" "0,1"
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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rgroup.long 0x210++0x3
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line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Mask" "0,1"
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bitfld.long 0x0 10. "ITER,Max Number of Repetitions Reached Interrupt Mask" "0,1"
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
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rgroup.long 0x210++0x7
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line.long 0x0 "FLEX_US_IMR_LIN_MODE,USART Interrupt Mask Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Mask" "0,1"
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Mask" "0,1"
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Mask" "0,1"
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Mask" "0,1"
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Mask" "0,1"
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Mask" "0,1"
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Mask" "0,1"
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Mask" "0,1"
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "0,1"
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Mask" "0,1"
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
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bitfld.long 0x4 24. "MANE,Manchester Error" "0: No Manchester error has been detected since the..,1: At least one Manchester error has been detected.."
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bitfld.long 0x4 23. "CTS,Image of CTS Input" "0: CTS input is driven low.,1: CTS input is driven high."
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bitfld.long 0x4 22. "CMP,Comparison Status" "0: No received character matched the comparison..,1: A received character matched the comparison.."
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0: No input change has been detected on the CTS pin..,1: At least one input change has been detected on.."
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt" "0: Non acknowledge has not been detected since the..,1: At least one non acknowledge has been detected.."
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bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached" "0: Maximum number of repetitions has not been..,1: Maximum number of repetitions has been reached.."
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bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0: There are characters in either FLEX_US_THR or..,1: There are no characters in FLEX_US_THR nor in.."
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bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0: There has not been a timeout since the last..,1: There has been a timeout since the last Start.."
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bitfld.long 0x4 7. "PARE,Parity Error" "0: No parity error has been detected since the last..,1: At least one parity error has been detected.."
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bitfld.long 0x4 6. "FRAME,Framing Error" "0: No stop bit has been detected low since the last..,1: At least one stop bit has been detected low.."
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bitfld.long 0x4 5. "OVRE,Overrun Error" "0: No overrun error has occurred since the last..,1: At least one overrun error has occurred since.."
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bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0: No break received or end of break detected since..,1: Break received or end of break detected since.."
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bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0: Transmit FIFO is full and cannot accept more data,1: Transmit FIFO is not full; one or more data can.."
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bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0: Receive FIFO is empty; no data to read,1: At least one unread data is in the Receive FIFO"
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rgroup.long 0x214++0x7
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line.long 0x0 "FLEX_US_CSR_LIN_MODE,USART Channel Status Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error" "0: No LIN header timeout error has been detected..,1: A LIN header timeout error has been detected.."
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error" "0: No LIN synch tolerance error has been detected..,1: A LIN synch tolerance error has been detected.."
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error" "0: No LIN slave not responding error has been..,1: A LIN slave not responding error has been.."
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error" "0: No LIN checksum error has been detected since..,1: A LIN checksum error has been detected since the.."
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Error" "0: No LIN identifier parity error has been detected..,1: A LIN identifier parity error has been detected.."
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error" "0: No LIN inconsistent synch field error has been..,1: The USART is configured as a slave node and a.."
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bitfld.long 0x0 25. "LINBE,LIN Bit Error" "0: No bit error has been detected since the last..,1: A bit error has been detected since the last.."
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bitfld.long 0x0 23. "LINBLS,LIN Bus Line Status" "0: LIN bus line is set to 0.,1: LIN bus line is set to 1."
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed" "0: The USART is idle or a LIN transfer is ongoing.,1: A LIN transfer has been completed since the last.."
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received" "0: No LIN identifier has been received since the..,1: At least one LIN identifier has been received.."
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received" "0: No LIN break has received sent since the last..,1: At least one LIN break has been received since.."
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bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0: There are characters in either FLEX_US_THR or..,1: There are no characters in FLEX_US_THR nor in.."
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bitfld.long 0x0 8. "TIMEOUT,Receiver Timeout" "0: There has not been a timeout since the last..,1: There has been a timeout since the last start.."
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bitfld.long 0x0 7. "PARE,Parity Error" "0: No parity error has been detected since the last..,1: At least one parity error has been detected.."
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bitfld.long 0x0 6. "FRAME,Framing Error" "0: No stop bit has been detected low since the last..,1: At least one stop bit has been detected low.."
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bitfld.long 0x0 5. "OVRE,Overrun Error" "0: No overrun error has occurred since the last..,1: At least one overrun error has occurred since.."
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bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0: A character in FLEX_US_THR is waiting to be..,1: There is no character in FLEX_US_THR."
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bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0: No complete character has been received since..,1: At least one complete character has been.."
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line.long 0x4 "FLEX_US_RHR,USART Receive Holding Register"
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bitfld.long 0x4 15. "RXSYNH,Received Sync" "0: Last character received is a data.,1: Last character received is a command."
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hexmask.long.word 0x4 0.--8. 1. "RXCHR,Received Character"
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rgroup.long 0x218++0x3
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line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Characters"
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hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Characters"
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hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Characters"
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hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Characters"
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wgroup.long 0x21C++0x3
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line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
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bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0: The next character sent is encoded as a data.,1: The next character sent is encoded as a command."
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hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
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wgroup.long 0x21C++0x3
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line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
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hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
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hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
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hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
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group.long 0x220++0xB
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line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
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bitfld.long 0x0 16.--18. "FP,Fractional Part" "0: Fractional divider is disabled.,?,?,?,?,?,?,?"
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hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
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line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
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hexmask.long.tbyte 0x4 0.--16. 1. "TO,Timeout Value"
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line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
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hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
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group.long 0x240++0x3
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line.long 0x0 "FLEX_US_FIDI,USART FI DI Ratio Register"
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hexmask.long.word 0x0 0.--15. 1. "FI_DI_RATIO,FI Over DI Ratio Value"
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rgroup.long 0x244++0x3
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line.long 0x0 "FLEX_US_NER,USART Number of Errors Register"
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hexmask.long.byte 0x0 0.--7. 1. "NB_ERRORS,Number of Errors"
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group.long 0x24C++0xF
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line.long 0x0 "FLEX_US_IF,USART IrDA Filter Register"
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hexmask.long.byte 0x0 0.--7. 1. "IRDA_FILTER,IrDA Filter"
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line.long 0x4 "FLEX_US_MAN,USART Manchester Configuration Register"
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bitfld.long 0x4 31. "RXIDLEV,Receiver Idle Value" "0: Receiver line idle value is 0.,1: Receiver line idle value is 1."
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bitfld.long 0x4 30. "DRIFT,Drift Compensation" "0: The USART cannot recover from an important clock..,1: The USART can recover from clock drift. The 16X.."
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bitfld.long 0x4 29. "ONE,Must Be Set to 1" "0,1"
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bitfld.long 0x4 28. "RX_MPOL,Receiver Manchester Polarity" "0: Logic zero is coded as a zero-to-one transition..,1: Logic zero is coded as a one-to-zero transition.."
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bitfld.long 0x4 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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hexmask.long.byte 0x4 16.--19. 1. "RX_PL,Receiver Preamble Length"
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bitfld.long 0x4 12. "TX_MPOL,Transmitter Manchester Polarity" "0: Logic zero is coded as a zero-to-one transition..,1: Logic zero is coded as a one-to-zero transition.."
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bitfld.long 0x4 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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hexmask.long.byte 0x4 0.--3. 1. "TX_PL,Transmitter Preamble Length"
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line.long 0x8 "FLEX_US_LINMR,USART LIN Mode Register"
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bitfld.long 0x8 17. "SYNCDIS,Synchronization Disable" "0: The synchronization procedure is performed in..,1: The synchronization procedure is not performed.."
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bitfld.long 0x8 16. "PDCM,DMAC Mode" "0: The LIN mode register FLEX_US_LINMR is not..,1: The LIN mode register FLEX_US_LINMR (excepting.."
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hexmask.long.byte 0x8 8.--15. 1. "DLC,Data Length Control"
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bitfld.long 0x8 7. "WKUPTYP,Wakeup Signal Type" "0: Setting the LINWKUP bit in the control register..,1: Setting the LINWKUP bit in the control register.."
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bitfld.long 0x8 6. "FSDIS,Frame Slot Mode Disable" "0: The Frame Slot mode is enabled.,1: The Frame Slot mode is disabled."
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bitfld.long 0x8 5. "DLM,Data Length Mode" "0: The response data length is defined by the DLC..,1: The response data length is defined by the bits.."
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bitfld.long 0x8 4. "CHKTYP,Checksum Type" "0: LIN 2.0 'enhanced' checksum,1: LIN 1.3 'classic' checksum"
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bitfld.long 0x8 3. "CHKDIS,Checksum Disable" "0: In master node configuration the checksum is..,1: Whatever the node configuration is the checksum.."
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bitfld.long 0x8 2. "PARDIS,Parity Disable" "0: In master node configuration the identifier..,1: Whatever the node configuration is the.."
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bitfld.long 0x8 0.--1. "NACT,LIN Node Action" "0: The USART transmits the response.,1: The USART receives the response.,2: The USART does not transmit and does not receive..,?"
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line.long 0xC "FLEX_US_LINIR,USART LIN Identifier Register"
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hexmask.long.byte 0xC 0.--7. 1. "IDCHR,Identifier Character"
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rgroup.long 0x25C++0x3
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line.long 0x0 "FLEX_US_LINBRR,USART LIN Baud Rate Register"
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bitfld.long 0x0 16.--18. "LINFP,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x0 0.--15. 1. "LINCD,Clock Divider after Synchronization"
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group.long 0x290++0x3
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line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
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hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
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bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0: The parity is not checked and a bad parity..,1: The parity is checked and a matching condition.."
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bitfld.long 0x0 12.--13. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start..,2: Comparison must be met to receive the current..,?"
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hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
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group.long 0x2A0++0x3
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line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
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hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
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hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
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bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0: RTS pin is not controlled by Receive FIFO..,1: RTS pin is controlled by Receive FIFO thresholds."
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bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x2A4++0x3
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line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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wgroup.long 0x2A8++0x7
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line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
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bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
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rgroup.long 0x2B0++0x7
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line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
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bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Number of unread data in Receive FIFO is above..,1: Number of unread data in Receive FIFO has.."
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bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0: The Transmit FIFO is not locked.,1: The Transmit FIFO is locked."
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bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0: No Receive FIFO pointer occurred,1: Receive FIFO pointer error occurred. Receiver.."
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bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0: No Transmit FIFO pointer occurred,1: Transmit FIFO pointer error occurred."
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bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Number of unread data in Receive FIFO is below..,1: Number of unread data in Receive FIFO has.."
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bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Receive FIFO is not empty.,1: Receive FIFO has been filled since the last.."
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bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Receive FIFO is not empty.,1: Receive FIFO has been emptied since the last.."
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bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Number of data in Transmit FIFO is above..,1: Number of data in Transmit FIFO has reached.."
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bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Transmit FIFO is not full.,1: Transmit FIFO has been filled since the last.."
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bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Transmit FIFO is not empty.,1: Transmit FIFO has been emptied since the last.."
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group.long 0x2E4++0x3
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line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection on configuration..,1: Enables the write protection on configuration.."
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rgroup.long 0x2E8++0x3
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line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
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hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
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wgroup.long 0x400++0x3
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line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
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bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0: No effect.,1: Disables the Transmit and Receive FIFOs"
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0: No effect.,1: Enables the Transmit and Receive FIFOs"
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bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0: No effect.,1: The current NPCS will be de-asserted after the.."
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bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0: No effect.,1: Empties the Receive FIFO."
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bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0: No effect.,1: Empties the Transmit FIFO."
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bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0: No effect.,1: Restarts the comparison trigger to enable.."
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bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0: No effect.,1: Reset the SPI. A software-triggered hardware.."
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bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0: No effect.,1: Disables the SPI."
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bitfld.long 0x0 0. "SPIEN,SPI Enable" "0: No effect.,1: Enables the SPI to transfer and receive data."
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group.long 0x404++0x3
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line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
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hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
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bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0: Local loopback path disabled.,1: Local loopback path enabled."
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bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0: No Effect. In Master mode a transfer can be..,1: In Master mode a transfer can start only if.."
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bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0: Mode fault detection is enabled.,1: Mode fault detection is disabled."
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bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
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bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0: The chip selects are directly connected to a..,1: The four NPCS chip select lines are connected to.."
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bitfld.long 0x0 1. "PS,Peripheral Select" "0: Fixed Peripheral Select,1: Variable Peripheral Select"
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bitfld.long 0x0 0. "MSTR,Master/Slave Mode" "0: SPI is in Slave mode.,1: SPI is in Master mode."
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rgroup.long 0x408++0x3
|
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line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
|
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
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rgroup.long 0x408++0x3
|
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line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
|
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hexmask.long.word 0x0 16.--31. 1. "RD1,Receive Data"
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hexmask.long.word 0x0 0.--15. 1. "RD0,Receive Data"
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rgroup.long 0x408++0x3
|
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line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
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hexmask.long.byte 0x0 24.--31. 1. "RD3,Receive Data"
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hexmask.long.byte 0x0 16.--23. 1. "RD2,Receive Data"
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hexmask.long.byte 0x0 8.--15. 1. "RD1,Receive Data"
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hexmask.long.byte 0x0 0.--7. 1. "RD0,Receive Data"
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wgroup.long 0x40C++0x3
|
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line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
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bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0: No effect.,1: The current NPCS is de-asserted after the.."
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
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wgroup.long 0x40C++0x3
|
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line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
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hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
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hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
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rgroup.long 0x410++0x3
|
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line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
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bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0: No Receive FIFO pointer occurred,1: Receive FIFO pointer error occurred. Receiver.."
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bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0: No Transmit FIFO pointer occurred,1: Transmit FIFO pointer error occurred."
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bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0: Number of unread data in Receive FIFO is below..,1: Number of unread data in Receive FIFO has.."
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bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0: Receive FIFO is not empty or RXFE flag has been..,1: Receive FIFO has been filled (changing states.."
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newline
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bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0: Receive FIFO is not empty or RXFE flag has been..,1: Receive FIFO has been emptied (changing states.."
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newline
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bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0: Number of data in Transmit FIFO is above..,1: Number of data in Transmit FIFO has reached.."
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newline
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bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0: Transmit FIFO is not full or TXFF flag has been..,1: Transmit FIFO has been filled since the last.."
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newline
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bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0: Transmit FIFO is not empty.,1: Transmit FIFO has been emptied since the last.."
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newline
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bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0: SPI is disabled.,1: SPI is enabled."
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newline
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bitfld.long 0x0 12. "SFERR,Slave Frame Error (cleared on read)" "0: There is no frame error detected for a slave..,1: In Slave mode the chip select raised while the.."
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newline
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bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0: No received character matched the comparison..,1: A received character matched the comparison.."
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newline
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bitfld.long 0x0 10. "UNDES,Underrun Error Status (Slave mode only) (cleared on read)" "0: No underrun has been detected since the last..,1: A transfer starts whereas no data has been.."
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newline
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0: As soon as data is written in FLEX_SPI_TDR.,1: FLEX_SPI_TDR and internal shift register are.."
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newline
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bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0: No rising edge detected on NSS pin since the..,1: A rising edge occurred on NSS pin since the last.."
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newline
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bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0: No overrun has been detected since the last read..,1: An overrun has occurred since the last read of.."
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newline
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bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0: No mode fault has been detected since the last..,1: A mode fault occurred since the last read of.."
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newline
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bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0: Transmit FIFO cannot accept more data.,1: Transmit FIFO can accept data; one or more data.."
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newline
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0: Receive FIFO is empty; no data to read,1: At least one unread data is in the Receive FIFO"
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wgroup.long 0x414++0x7
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line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
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bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
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newline
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bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
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bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
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newline
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bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
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rgroup.long 0x41C++0x3
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line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
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bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
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newline
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bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
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repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
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group.long ($2+0x430)++0x3
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line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register x"
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hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
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newline
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hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
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newline
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bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0: The Peripheral Chip Select Line rises as soon as..,1: The Peripheral Chip Select does not rise after.."
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newline
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bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0: The Peripheral Chip Select does not rise between..,1: The Peripheral Chip Select rises systematically.."
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newline
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bitfld.long 0x0 1. "NCPHA,Clock Phase" "0: Data are changed on the leading edge of SPCK and..,1: Data are captured on the leading edge of SPCK.."
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newline
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bitfld.long 0x0 0. "CPOL,Clock Polarity" "0: The inactive state value of SPCK is logic level..,1: The inactive state value of SPCK is logic level.."
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repeat.end
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group.long 0x440++0x3
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line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
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newline
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hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
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newline
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bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
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newline
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bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
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rgroup.long 0x444++0x3
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line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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newline
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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group.long 0x448++0x3
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line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
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hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
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newline
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hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
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group.long 0x4E4++0x3
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line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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newline
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
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newline
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
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newline
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
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rgroup.long 0x4E8++0x3
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line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
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hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
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newline
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0: No write protect violation has occurred since..,1: A write protect violation has occurred since the.."
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wgroup.long 0x600++0x3
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line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
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bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0: No effect.,1: Disable the Transmit and Receive FIFOs"
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newline
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bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0: No effect.,1: Enable the Transmit and Receive FIFOs"
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newline
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bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0: No effect.,1: Clear the TWI FSM lock."
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newline
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bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0: No effect.,1: Clear the Transmit Holding Register and set.."
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newline
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bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0: No effect.,1: Alternative Command mode disabled."
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newline
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bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0: No effect.,1: Alternative Command mode enabled."
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newline
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bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0: No effect.,1: If Master mode is enabled send a bus clear.."
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newline
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bitfld.long 0x0 14. "PECRQ,PEC Request" "0: No effect.,1: A PEC check or transmission is requested."
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newline
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bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0: No effect.,1: SMBus PEC (CRC) generation and check disabled."
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newline
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bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0: No effect.,1: SMBus PEC (CRC) generation and check enabled."
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newline
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bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0: No effect.,1: SMBus mode disabled."
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newline
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bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0: No effect.,1: If SMBDIS = 0 SMBus mode enabled."
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newline
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bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0: No effect.,1: High-speed mode disabled."
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newline
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bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0: No effect.,1: High-speed mode enabled."
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newline
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bitfld.long 0x0 7. "SWRST,Software Reset" "0: No effect.,1: Equivalent to a system reset."
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newline
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bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0: No effect.,1: If Master mode is enabled a SMBus Quick Command.."
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newline
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bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0: No effect.,1: The Slave mode is disabled. The shifter and.."
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newline
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bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0: No effect.,1: Enables the Slave mode (SVDIS must be written to.."
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newline
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bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0: No effect.,1: The Master mode is disabled all pending data is.."
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newline
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bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0: No effect.,1: Enables the Master mode (MSDIS must be written.."
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newline
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bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0: No effect.,1: STOP condition is sent just after completing the.."
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newline
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bitfld.long 0x0 0. "START,Send a START Condition" "0: No effect.,1: A frame beginning with a START bit is.."
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wgroup.long 0x600++0x3
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line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
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bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0: No effect.,1: Disable the Transmit and Receive FIFOs."
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newline
|
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bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0: No effect.,1: Enable the Transmit and Receive FIFOs."
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newline
|
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bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0: No effect.,1: Clears the Transmit FIFO Lock."
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newline
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bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0: No effect.,1: Empties the Receive FIFO."
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newline
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bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0: No effect.,1: Empties the Transmit FIFO."
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newline
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bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0: No effect.,1: Alternative Command mode disabled."
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newline
|
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bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0: No effect.,1: Alternative Command mode enabled."
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newline
|
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bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0: No effect.,1: If Master mode is enabled send a bus clear.."
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newline
|
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bitfld.long 0x0 14. "PECRQ,PEC Request" "0: No effect.,1: A PEC check or transmission is requested."
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|
newline
|
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bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0: No effect.,1: SMBus PEC (CRC) generation and check disabled."
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|
newline
|
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bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0: No effect.,1: SMBus PEC (CRC) generation and check enabled."
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newline
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bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0: No effect.,1: SMBus mode disabled."
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newline
|
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bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0: No effect.,1: If SMBDIS = 0 SMBus mode enabled."
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newline
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bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0: No effect.,1: High-speed mode disabled."
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newline
|
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bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0: No effect.,1: High-speed mode enabled."
|
|
newline
|
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bitfld.long 0x0 7. "SWRST,Software Reset" "0: No effect.,1: Equivalent to a system reset."
|
|
newline
|
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bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0: No effect.,1: If Master mode is enabled a SMBus Quick Command.."
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|
newline
|
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bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0: No effect.,1: The Slave mode is disabled. The shifter and.."
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|
newline
|
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bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0: No effect.,1: Enables the Slave mode (SVDIS must be written to.."
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newline
|
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bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0: No effect.,1: The Master mode is disabled all pending data is.."
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|
newline
|
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bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0: No effect.,1: Enables the Master mode (MSDIS must be written.."
|
|
newline
|
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bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0: No effect.,1: STOP condition is sent just after completing the.."
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|
newline
|
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bitfld.long 0x0 0. "START,Send a START Condition" "0: No effect.,1: A frame beginning with a START bit is.."
|
|
group.long 0x604++0xF
|
|
line.long 0x0 "FLEX_TWI_MMR,TWI Master Mode Register"
|
|
bitfld.long 0x0 24. "NOAP,No Auto-Stop On NACK Error" "0: A stop condition is sent automatically upon..,1: No automatic action is performed upon.."
|
|
newline
|
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hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
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|
newline
|
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bitfld.long 0x0 13.--14. "SCLRBL,SCL Rise Boost Level" "0,1,2,3"
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|
newline
|
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bitfld.long 0x0 12. "MREAD,Master Read Direction" "0: Master write direction.,1: Master read direction."
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|
newline
|
|
bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
|
|
line.long 0x4 "FLEX_TWI_SMR,TWI Slave Mode Register"
|
|
bitfld.long 0x4 31. "DATAMEN,Data Matching Enable" "0: Data matching on first received data is disabled.,1: Data matching on first received data is enabled."
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newline
|
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bitfld.long 0x4 30. "SADR3EN,Slave Address 3 Enable" "0: Slave address 3 matching is disabled.,1: Slave address 3 matching is enabled."
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newline
|
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bitfld.long 0x4 29. "SADR2EN,Slave Address 2 Enable" "0: Slave address 2 matching is disabled.,1: Slave address 2 matching is enabled."
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newline
|
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bitfld.long 0x4 28. "SADR1EN,Slave Address 1 Enable" "0: Slave address 1 matching is disabled.,1: Slave address 1 matching is enabled."
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|
newline
|
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hexmask.long.byte 0x4 16.--22. 1. "SADR,Slave Address"
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newline
|
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hexmask.long.byte 0x4 8.--14. 1. "MASK,Slave Address Mask"
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|
newline
|
|
bitfld.long 0x4 7. "SNIFF,Slave Sniffer Mode" "0: Slave Sniffer mode is disabled.,1: Slave Sniffer mode is enabled."
|
|
newline
|
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bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0: No effect.,1: Clock stretching disabled in Slave mode OVRE and.."
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|
newline
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bitfld.long 0x4 5. "BSEL,TWI Bus Selection" "0: TWI analyzes the TWCK and TWD pins from its TWI..,1: TWI analyzes the TWCK pins TWD from consecutive.."
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bitfld.long 0x4 4. "SADAT,Slave Address Treated as Data" "0: Slave address is handled normally (will not trig..,1: Slave address is handled as data field RXRDY.."
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bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0: Acknowledge of the SMBus Host Header disabled.,1: Acknowledge of the SMBus Host Header enabled."
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bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0: Acknowledge of the SMBus Default Address disabled.,1: Acknowledge of the SMBus Default Address enabled."
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bitfld.long 0x4 0. "NACKEN,Slave Receiver Data Phase NACK Enable" "0: Normal value to be returned in the ACK cycle of..,1: NACK value to be returned in the ACK cycle of.."
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line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
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hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
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line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
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hexmask.long.byte 0xC 24.--29. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
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bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
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bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
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hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
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rgroup.long 0x620++0x3
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line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
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bitfld.long 0x0 26. "SR,Start Repeated" "0: No repeated start has been detected since last..,1: At least one repeated start has been detected.."
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bitfld.long 0x0 25. "SDA,SDA Line Value" "0: SDA line sampled value is '0'.,1: SDA line sampled value is '1'."
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bitfld.long 0x0 24. "SCL,SCL Line Value" "0: SCL line sampled value is '0'.,1: SCL line sampled value is '1.'"
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bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0: The TWI is not locked.,1: The TWI is locked due to frame errors (see.."
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0: No SMBus Host Header Address received.,1: A SMBus Host Header Address was received."
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0: No SMBus Default Address received.,1: A SMBus Default Address was received."
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bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0: No SMBus PEC error occurred.,1: A SMBus PEC error occurred."
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bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0: No SMBus timeout occurred.,1: SMBus timeout occurred."
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bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag" "0: No SMBus slave drives the SMBALERT line.,1: At least one SMBus slave drives the SMBALERT line."
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0: No master code has been received.,1: A master code has been received."
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0: A slave access is being performing.,1: The Slave Access is finished. End Of Slave.."
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bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0: The clock is not stretched.,1: The clock is stretched. FLEX_TWI_THR /.."
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0: Arbitration won.,1: Arbitration lost. Another master of the TWI bus.."
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bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0: Each data byte has been correctly received by..,1: In Read mode a data byte has not been.."
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bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0: FLEX_TWI_THR has been filled on time.,1: FLEX_TWI_THR has not been filled on time."
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bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0: FLEX_TWI_RHR has not been loaded while RXRDY was..,1: FLEX_TWI_RHR has been loaded while RXRDY was.."
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bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0: No general call has been detected.,1: A general call has been detected. After the.."
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bitfld.long 0x0 4. "SVACC,Slave Access" "0: TWI is not addressed. SVACC is automatically..,1: Indicates that the address decoding sequence has.."
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bitfld.long 0x0 3. "SVREAD,Slave Read" "0: Indicates that a write access is performed by a..,1: Indicates that a read access is performed by a.."
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0: Transmit FIFO is full and cannot accept more data,1: Transmit FIFO is not full; one or more data can.."
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0: Receive FIFO is empty; no data to read,1: At least one unread data is in the Receive FIFO"
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0: As soon as a Start is detected.,1: After a Stop or a Repeated Start + an address.."
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rgroup.long 0x620++0x3
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line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
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bitfld.long 0x0 26. "SR,Start Repeated" "0: No repeated start has been detected since last..,1: At least one repeated start has been detected.."
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bitfld.long 0x0 25. "SDA,SDA Line Value" "0: SDA line sampled value is '0'.,1: SDA line sampled value is '1'."
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bitfld.long 0x0 24. "SCL,SCL Line Value" "0: SCL line sampled value is '0'.,1: SCL line sampled value is '1.'"
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bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0: The Transmit FIFO is not locked.,1: The Transmit FIFO is locked."
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0: No SMBus Host Header Address received.,1: A SMBus Host Header Address was received."
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0: No SMBus Default Address received.,1: A SMBus Default Address was received."
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bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0: No SMBus PEC error occurred.,1: A SMBus PEC error occurred."
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bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0: No SMBus timeout occurred.,1: SMBus timeout occurred."
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bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag" "0: No SMBus slave drives the SMBALERT line.,1: At least one SMBus slave drives the SMBALERT line."
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0: No master code has been received.,1: A master code has been received."
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0: A slave access is being performing.,1: The Slave Access is finished. End Of Slave.."
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bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0: The clock is not stretched.,1: The clock is stretched. FLEX_TWI_THR /.."
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0: Arbitration won.,1: Arbitration lost. Another master of the TWI bus.."
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bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0: Each data byte has been correctly received by..,1: In Read mode a data byte has not been.."
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bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0: FLEX_TWI_THR has been filled on time.,1: FLEX_TWI_THR has not been filled on time."
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bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0: FLEX_TWI_RHR has not been loaded while RXRDY was..,1: FLEX_TWI_RHR has been loaded while RXRDY was.."
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bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0: No general call has been detected.,1: A general call has been detected. After the.."
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bitfld.long 0x0 4. "SVACC,Slave Access" "0: TWI is not addressed. SVACC is automatically..,1: Indicates that the address decoding sequence has.."
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bitfld.long 0x0 3. "SVREAD,Slave Read" "0: Indicates that a write access is performed by a..,1: Indicates that a read access is performed by a.."
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0: Transmit FIFO is full and cannot accept more data.,1: Transmit FIFO is not full; one or more data can.."
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0: Receive FIFO is empty; no data to read.,1: At least one unread data is in the Receive FIFO."
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0: As soon as a Start is detected.,1: After a Stop or a Repeated Start + an address.."
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wgroup.long 0x624++0x7
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line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
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bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
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bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Enable" "0,1"
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bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
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bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
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bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
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bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Enable" "0,1"
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bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
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bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
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bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
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bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
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bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
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bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
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bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
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bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
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bitfld.long 0x4 16. "MCACK,Master Code Acknowledge Interrupt Disable" "0,1"
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bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
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bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
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bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
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bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
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bitfld.long 0x4 11. "EOSACC,End Of Slave Access Interrupt Disable" "0,1"
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bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
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bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
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bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
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bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
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bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
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bitfld.long 0x4 4. "SVACC,Slave Access Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
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rgroup.long 0x62C++0x7
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line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
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bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
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bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Mask" "0,1"
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bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
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bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
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bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
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bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Mask" "0,1"
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bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
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bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
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bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
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bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Mask" "0,1"
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
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bitfld.long 0x4 11.--12. "ASTATE,Acknowledge State (Slave Sniffer Mode only)" "0: No Acknowledge or Nacknowledge detected after..,1: Acknowledge (A) detected after previously logged..,2: Nacknowledge (NA) detected after previously..,3: Not defined"
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bitfld.long 0x4 10. "PSTATE,Stop State (Slave Sniffer Mode only)" "0: No STOP (P) detected after previous logged data.,1: Stop detected (P) after previous logged data."
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bitfld.long 0x4 8.--9. "SSTATE,Start State (Slave Sniffer Mode only)" "0: No START detected with the logged data,1: START (S) detected with the logged data,2: Repeated START (Sr) detected with the logged data,3: Not defined"
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hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Master or Slave Receive Holding Data"
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rgroup.long 0x630++0x3
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line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Master or Slave Receive Holding Data 3"
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hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Master or Slave Receive Holding Data 2"
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hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Master or Slave Receive Holding Data 1"
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hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Master or Slave Receive Holding Data 0"
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wgroup.long 0x634++0x3
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line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Master or Slave Transmit Holding Data"
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wgroup.long 0x634++0x3
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line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Master or Slave Transmit Holding Data 3"
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hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Master or Slave Transmit Holding Data 2"
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hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Master or Slave Transmit Holding Data 1"
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Master or Slave Transmit Holding Data 0"
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group.long 0x638++0x1B
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line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
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hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
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hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Master Clock Stretch Maximum Cycles"
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hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Slave Clock Stretch Maximum Cycles"
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hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
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line.long 0x4 "FLEX_TWI_HSR,TWI High Speed Register"
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hexmask.long.byte 0x4 0.--7. 1. "MCODE,TWI High Speed Master Code"
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line.long 0x8 "FLEX_TWI_ACR,TWI Alternative Command Register"
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bitfld.long 0x8 25. "NPEC,Next PEC Request (SMBus Mode only)" "0: The next transfer does not use a PEC byte.,1: The next transfer uses a PEC byte."
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bitfld.long 0x8 24. "NDIR,Next Transfer Direction" "0: Write direction.,1: Read direction."
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hexmask.long.byte 0x8 16.--23. 1. "NDATAL,Next Data Length"
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bitfld.long 0x8 9. "PEC,PEC Request (SMBus Mode only)" "0: The transfer does not use a PEC byte.,1: The transfer uses a PEC byte."
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bitfld.long 0x8 8. "DIR,Transfer Direction" "0: Write direction.,1: Read direction."
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hexmask.long.byte 0x8 0.--7. 1. "DATAL,Data Length"
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line.long 0xC "FLEX_TWI_FILTR,TWI Filter Register"
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bitfld.long 0xC 8.--10. "THRES,Digital Filter Threshold" "0: No filtering applied on TWI inputs.,?,?,?,?,?,?,?"
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bitfld.long 0xC 1. "PADFEN,PAD Filter Enable" "0: PAD analog filter is disabled.,1: PAD analog filter is enabled. (The analog filter.."
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newline
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bitfld.long 0xC 0. "FILT,RX Digital Filter" "0: No filtering applied on TWI inputs.,1: TWI input filtering is active. (Only in Standard.."
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line.long 0x10 "FLEX_TWI_HSCWGR,TWI High Speed Clock Waveform Generator Register"
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bitfld.long 0x10 16.--18. "HSCKDIV,High Speed Clock Divider" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x10 8.--15. 1. "HSCHDIV,High Speed Clock High Divider"
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hexmask.long.byte 0x10 0.--7. 1. "HSCLDIV,High Speed Clock Low Divider"
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line.long 0x14 "FLEX_TWI_SWMR,TWI Matching Register"
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hexmask.long.byte 0x14 24.--31. 1. "DATAM,Data Match"
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hexmask.long.byte 0x14 16.--22. 1. "SADR3,Slave Address 3"
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hexmask.long.byte 0x14 8.--14. 1. "SADR2,Slave Address 2"
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hexmask.long.byte 0x14 0.--6. 1. "SADR1,Slave Address 1"
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line.long 0x18 "FLEX_TWI_FMR,TWI FIFO Mode Register"
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hexmask.long.byte 0x18 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
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hexmask.long.byte 0x18 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
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bitfld.long 0x18 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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bitfld.long 0x18 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x654++0x3
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line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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rgroup.long 0x660++0x3
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line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
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bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0: No Receive FIFO pointer occurred,1: Receive FIFO pointer error occurred. Receiver.."
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bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0: No Transmit FIFO pointer occurred,1: Transmit FIFO pointer error occurred."
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bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0: Number of unread data in Receive FIFO is below..,1: Number of unread data in Receive FIFO has.."
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bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0: Receive FIFO is not empty.,1: Receive FIFO has been filled since the last read.."
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bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0: Receive FIFO is not empty.,1: Receive FIFO has been emptied since the last.."
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bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0: Number of data in Transmit FIFO is above..,1: Number of data in Transmit FIFO has reached.."
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bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0: Transmit FIFO is not full.,1: Transmit FIFO has been filled since the last.."
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bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0: Transmit FIFO is not empty.,1: Transmit FIFO has been emptied since the last.."
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wgroup.long 0x664++0x7
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line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
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rgroup.long 0x66C++0x3
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line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
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group.long 0x6E4++0x3
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line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
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rgroup.long 0x6E8++0x3
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line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
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bitfld.long 0x0 0. "WPVS,Write Protect Violation Status" "0: No Write Protection Violation has occurred since..,1: A Write Protection Violation has occurred since.."
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tree.end
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tree "FLEXCOM7"
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base ad:0xE2024000
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group.long 0x0++0x3
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line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
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bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected. USART/TWI..,3: All TWI related protocols are selected (TWI.."
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rgroup.long 0x10++0x3
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line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
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hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
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group.long 0x20++0x3
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line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
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wgroup.long 0x200++0x3
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line.long 0x0 "FLEX_US_CR,USART Control Register"
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bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0: No effect.,1: Disables the Transmit and Receive FIFOs."
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0: No effect.,1: Enables the Transmit and Receive FIFOs."
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bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0: No effect.,1: Restarts the comparison trigger to enable.."
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bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0: No effect.,1: Clears the Transmit FIFO Lock"
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bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0: No effect.,1: Empties the Receive FIFO."
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bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0: No effect.,1: Empties the Transmit FIFO."
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bitfld.long 0x0 21. "LINWKUP,Send LIN Wakeup Signal" "0: No effect:,1: Sends a wakeup signal on the LIN bus."
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bitfld.long 0x0 20. "LINABT,Abort LIN Transmission" "0: No effect.,1: Aborts the current LIN transmission."
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bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0: No effect.,1: Drives the RTS pin to 0 if FLEX_US_MR.USART_MODE.."
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bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0: No effect.,1: Drives the RTS pin to 1 if FLEX_US_MR.USART_MODE.."
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bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0: No effect,1: Immediately restarts timeout period."
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bitfld.long 0x0 14. "RSTNACK,Reset Non Acknowledge" "0: No effect,1: Resets FLEX_US_CSR.NACK."
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bitfld.long 0x0 13. "RSTIT,Reset Iterations" "0: No effect.,1: Resets FLEX_US_CSR.ITER. No effect if the.."
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bitfld.long 0x0 12. "SENDA,Send Address" "0: No effect.,1: In Multidrop mode only the next character.."
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bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0: No effect.,1: Starts waiting for a character before clocking.."
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bitfld.long 0x0 10. "STPBRK,Stop Break" "0: No effect.,1: Stops transmission of the break after a minimum.."
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bitfld.long 0x0 9. "STTBRK,Start Break" "0: No effect.,1: Starts transmission of a break after the.."
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bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0: No effect.,1: Resets the status bits PARE FRAME OVRE MANE.."
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bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0: No effect.,1: Disables the transmitter."
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bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0: No effect.,1: Enables the transmitter if TXDIS is 0."
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bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0: No effect.,1: Disables the receiver."
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bitfld.long 0x0 4. "RXEN,Receiver Enable" "0: No effect.,1: Enables the receiver if RXDIS is 0."
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bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0: No effect.,1: Resets the transmitter."
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bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0: No effect.,1: Resets the receiver."
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group.long 0x204++0x3
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line.long 0x0 "FLEX_US_MR,USART Mode Register"
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bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0: Start frame delimiter is COMMAND or DATA SYNC.,1: Start frame delimiter is one bit."
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bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0: The Manchester start bit is a 0 to 1 transition,1: The Manchester start bit is a 1 to 0 transition."
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bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0: Manchester encoder/decoder are disabled.,1: Manchester encoder/decoder are enabled."
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bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0: The USART does not filter the receive line.,1: The USART filters the receive line using a.."
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bitfld.long 0x0 24.--26. "MAX_ITERATION,Maximum Number of Automatic Iteration" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 23. "INVDATA,Inverted Data" "0: The data field transmitted on TXD line is the..,1: The data field transmitted on TXD line is.."
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bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0: User defined configuration of command or data..,1: The sync field is updated when a character is.."
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bitfld.long 0x0 21. "DSNACK,Disable Successive NACK" "0: NACK is sent on the ISO line as soon as a parity..,1: Successive parity errors are counted up to the.."
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bitfld.long 0x0 20. "INACK,Inhibit Non Acknowledge" "0: The NACK is generated.,1: The NACK is not generated."
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bitfld.long 0x0 19. "OVER,Oversampling Mode" "0: 16x Oversampling.,1: 8x Oversampling."
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bitfld.long 0x0 18. "CLKO,Clock Output Select" "0: The USART does not drive the SCK pin..,1: The USART drives the SCK pin if USCLKS does not.."
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bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0: CHRL defines character length.,1: 9-bit character length."
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bitfld.long 0x0 16. "MSBF,Bit Order" "0: Least significant bit is sent/received first.,1: Most significant bit is sent/received first."
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bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
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bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
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bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
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bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0: USART operates in Asynchronous mode (UART).,1: USART operates in Synchronous mode."
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bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
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bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
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hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
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wgroup.long 0x208++0x3
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line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Enable" "0,1"
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bitfld.long 0x0 10. "ITER,Max number of Repetitions Reached Interrupt Enable" "0,1"
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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wgroup.long 0x208++0x7
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line.long 0x0 "FLEX_US_IER_LIN_MODE,USART Interrupt Enable Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Enable" "0,1"
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Enable" "0,1"
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Enable" "0,1"
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Enable" "0,1"
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Enable" "0,1"
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Enable" "0,1"
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Enable" "0,1"
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Enable" "0,1"
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Enable" "0,1"
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Enable" "0,1"
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
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bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
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bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt Disable" "0,1"
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|
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bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached Interrupt Disable" "0,1"
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bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
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bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
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|
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bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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wgroup.long 0x20C++0x3
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line.long 0x0 "FLEX_US_IDR_LIN_MODE,USART Interrupt Disable Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Disable" "0,1"
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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rgroup.long 0x210++0x3
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line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 10. "ITER,Max Number of Repetitions Reached Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
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rgroup.long 0x210++0x7
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line.long 0x0 "FLEX_US_IMR_LIN_MODE,USART Interrupt Mask Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
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bitfld.long 0x4 24. "MANE,Manchester Error" "0: No Manchester error has been detected since the..,1: At least one Manchester error has been detected.."
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newline
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bitfld.long 0x4 23. "CTS,Image of CTS Input" "0: CTS input is driven low.,1: CTS input is driven high."
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newline
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bitfld.long 0x4 22. "CMP,Comparison Status" "0: No received character matched the comparison..,1: A received character matched the comparison.."
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newline
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0: No input change has been detected on the CTS pin..,1: At least one input change has been detected on.."
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newline
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt" "0: Non acknowledge has not been detected since the..,1: At least one non acknowledge has been detected.."
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newline
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bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached" "0: Maximum number of repetitions has not been..,1: Maximum number of repetitions has been reached.."
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newline
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bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0: There are characters in either FLEX_US_THR or..,1: There are no characters in FLEX_US_THR nor in.."
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newline
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bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0: There has not been a timeout since the last..,1: There has been a timeout since the last Start.."
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newline
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bitfld.long 0x4 7. "PARE,Parity Error" "0: No parity error has been detected since the last..,1: At least one parity error has been detected.."
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newline
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bitfld.long 0x4 6. "FRAME,Framing Error" "0: No stop bit has been detected low since the last..,1: At least one stop bit has been detected low.."
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newline
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bitfld.long 0x4 5. "OVRE,Overrun Error" "0: No overrun error has occurred since the last..,1: At least one overrun error has occurred since.."
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newline
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bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0: No break received or end of break detected since..,1: Break received or end of break detected since.."
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newline
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bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0: Transmit FIFO is full and cannot accept more data,1: Transmit FIFO is not full; one or more data can.."
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newline
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bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0: Receive FIFO is empty; no data to read,1: At least one unread data is in the Receive FIFO"
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rgroup.long 0x214++0x7
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line.long 0x0 "FLEX_US_CSR_LIN_MODE,USART Channel Status Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error" "0: No LIN header timeout error has been detected..,1: A LIN header timeout error has been detected.."
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newline
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error" "0: No LIN synch tolerance error has been detected..,1: A LIN synch tolerance error has been detected.."
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newline
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error" "0: No LIN slave not responding error has been..,1: A LIN slave not responding error has been.."
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newline
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error" "0: No LIN checksum error has been detected since..,1: A LIN checksum error has been detected since the.."
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newline
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Error" "0: No LIN identifier parity error has been detected..,1: A LIN identifier parity error has been detected.."
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newline
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error" "0: No LIN inconsistent synch field error has been..,1: The USART is configured as a slave node and a.."
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newline
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bitfld.long 0x0 25. "LINBE,LIN Bit Error" "0: No bit error has been detected since the last..,1: A bit error has been detected since the last.."
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newline
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bitfld.long 0x0 23. "LINBLS,LIN Bus Line Status" "0: LIN bus line is set to 0.,1: LIN bus line is set to 1."
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newline
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed" "0: The USART is idle or a LIN transfer is ongoing.,1: A LIN transfer has been completed since the last.."
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newline
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received" "0: No LIN identifier has been received since the..,1: At least one LIN identifier has been received.."
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newline
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received" "0: No LIN break has received sent since the last..,1: At least one LIN break has been received since.."
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newline
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bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0: There are characters in either FLEX_US_THR or..,1: There are no characters in FLEX_US_THR nor in.."
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newline
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bitfld.long 0x0 8. "TIMEOUT,Receiver Timeout" "0: There has not been a timeout since the last..,1: There has been a timeout since the last start.."
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newline
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bitfld.long 0x0 7. "PARE,Parity Error" "0: No parity error has been detected since the last..,1: At least one parity error has been detected.."
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error" "0: No stop bit has been detected low since the last..,1: At least one stop bit has been detected low.."
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error" "0: No overrun error has occurred since the last..,1: At least one overrun error has occurred since.."
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newline
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bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0: A character in FLEX_US_THR is waiting to be..,1: There is no character in FLEX_US_THR."
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newline
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bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0: No complete character has been received since..,1: At least one complete character has been.."
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line.long 0x4 "FLEX_US_RHR,USART Receive Holding Register"
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bitfld.long 0x4 15. "RXSYNH,Received Sync" "0: Last character received is a data.,1: Last character received is a command."
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newline
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hexmask.long.word 0x4 0.--8. 1. "RXCHR,Received Character"
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rgroup.long 0x218++0x3
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line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Characters"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Characters"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Characters"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Characters"
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wgroup.long 0x21C++0x3
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line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
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bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0: The next character sent is encoded as a data.,1: The next character sent is encoded as a command."
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newline
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hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
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wgroup.long 0x21C++0x3
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line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
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group.long 0x220++0xB
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line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
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bitfld.long 0x0 16.--18. "FP,Fractional Part" "0: Fractional divider is disabled.,?,?,?,?,?,?,?"
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newline
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hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
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line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
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hexmask.long.tbyte 0x4 0.--16. 1. "TO,Timeout Value"
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line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
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hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
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group.long 0x240++0x3
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line.long 0x0 "FLEX_US_FIDI,USART FI DI Ratio Register"
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hexmask.long.word 0x0 0.--15. 1. "FI_DI_RATIO,FI Over DI Ratio Value"
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rgroup.long 0x244++0x3
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line.long 0x0 "FLEX_US_NER,USART Number of Errors Register"
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hexmask.long.byte 0x0 0.--7. 1. "NB_ERRORS,Number of Errors"
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group.long 0x24C++0xF
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line.long 0x0 "FLEX_US_IF,USART IrDA Filter Register"
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hexmask.long.byte 0x0 0.--7. 1. "IRDA_FILTER,IrDA Filter"
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line.long 0x4 "FLEX_US_MAN,USART Manchester Configuration Register"
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bitfld.long 0x4 31. "RXIDLEV,Receiver Idle Value" "0: Receiver line idle value is 0.,1: Receiver line idle value is 1."
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newline
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bitfld.long 0x4 30. "DRIFT,Drift Compensation" "0: The USART cannot recover from an important clock..,1: The USART can recover from clock drift. The 16X.."
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newline
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bitfld.long 0x4 29. "ONE,Must Be Set to 1" "0,1"
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newline
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bitfld.long 0x4 28. "RX_MPOL,Receiver Manchester Polarity" "0: Logic zero is coded as a zero-to-one transition..,1: Logic zero is coded as a one-to-zero transition.."
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newline
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bitfld.long 0x4 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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newline
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hexmask.long.byte 0x4 16.--19. 1. "RX_PL,Receiver Preamble Length"
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newline
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bitfld.long 0x4 12. "TX_MPOL,Transmitter Manchester Polarity" "0: Logic zero is coded as a zero-to-one transition..,1: Logic zero is coded as a one-to-zero transition.."
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newline
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bitfld.long 0x4 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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newline
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hexmask.long.byte 0x4 0.--3. 1. "TX_PL,Transmitter Preamble Length"
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line.long 0x8 "FLEX_US_LINMR,USART LIN Mode Register"
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bitfld.long 0x8 17. "SYNCDIS,Synchronization Disable" "0: The synchronization procedure is performed in..,1: The synchronization procedure is not performed.."
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newline
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bitfld.long 0x8 16. "PDCM,DMAC Mode" "0: The LIN mode register FLEX_US_LINMR is not..,1: The LIN mode register FLEX_US_LINMR (excepting.."
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newline
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hexmask.long.byte 0x8 8.--15. 1. "DLC,Data Length Control"
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newline
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bitfld.long 0x8 7. "WKUPTYP,Wakeup Signal Type" "0: Setting the LINWKUP bit in the control register..,1: Setting the LINWKUP bit in the control register.."
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newline
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bitfld.long 0x8 6. "FSDIS,Frame Slot Mode Disable" "0: The Frame Slot mode is enabled.,1: The Frame Slot mode is disabled."
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newline
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bitfld.long 0x8 5. "DLM,Data Length Mode" "0: The response data length is defined by the DLC..,1: The response data length is defined by the bits.."
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newline
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bitfld.long 0x8 4. "CHKTYP,Checksum Type" "0: LIN 2.0 'enhanced' checksum,1: LIN 1.3 'classic' checksum"
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newline
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bitfld.long 0x8 3. "CHKDIS,Checksum Disable" "0: In master node configuration the checksum is..,1: Whatever the node configuration is the checksum.."
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newline
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bitfld.long 0x8 2. "PARDIS,Parity Disable" "0: In master node configuration the identifier..,1: Whatever the node configuration is the.."
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newline
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bitfld.long 0x8 0.--1. "NACT,LIN Node Action" "0: The USART transmits the response.,1: The USART receives the response.,2: The USART does not transmit and does not receive..,?"
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line.long 0xC "FLEX_US_LINIR,USART LIN Identifier Register"
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hexmask.long.byte 0xC 0.--7. 1. "IDCHR,Identifier Character"
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rgroup.long 0x25C++0x3
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line.long 0x0 "FLEX_US_LINBRR,USART LIN Baud Rate Register"
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bitfld.long 0x0 16.--18. "LINFP,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.word 0x0 0.--15. 1. "LINCD,Clock Divider after Synchronization"
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group.long 0x290++0x3
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line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
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hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
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newline
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bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0: The parity is not checked and a bad parity..,1: The parity is checked and a matching condition.."
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newline
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bitfld.long 0x0 12.--13. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start..,2: Comparison must be met to receive the current..,?"
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newline
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hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
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group.long 0x2A0++0x3
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line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
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newline
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hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
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newline
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hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
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newline
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bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0: RTS pin is not controlled by Receive FIFO..,1: RTS pin is controlled by Receive FIFO thresholds."
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newline
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bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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newline
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x2A4++0x3
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line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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newline
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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wgroup.long 0x2A8++0x7
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line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
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line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
|
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bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x2B0++0x7
|
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line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
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|
newline
|
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
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line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Number of unread data in Receive FIFO is above..,1: Number of unread data in Receive FIFO has.."
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newline
|
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bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0: The Transmit FIFO is not locked.,1: The Transmit FIFO is locked."
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newline
|
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bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0: No Receive FIFO pointer occurred,1: Receive FIFO pointer error occurred. Receiver.."
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newline
|
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bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0: No Transmit FIFO pointer occurred,1: Transmit FIFO pointer error occurred."
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|
newline
|
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bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Number of unread data in Receive FIFO is below..,1: Number of unread data in Receive FIFO has.."
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|
newline
|
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bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Receive FIFO is not empty.,1: Receive FIFO has been filled since the last.."
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newline
|
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bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Receive FIFO is not empty.,1: Receive FIFO has been emptied since the last.."
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|
newline
|
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bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Number of data in Transmit FIFO is above..,1: Number of data in Transmit FIFO has reached.."
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newline
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bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Transmit FIFO is not full.,1: Transmit FIFO has been filled since the last.."
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newline
|
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bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Transmit FIFO is not empty.,1: Transmit FIFO has been emptied since the last.."
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group.long 0x2E4++0x3
|
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line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
|
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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newline
|
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
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newline
|
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
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newline
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection on configuration..,1: Enables the write protection on configuration.."
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rgroup.long 0x2E8++0x3
|
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line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
|
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hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
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newline
|
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
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wgroup.long 0x400++0x3
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line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
|
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bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0: No effect.,1: Disables the Transmit and Receive FIFOs"
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newline
|
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0: No effect.,1: Enables the Transmit and Receive FIFOs"
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newline
|
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bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0: No effect.,1: The current NPCS will be de-asserted after the.."
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newline
|
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bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0: No effect.,1: Empties the Receive FIFO."
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newline
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bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0: No effect.,1: Empties the Transmit FIFO."
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newline
|
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bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0: No effect.,1: Restarts the comparison trigger to enable.."
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newline
|
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bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0: No effect.,1: Reset the SPI. A software-triggered hardware.."
|
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newline
|
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bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0: No effect.,1: Disables the SPI."
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newline
|
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bitfld.long 0x0 0. "SPIEN,SPI Enable" "0: No effect.,1: Enables the SPI to transfer and receive data."
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group.long 0x404++0x3
|
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line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
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newline
|
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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newline
|
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bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
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|
newline
|
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bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0: Local loopback path disabled.,1: Local loopback path enabled."
|
|
newline
|
|
bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0: No Effect. In Master mode a transfer can be..,1: In Master mode a transfer can start only if.."
|
|
newline
|
|
bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0: Mode fault detection is enabled.,1: Mode fault detection is disabled."
|
|
newline
|
|
bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
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newline
|
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bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0: The chip selects are directly connected to a..,1: The four NPCS chip select lines are connected to.."
|
|
newline
|
|
bitfld.long 0x0 1. "PS,Peripheral Select" "0: Fixed Peripheral Select,1: Variable Peripheral Select"
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|
newline
|
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bitfld.long 0x0 0. "MSTR,Master/Slave Mode" "0: SPI is in Slave mode.,1: SPI is in Master mode."
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
|
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rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
|
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hexmask.long.word 0x0 16.--31. 1. "RD1,Receive Data"
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newline
|
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hexmask.long.word 0x0 0.--15. 1. "RD0,Receive Data"
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rgroup.long 0x408++0x3
|
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line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "RD3,Receive Data"
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RD2,Receive Data"
|
|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "RD1,Receive Data"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "RD0,Receive Data"
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wgroup.long 0x40C++0x3
|
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line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
|
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bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0: No effect.,1: The current NPCS is de-asserted after the.."
|
|
newline
|
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
|
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wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
|
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hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
|
|
rgroup.long 0x410++0x3
|
|
line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0: No Receive FIFO pointer occurred,1: Receive FIFO pointer error occurred. Receiver.."
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|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0: No Transmit FIFO pointer occurred,1: Transmit FIFO pointer error occurred."
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0: Number of unread data in Receive FIFO is below..,1: Number of unread data in Receive FIFO has.."
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0: Receive FIFO is not empty or RXFE flag has been..,1: Receive FIFO has been filled (changing states.."
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0: Receive FIFO is not empty or RXFE flag has been..,1: Receive FIFO has been emptied (changing states.."
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0: Number of data in Transmit FIFO is above..,1: Number of data in Transmit FIFO has reached.."
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0: Transmit FIFO is not full or TXFF flag has been..,1: Transmit FIFO has been filled since the last.."
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0: Transmit FIFO is not empty.,1: Transmit FIFO has been emptied since the last.."
|
|
newline
|
|
bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0: SPI is disabled.,1: SPI is enabled."
|
|
newline
|
|
bitfld.long 0x0 12. "SFERR,Slave Frame Error (cleared on read)" "0: There is no frame error detected for a slave..,1: In Slave mode the chip select raised while the.."
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0: No received character matched the comparison..,1: A received character matched the comparison.."
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Status (Slave mode only) (cleared on read)" "0: No underrun has been detected since the last..,1: A transfer starts whereas no data has been.."
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0: As soon as data is written in FLEX_SPI_TDR.,1: FLEX_SPI_TDR and internal shift register are.."
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|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0: No rising edge detected on NSS pin since the..,1: A rising edge occurred on NSS pin since the last.."
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0: No overrun has been detected since the last read..,1: An overrun has occurred since the last read of.."
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0: No mode fault has been detected since the last..,1: A mode fault occurred since the last read of.."
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0: Transmit FIFO cannot accept more data.,1: Transmit FIFO can accept data; one or more data.."
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0: Receive FIFO is empty; no data to read,1: At least one unread data is in the Receive FIFO"
|
|
wgroup.long 0x414++0x7
|
|
line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x41C++0x3
|
|
line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x430)++0x3
|
|
line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register x"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
|
|
newline
|
|
bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0: The Peripheral Chip Select Line rises as soon as..,1: The Peripheral Chip Select does not rise after.."
|
|
newline
|
|
bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0: The Peripheral Chip Select does not rise between..,1: The Peripheral Chip Select rises systematically.."
|
|
newline
|
|
bitfld.long 0x0 1. "NCPHA,Clock Phase" "0: Data are changed on the leading edge of SPCK and..,1: Data are captured on the leading edge of SPCK.."
|
|
newline
|
|
bitfld.long 0x0 0. "CPOL,Clock Polarity" "0: The inactive state value of SPCK is logic level..,1: The inactive state value of SPCK is logic level.."
|
|
repeat.end
|
|
group.long 0x440++0x3
|
|
line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
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hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
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bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
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bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
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rgroup.long 0x444++0x3
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line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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group.long 0x448++0x3
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line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
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hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
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hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
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group.long 0x4E4++0x3
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line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
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rgroup.long 0x4E8++0x3
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line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
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hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0: No write protect violation has occurred since..,1: A write protect violation has occurred since the.."
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wgroup.long 0x600++0x3
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line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
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bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0: No effect.,1: Disable the Transmit and Receive FIFOs"
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bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0: No effect.,1: Enable the Transmit and Receive FIFOs"
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bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0: No effect.,1: Clear the TWI FSM lock."
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bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0: No effect.,1: Clear the Transmit Holding Register and set.."
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bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0: No effect.,1: Alternative Command mode disabled."
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bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0: No effect.,1: Alternative Command mode enabled."
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bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0: No effect.,1: If Master mode is enabled send a bus clear.."
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bitfld.long 0x0 14. "PECRQ,PEC Request" "0: No effect.,1: A PEC check or transmission is requested."
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bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0: No effect.,1: SMBus PEC (CRC) generation and check disabled."
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bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0: No effect.,1: SMBus PEC (CRC) generation and check enabled."
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bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0: No effect.,1: SMBus mode disabled."
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bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0: No effect.,1: If SMBDIS = 0 SMBus mode enabled."
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bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0: No effect.,1: High-speed mode disabled."
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bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0: No effect.,1: High-speed mode enabled."
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bitfld.long 0x0 7. "SWRST,Software Reset" "0: No effect.,1: Equivalent to a system reset."
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bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0: No effect.,1: If Master mode is enabled a SMBus Quick Command.."
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bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0: No effect.,1: The Slave mode is disabled. The shifter and.."
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bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0: No effect.,1: Enables the Slave mode (SVDIS must be written to.."
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bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0: No effect.,1: The Master mode is disabled all pending data is.."
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bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0: No effect.,1: Enables the Master mode (MSDIS must be written.."
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bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0: No effect.,1: STOP condition is sent just after completing the.."
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bitfld.long 0x0 0. "START,Send a START Condition" "0: No effect.,1: A frame beginning with a START bit is.."
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wgroup.long 0x600++0x3
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line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
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bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0: No effect.,1: Disable the Transmit and Receive FIFOs."
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bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0: No effect.,1: Enable the Transmit and Receive FIFOs."
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bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0: No effect.,1: Clears the Transmit FIFO Lock."
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bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0: No effect.,1: Empties the Receive FIFO."
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bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0: No effect.,1: Empties the Transmit FIFO."
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bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0: No effect.,1: Alternative Command mode disabled."
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bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0: No effect.,1: Alternative Command mode enabled."
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bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0: No effect.,1: If Master mode is enabled send a bus clear.."
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bitfld.long 0x0 14. "PECRQ,PEC Request" "0: No effect.,1: A PEC check or transmission is requested."
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bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0: No effect.,1: SMBus PEC (CRC) generation and check disabled."
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bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0: No effect.,1: SMBus PEC (CRC) generation and check enabled."
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bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0: No effect.,1: SMBus mode disabled."
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bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0: No effect.,1: If SMBDIS = 0 SMBus mode enabled."
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bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0: No effect.,1: High-speed mode disabled."
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bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0: No effect.,1: High-speed mode enabled."
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bitfld.long 0x0 7. "SWRST,Software Reset" "0: No effect.,1: Equivalent to a system reset."
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bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0: No effect.,1: If Master mode is enabled a SMBus Quick Command.."
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bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0: No effect.,1: The Slave mode is disabled. The shifter and.."
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bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0: No effect.,1: Enables the Slave mode (SVDIS must be written to.."
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bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0: No effect.,1: The Master mode is disabled all pending data is.."
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bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0: No effect.,1: Enables the Master mode (MSDIS must be written.."
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bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0: No effect.,1: STOP condition is sent just after completing the.."
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bitfld.long 0x0 0. "START,Send a START Condition" "0: No effect.,1: A frame beginning with a START bit is.."
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group.long 0x604++0xF
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line.long 0x0 "FLEX_TWI_MMR,TWI Master Mode Register"
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bitfld.long 0x0 24. "NOAP,No Auto-Stop On NACK Error" "0: A stop condition is sent automatically upon..,1: No automatic action is performed upon.."
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hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
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bitfld.long 0x0 13.--14. "SCLRBL,SCL Rise Boost Level" "0,1,2,3"
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bitfld.long 0x0 12. "MREAD,Master Read Direction" "0: Master write direction.,1: Master read direction."
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bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
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line.long 0x4 "FLEX_TWI_SMR,TWI Slave Mode Register"
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bitfld.long 0x4 31. "DATAMEN,Data Matching Enable" "0: Data matching on first received data is disabled.,1: Data matching on first received data is enabled."
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bitfld.long 0x4 30. "SADR3EN,Slave Address 3 Enable" "0: Slave address 3 matching is disabled.,1: Slave address 3 matching is enabled."
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bitfld.long 0x4 29. "SADR2EN,Slave Address 2 Enable" "0: Slave address 2 matching is disabled.,1: Slave address 2 matching is enabled."
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bitfld.long 0x4 28. "SADR1EN,Slave Address 1 Enable" "0: Slave address 1 matching is disabled.,1: Slave address 1 matching is enabled."
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hexmask.long.byte 0x4 16.--22. 1. "SADR,Slave Address"
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hexmask.long.byte 0x4 8.--14. 1. "MASK,Slave Address Mask"
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bitfld.long 0x4 7. "SNIFF,Slave Sniffer Mode" "0: Slave Sniffer mode is disabled.,1: Slave Sniffer mode is enabled."
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bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0: No effect.,1: Clock stretching disabled in Slave mode OVRE and.."
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bitfld.long 0x4 5. "BSEL,TWI Bus Selection" "0: TWI analyzes the TWCK and TWD pins from its TWI..,1: TWI analyzes the TWCK pins TWD from consecutive.."
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bitfld.long 0x4 4. "SADAT,Slave Address Treated as Data" "0: Slave address is handled normally (will not trig..,1: Slave address is handled as data field RXRDY.."
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bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0: Acknowledge of the SMBus Host Header disabled.,1: Acknowledge of the SMBus Host Header enabled."
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bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0: Acknowledge of the SMBus Default Address disabled.,1: Acknowledge of the SMBus Default Address enabled."
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bitfld.long 0x4 0. "NACKEN,Slave Receiver Data Phase NACK Enable" "0: Normal value to be returned in the ACK cycle of..,1: NACK value to be returned in the ACK cycle of.."
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line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
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hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
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line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
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hexmask.long.byte 0xC 24.--29. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
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bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
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bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
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hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
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rgroup.long 0x620++0x3
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line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
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bitfld.long 0x0 26. "SR,Start Repeated" "0: No repeated start has been detected since last..,1: At least one repeated start has been detected.."
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bitfld.long 0x0 25. "SDA,SDA Line Value" "0: SDA line sampled value is '0'.,1: SDA line sampled value is '1'."
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bitfld.long 0x0 24. "SCL,SCL Line Value" "0: SCL line sampled value is '0'.,1: SCL line sampled value is '1.'"
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bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0: The TWI is not locked.,1: The TWI is locked due to frame errors (see.."
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0: No SMBus Host Header Address received.,1: A SMBus Host Header Address was received."
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0: No SMBus Default Address received.,1: A SMBus Default Address was received."
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bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0: No SMBus PEC error occurred.,1: A SMBus PEC error occurred."
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bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0: No SMBus timeout occurred.,1: SMBus timeout occurred."
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bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag" "0: No SMBus slave drives the SMBALERT line.,1: At least one SMBus slave drives the SMBALERT line."
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0: No master code has been received.,1: A master code has been received."
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0: A slave access is being performing.,1: The Slave Access is finished. End Of Slave.."
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bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0: The clock is not stretched.,1: The clock is stretched. FLEX_TWI_THR /.."
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0: Arbitration won.,1: Arbitration lost. Another master of the TWI bus.."
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bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0: Each data byte has been correctly received by..,1: In Read mode a data byte has not been.."
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bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0: FLEX_TWI_THR has been filled on time.,1: FLEX_TWI_THR has not been filled on time."
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bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0: FLEX_TWI_RHR has not been loaded while RXRDY was..,1: FLEX_TWI_RHR has been loaded while RXRDY was.."
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bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0: No general call has been detected.,1: A general call has been detected. After the.."
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newline
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bitfld.long 0x0 4. "SVACC,Slave Access" "0: TWI is not addressed. SVACC is automatically..,1: Indicates that the address decoding sequence has.."
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bitfld.long 0x0 3. "SVREAD,Slave Read" "0: Indicates that a write access is performed by a..,1: Indicates that a read access is performed by a.."
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0: Transmit FIFO is full and cannot accept more data,1: Transmit FIFO is not full; one or more data can.."
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0: Receive FIFO is empty; no data to read,1: At least one unread data is in the Receive FIFO"
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0: As soon as a Start is detected.,1: After a Stop or a Repeated Start + an address.."
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rgroup.long 0x620++0x3
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line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
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bitfld.long 0x0 26. "SR,Start Repeated" "0: No repeated start has been detected since last..,1: At least one repeated start has been detected.."
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bitfld.long 0x0 25. "SDA,SDA Line Value" "0: SDA line sampled value is '0'.,1: SDA line sampled value is '1'."
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bitfld.long 0x0 24. "SCL,SCL Line Value" "0: SCL line sampled value is '0'.,1: SCL line sampled value is '1.'"
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bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0: The Transmit FIFO is not locked.,1: The Transmit FIFO is locked."
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0: No SMBus Host Header Address received.,1: A SMBus Host Header Address was received."
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0: No SMBus Default Address received.,1: A SMBus Default Address was received."
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bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0: No SMBus PEC error occurred.,1: A SMBus PEC error occurred."
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bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0: No SMBus timeout occurred.,1: SMBus timeout occurred."
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bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag" "0: No SMBus slave drives the SMBALERT line.,1: At least one SMBus slave drives the SMBALERT line."
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0: No master code has been received.,1: A master code has been received."
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0: A slave access is being performing.,1: The Slave Access is finished. End Of Slave.."
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bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0: The clock is not stretched.,1: The clock is stretched. FLEX_TWI_THR /.."
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0: Arbitration won.,1: Arbitration lost. Another master of the TWI bus.."
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bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0: Each data byte has been correctly received by..,1: In Read mode a data byte has not been.."
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bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0: FLEX_TWI_THR has been filled on time.,1: FLEX_TWI_THR has not been filled on time."
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bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0: FLEX_TWI_RHR has not been loaded while RXRDY was..,1: FLEX_TWI_RHR has been loaded while RXRDY was.."
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newline
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bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0: No general call has been detected.,1: A general call has been detected. After the.."
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newline
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bitfld.long 0x0 4. "SVACC,Slave Access" "0: TWI is not addressed. SVACC is automatically..,1: Indicates that the address decoding sequence has.."
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bitfld.long 0x0 3. "SVREAD,Slave Read" "0: Indicates that a write access is performed by a..,1: Indicates that a read access is performed by a.."
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0: Transmit FIFO is full and cannot accept more data.,1: Transmit FIFO is not full; one or more data can.."
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0: Receive FIFO is empty; no data to read.,1: At least one unread data is in the Receive FIFO."
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0: As soon as a Start is detected.,1: After a Stop or a Repeated Start + an address.."
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wgroup.long 0x624++0x7
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line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Enable" "0,1"
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bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
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bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
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bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
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bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Enable" "0,1"
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bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
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bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
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bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
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bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
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bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
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bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
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bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
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bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
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bitfld.long 0x4 16. "MCACK,Master Code Acknowledge Interrupt Disable" "0,1"
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bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
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bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
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bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
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bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
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bitfld.long 0x4 11. "EOSACC,End Of Slave Access Interrupt Disable" "0,1"
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bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
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bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
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bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
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bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
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bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
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bitfld.long 0x4 4. "SVACC,Slave Access Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
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rgroup.long 0x62C++0x7
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line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
|
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
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bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
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bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Mask" "0,1"
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bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
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bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
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bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
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bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Mask" "0,1"
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bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
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bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
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bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
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bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Mask" "0,1"
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
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bitfld.long 0x4 11.--12. "ASTATE,Acknowledge State (Slave Sniffer Mode only)" "0: No Acknowledge or Nacknowledge detected after..,1: Acknowledge (A) detected after previously logged..,2: Nacknowledge (NA) detected after previously..,3: Not defined"
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bitfld.long 0x4 10. "PSTATE,Stop State (Slave Sniffer Mode only)" "0: No STOP (P) detected after previous logged data.,1: Stop detected (P) after previous logged data."
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bitfld.long 0x4 8.--9. "SSTATE,Start State (Slave Sniffer Mode only)" "0: No START detected with the logged data,1: START (S) detected with the logged data,2: Repeated START (Sr) detected with the logged data,3: Not defined"
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hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Master or Slave Receive Holding Data"
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rgroup.long 0x630++0x3
|
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line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Master or Slave Receive Holding Data 3"
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hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Master or Slave Receive Holding Data 2"
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hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Master or Slave Receive Holding Data 1"
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hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Master or Slave Receive Holding Data 0"
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wgroup.long 0x634++0x3
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line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Master or Slave Transmit Holding Data"
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wgroup.long 0x634++0x3
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line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Master or Slave Transmit Holding Data 3"
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hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Master or Slave Transmit Holding Data 2"
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hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Master or Slave Transmit Holding Data 1"
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Master or Slave Transmit Holding Data 0"
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group.long 0x638++0x1B
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line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
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hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Master Clock Stretch Maximum Cycles"
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hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Slave Clock Stretch Maximum Cycles"
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hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
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line.long 0x4 "FLEX_TWI_HSR,TWI High Speed Register"
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hexmask.long.byte 0x4 0.--7. 1. "MCODE,TWI High Speed Master Code"
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line.long 0x8 "FLEX_TWI_ACR,TWI Alternative Command Register"
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bitfld.long 0x8 25. "NPEC,Next PEC Request (SMBus Mode only)" "0: The next transfer does not use a PEC byte.,1: The next transfer uses a PEC byte."
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bitfld.long 0x8 24. "NDIR,Next Transfer Direction" "0: Write direction.,1: Read direction."
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hexmask.long.byte 0x8 16.--23. 1. "NDATAL,Next Data Length"
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bitfld.long 0x8 9. "PEC,PEC Request (SMBus Mode only)" "0: The transfer does not use a PEC byte.,1: The transfer uses a PEC byte."
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bitfld.long 0x8 8. "DIR,Transfer Direction" "0: Write direction.,1: Read direction."
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hexmask.long.byte 0x8 0.--7. 1. "DATAL,Data Length"
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line.long 0xC "FLEX_TWI_FILTR,TWI Filter Register"
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bitfld.long 0xC 8.--10. "THRES,Digital Filter Threshold" "0: No filtering applied on TWI inputs.,?,?,?,?,?,?,?"
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newline
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bitfld.long 0xC 1. "PADFEN,PAD Filter Enable" "0: PAD analog filter is disabled.,1: PAD analog filter is enabled. (The analog filter.."
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newline
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bitfld.long 0xC 0. "FILT,RX Digital Filter" "0: No filtering applied on TWI inputs.,1: TWI input filtering is active. (Only in Standard.."
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line.long 0x10 "FLEX_TWI_HSCWGR,TWI High Speed Clock Waveform Generator Register"
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bitfld.long 0x10 16.--18. "HSCKDIV,High Speed Clock Divider" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x10 8.--15. 1. "HSCHDIV,High Speed Clock High Divider"
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hexmask.long.byte 0x10 0.--7. 1. "HSCLDIV,High Speed Clock Low Divider"
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line.long 0x14 "FLEX_TWI_SWMR,TWI Matching Register"
|
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hexmask.long.byte 0x14 24.--31. 1. "DATAM,Data Match"
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hexmask.long.byte 0x14 16.--22. 1. "SADR3,Slave Address 3"
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hexmask.long.byte 0x14 8.--14. 1. "SADR2,Slave Address 2"
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hexmask.long.byte 0x14 0.--6. 1. "SADR1,Slave Address 1"
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line.long 0x18 "FLEX_TWI_FMR,TWI FIFO Mode Register"
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hexmask.long.byte 0x18 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
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hexmask.long.byte 0x18 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
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bitfld.long 0x18 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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newline
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bitfld.long 0x18 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x654++0x3
|
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line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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newline
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
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rgroup.long 0x660++0x3
|
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line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
|
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bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0: No Receive FIFO pointer occurred,1: Receive FIFO pointer error occurred. Receiver.."
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newline
|
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bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0: No Transmit FIFO pointer occurred,1: Transmit FIFO pointer error occurred."
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newline
|
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bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0: Number of unread data in Receive FIFO is below..,1: Number of unread data in Receive FIFO has.."
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newline
|
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bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0: Receive FIFO is not empty.,1: Receive FIFO has been filled since the last read.."
|
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newline
|
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bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0: Receive FIFO is not empty.,1: Receive FIFO has been emptied since the last.."
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newline
|
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bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0: Number of data in Transmit FIFO is above..,1: Number of data in Transmit FIFO has reached.."
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newline
|
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bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0: Transmit FIFO is not full.,1: Transmit FIFO has been filled since the last.."
|
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newline
|
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bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0: Transmit FIFO is not empty.,1: Transmit FIFO has been emptied since the last.."
|
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wgroup.long 0x664++0x7
|
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line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
|
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
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line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
|
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x66C++0x3
|
|
line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
group.long 0x6E4++0x3
|
|
line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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newline
|
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
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newline
|
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
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newline
|
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
|
|
rgroup.long 0x6E8++0x3
|
|
line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protect Violation Status" "0: No Write Protection Violation has occurred since..,1: A Write Protection Violation has occurred since.."
|
|
tree.end
|
|
tree "FLEXCOM8"
|
|
base ad:0xE2818000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
|
|
bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected. USART/TWI..,3: All TWI related protocols are selected (TWI.."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
|
|
wgroup.long 0x200++0x3
|
|
line.long 0x0 "FLEX_US_CR,USART Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0: No effect.,1: Disables the Transmit and Receive FIFOs."
|
|
newline
|
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0: No effect.,1: Enables the Transmit and Receive FIFOs."
|
|
newline
|
|
bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0: No effect.,1: Restarts the comparison trigger to enable.."
|
|
newline
|
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bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0: No effect.,1: Clears the Transmit FIFO Lock"
|
|
newline
|
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bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0: No effect.,1: Empties the Receive FIFO."
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0: No effect.,1: Empties the Transmit FIFO."
|
|
newline
|
|
bitfld.long 0x0 21. "LINWKUP,Send LIN Wakeup Signal" "0: No effect:,1: Sends a wakeup signal on the LIN bus."
|
|
newline
|
|
bitfld.long 0x0 20. "LINABT,Abort LIN Transmission" "0: No effect.,1: Aborts the current LIN transmission."
|
|
newline
|
|
bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0: No effect.,1: Drives the RTS pin to 0 if FLEX_US_MR.USART_MODE.."
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newline
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bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0: No effect.,1: Drives the RTS pin to 1 if FLEX_US_MR.USART_MODE.."
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bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0: No effect,1: Immediately restarts timeout period."
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bitfld.long 0x0 14. "RSTNACK,Reset Non Acknowledge" "0: No effect,1: Resets FLEX_US_CSR.NACK."
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bitfld.long 0x0 13. "RSTIT,Reset Iterations" "0: No effect.,1: Resets FLEX_US_CSR.ITER. No effect if the.."
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bitfld.long 0x0 12. "SENDA,Send Address" "0: No effect.,1: In Multidrop mode only the next character.."
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bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0: No effect.,1: Starts waiting for a character before clocking.."
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bitfld.long 0x0 10. "STPBRK,Stop Break" "0: No effect.,1: Stops transmission of the break after a minimum.."
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bitfld.long 0x0 9. "STTBRK,Start Break" "0: No effect.,1: Starts transmission of a break after the.."
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bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0: No effect.,1: Resets the status bits PARE FRAME OVRE MANE.."
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bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0: No effect.,1: Disables the transmitter."
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bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0: No effect.,1: Enables the transmitter if TXDIS is 0."
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bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0: No effect.,1: Disables the receiver."
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bitfld.long 0x0 4. "RXEN,Receiver Enable" "0: No effect.,1: Enables the receiver if RXDIS is 0."
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bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0: No effect.,1: Resets the transmitter."
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bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0: No effect.,1: Resets the receiver."
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group.long 0x204++0x3
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line.long 0x0 "FLEX_US_MR,USART Mode Register"
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bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0: Start frame delimiter is COMMAND or DATA SYNC.,1: Start frame delimiter is one bit."
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bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0: The Manchester start bit is a 0 to 1 transition,1: The Manchester start bit is a 1 to 0 transition."
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bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0: Manchester encoder/decoder are disabled.,1: Manchester encoder/decoder are enabled."
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bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0: The USART does not filter the receive line.,1: The USART filters the receive line using a.."
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bitfld.long 0x0 24.--26. "MAX_ITERATION,Maximum Number of Automatic Iteration" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 23. "INVDATA,Inverted Data" "0: The data field transmitted on TXD line is the..,1: The data field transmitted on TXD line is.."
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bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0: User defined configuration of command or data..,1: The sync field is updated when a character is.."
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bitfld.long 0x0 21. "DSNACK,Disable Successive NACK" "0: NACK is sent on the ISO line as soon as a parity..,1: Successive parity errors are counted up to the.."
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bitfld.long 0x0 20. "INACK,Inhibit Non Acknowledge" "0: The NACK is generated.,1: The NACK is not generated."
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bitfld.long 0x0 19. "OVER,Oversampling Mode" "0: 16x Oversampling.,1: 8x Oversampling."
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bitfld.long 0x0 18. "CLKO,Clock Output Select" "0: The USART does not drive the SCK pin..,1: The USART drives the SCK pin if USCLKS does not.."
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bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0: CHRL defines character length.,1: 9-bit character length."
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bitfld.long 0x0 16. "MSBF,Bit Order" "0: Least significant bit is sent/received first.,1: Most significant bit is sent/received first."
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bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
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bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
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bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
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bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0: USART operates in Asynchronous mode (UART).,1: USART operates in Synchronous mode."
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bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
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bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
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hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
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wgroup.long 0x208++0x3
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line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Enable" "0,1"
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bitfld.long 0x0 10. "ITER,Max number of Repetitions Reached Interrupt Enable" "0,1"
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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wgroup.long 0x208++0x7
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line.long 0x0 "FLEX_US_IER_LIN_MODE,USART Interrupt Enable Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Enable" "0,1"
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Enable" "0,1"
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Enable" "0,1"
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Enable" "0,1"
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Enable" "0,1"
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Enable" "0,1"
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Enable" "0,1"
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Enable" "0,1"
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Enable" "0,1"
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Enable" "0,1"
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
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bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
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bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt Disable" "0,1"
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bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached Interrupt Disable" "0,1"
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bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
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bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
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bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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wgroup.long 0x20C++0x3
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line.long 0x0 "FLEX_US_IDR_LIN_MODE,USART Interrupt Disable Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Disable" "0,1"
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Disable" "0,1"
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Disable" "0,1"
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Disable" "0,1"
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Disable" "0,1"
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Disable" "0,1"
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Disable" "0,1"
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Disable" "0,1"
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Disable" "0,1"
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Disable" "0,1"
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Disable" "0,1"
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Disable" "0,1"
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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rgroup.long 0x210++0x3
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line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Mask" "0,1"
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bitfld.long 0x0 10. "ITER,Max Number of Repetitions Reached Interrupt Mask" "0,1"
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
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rgroup.long 0x210++0x7
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line.long 0x0 "FLEX_US_IMR_LIN_MODE,USART Interrupt Mask Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Mask" "0,1"
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Mask" "0,1"
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Mask" "0,1"
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Mask" "0,1"
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Mask" "0,1"
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Mask" "0,1"
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Mask" "0,1"
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Mask" "0,1"
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "0,1"
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Mask" "0,1"
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
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bitfld.long 0x4 24. "MANE,Manchester Error" "0: No Manchester error has been detected since the..,1: At least one Manchester error has been detected.."
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bitfld.long 0x4 23. "CTS,Image of CTS Input" "0: CTS input is driven low.,1: CTS input is driven high."
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bitfld.long 0x4 22. "CMP,Comparison Status" "0: No received character matched the comparison..,1: A received character matched the comparison.."
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0: No input change has been detected on the CTS pin..,1: At least one input change has been detected on.."
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt" "0: Non acknowledge has not been detected since the..,1: At least one non acknowledge has been detected.."
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bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached" "0: Maximum number of repetitions has not been..,1: Maximum number of repetitions has been reached.."
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bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0: There are characters in either FLEX_US_THR or..,1: There are no characters in FLEX_US_THR nor in.."
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bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0: There has not been a timeout since the last..,1: There has been a timeout since the last Start.."
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bitfld.long 0x4 7. "PARE,Parity Error" "0: No parity error has been detected since the last..,1: At least one parity error has been detected.."
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bitfld.long 0x4 6. "FRAME,Framing Error" "0: No stop bit has been detected low since the last..,1: At least one stop bit has been detected low.."
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bitfld.long 0x4 5. "OVRE,Overrun Error" "0: No overrun error has occurred since the last..,1: At least one overrun error has occurred since.."
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bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0: No break received or end of break detected since..,1: Break received or end of break detected since.."
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bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0: Transmit FIFO is full and cannot accept more data,1: Transmit FIFO is not full; one or more data can.."
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bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0: Receive FIFO is empty; no data to read,1: At least one unread data is in the Receive FIFO"
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rgroup.long 0x214++0x7
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line.long 0x0 "FLEX_US_CSR_LIN_MODE,USART Channel Status Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error" "0: No LIN header timeout error has been detected..,1: A LIN header timeout error has been detected.."
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error" "0: No LIN synch tolerance error has been detected..,1: A LIN synch tolerance error has been detected.."
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error" "0: No LIN slave not responding error has been..,1: A LIN slave not responding error has been.."
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error" "0: No LIN checksum error has been detected since..,1: A LIN checksum error has been detected since the.."
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Error" "0: No LIN identifier parity error has been detected..,1: A LIN identifier parity error has been detected.."
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error" "0: No LIN inconsistent synch field error has been..,1: The USART is configured as a slave node and a.."
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bitfld.long 0x0 25. "LINBE,LIN Bit Error" "0: No bit error has been detected since the last..,1: A bit error has been detected since the last.."
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bitfld.long 0x0 23. "LINBLS,LIN Bus Line Status" "0: LIN bus line is set to 0.,1: LIN bus line is set to 1."
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed" "0: The USART is idle or a LIN transfer is ongoing.,1: A LIN transfer has been completed since the last.."
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received" "0: No LIN identifier has been received since the..,1: At least one LIN identifier has been received.."
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received" "0: No LIN break has received sent since the last..,1: At least one LIN break has been received since.."
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bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0: There are characters in either FLEX_US_THR or..,1: There are no characters in FLEX_US_THR nor in.."
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bitfld.long 0x0 8. "TIMEOUT,Receiver Timeout" "0: There has not been a timeout since the last..,1: There has been a timeout since the last start.."
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bitfld.long 0x0 7. "PARE,Parity Error" "0: No parity error has been detected since the last..,1: At least one parity error has been detected.."
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bitfld.long 0x0 6. "FRAME,Framing Error" "0: No stop bit has been detected low since the last..,1: At least one stop bit has been detected low.."
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bitfld.long 0x0 5. "OVRE,Overrun Error" "0: No overrun error has occurred since the last..,1: At least one overrun error has occurred since.."
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bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0: A character in FLEX_US_THR is waiting to be..,1: There is no character in FLEX_US_THR."
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bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0: No complete character has been received since..,1: At least one complete character has been.."
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line.long 0x4 "FLEX_US_RHR,USART Receive Holding Register"
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bitfld.long 0x4 15. "RXSYNH,Received Sync" "0: Last character received is a data.,1: Last character received is a command."
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hexmask.long.word 0x4 0.--8. 1. "RXCHR,Received Character"
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rgroup.long 0x218++0x3
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line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Characters"
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hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Characters"
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hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Characters"
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hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Characters"
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wgroup.long 0x21C++0x3
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line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
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bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0: The next character sent is encoded as a data.,1: The next character sent is encoded as a command."
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hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
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wgroup.long 0x21C++0x3
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line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
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hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
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hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
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hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
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group.long 0x220++0xB
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line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
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bitfld.long 0x0 16.--18. "FP,Fractional Part" "0: Fractional divider is disabled.,?,?,?,?,?,?,?"
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hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
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line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
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hexmask.long.tbyte 0x4 0.--16. 1. "TO,Timeout Value"
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line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
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hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
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group.long 0x240++0x3
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line.long 0x0 "FLEX_US_FIDI,USART FI DI Ratio Register"
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hexmask.long.word 0x0 0.--15. 1. "FI_DI_RATIO,FI Over DI Ratio Value"
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rgroup.long 0x244++0x3
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line.long 0x0 "FLEX_US_NER,USART Number of Errors Register"
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hexmask.long.byte 0x0 0.--7. 1. "NB_ERRORS,Number of Errors"
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group.long 0x24C++0xF
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line.long 0x0 "FLEX_US_IF,USART IrDA Filter Register"
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hexmask.long.byte 0x0 0.--7. 1. "IRDA_FILTER,IrDA Filter"
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line.long 0x4 "FLEX_US_MAN,USART Manchester Configuration Register"
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bitfld.long 0x4 31. "RXIDLEV,Receiver Idle Value" "0: Receiver line idle value is 0.,1: Receiver line idle value is 1."
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bitfld.long 0x4 30. "DRIFT,Drift Compensation" "0: The USART cannot recover from an important clock..,1: The USART can recover from clock drift. The 16X.."
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bitfld.long 0x4 29. "ONE,Must Be Set to 1" "0,1"
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bitfld.long 0x4 28. "RX_MPOL,Receiver Manchester Polarity" "0: Logic zero is coded as a zero-to-one transition..,1: Logic zero is coded as a one-to-zero transition.."
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bitfld.long 0x4 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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hexmask.long.byte 0x4 16.--19. 1. "RX_PL,Receiver Preamble Length"
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bitfld.long 0x4 12. "TX_MPOL,Transmitter Manchester Polarity" "0: Logic zero is coded as a zero-to-one transition..,1: Logic zero is coded as a one-to-zero transition.."
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bitfld.long 0x4 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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hexmask.long.byte 0x4 0.--3. 1. "TX_PL,Transmitter Preamble Length"
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line.long 0x8 "FLEX_US_LINMR,USART LIN Mode Register"
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bitfld.long 0x8 17. "SYNCDIS,Synchronization Disable" "0: The synchronization procedure is performed in..,1: The synchronization procedure is not performed.."
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bitfld.long 0x8 16. "PDCM,DMAC Mode" "0: The LIN mode register FLEX_US_LINMR is not..,1: The LIN mode register FLEX_US_LINMR (excepting.."
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hexmask.long.byte 0x8 8.--15. 1. "DLC,Data Length Control"
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bitfld.long 0x8 7. "WKUPTYP,Wakeup Signal Type" "0: Setting the LINWKUP bit in the control register..,1: Setting the LINWKUP bit in the control register.."
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bitfld.long 0x8 6. "FSDIS,Frame Slot Mode Disable" "0: The Frame Slot mode is enabled.,1: The Frame Slot mode is disabled."
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bitfld.long 0x8 5. "DLM,Data Length Mode" "0: The response data length is defined by the DLC..,1: The response data length is defined by the bits.."
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bitfld.long 0x8 4. "CHKTYP,Checksum Type" "0: LIN 2.0 'enhanced' checksum,1: LIN 1.3 'classic' checksum"
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bitfld.long 0x8 3. "CHKDIS,Checksum Disable" "0: In master node configuration the checksum is..,1: Whatever the node configuration is the checksum.."
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bitfld.long 0x8 2. "PARDIS,Parity Disable" "0: In master node configuration the identifier..,1: Whatever the node configuration is the.."
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bitfld.long 0x8 0.--1. "NACT,LIN Node Action" "0: The USART transmits the response.,1: The USART receives the response.,2: The USART does not transmit and does not receive..,?"
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line.long 0xC "FLEX_US_LINIR,USART LIN Identifier Register"
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hexmask.long.byte 0xC 0.--7. 1. "IDCHR,Identifier Character"
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rgroup.long 0x25C++0x3
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line.long 0x0 "FLEX_US_LINBRR,USART LIN Baud Rate Register"
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bitfld.long 0x0 16.--18. "LINFP,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x0 0.--15. 1. "LINCD,Clock Divider after Synchronization"
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group.long 0x290++0x3
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line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
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hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
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bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0: The parity is not checked and a bad parity..,1: The parity is checked and a matching condition.."
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bitfld.long 0x0 12.--13. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start..,2: Comparison must be met to receive the current..,?"
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hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
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group.long 0x2A0++0x3
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line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
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hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
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hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
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bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0: RTS pin is not controlled by Receive FIFO..,1: RTS pin is controlled by Receive FIFO thresholds."
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bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x2A4++0x3
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line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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wgroup.long 0x2A8++0x7
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line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
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bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
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rgroup.long 0x2B0++0x7
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line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
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bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Number of unread data in Receive FIFO is above..,1: Number of unread data in Receive FIFO has.."
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bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0: The Transmit FIFO is not locked.,1: The Transmit FIFO is locked."
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bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0: No Receive FIFO pointer occurred,1: Receive FIFO pointer error occurred. Receiver.."
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bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0: No Transmit FIFO pointer occurred,1: Transmit FIFO pointer error occurred."
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bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Number of unread data in Receive FIFO is below..,1: Number of unread data in Receive FIFO has.."
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bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Receive FIFO is not empty.,1: Receive FIFO has been filled since the last.."
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bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Receive FIFO is not empty.,1: Receive FIFO has been emptied since the last.."
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bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Number of data in Transmit FIFO is above..,1: Number of data in Transmit FIFO has reached.."
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bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Transmit FIFO is not full.,1: Transmit FIFO has been filled since the last.."
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bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Transmit FIFO is not empty.,1: Transmit FIFO has been emptied since the last.."
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group.long 0x2E4++0x3
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line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection on configuration..,1: Enables the write protection on configuration.."
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rgroup.long 0x2E8++0x3
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line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
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hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
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wgroup.long 0x400++0x3
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line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
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bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0: No effect.,1: Disables the Transmit and Receive FIFOs"
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0: No effect.,1: Enables the Transmit and Receive FIFOs"
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bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0: No effect.,1: The current NPCS will be de-asserted after the.."
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bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0: No effect.,1: Empties the Receive FIFO."
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bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0: No effect.,1: Empties the Transmit FIFO."
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bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0: No effect.,1: Restarts the comparison trigger to enable.."
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bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0: No effect.,1: Reset the SPI. A software-triggered hardware.."
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bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0: No effect.,1: Disables the SPI."
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bitfld.long 0x0 0. "SPIEN,SPI Enable" "0: No effect.,1: Enables the SPI to transfer and receive data."
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group.long 0x404++0x3
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line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
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hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
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bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0: Local loopback path disabled.,1: Local loopback path enabled."
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bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0: No Effect. In Master mode a transfer can be..,1: In Master mode a transfer can start only if.."
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bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0: Mode fault detection is enabled.,1: Mode fault detection is disabled."
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bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
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bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0: The chip selects are directly connected to a..,1: The four NPCS chip select lines are connected to.."
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bitfld.long 0x0 1. "PS,Peripheral Select" "0: Fixed Peripheral Select,1: Variable Peripheral Select"
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bitfld.long 0x0 0. "MSTR,Master/Slave Mode" "0: SPI is in Slave mode.,1: SPI is in Master mode."
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rgroup.long 0x408++0x3
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line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
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rgroup.long 0x408++0x3
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line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
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hexmask.long.word 0x0 16.--31. 1. "RD1,Receive Data"
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hexmask.long.word 0x0 0.--15. 1. "RD0,Receive Data"
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rgroup.long 0x408++0x3
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line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
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hexmask.long.byte 0x0 24.--31. 1. "RD3,Receive Data"
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hexmask.long.byte 0x0 16.--23. 1. "RD2,Receive Data"
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hexmask.long.byte 0x0 8.--15. 1. "RD1,Receive Data"
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hexmask.long.byte 0x0 0.--7. 1. "RD0,Receive Data"
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wgroup.long 0x40C++0x3
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line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
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bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0: No effect.,1: The current NPCS is de-asserted after the.."
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newline
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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newline
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hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
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wgroup.long 0x40C++0x3
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line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
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hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
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newline
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hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
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rgroup.long 0x410++0x3
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line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
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bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0: No Receive FIFO pointer occurred,1: Receive FIFO pointer error occurred. Receiver.."
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newline
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bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0: No Transmit FIFO pointer occurred,1: Transmit FIFO pointer error occurred."
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newline
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bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0: Number of unread data in Receive FIFO is below..,1: Number of unread data in Receive FIFO has.."
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newline
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bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0: Receive FIFO is not empty or RXFE flag has been..,1: Receive FIFO has been filled (changing states.."
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newline
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bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0: Receive FIFO is not empty or RXFE flag has been..,1: Receive FIFO has been emptied (changing states.."
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newline
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bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0: Number of data in Transmit FIFO is above..,1: Number of data in Transmit FIFO has reached.."
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newline
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bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0: Transmit FIFO is not full or TXFF flag has been..,1: Transmit FIFO has been filled since the last.."
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newline
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bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0: Transmit FIFO is not empty.,1: Transmit FIFO has been emptied since the last.."
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newline
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bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0: SPI is disabled.,1: SPI is enabled."
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newline
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bitfld.long 0x0 12. "SFERR,Slave Frame Error (cleared on read)" "0: There is no frame error detected for a slave..,1: In Slave mode the chip select raised while the.."
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newline
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bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0: No received character matched the comparison..,1: A received character matched the comparison.."
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newline
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bitfld.long 0x0 10. "UNDES,Underrun Error Status (Slave mode only) (cleared on read)" "0: No underrun has been detected since the last..,1: A transfer starts whereas no data has been.."
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newline
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0: As soon as data is written in FLEX_SPI_TDR.,1: FLEX_SPI_TDR and internal shift register are.."
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newline
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bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0: No rising edge detected on NSS pin since the..,1: A rising edge occurred on NSS pin since the last.."
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newline
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bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0: No overrun has been detected since the last read..,1: An overrun has occurred since the last read of.."
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newline
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bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0: No mode fault has been detected since the last..,1: A mode fault occurred since the last read of.."
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newline
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bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0: Transmit FIFO cannot accept more data.,1: Transmit FIFO can accept data; one or more data.."
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newline
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0: Receive FIFO is empty; no data to read,1: At least one unread data is in the Receive FIFO"
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wgroup.long 0x414++0x7
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line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
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bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
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newline
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bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
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bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
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newline
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bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
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rgroup.long 0x41C++0x3
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line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
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bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
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newline
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bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
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repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
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group.long ($2+0x430)++0x3
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line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register x"
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hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
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newline
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hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
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newline
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bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0: The Peripheral Chip Select Line rises as soon as..,1: The Peripheral Chip Select does not rise after.."
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newline
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bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0: The Peripheral Chip Select does not rise between..,1: The Peripheral Chip Select rises systematically.."
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newline
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bitfld.long 0x0 1. "NCPHA,Clock Phase" "0: Data are changed on the leading edge of SPCK and..,1: Data are captured on the leading edge of SPCK.."
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newline
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bitfld.long 0x0 0. "CPOL,Clock Polarity" "0: The inactive state value of SPCK is logic level..,1: The inactive state value of SPCK is logic level.."
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repeat.end
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group.long 0x440++0x3
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line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
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newline
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hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
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newline
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bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
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newline
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bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
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rgroup.long 0x444++0x3
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line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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newline
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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group.long 0x448++0x3
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line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
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hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
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newline
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hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
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group.long 0x4E4++0x3
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line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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newline
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
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newline
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
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newline
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
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rgroup.long 0x4E8++0x3
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line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
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hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
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newline
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0: No write protect violation has occurred since..,1: A write protect violation has occurred since the.."
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wgroup.long 0x600++0x3
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line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
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bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0: No effect.,1: Disable the Transmit and Receive FIFOs"
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newline
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bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0: No effect.,1: Enable the Transmit and Receive FIFOs"
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newline
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bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0: No effect.,1: Clear the TWI FSM lock."
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newline
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bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0: No effect.,1: Clear the Transmit Holding Register and set.."
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newline
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bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0: No effect.,1: Alternative Command mode disabled."
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newline
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bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0: No effect.,1: Alternative Command mode enabled."
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newline
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bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0: No effect.,1: If Master mode is enabled send a bus clear.."
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newline
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bitfld.long 0x0 14. "PECRQ,PEC Request" "0: No effect.,1: A PEC check or transmission is requested."
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newline
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bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0: No effect.,1: SMBus PEC (CRC) generation and check disabled."
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newline
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bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0: No effect.,1: SMBus PEC (CRC) generation and check enabled."
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newline
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bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0: No effect.,1: SMBus mode disabled."
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newline
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bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0: No effect.,1: If SMBDIS = 0 SMBus mode enabled."
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newline
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bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0: No effect.,1: High-speed mode disabled."
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newline
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bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0: No effect.,1: High-speed mode enabled."
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newline
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bitfld.long 0x0 7. "SWRST,Software Reset" "0: No effect.,1: Equivalent to a system reset."
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newline
|
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bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0: No effect.,1: If Master mode is enabled a SMBus Quick Command.."
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newline
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bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0: No effect.,1: The Slave mode is disabled. The shifter and.."
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newline
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bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0: No effect.,1: Enables the Slave mode (SVDIS must be written to.."
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newline
|
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bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0: No effect.,1: The Master mode is disabled all pending data is.."
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newline
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bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0: No effect.,1: Enables the Master mode (MSDIS must be written.."
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newline
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bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0: No effect.,1: STOP condition is sent just after completing the.."
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newline
|
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bitfld.long 0x0 0. "START,Send a START Condition" "0: No effect.,1: A frame beginning with a START bit is.."
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wgroup.long 0x600++0x3
|
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line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0: No effect.,1: Disable the Transmit and Receive FIFOs."
|
|
newline
|
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bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0: No effect.,1: Enable the Transmit and Receive FIFOs."
|
|
newline
|
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bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0: No effect.,1: Clears the Transmit FIFO Lock."
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|
newline
|
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bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0: No effect.,1: Empties the Receive FIFO."
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|
newline
|
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bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0: No effect.,1: Empties the Transmit FIFO."
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|
newline
|
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bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0: No effect.,1: Alternative Command mode disabled."
|
|
newline
|
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bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0: No effect.,1: Alternative Command mode enabled."
|
|
newline
|
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bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0: No effect.,1: If Master mode is enabled send a bus clear.."
|
|
newline
|
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bitfld.long 0x0 14. "PECRQ,PEC Request" "0: No effect.,1: A PEC check or transmission is requested."
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0: No effect.,1: SMBus PEC (CRC) generation and check disabled."
|
|
newline
|
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bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0: No effect.,1: SMBus PEC (CRC) generation and check enabled."
|
|
newline
|
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bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0: No effect.,1: SMBus mode disabled."
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0: No effect.,1: If SMBDIS = 0 SMBus mode enabled."
|
|
newline
|
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bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0: No effect.,1: High-speed mode disabled."
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0: No effect.,1: High-speed mode enabled."
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0: No effect.,1: Equivalent to a system reset."
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0: No effect.,1: If Master mode is enabled a SMBus Quick Command.."
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0: No effect.,1: The Slave mode is disabled. The shifter and.."
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0: No effect.,1: Enables the Slave mode (SVDIS must be written to.."
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0: No effect.,1: The Master mode is disabled all pending data is.."
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0: No effect.,1: Enables the Master mode (MSDIS must be written.."
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0: No effect.,1: STOP condition is sent just after completing the.."
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0: No effect.,1: A frame beginning with a START bit is.."
|
|
group.long 0x604++0xF
|
|
line.long 0x0 "FLEX_TWI_MMR,TWI Master Mode Register"
|
|
bitfld.long 0x0 24. "NOAP,No Auto-Stop On NACK Error" "0: A stop condition is sent automatically upon..,1: No automatic action is performed upon.."
|
|
newline
|
|
hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
|
|
newline
|
|
bitfld.long 0x0 13.--14. "SCLRBL,SCL Rise Boost Level" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 12. "MREAD,Master Read Direction" "0: Master write direction.,1: Master read direction."
|
|
newline
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bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
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line.long 0x4 "FLEX_TWI_SMR,TWI Slave Mode Register"
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bitfld.long 0x4 31. "DATAMEN,Data Matching Enable" "0: Data matching on first received data is disabled.,1: Data matching on first received data is enabled."
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bitfld.long 0x4 30. "SADR3EN,Slave Address 3 Enable" "0: Slave address 3 matching is disabled.,1: Slave address 3 matching is enabled."
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bitfld.long 0x4 29. "SADR2EN,Slave Address 2 Enable" "0: Slave address 2 matching is disabled.,1: Slave address 2 matching is enabled."
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bitfld.long 0x4 28. "SADR1EN,Slave Address 1 Enable" "0: Slave address 1 matching is disabled.,1: Slave address 1 matching is enabled."
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hexmask.long.byte 0x4 16.--22. 1. "SADR,Slave Address"
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hexmask.long.byte 0x4 8.--14. 1. "MASK,Slave Address Mask"
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bitfld.long 0x4 7. "SNIFF,Slave Sniffer Mode" "0: Slave Sniffer mode is disabled.,1: Slave Sniffer mode is enabled."
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bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0: No effect.,1: Clock stretching disabled in Slave mode OVRE and.."
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bitfld.long 0x4 5. "BSEL,TWI Bus Selection" "0: TWI analyzes the TWCK and TWD pins from its TWI..,1: TWI analyzes the TWCK pins TWD from consecutive.."
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bitfld.long 0x4 4. "SADAT,Slave Address Treated as Data" "0: Slave address is handled normally (will not trig..,1: Slave address is handled as data field RXRDY.."
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bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0: Acknowledge of the SMBus Host Header disabled.,1: Acknowledge of the SMBus Host Header enabled."
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bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0: Acknowledge of the SMBus Default Address disabled.,1: Acknowledge of the SMBus Default Address enabled."
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bitfld.long 0x4 0. "NACKEN,Slave Receiver Data Phase NACK Enable" "0: Normal value to be returned in the ACK cycle of..,1: NACK value to be returned in the ACK cycle of.."
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line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
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hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
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line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
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hexmask.long.byte 0xC 24.--29. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
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bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
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bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
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hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
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rgroup.long 0x620++0x3
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line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
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bitfld.long 0x0 26. "SR,Start Repeated" "0: No repeated start has been detected since last..,1: At least one repeated start has been detected.."
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bitfld.long 0x0 25. "SDA,SDA Line Value" "0: SDA line sampled value is '0'.,1: SDA line sampled value is '1'."
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bitfld.long 0x0 24. "SCL,SCL Line Value" "0: SCL line sampled value is '0'.,1: SCL line sampled value is '1.'"
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bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0: The TWI is not locked.,1: The TWI is locked due to frame errors (see.."
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0: No SMBus Host Header Address received.,1: A SMBus Host Header Address was received."
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0: No SMBus Default Address received.,1: A SMBus Default Address was received."
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bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0: No SMBus PEC error occurred.,1: A SMBus PEC error occurred."
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bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0: No SMBus timeout occurred.,1: SMBus timeout occurred."
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bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag" "0: No SMBus slave drives the SMBALERT line.,1: At least one SMBus slave drives the SMBALERT line."
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0: No master code has been received.,1: A master code has been received."
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0: A slave access is being performing.,1: The Slave Access is finished. End Of Slave.."
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bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0: The clock is not stretched.,1: The clock is stretched. FLEX_TWI_THR /.."
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0: Arbitration won.,1: Arbitration lost. Another master of the TWI bus.."
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bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0: Each data byte has been correctly received by..,1: In Read mode a data byte has not been.."
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bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0: FLEX_TWI_THR has been filled on time.,1: FLEX_TWI_THR has not been filled on time."
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bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0: FLEX_TWI_RHR has not been loaded while RXRDY was..,1: FLEX_TWI_RHR has been loaded while RXRDY was.."
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bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0: No general call has been detected.,1: A general call has been detected. After the.."
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bitfld.long 0x0 4. "SVACC,Slave Access" "0: TWI is not addressed. SVACC is automatically..,1: Indicates that the address decoding sequence has.."
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bitfld.long 0x0 3. "SVREAD,Slave Read" "0: Indicates that a write access is performed by a..,1: Indicates that a read access is performed by a.."
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0: Transmit FIFO is full and cannot accept more data,1: Transmit FIFO is not full; one or more data can.."
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0: Receive FIFO is empty; no data to read,1: At least one unread data is in the Receive FIFO"
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0: As soon as a Start is detected.,1: After a Stop or a Repeated Start + an address.."
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rgroup.long 0x620++0x3
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line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
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bitfld.long 0x0 26. "SR,Start Repeated" "0: No repeated start has been detected since last..,1: At least one repeated start has been detected.."
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bitfld.long 0x0 25. "SDA,SDA Line Value" "0: SDA line sampled value is '0'.,1: SDA line sampled value is '1'."
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bitfld.long 0x0 24. "SCL,SCL Line Value" "0: SCL line sampled value is '0'.,1: SCL line sampled value is '1.'"
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bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0: The Transmit FIFO is not locked.,1: The Transmit FIFO is locked."
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0: No SMBus Host Header Address received.,1: A SMBus Host Header Address was received."
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0: No SMBus Default Address received.,1: A SMBus Default Address was received."
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bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0: No SMBus PEC error occurred.,1: A SMBus PEC error occurred."
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bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0: No SMBus timeout occurred.,1: SMBus timeout occurred."
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bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag" "0: No SMBus slave drives the SMBALERT line.,1: At least one SMBus slave drives the SMBALERT line."
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0: No master code has been received.,1: A master code has been received."
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0: A slave access is being performing.,1: The Slave Access is finished. End Of Slave.."
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bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0: The clock is not stretched.,1: The clock is stretched. FLEX_TWI_THR /.."
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0: Arbitration won.,1: Arbitration lost. Another master of the TWI bus.."
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bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0: Each data byte has been correctly received by..,1: In Read mode a data byte has not been.."
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bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0: FLEX_TWI_THR has been filled on time.,1: FLEX_TWI_THR has not been filled on time."
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bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0: FLEX_TWI_RHR has not been loaded while RXRDY was..,1: FLEX_TWI_RHR has been loaded while RXRDY was.."
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bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0: No general call has been detected.,1: A general call has been detected. After the.."
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bitfld.long 0x0 4. "SVACC,Slave Access" "0: TWI is not addressed. SVACC is automatically..,1: Indicates that the address decoding sequence has.."
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bitfld.long 0x0 3. "SVREAD,Slave Read" "0: Indicates that a write access is performed by a..,1: Indicates that a read access is performed by a.."
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0: Transmit FIFO is full and cannot accept more data.,1: Transmit FIFO is not full; one or more data can.."
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0: Receive FIFO is empty; no data to read.,1: At least one unread data is in the Receive FIFO."
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0: As soon as a Start is detected.,1: After a Stop or a Repeated Start + an address.."
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wgroup.long 0x624++0x7
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line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
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bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
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bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Enable" "0,1"
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bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
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bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
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bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
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bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Enable" "0,1"
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bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
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bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
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bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
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bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
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bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
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bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
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bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
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bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
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bitfld.long 0x4 16. "MCACK,Master Code Acknowledge Interrupt Disable" "0,1"
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bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
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bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
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bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
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bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
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bitfld.long 0x4 11. "EOSACC,End Of Slave Access Interrupt Disable" "0,1"
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bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
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bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
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bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
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bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
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bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
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bitfld.long 0x4 4. "SVACC,Slave Access Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
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rgroup.long 0x62C++0x7
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line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
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bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
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bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Mask" "0,1"
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bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
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bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
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bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
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bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Mask" "0,1"
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bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
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bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Mask" "0,1"
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
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bitfld.long 0x4 11.--12. "ASTATE,Acknowledge State (Slave Sniffer Mode only)" "0: No Acknowledge or Nacknowledge detected after..,1: Acknowledge (A) detected after previously logged..,2: Nacknowledge (NA) detected after previously..,3: Not defined"
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bitfld.long 0x4 10. "PSTATE,Stop State (Slave Sniffer Mode only)" "0: No STOP (P) detected after previous logged data.,1: Stop detected (P) after previous logged data."
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bitfld.long 0x4 8.--9. "SSTATE,Start State (Slave Sniffer Mode only)" "0: No START detected with the logged data,1: START (S) detected with the logged data,2: Repeated START (Sr) detected with the logged data,3: Not defined"
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hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Master or Slave Receive Holding Data"
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rgroup.long 0x630++0x3
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line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Master or Slave Receive Holding Data 3"
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hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Master or Slave Receive Holding Data 2"
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hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Master or Slave Receive Holding Data 1"
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hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Master or Slave Receive Holding Data 0"
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wgroup.long 0x634++0x3
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line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Master or Slave Transmit Holding Data"
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wgroup.long 0x634++0x3
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line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Master or Slave Transmit Holding Data 3"
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hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Master or Slave Transmit Holding Data 2"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Master or Slave Transmit Holding Data 1"
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Master or Slave Transmit Holding Data 0"
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group.long 0x638++0x1B
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line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
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hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Master Clock Stretch Maximum Cycles"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Slave Clock Stretch Maximum Cycles"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
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line.long 0x4 "FLEX_TWI_HSR,TWI High Speed Register"
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hexmask.long.byte 0x4 0.--7. 1. "MCODE,TWI High Speed Master Code"
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line.long 0x8 "FLEX_TWI_ACR,TWI Alternative Command Register"
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bitfld.long 0x8 25. "NPEC,Next PEC Request (SMBus Mode only)" "0: The next transfer does not use a PEC byte.,1: The next transfer uses a PEC byte."
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bitfld.long 0x8 24. "NDIR,Next Transfer Direction" "0: Write direction.,1: Read direction."
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hexmask.long.byte 0x8 16.--23. 1. "NDATAL,Next Data Length"
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bitfld.long 0x8 9. "PEC,PEC Request (SMBus Mode only)" "0: The transfer does not use a PEC byte.,1: The transfer uses a PEC byte."
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bitfld.long 0x8 8. "DIR,Transfer Direction" "0: Write direction.,1: Read direction."
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hexmask.long.byte 0x8 0.--7. 1. "DATAL,Data Length"
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line.long 0xC "FLEX_TWI_FILTR,TWI Filter Register"
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bitfld.long 0xC 8.--10. "THRES,Digital Filter Threshold" "0: No filtering applied on TWI inputs.,?,?,?,?,?,?,?"
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bitfld.long 0xC 1. "PADFEN,PAD Filter Enable" "0: PAD analog filter is disabled.,1: PAD analog filter is enabled. (The analog filter.."
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bitfld.long 0xC 0. "FILT,RX Digital Filter" "0: No filtering applied on TWI inputs.,1: TWI input filtering is active. (Only in Standard.."
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line.long 0x10 "FLEX_TWI_HSCWGR,TWI High Speed Clock Waveform Generator Register"
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bitfld.long 0x10 16.--18. "HSCKDIV,High Speed Clock Divider" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x10 8.--15. 1. "HSCHDIV,High Speed Clock High Divider"
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hexmask.long.byte 0x10 0.--7. 1. "HSCLDIV,High Speed Clock Low Divider"
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line.long 0x14 "FLEX_TWI_SWMR,TWI Matching Register"
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hexmask.long.byte 0x14 24.--31. 1. "DATAM,Data Match"
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hexmask.long.byte 0x14 16.--22. 1. "SADR3,Slave Address 3"
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hexmask.long.byte 0x14 8.--14. 1. "SADR2,Slave Address 2"
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hexmask.long.byte 0x14 0.--6. 1. "SADR1,Slave Address 1"
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line.long 0x18 "FLEX_TWI_FMR,TWI FIFO Mode Register"
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hexmask.long.byte 0x18 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
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hexmask.long.byte 0x18 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
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bitfld.long 0x18 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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bitfld.long 0x18 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x654++0x3
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line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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rgroup.long 0x660++0x3
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line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
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bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0: No Receive FIFO pointer occurred,1: Receive FIFO pointer error occurred. Receiver.."
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bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0: No Transmit FIFO pointer occurred,1: Transmit FIFO pointer error occurred."
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bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0: Number of unread data in Receive FIFO is below..,1: Number of unread data in Receive FIFO has.."
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bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0: Receive FIFO is not empty.,1: Receive FIFO has been filled since the last read.."
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bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0: Receive FIFO is not empty.,1: Receive FIFO has been emptied since the last.."
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bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0: Number of data in Transmit FIFO is above..,1: Number of data in Transmit FIFO has reached.."
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bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0: Transmit FIFO is not full.,1: Transmit FIFO has been filled since the last.."
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bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0: Transmit FIFO is not empty.,1: Transmit FIFO has been emptied since the last.."
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wgroup.long 0x664++0x7
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line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
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rgroup.long 0x66C++0x3
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line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
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group.long 0x6E4++0x3
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line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
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rgroup.long 0x6E8++0x3
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line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
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bitfld.long 0x0 0. "WPVS,Write Protect Violation Status" "0: No Write Protection Violation has occurred since..,1: A Write Protection Violation has occurred since.."
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tree.end
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tree "FLEXCOM9"
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base ad:0xE281C000
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group.long 0x0++0x3
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line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
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bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected. USART/TWI..,3: All TWI related protocols are selected (TWI.."
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rgroup.long 0x10++0x3
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line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
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hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
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group.long 0x20++0x3
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line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
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wgroup.long 0x200++0x3
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line.long 0x0 "FLEX_US_CR,USART Control Register"
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bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0: No effect.,1: Disables the Transmit and Receive FIFOs."
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0: No effect.,1: Enables the Transmit and Receive FIFOs."
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bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0: No effect.,1: Restarts the comparison trigger to enable.."
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bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0: No effect.,1: Clears the Transmit FIFO Lock"
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bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0: No effect.,1: Empties the Receive FIFO."
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bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0: No effect.,1: Empties the Transmit FIFO."
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bitfld.long 0x0 21. "LINWKUP,Send LIN Wakeup Signal" "0: No effect:,1: Sends a wakeup signal on the LIN bus."
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bitfld.long 0x0 20. "LINABT,Abort LIN Transmission" "0: No effect.,1: Aborts the current LIN transmission."
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bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0: No effect.,1: Drives the RTS pin to 0 if FLEX_US_MR.USART_MODE.."
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bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0: No effect.,1: Drives the RTS pin to 1 if FLEX_US_MR.USART_MODE.."
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bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0: No effect,1: Immediately restarts timeout period."
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bitfld.long 0x0 14. "RSTNACK,Reset Non Acknowledge" "0: No effect,1: Resets FLEX_US_CSR.NACK."
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bitfld.long 0x0 13. "RSTIT,Reset Iterations" "0: No effect.,1: Resets FLEX_US_CSR.ITER. No effect if the.."
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bitfld.long 0x0 12. "SENDA,Send Address" "0: No effect.,1: In Multidrop mode only the next character.."
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bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0: No effect.,1: Starts waiting for a character before clocking.."
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bitfld.long 0x0 10. "STPBRK,Stop Break" "0: No effect.,1: Stops transmission of the break after a minimum.."
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bitfld.long 0x0 9. "STTBRK,Start Break" "0: No effect.,1: Starts transmission of a break after the.."
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bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0: No effect.,1: Resets the status bits PARE FRAME OVRE MANE.."
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bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0: No effect.,1: Disables the transmitter."
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bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0: No effect.,1: Enables the transmitter if TXDIS is 0."
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bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0: No effect.,1: Disables the receiver."
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bitfld.long 0x0 4. "RXEN,Receiver Enable" "0: No effect.,1: Enables the receiver if RXDIS is 0."
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bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0: No effect.,1: Resets the transmitter."
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bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0: No effect.,1: Resets the receiver."
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group.long 0x204++0x3
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line.long 0x0 "FLEX_US_MR,USART Mode Register"
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bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0: Start frame delimiter is COMMAND or DATA SYNC.,1: Start frame delimiter is one bit."
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bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0: The Manchester start bit is a 0 to 1 transition,1: The Manchester start bit is a 1 to 0 transition."
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bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0: Manchester encoder/decoder are disabled.,1: Manchester encoder/decoder are enabled."
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bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0: The USART does not filter the receive line.,1: The USART filters the receive line using a.."
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bitfld.long 0x0 24.--26. "MAX_ITERATION,Maximum Number of Automatic Iteration" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 23. "INVDATA,Inverted Data" "0: The data field transmitted on TXD line is the..,1: The data field transmitted on TXD line is.."
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bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0: User defined configuration of command or data..,1: The sync field is updated when a character is.."
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bitfld.long 0x0 21. "DSNACK,Disable Successive NACK" "0: NACK is sent on the ISO line as soon as a parity..,1: Successive parity errors are counted up to the.."
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bitfld.long 0x0 20. "INACK,Inhibit Non Acknowledge" "0: The NACK is generated.,1: The NACK is not generated."
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bitfld.long 0x0 19. "OVER,Oversampling Mode" "0: 16x Oversampling.,1: 8x Oversampling."
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bitfld.long 0x0 18. "CLKO,Clock Output Select" "0: The USART does not drive the SCK pin..,1: The USART drives the SCK pin if USCLKS does not.."
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bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0: CHRL defines character length.,1: 9-bit character length."
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bitfld.long 0x0 16. "MSBF,Bit Order" "0: Least significant bit is sent/received first.,1: Most significant bit is sent/received first."
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bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
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bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
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bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
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bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0: USART operates in Asynchronous mode (UART).,1: USART operates in Synchronous mode."
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bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
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bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
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hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
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wgroup.long 0x208++0x3
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line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Enable" "0,1"
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bitfld.long 0x0 10. "ITER,Max number of Repetitions Reached Interrupt Enable" "0,1"
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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wgroup.long 0x208++0x7
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line.long 0x0 "FLEX_US_IER_LIN_MODE,USART Interrupt Enable Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Enable" "0,1"
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Enable" "0,1"
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Enable" "0,1"
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Enable" "0,1"
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Enable" "0,1"
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Enable" "0,1"
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Enable" "0,1"
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Enable" "0,1"
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Enable" "0,1"
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Enable" "0,1"
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
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bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
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bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
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bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
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bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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wgroup.long 0x20C++0x3
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line.long 0x0 "FLEX_US_IDR_LIN_MODE,USART Interrupt Disable Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Disable" "0,1"
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Disable" "0,1"
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Disable" "0,1"
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Disable" "0,1"
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Disable" "0,1"
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Disable" "0,1"
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Disable" "0,1"
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Disable" "0,1"
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Disable" "0,1"
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Disable" "0,1"
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Disable" "0,1"
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Disable" "0,1"
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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rgroup.long 0x210++0x3
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line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Mask" "0,1"
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bitfld.long 0x0 10. "ITER,Max Number of Repetitions Reached Interrupt Mask" "0,1"
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
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rgroup.long 0x210++0x7
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line.long 0x0 "FLEX_US_IMR_LIN_MODE,USART Interrupt Mask Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Mask" "0,1"
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Mask" "0,1"
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Mask" "0,1"
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Mask" "0,1"
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Mask" "0,1"
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Mask" "0,1"
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Mask" "0,1"
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Mask" "0,1"
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "0,1"
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Mask" "0,1"
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
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bitfld.long 0x4 24. "MANE,Manchester Error" "0: No Manchester error has been detected since the..,1: At least one Manchester error has been detected.."
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bitfld.long 0x4 23. "CTS,Image of CTS Input" "0: CTS input is driven low.,1: CTS input is driven high."
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bitfld.long 0x4 22. "CMP,Comparison Status" "0: No received character matched the comparison..,1: A received character matched the comparison.."
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0: No input change has been detected on the CTS pin..,1: At least one input change has been detected on.."
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt" "0: Non acknowledge has not been detected since the..,1: At least one non acknowledge has been detected.."
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bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached" "0: Maximum number of repetitions has not been..,1: Maximum number of repetitions has been reached.."
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bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0: There are characters in either FLEX_US_THR or..,1: There are no characters in FLEX_US_THR nor in.."
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bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0: There has not been a timeout since the last..,1: There has been a timeout since the last Start.."
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bitfld.long 0x4 7. "PARE,Parity Error" "0: No parity error has been detected since the last..,1: At least one parity error has been detected.."
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bitfld.long 0x4 6. "FRAME,Framing Error" "0: No stop bit has been detected low since the last..,1: At least one stop bit has been detected low.."
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bitfld.long 0x4 5. "OVRE,Overrun Error" "0: No overrun error has occurred since the last..,1: At least one overrun error has occurred since.."
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bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0: No break received or end of break detected since..,1: Break received or end of break detected since.."
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bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0: Transmit FIFO is full and cannot accept more data,1: Transmit FIFO is not full; one or more data can.."
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bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0: Receive FIFO is empty; no data to read,1: At least one unread data is in the Receive FIFO"
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rgroup.long 0x214++0x7
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line.long 0x0 "FLEX_US_CSR_LIN_MODE,USART Channel Status Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error" "0: No LIN header timeout error has been detected..,1: A LIN header timeout error has been detected.."
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error" "0: No LIN synch tolerance error has been detected..,1: A LIN synch tolerance error has been detected.."
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error" "0: No LIN slave not responding error has been..,1: A LIN slave not responding error has been.."
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error" "0: No LIN checksum error has been detected since..,1: A LIN checksum error has been detected since the.."
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Error" "0: No LIN identifier parity error has been detected..,1: A LIN identifier parity error has been detected.."
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error" "0: No LIN inconsistent synch field error has been..,1: The USART is configured as a slave node and a.."
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newline
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bitfld.long 0x0 25. "LINBE,LIN Bit Error" "0: No bit error has been detected since the last..,1: A bit error has been detected since the last.."
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bitfld.long 0x0 23. "LINBLS,LIN Bus Line Status" "0: LIN bus line is set to 0.,1: LIN bus line is set to 1."
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newline
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed" "0: The USART is idle or a LIN transfer is ongoing.,1: A LIN transfer has been completed since the last.."
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newline
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received" "0: No LIN identifier has been received since the..,1: At least one LIN identifier has been received.."
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received" "0: No LIN break has received sent since the last..,1: At least one LIN break has been received since.."
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bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0: There are characters in either FLEX_US_THR or..,1: There are no characters in FLEX_US_THR nor in.."
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bitfld.long 0x0 8. "TIMEOUT,Receiver Timeout" "0: There has not been a timeout since the last..,1: There has been a timeout since the last start.."
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newline
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bitfld.long 0x0 7. "PARE,Parity Error" "0: No parity error has been detected since the last..,1: At least one parity error has been detected.."
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error" "0: No stop bit has been detected low since the last..,1: At least one stop bit has been detected low.."
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error" "0: No overrun error has occurred since the last..,1: At least one overrun error has occurred since.."
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bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0: A character in FLEX_US_THR is waiting to be..,1: There is no character in FLEX_US_THR."
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bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0: No complete character has been received since..,1: At least one complete character has been.."
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line.long 0x4 "FLEX_US_RHR,USART Receive Holding Register"
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bitfld.long 0x4 15. "RXSYNH,Received Sync" "0: Last character received is a data.,1: Last character received is a command."
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newline
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hexmask.long.word 0x4 0.--8. 1. "RXCHR,Received Character"
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rgroup.long 0x218++0x3
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line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Characters"
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hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Characters"
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hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Characters"
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hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Characters"
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wgroup.long 0x21C++0x3
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line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
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bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0: The next character sent is encoded as a data.,1: The next character sent is encoded as a command."
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hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
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wgroup.long 0x21C++0x3
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line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
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hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
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hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
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hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
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group.long 0x220++0xB
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line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
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bitfld.long 0x0 16.--18. "FP,Fractional Part" "0: Fractional divider is disabled.,?,?,?,?,?,?,?"
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hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
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line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
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hexmask.long.tbyte 0x4 0.--16. 1. "TO,Timeout Value"
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line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
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hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
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group.long 0x240++0x3
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line.long 0x0 "FLEX_US_FIDI,USART FI DI Ratio Register"
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hexmask.long.word 0x0 0.--15. 1. "FI_DI_RATIO,FI Over DI Ratio Value"
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rgroup.long 0x244++0x3
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line.long 0x0 "FLEX_US_NER,USART Number of Errors Register"
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hexmask.long.byte 0x0 0.--7. 1. "NB_ERRORS,Number of Errors"
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group.long 0x24C++0xF
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line.long 0x0 "FLEX_US_IF,USART IrDA Filter Register"
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hexmask.long.byte 0x0 0.--7. 1. "IRDA_FILTER,IrDA Filter"
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line.long 0x4 "FLEX_US_MAN,USART Manchester Configuration Register"
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bitfld.long 0x4 31. "RXIDLEV,Receiver Idle Value" "0: Receiver line idle value is 0.,1: Receiver line idle value is 1."
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bitfld.long 0x4 30. "DRIFT,Drift Compensation" "0: The USART cannot recover from an important clock..,1: The USART can recover from clock drift. The 16X.."
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bitfld.long 0x4 29. "ONE,Must Be Set to 1" "0,1"
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bitfld.long 0x4 28. "RX_MPOL,Receiver Manchester Polarity" "0: Logic zero is coded as a zero-to-one transition..,1: Logic zero is coded as a one-to-zero transition.."
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bitfld.long 0x4 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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hexmask.long.byte 0x4 16.--19. 1. "RX_PL,Receiver Preamble Length"
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bitfld.long 0x4 12. "TX_MPOL,Transmitter Manchester Polarity" "0: Logic zero is coded as a zero-to-one transition..,1: Logic zero is coded as a one-to-zero transition.."
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bitfld.long 0x4 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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hexmask.long.byte 0x4 0.--3. 1. "TX_PL,Transmitter Preamble Length"
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line.long 0x8 "FLEX_US_LINMR,USART LIN Mode Register"
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bitfld.long 0x8 17. "SYNCDIS,Synchronization Disable" "0: The synchronization procedure is performed in..,1: The synchronization procedure is not performed.."
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bitfld.long 0x8 16. "PDCM,DMAC Mode" "0: The LIN mode register FLEX_US_LINMR is not..,1: The LIN mode register FLEX_US_LINMR (excepting.."
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hexmask.long.byte 0x8 8.--15. 1. "DLC,Data Length Control"
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bitfld.long 0x8 7. "WKUPTYP,Wakeup Signal Type" "0: Setting the LINWKUP bit in the control register..,1: Setting the LINWKUP bit in the control register.."
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bitfld.long 0x8 6. "FSDIS,Frame Slot Mode Disable" "0: The Frame Slot mode is enabled.,1: The Frame Slot mode is disabled."
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bitfld.long 0x8 5. "DLM,Data Length Mode" "0: The response data length is defined by the DLC..,1: The response data length is defined by the bits.."
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bitfld.long 0x8 4. "CHKTYP,Checksum Type" "0: LIN 2.0 'enhanced' checksum,1: LIN 1.3 'classic' checksum"
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bitfld.long 0x8 3. "CHKDIS,Checksum Disable" "0: In master node configuration the checksum is..,1: Whatever the node configuration is the checksum.."
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bitfld.long 0x8 2. "PARDIS,Parity Disable" "0: In master node configuration the identifier..,1: Whatever the node configuration is the.."
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bitfld.long 0x8 0.--1. "NACT,LIN Node Action" "0: The USART transmits the response.,1: The USART receives the response.,2: The USART does not transmit and does not receive..,?"
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line.long 0xC "FLEX_US_LINIR,USART LIN Identifier Register"
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hexmask.long.byte 0xC 0.--7. 1. "IDCHR,Identifier Character"
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rgroup.long 0x25C++0x3
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line.long 0x0 "FLEX_US_LINBRR,USART LIN Baud Rate Register"
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bitfld.long 0x0 16.--18. "LINFP,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x0 0.--15. 1. "LINCD,Clock Divider after Synchronization"
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group.long 0x290++0x3
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line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
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hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
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bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0: The parity is not checked and a bad parity..,1: The parity is checked and a matching condition.."
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bitfld.long 0x0 12.--13. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start..,2: Comparison must be met to receive the current..,?"
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hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
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group.long 0x2A0++0x3
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line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
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hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
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hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
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bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0: RTS pin is not controlled by Receive FIFO..,1: RTS pin is controlled by Receive FIFO thresholds."
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bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x2A4++0x3
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line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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wgroup.long 0x2A8++0x7
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line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
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bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
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rgroup.long 0x2B0++0x7
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line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
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bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Number of unread data in Receive FIFO is above..,1: Number of unread data in Receive FIFO has.."
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bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0: The Transmit FIFO is not locked.,1: The Transmit FIFO is locked."
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bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0: No Receive FIFO pointer occurred,1: Receive FIFO pointer error occurred. Receiver.."
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bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0: No Transmit FIFO pointer occurred,1: Transmit FIFO pointer error occurred."
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bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Number of unread data in Receive FIFO is below..,1: Number of unread data in Receive FIFO has.."
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bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Receive FIFO is not empty.,1: Receive FIFO has been filled since the last.."
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bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Receive FIFO is not empty.,1: Receive FIFO has been emptied since the last.."
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bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Number of data in Transmit FIFO is above..,1: Number of data in Transmit FIFO has reached.."
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bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Transmit FIFO is not full.,1: Transmit FIFO has been filled since the last.."
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bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Transmit FIFO is not empty.,1: Transmit FIFO has been emptied since the last.."
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group.long 0x2E4++0x3
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line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection on configuration..,1: Enables the write protection on configuration.."
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rgroup.long 0x2E8++0x3
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line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
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hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
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newline
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
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wgroup.long 0x400++0x3
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line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
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bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0: No effect.,1: Disables the Transmit and Receive FIFOs"
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newline
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0: No effect.,1: Enables the Transmit and Receive FIFOs"
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bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0: No effect.,1: The current NPCS will be de-asserted after the.."
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newline
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bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0: No effect.,1: Empties the Receive FIFO."
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newline
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bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0: No effect.,1: Empties the Transmit FIFO."
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newline
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bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0: No effect.,1: Restarts the comparison trigger to enable.."
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newline
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bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0: No effect.,1: Reset the SPI. A software-triggered hardware.."
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newline
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bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0: No effect.,1: Disables the SPI."
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newline
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bitfld.long 0x0 0. "SPIEN,SPI Enable" "0: No effect.,1: Enables the SPI to transfer and receive data."
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group.long 0x404++0x3
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line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
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hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
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newline
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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newline
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bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
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newline
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bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0: Local loopback path disabled.,1: Local loopback path enabled."
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newline
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bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0: No Effect. In Master mode a transfer can be..,1: In Master mode a transfer can start only if.."
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newline
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bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0: Mode fault detection is enabled.,1: Mode fault detection is disabled."
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newline
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bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
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newline
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bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0: The chip selects are directly connected to a..,1: The four NPCS chip select lines are connected to.."
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newline
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bitfld.long 0x0 1. "PS,Peripheral Select" "0: Fixed Peripheral Select,1: Variable Peripheral Select"
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newline
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bitfld.long 0x0 0. "MSTR,Master/Slave Mode" "0: SPI is in Slave mode.,1: SPI is in Master mode."
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rgroup.long 0x408++0x3
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line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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newline
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hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
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rgroup.long 0x408++0x3
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line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
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hexmask.long.word 0x0 16.--31. 1. "RD1,Receive Data"
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newline
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hexmask.long.word 0x0 0.--15. 1. "RD0,Receive Data"
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rgroup.long 0x408++0x3
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line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
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hexmask.long.byte 0x0 24.--31. 1. "RD3,Receive Data"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "RD2,Receive Data"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "RD1,Receive Data"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "RD0,Receive Data"
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wgroup.long 0x40C++0x3
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line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
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bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0: No effect.,1: The current NPCS is de-asserted after the.."
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newline
|
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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newline
|
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hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
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wgroup.long 0x40C++0x3
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line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
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hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
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newline
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hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
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rgroup.long 0x410++0x3
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line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
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bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0: No Receive FIFO pointer occurred,1: Receive FIFO pointer error occurred. Receiver.."
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newline
|
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bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0: No Transmit FIFO pointer occurred,1: Transmit FIFO pointer error occurred."
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newline
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bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0: Number of unread data in Receive FIFO is below..,1: Number of unread data in Receive FIFO has.."
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newline
|
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bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0: Receive FIFO is not empty or RXFE flag has been..,1: Receive FIFO has been filled (changing states.."
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newline
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bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0: Receive FIFO is not empty or RXFE flag has been..,1: Receive FIFO has been emptied (changing states.."
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newline
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bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0: Number of data in Transmit FIFO is above..,1: Number of data in Transmit FIFO has reached.."
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newline
|
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bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0: Transmit FIFO is not full or TXFF flag has been..,1: Transmit FIFO has been filled since the last.."
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newline
|
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bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0: Transmit FIFO is not empty.,1: Transmit FIFO has been emptied since the last.."
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newline
|
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bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0: SPI is disabled.,1: SPI is enabled."
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newline
|
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bitfld.long 0x0 12. "SFERR,Slave Frame Error (cleared on read)" "0: There is no frame error detected for a slave..,1: In Slave mode the chip select raised while the.."
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newline
|
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bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0: No received character matched the comparison..,1: A received character matched the comparison.."
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newline
|
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bitfld.long 0x0 10. "UNDES,Underrun Error Status (Slave mode only) (cleared on read)" "0: No underrun has been detected since the last..,1: A transfer starts whereas no data has been.."
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0: As soon as data is written in FLEX_SPI_TDR.,1: FLEX_SPI_TDR and internal shift register are.."
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newline
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bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0: No rising edge detected on NSS pin since the..,1: A rising edge occurred on NSS pin since the last.."
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newline
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bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0: No overrun has been detected since the last read..,1: An overrun has occurred since the last read of.."
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newline
|
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bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0: No mode fault has been detected since the last..,1: A mode fault occurred since the last read of.."
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newline
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bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0: Transmit FIFO cannot accept more data.,1: Transmit FIFO can accept data; one or more data.."
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newline
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0: Receive FIFO is empty; no data to read,1: At least one unread data is in the Receive FIFO"
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wgroup.long 0x414++0x7
|
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line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
|
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bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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|
newline
|
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bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
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|
newline
|
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bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
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|
newline
|
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
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newline
|
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bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
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|
newline
|
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bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
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|
newline
|
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bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
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|
newline
|
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x41C++0x3
|
|
line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
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newline
|
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bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
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repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
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group.long ($2+0x430)++0x3
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line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register x"
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hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
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newline
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hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
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newline
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bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0: The Peripheral Chip Select Line rises as soon as..,1: The Peripheral Chip Select does not rise after.."
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newline
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bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0: The Peripheral Chip Select does not rise between..,1: The Peripheral Chip Select rises systematically.."
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newline
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bitfld.long 0x0 1. "NCPHA,Clock Phase" "0: Data are changed on the leading edge of SPCK and..,1: Data are captured on the leading edge of SPCK.."
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newline
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bitfld.long 0x0 0. "CPOL,Clock Polarity" "0: The inactive state value of SPCK is logic level..,1: The inactive state value of SPCK is logic level.."
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repeat.end
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group.long 0x440++0x3
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line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
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newline
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hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
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newline
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bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
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newline
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bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
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rgroup.long 0x444++0x3
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line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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newline
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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group.long 0x448++0x3
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line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
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hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
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newline
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hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
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group.long 0x4E4++0x3
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line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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newline
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
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newline
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
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newline
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
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rgroup.long 0x4E8++0x3
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line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
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hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
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newline
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0: No write protect violation has occurred since..,1: A write protect violation has occurred since the.."
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wgroup.long 0x600++0x3
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line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
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bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0: No effect.,1: Disable the Transmit and Receive FIFOs"
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newline
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bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0: No effect.,1: Enable the Transmit and Receive FIFOs"
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newline
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bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0: No effect.,1: Clear the TWI FSM lock."
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newline
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bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0: No effect.,1: Clear the Transmit Holding Register and set.."
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|
newline
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bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0: No effect.,1: Alternative Command mode disabled."
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|
newline
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bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0: No effect.,1: Alternative Command mode enabled."
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|
newline
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bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0: No effect.,1: If Master mode is enabled send a bus clear.."
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newline
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bitfld.long 0x0 14. "PECRQ,PEC Request" "0: No effect.,1: A PEC check or transmission is requested."
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|
newline
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bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0: No effect.,1: SMBus PEC (CRC) generation and check disabled."
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newline
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bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0: No effect.,1: SMBus PEC (CRC) generation and check enabled."
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|
newline
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bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0: No effect.,1: SMBus mode disabled."
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|
newline
|
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bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0: No effect.,1: If SMBDIS = 0 SMBus mode enabled."
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|
newline
|
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bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0: No effect.,1: High-speed mode disabled."
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|
newline
|
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bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0: No effect.,1: High-speed mode enabled."
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|
newline
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bitfld.long 0x0 7. "SWRST,Software Reset" "0: No effect.,1: Equivalent to a system reset."
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|
newline
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bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0: No effect.,1: If Master mode is enabled a SMBus Quick Command.."
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newline
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bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0: No effect.,1: The Slave mode is disabled. The shifter and.."
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|
newline
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bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0: No effect.,1: Enables the Slave mode (SVDIS must be written to.."
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|
newline
|
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bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0: No effect.,1: The Master mode is disabled all pending data is.."
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newline
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bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0: No effect.,1: Enables the Master mode (MSDIS must be written.."
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|
newline
|
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bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0: No effect.,1: STOP condition is sent just after completing the.."
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|
newline
|
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bitfld.long 0x0 0. "START,Send a START Condition" "0: No effect.,1: A frame beginning with a START bit is.."
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|
wgroup.long 0x600++0x3
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line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0: No effect.,1: Disable the Transmit and Receive FIFOs."
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|
newline
|
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bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0: No effect.,1: Enable the Transmit and Receive FIFOs."
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|
newline
|
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bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0: No effect.,1: Clears the Transmit FIFO Lock."
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|
newline
|
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bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0: No effect.,1: Empties the Receive FIFO."
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|
newline
|
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bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0: No effect.,1: Empties the Transmit FIFO."
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|
newline
|
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bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0: No effect.,1: Alternative Command mode disabled."
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|
newline
|
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bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0: No effect.,1: Alternative Command mode enabled."
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|
newline
|
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bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0: No effect.,1: If Master mode is enabled send a bus clear.."
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|
newline
|
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bitfld.long 0x0 14. "PECRQ,PEC Request" "0: No effect.,1: A PEC check or transmission is requested."
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|
newline
|
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bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0: No effect.,1: SMBus PEC (CRC) generation and check disabled."
|
|
newline
|
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bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0: No effect.,1: SMBus PEC (CRC) generation and check enabled."
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|
newline
|
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bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0: No effect.,1: SMBus mode disabled."
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|
newline
|
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bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0: No effect.,1: If SMBDIS = 0 SMBus mode enabled."
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newline
|
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bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0: No effect.,1: High-speed mode disabled."
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|
newline
|
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bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0: No effect.,1: High-speed mode enabled."
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|
newline
|
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bitfld.long 0x0 7. "SWRST,Software Reset" "0: No effect.,1: Equivalent to a system reset."
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|
newline
|
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bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0: No effect.,1: If Master mode is enabled a SMBus Quick Command.."
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|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0: No effect.,1: The Slave mode is disabled. The shifter and.."
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|
newline
|
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bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0: No effect.,1: Enables the Slave mode (SVDIS must be written to.."
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|
newline
|
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bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0: No effect.,1: The Master mode is disabled all pending data is.."
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|
newline
|
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bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0: No effect.,1: Enables the Master mode (MSDIS must be written.."
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|
newline
|
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bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0: No effect.,1: STOP condition is sent just after completing the.."
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|
newline
|
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bitfld.long 0x0 0. "START,Send a START Condition" "0: No effect.,1: A frame beginning with a START bit is.."
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|
group.long 0x604++0xF
|
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line.long 0x0 "FLEX_TWI_MMR,TWI Master Mode Register"
|
|
bitfld.long 0x0 24. "NOAP,No Auto-Stop On NACK Error" "0: A stop condition is sent automatically upon..,1: No automatic action is performed upon.."
|
|
newline
|
|
hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
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|
newline
|
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bitfld.long 0x0 13.--14. "SCLRBL,SCL Rise Boost Level" "0,1,2,3"
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|
newline
|
|
bitfld.long 0x0 12. "MREAD,Master Read Direction" "0: Master write direction.,1: Master read direction."
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|
newline
|
|
bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
|
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line.long 0x4 "FLEX_TWI_SMR,TWI Slave Mode Register"
|
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bitfld.long 0x4 31. "DATAMEN,Data Matching Enable" "0: Data matching on first received data is disabled.,1: Data matching on first received data is enabled."
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|
newline
|
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bitfld.long 0x4 30. "SADR3EN,Slave Address 3 Enable" "0: Slave address 3 matching is disabled.,1: Slave address 3 matching is enabled."
|
|
newline
|
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bitfld.long 0x4 29. "SADR2EN,Slave Address 2 Enable" "0: Slave address 2 matching is disabled.,1: Slave address 2 matching is enabled."
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|
newline
|
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bitfld.long 0x4 28. "SADR1EN,Slave Address 1 Enable" "0: Slave address 1 matching is disabled.,1: Slave address 1 matching is enabled."
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|
newline
|
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hexmask.long.byte 0x4 16.--22. 1. "SADR,Slave Address"
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|
newline
|
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hexmask.long.byte 0x4 8.--14. 1. "MASK,Slave Address Mask"
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|
newline
|
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bitfld.long 0x4 7. "SNIFF,Slave Sniffer Mode" "0: Slave Sniffer mode is disabled.,1: Slave Sniffer mode is enabled."
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|
newline
|
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bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0: No effect.,1: Clock stretching disabled in Slave mode OVRE and.."
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|
newline
|
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bitfld.long 0x4 5. "BSEL,TWI Bus Selection" "0: TWI analyzes the TWCK and TWD pins from its TWI..,1: TWI analyzes the TWCK pins TWD from consecutive.."
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|
newline
|
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bitfld.long 0x4 4. "SADAT,Slave Address Treated as Data" "0: Slave address is handled normally (will not trig..,1: Slave address is handled as data field RXRDY.."
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newline
|
|
bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0: Acknowledge of the SMBus Host Header disabled.,1: Acknowledge of the SMBus Host Header enabled."
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|
newline
|
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bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0: Acknowledge of the SMBus Default Address disabled.,1: Acknowledge of the SMBus Default Address enabled."
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|
newline
|
|
bitfld.long 0x4 0. "NACKEN,Slave Receiver Data Phase NACK Enable" "0: Normal value to be returned in the ACK cycle of..,1: NACK value to be returned in the ACK cycle of.."
|
|
line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
|
|
line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
hexmask.long.byte 0xC 24.--29. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
|
|
newline
|
|
bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0: No repeated start has been detected since last..,1: At least one repeated start has been detected.."
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|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0: SDA line sampled value is '0'.,1: SDA line sampled value is '1'."
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|
newline
|
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bitfld.long 0x0 24. "SCL,SCL Line Value" "0: SCL line sampled value is '0'.,1: SCL line sampled value is '1.'"
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|
newline
|
|
bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0: The TWI is not locked.,1: The TWI is locked due to frame errors (see.."
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0: No SMBus Host Header Address received.,1: A SMBus Host Header Address was received."
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0: No SMBus Default Address received.,1: A SMBus Default Address was received."
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0: No SMBus PEC error occurred.,1: A SMBus PEC error occurred."
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0: No SMBus timeout occurred.,1: SMBus timeout occurred."
|
|
newline
|
|
bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag" "0: No SMBus slave drives the SMBALERT line.,1: At least one SMBus slave drives the SMBALERT line."
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0: No master code has been received.,1: A master code has been received."
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newline
|
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0: A slave access is being performing.,1: The Slave Access is finished. End Of Slave.."
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newline
|
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bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0: The clock is not stretched.,1: The clock is stretched. FLEX_TWI_THR /.."
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0: Arbitration won.,1: Arbitration lost. Another master of the TWI bus.."
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0: Each data byte has been correctly received by..,1: In Read mode a data byte has not been.."
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|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0: FLEX_TWI_THR has been filled on time.,1: FLEX_TWI_THR has not been filled on time."
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|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0: FLEX_TWI_RHR has not been loaded while RXRDY was..,1: FLEX_TWI_RHR has been loaded while RXRDY was.."
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|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0: No general call has been detected.,1: A general call has been detected. After the.."
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|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0: TWI is not addressed. SVACC is automatically..,1: Indicates that the address decoding sequence has.."
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0: Indicates that a write access is performed by a..,1: Indicates that a read access is performed by a.."
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0: Transmit FIFO is full and cannot accept more data,1: Transmit FIFO is not full; one or more data can.."
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0: Receive FIFO is empty; no data to read,1: At least one unread data is in the Receive FIFO"
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|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0: As soon as a Start is detected.,1: After a Stop or a Repeated Start + an address.."
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0: No repeated start has been detected since last..,1: At least one repeated start has been detected.."
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0: SDA line sampled value is '0'.,1: SDA line sampled value is '1'."
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0: SCL line sampled value is '0'.,1: SCL line sampled value is '1.'"
|
|
newline
|
|
bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0: The Transmit FIFO is not locked.,1: The Transmit FIFO is locked."
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|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0: No SMBus Host Header Address received.,1: A SMBus Host Header Address was received."
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0: No SMBus Default Address received.,1: A SMBus Default Address was received."
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0: No SMBus PEC error occurred.,1: A SMBus PEC error occurred."
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0: No SMBus timeout occurred.,1: SMBus timeout occurred."
|
|
newline
|
|
bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag" "0: No SMBus slave drives the SMBALERT line.,1: At least one SMBus slave drives the SMBALERT line."
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0: No master code has been received.,1: A master code has been received."
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0: A slave access is being performing.,1: The Slave Access is finished. End Of Slave.."
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0: The clock is not stretched.,1: The clock is stretched. FLEX_TWI_THR /.."
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0: Arbitration won.,1: Arbitration lost. Another master of the TWI bus.."
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0: Each data byte has been correctly received by..,1: In Read mode a data byte has not been.."
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0: FLEX_TWI_THR has been filled on time.,1: FLEX_TWI_THR has not been filled on time."
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0: FLEX_TWI_RHR has not been loaded while RXRDY was..,1: FLEX_TWI_RHR has been loaded while RXRDY was.."
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|
newline
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bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0: No general call has been detected.,1: A general call has been detected. After the.."
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bitfld.long 0x0 4. "SVACC,Slave Access" "0: TWI is not addressed. SVACC is automatically..,1: Indicates that the address decoding sequence has.."
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bitfld.long 0x0 3. "SVREAD,Slave Read" "0: Indicates that a write access is performed by a..,1: Indicates that a read access is performed by a.."
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0: Transmit FIFO is full and cannot accept more data.,1: Transmit FIFO is not full; one or more data can.."
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0: Receive FIFO is empty; no data to read.,1: At least one unread data is in the Receive FIFO."
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0: As soon as a Start is detected.,1: After a Stop or a Repeated Start + an address.."
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wgroup.long 0x624++0x7
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line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
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bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
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bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Enable" "0,1"
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bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
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bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
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bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
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bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Enable" "0,1"
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bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
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bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
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bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
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bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
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bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
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bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
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bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
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bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
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bitfld.long 0x4 16. "MCACK,Master Code Acknowledge Interrupt Disable" "0,1"
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bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
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bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
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bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
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bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
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bitfld.long 0x4 11. "EOSACC,End Of Slave Access Interrupt Disable" "0,1"
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bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
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bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
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bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
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bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
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bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
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bitfld.long 0x4 4. "SVACC,Slave Access Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
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rgroup.long 0x62C++0x7
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line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
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bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
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bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Mask" "0,1"
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bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
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bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
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bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
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bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Mask" "0,1"
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bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
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bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
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bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
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bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Mask" "0,1"
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
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bitfld.long 0x4 11.--12. "ASTATE,Acknowledge State (Slave Sniffer Mode only)" "0: No Acknowledge or Nacknowledge detected after..,1: Acknowledge (A) detected after previously logged..,2: Nacknowledge (NA) detected after previously..,3: Not defined"
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bitfld.long 0x4 10. "PSTATE,Stop State (Slave Sniffer Mode only)" "0: No STOP (P) detected after previous logged data.,1: Stop detected (P) after previous logged data."
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bitfld.long 0x4 8.--9. "SSTATE,Start State (Slave Sniffer Mode only)" "0: No START detected with the logged data,1: START (S) detected with the logged data,2: Repeated START (Sr) detected with the logged data,3: Not defined"
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hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Master or Slave Receive Holding Data"
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rgroup.long 0x630++0x3
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line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Master or Slave Receive Holding Data 3"
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hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Master or Slave Receive Holding Data 2"
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hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Master or Slave Receive Holding Data 1"
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hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Master or Slave Receive Holding Data 0"
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wgroup.long 0x634++0x3
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line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Master or Slave Transmit Holding Data"
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wgroup.long 0x634++0x3
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line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Master or Slave Transmit Holding Data 3"
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hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Master or Slave Transmit Holding Data 2"
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hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Master or Slave Transmit Holding Data 1"
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Master or Slave Transmit Holding Data 0"
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group.long 0x638++0x1B
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line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
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hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
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hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Master Clock Stretch Maximum Cycles"
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hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Slave Clock Stretch Maximum Cycles"
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hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
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line.long 0x4 "FLEX_TWI_HSR,TWI High Speed Register"
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hexmask.long.byte 0x4 0.--7. 1. "MCODE,TWI High Speed Master Code"
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line.long 0x8 "FLEX_TWI_ACR,TWI Alternative Command Register"
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bitfld.long 0x8 25. "NPEC,Next PEC Request (SMBus Mode only)" "0: The next transfer does not use a PEC byte.,1: The next transfer uses a PEC byte."
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bitfld.long 0x8 24. "NDIR,Next Transfer Direction" "0: Write direction.,1: Read direction."
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hexmask.long.byte 0x8 16.--23. 1. "NDATAL,Next Data Length"
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bitfld.long 0x8 9. "PEC,PEC Request (SMBus Mode only)" "0: The transfer does not use a PEC byte.,1: The transfer uses a PEC byte."
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bitfld.long 0x8 8. "DIR,Transfer Direction" "0: Write direction.,1: Read direction."
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hexmask.long.byte 0x8 0.--7. 1. "DATAL,Data Length"
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line.long 0xC "FLEX_TWI_FILTR,TWI Filter Register"
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bitfld.long 0xC 8.--10. "THRES,Digital Filter Threshold" "0: No filtering applied on TWI inputs.,?,?,?,?,?,?,?"
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bitfld.long 0xC 1. "PADFEN,PAD Filter Enable" "0: PAD analog filter is disabled.,1: PAD analog filter is enabled. (The analog filter.."
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bitfld.long 0xC 0. "FILT,RX Digital Filter" "0: No filtering applied on TWI inputs.,1: TWI input filtering is active. (Only in Standard.."
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line.long 0x10 "FLEX_TWI_HSCWGR,TWI High Speed Clock Waveform Generator Register"
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bitfld.long 0x10 16.--18. "HSCKDIV,High Speed Clock Divider" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x10 8.--15. 1. "HSCHDIV,High Speed Clock High Divider"
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hexmask.long.byte 0x10 0.--7. 1. "HSCLDIV,High Speed Clock Low Divider"
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line.long 0x14 "FLEX_TWI_SWMR,TWI Matching Register"
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hexmask.long.byte 0x14 24.--31. 1. "DATAM,Data Match"
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hexmask.long.byte 0x14 16.--22. 1. "SADR3,Slave Address 3"
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hexmask.long.byte 0x14 8.--14. 1. "SADR2,Slave Address 2"
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hexmask.long.byte 0x14 0.--6. 1. "SADR1,Slave Address 1"
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line.long 0x18 "FLEX_TWI_FMR,TWI FIFO Mode Register"
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hexmask.long.byte 0x18 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
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hexmask.long.byte 0x18 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
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bitfld.long 0x18 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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bitfld.long 0x18 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x654++0x3
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line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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rgroup.long 0x660++0x3
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line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
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bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0: No Receive FIFO pointer occurred,1: Receive FIFO pointer error occurred. Receiver.."
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bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0: No Transmit FIFO pointer occurred,1: Transmit FIFO pointer error occurred."
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bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0: Number of unread data in Receive FIFO is below..,1: Number of unread data in Receive FIFO has.."
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bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0: Receive FIFO is not empty.,1: Receive FIFO has been filled since the last read.."
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bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0: Receive FIFO is not empty.,1: Receive FIFO has been emptied since the last.."
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bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0: Number of data in Transmit FIFO is above..,1: Number of data in Transmit FIFO has reached.."
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bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0: Transmit FIFO is not full.,1: Transmit FIFO has been filled since the last.."
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bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0: Transmit FIFO is not empty.,1: Transmit FIFO has been emptied since the last.."
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wgroup.long 0x664++0x7
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line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
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|
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bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
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|
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
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|
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
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rgroup.long 0x66C++0x3
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line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
|
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
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|
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
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|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
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|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
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|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
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|
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
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group.long 0x6E4++0x3
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line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
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rgroup.long 0x6E8++0x3
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line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
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bitfld.long 0x0 0. "WPVS,Write Protect Violation Status" "0: No Write Protection Violation has occurred since..,1: A Write Protection Violation has occurred since.."
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tree.end
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tree "FLEXCOM10"
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base ad:0xE2820000
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group.long 0x0++0x3
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line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
|
|
bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected. USART/TWI..,3: All TWI related protocols are selected (TWI.."
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rgroup.long 0x10++0x3
|
|
line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
|
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hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
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group.long 0x20++0x3
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line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
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wgroup.long 0x200++0x3
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line.long 0x0 "FLEX_US_CR,USART Control Register"
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bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0: No effect.,1: Disables the Transmit and Receive FIFOs."
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0: No effect.,1: Enables the Transmit and Receive FIFOs."
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bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0: No effect.,1: Restarts the comparison trigger to enable.."
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bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0: No effect.,1: Clears the Transmit FIFO Lock"
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bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0: No effect.,1: Empties the Receive FIFO."
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bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0: No effect.,1: Empties the Transmit FIFO."
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bitfld.long 0x0 21. "LINWKUP,Send LIN Wakeup Signal" "0: No effect:,1: Sends a wakeup signal on the LIN bus."
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bitfld.long 0x0 20. "LINABT,Abort LIN Transmission" "0: No effect.,1: Aborts the current LIN transmission."
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bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0: No effect.,1: Drives the RTS pin to 0 if FLEX_US_MR.USART_MODE.."
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bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0: No effect.,1: Drives the RTS pin to 1 if FLEX_US_MR.USART_MODE.."
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bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0: No effect,1: Immediately restarts timeout period."
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bitfld.long 0x0 14. "RSTNACK,Reset Non Acknowledge" "0: No effect,1: Resets FLEX_US_CSR.NACK."
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bitfld.long 0x0 13. "RSTIT,Reset Iterations" "0: No effect.,1: Resets FLEX_US_CSR.ITER. No effect if the.."
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bitfld.long 0x0 12. "SENDA,Send Address" "0: No effect.,1: In Multidrop mode only the next character.."
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bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0: No effect.,1: Starts waiting for a character before clocking.."
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bitfld.long 0x0 10. "STPBRK,Stop Break" "0: No effect.,1: Stops transmission of the break after a minimum.."
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bitfld.long 0x0 9. "STTBRK,Start Break" "0: No effect.,1: Starts transmission of a break after the.."
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bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0: No effect.,1: Resets the status bits PARE FRAME OVRE MANE.."
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bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0: No effect.,1: Disables the transmitter."
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bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0: No effect.,1: Enables the transmitter if TXDIS is 0."
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bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0: No effect.,1: Disables the receiver."
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bitfld.long 0x0 4. "RXEN,Receiver Enable" "0: No effect.,1: Enables the receiver if RXDIS is 0."
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bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0: No effect.,1: Resets the transmitter."
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bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0: No effect.,1: Resets the receiver."
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group.long 0x204++0x3
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line.long 0x0 "FLEX_US_MR,USART Mode Register"
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bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0: Start frame delimiter is COMMAND or DATA SYNC.,1: Start frame delimiter is one bit."
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bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0: The Manchester start bit is a 0 to 1 transition,1: The Manchester start bit is a 1 to 0 transition."
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bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0: Manchester encoder/decoder are disabled.,1: Manchester encoder/decoder are enabled."
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bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0: The USART does not filter the receive line.,1: The USART filters the receive line using a.."
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bitfld.long 0x0 24.--26. "MAX_ITERATION,Maximum Number of Automatic Iteration" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 23. "INVDATA,Inverted Data" "0: The data field transmitted on TXD line is the..,1: The data field transmitted on TXD line is.."
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bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0: User defined configuration of command or data..,1: The sync field is updated when a character is.."
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bitfld.long 0x0 21. "DSNACK,Disable Successive NACK" "0: NACK is sent on the ISO line as soon as a parity..,1: Successive parity errors are counted up to the.."
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bitfld.long 0x0 20. "INACK,Inhibit Non Acknowledge" "0: The NACK is generated.,1: The NACK is not generated."
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bitfld.long 0x0 19. "OVER,Oversampling Mode" "0: 16x Oversampling.,1: 8x Oversampling."
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bitfld.long 0x0 18. "CLKO,Clock Output Select" "0: The USART does not drive the SCK pin..,1: The USART drives the SCK pin if USCLKS does not.."
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bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0: CHRL defines character length.,1: 9-bit character length."
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bitfld.long 0x0 16. "MSBF,Bit Order" "0: Least significant bit is sent/received first.,1: Most significant bit is sent/received first."
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bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
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bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
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bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
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bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0: USART operates in Asynchronous mode (UART).,1: USART operates in Synchronous mode."
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bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
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bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
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hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
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wgroup.long 0x208++0x3
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line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Enable" "0,1"
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bitfld.long 0x0 10. "ITER,Max number of Repetitions Reached Interrupt Enable" "0,1"
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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wgroup.long 0x208++0x7
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line.long 0x0 "FLEX_US_IER_LIN_MODE,USART Interrupt Enable Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Enable" "0,1"
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Enable" "0,1"
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Enable" "0,1"
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Enable" "0,1"
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Enable" "0,1"
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Enable" "0,1"
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Enable" "0,1"
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Enable" "0,1"
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Enable" "0,1"
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Enable" "0,1"
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
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bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt Disable" "0,1"
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bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached Interrupt Disable" "0,1"
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bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
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bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
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bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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wgroup.long 0x20C++0x3
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line.long 0x0 "FLEX_US_IDR_LIN_MODE,USART Interrupt Disable Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Disable" "0,1"
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Disable" "0,1"
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Disable" "0,1"
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Disable" "0,1"
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Disable" "0,1"
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Disable" "0,1"
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Disable" "0,1"
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Disable" "0,1"
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Disable" "0,1"
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Disable" "0,1"
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Disable" "0,1"
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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rgroup.long 0x210++0x3
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line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Mask" "0,1"
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bitfld.long 0x0 10. "ITER,Max Number of Repetitions Reached Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
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rgroup.long 0x210++0x7
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line.long 0x0 "FLEX_US_IMR_LIN_MODE,USART Interrupt Mask Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Mask" "0,1"
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
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bitfld.long 0x4 24. "MANE,Manchester Error" "0: No Manchester error has been detected since the..,1: At least one Manchester error has been detected.."
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bitfld.long 0x4 23. "CTS,Image of CTS Input" "0: CTS input is driven low.,1: CTS input is driven high."
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newline
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bitfld.long 0x4 22. "CMP,Comparison Status" "0: No received character matched the comparison..,1: A received character matched the comparison.."
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0: No input change has been detected on the CTS pin..,1: At least one input change has been detected on.."
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newline
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt" "0: Non acknowledge has not been detected since the..,1: At least one non acknowledge has been detected.."
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newline
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bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached" "0: Maximum number of repetitions has not been..,1: Maximum number of repetitions has been reached.."
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bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0: There are characters in either FLEX_US_THR or..,1: There are no characters in FLEX_US_THR nor in.."
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bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0: There has not been a timeout since the last..,1: There has been a timeout since the last Start.."
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newline
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bitfld.long 0x4 7. "PARE,Parity Error" "0: No parity error has been detected since the last..,1: At least one parity error has been detected.."
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newline
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bitfld.long 0x4 6. "FRAME,Framing Error" "0: No stop bit has been detected low since the last..,1: At least one stop bit has been detected low.."
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newline
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bitfld.long 0x4 5. "OVRE,Overrun Error" "0: No overrun error has occurred since the last..,1: At least one overrun error has occurred since.."
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bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0: No break received or end of break detected since..,1: Break received or end of break detected since.."
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bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0: Transmit FIFO is full and cannot accept more data,1: Transmit FIFO is not full; one or more data can.."
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bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0: Receive FIFO is empty; no data to read,1: At least one unread data is in the Receive FIFO"
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rgroup.long 0x214++0x7
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line.long 0x0 "FLEX_US_CSR_LIN_MODE,USART Channel Status Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error" "0: No LIN header timeout error has been detected..,1: A LIN header timeout error has been detected.."
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error" "0: No LIN synch tolerance error has been detected..,1: A LIN synch tolerance error has been detected.."
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error" "0: No LIN slave not responding error has been..,1: A LIN slave not responding error has been.."
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error" "0: No LIN checksum error has been detected since..,1: A LIN checksum error has been detected since the.."
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Error" "0: No LIN identifier parity error has been detected..,1: A LIN identifier parity error has been detected.."
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error" "0: No LIN inconsistent synch field error has been..,1: The USART is configured as a slave node and a.."
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bitfld.long 0x0 25. "LINBE,LIN Bit Error" "0: No bit error has been detected since the last..,1: A bit error has been detected since the last.."
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bitfld.long 0x0 23. "LINBLS,LIN Bus Line Status" "0: LIN bus line is set to 0.,1: LIN bus line is set to 1."
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed" "0: The USART is idle or a LIN transfer is ongoing.,1: A LIN transfer has been completed since the last.."
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received" "0: No LIN identifier has been received since the..,1: At least one LIN identifier has been received.."
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received" "0: No LIN break has received sent since the last..,1: At least one LIN break has been received since.."
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bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0: There are characters in either FLEX_US_THR or..,1: There are no characters in FLEX_US_THR nor in.."
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bitfld.long 0x0 8. "TIMEOUT,Receiver Timeout" "0: There has not been a timeout since the last..,1: There has been a timeout since the last start.."
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bitfld.long 0x0 7. "PARE,Parity Error" "0: No parity error has been detected since the last..,1: At least one parity error has been detected.."
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bitfld.long 0x0 6. "FRAME,Framing Error" "0: No stop bit has been detected low since the last..,1: At least one stop bit has been detected low.."
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bitfld.long 0x0 5. "OVRE,Overrun Error" "0: No overrun error has occurred since the last..,1: At least one overrun error has occurred since.."
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bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0: A character in FLEX_US_THR is waiting to be..,1: There is no character in FLEX_US_THR."
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bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0: No complete character has been received since..,1: At least one complete character has been.."
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line.long 0x4 "FLEX_US_RHR,USART Receive Holding Register"
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bitfld.long 0x4 15. "RXSYNH,Received Sync" "0: Last character received is a data.,1: Last character received is a command."
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hexmask.long.word 0x4 0.--8. 1. "RXCHR,Received Character"
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rgroup.long 0x218++0x3
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line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Characters"
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hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Characters"
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hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Characters"
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hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Characters"
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wgroup.long 0x21C++0x3
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line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
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bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0: The next character sent is encoded as a data.,1: The next character sent is encoded as a command."
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hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
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wgroup.long 0x21C++0x3
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line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
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hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
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hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
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hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
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group.long 0x220++0xB
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line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
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bitfld.long 0x0 16.--18. "FP,Fractional Part" "0: Fractional divider is disabled.,?,?,?,?,?,?,?"
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hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
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line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
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hexmask.long.tbyte 0x4 0.--16. 1. "TO,Timeout Value"
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line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
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hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
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group.long 0x240++0x3
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line.long 0x0 "FLEX_US_FIDI,USART FI DI Ratio Register"
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hexmask.long.word 0x0 0.--15. 1. "FI_DI_RATIO,FI Over DI Ratio Value"
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rgroup.long 0x244++0x3
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line.long 0x0 "FLEX_US_NER,USART Number of Errors Register"
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hexmask.long.byte 0x0 0.--7. 1. "NB_ERRORS,Number of Errors"
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group.long 0x24C++0xF
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line.long 0x0 "FLEX_US_IF,USART IrDA Filter Register"
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hexmask.long.byte 0x0 0.--7. 1. "IRDA_FILTER,IrDA Filter"
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line.long 0x4 "FLEX_US_MAN,USART Manchester Configuration Register"
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bitfld.long 0x4 31. "RXIDLEV,Receiver Idle Value" "0: Receiver line idle value is 0.,1: Receiver line idle value is 1."
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bitfld.long 0x4 30. "DRIFT,Drift Compensation" "0: The USART cannot recover from an important clock..,1: The USART can recover from clock drift. The 16X.."
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bitfld.long 0x4 29. "ONE,Must Be Set to 1" "0,1"
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bitfld.long 0x4 28. "RX_MPOL,Receiver Manchester Polarity" "0: Logic zero is coded as a zero-to-one transition..,1: Logic zero is coded as a one-to-zero transition.."
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bitfld.long 0x4 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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hexmask.long.byte 0x4 16.--19. 1. "RX_PL,Receiver Preamble Length"
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bitfld.long 0x4 12. "TX_MPOL,Transmitter Manchester Polarity" "0: Logic zero is coded as a zero-to-one transition..,1: Logic zero is coded as a one-to-zero transition.."
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bitfld.long 0x4 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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hexmask.long.byte 0x4 0.--3. 1. "TX_PL,Transmitter Preamble Length"
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line.long 0x8 "FLEX_US_LINMR,USART LIN Mode Register"
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bitfld.long 0x8 17. "SYNCDIS,Synchronization Disable" "0: The synchronization procedure is performed in..,1: The synchronization procedure is not performed.."
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bitfld.long 0x8 16. "PDCM,DMAC Mode" "0: The LIN mode register FLEX_US_LINMR is not..,1: The LIN mode register FLEX_US_LINMR (excepting.."
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hexmask.long.byte 0x8 8.--15. 1. "DLC,Data Length Control"
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bitfld.long 0x8 7. "WKUPTYP,Wakeup Signal Type" "0: Setting the LINWKUP bit in the control register..,1: Setting the LINWKUP bit in the control register.."
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bitfld.long 0x8 6. "FSDIS,Frame Slot Mode Disable" "0: The Frame Slot mode is enabled.,1: The Frame Slot mode is disabled."
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bitfld.long 0x8 5. "DLM,Data Length Mode" "0: The response data length is defined by the DLC..,1: The response data length is defined by the bits.."
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bitfld.long 0x8 4. "CHKTYP,Checksum Type" "0: LIN 2.0 'enhanced' checksum,1: LIN 1.3 'classic' checksum"
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bitfld.long 0x8 3. "CHKDIS,Checksum Disable" "0: In master node configuration the checksum is..,1: Whatever the node configuration is the checksum.."
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bitfld.long 0x8 2. "PARDIS,Parity Disable" "0: In master node configuration the identifier..,1: Whatever the node configuration is the.."
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bitfld.long 0x8 0.--1. "NACT,LIN Node Action" "0: The USART transmits the response.,1: The USART receives the response.,2: The USART does not transmit and does not receive..,?"
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line.long 0xC "FLEX_US_LINIR,USART LIN Identifier Register"
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hexmask.long.byte 0xC 0.--7. 1. "IDCHR,Identifier Character"
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rgroup.long 0x25C++0x3
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line.long 0x0 "FLEX_US_LINBRR,USART LIN Baud Rate Register"
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bitfld.long 0x0 16.--18. "LINFP,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x0 0.--15. 1. "LINCD,Clock Divider after Synchronization"
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group.long 0x290++0x3
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line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
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hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
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bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0: The parity is not checked and a bad parity..,1: The parity is checked and a matching condition.."
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bitfld.long 0x0 12.--13. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start..,2: Comparison must be met to receive the current..,?"
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hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
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group.long 0x2A0++0x3
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line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
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hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
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hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
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bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0: RTS pin is not controlled by Receive FIFO..,1: RTS pin is controlled by Receive FIFO thresholds."
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bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x2A4++0x3
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line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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wgroup.long 0x2A8++0x7
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line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
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bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
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rgroup.long 0x2B0++0x7
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line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
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bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Number of unread data in Receive FIFO is above..,1: Number of unread data in Receive FIFO has.."
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bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0: The Transmit FIFO is not locked.,1: The Transmit FIFO is locked."
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bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0: No Receive FIFO pointer occurred,1: Receive FIFO pointer error occurred. Receiver.."
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bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0: No Transmit FIFO pointer occurred,1: Transmit FIFO pointer error occurred."
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bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Number of unread data in Receive FIFO is below..,1: Number of unread data in Receive FIFO has.."
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bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Receive FIFO is not empty.,1: Receive FIFO has been filled since the last.."
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bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Receive FIFO is not empty.,1: Receive FIFO has been emptied since the last.."
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bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Number of data in Transmit FIFO is above..,1: Number of data in Transmit FIFO has reached.."
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bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Transmit FIFO is not full.,1: Transmit FIFO has been filled since the last.."
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bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Transmit FIFO is not empty.,1: Transmit FIFO has been emptied since the last.."
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group.long 0x2E4++0x3
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line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection on configuration..,1: Enables the write protection on configuration.."
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rgroup.long 0x2E8++0x3
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line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
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hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
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wgroup.long 0x400++0x3
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line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
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bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0: No effect.,1: Disables the Transmit and Receive FIFOs"
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0: No effect.,1: Enables the Transmit and Receive FIFOs"
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bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0: No effect.,1: The current NPCS will be de-asserted after the.."
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bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0: No effect.,1: Empties the Receive FIFO."
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bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0: No effect.,1: Empties the Transmit FIFO."
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bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0: No effect.,1: Restarts the comparison trigger to enable.."
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bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0: No effect.,1: Reset the SPI. A software-triggered hardware.."
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bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0: No effect.,1: Disables the SPI."
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bitfld.long 0x0 0. "SPIEN,SPI Enable" "0: No effect.,1: Enables the SPI to transfer and receive data."
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group.long 0x404++0x3
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line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
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hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
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bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0: Local loopback path disabled.,1: Local loopback path enabled."
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bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0: No Effect. In Master mode a transfer can be..,1: In Master mode a transfer can start only if.."
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bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0: Mode fault detection is enabled.,1: Mode fault detection is disabled."
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bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
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bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0: The chip selects are directly connected to a..,1: The four NPCS chip select lines are connected to.."
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bitfld.long 0x0 1. "PS,Peripheral Select" "0: Fixed Peripheral Select,1: Variable Peripheral Select"
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bitfld.long 0x0 0. "MSTR,Master/Slave Mode" "0: SPI is in Slave mode.,1: SPI is in Master mode."
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rgroup.long 0x408++0x3
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line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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newline
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hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
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rgroup.long 0x408++0x3
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line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
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hexmask.long.word 0x0 16.--31. 1. "RD1,Receive Data"
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newline
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hexmask.long.word 0x0 0.--15. 1. "RD0,Receive Data"
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rgroup.long 0x408++0x3
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line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
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hexmask.long.byte 0x0 24.--31. 1. "RD3,Receive Data"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "RD2,Receive Data"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "RD1,Receive Data"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "RD0,Receive Data"
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wgroup.long 0x40C++0x3
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line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
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bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0: No effect.,1: The current NPCS is de-asserted after the.."
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newline
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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newline
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hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
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wgroup.long 0x40C++0x3
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line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
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hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
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newline
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hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
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rgroup.long 0x410++0x3
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line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
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bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0: No Receive FIFO pointer occurred,1: Receive FIFO pointer error occurred. Receiver.."
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newline
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bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0: No Transmit FIFO pointer occurred,1: Transmit FIFO pointer error occurred."
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newline
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bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0: Number of unread data in Receive FIFO is below..,1: Number of unread data in Receive FIFO has.."
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newline
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bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0: Receive FIFO is not empty or RXFE flag has been..,1: Receive FIFO has been filled (changing states.."
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newline
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bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0: Receive FIFO is not empty or RXFE flag has been..,1: Receive FIFO has been emptied (changing states.."
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newline
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bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0: Number of data in Transmit FIFO is above..,1: Number of data in Transmit FIFO has reached.."
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newline
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bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0: Transmit FIFO is not full or TXFF flag has been..,1: Transmit FIFO has been filled since the last.."
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newline
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bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0: Transmit FIFO is not empty.,1: Transmit FIFO has been emptied since the last.."
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newline
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bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0: SPI is disabled.,1: SPI is enabled."
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newline
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bitfld.long 0x0 12. "SFERR,Slave Frame Error (cleared on read)" "0: There is no frame error detected for a slave..,1: In Slave mode the chip select raised while the.."
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newline
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bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0: No received character matched the comparison..,1: A received character matched the comparison.."
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newline
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bitfld.long 0x0 10. "UNDES,Underrun Error Status (Slave mode only) (cleared on read)" "0: No underrun has been detected since the last..,1: A transfer starts whereas no data has been.."
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newline
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0: As soon as data is written in FLEX_SPI_TDR.,1: FLEX_SPI_TDR and internal shift register are.."
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newline
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bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0: No rising edge detected on NSS pin since the..,1: A rising edge occurred on NSS pin since the last.."
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newline
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bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0: No overrun has been detected since the last read..,1: An overrun has occurred since the last read of.."
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newline
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bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0: No mode fault has been detected since the last..,1: A mode fault occurred since the last read of.."
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newline
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bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0: Transmit FIFO cannot accept more data.,1: Transmit FIFO can accept data; one or more data.."
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newline
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0: Receive FIFO is empty; no data to read,1: At least one unread data is in the Receive FIFO"
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wgroup.long 0x414++0x7
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line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
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bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
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newline
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bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
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bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
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newline
|
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bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
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rgroup.long 0x41C++0x3
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line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
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bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
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newline
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bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
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repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
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group.long ($2+0x430)++0x3
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line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register x"
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hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
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newline
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hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
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newline
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bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0: The Peripheral Chip Select Line rises as soon as..,1: The Peripheral Chip Select does not rise after.."
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newline
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bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0: The Peripheral Chip Select does not rise between..,1: The Peripheral Chip Select rises systematically.."
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newline
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bitfld.long 0x0 1. "NCPHA,Clock Phase" "0: Data are changed on the leading edge of SPCK and..,1: Data are captured on the leading edge of SPCK.."
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newline
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bitfld.long 0x0 0. "CPOL,Clock Polarity" "0: The inactive state value of SPCK is logic level..,1: The inactive state value of SPCK is logic level.."
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repeat.end
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group.long 0x440++0x3
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line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
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newline
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hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
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newline
|
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bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
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newline
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bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
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rgroup.long 0x444++0x3
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line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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newline
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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group.long 0x448++0x3
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line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
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hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
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newline
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hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
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group.long 0x4E4++0x3
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line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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newline
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
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newline
|
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
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|
newline
|
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
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rgroup.long 0x4E8++0x3
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line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
|
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hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
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newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0: No write protect violation has occurred since..,1: A write protect violation has occurred since the.."
|
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wgroup.long 0x600++0x3
|
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line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
|
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bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0: No effect.,1: Disable the Transmit and Receive FIFOs"
|
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newline
|
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bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0: No effect.,1: Enable the Transmit and Receive FIFOs"
|
|
newline
|
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bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0: No effect.,1: Clear the TWI FSM lock."
|
|
newline
|
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bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0: No effect.,1: Clear the Transmit Holding Register and set.."
|
|
newline
|
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bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0: No effect.,1: Alternative Command mode disabled."
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0: No effect.,1: Alternative Command mode enabled."
|
|
newline
|
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bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0: No effect.,1: If Master mode is enabled send a bus clear.."
|
|
newline
|
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bitfld.long 0x0 14. "PECRQ,PEC Request" "0: No effect.,1: A PEC check or transmission is requested."
|
|
newline
|
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bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0: No effect.,1: SMBus PEC (CRC) generation and check disabled."
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0: No effect.,1: SMBus PEC (CRC) generation and check enabled."
|
|
newline
|
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bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0: No effect.,1: SMBus mode disabled."
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0: No effect.,1: If SMBDIS = 0 SMBus mode enabled."
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0: No effect.,1: High-speed mode disabled."
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0: No effect.,1: High-speed mode enabled."
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0: No effect.,1: Equivalent to a system reset."
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0: No effect.,1: If Master mode is enabled a SMBus Quick Command.."
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0: No effect.,1: The Slave mode is disabled. The shifter and.."
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0: No effect.,1: Enables the Slave mode (SVDIS must be written to.."
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0: No effect.,1: The Master mode is disabled all pending data is.."
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0: No effect.,1: Enables the Master mode (MSDIS must be written.."
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0: No effect.,1: STOP condition is sent just after completing the.."
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0: No effect.,1: A frame beginning with a START bit is.."
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0: No effect.,1: Disable the Transmit and Receive FIFOs."
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0: No effect.,1: Enable the Transmit and Receive FIFOs."
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0: No effect.,1: Clears the Transmit FIFO Lock."
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0: No effect.,1: Empties the Receive FIFO."
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0: No effect.,1: Empties the Transmit FIFO."
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0: No effect.,1: Alternative Command mode disabled."
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0: No effect.,1: Alternative Command mode enabled."
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0: No effect.,1: If Master mode is enabled send a bus clear.."
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0: No effect.,1: A PEC check or transmission is requested."
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0: No effect.,1: SMBus PEC (CRC) generation and check disabled."
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0: No effect.,1: SMBus PEC (CRC) generation and check enabled."
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0: No effect.,1: SMBus mode disabled."
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0: No effect.,1: If SMBDIS = 0 SMBus mode enabled."
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0: No effect.,1: High-speed mode disabled."
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0: No effect.,1: High-speed mode enabled."
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0: No effect.,1: Equivalent to a system reset."
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0: No effect.,1: If Master mode is enabled a SMBus Quick Command.."
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0: No effect.,1: The Slave mode is disabled. The shifter and.."
|
|
newline
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bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0: No effect.,1: Enables the Slave mode (SVDIS must be written to.."
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bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0: No effect.,1: The Master mode is disabled all pending data is.."
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bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0: No effect.,1: Enables the Master mode (MSDIS must be written.."
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bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0: No effect.,1: STOP condition is sent just after completing the.."
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bitfld.long 0x0 0. "START,Send a START Condition" "0: No effect.,1: A frame beginning with a START bit is.."
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group.long 0x604++0xF
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line.long 0x0 "FLEX_TWI_MMR,TWI Master Mode Register"
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bitfld.long 0x0 24. "NOAP,No Auto-Stop On NACK Error" "0: A stop condition is sent automatically upon..,1: No automatic action is performed upon.."
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hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
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bitfld.long 0x0 13.--14. "SCLRBL,SCL Rise Boost Level" "0,1,2,3"
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bitfld.long 0x0 12. "MREAD,Master Read Direction" "0: Master write direction.,1: Master read direction."
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bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
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line.long 0x4 "FLEX_TWI_SMR,TWI Slave Mode Register"
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bitfld.long 0x4 31. "DATAMEN,Data Matching Enable" "0: Data matching on first received data is disabled.,1: Data matching on first received data is enabled."
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bitfld.long 0x4 30. "SADR3EN,Slave Address 3 Enable" "0: Slave address 3 matching is disabled.,1: Slave address 3 matching is enabled."
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bitfld.long 0x4 29. "SADR2EN,Slave Address 2 Enable" "0: Slave address 2 matching is disabled.,1: Slave address 2 matching is enabled."
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bitfld.long 0x4 28. "SADR1EN,Slave Address 1 Enable" "0: Slave address 1 matching is disabled.,1: Slave address 1 matching is enabled."
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hexmask.long.byte 0x4 16.--22. 1. "SADR,Slave Address"
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hexmask.long.byte 0x4 8.--14. 1. "MASK,Slave Address Mask"
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bitfld.long 0x4 7. "SNIFF,Slave Sniffer Mode" "0: Slave Sniffer mode is disabled.,1: Slave Sniffer mode is enabled."
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bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0: No effect.,1: Clock stretching disabled in Slave mode OVRE and.."
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bitfld.long 0x4 5. "BSEL,TWI Bus Selection" "0: TWI analyzes the TWCK and TWD pins from its TWI..,1: TWI analyzes the TWCK pins TWD from consecutive.."
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bitfld.long 0x4 4. "SADAT,Slave Address Treated as Data" "0: Slave address is handled normally (will not trig..,1: Slave address is handled as data field RXRDY.."
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bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0: Acknowledge of the SMBus Host Header disabled.,1: Acknowledge of the SMBus Host Header enabled."
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bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0: Acknowledge of the SMBus Default Address disabled.,1: Acknowledge of the SMBus Default Address enabled."
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bitfld.long 0x4 0. "NACKEN,Slave Receiver Data Phase NACK Enable" "0: Normal value to be returned in the ACK cycle of..,1: NACK value to be returned in the ACK cycle of.."
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line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
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hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
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line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
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hexmask.long.byte 0xC 24.--29. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
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bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
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bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
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hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
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rgroup.long 0x620++0x3
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line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
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bitfld.long 0x0 26. "SR,Start Repeated" "0: No repeated start has been detected since last..,1: At least one repeated start has been detected.."
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bitfld.long 0x0 25. "SDA,SDA Line Value" "0: SDA line sampled value is '0'.,1: SDA line sampled value is '1'."
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bitfld.long 0x0 24. "SCL,SCL Line Value" "0: SCL line sampled value is '0'.,1: SCL line sampled value is '1.'"
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bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0: The TWI is not locked.,1: The TWI is locked due to frame errors (see.."
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0: No SMBus Host Header Address received.,1: A SMBus Host Header Address was received."
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0: No SMBus Default Address received.,1: A SMBus Default Address was received."
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bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0: No SMBus PEC error occurred.,1: A SMBus PEC error occurred."
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bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0: No SMBus timeout occurred.,1: SMBus timeout occurred."
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bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag" "0: No SMBus slave drives the SMBALERT line.,1: At least one SMBus slave drives the SMBALERT line."
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0: No master code has been received.,1: A master code has been received."
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0: A slave access is being performing.,1: The Slave Access is finished. End Of Slave.."
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bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0: The clock is not stretched.,1: The clock is stretched. FLEX_TWI_THR /.."
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0: Arbitration won.,1: Arbitration lost. Another master of the TWI bus.."
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bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0: Each data byte has been correctly received by..,1: In Read mode a data byte has not been.."
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bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0: FLEX_TWI_THR has been filled on time.,1: FLEX_TWI_THR has not been filled on time."
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bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0: FLEX_TWI_RHR has not been loaded while RXRDY was..,1: FLEX_TWI_RHR has been loaded while RXRDY was.."
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bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0: No general call has been detected.,1: A general call has been detected. After the.."
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bitfld.long 0x0 4. "SVACC,Slave Access" "0: TWI is not addressed. SVACC is automatically..,1: Indicates that the address decoding sequence has.."
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bitfld.long 0x0 3. "SVREAD,Slave Read" "0: Indicates that a write access is performed by a..,1: Indicates that a read access is performed by a.."
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0: Transmit FIFO is full and cannot accept more data,1: Transmit FIFO is not full; one or more data can.."
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0: Receive FIFO is empty; no data to read,1: At least one unread data is in the Receive FIFO"
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0: As soon as a Start is detected.,1: After a Stop or a Repeated Start + an address.."
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rgroup.long 0x620++0x3
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line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
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bitfld.long 0x0 26. "SR,Start Repeated" "0: No repeated start has been detected since last..,1: At least one repeated start has been detected.."
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bitfld.long 0x0 25. "SDA,SDA Line Value" "0: SDA line sampled value is '0'.,1: SDA line sampled value is '1'."
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bitfld.long 0x0 24. "SCL,SCL Line Value" "0: SCL line sampled value is '0'.,1: SCL line sampled value is '1.'"
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bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0: The Transmit FIFO is not locked.,1: The Transmit FIFO is locked."
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0: No SMBus Host Header Address received.,1: A SMBus Host Header Address was received."
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0: No SMBus Default Address received.,1: A SMBus Default Address was received."
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bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0: No SMBus PEC error occurred.,1: A SMBus PEC error occurred."
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bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0: No SMBus timeout occurred.,1: SMBus timeout occurred."
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bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag" "0: No SMBus slave drives the SMBALERT line.,1: At least one SMBus slave drives the SMBALERT line."
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0: No master code has been received.,1: A master code has been received."
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0: A slave access is being performing.,1: The Slave Access is finished. End Of Slave.."
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bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0: The clock is not stretched.,1: The clock is stretched. FLEX_TWI_THR /.."
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0: Arbitration won.,1: Arbitration lost. Another master of the TWI bus.."
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bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0: Each data byte has been correctly received by..,1: In Read mode a data byte has not been.."
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bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0: FLEX_TWI_THR has been filled on time.,1: FLEX_TWI_THR has not been filled on time."
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bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0: FLEX_TWI_RHR has not been loaded while RXRDY was..,1: FLEX_TWI_RHR has been loaded while RXRDY was.."
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bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0: No general call has been detected.,1: A general call has been detected. After the.."
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bitfld.long 0x0 4. "SVACC,Slave Access" "0: TWI is not addressed. SVACC is automatically..,1: Indicates that the address decoding sequence has.."
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bitfld.long 0x0 3. "SVREAD,Slave Read" "0: Indicates that a write access is performed by a..,1: Indicates that a read access is performed by a.."
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0: Transmit FIFO is full and cannot accept more data.,1: Transmit FIFO is not full; one or more data can.."
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0: Receive FIFO is empty; no data to read.,1: At least one unread data is in the Receive FIFO."
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0: As soon as a Start is detected.,1: After a Stop or a Repeated Start + an address.."
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wgroup.long 0x624++0x7
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line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
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bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
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bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Enable" "0,1"
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bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
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bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
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bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
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bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Enable" "0,1"
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bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
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bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
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bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
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bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
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bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
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bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
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bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
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bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
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bitfld.long 0x4 16. "MCACK,Master Code Acknowledge Interrupt Disable" "0,1"
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bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
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bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
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bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
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bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
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bitfld.long 0x4 11. "EOSACC,End Of Slave Access Interrupt Disable" "0,1"
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bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
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bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
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bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
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bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
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bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
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bitfld.long 0x4 4. "SVACC,Slave Access Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
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rgroup.long 0x62C++0x7
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line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
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bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
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bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Mask" "0,1"
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bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
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bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
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bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
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bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Mask" "0,1"
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bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
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bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
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bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Mask" "0,1"
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
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bitfld.long 0x4 11.--12. "ASTATE,Acknowledge State (Slave Sniffer Mode only)" "0: No Acknowledge or Nacknowledge detected after..,1: Acknowledge (A) detected after previously logged..,2: Nacknowledge (NA) detected after previously..,3: Not defined"
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bitfld.long 0x4 10. "PSTATE,Stop State (Slave Sniffer Mode only)" "0: No STOP (P) detected after previous logged data.,1: Stop detected (P) after previous logged data."
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bitfld.long 0x4 8.--9. "SSTATE,Start State (Slave Sniffer Mode only)" "0: No START detected with the logged data,1: START (S) detected with the logged data,2: Repeated START (Sr) detected with the logged data,3: Not defined"
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hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Master or Slave Receive Holding Data"
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rgroup.long 0x630++0x3
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line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Master or Slave Receive Holding Data 3"
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hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Master or Slave Receive Holding Data 2"
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hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Master or Slave Receive Holding Data 1"
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hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Master or Slave Receive Holding Data 0"
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wgroup.long 0x634++0x3
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line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Master or Slave Transmit Holding Data"
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wgroup.long 0x634++0x3
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line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Master or Slave Transmit Holding Data 3"
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hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Master or Slave Transmit Holding Data 2"
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hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Master or Slave Transmit Holding Data 1"
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Master or Slave Transmit Holding Data 0"
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group.long 0x638++0x1B
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line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
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hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
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hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Master Clock Stretch Maximum Cycles"
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hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Slave Clock Stretch Maximum Cycles"
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hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
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line.long 0x4 "FLEX_TWI_HSR,TWI High Speed Register"
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hexmask.long.byte 0x4 0.--7. 1. "MCODE,TWI High Speed Master Code"
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line.long 0x8 "FLEX_TWI_ACR,TWI Alternative Command Register"
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bitfld.long 0x8 25. "NPEC,Next PEC Request (SMBus Mode only)" "0: The next transfer does not use a PEC byte.,1: The next transfer uses a PEC byte."
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bitfld.long 0x8 24. "NDIR,Next Transfer Direction" "0: Write direction.,1: Read direction."
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hexmask.long.byte 0x8 16.--23. 1. "NDATAL,Next Data Length"
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bitfld.long 0x8 9. "PEC,PEC Request (SMBus Mode only)" "0: The transfer does not use a PEC byte.,1: The transfer uses a PEC byte."
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bitfld.long 0x8 8. "DIR,Transfer Direction" "0: Write direction.,1: Read direction."
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hexmask.long.byte 0x8 0.--7. 1. "DATAL,Data Length"
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line.long 0xC "FLEX_TWI_FILTR,TWI Filter Register"
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bitfld.long 0xC 8.--10. "THRES,Digital Filter Threshold" "0: No filtering applied on TWI inputs.,?,?,?,?,?,?,?"
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bitfld.long 0xC 1. "PADFEN,PAD Filter Enable" "0: PAD analog filter is disabled.,1: PAD analog filter is enabled. (The analog filter.."
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bitfld.long 0xC 0. "FILT,RX Digital Filter" "0: No filtering applied on TWI inputs.,1: TWI input filtering is active. (Only in Standard.."
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line.long 0x10 "FLEX_TWI_HSCWGR,TWI High Speed Clock Waveform Generator Register"
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bitfld.long 0x10 16.--18. "HSCKDIV,High Speed Clock Divider" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x10 8.--15. 1. "HSCHDIV,High Speed Clock High Divider"
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hexmask.long.byte 0x10 0.--7. 1. "HSCLDIV,High Speed Clock Low Divider"
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line.long 0x14 "FLEX_TWI_SWMR,TWI Matching Register"
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hexmask.long.byte 0x14 24.--31. 1. "DATAM,Data Match"
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hexmask.long.byte 0x14 16.--22. 1. "SADR3,Slave Address 3"
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hexmask.long.byte 0x14 8.--14. 1. "SADR2,Slave Address 2"
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hexmask.long.byte 0x14 0.--6. 1. "SADR1,Slave Address 1"
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line.long 0x18 "FLEX_TWI_FMR,TWI FIFO Mode Register"
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hexmask.long.byte 0x18 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
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hexmask.long.byte 0x18 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
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bitfld.long 0x18 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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bitfld.long 0x18 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x654++0x3
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line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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rgroup.long 0x660++0x3
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line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
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bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0: No Receive FIFO pointer occurred,1: Receive FIFO pointer error occurred. Receiver.."
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bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0: No Transmit FIFO pointer occurred,1: Transmit FIFO pointer error occurred."
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bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0: Number of unread data in Receive FIFO is below..,1: Number of unread data in Receive FIFO has.."
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bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0: Receive FIFO is not empty.,1: Receive FIFO has been filled since the last read.."
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bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0: Receive FIFO is not empty.,1: Receive FIFO has been emptied since the last.."
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bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0: Number of data in Transmit FIFO is above..,1: Number of data in Transmit FIFO has reached.."
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bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0: Transmit FIFO is not full.,1: Transmit FIFO has been filled since the last.."
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bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0: Transmit FIFO is not empty.,1: Transmit FIFO has been emptied since the last.."
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wgroup.long 0x664++0x7
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line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
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rgroup.long 0x66C++0x3
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line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
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group.long 0x6E4++0x3
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line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
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rgroup.long 0x6E8++0x3
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line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
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bitfld.long 0x0 0. "WPVS,Write Protect Violation Status" "0: No Write Protection Violation has occurred since..,1: A Write Protection Violation has occurred since.."
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tree.end
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tree "FLEXCOM11"
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base ad:0xE2824000
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group.long 0x0++0x3
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line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
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bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected. USART/TWI..,3: All TWI related protocols are selected (TWI.."
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rgroup.long 0x10++0x3
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line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
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hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
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group.long 0x20++0x3
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line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
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wgroup.long 0x200++0x3
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line.long 0x0 "FLEX_US_CR,USART Control Register"
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bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0: No effect.,1: Disables the Transmit and Receive FIFOs."
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0: No effect.,1: Enables the Transmit and Receive FIFOs."
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bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0: No effect.,1: Restarts the comparison trigger to enable.."
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bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0: No effect.,1: Clears the Transmit FIFO Lock"
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bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0: No effect.,1: Empties the Receive FIFO."
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bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0: No effect.,1: Empties the Transmit FIFO."
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bitfld.long 0x0 21. "LINWKUP,Send LIN Wakeup Signal" "0: No effect:,1: Sends a wakeup signal on the LIN bus."
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bitfld.long 0x0 20. "LINABT,Abort LIN Transmission" "0: No effect.,1: Aborts the current LIN transmission."
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bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0: No effect.,1: Drives the RTS pin to 0 if FLEX_US_MR.USART_MODE.."
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bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0: No effect.,1: Drives the RTS pin to 1 if FLEX_US_MR.USART_MODE.."
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bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0: No effect,1: Immediately restarts timeout period."
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bitfld.long 0x0 14. "RSTNACK,Reset Non Acknowledge" "0: No effect,1: Resets FLEX_US_CSR.NACK."
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bitfld.long 0x0 13. "RSTIT,Reset Iterations" "0: No effect.,1: Resets FLEX_US_CSR.ITER. No effect if the.."
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bitfld.long 0x0 12. "SENDA,Send Address" "0: No effect.,1: In Multidrop mode only the next character.."
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bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0: No effect.,1: Starts waiting for a character before clocking.."
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bitfld.long 0x0 10. "STPBRK,Stop Break" "0: No effect.,1: Stops transmission of the break after a minimum.."
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bitfld.long 0x0 9. "STTBRK,Start Break" "0: No effect.,1: Starts transmission of a break after the.."
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bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0: No effect.,1: Resets the status bits PARE FRAME OVRE MANE.."
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bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0: No effect.,1: Disables the transmitter."
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bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0: No effect.,1: Enables the transmitter if TXDIS is 0."
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bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0: No effect.,1: Disables the receiver."
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bitfld.long 0x0 4. "RXEN,Receiver Enable" "0: No effect.,1: Enables the receiver if RXDIS is 0."
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bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0: No effect.,1: Resets the transmitter."
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bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0: No effect.,1: Resets the receiver."
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group.long 0x204++0x3
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line.long 0x0 "FLEX_US_MR,USART Mode Register"
|
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bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0: Start frame delimiter is COMMAND or DATA SYNC.,1: Start frame delimiter is one bit."
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bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0: The Manchester start bit is a 0 to 1 transition,1: The Manchester start bit is a 1 to 0 transition."
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bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0: Manchester encoder/decoder are disabled.,1: Manchester encoder/decoder are enabled."
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bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0: The USART does not filter the receive line.,1: The USART filters the receive line using a.."
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bitfld.long 0x0 24.--26. "MAX_ITERATION,Maximum Number of Automatic Iteration" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 23. "INVDATA,Inverted Data" "0: The data field transmitted on TXD line is the..,1: The data field transmitted on TXD line is.."
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bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0: User defined configuration of command or data..,1: The sync field is updated when a character is.."
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bitfld.long 0x0 21. "DSNACK,Disable Successive NACK" "0: NACK is sent on the ISO line as soon as a parity..,1: Successive parity errors are counted up to the.."
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bitfld.long 0x0 20. "INACK,Inhibit Non Acknowledge" "0: The NACK is generated.,1: The NACK is not generated."
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bitfld.long 0x0 19. "OVER,Oversampling Mode" "0: 16x Oversampling.,1: 8x Oversampling."
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bitfld.long 0x0 18. "CLKO,Clock Output Select" "0: The USART does not drive the SCK pin..,1: The USART drives the SCK pin if USCLKS does not.."
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bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0: CHRL defines character length.,1: 9-bit character length."
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bitfld.long 0x0 16. "MSBF,Bit Order" "0: Least significant bit is sent/received first.,1: Most significant bit is sent/received first."
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bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
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bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
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bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
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bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0: USART operates in Asynchronous mode (UART).,1: USART operates in Synchronous mode."
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bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
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bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
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hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
|
|
wgroup.long 0x208++0x3
|
|
line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 10. "ITER,Max number of Repetitions Reached Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
wgroup.long 0x208++0x7
|
|
line.long 0x0 "FLEX_US_IER_LIN_MODE,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Enable" "0,1"
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Enable" "0,1"
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|
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|
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Enable" "0,1"
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|
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|
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Enable" "0,1"
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|
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|
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Enable" "0,1"
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|
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|
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Enable" "0,1"
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
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bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt Disable" "0,1"
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bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
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bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
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bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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wgroup.long 0x20C++0x3
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line.long 0x0 "FLEX_US_IDR_LIN_MODE,USART Interrupt Disable Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Disable" "0,1"
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Disable" "0,1"
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Disable" "0,1"
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Disable" "0,1"
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Disable" "0,1"
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Disable" "0,1"
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Disable" "0,1"
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Disable" "0,1"
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Disable" "0,1"
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Disable" "0,1"
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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rgroup.long 0x210++0x3
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line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Mask" "0,1"
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bitfld.long 0x0 10. "ITER,Max Number of Repetitions Reached Interrupt Mask" "0,1"
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
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rgroup.long 0x210++0x7
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line.long 0x0 "FLEX_US_IMR_LIN_MODE,USART Interrupt Mask Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Mask" "0,1"
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Mask" "0,1"
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error Interrupt Mask" "0,1"
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Mask" "0,1"
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Mask" "0,1"
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Mask" "0,1"
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Mask" "0,1"
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Mask" "0,1"
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
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bitfld.long 0x4 24. "MANE,Manchester Error" "0: No Manchester error has been detected since the..,1: At least one Manchester error has been detected.."
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bitfld.long 0x4 23. "CTS,Image of CTS Input" "0: CTS input is driven low.,1: CTS input is driven high."
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newline
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bitfld.long 0x4 22. "CMP,Comparison Status" "0: No received character matched the comparison..,1: A received character matched the comparison.."
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newline
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0: No input change has been detected on the CTS pin..,1: At least one input change has been detected on.."
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newline
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt" "0: Non acknowledge has not been detected since the..,1: At least one non acknowledge has been detected.."
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newline
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bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached" "0: Maximum number of repetitions has not been..,1: Maximum number of repetitions has been reached.."
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newline
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bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0: There are characters in either FLEX_US_THR or..,1: There are no characters in FLEX_US_THR nor in.."
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bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0: There has not been a timeout since the last..,1: There has been a timeout since the last Start.."
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newline
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bitfld.long 0x4 7. "PARE,Parity Error" "0: No parity error has been detected since the last..,1: At least one parity error has been detected.."
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newline
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bitfld.long 0x4 6. "FRAME,Framing Error" "0: No stop bit has been detected low since the last..,1: At least one stop bit has been detected low.."
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newline
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bitfld.long 0x4 5. "OVRE,Overrun Error" "0: No overrun error has occurred since the last..,1: At least one overrun error has occurred since.."
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newline
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bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0: No break received or end of break detected since..,1: Break received or end of break detected since.."
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bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0: Transmit FIFO is full and cannot accept more data,1: Transmit FIFO is not full; one or more data can.."
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bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0: Receive FIFO is empty; no data to read,1: At least one unread data is in the Receive FIFO"
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rgroup.long 0x214++0x7
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line.long 0x0 "FLEX_US_CSR_LIN_MODE,USART Channel Status Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error" "0: No LIN header timeout error has been detected..,1: A LIN header timeout error has been detected.."
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error" "0: No LIN synch tolerance error has been detected..,1: A LIN synch tolerance error has been detected.."
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newline
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bitfld.long 0x0 29. "LINSNRE,LIN Slave Not Responding Error" "0: No LIN slave not responding error has been..,1: A LIN slave not responding error has been.."
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newline
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error" "0: No LIN checksum error has been detected since..,1: A LIN checksum error has been detected since the.."
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newline
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Error" "0: No LIN identifier parity error has been detected..,1: A LIN identifier parity error has been detected.."
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error" "0: No LIN inconsistent synch field error has been..,1: The USART is configured as a slave node and a.."
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newline
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bitfld.long 0x0 25. "LINBE,LIN Bit Error" "0: No bit error has been detected since the last..,1: A bit error has been detected since the last.."
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bitfld.long 0x0 23. "LINBLS,LIN Bus Line Status" "0: LIN bus line is set to 0.,1: LIN bus line is set to 1."
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newline
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed" "0: The USART is idle or a LIN transfer is ongoing.,1: A LIN transfer has been completed since the last.."
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newline
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received" "0: No LIN identifier has been received since the..,1: At least one LIN identifier has been received.."
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received" "0: No LIN break has received sent since the last..,1: At least one LIN break has been received since.."
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bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0: There are characters in either FLEX_US_THR or..,1: There are no characters in FLEX_US_THR nor in.."
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bitfld.long 0x0 8. "TIMEOUT,Receiver Timeout" "0: There has not been a timeout since the last..,1: There has been a timeout since the last start.."
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newline
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bitfld.long 0x0 7. "PARE,Parity Error" "0: No parity error has been detected since the last..,1: At least one parity error has been detected.."
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error" "0: No stop bit has been detected low since the last..,1: At least one stop bit has been detected low.."
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error" "0: No overrun error has occurred since the last..,1: At least one overrun error has occurred since.."
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bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0: A character in FLEX_US_THR is waiting to be..,1: There is no character in FLEX_US_THR."
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bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0: No complete character has been received since..,1: At least one complete character has been.."
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line.long 0x4 "FLEX_US_RHR,USART Receive Holding Register"
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bitfld.long 0x4 15. "RXSYNH,Received Sync" "0: Last character received is a data.,1: Last character received is a command."
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newline
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hexmask.long.word 0x4 0.--8. 1. "RXCHR,Received Character"
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rgroup.long 0x218++0x3
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line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Characters"
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hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Characters"
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hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Characters"
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hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Characters"
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wgroup.long 0x21C++0x3
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line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
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bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0: The next character sent is encoded as a data.,1: The next character sent is encoded as a command."
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newline
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hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
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wgroup.long 0x21C++0x3
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line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
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hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
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hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
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group.long 0x220++0xB
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line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
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bitfld.long 0x0 16.--18. "FP,Fractional Part" "0: Fractional divider is disabled.,?,?,?,?,?,?,?"
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newline
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hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
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line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
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hexmask.long.tbyte 0x4 0.--16. 1. "TO,Timeout Value"
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line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
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hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
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group.long 0x240++0x3
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line.long 0x0 "FLEX_US_FIDI,USART FI DI Ratio Register"
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hexmask.long.word 0x0 0.--15. 1. "FI_DI_RATIO,FI Over DI Ratio Value"
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rgroup.long 0x244++0x3
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line.long 0x0 "FLEX_US_NER,USART Number of Errors Register"
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hexmask.long.byte 0x0 0.--7. 1. "NB_ERRORS,Number of Errors"
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group.long 0x24C++0xF
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line.long 0x0 "FLEX_US_IF,USART IrDA Filter Register"
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hexmask.long.byte 0x0 0.--7. 1. "IRDA_FILTER,IrDA Filter"
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line.long 0x4 "FLEX_US_MAN,USART Manchester Configuration Register"
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bitfld.long 0x4 31. "RXIDLEV,Receiver Idle Value" "0: Receiver line idle value is 0.,1: Receiver line idle value is 1."
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bitfld.long 0x4 30. "DRIFT,Drift Compensation" "0: The USART cannot recover from an important clock..,1: The USART can recover from clock drift. The 16X.."
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bitfld.long 0x4 29. "ONE,Must Be Set to 1" "0,1"
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bitfld.long 0x4 28. "RX_MPOL,Receiver Manchester Polarity" "0: Logic zero is coded as a zero-to-one transition..,1: Logic zero is coded as a one-to-zero transition.."
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bitfld.long 0x4 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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hexmask.long.byte 0x4 16.--19. 1. "RX_PL,Receiver Preamble Length"
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bitfld.long 0x4 12. "TX_MPOL,Transmitter Manchester Polarity" "0: Logic zero is coded as a zero-to-one transition..,1: Logic zero is coded as a one-to-zero transition.."
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bitfld.long 0x4 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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hexmask.long.byte 0x4 0.--3. 1. "TX_PL,Transmitter Preamble Length"
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line.long 0x8 "FLEX_US_LINMR,USART LIN Mode Register"
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bitfld.long 0x8 17. "SYNCDIS,Synchronization Disable" "0: The synchronization procedure is performed in..,1: The synchronization procedure is not performed.."
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bitfld.long 0x8 16. "PDCM,DMAC Mode" "0: The LIN mode register FLEX_US_LINMR is not..,1: The LIN mode register FLEX_US_LINMR (excepting.."
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hexmask.long.byte 0x8 8.--15. 1. "DLC,Data Length Control"
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bitfld.long 0x8 7. "WKUPTYP,Wakeup Signal Type" "0: Setting the LINWKUP bit in the control register..,1: Setting the LINWKUP bit in the control register.."
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bitfld.long 0x8 6. "FSDIS,Frame Slot Mode Disable" "0: The Frame Slot mode is enabled.,1: The Frame Slot mode is disabled."
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bitfld.long 0x8 5. "DLM,Data Length Mode" "0: The response data length is defined by the DLC..,1: The response data length is defined by the bits.."
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bitfld.long 0x8 4. "CHKTYP,Checksum Type" "0: LIN 2.0 'enhanced' checksum,1: LIN 1.3 'classic' checksum"
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bitfld.long 0x8 3. "CHKDIS,Checksum Disable" "0: In master node configuration the checksum is..,1: Whatever the node configuration is the checksum.."
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bitfld.long 0x8 2. "PARDIS,Parity Disable" "0: In master node configuration the identifier..,1: Whatever the node configuration is the.."
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bitfld.long 0x8 0.--1. "NACT,LIN Node Action" "0: The USART transmits the response.,1: The USART receives the response.,2: The USART does not transmit and does not receive..,?"
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line.long 0xC "FLEX_US_LINIR,USART LIN Identifier Register"
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hexmask.long.byte 0xC 0.--7. 1. "IDCHR,Identifier Character"
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rgroup.long 0x25C++0x3
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line.long 0x0 "FLEX_US_LINBRR,USART LIN Baud Rate Register"
|
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bitfld.long 0x0 16.--18. "LINFP,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.word 0x0 0.--15. 1. "LINCD,Clock Divider after Synchronization"
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group.long 0x290++0x3
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line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
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hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
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newline
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bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0: The parity is not checked and a bad parity..,1: The parity is checked and a matching condition.."
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newline
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bitfld.long 0x0 12.--13. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start..,2: Comparison must be met to receive the current..,?"
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hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
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group.long 0x2A0++0x3
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line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
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hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
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hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
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bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0: RTS pin is not controlled by Receive FIFO..,1: RTS pin is controlled by Receive FIFO thresholds."
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bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x2A4++0x3
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line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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wgroup.long 0x2A8++0x7
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line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
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bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
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rgroup.long 0x2B0++0x7
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line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
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bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Number of unread data in Receive FIFO is above..,1: Number of unread data in Receive FIFO has.."
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bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0: The Transmit FIFO is not locked.,1: The Transmit FIFO is locked."
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bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0: No Receive FIFO pointer occurred,1: Receive FIFO pointer error occurred. Receiver.."
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bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0: No Transmit FIFO pointer occurred,1: Transmit FIFO pointer error occurred."
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bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Number of unread data in Receive FIFO is below..,1: Number of unread data in Receive FIFO has.."
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bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Receive FIFO is not empty.,1: Receive FIFO has been filled since the last.."
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bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Receive FIFO is not empty.,1: Receive FIFO has been emptied since the last.."
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bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Number of data in Transmit FIFO is above..,1: Number of data in Transmit FIFO has reached.."
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bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Transmit FIFO is not full.,1: Transmit FIFO has been filled since the last.."
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bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0: Transmit FIFO is not empty.,1: Transmit FIFO has been emptied since the last.."
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group.long 0x2E4++0x3
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line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection on configuration..,1: Enables the write protection on configuration.."
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rgroup.long 0x2E8++0x3
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line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
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hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
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wgroup.long 0x400++0x3
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line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
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bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0: No effect.,1: Disables the Transmit and Receive FIFOs"
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0: No effect.,1: Enables the Transmit and Receive FIFOs"
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bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0: No effect.,1: The current NPCS will be de-asserted after the.."
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bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0: No effect.,1: Empties the Receive FIFO."
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bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0: No effect.,1: Empties the Transmit FIFO."
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bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0: No effect.,1: Restarts the comparison trigger to enable.."
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bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0: No effect.,1: Reset the SPI. A software-triggered hardware.."
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bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0: No effect.,1: Disables the SPI."
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bitfld.long 0x0 0. "SPIEN,SPI Enable" "0: No effect.,1: Enables the SPI to transfer and receive data."
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group.long 0x404++0x3
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line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
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hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
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bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0: Local loopback path disabled.,1: Local loopback path enabled."
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bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0: No Effect. In Master mode a transfer can be..,1: In Master mode a transfer can start only if.."
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bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0: Mode fault detection is enabled.,1: Mode fault detection is disabled."
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bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
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bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0: The chip selects are directly connected to a..,1: The four NPCS chip select lines are connected to.."
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bitfld.long 0x0 1. "PS,Peripheral Select" "0: Fixed Peripheral Select,1: Variable Peripheral Select"
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bitfld.long 0x0 0. "MSTR,Master/Slave Mode" "0: SPI is in Slave mode.,1: SPI is in Master mode."
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rgroup.long 0x408++0x3
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line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
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rgroup.long 0x408++0x3
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line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
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hexmask.long.word 0x0 16.--31. 1. "RD1,Receive Data"
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hexmask.long.word 0x0 0.--15. 1. "RD0,Receive Data"
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rgroup.long 0x408++0x3
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line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
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hexmask.long.byte 0x0 24.--31. 1. "RD3,Receive Data"
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hexmask.long.byte 0x0 16.--23. 1. "RD2,Receive Data"
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hexmask.long.byte 0x0 8.--15. 1. "RD1,Receive Data"
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hexmask.long.byte 0x0 0.--7. 1. "RD0,Receive Data"
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wgroup.long 0x40C++0x3
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line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
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bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0: No effect.,1: The current NPCS is de-asserted after the.."
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
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wgroup.long 0x40C++0x3
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line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
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hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
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hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
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rgroup.long 0x410++0x3
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line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
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bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0: No Receive FIFO pointer occurred,1: Receive FIFO pointer error occurred. Receiver.."
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bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0: No Transmit FIFO pointer occurred,1: Transmit FIFO pointer error occurred."
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bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0: Number of unread data in Receive FIFO is below..,1: Number of unread data in Receive FIFO has.."
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bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0: Receive FIFO is not empty or RXFE flag has been..,1: Receive FIFO has been filled (changing states.."
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bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0: Receive FIFO is not empty or RXFE flag has been..,1: Receive FIFO has been emptied (changing states.."
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bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0: Number of data in Transmit FIFO is above..,1: Number of data in Transmit FIFO has reached.."
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bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0: Transmit FIFO is not full or TXFF flag has been..,1: Transmit FIFO has been filled since the last.."
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bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0: Transmit FIFO is not empty.,1: Transmit FIFO has been emptied since the last.."
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bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0: SPI is disabled.,1: SPI is enabled."
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bitfld.long 0x0 12. "SFERR,Slave Frame Error (cleared on read)" "0: There is no frame error detected for a slave..,1: In Slave mode the chip select raised while the.."
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bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0: No received character matched the comparison..,1: A received character matched the comparison.."
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bitfld.long 0x0 10. "UNDES,Underrun Error Status (Slave mode only) (cleared on read)" "0: No underrun has been detected since the last..,1: A transfer starts whereas no data has been.."
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0: As soon as data is written in FLEX_SPI_TDR.,1: FLEX_SPI_TDR and internal shift register are.."
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bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0: No rising edge detected on NSS pin since the..,1: A rising edge occurred on NSS pin since the last.."
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bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0: No overrun has been detected since the last read..,1: An overrun has occurred since the last read of.."
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bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0: No mode fault has been detected since the last..,1: A mode fault occurred since the last read of.."
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bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0: Transmit FIFO cannot accept more data.,1: Transmit FIFO can accept data; one or more data.."
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0: Receive FIFO is empty; no data to read,1: At least one unread data is in the Receive FIFO"
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wgroup.long 0x414++0x7
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line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
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bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
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bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
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bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
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bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
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bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
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bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
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bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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|
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bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
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bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
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|
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bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
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|
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bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
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|
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bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
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bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
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|
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bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
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|
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bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
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|
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bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
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|
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bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
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rgroup.long 0x41C++0x3
|
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line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
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bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
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|
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bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
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|
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bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
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bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
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newline
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bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
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repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
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group.long ($2+0x430)++0x3
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line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register x"
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hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
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newline
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hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
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newline
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bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0: The Peripheral Chip Select Line rises as soon as..,1: The Peripheral Chip Select does not rise after.."
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newline
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bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0: The Peripheral Chip Select does not rise between..,1: The Peripheral Chip Select rises systematically.."
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newline
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bitfld.long 0x0 1. "NCPHA,Clock Phase" "0: Data are changed on the leading edge of SPCK and..,1: Data are captured on the leading edge of SPCK.."
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newline
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bitfld.long 0x0 0. "CPOL,Clock Polarity" "0: The inactive state value of SPCK is logic level..,1: The inactive state value of SPCK is logic level.."
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repeat.end
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group.long 0x440++0x3
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line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
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newline
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hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
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newline
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bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
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newline
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bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
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rgroup.long 0x444++0x3
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line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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newline
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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group.long 0x448++0x3
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line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
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hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
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newline
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hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
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group.long 0x4E4++0x3
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line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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newline
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
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newline
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
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newline
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
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rgroup.long 0x4E8++0x3
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line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
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hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
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newline
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0: No write protect violation has occurred since..,1: A write protect violation has occurred since the.."
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wgroup.long 0x600++0x3
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line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
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bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0: No effect.,1: Disable the Transmit and Receive FIFOs"
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newline
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bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0: No effect.,1: Enable the Transmit and Receive FIFOs"
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newline
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bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0: No effect.,1: Clear the TWI FSM lock."
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newline
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bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0: No effect.,1: Clear the Transmit Holding Register and set.."
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newline
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bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0: No effect.,1: Alternative Command mode disabled."
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newline
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bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0: No effect.,1: Alternative Command mode enabled."
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newline
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bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0: No effect.,1: If Master mode is enabled send a bus clear.."
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newline
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bitfld.long 0x0 14. "PECRQ,PEC Request" "0: No effect.,1: A PEC check or transmission is requested."
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newline
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bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0: No effect.,1: SMBus PEC (CRC) generation and check disabled."
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newline
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bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0: No effect.,1: SMBus PEC (CRC) generation and check enabled."
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|
newline
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bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0: No effect.,1: SMBus mode disabled."
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|
newline
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bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0: No effect.,1: If SMBDIS = 0 SMBus mode enabled."
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newline
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bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0: No effect.,1: High-speed mode disabled."
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newline
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bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0: No effect.,1: High-speed mode enabled."
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newline
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bitfld.long 0x0 7. "SWRST,Software Reset" "0: No effect.,1: Equivalent to a system reset."
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newline
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bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0: No effect.,1: If Master mode is enabled a SMBus Quick Command.."
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newline
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bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0: No effect.,1: The Slave mode is disabled. The shifter and.."
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newline
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bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0: No effect.,1: Enables the Slave mode (SVDIS must be written to.."
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|
newline
|
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bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0: No effect.,1: The Master mode is disabled all pending data is.."
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newline
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bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0: No effect.,1: Enables the Master mode (MSDIS must be written.."
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newline
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bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0: No effect.,1: STOP condition is sent just after completing the.."
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newline
|
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bitfld.long 0x0 0. "START,Send a START Condition" "0: No effect.,1: A frame beginning with a START bit is.."
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wgroup.long 0x600++0x3
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line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
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bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0: No effect.,1: Disable the Transmit and Receive FIFOs."
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|
newline
|
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bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0: No effect.,1: Enable the Transmit and Receive FIFOs."
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newline
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bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0: No effect.,1: Clears the Transmit FIFO Lock."
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newline
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bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0: No effect.,1: Empties the Receive FIFO."
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|
newline
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bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0: No effect.,1: Empties the Transmit FIFO."
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newline
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bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0: No effect.,1: Alternative Command mode disabled."
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|
newline
|
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bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0: No effect.,1: Alternative Command mode enabled."
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newline
|
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bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0: No effect.,1: If Master mode is enabled send a bus clear.."
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|
newline
|
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bitfld.long 0x0 14. "PECRQ,PEC Request" "0: No effect.,1: A PEC check or transmission is requested."
|
|
newline
|
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bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0: No effect.,1: SMBus PEC (CRC) generation and check disabled."
|
|
newline
|
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bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0: No effect.,1: SMBus PEC (CRC) generation and check enabled."
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|
newline
|
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bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0: No effect.,1: SMBus mode disabled."
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newline
|
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bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0: No effect.,1: If SMBDIS = 0 SMBus mode enabled."
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newline
|
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bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0: No effect.,1: High-speed mode disabled."
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|
newline
|
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bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0: No effect.,1: High-speed mode enabled."
|
|
newline
|
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bitfld.long 0x0 7. "SWRST,Software Reset" "0: No effect.,1: Equivalent to a system reset."
|
|
newline
|
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bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0: No effect.,1: If Master mode is enabled a SMBus Quick Command.."
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0: No effect.,1: The Slave mode is disabled. The shifter and.."
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|
newline
|
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bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0: No effect.,1: Enables the Slave mode (SVDIS must be written to.."
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newline
|
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bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0: No effect.,1: The Master mode is disabled all pending data is.."
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|
newline
|
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bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0: No effect.,1: Enables the Master mode (MSDIS must be written.."
|
|
newline
|
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bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0: No effect.,1: STOP condition is sent just after completing the.."
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|
newline
|
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bitfld.long 0x0 0. "START,Send a START Condition" "0: No effect.,1: A frame beginning with a START bit is.."
|
|
group.long 0x604++0xF
|
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line.long 0x0 "FLEX_TWI_MMR,TWI Master Mode Register"
|
|
bitfld.long 0x0 24. "NOAP,No Auto-Stop On NACK Error" "0: A stop condition is sent automatically upon..,1: No automatic action is performed upon.."
|
|
newline
|
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hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
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|
newline
|
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bitfld.long 0x0 13.--14. "SCLRBL,SCL Rise Boost Level" "0,1,2,3"
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newline
|
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bitfld.long 0x0 12. "MREAD,Master Read Direction" "0: Master write direction.,1: Master read direction."
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|
newline
|
|
bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
|
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line.long 0x4 "FLEX_TWI_SMR,TWI Slave Mode Register"
|
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bitfld.long 0x4 31. "DATAMEN,Data Matching Enable" "0: Data matching on first received data is disabled.,1: Data matching on first received data is enabled."
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newline
|
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bitfld.long 0x4 30. "SADR3EN,Slave Address 3 Enable" "0: Slave address 3 matching is disabled.,1: Slave address 3 matching is enabled."
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newline
|
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bitfld.long 0x4 29. "SADR2EN,Slave Address 2 Enable" "0: Slave address 2 matching is disabled.,1: Slave address 2 matching is enabled."
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newline
|
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bitfld.long 0x4 28. "SADR1EN,Slave Address 1 Enable" "0: Slave address 1 matching is disabled.,1: Slave address 1 matching is enabled."
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newline
|
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hexmask.long.byte 0x4 16.--22. 1. "SADR,Slave Address"
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newline
|
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hexmask.long.byte 0x4 8.--14. 1. "MASK,Slave Address Mask"
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newline
|
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bitfld.long 0x4 7. "SNIFF,Slave Sniffer Mode" "0: Slave Sniffer mode is disabled.,1: Slave Sniffer mode is enabled."
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|
newline
|
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bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0: No effect.,1: Clock stretching disabled in Slave mode OVRE and.."
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|
newline
|
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bitfld.long 0x4 5. "BSEL,TWI Bus Selection" "0: TWI analyzes the TWCK and TWD pins from its TWI..,1: TWI analyzes the TWCK pins TWD from consecutive.."
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newline
|
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bitfld.long 0x4 4. "SADAT,Slave Address Treated as Data" "0: Slave address is handled normally (will not trig..,1: Slave address is handled as data field RXRDY.."
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newline
|
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bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0: Acknowledge of the SMBus Host Header disabled.,1: Acknowledge of the SMBus Host Header enabled."
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|
newline
|
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bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0: Acknowledge of the SMBus Default Address disabled.,1: Acknowledge of the SMBus Default Address enabled."
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newline
|
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bitfld.long 0x4 0. "NACKEN,Slave Receiver Data Phase NACK Enable" "0: Normal value to be returned in the ACK cycle of..,1: NACK value to be returned in the ACK cycle of.."
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|
line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
|
|
line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
hexmask.long.byte 0xC 24.--29. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
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|
newline
|
|
bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
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bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
newline
|
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hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
|
|
newline
|
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hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0: No repeated start has been detected since last..,1: At least one repeated start has been detected.."
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|
newline
|
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bitfld.long 0x0 25. "SDA,SDA Line Value" "0: SDA line sampled value is '0'.,1: SDA line sampled value is '1'."
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|
newline
|
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bitfld.long 0x0 24. "SCL,SCL Line Value" "0: SCL line sampled value is '0'.,1: SCL line sampled value is '1.'"
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|
newline
|
|
bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0: The TWI is not locked.,1: The TWI is locked due to frame errors (see.."
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|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0: No SMBus Host Header Address received.,1: A SMBus Host Header Address was received."
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|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0: No SMBus Default Address received.,1: A SMBus Default Address was received."
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|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0: No SMBus PEC error occurred.,1: A SMBus PEC error occurred."
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|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0: No SMBus timeout occurred.,1: SMBus timeout occurred."
|
|
newline
|
|
bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag" "0: No SMBus slave drives the SMBALERT line.,1: At least one SMBus slave drives the SMBALERT line."
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|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0: No master code has been received.,1: A master code has been received."
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|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0: A slave access is being performing.,1: The Slave Access is finished. End Of Slave.."
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|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0: The clock is not stretched.,1: The clock is stretched. FLEX_TWI_THR /.."
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|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0: Arbitration won.,1: Arbitration lost. Another master of the TWI bus.."
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0: Each data byte has been correctly received by..,1: In Read mode a data byte has not been.."
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|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0: FLEX_TWI_THR has been filled on time.,1: FLEX_TWI_THR has not been filled on time."
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0: FLEX_TWI_RHR has not been loaded while RXRDY was..,1: FLEX_TWI_RHR has been loaded while RXRDY was.."
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|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0: No general call has been detected.,1: A general call has been detected. After the.."
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|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0: TWI is not addressed. SVACC is automatically..,1: Indicates that the address decoding sequence has.."
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0: Indicates that a write access is performed by a..,1: Indicates that a read access is performed by a.."
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0: Transmit FIFO is full and cannot accept more data,1: Transmit FIFO is not full; one or more data can.."
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|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0: Receive FIFO is empty; no data to read,1: At least one unread data is in the Receive FIFO"
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|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0: As soon as a Start is detected.,1: After a Stop or a Repeated Start + an address.."
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0: No repeated start has been detected since last..,1: At least one repeated start has been detected.."
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0: SDA line sampled value is '0'.,1: SDA line sampled value is '1'."
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0: SCL line sampled value is '0'.,1: SCL line sampled value is '1.'"
|
|
newline
|
|
bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0: The Transmit FIFO is not locked.,1: The Transmit FIFO is locked."
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0: No SMBus Host Header Address received.,1: A SMBus Host Header Address was received."
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0: No SMBus Default Address received.,1: A SMBus Default Address was received."
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0: No SMBus PEC error occurred.,1: A SMBus PEC error occurred."
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0: No SMBus timeout occurred.,1: SMBus timeout occurred."
|
|
newline
|
|
bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag" "0: No SMBus slave drives the SMBALERT line.,1: At least one SMBus slave drives the SMBALERT line."
|
|
newline
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0: No master code has been received.,1: A master code has been received."
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0: A slave access is being performing.,1: The Slave Access is finished. End Of Slave.."
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bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0: The clock is not stretched.,1: The clock is stretched. FLEX_TWI_THR /.."
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0: Arbitration won.,1: Arbitration lost. Another master of the TWI bus.."
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bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0: Each data byte has been correctly received by..,1: In Read mode a data byte has not been.."
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bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0: FLEX_TWI_THR has been filled on time.,1: FLEX_TWI_THR has not been filled on time."
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bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0: FLEX_TWI_RHR has not been loaded while RXRDY was..,1: FLEX_TWI_RHR has been loaded while RXRDY was.."
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bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0: No general call has been detected.,1: A general call has been detected. After the.."
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bitfld.long 0x0 4. "SVACC,Slave Access" "0: TWI is not addressed. SVACC is automatically..,1: Indicates that the address decoding sequence has.."
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bitfld.long 0x0 3. "SVREAD,Slave Read" "0: Indicates that a write access is performed by a..,1: Indicates that a read access is performed by a.."
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0: Transmit FIFO is full and cannot accept more data.,1: Transmit FIFO is not full; one or more data can.."
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0: Receive FIFO is empty; no data to read.,1: At least one unread data is in the Receive FIFO."
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0: As soon as a Start is detected.,1: After a Stop or a Repeated Start + an address.."
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wgroup.long 0x624++0x7
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line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
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bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
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bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Enable" "0,1"
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bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
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bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
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bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
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bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Enable" "0,1"
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bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
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bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
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bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
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bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
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bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
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bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
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bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
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bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
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bitfld.long 0x4 16. "MCACK,Master Code Acknowledge Interrupt Disable" "0,1"
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bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
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bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
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bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
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bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
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bitfld.long 0x4 11. "EOSACC,End Of Slave Access Interrupt Disable" "0,1"
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bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
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bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
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bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
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bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
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bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
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bitfld.long 0x4 4. "SVACC,Slave Access Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
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rgroup.long 0x62C++0x7
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line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
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bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
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bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
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bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Mask" "0,1"
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bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
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bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
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bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
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bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Mask" "0,1"
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bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
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bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
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bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
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bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Mask" "0,1"
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
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bitfld.long 0x4 11.--12. "ASTATE,Acknowledge State (Slave Sniffer Mode only)" "0: No Acknowledge or Nacknowledge detected after..,1: Acknowledge (A) detected after previously logged..,2: Nacknowledge (NA) detected after previously..,3: Not defined"
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bitfld.long 0x4 10. "PSTATE,Stop State (Slave Sniffer Mode only)" "0: No STOP (P) detected after previous logged data.,1: Stop detected (P) after previous logged data."
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bitfld.long 0x4 8.--9. "SSTATE,Start State (Slave Sniffer Mode only)" "0: No START detected with the logged data,1: START (S) detected with the logged data,2: Repeated START (Sr) detected with the logged data,3: Not defined"
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hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Master or Slave Receive Holding Data"
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rgroup.long 0x630++0x3
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line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Master or Slave Receive Holding Data 3"
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hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Master or Slave Receive Holding Data 2"
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hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Master or Slave Receive Holding Data 1"
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hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Master or Slave Receive Holding Data 0"
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wgroup.long 0x634++0x3
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line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Master or Slave Transmit Holding Data"
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wgroup.long 0x634++0x3
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line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Master or Slave Transmit Holding Data 3"
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hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Master or Slave Transmit Holding Data 2"
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hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Master or Slave Transmit Holding Data 1"
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Master or Slave Transmit Holding Data 0"
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group.long 0x638++0x1B
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line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
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hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
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hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Master Clock Stretch Maximum Cycles"
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hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Slave Clock Stretch Maximum Cycles"
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hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
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line.long 0x4 "FLEX_TWI_HSR,TWI High Speed Register"
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hexmask.long.byte 0x4 0.--7. 1. "MCODE,TWI High Speed Master Code"
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line.long 0x8 "FLEX_TWI_ACR,TWI Alternative Command Register"
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bitfld.long 0x8 25. "NPEC,Next PEC Request (SMBus Mode only)" "0: The next transfer does not use a PEC byte.,1: The next transfer uses a PEC byte."
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bitfld.long 0x8 24. "NDIR,Next Transfer Direction" "0: Write direction.,1: Read direction."
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hexmask.long.byte 0x8 16.--23. 1. "NDATAL,Next Data Length"
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bitfld.long 0x8 9. "PEC,PEC Request (SMBus Mode only)" "0: The transfer does not use a PEC byte.,1: The transfer uses a PEC byte."
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bitfld.long 0x8 8. "DIR,Transfer Direction" "0: Write direction.,1: Read direction."
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hexmask.long.byte 0x8 0.--7. 1. "DATAL,Data Length"
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line.long 0xC "FLEX_TWI_FILTR,TWI Filter Register"
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bitfld.long 0xC 8.--10. "THRES,Digital Filter Threshold" "0: No filtering applied on TWI inputs.,?,?,?,?,?,?,?"
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bitfld.long 0xC 1. "PADFEN,PAD Filter Enable" "0: PAD analog filter is disabled.,1: PAD analog filter is enabled. (The analog filter.."
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bitfld.long 0xC 0. "FILT,RX Digital Filter" "0: No filtering applied on TWI inputs.,1: TWI input filtering is active. (Only in Standard.."
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line.long 0x10 "FLEX_TWI_HSCWGR,TWI High Speed Clock Waveform Generator Register"
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bitfld.long 0x10 16.--18. "HSCKDIV,High Speed Clock Divider" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x10 8.--15. 1. "HSCHDIV,High Speed Clock High Divider"
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hexmask.long.byte 0x10 0.--7. 1. "HSCLDIV,High Speed Clock Low Divider"
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line.long 0x14 "FLEX_TWI_SWMR,TWI Matching Register"
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hexmask.long.byte 0x14 24.--31. 1. "DATAM,Data Match"
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hexmask.long.byte 0x14 16.--22. 1. "SADR3,Slave Address 3"
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hexmask.long.byte 0x14 8.--14. 1. "SADR2,Slave Address 2"
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hexmask.long.byte 0x14 0.--6. 1. "SADR1,Slave Address 1"
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line.long 0x18 "FLEX_TWI_FMR,TWI FIFO Mode Register"
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hexmask.long.byte 0x18 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
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hexmask.long.byte 0x18 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
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bitfld.long 0x18 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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bitfld.long 0x18 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x654++0x3
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line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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rgroup.long 0x660++0x3
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line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
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bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0: No Receive FIFO pointer occurred,1: Receive FIFO pointer error occurred. Receiver.."
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bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0: No Transmit FIFO pointer occurred,1: Transmit FIFO pointer error occurred."
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bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0: Number of unread data in Receive FIFO is below..,1: Number of unread data in Receive FIFO has.."
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bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0: Receive FIFO is not empty.,1: Receive FIFO has been filled since the last read.."
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bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0: Receive FIFO is not empty.,1: Receive FIFO has been emptied since the last.."
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bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0: Number of data in Transmit FIFO is above..,1: Number of data in Transmit FIFO has reached.."
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bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0: Transmit FIFO is not full.,1: Transmit FIFO has been filled since the last.."
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bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0: Transmit FIFO is not empty.,1: Transmit FIFO has been emptied since the last.."
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wgroup.long 0x664++0x7
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line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
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rgroup.long 0x66C++0x3
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line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
|
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
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group.long 0x6E4++0x3
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line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
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|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
|
|
rgroup.long 0x6E8++0x3
|
|
line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protect Violation Status" "0: No Write Protection Violation has occurred since..,1: A Write Protection Violation has occurred since.."
|
|
tree.end
|
|
tree.end
|
|
tree "GMAC (Ethernet MAC)"
|
|
base ad:0x0
|
|
tree "GMAC0"
|
|
base ad:0xE2800000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "NCR,Network Control Register"
|
|
bitfld.long 0x0 30. "IFGQAVCRED,IFG Eats QAV Credit" "0,1"
|
|
bitfld.long 0x0 28. "MIIONRGMII," "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "OSSCORR,OSS Correction Field" "0: MII on RGMII is not used.,1: MII operations are used on RGMII physical.."
|
|
bitfld.long 0x0 26. "EXTSELRQEN,External Selection of Receive Queue Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "PFCCTL,Multiple PFC Pause quantum Enable" "0: Disables multiple PFC pause quantums.,1: Enables multiple PFC pause quantums one per.."
|
|
bitfld.long 0x0 24. "OSSMODE,One Step Sync Mode" "0: 1588 One Step Sync Mode is disabled.,1: 1588 One Step Sync Mode is enabled. Replaces.."
|
|
newline
|
|
bitfld.long 0x0 22. "STUDPOFFSET,Store UDP Offset" "0: Normal operations.,1: The upper 16 bits of the CRC of every received.."
|
|
bitfld.long 0x0 20. "PTPUNIENA,Detection of Unicast PTP Frames Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TXLPIEN,Enable LPI Transmission" "0,1"
|
|
bitfld.long 0x0 18. "FNP,Flush Next Packet" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "TXPBPF,Transmit PFC Priority-based Pause Frame" "0,1"
|
|
bitfld.long 0x0 16. "ENPBPR,Enable PFC Priority-based Pause Reception" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "SRTSM,Store Receive Timestamp to Memory" "0: Normal operation.,1: Causes the CRC of every received frame to be.."
|
|
bitfld.long 0x0 12. "TXZQPF,Transmit Zero Quantum Pause Frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TXPF,Transmit Pause Frame" "0,1"
|
|
bitfld.long 0x0 10. "THALT,Transmit Halt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TSTART,Start Transmission" "0,1"
|
|
bitfld.long 0x0 8. "BP,Back pressure" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "WESTAT,Write Enable for Statistics Registers" "0,1"
|
|
bitfld.long 0x0 6. "INCSTAT,Increment Statistics Registers" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CLRSTAT,Clear Statistics Registers" "0,1"
|
|
bitfld.long 0x0 4. "MPE,Management Port Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TXEN,Transmit Enable" "0,1"
|
|
bitfld.long 0x0 2. "RXEN,Receive Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LBL,Loop Back Local" "0,1"
|
|
line.long 0x4 "NCFGR,Network Configuration Register"
|
|
bitfld.long 0x4 30. "IRXER,Ignore IPG GRXER" "0,1"
|
|
bitfld.long 0x4 29. "RXBP,Receive Bad Preamble" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "IPGSEN,IP Stretch Enable" "0,1"
|
|
bitfld.long 0x4 26. "IRXFCS,Ignore RX FCS" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "EFRHD,Enable Frames Received in Half Duplex" "0,1"
|
|
bitfld.long 0x4 24. "RXCOEN,Receive Checksum Offload Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "DCPF,Disable Copy of Pause Frames" "0,1"
|
|
bitfld.long 0x4 21.--22. "DBW,Data Bus Width" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 18.--20. "CLK,MDC CLock Division" "0: MCK divided by 8 (MCK up to 20 MHz),1: MCK divided by 16 (MCK up to 40 MHz),2: MCK divided by 32 (MCK up to 80 MHz),3: MCK divided by 48 (MCK up to 120 MHz),4: MCK divided by 64 (MCK up to 160 MHz),5: MCK divided by 96 (MCK up to 240 MHz),?,?"
|
|
bitfld.long 0x4 17. "RFCS,Remove FCS" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "LFERD,Length Field Error Frame Discard" "0,1"
|
|
bitfld.long 0x4 14.--15. "RXBUFO,Receive Buffer Offset" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 13. "PEN,Pause Enable" "0,1"
|
|
bitfld.long 0x4 12. "RTY,Retry Test" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "GBE,Gigabit Mode Enable" "0: 10/100 operation using MII interface.,1: Gigabit operation using GMII interface."
|
|
bitfld.long 0x4 8. "MAXFS,1536 Maximum Frame Size" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "UNIHEN,Unicast Hash Enable" "0,1"
|
|
bitfld.long 0x4 6. "MTIHEN,Multicast Hash Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "NBC,No Broadcast" "0,1"
|
|
bitfld.long 0x4 4. "CAF,Copy All Frames" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "JFRAME,Jumbo Frame Size" "0,1"
|
|
bitfld.long 0x4 2. "DNVLAN,Discard Non-VLAN FRAMES" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "FD,Full Duplex" "0,1"
|
|
bitfld.long 0x4 0. "SPD,Speed" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "NSR,Network Status Register"
|
|
bitfld.long 0x0 7. "RXLPIS,LPI Indication" "0,1"
|
|
bitfld.long 0x0 6. "PFCPAUSN,PFC Pause Negotiated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "IDLE,PHY Management Logic Idle" "0,1"
|
|
bitfld.long 0x0 1. "MDIO,MDIO Input Status" "0,1"
|
|
group.long 0xC++0x17
|
|
line.long 0x0 "UR,User Register"
|
|
bitfld.long 0x0 6. "HDFLCTLEN,Half Duplex Flow Control Enable" "0: Half duplex flow control is disabled.,1: Half duplex flow control is enabled."
|
|
bitfld.long 0x0 2. "REFCLK,Reference Clock Selection" "0: GCLK is selected.,1: External PIO input selected."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "MIM,Media Interface Mode" "0: MII mode is selected.,1: RMII mode is selected.,2: RGMII mode is selected.,?"
|
|
line.long 0x4 "DCFGR,DMA Configuration Register"
|
|
bitfld.long 0x4 29. "TXBD_EXTENDED,Transmit Buffer Descriptor Extended Mode" "0: Disables Transmit Buffer Data Extended mode.,1: Enables Transmit Buffer Data Extended mode. See.."
|
|
bitfld.long 0x4 28. "RXBD_EXTENDED,Receive Buffer Descriptor Extended Mode" "0: Disables Transmit Buffer Data Extended mode.,1: Enables Transmit Buffer Data Extended mode. See.."
|
|
newline
|
|
bitfld.long 0x4 24. "DDRP,DMA Discard Receive Packets" "0,1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "DRBS,DMA Receive Buffer Size"
|
|
newline
|
|
bitfld.long 0x4 13. "CRCERRREP,CRC Errors Report" "0: Bit 16 of the receive buffer descriptor..,1: Bit 16 of the receive buffer descriptor.."
|
|
bitfld.long 0x4 12. "INFLASTEN,Infinite Size for Last Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "TXCOEN,Transmitter Checksum Generation Offload Enable" "0,1"
|
|
bitfld.long 0x4 10. "TXPBMS,Transmitter Packet Buffer Memory Size Select" "0: Do not use top address bit (2 Kbytes).,1: Use full configured addressable space (4 Kbytes)."
|
|
newline
|
|
bitfld.long 0x4 8.--9. "RXBMS,Receiver Packet Buffer Memory Size Select" "0: 4/8 Kbyte Memory Size,1: 4/4 Kbytes Memory Size,2: 4/2 Kbytes Memory Size,3: 4 Kbytes Memory Size"
|
|
bitfld.long 0x4 7. "ESPA,Endian Swap Mode Enable for Packet Data Accesses" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "ESMA,Endian Swap Mode Enable for Management Descriptor Accesses" "0,1"
|
|
hexmask.long.byte 0x4 0.--4. 1. "FBLDO,Fixed Burst Length for DMA Data Operations:"
|
|
line.long 0x8 "TSR,Transmit Status Register"
|
|
bitfld.long 0x8 8. "HRESP,HRESP Not OK" "0,1"
|
|
bitfld.long 0x8 7. "LCO,Late Collision Occurred" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "TXCOMP,Transmit Complete" "0,1"
|
|
bitfld.long 0x8 4. "TFC,Transmit Frame Corruption Due to AHB Error" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "TXGO,Transmit Go" "0,1"
|
|
bitfld.long 0x8 2. "RLE,Retry Limit Exceeded" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "COL,Collision Occurred" "0,1"
|
|
bitfld.long 0x8 0. "UBR,Used Bit Read" "0,1"
|
|
line.long 0xC "RBQB,Receive Buffer Queue Base Address Register"
|
|
hexmask.long 0xC 2.--31. 1. "ADDR,Receive Buffer Queue Base Address"
|
|
bitfld.long 0xC 0. "RXQDIS,Receive Queue Disable" "0: Queue is enabled,1: Queue is disabled. Used to reduce the number of.."
|
|
line.long 0x10 "TBQB,Transmit Buffer Queue Base Address Register"
|
|
hexmask.long 0x10 2.--31. 1. "ADDR,Transmit Buffer Queue Base Address"
|
|
bitfld.long 0x10 0. "TXQDIS," "0,1"
|
|
line.long 0x14 "RSR,Receive Status Register"
|
|
bitfld.long 0x14 3. "HNO,HRESP Not OK" "0,1"
|
|
bitfld.long 0x14 2. "RXOVR,Receive Overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "REC,Frame Received" "0,1"
|
|
bitfld.long 0x14 0. "BNA,Buffer Not Available" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x0 29. "TSUTIMCOMP,TSU Timer Comparison" "0,1"
|
|
bitfld.long 0x0 28. "WOL,Wake On LAN" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXLPISBC,Receive LPI indication Status Bit Change" "0,1"
|
|
bitfld.long 0x0 26. "SRI,TSU Seconds Register Increment" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "PDRSFT,PDelay Response Frame Transmitted" "0,1"
|
|
bitfld.long 0x0 24. "PDRQFT,PDelay Request Frame Transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "PDRSFR,PDelay Response Frame Received" "0,1"
|
|
bitfld.long 0x0 22. "PDRQFR,PDelay Request Frame Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SFT,PTP Sync Frame Transmitted" "0,1"
|
|
bitfld.long 0x0 20. "DRQFT,PTP Delay Request Frame Transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "SFR,PTP Sync Frame Received" "0,1"
|
|
bitfld.long 0x0 18. "DRQFR,PTP Delay Request Frame Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PFTR,Pause Frame Transmitted" "0,1"
|
|
bitfld.long 0x0 13. "PTZ,Pause Time Zero" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PFNZ,Pause Frame with Non-zero Pause Quantum Received" "0,1"
|
|
bitfld.long 0x0 11. "HRESP,HRESP Not OK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ROVR,Receive Overrun" "0,1"
|
|
bitfld.long 0x0 7. "TCOMP,Transmit Complete" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TFC,Transmit Frame Corruption Due to AHB Error" "0,1"
|
|
bitfld.long 0x0 5. "RLEX,Retry Limit Exceeded or Late Collision" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TUR,Transmit Underrun" "0,1"
|
|
bitfld.long 0x0 3. "TXUBR,TX Used Bit Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXUBR,RX Used Bit Read" "0,1"
|
|
bitfld.long 0x0 1. "RCOMP,Receive Complete" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MFS,Management Frame Sent" "0,1"
|
|
wgroup.long 0x28++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 29. "TSUTIMCOMP,TSU Timer Comparison" "0,1"
|
|
bitfld.long 0x0 28. "WOL,Wake On LAN" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXLPISBC,Enable RX LPI Indication" "0,1"
|
|
bitfld.long 0x0 26. "SRI,TSU Seconds Register Increment" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "PDRSFT,PDelay Response Frame Transmitted" "0,1"
|
|
bitfld.long 0x0 24. "PDRQFT,PDelay Request Frame Transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "PDRSFR,PDelay Response Frame Received" "0,1"
|
|
bitfld.long 0x0 22. "PDRQFR,PDelay Request Frame Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SFT,PTP Sync Frame Transmitted" "0,1"
|
|
bitfld.long 0x0 20. "DRQFT,PTP Delay Request Frame Transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "SFR,PTP Sync Frame Received" "0,1"
|
|
bitfld.long 0x0 18. "DRQFR,PTP Delay Request Frame Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "EXINT,External Interrupt" "0,1"
|
|
bitfld.long 0x0 14. "PFTR,Pause Frame Transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PTZ,Pause Time Zero" "0,1"
|
|
bitfld.long 0x0 12. "PFNZ,Pause Frame with Non-zero Pause Quantum Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "HRESP,HRESP Not OK" "0,1"
|
|
bitfld.long 0x0 10. "ROVR,Receive Overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TCOMP,Transmit Complete" "0,1"
|
|
bitfld.long 0x0 6. "TFC,Transmit Frame Corruption Due to AHB Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RLEX,Retry Limit Exceeded or Late Collision" "0,1"
|
|
bitfld.long 0x0 4. "TUR,Transmit Underrun" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TXUBR,TX Used Bit Read" "0,1"
|
|
bitfld.long 0x0 2. "RXUBR,RX Used Bit Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RCOMP,Receive Complete" "0,1"
|
|
bitfld.long 0x0 0. "MFS,Management Frame Sent" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 29. "TSUTIMCOMP,TSU Timer Comparison" "0,1"
|
|
bitfld.long 0x4 28. "WOL,Wake On LAN" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "RXLPISBC,Enable RX LPI Indication" "0,1"
|
|
bitfld.long 0x4 26. "SRI,TSU Seconds Register Increment" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "PDRSFT,PDelay Response Frame Transmitted" "0,1"
|
|
bitfld.long 0x4 24. "PDRQFT,PDelay Request Frame Transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "PDRSFR,PDelay Response Frame Received" "0,1"
|
|
bitfld.long 0x4 22. "PDRQFR,PDelay Request Frame Received" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "SFT,PTP Sync Frame Transmitted" "0,1"
|
|
bitfld.long 0x4 20. "DRQFT,PTP Delay Request Frame Transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "SFR,PTP Sync Frame Received" "0,1"
|
|
bitfld.long 0x4 18. "DRQFR,PTP Delay Request Frame Received" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "EXINT,External Interrupt" "0,1"
|
|
bitfld.long 0x4 14. "PFTR,Pause Frame Transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "PTZ,Pause Time Zero" "0,1"
|
|
bitfld.long 0x4 12. "PFNZ,Pause Frame with Non-zero Pause Quantum Received" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "HRESP,HRESP Not OK" "0,1"
|
|
bitfld.long 0x4 10. "ROVR,Receive Overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "TCOMP,Transmit Complete" "0,1"
|
|
bitfld.long 0x4 6. "TFC,Transmit Frame Corruption Due to AHB Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RLEX,Retry Limit Exceeded or Late Collision" "0,1"
|
|
bitfld.long 0x4 4. "TUR,Transmit Underrun" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "TXUBR,TX Used Bit Read" "0,1"
|
|
bitfld.long 0x4 2. "RXUBR,RX Used Bit Read" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RCOMP,Receive Complete" "0,1"
|
|
bitfld.long 0x4 0. "MFS,Management Frame Sent" "0,1"
|
|
group.long 0x30++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 29. "TSUTIMCOMP,TSU Timer Comparison" "0,1"
|
|
bitfld.long 0x0 28. "WOL,Wake On LAN" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXLPISBC,Enable RX LPI Indication" "0,1"
|
|
bitfld.long 0x0 26. "SRI,TSU Seconds Register Increment" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "PDRSFT,PDelay Response Frame Transmitted" "0,1"
|
|
bitfld.long 0x0 24. "PDRQFT,PDelay Request Frame Transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "PDRSFR,PDelay Response Frame Received" "0,1"
|
|
bitfld.long 0x0 22. "PDRQFR,PDelay Request Frame Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SFT,PTP Sync Frame Transmitted" "0,1"
|
|
bitfld.long 0x0 20. "DRQFT,PTP Delay Request Frame Transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "SFR,PTP Sync Frame Received" "0,1"
|
|
bitfld.long 0x0 18. "DRQFR,PTP Delay Request Frame Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "EXINT,External Interrupt" "0,1"
|
|
bitfld.long 0x0 14. "PFTR,Pause Frame Transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PTZ,Pause Time Zero" "0,1"
|
|
bitfld.long 0x0 12. "PFNZ,Pause Frame with Non-zero Pause Quantum Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "HRESP,HRESP Not OK" "0,1"
|
|
bitfld.long 0x0 10. "ROVR,Receive Overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TCOMP,Transmit Complete" "0,1"
|
|
bitfld.long 0x0 6. "TFC,Transmit Frame Corruption Due to AHB Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RLEX,Retry Limit Exceeded or Late Collision" "0,1"
|
|
bitfld.long 0x0 4. "TUR,Transmit Underrun" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TXUBR,TX Used Bit Read" "0,1"
|
|
bitfld.long 0x0 2. "RXUBR,RX Used Bit Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RCOMP,Receive Complete" "0,1"
|
|
bitfld.long 0x0 0. "MFS,Management Frame Sent" "0,1"
|
|
line.long 0x4 "MAN,PHY Maintenance Register"
|
|
bitfld.long 0x4 31. "WZO,Write ZERO" "0,1"
|
|
bitfld.long 0x4 30. "CLTTO,Clause 22 Operation" "0: Clause 45 operation,1: Clause 22 operation"
|
|
newline
|
|
bitfld.long 0x4 28.--29. "OP,Operation" "?,1: Write,2: Read,?"
|
|
hexmask.long.byte 0x4 23.--27. 1. "PHYA,PHY Address"
|
|
newline
|
|
hexmask.long.byte 0x4 18.--22. 1. "REGA,Register Address"
|
|
bitfld.long 0x4 16.--17. "WTN,Write Ten" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "DATA,PHY Data"
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "RPQ,Received Pause Quantum Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RPQ,Received Pause Quantum"
|
|
group.long 0x3C++0xF
|
|
line.long 0x0 "TPQ,Transmit Pause Quantum Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "P1TPQ,Priority 1 Transmit Pause Quantum"
|
|
hexmask.long.word 0x0 0.--15. 1. "TPQ,Transmit Pause Quantum"
|
|
line.long 0x4 "TPSF,TX Partial Store and Forward Register"
|
|
bitfld.long 0x4 31. "ENTXP,Enable TX Partial Store and Forward Operation" "0,1"
|
|
hexmask.long.word 0x4 0.--11. 1. "TPB1ADR,Transmit Partial Store and Forward Address"
|
|
line.long 0x8 "RPSF,RX Partial Store and Forward Register"
|
|
bitfld.long 0x8 31. "ENRXP,Enable RX Partial Store and Forward Operation" "0,1"
|
|
hexmask.long.word 0x8 0.--10. 1. "RPB1ADR,Receive Partial Store and Forward Address"
|
|
line.long 0xC "RJFML,RX Jumbo Frame Max Length Register"
|
|
hexmask.long.word 0xC 0.--13. 1. "FML,Frame Max Length"
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "AMP,AXI Max Pipeline"
|
|
bitfld.long 0x0 16. "USE_FROM,Use AW to W or to B" "0: Operates between the AW and W channels.,1: Operates between the AW and B channels."
|
|
hexmask.long.byte 0x0 8.--15. 1. "AW2W_MAX_PIPELINE,AW to W Max Pipeline"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "AR2R_MAX_PIPELINE,AR to R Max Pipeline"
|
|
group.long 0x5C++0x7
|
|
line.long 0x0 "INTM,GMAC Interrupt Moderation Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "TXINTMOD,Transmit Interrupt Moderation"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXINTMOD,Receive Interrupt Moderation"
|
|
line.long 0x4 "SYSWT,GMAC System Wake-Up Time Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "SYSWKUPTIME,System Wake-up Time"
|
|
group.long 0x80++0x67
|
|
line.long 0x0 "HRB,Hash Register Bottom"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Hash Address"
|
|
line.long 0x4 "HRT,Hash Register Top"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR,Hash Address"
|
|
line.long 0x8 "SAB1,Specific Address 1 Bottom Register"
|
|
hexmask.long 0x8 0.--31. 1. "ADDR,Specific Address 1"
|
|
line.long 0xC "SAT1,Specific Address 1 Top Register"
|
|
bitfld.long 0xC 16. "FILTSORD,Filter Source or Destination MAC Address" "0: The filter is a destination address filter.,1: The filter is a source address filter."
|
|
hexmask.long.word 0xC 0.--15. 1. "ADDR,Specific Address 1"
|
|
line.long 0x10 "SAB2,Specific Address 2 Bottom Register"
|
|
hexmask.long 0x10 0.--31. 1. "ADDR,Specific Address 2"
|
|
line.long 0x14 "SAT2,Specific Address 2 Top Register"
|
|
hexmask.long.byte 0x14 24.--29. 1. "FILTBMSK,Filter Bytes Mask"
|
|
bitfld.long 0x14 16. "FILTSORD,Filter Source or Destination MAC Address" "0: The filter is a destination address filter.,1: The filter is a source address filter."
|
|
newline
|
|
hexmask.long.word 0x14 0.--15. 1. "ADDR,Specific Address 2"
|
|
line.long 0x18 "SAB3,Specific Address 3 Bottom Register"
|
|
hexmask.long 0x18 0.--31. 1. "ADDR,Specific Address 3"
|
|
line.long 0x1C "SAT3,Specific Address 3 Top Register"
|
|
hexmask.long.byte 0x1C 24.--29. 1. "FILTBMSK,Filter Bytes Mask"
|
|
bitfld.long 0x1C 16. "FILTSORD,Filter Source or Destination MAC Address" "0: The filter is a destination address filter.,1: The filter is a source address filter."
|
|
newline
|
|
hexmask.long.word 0x1C 0.--15. 1. "ADDR,Specific Address 3"
|
|
line.long 0x20 "SAB4,Specific Address 4 Bottom Register"
|
|
hexmask.long 0x20 0.--31. 1. "ADDR,Specific Address 4"
|
|
line.long 0x24 "SAT4,Specific Address 4 Top Register"
|
|
hexmask.long.byte 0x24 24.--29. 1. "FILTBMSK,Filter Bytes Mask"
|
|
bitfld.long 0x24 16. "FILTSORD,Filter Source or Destination MAC Address" "0: The filter is a destination address filter.,1: The filter is a source address filter."
|
|
newline
|
|
hexmask.long.word 0x24 0.--15. 1. "ADDR,Specific Address 4"
|
|
line.long 0x28 "TIDM1,Type ID Match 1 Register"
|
|
bitfld.long 0x28 31. "ENID1,Enable Copying of TID Matched Frames" "0: TID is not part of the comparison match.,1: TID is processed for the comparison match."
|
|
hexmask.long.word 0x28 0.--15. 1. "TID,Type ID Match 1"
|
|
line.long 0x2C "TIDM2,Type ID Match 2 Register"
|
|
bitfld.long 0x2C 31. "ENID2,Enable Copying of TID Matched Frames" "0: TID is not part of the comparison match.,1: TID is processed for the comparison match."
|
|
hexmask.long.word 0x2C 0.--15. 1. "TID,Type ID Match 2"
|
|
line.long 0x30 "TIDM3,Type ID Match 3 Register"
|
|
bitfld.long 0x30 31. "ENID3,Enable Copying of TID Matched Frames" "0: TID is not part of the comparison match.,1: TID is processed for the comparison match."
|
|
hexmask.long.word 0x30 0.--15. 1. "TID,Type ID Match 3"
|
|
line.long 0x34 "TIDM4,Type ID Match 4 Register"
|
|
bitfld.long 0x34 31. "ENID4,Enable Copying of TID Matched Frames" "0: TID is not part of the comparison match.,1: TID is processed for the comparison match."
|
|
hexmask.long.word 0x34 0.--15. 1. "TID,Type ID Match 4"
|
|
line.long 0x38 "WOL,Wake on LAN Register"
|
|
bitfld.long 0x38 19. "MTI,Multicast Hash Event Enable" "0,1"
|
|
bitfld.long 0x38 18. "SA1,Specific Address Register 1 Event Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x38 17. "ARP,ARP Request Event Enable" "0,1"
|
|
bitfld.long 0x38 16. "MAG,Magic Packet Event Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x38 0.--15. 1. "IP,ARP Request IP Address"
|
|
line.long 0x3C "IPGS,IPG Stretch Register"
|
|
hexmask.long.word 0x3C 0.--15. 1. "FL,Frame Length"
|
|
line.long 0x40 "SVLAN,Stacked VLAN Register"
|
|
bitfld.long 0x40 31. "ESVLAN,Enable Stacked VLAN Processing Mode" "0: Disable the stacked VLAN processing mode,1: Enable the stacked VLAN processing mode"
|
|
hexmask.long.word 0x40 0.--15. 1. "VLAN_TYPE,User Defined VLAN_TYPE Field"
|
|
line.long 0x44 "TPFCP,Transmit PFC Pause Register"
|
|
hexmask.long.byte 0x44 8.--15. 1. "PQ,Pause Quantum"
|
|
hexmask.long.byte 0x44 0.--7. 1. "PEV,Priority Enable Vector"
|
|
line.long 0x48 "SAMB1,Specific Address 1 Mask Bottom Register"
|
|
hexmask.long 0x48 0.--31. 1. "ADDR,Specific Address 1 Mask"
|
|
line.long 0x4C "SAMT1,Specific Address 1 Mask Top Register"
|
|
hexmask.long.word 0x4C 0.--15. 1. "ADDR,Specific Address 1 Mask"
|
|
line.long 0x50 "AMRX,AHB Address Mask for RX Data Buffer Accesses Register"
|
|
hexmask.long.byte 0x50 28.--31. 1. "MSBADDR,MSB of the Receive Data Buffer AHB/AXI Address"
|
|
hexmask.long.byte 0x50 0.--3. 1. "MSBADDRMSK,Mask of the Receive Data Buffer AHB/AXI Address"
|
|
line.long 0x54 "RXUDAR,PTP RX Unicast IP Destination Address Register"
|
|
hexmask.long 0x54 0.--31. 1. "RXUDA,Receive Unicast Destination Address"
|
|
line.long 0x58 "TXUDAR,PTP TX Unicast IP Destination Address Register"
|
|
hexmask.long 0x58 0.--31. 1. "TXUDA,Transmit Unicast Destination Address"
|
|
line.long 0x5C "NSC,1588 Timer Nanosecond Comparison Register"
|
|
hexmask.long.tbyte 0x5C 0.--21. 1. "NANOSEC,1588 Timer Nanosecond Comparison Value"
|
|
line.long 0x60 "SCL,1588 Timer Second Comparison Low Register"
|
|
hexmask.long 0x60 0.--31. 1. "SEC,1588 Timer Second Comparison Value"
|
|
line.long 0x64 "SCH,1588 Timer Second Comparison High Register"
|
|
hexmask.long.word 0x64 0.--15. 1. "SEC,1588 Timer Second Comparison Value"
|
|
rgroup.long 0xE8++0xF
|
|
line.long 0x0 "EFTSH,PTP Event Frame Transmitted Seconds High Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RUD,Register Update"
|
|
line.long 0x4 "EFRSH,PTP Event Frame Received Seconds High Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "RUD,Register Update"
|
|
line.long 0x8 "PEFTSH,PTP Peer Event Frame Transmitted Seconds High Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "RUD,Register Update"
|
|
line.long 0xC "PEFRSH,PTP Peer Event Frame Received Seconds High Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "RUD,Register Update"
|
|
rgroup.long 0x100++0xB3
|
|
line.long 0x0 "OTLO,Octets Transmitted Low Register"
|
|
hexmask.long 0x0 0.--31. 1. "TXO,Transmitted Octets"
|
|
line.long 0x4 "OTHI,Octets Transmitted High Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "TXO,Transmitted Octets"
|
|
line.long 0x8 "FT,Frames Transmitted Register"
|
|
hexmask.long 0x8 0.--31. 1. "FTX,Frames Transmitted without Error"
|
|
line.long 0xC "BCFT,Broadcast Frames Transmitted Register"
|
|
hexmask.long 0xC 0.--31. 1. "BFTX,Broadcast Frames Transmitted without Error"
|
|
line.long 0x10 "MFT,Multicast Frames Transmitted Register"
|
|
hexmask.long 0x10 0.--31. 1. "MFTX,Multicast Frames Transmitted without Error"
|
|
line.long 0x14 "PFT,Pause Frames Transmitted Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "PFTX,Pause Frames Transmitted Register"
|
|
line.long 0x18 "BFT64,64 Byte Frames Transmitted Register"
|
|
hexmask.long 0x18 0.--31. 1. "NFTX,64 Byte Frames Transmitted without Error"
|
|
line.long 0x1C "TBFT127,65 to 127 Byte Frames Transmitted Register"
|
|
hexmask.long 0x1C 0.--31. 1. "NFTX,65 to 127 Byte Frames Transmitted without Error"
|
|
line.long 0x20 "TBFT255,128 to 255 Byte Frames Transmitted Register"
|
|
hexmask.long 0x20 0.--31. 1. "NFTX,128 to 255 Byte Frames Transmitted without Error"
|
|
line.long 0x24 "TBFT511,256 to 511 Byte Frames Transmitted Register"
|
|
hexmask.long 0x24 0.--31. 1. "NFTX,256 to 511 Byte Frames Transmitted without Error"
|
|
line.long 0x28 "TBFT1023,512 to 1023 Byte Frames Transmitted Register"
|
|
hexmask.long 0x28 0.--31. 1. "NFTX,512 to 1023 Byte Frames Transmitted without Error"
|
|
line.long 0x2C "TBFT1518,1024 to 1518 Byte Frames Transmitted Register"
|
|
hexmask.long 0x2C 0.--31. 1. "NFTX,1024 to 1518 Byte Frames Transmitted without Error"
|
|
line.long 0x30 "GTBFT1518,Greater Than 1518 Byte Frames Transmitted Register"
|
|
hexmask.long 0x30 0.--31. 1. "NFTX,Greater than 1518 Byte Frames Transmitted without Error"
|
|
line.long 0x34 "TUR,Transmit Underruns Register"
|
|
hexmask.long.word 0x34 0.--9. 1. "TXUNR,Transmit Underruns"
|
|
line.long 0x38 "SCF,Single Collision Frames Register"
|
|
hexmask.long.tbyte 0x38 0.--17. 1. "SCOL,Single Collision"
|
|
line.long 0x3C "MCF,Multiple Collision Frames Register"
|
|
hexmask.long.tbyte 0x3C 0.--17. 1. "MCOL,Multiple Collision"
|
|
line.long 0x40 "EC,Excessive Collisions Register"
|
|
hexmask.long.word 0x40 0.--9. 1. "XCOL,Excessive Collisions"
|
|
line.long 0x44 "LC,Late Collisions Register"
|
|
hexmask.long.word 0x44 0.--9. 1. "LCOL,Late Collisions"
|
|
line.long 0x48 "DTF,Deferred Transmission Frames Register"
|
|
hexmask.long.tbyte 0x48 0.--17. 1. "DEFT,Deferred Transmission"
|
|
line.long 0x4C "CSE,Carrier Sense Errors Register"
|
|
hexmask.long.word 0x4C 0.--9. 1. "CSR,Carrier Sense Error"
|
|
line.long 0x50 "ORLO,Octets Received Low Received Register"
|
|
hexmask.long 0x50 0.--31. 1. "RXO,Received Octets"
|
|
line.long 0x54 "ORHI,Octets Received High Received Register"
|
|
hexmask.long.word 0x54 0.--15. 1. "RXO,Received Octets"
|
|
line.long 0x58 "FR,Frames Received Register"
|
|
hexmask.long 0x58 0.--31. 1. "FRX,Frames Received without Error"
|
|
line.long 0x5C "BCFR,Broadcast Frames Received Register"
|
|
hexmask.long 0x5C 0.--31. 1. "BFRX,Broadcast Frames Received without Error"
|
|
line.long 0x60 "MFR,Multicast Frames Received Register"
|
|
hexmask.long 0x60 0.--31. 1. "MFRX,Multicast Frames Received without Error"
|
|
line.long 0x64 "PFR,Pause Frames Received Register"
|
|
hexmask.long.word 0x64 0.--15. 1. "PFRX,Pause Frames Received Register"
|
|
line.long 0x68 "BFR64,64 Byte Frames Received Register"
|
|
hexmask.long 0x68 0.--31. 1. "NFRX,64 Byte Frames Received without Error"
|
|
line.long 0x6C "TBFR127,65 to 127 Byte Frames Received Register"
|
|
hexmask.long 0x6C 0.--31. 1. "NFRX,65 to 127 Byte Frames Received without Error"
|
|
line.long 0x70 "TBFR255,128 to 255 Byte Frames Received Register"
|
|
hexmask.long 0x70 0.--31. 1. "NFRX,128 to 255 Byte Frames Received without Error"
|
|
line.long 0x74 "TBFR511,256 to 511 Byte Frames Received Register"
|
|
hexmask.long 0x74 0.--31. 1. "NFRX,256 to 511 Byte Frames Received without Error"
|
|
line.long 0x78 "TBFR1023,512 to 1023 Byte Frames Received Register"
|
|
hexmask.long 0x78 0.--31. 1. "NFRX,512 to 1023 Byte Frames Received without Error"
|
|
line.long 0x7C "TBFR1518,1024 to 1518 Byte Frames Received Register"
|
|
hexmask.long 0x7C 0.--31. 1. "NFRX,1024 to 1518 Byte Frames Received without Error"
|
|
line.long 0x80 "TMXBFR,1519 to Maximum Byte Frames Received Register"
|
|
hexmask.long 0x80 0.--31. 1. "NFRX,1519 to Maximum Byte Frames Received without Error"
|
|
line.long 0x84 "UFR,Undersize Frames Received Register"
|
|
hexmask.long.word 0x84 0.--9. 1. "UFRX,Undersize Frames Received"
|
|
line.long 0x88 "OFR,Oversize Frames Received Register"
|
|
hexmask.long.word 0x88 0.--9. 1. "OFRX,Oversized Frames Received"
|
|
line.long 0x8C "JR,Jabbers Received Register"
|
|
hexmask.long.word 0x8C 0.--9. 1. "JRX,Jabbers Received"
|
|
line.long 0x90 "FCSE,Frame Check Sequence Errors Register"
|
|
hexmask.long.word 0x90 0.--9. 1. "FCKR,Frame Check Sequence Errors"
|
|
line.long 0x94 "LFFE,Length Field Frame Errors Register"
|
|
hexmask.long.word 0x94 0.--9. 1. "LFER,Length Field Frame Errors"
|
|
line.long 0x98 "RSE,Receive Symbol Errors Register"
|
|
hexmask.long.word 0x98 0.--9. 1. "RXSE,Receive Symbol Errors"
|
|
line.long 0x9C "AE,Alignment Errors Register"
|
|
hexmask.long.word 0x9C 0.--9. 1. "AER,Alignment Errors"
|
|
line.long 0xA0 "RRE,Receive Resource Errors Register"
|
|
hexmask.long.tbyte 0xA0 0.--17. 1. "RXRER,Receive Resource Errors"
|
|
line.long 0xA4 "ROE,Receive Overrun Register"
|
|
hexmask.long.word 0xA4 0.--9. 1. "RXOVR,Receive Overruns"
|
|
line.long 0xA8 "IHCE,IP Header Checksum Errors Register"
|
|
hexmask.long.byte 0xA8 0.--7. 1. "HCKER,IP Header Checksum Errors"
|
|
line.long 0xAC "TCE,TCP Checksum Errors Register"
|
|
hexmask.long.byte 0xAC 0.--7. 1. "TCKER,TCP Checksum Errors"
|
|
line.long 0xB0 "UCE,UDP Checksum Errors Register"
|
|
hexmask.long.byte 0xB0 0.--7. 1. "UCKER,UDP Checksum Errors"
|
|
group.long 0x1BC++0x7
|
|
line.long 0x0 "TISUBN,1588 Timer Increment Sub-nanoseconds Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "LSBTIR,Lower Significant Bits of Timer Increment Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "MSBTIR,Most Significant Bits of Timer Increment Register"
|
|
line.long 0x4 "TSH,1588 Timer Seconds High Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "TCS,Timer Count in Seconds"
|
|
group.long 0x1D0++0x7
|
|
line.long 0x0 "TSL,1588 Timer Seconds Low Register"
|
|
hexmask.long 0x0 0.--31. 1. "TCS,Timer Count in Seconds"
|
|
line.long 0x4 "TN,1588 Timer Nanoseconds Register"
|
|
hexmask.long 0x4 0.--29. 1. "TNS,Timer Count in Nanoseconds"
|
|
wgroup.long 0x1D8++0x3
|
|
line.long 0x0 "TA,1588 Timer Adjust Register"
|
|
bitfld.long 0x0 31. "ADJ,Adjust 1588 Timer" "0,1"
|
|
hexmask.long 0x0 0.--29. 1. "ITDT,Increment/Decrement"
|
|
group.long 0x1DC++0x3
|
|
line.long 0x0 "TI,1588 Timer Increment Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "NIT,Number of Increments"
|
|
hexmask.long.byte 0x0 8.--15. 1. "ACNS,Alternative Count Nanoseconds"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "CNS,Count Nanoseconds"
|
|
rgroup.long 0x1E0++0x1F
|
|
line.long 0x0 "EFTSL,PTP Event Frame Transmitted Seconds Low Register"
|
|
hexmask.long 0x0 0.--31. 1. "RUD,Register Update"
|
|
line.long 0x4 "EFTN,PTP Event Frame Transmitted Nanoseconds Register"
|
|
hexmask.long 0x4 0.--29. 1. "RUD,Register Update"
|
|
line.long 0x8 "EFRSL,PTP Event Frame Received Seconds Low Register"
|
|
hexmask.long 0x8 0.--31. 1. "RUD,Register Update"
|
|
line.long 0xC "EFRN,PTP Event Frame Received Nanoseconds Register"
|
|
hexmask.long 0xC 0.--29. 1. "RUD,Register Update"
|
|
line.long 0x10 "PEFTSL,PTP Peer Event Frame Transmitted Seconds Low Register"
|
|
hexmask.long 0x10 0.--31. 1. "RUD,Register Update"
|
|
line.long 0x14 "PEFTN,PTP Peer Event Frame Transmitted Nanoseconds Register"
|
|
hexmask.long 0x14 0.--29. 1. "RUD,Register Update"
|
|
line.long 0x18 "PEFRSL,PTP Peer Event Frame Received Seconds Low Register"
|
|
hexmask.long 0x18 0.--31. 1. "RUD,Register Update"
|
|
line.long 0x1C "PEFRN,PTP Peer Event Frame Received Nanoseconds Register"
|
|
hexmask.long 0x1C 0.--29. 1. "RUD,Register Update"
|
|
group.long 0x260++0xB
|
|
line.long 0x0 "TXPQUANT1,GMAC Transmit Pause Quantum 1 Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "QUANT_P3,Transmit Pause Quantum for Priority 3"
|
|
hexmask.long.word 0x0 0.--15. 1. "QUANT_P2,Transmit Pause Quantum for Priority 2"
|
|
line.long 0x4 "TXPQUANT2,GMAC Transmit Pause Quantum 2 Register"
|
|
hexmask.long.word 0x4 16.--31. 1. "QUANT_P5,Transmit Pause Quantum for Priority 5"
|
|
hexmask.long.word 0x4 0.--15. 1. "QUANT_P4,Transmit Pause Quantum for Priority 4"
|
|
line.long 0x8 "TXPQUANT3,GMAC Transmit Pause Quantum 3 Register"
|
|
hexmask.long.word 0x8 16.--31. 1. "QUANT_P7,Transmit Pause Quantum for Priority 7"
|
|
hexmask.long.word 0x8 0.--15. 1. "QUANT_P6,Transmit Pause Quantum for Priority 6"
|
|
rgroup.long 0x270++0xF
|
|
line.long 0x0 "RXLPI,Received LPI Transitions"
|
|
hexmask.long.word 0x0 0.--15. 1. "COUNT,Count of RX LPI transitions (cleared on read)"
|
|
line.long 0x4 "RXLPITIME,Received LPI Time"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "LPITIME,Time in LPI (cleared on read)"
|
|
line.long 0x8 "TXLPI,Transmit LPI Transitions"
|
|
hexmask.long.word 0x8 0.--15. 1. "COUNT,Count of LPI transitions (cleared on read)"
|
|
line.long 0xC "TXLPITIME,Transmit LPI Time"
|
|
hexmask.long.tbyte 0xC 0.--23. 1. "LPITIME,Time in LPI (cleared on read)"
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x400)++0x3
|
|
line.long 0x0 "ISRPQ[$1],Interrupt Status Register Priority Queue (index = 1)"
|
|
bitfld.long 0x0 11. "HRESP,HRESP Not OK" "0,1"
|
|
bitfld.long 0x0 10. "ROVR,Receive Overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TCOMP,Transmit Complete" "0,1"
|
|
bitfld.long 0x0 6. "TFC,Transmit Frame Corruption Due to AHB Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RLEX,Retry Limit Exceeded or Late Collision" "0,1"
|
|
bitfld.long 0x0 2. "RXUBR,RX Used Bit Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RCOMP,Receive Complete" "0,1"
|
|
repeat.end
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x440)++0x3
|
|
line.long 0x0 "TBQBAPQ[$1],Transmit Buffer Queue Base Address Register Priority Queue (index = 1)"
|
|
hexmask.long 0x0 2.--31. 1. "TXBQBA,Transmit Buffer Queue Base Address"
|
|
repeat.end
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x480)++0x3
|
|
line.long 0x0 "RBQBAPQ[$1],Receive Buffer Queue Base Address Register Priority Queue (index = 1)"
|
|
hexmask.long 0x0 2.--31. 1. "RXBQBA,Receive Buffer Queue Base Address"
|
|
repeat.end
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x4A0)++0x3
|
|
line.long 0x0 "RBSRPQ[$1],Receive Buffer Size Register Priority Queue (index = 1)"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RBS,Receive Buffer Size"
|
|
repeat.end
|
|
group.long 0x4BC++0x1B
|
|
line.long 0x0 "CBSCR,Credit-Based Shaping Control Register"
|
|
bitfld.long 0x0 1. "QAE,Queue A CBS Enable" "0: Credit-based shaping on the second highest..,1: Credit-based shaping on the second highest.."
|
|
bitfld.long 0x0 0. "QBE,Queue B CBS Enable" "0: Credit-based shaping on the highest priority..,1: Credit-based shaping on the highest priority.."
|
|
line.long 0x4 "CBSISQA,Credit-Based Shaping IdleSlope Register for Queue A"
|
|
hexmask.long 0x4 0.--31. 1. "IS,IdleSlope"
|
|
line.long 0x8 "CBSISQB,Credit-Based Shaping IdleSlope Register for Queue B"
|
|
hexmask.long 0x8 0.--31. 1. "IS,IdleSlope"
|
|
line.long 0xC "TQUBA,Transmit Queue Upper Base Address Register"
|
|
hexmask.long 0xC 0.--31. 1. "TQUBA,Transmit Queue Upper Base Address"
|
|
line.long 0x10 "TXBDCTRL,Transmit BD Control Register"
|
|
bitfld.long 0x10 4.--5. "TSMODE,TX Descriptor Timestamp Insertion Mode" "0: TS insertion disable,1: TS inserted for PTP Event Frames only,2: TS inserted for All PTP Frames only,3: TS insertion for All Frames"
|
|
line.long 0x14 "RXBDCTRL,Receive BD Control Register"
|
|
bitfld.long 0x14 4.--5. "TSMODE,RX Descriptor Timestamp Insertion Mode" "0: TS insertion disable,1: TS inserted for PTP Event Frames only,2: TS inserted for All PTP Frames only,3: TS insertion for All Frames"
|
|
line.long 0x18 "RQUBA,Receive Queue Upper Base Address Register"
|
|
hexmask.long 0x18 0.--31. 1. "RQUBA,Receive Queue Upper Base Address"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x500)++0x3
|
|
line.long 0x0 "ST1RPQ[$1],Screening Type 1 Register Priority Queue (index = 0)"
|
|
bitfld.long 0x0 29. "UDPE,UDP Port Match Enable" "0,1"
|
|
bitfld.long 0x0 28. "DSTCE,Differentiated Services or Traffic Class Match Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 12.--27. 1. "UDPM,UDP Port Match"
|
|
hexmask.long.byte 0x0 4.--11. 1. "DSTCM,Differentiated Services or Traffic Class Match"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "QNB,Queue Number (0-5)" "0,1,2,3,4,5,6,7"
|
|
repeat.end
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x540)++0x3
|
|
line.long 0x0 "ST2RPQ[$1],Screening Type 2 Register Priority Queue (index = 0)"
|
|
bitfld.long 0x0 30. "COMPCE,Compare C Enable" "0: Comparison via the register designated by index..,1: Comparison via the register designated by index.."
|
|
hexmask.long.byte 0x0 25.--29. 1. "COMPC,Index of Screening Type 2 Compare Word 0/Word 1 register"
|
|
newline
|
|
bitfld.long 0x0 24. "COMPBE,Compare B Enable" "0: Comparison via the register designated by index..,1: Comparison via the register designated by index.."
|
|
hexmask.long.byte 0x0 19.--23. 1. "COMPB,Index of Screening Type 2 Compare Word 0/Word 1 register"
|
|
newline
|
|
bitfld.long 0x0 18. "COMPAE,Compare A Enable" "0: Comparison via the register designated by index..,1: Comparison via the register designated by index.."
|
|
hexmask.long.byte 0x0 13.--17. 1. "COMPA,Index of Screening Type 2 Compare Word 0/Word 1 register"
|
|
newline
|
|
bitfld.long 0x0 12. "ETHE,EtherType Enable" "0: EtherType match with bits 15:0 in the register..,1: EtherType match with bits 15:0 in the register.."
|
|
bitfld.long 0x0 9.--11. "I2ETH,Index of Screening Type 2 EtherType register" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 8. "VLANE,VLAN Enable" "0: VLAN match is disabled.,1: VLAN match is enabled."
|
|
bitfld.long 0x0 4.--6. "VLANP,VLAN Priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "QNB,Queue Number (0-5)" "0,1,2,3,4,5,6,7"
|
|
repeat.end
|
|
group.long 0x580++0x3
|
|
line.long 0x0 "TSCTL,GMAC Transmit Schedule Control Register"
|
|
bitfld.long 0x0 10.--11. "TXSQ5,Transmit Schedule for Qx" "0: Fixed Priority,1: CBS Enabled only valid for top two enabled..,2: DWRR enabled,3: ETS enabled"
|
|
bitfld.long 0x0 8.--9. "TXSQ4,Transmit Schedule for Qx" "0: Fixed Priority,1: CBS Enabled only valid for top two enabled..,2: DWRR enabled,3: ETS enabled"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "TXSQ3,Transmit Schedule for Qx" "0: Fixed Priority,1: CBS Enabled only valid for top two enabled..,2: DWRR enabled,3: ETS enabled"
|
|
bitfld.long 0x0 4.--5. "TXSQ2,Transmit Schedule for Qx" "0: Fixed Priority,1: CBS Enabled only valid for top two enabled..,2: DWRR enabled,3: ETS enabled"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "TXSQ1,Transmit Schedule for Qx" "0: Fixed Priority,1: CBS Enabled only valid for top two enabled..,2: DWRR enabled,3: ETS enabled"
|
|
bitfld.long 0x0 0.--1. "TXSQ0,Transmit Schedule for Qx" "0: Fixed Priority,1: CBS Enabled only valid for top two enabled..,2: DWRR enabled,3: ETS enabled"
|
|
group.long 0x590++0x7
|
|
line.long 0x0 "TQBWRL0,GMAC Transmit Queue Bandwidth Rate Limit 0 Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ALLOCQ3,DWRR Weighting or ETS Bandwidth Allocation for Qx"
|
|
hexmask.long.byte 0x0 16.--23. 1. "ALLOCQ2,DWRR Weighting or ETS Bandwidth Allocation for Qx"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "ALLOCQ1,DWRR Weighting or ETS Bandwidth Allocation for Qx"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ALLOCQ0,DWRR Weighting or ETS Bandwidth Allocation for Qx"
|
|
line.long 0x4 "TQBWRL1,GMAC Transmit Queue Bandwidth Rate Limit 1 Register"
|
|
hexmask.long.byte 0x4 8.--15. 1. "ALLOCQ5,DWRR Weighting or ETS Bandwidth Allocation for Qx"
|
|
hexmask.long.byte 0x4 0.--7. 1. "ALLOCQ4,DWRR Weighting or ETS Bandwidth Allocation for Qx"
|
|
group.long 0x5A0++0x3
|
|
line.long 0x0 "TQSA,GMAC Transmit Queue Segment Allocation Register"
|
|
bitfld.long 0x0 20.--22. "SEGALLOCQ5,Segment Allocation for Qx" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16.--18. "SEGALLOCQ4,Segment Allocation for Qx" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 12.--14. "SEGALLOCQ3,Segment Allocation for Qx" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 8.--10. "SEGALLOCQ2,Segment Allocation for Qx" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "SEGALLOCQ1,Segment Allocation for Qx" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0.--2. "SEGALLOCQ0,Segment Allocation for Qx" "0,1,2,3,4,5,6,7"
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x600)++0x3
|
|
line.long 0x0 "IERPQ[$1],Interrupt Enable Register Priority Queue (index = 1)"
|
|
bitfld.long 0x0 11. "HRESP,HRESP Not OK" "0,1"
|
|
bitfld.long 0x0 7. "TCOMP,Transmit Complete" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TFC,Transmit Frame Corruption Due to AHB Error" "0,1"
|
|
bitfld.long 0x0 5. "RLEX,Retry Limit Exceeded or Late Collision" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXUBR,RX Used Bit Read" "0,1"
|
|
bitfld.long 0x0 1. "RCOMP,Receive Complete" "0,1"
|
|
repeat.end
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x620)++0x3
|
|
line.long 0x0 "IDRPQ[$1],Interrupt Disable Register Priority Queue (index = 1)"
|
|
bitfld.long 0x0 11. "HRESP,HRESP Not OK" "0,1"
|
|
bitfld.long 0x0 7. "TCOMP,Transmit Complete" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TFC,Transmit Frame Corruption Due to AHB Error" "0,1"
|
|
bitfld.long 0x0 5. "RLEX,Retry Limit Exceeded or Late Collision" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXUBR,RX Used Bit Read" "0,1"
|
|
bitfld.long 0x0 1. "RCOMP,Receive Complete" "0,1"
|
|
repeat.end
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x640)++0x3
|
|
line.long 0x0 "IMRPQ[$1],Interrupt Mask Register Priority Queue (index = 1)"
|
|
bitfld.long 0x0 11. "HRESP,HRESP Not OK" "0,1"
|
|
bitfld.long 0x0 7. "TCOMP,Transmit Complete" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "AHB,AHB Error" "0,1"
|
|
bitfld.long 0x0 5. "RLEX,Retry Limit Exceeded or Late Collision" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXUBR,RX Used Bit Read" "0,1"
|
|
bitfld.long 0x0 1. "RCOMP,Receive Complete" "0,1"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x6E0)++0x3
|
|
line.long 0x0 "ST2ER[$1],Screening Type 2 Ethertype Register (index = 0)"
|
|
hexmask.long.word 0x0 0.--15. 1. "COMPVAL,Ethertype Compare Value"
|
|
repeat.end
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0xE2800700 ad:0xE2800708 ad:0xE2800710 ad:0xE2800718 ad:0xE2800720 ad:0xE2800728 ad:0xE2800730 ad:0xE2800738 ad:0xE2800740 ad:0xE2800748 ad:0xE2800750 ad:0xE2800758 ad:0xE2800760 ad:0xE2800768 ad:0xE2800770 ad:0xE2800778)
|
|
tree "GMAC_ST2CW[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "ST2CW0R,Screening Type 2 Compare Word 0 Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "COMPVAL,Compare Value"
|
|
hexmask.long.word 0x0 0.--15. 1. "MASKVAL,Mask Value"
|
|
line.long 0x4 "ST2CW1R,Screening Type 2 Compare Word 1 Register"
|
|
bitfld.long 0x4 9. "DISMASK,Disable Mask" "0: GMAC_ST2CW0x contains a 2-byte compare value..,1: GMAC_ST2CW0x contains a 4-byte compare value."
|
|
bitfld.long 0x4 7.--8. "OFFSSTRT,Ethernet Frame Offset Start" "0: Offset from the start of the frame,1: Offset from the byte after the EtherType field,2: Offset from the byte after the IP header field,3: Offset from the byte after the TCP/UDP header.."
|
|
hexmask.long.byte 0x4 0.--6. 1. "OFFSVAL,Offset Value in Bytes"
|
|
tree.end
|
|
repeat.end
|
|
repeat 8. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17)(list ad:0xE2800780 ad:0xE2800788 ad:0xE2800790 ad:0xE2800798 ad:0xE28007A0 ad:0xE28007A8 ad:0xE28007B0 ad:0xE28007B8)
|
|
tree "GMAC_ST2CW[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "ST2CW0R,Screening Type 2 Compare Word 0 Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "COMPVAL,Compare Value"
|
|
hexmask.long.word 0x0 0.--15. 1. "MASKVAL,Mask Value"
|
|
line.long 0x4 "ST2CW1R,Screening Type 2 Compare Word 1 Register"
|
|
bitfld.long 0x4 9. "DISMASK,Disable Mask" "0: GMAC_ST2CW0x contains a 2-byte compare value..,1: GMAC_ST2CW0x contains a 4-byte compare value."
|
|
bitfld.long 0x4 7.--8. "OFFSSTRT,Ethernet Frame Offset Start" "0: Offset from the start of the frame,1: Offset from the byte after the EtherType field,2: Offset from the byte after the IP header field,3: Offset from the byte after the TCP/UDP header.."
|
|
hexmask.long.byte 0x4 0.--6. 1. "OFFSVAL,Offset Value in Bytes"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "GMAC1"
|
|
base ad:0xE2804000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "NCR,Network Control Register"
|
|
bitfld.long 0x0 30. "IFGQAVCRED,IFG Eats QAV Credit" "0,1"
|
|
bitfld.long 0x0 28. "MIIONRGMII," "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "OSSCORR,OSS Correction Field" "0: MII on RGMII is not used.,1: MII operations are used on RGMII physical.."
|
|
bitfld.long 0x0 26. "EXTSELRQEN,External Selection of Receive Queue Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "PFCCTL,Multiple PFC Pause quantum Enable" "0: Disables multiple PFC pause quantums.,1: Enables multiple PFC pause quantums one per.."
|
|
bitfld.long 0x0 24. "OSSMODE,One Step Sync Mode" "0: 1588 One Step Sync Mode is disabled.,1: 1588 One Step Sync Mode is enabled. Replaces.."
|
|
newline
|
|
bitfld.long 0x0 22. "STUDPOFFSET,Store UDP Offset" "0: Normal operations.,1: The upper 16 bits of the CRC of every received.."
|
|
bitfld.long 0x0 20. "PTPUNIENA,Detection of Unicast PTP Frames Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TXLPIEN,Enable LPI Transmission" "0,1"
|
|
bitfld.long 0x0 18. "FNP,Flush Next Packet" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "TXPBPF,Transmit PFC Priority-based Pause Frame" "0,1"
|
|
bitfld.long 0x0 16. "ENPBPR,Enable PFC Priority-based Pause Reception" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "SRTSM,Store Receive Timestamp to Memory" "0: Normal operation.,1: Causes the CRC of every received frame to be.."
|
|
bitfld.long 0x0 12. "TXZQPF,Transmit Zero Quantum Pause Frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TXPF,Transmit Pause Frame" "0,1"
|
|
bitfld.long 0x0 10. "THALT,Transmit Halt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TSTART,Start Transmission" "0,1"
|
|
bitfld.long 0x0 8. "BP,Back pressure" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "WESTAT,Write Enable for Statistics Registers" "0,1"
|
|
bitfld.long 0x0 6. "INCSTAT,Increment Statistics Registers" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CLRSTAT,Clear Statistics Registers" "0,1"
|
|
bitfld.long 0x0 4. "MPE,Management Port Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TXEN,Transmit Enable" "0,1"
|
|
bitfld.long 0x0 2. "RXEN,Receive Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LBL,Loop Back Local" "0,1"
|
|
line.long 0x4 "NCFGR,Network Configuration Register"
|
|
bitfld.long 0x4 30. "IRXER,Ignore IPG GRXER" "0,1"
|
|
bitfld.long 0x4 29. "RXBP,Receive Bad Preamble" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "IPGSEN,IP Stretch Enable" "0,1"
|
|
bitfld.long 0x4 26. "IRXFCS,Ignore RX FCS" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "EFRHD,Enable Frames Received in Half Duplex" "0,1"
|
|
bitfld.long 0x4 24. "RXCOEN,Receive Checksum Offload Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "DCPF,Disable Copy of Pause Frames" "0,1"
|
|
bitfld.long 0x4 21.--22. "DBW,Data Bus Width" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 18.--20. "CLK,MDC CLock Division" "0: MCK divided by 8 (MCK up to 20 MHz),1: MCK divided by 16 (MCK up to 40 MHz),2: MCK divided by 32 (MCK up to 80 MHz),3: MCK divided by 48 (MCK up to 120 MHz),4: MCK divided by 64 (MCK up to 160 MHz),5: MCK divided by 96 (MCK up to 240 MHz),?,?"
|
|
bitfld.long 0x4 17. "RFCS,Remove FCS" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "LFERD,Length Field Error Frame Discard" "0,1"
|
|
bitfld.long 0x4 14.--15. "RXBUFO,Receive Buffer Offset" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 13. "PEN,Pause Enable" "0,1"
|
|
bitfld.long 0x4 12. "RTY,Retry Test" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "GBE,Gigabit Mode Enable" "0: 10/100 operation using MII interface.,1: Gigabit operation using GMII interface."
|
|
bitfld.long 0x4 8. "MAXFS,1536 Maximum Frame Size" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "UNIHEN,Unicast Hash Enable" "0,1"
|
|
bitfld.long 0x4 6. "MTIHEN,Multicast Hash Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "NBC,No Broadcast" "0,1"
|
|
bitfld.long 0x4 4. "CAF,Copy All Frames" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "JFRAME,Jumbo Frame Size" "0,1"
|
|
bitfld.long 0x4 2. "DNVLAN,Discard Non-VLAN FRAMES" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "FD,Full Duplex" "0,1"
|
|
bitfld.long 0x4 0. "SPD,Speed" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "NSR,Network Status Register"
|
|
bitfld.long 0x0 7. "RXLPIS,LPI Indication" "0,1"
|
|
bitfld.long 0x0 6. "PFCPAUSN,PFC Pause Negotiated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "IDLE,PHY Management Logic Idle" "0,1"
|
|
bitfld.long 0x0 1. "MDIO,MDIO Input Status" "0,1"
|
|
group.long 0xC++0x17
|
|
line.long 0x0 "UR,User Register"
|
|
bitfld.long 0x0 6. "HDFLCTLEN,Half Duplex Flow Control Enable" "0: Half duplex flow control is disabled.,1: Half duplex flow control is enabled."
|
|
bitfld.long 0x0 2. "REFCLK,Reference Clock Selection" "0: GCLK is selected.,1: External PIO input selected."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "MIM,Media Interface Mode" "0: MII mode is selected.,1: RMII mode is selected.,2: RGMII mode is selected.,?"
|
|
line.long 0x4 "DCFGR,DMA Configuration Register"
|
|
bitfld.long 0x4 29. "TXBD_EXTENDED,Transmit Buffer Descriptor Extended Mode" "0: Disables Transmit Buffer Data Extended mode.,1: Enables Transmit Buffer Data Extended mode. See.."
|
|
bitfld.long 0x4 28. "RXBD_EXTENDED,Receive Buffer Descriptor Extended Mode" "0: Disables Transmit Buffer Data Extended mode.,1: Enables Transmit Buffer Data Extended mode. See.."
|
|
newline
|
|
bitfld.long 0x4 24. "DDRP,DMA Discard Receive Packets" "0,1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "DRBS,DMA Receive Buffer Size"
|
|
newline
|
|
bitfld.long 0x4 13. "CRCERRREP,CRC Errors Report" "0: Bit 16 of the receive buffer descriptor..,1: Bit 16 of the receive buffer descriptor.."
|
|
bitfld.long 0x4 12. "INFLASTEN,Infinite Size for Last Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "TXCOEN,Transmitter Checksum Generation Offload Enable" "0,1"
|
|
bitfld.long 0x4 10. "TXPBMS,Transmitter Packet Buffer Memory Size Select" "0: Do not use top address bit (2 Kbytes).,1: Use full configured addressable space (4 Kbytes)."
|
|
newline
|
|
bitfld.long 0x4 8.--9. "RXBMS,Receiver Packet Buffer Memory Size Select" "0: 4/8 Kbyte Memory Size,1: 4/4 Kbytes Memory Size,2: 4/2 Kbytes Memory Size,3: 4 Kbytes Memory Size"
|
|
bitfld.long 0x4 7. "ESPA,Endian Swap Mode Enable for Packet Data Accesses" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "ESMA,Endian Swap Mode Enable for Management Descriptor Accesses" "0,1"
|
|
hexmask.long.byte 0x4 0.--4. 1. "FBLDO,Fixed Burst Length for DMA Data Operations:"
|
|
line.long 0x8 "TSR,Transmit Status Register"
|
|
bitfld.long 0x8 8. "HRESP,HRESP Not OK" "0,1"
|
|
bitfld.long 0x8 7. "LCO,Late Collision Occurred" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "TXCOMP,Transmit Complete" "0,1"
|
|
bitfld.long 0x8 4. "TFC,Transmit Frame Corruption Due to AHB Error" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "TXGO,Transmit Go" "0,1"
|
|
bitfld.long 0x8 2. "RLE,Retry Limit Exceeded" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "COL,Collision Occurred" "0,1"
|
|
bitfld.long 0x8 0. "UBR,Used Bit Read" "0,1"
|
|
line.long 0xC "RBQB,Receive Buffer Queue Base Address Register"
|
|
hexmask.long 0xC 2.--31. 1. "ADDR,Receive Buffer Queue Base Address"
|
|
bitfld.long 0xC 0. "RXQDIS,Receive Queue Disable" "0: Queue is enabled,1: Queue is disabled. Used to reduce the number of.."
|
|
line.long 0x10 "TBQB,Transmit Buffer Queue Base Address Register"
|
|
hexmask.long 0x10 2.--31. 1. "ADDR,Transmit Buffer Queue Base Address"
|
|
bitfld.long 0x10 0. "TXQDIS," "0,1"
|
|
line.long 0x14 "RSR,Receive Status Register"
|
|
bitfld.long 0x14 3. "HNO,HRESP Not OK" "0,1"
|
|
bitfld.long 0x14 2. "RXOVR,Receive Overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "REC,Frame Received" "0,1"
|
|
bitfld.long 0x14 0. "BNA,Buffer Not Available" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x0 29. "TSUTIMCOMP,TSU Timer Comparison" "0,1"
|
|
bitfld.long 0x0 28. "WOL,Wake On LAN" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXLPISBC,Receive LPI indication Status Bit Change" "0,1"
|
|
bitfld.long 0x0 26. "SRI,TSU Seconds Register Increment" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "PDRSFT,PDelay Response Frame Transmitted" "0,1"
|
|
bitfld.long 0x0 24. "PDRQFT,PDelay Request Frame Transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "PDRSFR,PDelay Response Frame Received" "0,1"
|
|
bitfld.long 0x0 22. "PDRQFR,PDelay Request Frame Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SFT,PTP Sync Frame Transmitted" "0,1"
|
|
bitfld.long 0x0 20. "DRQFT,PTP Delay Request Frame Transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "SFR,PTP Sync Frame Received" "0,1"
|
|
bitfld.long 0x0 18. "DRQFR,PTP Delay Request Frame Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PFTR,Pause Frame Transmitted" "0,1"
|
|
bitfld.long 0x0 13. "PTZ,Pause Time Zero" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PFNZ,Pause Frame with Non-zero Pause Quantum Received" "0,1"
|
|
bitfld.long 0x0 11. "HRESP,HRESP Not OK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ROVR,Receive Overrun" "0,1"
|
|
bitfld.long 0x0 7. "TCOMP,Transmit Complete" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TFC,Transmit Frame Corruption Due to AHB Error" "0,1"
|
|
bitfld.long 0x0 5. "RLEX,Retry Limit Exceeded or Late Collision" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TUR,Transmit Underrun" "0,1"
|
|
bitfld.long 0x0 3. "TXUBR,TX Used Bit Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXUBR,RX Used Bit Read" "0,1"
|
|
bitfld.long 0x0 1. "RCOMP,Receive Complete" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MFS,Management Frame Sent" "0,1"
|
|
wgroup.long 0x28++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 29. "TSUTIMCOMP,TSU Timer Comparison" "0,1"
|
|
bitfld.long 0x0 28. "WOL,Wake On LAN" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXLPISBC,Enable RX LPI Indication" "0,1"
|
|
bitfld.long 0x0 26. "SRI,TSU Seconds Register Increment" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "PDRSFT,PDelay Response Frame Transmitted" "0,1"
|
|
bitfld.long 0x0 24. "PDRQFT,PDelay Request Frame Transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "PDRSFR,PDelay Response Frame Received" "0,1"
|
|
bitfld.long 0x0 22. "PDRQFR,PDelay Request Frame Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SFT,PTP Sync Frame Transmitted" "0,1"
|
|
bitfld.long 0x0 20. "DRQFT,PTP Delay Request Frame Transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "SFR,PTP Sync Frame Received" "0,1"
|
|
bitfld.long 0x0 18. "DRQFR,PTP Delay Request Frame Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "EXINT,External Interrupt" "0,1"
|
|
bitfld.long 0x0 14. "PFTR,Pause Frame Transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PTZ,Pause Time Zero" "0,1"
|
|
bitfld.long 0x0 12. "PFNZ,Pause Frame with Non-zero Pause Quantum Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "HRESP,HRESP Not OK" "0,1"
|
|
bitfld.long 0x0 10. "ROVR,Receive Overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TCOMP,Transmit Complete" "0,1"
|
|
bitfld.long 0x0 6. "TFC,Transmit Frame Corruption Due to AHB Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RLEX,Retry Limit Exceeded or Late Collision" "0,1"
|
|
bitfld.long 0x0 4. "TUR,Transmit Underrun" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TXUBR,TX Used Bit Read" "0,1"
|
|
bitfld.long 0x0 2. "RXUBR,RX Used Bit Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RCOMP,Receive Complete" "0,1"
|
|
bitfld.long 0x0 0. "MFS,Management Frame Sent" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 29. "TSUTIMCOMP,TSU Timer Comparison" "0,1"
|
|
bitfld.long 0x4 28. "WOL,Wake On LAN" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "RXLPISBC,Enable RX LPI Indication" "0,1"
|
|
bitfld.long 0x4 26. "SRI,TSU Seconds Register Increment" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "PDRSFT,PDelay Response Frame Transmitted" "0,1"
|
|
bitfld.long 0x4 24. "PDRQFT,PDelay Request Frame Transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "PDRSFR,PDelay Response Frame Received" "0,1"
|
|
bitfld.long 0x4 22. "PDRQFR,PDelay Request Frame Received" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "SFT,PTP Sync Frame Transmitted" "0,1"
|
|
bitfld.long 0x4 20. "DRQFT,PTP Delay Request Frame Transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "SFR,PTP Sync Frame Received" "0,1"
|
|
bitfld.long 0x4 18. "DRQFR,PTP Delay Request Frame Received" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "EXINT,External Interrupt" "0,1"
|
|
bitfld.long 0x4 14. "PFTR,Pause Frame Transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "PTZ,Pause Time Zero" "0,1"
|
|
bitfld.long 0x4 12. "PFNZ,Pause Frame with Non-zero Pause Quantum Received" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "HRESP,HRESP Not OK" "0,1"
|
|
bitfld.long 0x4 10. "ROVR,Receive Overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "TCOMP,Transmit Complete" "0,1"
|
|
bitfld.long 0x4 6. "TFC,Transmit Frame Corruption Due to AHB Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RLEX,Retry Limit Exceeded or Late Collision" "0,1"
|
|
bitfld.long 0x4 4. "TUR,Transmit Underrun" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "TXUBR,TX Used Bit Read" "0,1"
|
|
bitfld.long 0x4 2. "RXUBR,RX Used Bit Read" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RCOMP,Receive Complete" "0,1"
|
|
bitfld.long 0x4 0. "MFS,Management Frame Sent" "0,1"
|
|
group.long 0x30++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 29. "TSUTIMCOMP,TSU Timer Comparison" "0,1"
|
|
bitfld.long 0x0 28. "WOL,Wake On LAN" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXLPISBC,Enable RX LPI Indication" "0,1"
|
|
bitfld.long 0x0 26. "SRI,TSU Seconds Register Increment" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "PDRSFT,PDelay Response Frame Transmitted" "0,1"
|
|
bitfld.long 0x0 24. "PDRQFT,PDelay Request Frame Transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "PDRSFR,PDelay Response Frame Received" "0,1"
|
|
bitfld.long 0x0 22. "PDRQFR,PDelay Request Frame Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SFT,PTP Sync Frame Transmitted" "0,1"
|
|
bitfld.long 0x0 20. "DRQFT,PTP Delay Request Frame Transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "SFR,PTP Sync Frame Received" "0,1"
|
|
bitfld.long 0x0 18. "DRQFR,PTP Delay Request Frame Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "EXINT,External Interrupt" "0,1"
|
|
bitfld.long 0x0 14. "PFTR,Pause Frame Transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PTZ,Pause Time Zero" "0,1"
|
|
bitfld.long 0x0 12. "PFNZ,Pause Frame with Non-zero Pause Quantum Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "HRESP,HRESP Not OK" "0,1"
|
|
bitfld.long 0x0 10. "ROVR,Receive Overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TCOMP,Transmit Complete" "0,1"
|
|
bitfld.long 0x0 6. "TFC,Transmit Frame Corruption Due to AHB Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RLEX,Retry Limit Exceeded or Late Collision" "0,1"
|
|
bitfld.long 0x0 4. "TUR,Transmit Underrun" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TXUBR,TX Used Bit Read" "0,1"
|
|
bitfld.long 0x0 2. "RXUBR,RX Used Bit Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RCOMP,Receive Complete" "0,1"
|
|
bitfld.long 0x0 0. "MFS,Management Frame Sent" "0,1"
|
|
line.long 0x4 "MAN,PHY Maintenance Register"
|
|
bitfld.long 0x4 31. "WZO,Write ZERO" "0,1"
|
|
bitfld.long 0x4 30. "CLTTO,Clause 22 Operation" "0: Clause 45 operation,1: Clause 22 operation"
|
|
newline
|
|
bitfld.long 0x4 28.--29. "OP,Operation" "?,1: Write,2: Read,?"
|
|
hexmask.long.byte 0x4 23.--27. 1. "PHYA,PHY Address"
|
|
newline
|
|
hexmask.long.byte 0x4 18.--22. 1. "REGA,Register Address"
|
|
bitfld.long 0x4 16.--17. "WTN,Write Ten" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "DATA,PHY Data"
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "RPQ,Received Pause Quantum Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RPQ,Received Pause Quantum"
|
|
group.long 0x3C++0xF
|
|
line.long 0x0 "TPQ,Transmit Pause Quantum Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "P1TPQ,Priority 1 Transmit Pause Quantum"
|
|
hexmask.long.word 0x0 0.--15. 1. "TPQ,Transmit Pause Quantum"
|
|
line.long 0x4 "TPSF,TX Partial Store and Forward Register"
|
|
bitfld.long 0x4 31. "ENTXP,Enable TX Partial Store and Forward Operation" "0,1"
|
|
hexmask.long.word 0x4 0.--11. 1. "TPB1ADR,Transmit Partial Store and Forward Address"
|
|
line.long 0x8 "RPSF,RX Partial Store and Forward Register"
|
|
bitfld.long 0x8 31. "ENRXP,Enable RX Partial Store and Forward Operation" "0,1"
|
|
hexmask.long.word 0x8 0.--10. 1. "RPB1ADR,Receive Partial Store and Forward Address"
|
|
line.long 0xC "RJFML,RX Jumbo Frame Max Length Register"
|
|
hexmask.long.word 0xC 0.--13. 1. "FML,Frame Max Length"
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "AMP,AXI Max Pipeline"
|
|
bitfld.long 0x0 16. "USE_FROM,Use AW to W or to B" "0: Operates between the AW and W channels.,1: Operates between the AW and B channels."
|
|
hexmask.long.byte 0x0 8.--15. 1. "AW2W_MAX_PIPELINE,AW to W Max Pipeline"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "AR2R_MAX_PIPELINE,AR to R Max Pipeline"
|
|
group.long 0x5C++0x7
|
|
line.long 0x0 "INTM,GMAC Interrupt Moderation Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "TXINTMOD,Transmit Interrupt Moderation"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXINTMOD,Receive Interrupt Moderation"
|
|
line.long 0x4 "SYSWT,GMAC System Wake-Up Time Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "SYSWKUPTIME,System Wake-up Time"
|
|
group.long 0x80++0x67
|
|
line.long 0x0 "HRB,Hash Register Bottom"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Hash Address"
|
|
line.long 0x4 "HRT,Hash Register Top"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR,Hash Address"
|
|
line.long 0x8 "SAB1,Specific Address 1 Bottom Register"
|
|
hexmask.long 0x8 0.--31. 1. "ADDR,Specific Address 1"
|
|
line.long 0xC "SAT1,Specific Address 1 Top Register"
|
|
bitfld.long 0xC 16. "FILTSORD,Filter Source or Destination MAC Address" "0: The filter is a destination address filter.,1: The filter is a source address filter."
|
|
hexmask.long.word 0xC 0.--15. 1. "ADDR,Specific Address 1"
|
|
line.long 0x10 "SAB2,Specific Address 2 Bottom Register"
|
|
hexmask.long 0x10 0.--31. 1. "ADDR,Specific Address 2"
|
|
line.long 0x14 "SAT2,Specific Address 2 Top Register"
|
|
hexmask.long.byte 0x14 24.--29. 1. "FILTBMSK,Filter Bytes Mask"
|
|
bitfld.long 0x14 16. "FILTSORD,Filter Source or Destination MAC Address" "0: The filter is a destination address filter.,1: The filter is a source address filter."
|
|
newline
|
|
hexmask.long.word 0x14 0.--15. 1. "ADDR,Specific Address 2"
|
|
line.long 0x18 "SAB3,Specific Address 3 Bottom Register"
|
|
hexmask.long 0x18 0.--31. 1. "ADDR,Specific Address 3"
|
|
line.long 0x1C "SAT3,Specific Address 3 Top Register"
|
|
hexmask.long.byte 0x1C 24.--29. 1. "FILTBMSK,Filter Bytes Mask"
|
|
bitfld.long 0x1C 16. "FILTSORD,Filter Source or Destination MAC Address" "0: The filter is a destination address filter.,1: The filter is a source address filter."
|
|
newline
|
|
hexmask.long.word 0x1C 0.--15. 1. "ADDR,Specific Address 3"
|
|
line.long 0x20 "SAB4,Specific Address 4 Bottom Register"
|
|
hexmask.long 0x20 0.--31. 1. "ADDR,Specific Address 4"
|
|
line.long 0x24 "SAT4,Specific Address 4 Top Register"
|
|
hexmask.long.byte 0x24 24.--29. 1. "FILTBMSK,Filter Bytes Mask"
|
|
bitfld.long 0x24 16. "FILTSORD,Filter Source or Destination MAC Address" "0: The filter is a destination address filter.,1: The filter is a source address filter."
|
|
newline
|
|
hexmask.long.word 0x24 0.--15. 1. "ADDR,Specific Address 4"
|
|
line.long 0x28 "TIDM1,Type ID Match 1 Register"
|
|
bitfld.long 0x28 31. "ENID1,Enable Copying of TID Matched Frames" "0: TID is not part of the comparison match.,1: TID is processed for the comparison match."
|
|
hexmask.long.word 0x28 0.--15. 1. "TID,Type ID Match 1"
|
|
line.long 0x2C "TIDM2,Type ID Match 2 Register"
|
|
bitfld.long 0x2C 31. "ENID2,Enable Copying of TID Matched Frames" "0: TID is not part of the comparison match.,1: TID is processed for the comparison match."
|
|
hexmask.long.word 0x2C 0.--15. 1. "TID,Type ID Match 2"
|
|
line.long 0x30 "TIDM3,Type ID Match 3 Register"
|
|
bitfld.long 0x30 31. "ENID3,Enable Copying of TID Matched Frames" "0: TID is not part of the comparison match.,1: TID is processed for the comparison match."
|
|
hexmask.long.word 0x30 0.--15. 1. "TID,Type ID Match 3"
|
|
line.long 0x34 "TIDM4,Type ID Match 4 Register"
|
|
bitfld.long 0x34 31. "ENID4,Enable Copying of TID Matched Frames" "0: TID is not part of the comparison match.,1: TID is processed for the comparison match."
|
|
hexmask.long.word 0x34 0.--15. 1. "TID,Type ID Match 4"
|
|
line.long 0x38 "WOL,Wake on LAN Register"
|
|
bitfld.long 0x38 19. "MTI,Multicast Hash Event Enable" "0,1"
|
|
bitfld.long 0x38 18. "SA1,Specific Address Register 1 Event Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x38 17. "ARP,ARP Request Event Enable" "0,1"
|
|
bitfld.long 0x38 16. "MAG,Magic Packet Event Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x38 0.--15. 1. "IP,ARP Request IP Address"
|
|
line.long 0x3C "IPGS,IPG Stretch Register"
|
|
hexmask.long.word 0x3C 0.--15. 1. "FL,Frame Length"
|
|
line.long 0x40 "SVLAN,Stacked VLAN Register"
|
|
bitfld.long 0x40 31. "ESVLAN,Enable Stacked VLAN Processing Mode" "0: Disable the stacked VLAN processing mode,1: Enable the stacked VLAN processing mode"
|
|
hexmask.long.word 0x40 0.--15. 1. "VLAN_TYPE,User Defined VLAN_TYPE Field"
|
|
line.long 0x44 "TPFCP,Transmit PFC Pause Register"
|
|
hexmask.long.byte 0x44 8.--15. 1. "PQ,Pause Quantum"
|
|
hexmask.long.byte 0x44 0.--7. 1. "PEV,Priority Enable Vector"
|
|
line.long 0x48 "SAMB1,Specific Address 1 Mask Bottom Register"
|
|
hexmask.long 0x48 0.--31. 1. "ADDR,Specific Address 1 Mask"
|
|
line.long 0x4C "SAMT1,Specific Address 1 Mask Top Register"
|
|
hexmask.long.word 0x4C 0.--15. 1. "ADDR,Specific Address 1 Mask"
|
|
line.long 0x50 "AMRX,AHB Address Mask for RX Data Buffer Accesses Register"
|
|
hexmask.long.byte 0x50 28.--31. 1. "MSBADDR,MSB of the Receive Data Buffer AHB/AXI Address"
|
|
hexmask.long.byte 0x50 0.--3. 1. "MSBADDRMSK,Mask of the Receive Data Buffer AHB/AXI Address"
|
|
line.long 0x54 "RXUDAR,PTP RX Unicast IP Destination Address Register"
|
|
hexmask.long 0x54 0.--31. 1. "RXUDA,Receive Unicast Destination Address"
|
|
line.long 0x58 "TXUDAR,PTP TX Unicast IP Destination Address Register"
|
|
hexmask.long 0x58 0.--31. 1. "TXUDA,Transmit Unicast Destination Address"
|
|
line.long 0x5C "NSC,1588 Timer Nanosecond Comparison Register"
|
|
hexmask.long.tbyte 0x5C 0.--21. 1. "NANOSEC,1588 Timer Nanosecond Comparison Value"
|
|
line.long 0x60 "SCL,1588 Timer Second Comparison Low Register"
|
|
hexmask.long 0x60 0.--31. 1. "SEC,1588 Timer Second Comparison Value"
|
|
line.long 0x64 "SCH,1588 Timer Second Comparison High Register"
|
|
hexmask.long.word 0x64 0.--15. 1. "SEC,1588 Timer Second Comparison Value"
|
|
rgroup.long 0xE8++0xF
|
|
line.long 0x0 "EFTSH,PTP Event Frame Transmitted Seconds High Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RUD,Register Update"
|
|
line.long 0x4 "EFRSH,PTP Event Frame Received Seconds High Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "RUD,Register Update"
|
|
line.long 0x8 "PEFTSH,PTP Peer Event Frame Transmitted Seconds High Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "RUD,Register Update"
|
|
line.long 0xC "PEFRSH,PTP Peer Event Frame Received Seconds High Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "RUD,Register Update"
|
|
rgroup.long 0x100++0xB3
|
|
line.long 0x0 "OTLO,Octets Transmitted Low Register"
|
|
hexmask.long 0x0 0.--31. 1. "TXO,Transmitted Octets"
|
|
line.long 0x4 "OTHI,Octets Transmitted High Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "TXO,Transmitted Octets"
|
|
line.long 0x8 "FT,Frames Transmitted Register"
|
|
hexmask.long 0x8 0.--31. 1. "FTX,Frames Transmitted without Error"
|
|
line.long 0xC "BCFT,Broadcast Frames Transmitted Register"
|
|
hexmask.long 0xC 0.--31. 1. "BFTX,Broadcast Frames Transmitted without Error"
|
|
line.long 0x10 "MFT,Multicast Frames Transmitted Register"
|
|
hexmask.long 0x10 0.--31. 1. "MFTX,Multicast Frames Transmitted without Error"
|
|
line.long 0x14 "PFT,Pause Frames Transmitted Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "PFTX,Pause Frames Transmitted Register"
|
|
line.long 0x18 "BFT64,64 Byte Frames Transmitted Register"
|
|
hexmask.long 0x18 0.--31. 1. "NFTX,64 Byte Frames Transmitted without Error"
|
|
line.long 0x1C "TBFT127,65 to 127 Byte Frames Transmitted Register"
|
|
hexmask.long 0x1C 0.--31. 1. "NFTX,65 to 127 Byte Frames Transmitted without Error"
|
|
line.long 0x20 "TBFT255,128 to 255 Byte Frames Transmitted Register"
|
|
hexmask.long 0x20 0.--31. 1. "NFTX,128 to 255 Byte Frames Transmitted without Error"
|
|
line.long 0x24 "TBFT511,256 to 511 Byte Frames Transmitted Register"
|
|
hexmask.long 0x24 0.--31. 1. "NFTX,256 to 511 Byte Frames Transmitted without Error"
|
|
line.long 0x28 "TBFT1023,512 to 1023 Byte Frames Transmitted Register"
|
|
hexmask.long 0x28 0.--31. 1. "NFTX,512 to 1023 Byte Frames Transmitted without Error"
|
|
line.long 0x2C "TBFT1518,1024 to 1518 Byte Frames Transmitted Register"
|
|
hexmask.long 0x2C 0.--31. 1. "NFTX,1024 to 1518 Byte Frames Transmitted without Error"
|
|
line.long 0x30 "GTBFT1518,Greater Than 1518 Byte Frames Transmitted Register"
|
|
hexmask.long 0x30 0.--31. 1. "NFTX,Greater than 1518 Byte Frames Transmitted without Error"
|
|
line.long 0x34 "TUR,Transmit Underruns Register"
|
|
hexmask.long.word 0x34 0.--9. 1. "TXUNR,Transmit Underruns"
|
|
line.long 0x38 "SCF,Single Collision Frames Register"
|
|
hexmask.long.tbyte 0x38 0.--17. 1. "SCOL,Single Collision"
|
|
line.long 0x3C "MCF,Multiple Collision Frames Register"
|
|
hexmask.long.tbyte 0x3C 0.--17. 1. "MCOL,Multiple Collision"
|
|
line.long 0x40 "EC,Excessive Collisions Register"
|
|
hexmask.long.word 0x40 0.--9. 1. "XCOL,Excessive Collisions"
|
|
line.long 0x44 "LC,Late Collisions Register"
|
|
hexmask.long.word 0x44 0.--9. 1. "LCOL,Late Collisions"
|
|
line.long 0x48 "DTF,Deferred Transmission Frames Register"
|
|
hexmask.long.tbyte 0x48 0.--17. 1. "DEFT,Deferred Transmission"
|
|
line.long 0x4C "CSE,Carrier Sense Errors Register"
|
|
hexmask.long.word 0x4C 0.--9. 1. "CSR,Carrier Sense Error"
|
|
line.long 0x50 "ORLO,Octets Received Low Received Register"
|
|
hexmask.long 0x50 0.--31. 1. "RXO,Received Octets"
|
|
line.long 0x54 "ORHI,Octets Received High Received Register"
|
|
hexmask.long.word 0x54 0.--15. 1. "RXO,Received Octets"
|
|
line.long 0x58 "FR,Frames Received Register"
|
|
hexmask.long 0x58 0.--31. 1. "FRX,Frames Received without Error"
|
|
line.long 0x5C "BCFR,Broadcast Frames Received Register"
|
|
hexmask.long 0x5C 0.--31. 1. "BFRX,Broadcast Frames Received without Error"
|
|
line.long 0x60 "MFR,Multicast Frames Received Register"
|
|
hexmask.long 0x60 0.--31. 1. "MFRX,Multicast Frames Received without Error"
|
|
line.long 0x64 "PFR,Pause Frames Received Register"
|
|
hexmask.long.word 0x64 0.--15. 1. "PFRX,Pause Frames Received Register"
|
|
line.long 0x68 "BFR64,64 Byte Frames Received Register"
|
|
hexmask.long 0x68 0.--31. 1. "NFRX,64 Byte Frames Received without Error"
|
|
line.long 0x6C "TBFR127,65 to 127 Byte Frames Received Register"
|
|
hexmask.long 0x6C 0.--31. 1. "NFRX,65 to 127 Byte Frames Received without Error"
|
|
line.long 0x70 "TBFR255,128 to 255 Byte Frames Received Register"
|
|
hexmask.long 0x70 0.--31. 1. "NFRX,128 to 255 Byte Frames Received without Error"
|
|
line.long 0x74 "TBFR511,256 to 511 Byte Frames Received Register"
|
|
hexmask.long 0x74 0.--31. 1. "NFRX,256 to 511 Byte Frames Received without Error"
|
|
line.long 0x78 "TBFR1023,512 to 1023 Byte Frames Received Register"
|
|
hexmask.long 0x78 0.--31. 1. "NFRX,512 to 1023 Byte Frames Received without Error"
|
|
line.long 0x7C "TBFR1518,1024 to 1518 Byte Frames Received Register"
|
|
hexmask.long 0x7C 0.--31. 1. "NFRX,1024 to 1518 Byte Frames Received without Error"
|
|
line.long 0x80 "TMXBFR,1519 to Maximum Byte Frames Received Register"
|
|
hexmask.long 0x80 0.--31. 1. "NFRX,1519 to Maximum Byte Frames Received without Error"
|
|
line.long 0x84 "UFR,Undersize Frames Received Register"
|
|
hexmask.long.word 0x84 0.--9. 1. "UFRX,Undersize Frames Received"
|
|
line.long 0x88 "OFR,Oversize Frames Received Register"
|
|
hexmask.long.word 0x88 0.--9. 1. "OFRX,Oversized Frames Received"
|
|
line.long 0x8C "JR,Jabbers Received Register"
|
|
hexmask.long.word 0x8C 0.--9. 1. "JRX,Jabbers Received"
|
|
line.long 0x90 "FCSE,Frame Check Sequence Errors Register"
|
|
hexmask.long.word 0x90 0.--9. 1. "FCKR,Frame Check Sequence Errors"
|
|
line.long 0x94 "LFFE,Length Field Frame Errors Register"
|
|
hexmask.long.word 0x94 0.--9. 1. "LFER,Length Field Frame Errors"
|
|
line.long 0x98 "RSE,Receive Symbol Errors Register"
|
|
hexmask.long.word 0x98 0.--9. 1. "RXSE,Receive Symbol Errors"
|
|
line.long 0x9C "AE,Alignment Errors Register"
|
|
hexmask.long.word 0x9C 0.--9. 1. "AER,Alignment Errors"
|
|
line.long 0xA0 "RRE,Receive Resource Errors Register"
|
|
hexmask.long.tbyte 0xA0 0.--17. 1. "RXRER,Receive Resource Errors"
|
|
line.long 0xA4 "ROE,Receive Overrun Register"
|
|
hexmask.long.word 0xA4 0.--9. 1. "RXOVR,Receive Overruns"
|
|
line.long 0xA8 "IHCE,IP Header Checksum Errors Register"
|
|
hexmask.long.byte 0xA8 0.--7. 1. "HCKER,IP Header Checksum Errors"
|
|
line.long 0xAC "TCE,TCP Checksum Errors Register"
|
|
hexmask.long.byte 0xAC 0.--7. 1. "TCKER,TCP Checksum Errors"
|
|
line.long 0xB0 "UCE,UDP Checksum Errors Register"
|
|
hexmask.long.byte 0xB0 0.--7. 1. "UCKER,UDP Checksum Errors"
|
|
group.long 0x1BC++0x7
|
|
line.long 0x0 "TISUBN,1588 Timer Increment Sub-nanoseconds Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "LSBTIR,Lower Significant Bits of Timer Increment Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "MSBTIR,Most Significant Bits of Timer Increment Register"
|
|
line.long 0x4 "TSH,1588 Timer Seconds High Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "TCS,Timer Count in Seconds"
|
|
group.long 0x1D0++0x7
|
|
line.long 0x0 "TSL,1588 Timer Seconds Low Register"
|
|
hexmask.long 0x0 0.--31. 1. "TCS,Timer Count in Seconds"
|
|
line.long 0x4 "TN,1588 Timer Nanoseconds Register"
|
|
hexmask.long 0x4 0.--29. 1. "TNS,Timer Count in Nanoseconds"
|
|
wgroup.long 0x1D8++0x3
|
|
line.long 0x0 "TA,1588 Timer Adjust Register"
|
|
bitfld.long 0x0 31. "ADJ,Adjust 1588 Timer" "0,1"
|
|
hexmask.long 0x0 0.--29. 1. "ITDT,Increment/Decrement"
|
|
group.long 0x1DC++0x3
|
|
line.long 0x0 "TI,1588 Timer Increment Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "NIT,Number of Increments"
|
|
hexmask.long.byte 0x0 8.--15. 1. "ACNS,Alternative Count Nanoseconds"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "CNS,Count Nanoseconds"
|
|
rgroup.long 0x1E0++0x1F
|
|
line.long 0x0 "EFTSL,PTP Event Frame Transmitted Seconds Low Register"
|
|
hexmask.long 0x0 0.--31. 1. "RUD,Register Update"
|
|
line.long 0x4 "EFTN,PTP Event Frame Transmitted Nanoseconds Register"
|
|
hexmask.long 0x4 0.--29. 1. "RUD,Register Update"
|
|
line.long 0x8 "EFRSL,PTP Event Frame Received Seconds Low Register"
|
|
hexmask.long 0x8 0.--31. 1. "RUD,Register Update"
|
|
line.long 0xC "EFRN,PTP Event Frame Received Nanoseconds Register"
|
|
hexmask.long 0xC 0.--29. 1. "RUD,Register Update"
|
|
line.long 0x10 "PEFTSL,PTP Peer Event Frame Transmitted Seconds Low Register"
|
|
hexmask.long 0x10 0.--31. 1. "RUD,Register Update"
|
|
line.long 0x14 "PEFTN,PTP Peer Event Frame Transmitted Nanoseconds Register"
|
|
hexmask.long 0x14 0.--29. 1. "RUD,Register Update"
|
|
line.long 0x18 "PEFRSL,PTP Peer Event Frame Received Seconds Low Register"
|
|
hexmask.long 0x18 0.--31. 1. "RUD,Register Update"
|
|
line.long 0x1C "PEFRN,PTP Peer Event Frame Received Nanoseconds Register"
|
|
hexmask.long 0x1C 0.--29. 1. "RUD,Register Update"
|
|
group.long 0x260++0xB
|
|
line.long 0x0 "TXPQUANT1,GMAC Transmit Pause Quantum 1 Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "QUANT_P3,Transmit Pause Quantum for Priority 3"
|
|
hexmask.long.word 0x0 0.--15. 1. "QUANT_P2,Transmit Pause Quantum for Priority 2"
|
|
line.long 0x4 "TXPQUANT2,GMAC Transmit Pause Quantum 2 Register"
|
|
hexmask.long.word 0x4 16.--31. 1. "QUANT_P5,Transmit Pause Quantum for Priority 5"
|
|
hexmask.long.word 0x4 0.--15. 1. "QUANT_P4,Transmit Pause Quantum for Priority 4"
|
|
line.long 0x8 "TXPQUANT3,GMAC Transmit Pause Quantum 3 Register"
|
|
hexmask.long.word 0x8 16.--31. 1. "QUANT_P7,Transmit Pause Quantum for Priority 7"
|
|
hexmask.long.word 0x8 0.--15. 1. "QUANT_P6,Transmit Pause Quantum for Priority 6"
|
|
rgroup.long 0x270++0xF
|
|
line.long 0x0 "RXLPI,Received LPI Transitions"
|
|
hexmask.long.word 0x0 0.--15. 1. "COUNT,Count of RX LPI transitions (cleared on read)"
|
|
line.long 0x4 "RXLPITIME,Received LPI Time"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "LPITIME,Time in LPI (cleared on read)"
|
|
line.long 0x8 "TXLPI,Transmit LPI Transitions"
|
|
hexmask.long.word 0x8 0.--15. 1. "COUNT,Count of LPI transitions (cleared on read)"
|
|
line.long 0xC "TXLPITIME,Transmit LPI Time"
|
|
hexmask.long.tbyte 0xC 0.--23. 1. "LPITIME,Time in LPI (cleared on read)"
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x400)++0x3
|
|
line.long 0x0 "ISRPQ[$1],Interrupt Status Register Priority Queue (index = 1)"
|
|
bitfld.long 0x0 11. "HRESP,HRESP Not OK" "0,1"
|
|
bitfld.long 0x0 10. "ROVR,Receive Overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TCOMP,Transmit Complete" "0,1"
|
|
bitfld.long 0x0 6. "TFC,Transmit Frame Corruption Due to AHB Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RLEX,Retry Limit Exceeded or Late Collision" "0,1"
|
|
bitfld.long 0x0 2. "RXUBR,RX Used Bit Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RCOMP,Receive Complete" "0,1"
|
|
repeat.end
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x440)++0x3
|
|
line.long 0x0 "TBQBAPQ[$1],Transmit Buffer Queue Base Address Register Priority Queue (index = 1)"
|
|
hexmask.long 0x0 2.--31. 1. "TXBQBA,Transmit Buffer Queue Base Address"
|
|
repeat.end
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x480)++0x3
|
|
line.long 0x0 "RBQBAPQ[$1],Receive Buffer Queue Base Address Register Priority Queue (index = 1)"
|
|
hexmask.long 0x0 2.--31. 1. "RXBQBA,Receive Buffer Queue Base Address"
|
|
repeat.end
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x4A0)++0x3
|
|
line.long 0x0 "RBSRPQ[$1],Receive Buffer Size Register Priority Queue (index = 1)"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RBS,Receive Buffer Size"
|
|
repeat.end
|
|
group.long 0x4BC++0x1B
|
|
line.long 0x0 "CBSCR,Credit-Based Shaping Control Register"
|
|
bitfld.long 0x0 1. "QAE,Queue A CBS Enable" "0: Credit-based shaping on the second highest..,1: Credit-based shaping on the second highest.."
|
|
bitfld.long 0x0 0. "QBE,Queue B CBS Enable" "0: Credit-based shaping on the highest priority..,1: Credit-based shaping on the highest priority.."
|
|
line.long 0x4 "CBSISQA,Credit-Based Shaping IdleSlope Register for Queue A"
|
|
hexmask.long 0x4 0.--31. 1. "IS,IdleSlope"
|
|
line.long 0x8 "CBSISQB,Credit-Based Shaping IdleSlope Register for Queue B"
|
|
hexmask.long 0x8 0.--31. 1. "IS,IdleSlope"
|
|
line.long 0xC "TQUBA,Transmit Queue Upper Base Address Register"
|
|
hexmask.long 0xC 0.--31. 1. "TQUBA,Transmit Queue Upper Base Address"
|
|
line.long 0x10 "TXBDCTRL,Transmit BD Control Register"
|
|
bitfld.long 0x10 4.--5. "TSMODE,TX Descriptor Timestamp Insertion Mode" "0: TS insertion disable,1: TS inserted for PTP Event Frames only,2: TS inserted for All PTP Frames only,3: TS insertion for All Frames"
|
|
line.long 0x14 "RXBDCTRL,Receive BD Control Register"
|
|
bitfld.long 0x14 4.--5. "TSMODE,RX Descriptor Timestamp Insertion Mode" "0: TS insertion disable,1: TS inserted for PTP Event Frames only,2: TS inserted for All PTP Frames only,3: TS insertion for All Frames"
|
|
line.long 0x18 "RQUBA,Receive Queue Upper Base Address Register"
|
|
hexmask.long 0x18 0.--31. 1. "RQUBA,Receive Queue Upper Base Address"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x500)++0x3
|
|
line.long 0x0 "ST1RPQ[$1],Screening Type 1 Register Priority Queue (index = 0)"
|
|
bitfld.long 0x0 29. "UDPE,UDP Port Match Enable" "0,1"
|
|
bitfld.long 0x0 28. "DSTCE,Differentiated Services or Traffic Class Match Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 12.--27. 1. "UDPM,UDP Port Match"
|
|
hexmask.long.byte 0x0 4.--11. 1. "DSTCM,Differentiated Services or Traffic Class Match"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "QNB,Queue Number (0-5)" "0,1,2,3,4,5,6,7"
|
|
repeat.end
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x540)++0x3
|
|
line.long 0x0 "ST2RPQ[$1],Screening Type 2 Register Priority Queue (index = 0)"
|
|
bitfld.long 0x0 30. "COMPCE,Compare C Enable" "0: Comparison via the register designated by index..,1: Comparison via the register designated by index.."
|
|
hexmask.long.byte 0x0 25.--29. 1. "COMPC,Index of Screening Type 2 Compare Word 0/Word 1 register"
|
|
newline
|
|
bitfld.long 0x0 24. "COMPBE,Compare B Enable" "0: Comparison via the register designated by index..,1: Comparison via the register designated by index.."
|
|
hexmask.long.byte 0x0 19.--23. 1. "COMPB,Index of Screening Type 2 Compare Word 0/Word 1 register"
|
|
newline
|
|
bitfld.long 0x0 18. "COMPAE,Compare A Enable" "0: Comparison via the register designated by index..,1: Comparison via the register designated by index.."
|
|
hexmask.long.byte 0x0 13.--17. 1. "COMPA,Index of Screening Type 2 Compare Word 0/Word 1 register"
|
|
newline
|
|
bitfld.long 0x0 12. "ETHE,EtherType Enable" "0: EtherType match with bits 15:0 in the register..,1: EtherType match with bits 15:0 in the register.."
|
|
bitfld.long 0x0 9.--11. "I2ETH,Index of Screening Type 2 EtherType register" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 8. "VLANE,VLAN Enable" "0: VLAN match is disabled.,1: VLAN match is enabled."
|
|
bitfld.long 0x0 4.--6. "VLANP,VLAN Priority" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "QNB,Queue Number (0-5)" "0,1,2,3,4,5,6,7"
|
|
repeat.end
|
|
group.long 0x580++0x3
|
|
line.long 0x0 "TSCTL,GMAC Transmit Schedule Control Register"
|
|
bitfld.long 0x0 10.--11. "TXSQ5,Transmit Schedule for Qx" "0: Fixed Priority,1: CBS Enabled only valid for top two enabled..,2: DWRR enabled,3: ETS enabled"
|
|
bitfld.long 0x0 8.--9. "TXSQ4,Transmit Schedule for Qx" "0: Fixed Priority,1: CBS Enabled only valid for top two enabled..,2: DWRR enabled,3: ETS enabled"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "TXSQ3,Transmit Schedule for Qx" "0: Fixed Priority,1: CBS Enabled only valid for top two enabled..,2: DWRR enabled,3: ETS enabled"
|
|
bitfld.long 0x0 4.--5. "TXSQ2,Transmit Schedule for Qx" "0: Fixed Priority,1: CBS Enabled only valid for top two enabled..,2: DWRR enabled,3: ETS enabled"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "TXSQ1,Transmit Schedule for Qx" "0: Fixed Priority,1: CBS Enabled only valid for top two enabled..,2: DWRR enabled,3: ETS enabled"
|
|
bitfld.long 0x0 0.--1. "TXSQ0,Transmit Schedule for Qx" "0: Fixed Priority,1: CBS Enabled only valid for top two enabled..,2: DWRR enabled,3: ETS enabled"
|
|
group.long 0x590++0x7
|
|
line.long 0x0 "TQBWRL0,GMAC Transmit Queue Bandwidth Rate Limit 0 Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ALLOCQ3,DWRR Weighting or ETS Bandwidth Allocation for Qx"
|
|
hexmask.long.byte 0x0 16.--23. 1. "ALLOCQ2,DWRR Weighting or ETS Bandwidth Allocation for Qx"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "ALLOCQ1,DWRR Weighting or ETS Bandwidth Allocation for Qx"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ALLOCQ0,DWRR Weighting or ETS Bandwidth Allocation for Qx"
|
|
line.long 0x4 "TQBWRL1,GMAC Transmit Queue Bandwidth Rate Limit 1 Register"
|
|
hexmask.long.byte 0x4 8.--15. 1. "ALLOCQ5,DWRR Weighting or ETS Bandwidth Allocation for Qx"
|
|
hexmask.long.byte 0x4 0.--7. 1. "ALLOCQ4,DWRR Weighting or ETS Bandwidth Allocation for Qx"
|
|
group.long 0x5A0++0x3
|
|
line.long 0x0 "TQSA,GMAC Transmit Queue Segment Allocation Register"
|
|
bitfld.long 0x0 20.--22. "SEGALLOCQ5,Segment Allocation for Qx" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 16.--18. "SEGALLOCQ4,Segment Allocation for Qx" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 12.--14. "SEGALLOCQ3,Segment Allocation for Qx" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 8.--10. "SEGALLOCQ2,Segment Allocation for Qx" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "SEGALLOCQ1,Segment Allocation for Qx" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0.--2. "SEGALLOCQ0,Segment Allocation for Qx" "0,1,2,3,4,5,6,7"
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x600)++0x3
|
|
line.long 0x0 "IERPQ[$1],Interrupt Enable Register Priority Queue (index = 1)"
|
|
bitfld.long 0x0 11. "HRESP,HRESP Not OK" "0,1"
|
|
bitfld.long 0x0 7. "TCOMP,Transmit Complete" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TFC,Transmit Frame Corruption Due to AHB Error" "0,1"
|
|
bitfld.long 0x0 5. "RLEX,Retry Limit Exceeded or Late Collision" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXUBR,RX Used Bit Read" "0,1"
|
|
bitfld.long 0x0 1. "RCOMP,Receive Complete" "0,1"
|
|
repeat.end
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x620)++0x3
|
|
line.long 0x0 "IDRPQ[$1],Interrupt Disable Register Priority Queue (index = 1)"
|
|
bitfld.long 0x0 11. "HRESP,HRESP Not OK" "0,1"
|
|
bitfld.long 0x0 7. "TCOMP,Transmit Complete" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TFC,Transmit Frame Corruption Due to AHB Error" "0,1"
|
|
bitfld.long 0x0 5. "RLEX,Retry Limit Exceeded or Late Collision" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXUBR,RX Used Bit Read" "0,1"
|
|
bitfld.long 0x0 1. "RCOMP,Receive Complete" "0,1"
|
|
repeat.end
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x640)++0x3
|
|
line.long 0x0 "IMRPQ[$1],Interrupt Mask Register Priority Queue (index = 1)"
|
|
bitfld.long 0x0 11. "HRESP,HRESP Not OK" "0,1"
|
|
bitfld.long 0x0 7. "TCOMP,Transmit Complete" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "AHB,AHB Error" "0,1"
|
|
bitfld.long 0x0 5. "RLEX,Retry Limit Exceeded or Late Collision" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXUBR,RX Used Bit Read" "0,1"
|
|
bitfld.long 0x0 1. "RCOMP,Receive Complete" "0,1"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x6E0)++0x3
|
|
line.long 0x0 "ST2ER[$1],Screening Type 2 Ethertype Register (index = 0)"
|
|
hexmask.long.word 0x0 0.--15. 1. "COMPVAL,Ethertype Compare Value"
|
|
repeat.end
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0xE2804700 ad:0xE2804708 ad:0xE2804710 ad:0xE2804718 ad:0xE2804720 ad:0xE2804728 ad:0xE2804730 ad:0xE2804738 ad:0xE2804740 ad:0xE2804748 ad:0xE2804750 ad:0xE2804758 ad:0xE2804760 ad:0xE2804768 ad:0xE2804770 ad:0xE2804778)
|
|
tree "GMAC_ST2CW[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "ST2CW0R,Screening Type 2 Compare Word 0 Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "COMPVAL,Compare Value"
|
|
hexmask.long.word 0x0 0.--15. 1. "MASKVAL,Mask Value"
|
|
line.long 0x4 "ST2CW1R,Screening Type 2 Compare Word 1 Register"
|
|
bitfld.long 0x4 9. "DISMASK,Disable Mask" "0: GMAC_ST2CW0x contains a 2-byte compare value..,1: GMAC_ST2CW0x contains a 4-byte compare value."
|
|
bitfld.long 0x4 7.--8. "OFFSSTRT,Ethernet Frame Offset Start" "0: Offset from the start of the frame,1: Offset from the byte after the EtherType field,2: Offset from the byte after the IP header field,3: Offset from the byte after the TCP/UDP header.."
|
|
hexmask.long.byte 0x4 0.--6. 1. "OFFSVAL,Offset Value in Bytes"
|
|
tree.end
|
|
repeat.end
|
|
repeat 8. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17)(list ad:0xE2804780 ad:0xE2804788 ad:0xE2804790 ad:0xE2804798 ad:0xE28047A0 ad:0xE28047A8 ad:0xE28047B0 ad:0xE28047B8)
|
|
tree "GMAC_ST2CW[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "ST2CW0R,Screening Type 2 Compare Word 0 Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "COMPVAL,Compare Value"
|
|
hexmask.long.word 0x0 0.--15. 1. "MASKVAL,Mask Value"
|
|
line.long 0x4 "ST2CW1R,Screening Type 2 Compare Word 1 Register"
|
|
bitfld.long 0x4 9. "DISMASK,Disable Mask" "0: GMAC_ST2CW0x contains a 2-byte compare value..,1: GMAC_ST2CW0x contains a 4-byte compare value."
|
|
bitfld.long 0x4 7.--8. "OFFSSTRT,Ethernet Frame Offset Start" "0: Offset from the start of the frame,1: Offset from the byte after the EtherType field,2: Offset from the byte after the IP header field,3: Offset from the byte after the TCP/UDP header.."
|
|
hexmask.long.byte 0x4 0.--6. 1. "OFFSVAL,Offset Value in Bytes"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree.end
|
|
tree "GPBR (General Purpose Backup Registers)"
|
|
base ad:0xE001D060
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "MR,GPBR Mode Register"
|
|
bitfld.long 0x0 17. "GPBRRP1,GPBRx Read Protection" "0: The content of the corresponding GPBR register..,1: The corresponding GPBR register (32-bit.."
|
|
bitfld.long 0x0 16. "GPBRRP0,GPBRx Read Protection" "0: The content of the corresponding GPBR register..,1: The corresponding GPBR register (32-bit.."
|
|
newline
|
|
bitfld.long 0x0 1. "GPBRWP1,GPBRx Write Protection" "0: The corresponding GPBR register (32-bit..,1: The corresponding GPBR register (32-bit.."
|
|
bitfld.long 0x0 0. "GPBRWP0,GPBRx Write Protection" "0: The corresponding GPBR register (32-bit..,1: The corresponding GPBR register (32-bit.."
|
|
line.long 0x4 "FCLR,GPBR Full Clear Register"
|
|
bitfld.long 0x4 0. "FCLR,Full Clear Enable" "0: SYS_GPBR0 to SYS_GPBR1 are immediately cleared..,1: All SYS_GPBRx are immediately cleared in case of.."
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x8)++0x3
|
|
line.long 0x0 "SYS_GPBR[$1],General Purpose Backup Register x"
|
|
hexmask.long 0x0 0.--31. 1. "GPBR_VALUE,Value of SYS_GPBRx"
|
|
repeat.end
|
|
tree.end
|
|
tree "HSMC (Static Memory Controller)"
|
|
base ad:0xE0808000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "HSMC_CFG,NFC Configuration Register"
|
|
hexmask.long.byte 0x0 24.--30. 1. "NFCSPARESIZE,NAND Flash Spare Area Size Retrieved by the Host Controller"
|
|
bitfld.long 0x0 20.--22. "DTOMUL,Data Timeout Multiplier" "0: DTOCYC,1: DTOCYC x 16,2: DTOCYC x 128,3: DTOCYC x 256,4: DTOCYC x 1024,5: DTOCYC x 4096,6: DTOCYC x 65536,7: DTOCYC x 1048576"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "DTOCYC,Data Timeout Cycle Number"
|
|
bitfld.long 0x0 13. "RBEDGE,Ready/Busy Signal Edge Detection" "0: RBEDGE indicates the level of the Ready/Busy line.,1: RBEDGE indicates a transition has occurred on.."
|
|
newline
|
|
bitfld.long 0x0 12. "EDGECTRL,Rising/Falling Edge Detection Control" "0: Rising edge is detected,1: Falling edge is detected"
|
|
bitfld.long 0x0 9. "RSPARE,Read Spare Area" "0: The NFC skips the spare area in Read mode.,1: The NFC reads both main area and spare area in.."
|
|
newline
|
|
bitfld.long 0x0 8. "WSPARE,Write Spare Area" "0: The NFC skips the spare area in Write mode.,1: The NFC writes both main area and spare area in.."
|
|
bitfld.long 0x0 0.--2. "PAGESIZE,Page Size of the NAND Flash Device" "0: Main area 512 bytes,1: Main area 1024 bytes,2: Main area 2048 bytes,3: Main area 4096 bytes,4: Main area 8192 bytes,?,?,?"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "HSMC_CTRL,NFC Control Register"
|
|
bitfld.long 0x0 1. "NFCDIS,NAND Flash Controller Disable" "0: No effect,1: Disable the NAND Flash controller."
|
|
bitfld.long 0x0 0. "NFCEN,NAND Flash Controller Enable" "0: No effect,1: Enable the NAND Flash controller."
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "HSMC_SR,NFC Status Register"
|
|
bitfld.long 0x0 24. "RB_EDGE0,Ready/Busy Line 0 Edge Detected" "0,1"
|
|
bitfld.long 0x0 23. "NFCASE,NFC Access Size Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "AWB,Accessing While Busy" "0,1"
|
|
bitfld.long 0x0 21. "UNDEF,Undefined Area Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "DTOE,Data Timeout Error" "0,1"
|
|
bitfld.long 0x0 17. "CMDDONE,Command Done" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "XFRDONE,NFC Data Transfer Terminated" "0,1"
|
|
bitfld.long 0x0 12.--14. "NFCSID,NFC Chip Select ID (this field cannot be reset)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 11. "NFCWR,NFC Write/Read Operation (this field cannot be reset)" "0,1"
|
|
bitfld.long 0x0 8. "NFCBUSY,NFC Busy (this field cannot be reset)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RB_FALL,Selected Ready Busy Falling Edge Detected" "0,1"
|
|
bitfld.long 0x0 4. "RB_RISE,Selected Ready Busy Rising Edge Detected" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SMCSTS,NAND Flash Controller Status (this field cannot be reset)" "0: NAND Flash Controller disabled,1: NAND Flash Controller enabled"
|
|
wgroup.long 0xC++0x7
|
|
line.long 0x0 "HSMC_IER,NFC Interrupt Enable Register"
|
|
bitfld.long 0x0 24. "RB_EDGE0,Ready/Busy Line 0 Interrupt Enable" "0: No effect,1: Interrupt source enabled"
|
|
bitfld.long 0x0 23. "NFCASE,NFC Access Size Error Interrupt Enable" "0: No effect,1: Interrupt source enabled"
|
|
newline
|
|
bitfld.long 0x0 22. "AWB,Accessing While Busy Interrupt Enable" "0: No effect,1: Interrupt source enabled"
|
|
bitfld.long 0x0 21. "UNDEF,Undefined Area Access Interrupt Enable" "0: No effect,1: Interrupt source enabled"
|
|
newline
|
|
bitfld.long 0x0 20. "DTOE,Data Timeout Error Interrupt Enable" "0: No effect,1: Interrupt source enabled"
|
|
bitfld.long 0x0 17. "CMDDONE,Command Done Interrupt Enable" "0: No effect,1: Interrupt source enabled"
|
|
newline
|
|
bitfld.long 0x0 16. "XFRDONE,Transfer Done Interrupt Enable" "0: No effect,1: Interrupt source enabled"
|
|
bitfld.long 0x0 5. "RB_FALL,Ready Busy Falling Edge Detection Interrupt Enable" "0: No effect,1: Interrupt source enabled"
|
|
newline
|
|
bitfld.long 0x0 4. "RB_RISE,Ready Busy Rising Edge Detection Interrupt Enable" "0: No effect,1: Interrupt source enabled"
|
|
line.long 0x4 "HSMC_IDR,NFC Interrupt Disable Register"
|
|
bitfld.long 0x4 24. "RB_EDGE0,Ready/Busy Line 0 Interrupt Disable" "0: No effect,1: Interrupt source disabled"
|
|
bitfld.long 0x4 23. "NFCASE,NFC Access Size Error Interrupt Disable" "0: No effect,1: Interrupt source disabled"
|
|
newline
|
|
bitfld.long 0x4 22. "AWB,Accessing While Busy Interrupt Disable" "0: No effect,1: Interrupt source disabled"
|
|
bitfld.long 0x4 21. "UNDEF,Undefined Area Access Interrupt Disable" "0: No effect,1: Interrupt source disabled"
|
|
newline
|
|
bitfld.long 0x4 20. "DTOE,Data Timeout Error Interrupt Disable" "0: No effect,1: Interrupt source disabled"
|
|
bitfld.long 0x4 17. "CMDDONE,Command Done Interrupt Disable" "0: No effect,1: Interrupt source disabled"
|
|
newline
|
|
bitfld.long 0x4 16. "XFRDONE,Transfer Done Interrupt Disable" "0: No effect,1: Interrupt source disabled"
|
|
bitfld.long 0x4 5. "RB_FALL,Ready Busy Falling Edge Detection Interrupt Disable" "0: No effect,1: Interrupt source disabled"
|
|
newline
|
|
bitfld.long 0x4 4. "RB_RISE,Ready Busy Rising Edge Detection Interrupt Disable" "0: No effect,1: Interrupt source disabled"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "HSMC_IMR,NFC Interrupt Mask Register"
|
|
bitfld.long 0x0 24. "RB_EDGE0,Ready/Busy Line 0 Interrupt Mask" "0: Interrupt source disabled,1: Interrupt source enabled"
|
|
bitfld.long 0x0 23. "NFCASE,NFC Access Size Error Interrupt Mask" "0: Interrupt source disabled,1: Interrupt source enabled"
|
|
newline
|
|
bitfld.long 0x0 22. "AWB,Accessing While Busy Interrupt Mask" "0: Interrupt source disabled,1: Interrupt source enabled"
|
|
bitfld.long 0x0 21. "UNDEF,Undefined Area Access Interrupt Mask5" "0: Interrupt source disabled,1: Interrupt source enabled"
|
|
newline
|
|
bitfld.long 0x0 20. "DTOE,Data Timeout Error Interrupt Mask" "0: Interrupt source disabled,1: Interrupt source enabled"
|
|
bitfld.long 0x0 17. "CMDDONE,Command Done Interrupt Mask" "0: Interrupt source disabled,1: Interrupt source enabled"
|
|
newline
|
|
bitfld.long 0x0 16. "XFRDONE,Transfer Done Interrupt Mask" "0: Interrupt source disabled,1: Interrupt source enabled"
|
|
bitfld.long 0x0 5. "RB_FALL,Ready Busy Falling Edge Detection Interrupt Mask" "0: Interrupt source disabled,1: Interrupt source enabled"
|
|
newline
|
|
bitfld.long 0x0 4. "RB_RISE,Ready Busy Rising Edge Detection Interrupt Mask" "0: Interrupt source disabled,1: Interrupt source enabled"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "HSMC_ADDR,NFC Address Cycle Zero Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ADDR_CYCLE0,NAND Flash Array Address Cycle 0"
|
|
line.long 0x4 "HSMC_BANK,Bank Address Register"
|
|
bitfld.long 0x4 0. "BANK,Bank Identifier" "0: Bank 0 is used.,1: Bank 1 is used."
|
|
group.long 0x70++0xF
|
|
line.long 0x0 "HSMC_PMECCFG,PMECC Configuration Register"
|
|
bitfld.long 0x0 20. "AUTO,Automatic Mode Enable" "0: Indicates that the spare area is not protected.,1: Indicates that the spare area is.."
|
|
bitfld.long 0x0 16. "SPAREEN,Spare Enable" "0: The spare area is skipped.,1: The spare area contains protected data or only.."
|
|
newline
|
|
bitfld.long 0x0 12. "NANDWR,NAND Write Access" "0: NAND read access,1: NAND write access"
|
|
bitfld.long 0x0 8.--9. "PAGESIZE,Number of Sectors in the Page" "0: 1 sector for main area (512 or 1024 bytes),1: 2 sectors for main area (1024 or 2048 bytes),2: 4 sectors for main area (2048 or 4096 bytes),3: 8 sectors for main area (4096 or 8192 bytes)"
|
|
newline
|
|
bitfld.long 0x0 4. "SECTORSZ,Sector Size" "0: The ECC computation is based on a sector of 512..,1: The ECC computation is based on a sector of 1024.."
|
|
bitfld.long 0x0 0.--2. "BCH_ERR,Error Correcting Capability" "0: 2 errors,1: 4 errors,2: 8 errors,3: 12 errors,4: 24 errors,5: 32 errors,?,?"
|
|
line.long 0x4 "HSMC_PMECCSAREA,PMECC Spare Area Size Register"
|
|
hexmask.long.word 0x4 0.--8. 1. "SPARESIZE,Spare Area Size"
|
|
line.long 0x8 "HSMC_PMECCSADDR,PMECC Start Address Register"
|
|
hexmask.long.word 0x8 0.--8. 1. "STARTADDR,ECC Area Start Address"
|
|
line.long 0xC "HSMC_PMECCEADDR,PMECC End Address Register"
|
|
hexmask.long.word 0xC 0.--8. 1. "ENDADDR,ECC Area End Address"
|
|
wgroup.long 0x84++0x3
|
|
line.long 0x0 "HSMC_PMECCTRL,PMECC Control Register"
|
|
bitfld.long 0x0 5. "DISABLE,PMECC Enable" "0: No effect,1: Disable the PMECC controller."
|
|
bitfld.long 0x0 4. "ENABLE,PMECC Enable" "0: No effect,1: Enable the PMECC controller."
|
|
newline
|
|
bitfld.long 0x0 2. "USER,Start a User Mode Phase" "0: No effect,1: The PMECC controller enters a User mode phase."
|
|
bitfld.long 0x0 1. "DATA,Start a Data Phase" "0: No effect,1: The PMECC controller enters a Data phase."
|
|
newline
|
|
bitfld.long 0x0 0. "RST,Reset the PMECC Module" "0: No effect,1: Reset the PMECC controller."
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "HSMC_PMECCSR,PMECC Status Register"
|
|
bitfld.long 0x0 4. "ENABLE,PMECC Enable bit" "0: PMECC controller disabled,1: PMECC controller enabled"
|
|
bitfld.long 0x0 0. "BUSY,The kernel of the PMECC is busy" "0: PMECC controller finite state machine reached..,1: PMECC controller finite state machine is.."
|
|
wgroup.long 0x8C++0x7
|
|
line.long 0x0 "HSMC_PMECCIER,PMECC Interrupt Enable register"
|
|
bitfld.long 0x0 0. "ERRIE,Error Interrupt Enable" "0: No effect,1: The Multibit Error interrupt is enabled. An.."
|
|
line.long 0x4 "HSMC_PMECCIDR,PMECC Interrupt Disable Register"
|
|
bitfld.long 0x4 0. "ERRID,Error Interrupt Disable" "0: No effect,1: Multibit Error interrupt disabled"
|
|
rgroup.long 0x94++0x7
|
|
line.long 0x0 "HSMC_PMECCIMR,PMECC Interrupt Mask Register"
|
|
bitfld.long 0x0 0. "ERRIM,Error Interrupt Mask" "0: Multibit Error disabled,1: Multibit Error enabled"
|
|
line.long 0x4 "HSMC_PMECCISR,PMECC Interrupt Status Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "ERRIS,Error Interrupt Status Register"
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0xE08080B0 ad:0xE08080F0 ad:0xE0808130 ad:0xE0808170 ad:0xE08081B0 ad:0xE08081F0 ad:0xE0808230 ad:0xE0808270)
|
|
tree "SMC_PMECC[$1]"
|
|
base $2
|
|
repeat 14. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "HSMC_PMECC[$1],PMECC Redundancy x Register"
|
|
hexmask.long 0x0 0.--31. 1. "ECC,BCH Redundancy"
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0xE08082B0 ad:0xE08082F0 ad:0xE0808330 ad:0xE0808370 ad:0xE08083B0 ad:0xE08083F0 ad:0xE0808430 ad:0xE0808470)
|
|
tree "SMC_REM[$1]"
|
|
base $2
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "HSMC_REM[$1],PMECC Remainder x Register"
|
|
hexmask.long.word 0x0 16.--29. 1. "REM2NP3,BCH Remainder 2 * N + 3"
|
|
hexmask.long.word 0x0 0.--13. 1. "REM2NP1,BCH Remainder 2 * N + 1"
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
base ad:0xE0808000
|
|
group.long 0x500++0x3
|
|
line.long 0x0 "HSMC_ELCFG,PMECC Error Location Configuration Register"
|
|
hexmask.long.byte 0x0 16.--20. 1. "ERRNUM,Number of Errors"
|
|
bitfld.long 0x0 0. "SECTORSZ,Sector Size" "0: The ECC computation is based on a 512 bytes..,1: The ECC computation is based on a 1024 bytes.."
|
|
rgroup.long 0x504++0x3
|
|
line.long 0x0 "HSMC_ELPRIM,PMECC Error Location Primitive Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "PRIMITIV,Primitive Polynomial"
|
|
wgroup.long 0x508++0x7
|
|
line.long 0x0 "HSMC_ELEN,PMECC Error Location Enable Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "ENINIT,Error Location Enable"
|
|
line.long 0x4 "HSMC_ELDIS,PMECC Error Location Disable Register"
|
|
bitfld.long 0x4 0. "DIS,Disable Error Location Engine" "0: No effect,1: Disable the Error location engine."
|
|
rgroup.long 0x510++0x3
|
|
line.long 0x0 "HSMC_ELSR,PMECC Error Location Status Register"
|
|
bitfld.long 0x0 0. "BUSY,Error Location Engine Busy" "0: Error location engine is disabled.,1: Error location engine is enabled and is finding.."
|
|
wgroup.long 0x514++0x7
|
|
line.long 0x0 "HSMC_ELIER,PMECC Error Location Interrupt Enable register"
|
|
bitfld.long 0x0 0. "DONE,Computation Terminated Interrupt Enable" "0: No effect,1: Interrupt enable"
|
|
line.long 0x4 "HSMC_ELIDR,PMECC Error Location Interrupt Disable Register"
|
|
bitfld.long 0x4 0. "DONE,Computation Terminated Interrupt Disable" "0: No effect,1: Interrupt disable."
|
|
rgroup.long 0x51C++0x7
|
|
line.long 0x0 "HSMC_ELIMR,PMECC Error Location Interrupt Mask Register"
|
|
bitfld.long 0x0 0. "DONE,Computation Terminated Interrupt Mask" "0: Computation Terminated interrupt disabled,1: Computation Terminated interrupt enabled"
|
|
line.long 0x4 "HSMC_ELISR,PMECC Error Location Interrupt Status Register"
|
|
hexmask.long.byte 0x4 8.--13. 1. "ERR_CNT,Error Counter value"
|
|
bitfld.long 0x4 0. "DONE,Computation Terminated Interrupt Status" "0,1"
|
|
rgroup.long 0x528++0x3
|
|
line.long 0x0 "HSMC_SIGMA0,PMECC Error Location SIGMA 0 Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "SIGMA0,Coefficient of degree 0 in the SIGMA polynomial"
|
|
group.long 0x52C++0x7F
|
|
line.long 0x0 "HSMC_SIGMA1,PMECC Error Location SIGMA 1 Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "SIGMA1,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x4 "HSMC_SIGMA2,PMECC Error Location SIGMA 2 Register"
|
|
hexmask.long.word 0x4 0.--13. 1. "SIGMA2,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x8 "HSMC_SIGMA3,PMECC Error Location SIGMA 3 Register"
|
|
hexmask.long.word 0x8 0.--13. 1. "SIGMA3,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0xC "HSMC_SIGMA4,PMECC Error Location SIGMA 4 Register"
|
|
hexmask.long.word 0xC 0.--13. 1. "SIGMA4,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x10 "HSMC_SIGMA5,PMECC Error Location SIGMA 5 Register"
|
|
hexmask.long.word 0x10 0.--13. 1. "SIGMA5,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x14 "HSMC_SIGMA6,PMECC Error Location SIGMA 6 Register"
|
|
hexmask.long.word 0x14 0.--13. 1. "SIGMA6,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x18 "HSMC_SIGMA7,PMECC Error Location SIGMA 7 Register"
|
|
hexmask.long.word 0x18 0.--13. 1. "SIGMA7,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x1C "HSMC_SIGMA8,PMECC Error Location SIGMA 8 Register"
|
|
hexmask.long.word 0x1C 0.--13. 1. "SIGMA8,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x20 "HSMC_SIGMA9,PMECC Error Location SIGMA 9 Register"
|
|
hexmask.long.word 0x20 0.--13. 1. "SIGMA9,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x24 "HSMC_SIGMA10,PMECC Error Location SIGMA 10 Register"
|
|
hexmask.long.word 0x24 0.--13. 1. "SIGMA10,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x28 "HSMC_SIGMA11,PMECC Error Location SIGMA 11 Register"
|
|
hexmask.long.word 0x28 0.--13. 1. "SIGMA11,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x2C "HSMC_SIGMA12,PMECC Error Location SIGMA 12 Register"
|
|
hexmask.long.word 0x2C 0.--13. 1. "SIGMA12,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x30 "HSMC_SIGMA13,PMECC Error Location SIGMA 13 Register"
|
|
hexmask.long.word 0x30 0.--13. 1. "SIGMA13,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x34 "HSMC_SIGMA14,PMECC Error Location SIGMA 14 Register"
|
|
hexmask.long.word 0x34 0.--13. 1. "SIGMA14,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x38 "HSMC_SIGMA15,PMECC Error Location SIGMA 15 Register"
|
|
hexmask.long.word 0x38 0.--13. 1. "SIGMA15,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x3C "HSMC_SIGMA16,PMECC Error Location SIGMA 16 Register"
|
|
hexmask.long.word 0x3C 0.--13. 1. "SIGMA16,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x40 "HSMC_SIGMA17,PMECC Error Location SIGMA 17 Register"
|
|
hexmask.long.word 0x40 0.--13. 1. "SIGMA17,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x44 "HSMC_SIGMA18,PMECC Error Location SIGMA 18 Register"
|
|
hexmask.long.word 0x44 0.--13. 1. "SIGMA18,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x48 "HSMC_SIGMA19,PMECC Error Location SIGMA 19 Register"
|
|
hexmask.long.word 0x48 0.--13. 1. "SIGMA19,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x4C "HSMC_SIGMA20,PMECC Error Location SIGMA 20 Register"
|
|
hexmask.long.word 0x4C 0.--13. 1. "SIGMA20,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x50 "HSMC_SIGMA21,PMECC Error Location SIGMA 21 Register"
|
|
hexmask.long.word 0x50 0.--13. 1. "SIGMA21,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x54 "HSMC_SIGMA22,PMECC Error Location SIGMA 22 Register"
|
|
hexmask.long.word 0x54 0.--13. 1. "SIGMA22,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x58 "HSMC_SIGMA23,PMECC Error Location SIGMA 23 Register"
|
|
hexmask.long.word 0x58 0.--13. 1. "SIGMA23,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x5C "HSMC_SIGMA24,PMECC Error Location SIGMA 24 Register"
|
|
hexmask.long.word 0x5C 0.--13. 1. "SIGMA24,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x60 "HSMC_SIGMA25,PMECC Error Location SIGMA 25 Register"
|
|
hexmask.long.word 0x60 0.--13. 1. "SIGMA25,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x64 "HSMC_SIGMA26,PMECC Error Location SIGMA 26 Register"
|
|
hexmask.long.word 0x64 0.--13. 1. "SIGMA26,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x68 "HSMC_SIGMA27,PMECC Error Location SIGMA 27 Register"
|
|
hexmask.long.word 0x68 0.--13. 1. "SIGMA27,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x6C "HSMC_SIGMA28,PMECC Error Location SIGMA 28 Register"
|
|
hexmask.long.word 0x6C 0.--13. 1. "SIGMA28,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x70 "HSMC_SIGMA29,PMECC Error Location SIGMA 29 Register"
|
|
hexmask.long.word 0x70 0.--13. 1. "SIGMA29,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x74 "HSMC_SIGMA30,PMECC Error Location SIGMA 30 Register"
|
|
hexmask.long.word 0x74 0.--13. 1. "SIGMA30,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x78 "HSMC_SIGMA31,PMECC Error Location SIGMA 31 Register"
|
|
hexmask.long.word 0x78 0.--13. 1. "SIGMA31,Coefficient of degree x in the SIGMA polynomial"
|
|
line.long 0x7C "HSMC_SIGMA32,PMECC Error Location SIGMA 32 Register"
|
|
hexmask.long.word 0x7C 0.--13. 1. "SIGMA32,Coefficient of degree x in the SIGMA polynomial"
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x5AC)++0x3
|
|
line.long 0x0 "HSMC_ERRLOC[$1],PMECC Error Location x Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "ERRLOCN,Error Position within the Set {sector area spare area}"
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0xE0808700 ad:0xE0808714 ad:0xE0808728 ad:0xE080873C)
|
|
tree "SMC_CS_NUMBER[$1]"
|
|
base $2
|
|
group.long ($2)++0x13
|
|
line.long 0x0 "HSMC_SETUP,Setup Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "NCS_RD_SETUP,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x0 16.--21. 1. "NRD_SETUP,NRD Setup Length"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "NCS_WR_SETUP,NCS Setup Length in Write Access"
|
|
hexmask.long.byte 0x0 0.--5. 1. "NWE_SETUP,NWE Setup Length"
|
|
line.long 0x4 "HSMC_PULSE,Pulse Register"
|
|
hexmask.long.byte 0x4 24.--30. 1. "NCS_RD_PULSE,NCS Pulse Length in READ Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. "NRD_PULSE,NRD Pulse Length"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--14. 1. "NCS_WR_PULSE,NCS Pulse Length in WRITE Access"
|
|
hexmask.long.byte 0x4 0.--6. 1. "NWE_PULSE,NWE Pulse Length"
|
|
line.long 0x8 "HSMC_CYCLE,Cycle Register"
|
|
hexmask.long.word 0x8 16.--24. 1. "NRD_CYCLE,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. "NWE_CYCLE,Total Write Cycle Length"
|
|
line.long 0xC "HSMC_TIMINGS,Timings Register"
|
|
bitfld.long 0xC 31. "NFSEL,NAND Flash Selection" "0,1"
|
|
hexmask.long.byte 0xC 24.--27. 1. "TWB,WEN High to REN to Busy"
|
|
newline
|
|
hexmask.long.byte 0xC 16.--19. 1. "TRR,Ready to REN Low Delay"
|
|
bitfld.long 0xC 12. "OCMS,Off Chip Memory Scrambling Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--11. 1. "TAR,ALE to REN Low Delay"
|
|
hexmask.long.byte 0xC 4.--7. 1. "TADL,ALE to Data Start"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--3. 1. "TCLR,CLE to REN Low Delay"
|
|
line.long 0x10 "HSMC_MODE,Mode Register"
|
|
bitfld.long 0x10 20. "TDF_MODE,TDF Optimization" "0: TDF optimization disabled,1: TDF optimization enabled"
|
|
hexmask.long.byte 0x10 16.--19. 1. "TDF_CYCLES,Data Float Time"
|
|
newline
|
|
bitfld.long 0x10 12. "DBW,Data Bus Width" "0: 8-bit bus,1: 16-bit bus"
|
|
bitfld.long 0x10 8. "BAT,Byte Access Type" "0: Byte select access type: - Write operation is..,1: Byte write access type: - Write operation is.."
|
|
newline
|
|
bitfld.long 0x10 4.--5. "EXNW_MODE,NWAIT Mode" "0: Disabled-The NWAIT input signal is ignored on..,?,2: Frozen Mode-If asserted the NWAIT signal freezes..,3: Ready Mode-The NWAIT signal indicates the.."
|
|
bitfld.long 0x10 1. "WRITE_MODE,Selection of the Control Signal for Write Operation" "0: The Write operation is controller by the NCS..,1: The Write operation is controlled by the NWE.."
|
|
newline
|
|
bitfld.long 0x10 0. "READ_MODE,Selection of the Control Signal for Read Operation" "0: The Read operation is controlled by the NCS..,1: The Read operation is controlled by the NRD.."
|
|
tree.end
|
|
repeat.end
|
|
base ad:0xE0808000
|
|
group.long 0x7A0++0x3
|
|
line.long 0x0 "HSMC_OCMS,Off Chip Memory Scrambling Register"
|
|
bitfld.long 0x0 1. "SRSE,NFC Internal SRAM Scrambling Enable" "0: Disable Scrambling for NFC internal SRAM access.,1: Enable Scrambling for NFC internal SRAM access."
|
|
bitfld.long 0x0 0. "SMSE,Static Memory Controller Scrambling Enable" "0: Disable 'Off Chip' Scrambling for SMC access.,1: Enable 'Off Chip' Scrambling for SMC access. (If.."
|
|
wgroup.long 0x7A4++0x7
|
|
line.long 0x0 "HSMC_KEY1,Off Chip Memory Scrambling KEY1 Register"
|
|
hexmask.long 0x0 0.--31. 1. "KEY1,Off Chip Memory Scrambling (OCMS) Key Part 1"
|
|
line.long 0x4 "HSMC_KEY2,Off Chip Memory Scrambling KEY2 Register"
|
|
hexmask.long 0x4 0.--31. 1. "KEY2,Off Chip Memory Scrambling (OCMS) Key Part 2"
|
|
group.long 0x7AC++0x3
|
|
line.long 0x0 "HSMC_CLKCFG,Clock Configuration Register"
|
|
bitfld.long 0x0 17. "CLKEDGE,SMC Clock Edge" "0,1"
|
|
bitfld.long 0x0 16. "CLKEN,SMC Clock Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "CLKDIV,SMC Clock Divider"
|
|
group.long 0x7E4++0x3
|
|
line.long 0x0 "HSMC_WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables write protection if WPKEY value..,1: Enables write protection if WPKEY value.."
|
|
rgroup.long 0x7E8++0x3
|
|
line.long 0x0 "HSMC_WPSR,Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0: No write protect violation has occurred since..,1: A write protect violation has occurred since the.."
|
|
tree.end
|
|
tree "I2SMCC (Inter-IC Sound Multi-Channel Controller)"
|
|
base ad:0x0
|
|
tree "I2SMCC0"
|
|
base ad:0xE161C000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0: No effect.,1: Resets all the registers in the I2SMCC. The.."
|
|
bitfld.long 0x0 5. "TXDIS,Transmitter Disable" "0: No effect.,1: Disables the I2SMCC transmitter. Bit.."
|
|
newline
|
|
bitfld.long 0x0 4. "TXEN,Transmitter Enable" "0: No effect.,1: Enables the I2SMCC transmitter if TXDIS is not.."
|
|
bitfld.long 0x0 3. "CKDIS,Clocks Disable" "0: No effect.,1: Disables the I2SMCC clock generation."
|
|
newline
|
|
bitfld.long 0x0 2. "CKEN,Clocks Enable" "0: No effect.,1: Enables the I2SMCC clock generation if CKDIS is.."
|
|
bitfld.long 0x0 1. "RXDIS,Receiver Disable" "0: No effect.,1: Disables the I2SMCC receiver. Bit I2SMCC_SR.RXEN.."
|
|
newline
|
|
bitfld.long 0x0 0. "RXEN,Receiver Enable" "0: No effect.,1: Enables the I2SMCC receiver if RXDIS is not '1'."
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "MRA,Mode Register A"
|
|
bitfld.long 0x0 31. "IWS,I2SMCC_WS Slot Length" "0: I2SMCC_WS slot is 32 bits long for DATALENGTH =..,1: I2SMCC_WS slot is 24 bits long for DATALENGTH =.."
|
|
bitfld.long 0x0 30. "IMCKMODE,Master Clock Mode" "0: No master clock generated.,1: Master clock generated."
|
|
newline
|
|
hexmask.long.byte 0x0 24.--29. 1. "ISCKDIV,Selected Clock to I2SMCC Serial Clock Ratio"
|
|
bitfld.long 0x0 22.--23. "TDMFS,TDM Frame Synchronization" "0: I2SMCC_WS pulse is high for one time slot at..,1: I2SMCC_WS pulse is high for half the time slots..,2: I2SMCC_WS pulse is high for one bit period at..,?"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "IMCKDIV,Selected Clock to I2SMCC Master Clock Ratio"
|
|
bitfld.long 0x0 13.--15. "NBCHAN,Number of TDM Channels-1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 12. "SRCCLK,Source Clock Selection" "0: The Peripheral clock is selected as source clock.,1: The PMC.GCLKx clock is selected as source clock."
|
|
bitfld.long 0x0 11. "TXSAME,Transmit Data when Underrun" "0: '0' is transmitted when underrun.,1: Previous sample transmitted when underrun."
|
|
newline
|
|
bitfld.long 0x0 10. "TXMONO,Transmit Mono" "0: Stereo.,1: Mono with left audio samples duplicated to right.."
|
|
bitfld.long 0x0 9. "RXLOOP,Loop-back Test Mode" "0: Normal mode.,1: I2SMCC_DOUT outputs of I2SMCC are internally.."
|
|
newline
|
|
bitfld.long 0x0 8. "RXMONO,Receive Mono" "0: Stereo.,1: Mono with left audio samples duplicated to right.."
|
|
bitfld.long 0x0 6.--7. "FORMAT,Data Format" "0: I2S format stereo with I2SMCC_WS low for left..,1: Left-justified format stereo with I2SMCC_WS high..,2: TDM format with (NBCHAN + 1) channels I2SMCC_WS..,3: TDM format left-justified with (NBCHAN + 1).."
|
|
newline
|
|
bitfld.long 0x0 4.--5. "WIRECFG,Wire Configuration" "0: In I2S and LJ formats I2SMCC_DIN0 and..,1: In I2S and LJ formats I2SMCC_DIN1..0 and..,2: In I2S and LJ formats I2SMCC_DIN3..0 and..,3: In I2S and LJ formats reserved for future use do.."
|
|
bitfld.long 0x0 1.--3. "DATALENGTH,Data Word Length" "0: Data length is set to 32 bits.,1: Data length is set to 24 bits.,2: Data length is set to 20 bits.,3: Data length is set to 18 bits.,4: Data length is set to 16 bits.,5: Data length is set to 16-bit compact stereo.,6: Data length is set to 8 bits.,7: Data length is set to 8-bit compact stereo. Left.."
|
|
newline
|
|
bitfld.long 0x0 0. "MODE,Inter-IC Sound Multi Channel Controller Mode" "0: I2SMCC_CK and I2SMCC_WS pin inputs used as bit..,1: Bit clock and word select/frame synchronization.."
|
|
line.long 0x4 "MRB,Mode Register B"
|
|
bitfld.long 0x4 16. "CLKSEL,Serial Clock Selection" "0: The I2SMCC_CK clock (provided by the external..,1: The internal clock (generated from source clock).."
|
|
bitfld.long 0x4 8.--9. "DMACHUNK,DMA Chunk Size" "0: Each DMA transfer contains 1 word.,1: Each DMA transfer contains 2 words.,2: Each DMA transfer contains 4 words.,3: Each DMA transfer contains 8 words."
|
|
newline
|
|
bitfld.long 0x4 4. "FIFOEN,FIFO Enable" "0: The Receive and Transmit FIFOs are disabled.,1: The Receive and Transmit FIFOs are enabled."
|
|
bitfld.long 0x4 0. "CRAMODE,Common Register Access Mode" "0: All enabled I2S left channels are filled first..,1: An enabled I2S left channel is filled then the.."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 4. "TXEN,Transmitter Enabled" "0: Cleared when the transmitter is disabled..,1: Set when the transmitter is enabled following a.."
|
|
bitfld.long 0x0 0. "RXEN,Receiver Enabled" "0: Cleared when the receiver is disabled following..,1: Set when the receiver is enabled following a.."
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IERA,Interrupt Enable Register A"
|
|
bitfld.long 0x0 31. "RXROVF3,I2S Receive Right 3 or TDM Channel [2x]+1 Overrun Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 30. "RXLOVF3,I2S Receive Left 3 or TDM Channel 2x Overrun Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXROVF2,I2S Receive Right 2 or TDM Channel [2x]+1 Overrun Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 28. "RXLOVF2,I2S Receive Left 2 or TDM Channel 2x Overrun Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXROVF1,I2S Receive Right 1 or TDM Channel [2x]+1 Overrun Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 26. "RXLOVF1,I2S Receive Left 1 or TDM Channel 2x Overrun Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 25. "RXROVF0,I2S Receive Right 0 or TDM Channel [2x]+1 Overrun Interrupt Enable" "0,1"
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bitfld.long 0x0 24. "RXLOVF0,I2S Receive Left 0 or TDM Channel 2x Overrun Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 23. "RXRRDY3,I2S Receive Right 3 or TDM Channel [2x]+1 Ready Interrupt Enable" "0,1"
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bitfld.long 0x0 22. "RXLRDY3,I2S Receive Left 3 or TDM Channel 2x Ready Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 21. "RXRRDY2,I2S Receive Right 2 or TDM Channel [2x]+1 Ready Interrupt Enable" "0,1"
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bitfld.long 0x0 20. "RXLRDY2,I2S Receive Left 2 or TDM Channel 2x Ready Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 19. "RXRRDY1,I2S Receive Right 1 or TDM Channel [2x]+1 Ready Interrupt Enable" "0,1"
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bitfld.long 0x0 18. "RXLRDY1,I2S Receive Left 1 or TDM Channel 2x Ready Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 17. "RXRRDY0,I2S Receive Right 0 or TDM Channel [2x]+1 Ready Interrupt Enable" "0,1"
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bitfld.long 0x0 16. "RXLRDY0,I2S Receive Left 0 or TDM Channel 2x Ready Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 15. "TXRUNF3,I2S Transmit Right 3 or TDM Channel [2x]+1 Underrun Interrupt Enable" "0,1"
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bitfld.long 0x0 14. "TXLUNF3,I2S Transmit Left 3 or TDM Channel 2x Underrun Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 13. "TXRUNF2,I2S Transmit Right 2 or TDM Channel [2x]+1 Underrun Interrupt Enable" "0,1"
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bitfld.long 0x0 12. "TXLUNF2,I2S Transmit Left 2 or TDM Channel 2x Underrun Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 11. "TXRUNF1,I2S Transmit Right 1 or TDM Channel [2x]+1 Underrun Interrupt Enable" "0,1"
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bitfld.long 0x0 10. "TXLUNF1,I2S Transmit Left 1 or TDM Channel 2x Underrun Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 9. "TXRUNF0,I2S Transmit Right 0 or TDM Channel [2x]+1 Underrun Interrupt Enable" "0,1"
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bitfld.long 0x0 8. "TXLUNF0,I2S Transmit Left 0 or TDM Channel 2x Underrun Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 7. "TXRRDY3,I2S Transmit Right 3 or TDM Channel [2x]+1 Ready Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "TXLRDY3,I2S Transmit Left 3 or TDM Channel 2x ReadyInterrupt Enable" "0,1"
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newline
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bitfld.long 0x0 5. "TXRRDY2,I2S Transmit Right 2 or TDM Channel [2x]+1 Ready Interrupt Enable" "0,1"
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bitfld.long 0x0 4. "TXLRDY2,I2S Transmit Left 2 or TDM Channel 2x ReadyInterrupt Enable" "0,1"
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newline
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bitfld.long 0x0 3. "TXRRDY1,I2S Transmit Right 1 or TDM Channel [2x]+1 Ready Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "TXLRDY1,I2S Transmit Left 1 or TDM Channel 2x ReadyInterrupt Enable" "0,1"
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newline
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bitfld.long 0x0 1. "TXRRDY0,I2S Transmit Right 0 or TDM Channel [2x]+1 Ready Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "TXLRDY0,I2S Transmit Left 0 or TDM Channel 2x ReadyInterrupt Enable" "0,1"
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line.long 0x4 "IDRA,Interrupt Disable Register A"
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bitfld.long 0x4 31. "RXROVF3,I2S Receive Right 3 or TDM Channel [2x]+1 Overrun Interrupt Disable" "0,1"
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bitfld.long 0x4 30. "RXLOVF3,I2S Receive Left 3 or TDM Channel 2x Overrun Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 29. "RXROVF2,I2S Receive Right 2 or TDM Channel [2x]+1 Overrun Interrupt Disable" "0,1"
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bitfld.long 0x4 28. "RXLOVF2,I2S Receive Left 2 or TDM Channel 2x Overrun Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 27. "RXROVF1,I2S Receive Right 1 or TDM Channel [2x]+1 Overrun Interrupt Disable" "0,1"
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bitfld.long 0x4 26. "RXLOVF1,I2S Receive Left 1 or TDM Channel 2x Overrun Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 25. "RXROVF0,I2S Receive Right 0 or TDM Channel [2x]+1 Overrun Interrupt Disable" "0,1"
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bitfld.long 0x4 24. "RXLOVF0,I2S Receive Left 0 or TDM Channel 2x Overrun Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 23. "RXRRDY3,I2S Receive Right 3 or TDM Channel [2x]+1 Ready Interrupt Disable" "0,1"
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bitfld.long 0x4 22. "RXLRDY3,I2S Receive Left 3 or TDM Channel 2x Ready Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 21. "RXRRDY2,I2S Receive Right 2 or TDM Channel [2x]+1 Ready Interrupt Disable" "0,1"
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bitfld.long 0x4 20. "RXLRDY2,I2S Receive Left 2 or TDM Channel 2x Ready Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 19. "RXRRDY1,I2S Receive Right 1 or TDM Channel [2x]+1 Ready Interrupt Disable" "0,1"
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bitfld.long 0x4 18. "RXLRDY1,I2S Receive Left 1 or TDM Channel 2x Ready Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 17. "RXRRDY0,I2S Receive Right 0 or TDM Channel [2x]+1 Ready Interrupt Disable" "0,1"
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bitfld.long 0x4 16. "RXLRDY0,I2S Receive Left 0 or TDM Channel 2x Ready Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 15. "TXRUNF3,I2S Transmit Right 3 or TDM Channel [2x]+1 Underrun Interrupt Disable" "0,1"
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bitfld.long 0x4 14. "TXLUNF3,I2S Transmit Left 3 or TDM Channel 2x Underrun Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 13. "TXRUNF2,I2S Transmit Right 2 or TDM Channel [2x]+1 Underrun Interrupt Disable" "0,1"
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bitfld.long 0x4 12. "TXLUNF2,I2S Transmit Left 2 or TDM Channel 2x Underrun Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 11. "TXRUNF1,I2S Transmit Right 1 or TDM Channel [2x]+1 Underrun Interrupt Disable" "0,1"
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bitfld.long 0x4 10. "TXLUNF1,I2S Transmit Left 1 or TDM Channel 2x Underrun Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 9. "TXRUNF0,I2S Transmit Right 0 or TDM Channel [2x]+1 Underrun Interrupt Disable" "0,1"
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bitfld.long 0x4 8. "TXLUNF0,I2S Transmit Left 0 or TDM Channel 2x Underrun Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 7. "TXRRDY3,I2S Transmit Right 3 or TDM Channel [2x]+1 Ready Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "TXLRDY3,I2S Transmit Left 3 or TDM Channel 2x ReadyInterrupt Disable" "0,1"
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newline
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bitfld.long 0x4 5. "TXRRDY2,I2S Transmit Right 2 or TDM Channel [2x]+1 Ready Interrupt Disable" "0,1"
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bitfld.long 0x4 4. "TXLRDY2,I2S Transmit Left 2 or TDM Channel 2x ReadyInterrupt Disable" "0,1"
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newline
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bitfld.long 0x4 3. "TXRRDY1,I2S Transmit Right 1 or TDM Channel [2x]+1 Ready Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "TXLRDY1,I2S Transmit Left 1 or TDM Channel 2x ReadyInterrupt Disable" "0,1"
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newline
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bitfld.long 0x4 1. "TXRRDY0,I2S Transmit Right 0 or TDM Channel [2x]+1 Ready Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "TXLRDY0,I2S Transmit Left 0 or TDM Channel 2x ReadyInterrupt Disable" "0,1"
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rgroup.long 0x18++0x7
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line.long 0x0 "IMRA,Interrupt Mask Register A"
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bitfld.long 0x0 31. "RXROVF3,I2S Receive Right 3 or TDM Channel [2x]+1 Overrun Interrupt Mask" "0,1"
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bitfld.long 0x0 30. "RXLOVF3,I2S Receive Left 3 or TDM Channel 2x Overrun Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 29. "RXROVF2,I2S Receive Right 2 or TDM Channel [2x]+1 Overrun Interrupt Mask" "0,1"
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bitfld.long 0x0 28. "RXLOVF2,I2S Receive Left 2 or TDM Channel 2x Overrun Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 27. "RXROVF1,I2S Receive Right 1 or TDM Channel [2x]+1 Overrun Interrupt Mask" "0,1"
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bitfld.long 0x0 26. "RXLOVF1,I2S Receive Left 1 or TDM Channel 2x Overrun Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 25. "RXROVF0,I2S Receive Right 0 or TDM Channel [2x]+1 Overrun Interrupt Mask" "0,1"
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bitfld.long 0x0 24. "RXLOVF0,I2S Receive Left 0 or TDM Channel 2x Overrun Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 23. "RXRRDY3,I2S Receive Right 3 or TDM Channel [2x]+1 Ready Interrupt Mask" "0,1"
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bitfld.long 0x0 22. "RXLRDY3,I2S Receive Left 3 or TDM Channel 2x Ready Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 21. "RXRRDY2,I2S Receive Right 2 or TDM Channel [2x]+1 Ready Interrupt Mask" "0,1"
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bitfld.long 0x0 20. "RXLRDY2,I2S Receive Left 2 or TDM Channel 2x Ready Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 19. "RXRRDY1,I2S Receive Right 1 or TDM Channel [2x]+1 Ready Interrupt Mask" "0,1"
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bitfld.long 0x0 18. "RXLRDY1,I2S Receive Left 1 or TDM Channel 2x Ready Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 17. "RXRRDY0,I2S Receive Right 0 or TDM Channel [2x]+1 Ready Interrupt Mask" "0,1"
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bitfld.long 0x0 16. "RXLRDY0,I2S Receive Left 0 or TDM Channel 2x Ready Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 15. "TXRUNF3,I2S Transmit Right 3 or TDM Channel [2x]+1 Underrun Interrupt Mask" "0,1"
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bitfld.long 0x0 14. "TXLUNF3,I2S Transmit Left 3 or TDM Channel 2x Underrun Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 13. "TXRUNF2,I2S Transmit Right 2 or TDM Channel [2x]+1 Underrun Interrupt Mask" "0,1"
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bitfld.long 0x0 12. "TXLUNF2,I2S Transmit Left 2 or TDM Channel 2x Underrun Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 11. "TXRUNF1,I2S Transmit Right 1 or TDM Channel [2x]+1 Underrun Interrupt Mask" "0,1"
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bitfld.long 0x0 10. "TXLUNF1,I2S Transmit Left 1 or TDM Channel 2x Underrun Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 9. "TXRUNF0,I2S Transmit Right 0 or TDM Channel [2x]+1 Underrun Interrupt Mask" "0,1"
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bitfld.long 0x0 8. "TXLUNF0,I2S Transmit Left 0 or TDM Channel 2x Underrun Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 7. "TXRRDY3,I2S Transmit Right 3 or TDM Channel [2x]+1 Ready Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "TXLRDY3,I2S Transmit Left 3 or TDM Channel 2x ReadyInterrupt Mask" "0,1"
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newline
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bitfld.long 0x0 5. "TXRRDY2,I2S Transmit Right 2 or TDM Channel [2x]+1 Ready Interrupt Mask" "0,1"
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bitfld.long 0x0 4. "TXLRDY2,I2S Transmit Left 2 or TDM Channel 2x ReadyInterrupt Mask" "0,1"
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newline
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bitfld.long 0x0 3. "TXRRDY1,I2S Transmit Right 1 or TDM Channel [2x]+1 Ready Interrupt Mask" "0,1"
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bitfld.long 0x0 2. "TXLRDY1,I2S Transmit Left 1 or TDM Channel 2x ReadyInterrupt Mask" "0,1"
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newline
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bitfld.long 0x0 1. "TXRRDY0,I2S Transmit Right 0 or TDM Channel [2x]+1 Ready Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "TXLRDY0,I2S Transmit Left 0 or TDM Channel 2x ReadyInterrupt Mask" "0,1"
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line.long 0x4 "ISRA,Interrupt Status Register A"
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bitfld.long 0x4 31. "RXROVF3,I2S Receive Right 3 or TDM Channel [2x]+1 Overrun Flag (Cleared on read)" "0: Cleared when I2SMCC_ISRA is read.,1: Set when an overrun error occurs in either.."
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bitfld.long 0x4 30. "RXLOVF3,I2S Receive Left 3 or TDM Channel 2x Overrun Flag (Cleared on read)" "0: Cleared when I2SMCC_ISRA is read.,1: Set when an overrun error occurs in either.."
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newline
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bitfld.long 0x4 29. "RXROVF2,I2S Receive Right 2 or TDM Channel [2x]+1 Overrun Flag (Cleared on read)" "0: Cleared when I2SMCC_ISRA is read.,1: Set when an overrun error occurs in either.."
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bitfld.long 0x4 28. "RXLOVF2,I2S Receive Left 2 or TDM Channel 2x Overrun Flag (Cleared on read)" "0: Cleared when I2SMCC_ISRA is read.,1: Set when an overrun error occurs in either.."
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newline
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bitfld.long 0x4 27. "RXROVF1,I2S Receive Right 1 or TDM Channel [2x]+1 Overrun Flag (Cleared on read)" "0: Cleared when I2SMCC_ISRA is read.,1: Set when an overrun error occurs in either.."
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bitfld.long 0x4 26. "RXLOVF1,I2S Receive Left 1 or TDM Channel 2x Overrun Flag (Cleared on read)" "0: Cleared when I2SMCC_ISRA is read.,1: Set when an overrun error occurs in either.."
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newline
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bitfld.long 0x4 25. "RXROVF0,I2S Receive Right 0 or TDM Channel [2x]+1 Overrun Flag (Cleared on read)" "0: Cleared when I2SMCC_ISRA is read.,1: Set when an overrun error occurs in either.."
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bitfld.long 0x4 24. "RXLOVF0,I2S Receive Left 0 or TDM Channel 2x Overrun Flag (Cleared on read)" "0: Cleared when I2SMCC_ISRA is read.,1: Set when an overrun error occurs in either.."
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newline
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bitfld.long 0x4 23. "RXRRDY3,I2S Receive Right 3 or TDM Channel [2x]+1 Ready Flag (Cleared by reading I2SMCC_RHR/RHLxR)" "0: Cleared when I2SMCC_RHRxR is read or when the..,1: Set when received data is available in either.."
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bitfld.long 0x4 22. "RXLRDY3,I2S Receive Left 3 or TDM Channel 2x Ready Flag (Cleared by reading I2SMCC_RHR/RHLxR)" "0: Cleared when either I2SMCC_RHLxR is read or when..,1: Set when received data is available in either.."
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newline
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bitfld.long 0x4 21. "RXRRDY2,I2S Receive Right 2 or TDM Channel [2x]+1 Ready Flag (Cleared by reading I2SMCC_RHR/RHLxR)" "0: Cleared when I2SMCC_RHRxR is read or when the..,1: Set when received data is available in either.."
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bitfld.long 0x4 20. "RXLRDY2,I2S Receive Left 2 or TDM Channel 2x Ready Flag (Cleared by reading I2SMCC_RHR/RHLxR)" "0: Cleared when either I2SMCC_RHLxR is read or when..,1: Set when received data is available in either.."
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newline
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bitfld.long 0x4 19. "RXRRDY1,I2S Receive Right 1 or TDM Channel [2x]+1 Ready Flag (Cleared by reading I2SMCC_RHR/RHLxR)" "0: Cleared when I2SMCC_RHRxR is read or when the..,1: Set when received data is available in either.."
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bitfld.long 0x4 18. "RXLRDY1,I2S Receive Left 1 or TDM Channel 2x Ready Flag (Cleared by reading I2SMCC_RHR/RHLxR)" "0: Cleared when either I2SMCC_RHLxR is read or when..,1: Set when received data is available in either.."
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newline
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bitfld.long 0x4 17. "RXRRDY0,I2S Receive Right 0 or TDM Channel [2x]+1 Ready Flag (Cleared by reading I2SMCC_RHR/RHLxR)" "0: Cleared when I2SMCC_RHRxR is read or when the..,1: Set when received data is available in either.."
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bitfld.long 0x4 16. "RXLRDY0,I2S Receive Left 0 or TDM Channel 2x Ready Flag (Cleared by reading I2SMCC_RHR/RHLxR)" "0: Cleared when either I2SMCC_RHLxR is read or when..,1: Set when received data is available in either.."
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newline
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bitfld.long 0x4 15. "TXRUNF3,I2S Transmit Right 3 or TDM Channel [2x]+1 Underrun Flag (Cleared on read)" "0: Cleared when the I2SMCC_ISRA is read.,1: Set when an underrun error occurs in either.."
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bitfld.long 0x4 14. "TXLUNF3,I2S Transmit Left 3 or TDM Channel 2x Underrun (Cleared on read)" "0: Cleared when I2SMCC_ISRA is read.,1: Set when an underrun error occurs in either.."
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newline
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bitfld.long 0x4 13. "TXRUNF2,I2S Transmit Right 2 or TDM Channel [2x]+1 Underrun Flag (Cleared on read)" "0: Cleared when the I2SMCC_ISRA is read.,1: Set when an underrun error occurs in either.."
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bitfld.long 0x4 12. "TXLUNF2,I2S Transmit Left 2 or TDM Channel 2x Underrun (Cleared on read)" "0: Cleared when I2SMCC_ISRA is read.,1: Set when an underrun error occurs in either.."
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newline
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bitfld.long 0x4 11. "TXRUNF1,I2S Transmit Right 1 or TDM Channel [2x]+1 Underrun Flag (Cleared on read)" "0: Cleared when the I2SMCC_ISRA is read.,1: Set when an underrun error occurs in either.."
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bitfld.long 0x4 10. "TXLUNF1,I2S Transmit Left 1 or TDM Channel 2x Underrun (Cleared on read)" "0: Cleared when I2SMCC_ISRA is read.,1: Set when an underrun error occurs in either.."
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newline
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bitfld.long 0x4 9. "TXRUNF0,I2S Transmit Right 0 or TDM Channel [2x]+1 Underrun Flag (Cleared on read)" "0: Cleared when the I2SMCC_ISRA is read.,1: Set when an underrun error occurs in either.."
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bitfld.long 0x4 8. "TXLUNF0,I2S Transmit Left 0 or TDM Channel 2x Underrun (Cleared on read)" "0: Cleared when I2SMCC_ISRA is read.,1: Set when an underrun error occurs in either.."
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newline
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bitfld.long 0x4 7. "TXRRDY3,I2S Transmit Right 3 or TDM Channel [2x]+1 Ready Flag (Cleared by writing I2SMCC_THR/THRxR)" "0: Cleared when either I2SMCC_THRxR is written or..,1: Set when I2SMCC_THR or I2SMCC_THLxR is empty."
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bitfld.long 0x4 6. "TXLRDY3,I2S Transmit Left 3 or TDM Channel 2x Ready Flag (Cleared by writing I2SMCC_THR/THLxR)" "0: Cleared when either I2SMCC_THLxR is written or..,1: Set when I2SMCC_THR or I2SMCC_THLxR is empty."
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newline
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bitfld.long 0x4 5. "TXRRDY2,I2S Transmit Right 2 or TDM Channel [2x]+1 Ready Flag (Cleared by writing I2SMCC_THR/THRxR)" "0: Cleared when either I2SMCC_THRxR is written or..,1: Set when I2SMCC_THR or I2SMCC_THLxR is empty."
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bitfld.long 0x4 4. "TXLRDY2,I2S Transmit Left 2 or TDM Channel 2x Ready Flag (Cleared by writing I2SMCC_THR/THLxR)" "0: Cleared when either I2SMCC_THLxR is written or..,1: Set when I2SMCC_THR or I2SMCC_THLxR is empty."
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newline
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bitfld.long 0x4 3. "TXRRDY1,I2S Transmit Right 1 or TDM Channel [2x]+1 Ready Flag (Cleared by writing I2SMCC_THR/THRxR)" "0: Cleared when either I2SMCC_THRxR is written or..,1: Set when I2SMCC_THR or I2SMCC_THLxR is empty."
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bitfld.long 0x4 2. "TXLRDY1,I2S Transmit Left 1 or TDM Channel 2x Ready Flag (Cleared by writing I2SMCC_THR/THLxR)" "0: Cleared when either I2SMCC_THLxR is written or..,1: Set when I2SMCC_THR or I2SMCC_THLxR is empty."
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newline
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bitfld.long 0x4 1. "TXRRDY0,I2S Transmit Right 0 or TDM Channel [2x]+1 Ready Flag (Cleared by writing I2SMCC_THR/THRxR)" "0: Cleared when either I2SMCC_THRxR is written or..,1: Set when I2SMCC_THR or I2SMCC_THLxR is empty."
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bitfld.long 0x4 0. "TXLRDY0,I2S Transmit Left 0 or TDM Channel 2x Ready Flag (Cleared by writing I2SMCC_THR/THLxR)" "0: Cleared when either I2SMCC_THLxR is written or..,1: Set when I2SMCC_THR or I2SMCC_THLxR is empty."
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wgroup.long 0x20++0x7
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line.long 0x0 "IERB,Interrupt Enable Register B"
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bitfld.long 0x0 13. "RXFFFUL,RX FIFO Full Interrupt Enable" "0,1"
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bitfld.long 0x0 12. "RXFFRDY,RX FIFO Ready Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 9. "TXFFEMP,TX FIFO Empty Interrupt Enable" "0,1"
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bitfld.long 0x0 8. "TXFFRDY,TX FIFO Ready Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 0. "WERR,Write Error Interrupt Enable" "0,1"
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line.long 0x4 "IDRB,Interrupt Disable Register B"
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bitfld.long 0x4 13. "RXFFFUL,RTX FIFO Full Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 12. "RXFFRDY,RX FIFO Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXFFEMP,TX FIFO Empty Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 8. "TXFFRDY,TX FIFO Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "WERR,Write Error Interrupt Disable" "0,1"
|
|
rgroup.long 0x28++0xB
|
|
line.long 0x0 "IMRB,Interrupt Mask Register B"
|
|
bitfld.long 0x0 13. "RXFFFUL,RX FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 12. "RXFFRDY,RX FIFO Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXFFEMP,TX FIFO Empty Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 8. "TXFFRDY,TX FIFO Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WERR,Write Error Interrupt Enable" "0,1"
|
|
line.long 0x4 "ISRB,Interrupt Status Register B"
|
|
bitfld.long 0x4 13. "RXFFFUL,RX FIFO Full Flag (Cleared on read)" "0: Cleared when I2SMCC_ISRB is read.,1: Set when RX FIFO is full. This status bit is not.."
|
|
bitfld.long 0x4 12. "RXFFRDY,RX FIFO Ready Flag (Cleared on read)" "0: Cleared when I2SMCC_ISRB is read.,1: Set when RX FIFO is ready to be read. This.."
|
|
newline
|
|
bitfld.long 0x4 9. "TXFFEMP,TX FIFO Empty Flag (Cleared on read)" "0: Cleared when I2SMCC_ISRB is read.,1: Set when TX FIFO is empty. This status bit is.."
|
|
bitfld.long 0x4 8. "TXFFRDY,TX FIFO Ready Flag (Cleared on read)" "0: Cleared when I2SMCC_ISRB is read.,1: Set when TX FIFO is ready to be written. This.."
|
|
newline
|
|
bitfld.long 0x4 0. "WERR,Write Error Flag (cleared on read)" "0: Cleared when I2SMCC_ISRB is read.,1: Set when a write occurs in a protected register."
|
|
line.long 0x8 "RHR,Receiver Holding Register"
|
|
hexmask.long 0x8 0.--31. 1. "RHR,Receiver Holding Register"
|
|
wgroup.long 0x34++0x3
|
|
line.long 0x0 "THR,Transmitter Holding Register"
|
|
hexmask.long 0x0 0.--31. 1. "THR,Transmitter Holding Register"
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0xE161C040 ad:0xE161C048 ad:0xE161C050 ad:0xE161C058)
|
|
tree "I2SMCC_RH[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "RHLxR,Receiver Holding Left x Register"
|
|
hexmask.long 0x0 0.--31. 1. "RHL,Receiver Holding Left"
|
|
line.long 0x4 "RHRxR,Receiver Holding Right x Register"
|
|
hexmask.long 0x4 0.--31. 1. "RHR,Receiver Holding Right"
|
|
tree.end
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0xE161C060 ad:0xE161C068 ad:0xE161C070 ad:0xE161C078)
|
|
tree "I2SMCC_TH[$1]"
|
|
base $2
|
|
wgroup.long ($2)++0x7
|
|
line.long 0x0 "THLxR,Transmitter Holding Left x Register"
|
|
hexmask.long 0x0 0.--31. 1. "THL,Transmitter Holding Left"
|
|
line.long 0x4 "THRxR,Transmitter Holding Right x Register"
|
|
hexmask.long 0x4 0.--31. 1. "THR,Transmitter Holding Right"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0xE161C000
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 2. "WPCTEN,Write Protection Control Enable" "0: Disables the write protection of the control if..,1: Enables the write protection of the control if.."
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection of the..,1: Enables the write protection of the interruption.."
|
|
bitfld.long 0x0 0. "WPCFEN,Write Protection Configuration Enable" "0: Disables the write protection of the..,1: Enables the write protection of the.."
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
|
|
tree.end
|
|
tree "I2SMCC1"
|
|
base ad:0xE1620000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0: No effect.,1: Resets all the registers in the I2SMCC. The.."
|
|
bitfld.long 0x0 5. "TXDIS,Transmitter Disable" "0: No effect.,1: Disables the I2SMCC transmitter. Bit.."
|
|
newline
|
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bitfld.long 0x0 4. "TXEN,Transmitter Enable" "0: No effect.,1: Enables the I2SMCC transmitter if TXDIS is not.."
|
|
bitfld.long 0x0 3. "CKDIS,Clocks Disable" "0: No effect.,1: Disables the I2SMCC clock generation."
|
|
newline
|
|
bitfld.long 0x0 2. "CKEN,Clocks Enable" "0: No effect.,1: Enables the I2SMCC clock generation if CKDIS is.."
|
|
bitfld.long 0x0 1. "RXDIS,Receiver Disable" "0: No effect.,1: Disables the I2SMCC receiver. Bit I2SMCC_SR.RXEN.."
|
|
newline
|
|
bitfld.long 0x0 0. "RXEN,Receiver Enable" "0: No effect.,1: Enables the I2SMCC receiver if RXDIS is not '1'."
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "MRA,Mode Register A"
|
|
bitfld.long 0x0 31. "IWS,I2SMCC_WS Slot Length" "0: I2SMCC_WS slot is 32 bits long for DATALENGTH =..,1: I2SMCC_WS slot is 24 bits long for DATALENGTH =.."
|
|
bitfld.long 0x0 30. "IMCKMODE,Master Clock Mode" "0: No master clock generated.,1: Master clock generated."
|
|
newline
|
|
hexmask.long.byte 0x0 24.--29. 1. "ISCKDIV,Selected Clock to I2SMCC Serial Clock Ratio"
|
|
bitfld.long 0x0 22.--23. "TDMFS,TDM Frame Synchronization" "0: I2SMCC_WS pulse is high for one time slot at..,1: I2SMCC_WS pulse is high for half the time slots..,2: I2SMCC_WS pulse is high for one bit period at..,?"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "IMCKDIV,Selected Clock to I2SMCC Master Clock Ratio"
|
|
bitfld.long 0x0 13.--15. "NBCHAN,Number of TDM Channels-1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 12. "SRCCLK,Source Clock Selection" "0: The Peripheral clock is selected as source clock.,1: The PMC.GCLKx clock is selected as source clock."
|
|
bitfld.long 0x0 11. "TXSAME,Transmit Data when Underrun" "0: '0' is transmitted when underrun.,1: Previous sample transmitted when underrun."
|
|
newline
|
|
bitfld.long 0x0 10. "TXMONO,Transmit Mono" "0: Stereo.,1: Mono with left audio samples duplicated to right.."
|
|
bitfld.long 0x0 9. "RXLOOP,Loop-back Test Mode" "0: Normal mode.,1: I2SMCC_DOUT outputs of I2SMCC are internally.."
|
|
newline
|
|
bitfld.long 0x0 8. "RXMONO,Receive Mono" "0: Stereo.,1: Mono with left audio samples duplicated to right.."
|
|
bitfld.long 0x0 6.--7. "FORMAT,Data Format" "0: I2S format stereo with I2SMCC_WS low for left..,1: Left-justified format stereo with I2SMCC_WS high..,2: TDM format with (NBCHAN + 1) channels I2SMCC_WS..,3: TDM format left-justified with (NBCHAN + 1).."
|
|
newline
|
|
bitfld.long 0x0 4.--5. "WIRECFG,Wire Configuration" "0: In I2S and LJ formats I2SMCC_DIN0 and..,1: In I2S and LJ formats I2SMCC_DIN1..0 and..,2: In I2S and LJ formats I2SMCC_DIN3..0 and..,3: In I2S and LJ formats reserved for future use do.."
|
|
bitfld.long 0x0 1.--3. "DATALENGTH,Data Word Length" "0: Data length is set to 32 bits.,1: Data length is set to 24 bits.,2: Data length is set to 20 bits.,3: Data length is set to 18 bits.,4: Data length is set to 16 bits.,5: Data length is set to 16-bit compact stereo.,6: Data length is set to 8 bits.,7: Data length is set to 8-bit compact stereo. Left.."
|
|
newline
|
|
bitfld.long 0x0 0. "MODE,Inter-IC Sound Multi Channel Controller Mode" "0: I2SMCC_CK and I2SMCC_WS pin inputs used as bit..,1: Bit clock and word select/frame synchronization.."
|
|
line.long 0x4 "MRB,Mode Register B"
|
|
bitfld.long 0x4 16. "CLKSEL,Serial Clock Selection" "0: The I2SMCC_CK clock (provided by the external..,1: The internal clock (generated from source clock).."
|
|
bitfld.long 0x4 8.--9. "DMACHUNK,DMA Chunk Size" "0: Each DMA transfer contains 1 word.,1: Each DMA transfer contains 2 words.,2: Each DMA transfer contains 4 words.,3: Each DMA transfer contains 8 words."
|
|
newline
|
|
bitfld.long 0x4 4. "FIFOEN,FIFO Enable" "0: The Receive and Transmit FIFOs are disabled.,1: The Receive and Transmit FIFOs are enabled."
|
|
bitfld.long 0x4 0. "CRAMODE,Common Register Access Mode" "0: All enabled I2S left channels are filled first..,1: An enabled I2S left channel is filled then the.."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 4. "TXEN,Transmitter Enabled" "0: Cleared when the transmitter is disabled..,1: Set when the transmitter is enabled following a.."
|
|
bitfld.long 0x0 0. "RXEN,Receiver Enabled" "0: Cleared when the receiver is disabled following..,1: Set when the receiver is enabled following a.."
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IERA,Interrupt Enable Register A"
|
|
bitfld.long 0x0 31. "RXROVF3,I2S Receive Right 3 or TDM Channel [2x]+1 Overrun Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 30. "RXLOVF3,I2S Receive Left 3 or TDM Channel 2x Overrun Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXROVF2,I2S Receive Right 2 or TDM Channel [2x]+1 Overrun Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 28. "RXLOVF2,I2S Receive Left 2 or TDM Channel 2x Overrun Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXROVF1,I2S Receive Right 1 or TDM Channel [2x]+1 Overrun Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 26. "RXLOVF1,I2S Receive Left 1 or TDM Channel 2x Overrun Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXROVF0,I2S Receive Right 0 or TDM Channel [2x]+1 Overrun Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 24. "RXLOVF0,I2S Receive Left 0 or TDM Channel 2x Overrun Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "RXRRDY3,I2S Receive Right 3 or TDM Channel [2x]+1 Ready Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 22. "RXLRDY3,I2S Receive Left 3 or TDM Channel 2x Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "RXRRDY2,I2S Receive Right 2 or TDM Channel [2x]+1 Ready Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 20. "RXLRDY2,I2S Receive Left 2 or TDM Channel 2x Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RXRRDY1,I2S Receive Right 1 or TDM Channel [2x]+1 Ready Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 18. "RXLRDY1,I2S Receive Left 1 or TDM Channel 2x Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RXRRDY0,I2S Receive Right 0 or TDM Channel [2x]+1 Ready Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 16. "RXLRDY0,I2S Receive Left 0 or TDM Channel 2x Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXRUNF3,I2S Transmit Right 3 or TDM Channel [2x]+1 Underrun Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 14. "TXLUNF3,I2S Transmit Left 3 or TDM Channel 2x Underrun Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TXRUNF2,I2S Transmit Right 2 or TDM Channel [2x]+1 Underrun Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 12. "TXLUNF2,I2S Transmit Left 2 or TDM Channel 2x Underrun Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TXRUNF1,I2S Transmit Right 1 or TDM Channel [2x]+1 Underrun Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 10. "TXLUNF1,I2S Transmit Left 1 or TDM Channel 2x Underrun Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXRUNF0,I2S Transmit Right 0 or TDM Channel [2x]+1 Underrun Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 8. "TXLUNF0,I2S Transmit Left 0 or TDM Channel 2x Underrun Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXRRDY3,I2S Transmit Right 3 or TDM Channel [2x]+1 Ready Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 6. "TXLRDY3,I2S Transmit Left 3 or TDM Channel 2x ReadyInterrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TXRRDY2,I2S Transmit Right 2 or TDM Channel [2x]+1 Ready Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "TXLRDY2,I2S Transmit Left 2 or TDM Channel 2x ReadyInterrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TXRRDY1,I2S Transmit Right 1 or TDM Channel [2x]+1 Ready Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "TXLRDY1,I2S Transmit Left 1 or TDM Channel 2x ReadyInterrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRRDY0,I2S Transmit Right 0 or TDM Channel [2x]+1 Ready Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "TXLRDY0,I2S Transmit Left 0 or TDM Channel 2x ReadyInterrupt Enable" "0,1"
|
|
line.long 0x4 "IDRA,Interrupt Disable Register A"
|
|
bitfld.long 0x4 31. "RXROVF3,I2S Receive Right 3 or TDM Channel [2x]+1 Overrun Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 30. "RXLOVF3,I2S Receive Left 3 or TDM Channel 2x Overrun Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RXROVF2,I2S Receive Right 2 or TDM Channel [2x]+1 Overrun Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 28. "RXLOVF2,I2S Receive Left 2 or TDM Channel 2x Overrun Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "RXROVF1,I2S Receive Right 1 or TDM Channel [2x]+1 Overrun Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 26. "RXLOVF1,I2S Receive Left 1 or TDM Channel 2x Overrun Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "RXROVF0,I2S Receive Right 0 or TDM Channel [2x]+1 Overrun Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 24. "RXLOVF0,I2S Receive Left 0 or TDM Channel 2x Overrun Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "RXRRDY3,I2S Receive Right 3 or TDM Channel [2x]+1 Ready Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 22. "RXLRDY3,I2S Receive Left 3 or TDM Channel 2x Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "RXRRDY2,I2S Receive Right 2 or TDM Channel [2x]+1 Ready Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 20. "RXLRDY2,I2S Receive Left 2 or TDM Channel 2x Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "RXRRDY1,I2S Receive Right 1 or TDM Channel [2x]+1 Ready Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 18. "RXLRDY1,I2S Receive Left 1 or TDM Channel 2x Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "RXRRDY0,I2S Receive Right 0 or TDM Channel [2x]+1 Ready Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 16. "RXLRDY0,I2S Receive Left 0 or TDM Channel 2x Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TXRUNF3,I2S Transmit Right 3 or TDM Channel [2x]+1 Underrun Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 14. "TXLUNF3,I2S Transmit Left 3 or TDM Channel 2x Underrun Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "TXRUNF2,I2S Transmit Right 2 or TDM Channel [2x]+1 Underrun Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 12. "TXLUNF2,I2S Transmit Left 2 or TDM Channel 2x Underrun Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "TXRUNF1,I2S Transmit Right 1 or TDM Channel [2x]+1 Underrun Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 10. "TXLUNF1,I2S Transmit Left 1 or TDM Channel 2x Underrun Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXRUNF0,I2S Transmit Right 0 or TDM Channel [2x]+1 Underrun Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 8. "TXLUNF0,I2S Transmit Left 0 or TDM Channel 2x Underrun Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "TXRRDY3,I2S Transmit Right 3 or TDM Channel [2x]+1 Ready Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 6. "TXLRDY3,I2S Transmit Left 3 or TDM Channel 2x ReadyInterrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "TXRRDY2,I2S Transmit Right 2 or TDM Channel [2x]+1 Ready Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 4. "TXLRDY2,I2S Transmit Left 2 or TDM Channel 2x ReadyInterrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "TXRRDY1,I2S Transmit Right 1 or TDM Channel [2x]+1 Ready Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 2. "TXLRDY1,I2S Transmit Left 1 or TDM Channel 2x ReadyInterrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRRDY0,I2S Transmit Right 0 or TDM Channel [2x]+1 Ready Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "TXLRDY0,I2S Transmit Left 0 or TDM Channel 2x ReadyInterrupt Disable" "0,1"
|
|
rgroup.long 0x18++0x7
|
|
line.long 0x0 "IMRA,Interrupt Mask Register A"
|
|
bitfld.long 0x0 31. "RXROVF3,I2S Receive Right 3 or TDM Channel [2x]+1 Overrun Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 30. "RXLOVF3,I2S Receive Left 3 or TDM Channel 2x Overrun Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXROVF2,I2S Receive Right 2 or TDM Channel [2x]+1 Overrun Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 28. "RXLOVF2,I2S Receive Left 2 or TDM Channel 2x Overrun Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXROVF1,I2S Receive Right 1 or TDM Channel [2x]+1 Overrun Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 26. "RXLOVF1,I2S Receive Left 1 or TDM Channel 2x Overrun Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXROVF0,I2S Receive Right 0 or TDM Channel [2x]+1 Overrun Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 24. "RXLOVF0,I2S Receive Left 0 or TDM Channel 2x Overrun Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "RXRRDY3,I2S Receive Right 3 or TDM Channel [2x]+1 Ready Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 22. "RXLRDY3,I2S Receive Left 3 or TDM Channel 2x Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "RXRRDY2,I2S Receive Right 2 or TDM Channel [2x]+1 Ready Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 20. "RXLRDY2,I2S Receive Left 2 or TDM Channel 2x Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RXRRDY1,I2S Receive Right 1 or TDM Channel [2x]+1 Ready Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 18. "RXLRDY1,I2S Receive Left 1 or TDM Channel 2x Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RXRRDY0,I2S Receive Right 0 or TDM Channel [2x]+1 Ready Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 16. "RXLRDY0,I2S Receive Left 0 or TDM Channel 2x Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXRUNF3,I2S Transmit Right 3 or TDM Channel [2x]+1 Underrun Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 14. "TXLUNF3,I2S Transmit Left 3 or TDM Channel 2x Underrun Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TXRUNF2,I2S Transmit Right 2 or TDM Channel [2x]+1 Underrun Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 12. "TXLUNF2,I2S Transmit Left 2 or TDM Channel 2x Underrun Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TXRUNF1,I2S Transmit Right 1 or TDM Channel [2x]+1 Underrun Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 10. "TXLUNF1,I2S Transmit Left 1 or TDM Channel 2x Underrun Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXRUNF0,I2S Transmit Right 0 or TDM Channel [2x]+1 Underrun Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 8. "TXLUNF0,I2S Transmit Left 0 or TDM Channel 2x Underrun Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXRRDY3,I2S Transmit Right 3 or TDM Channel [2x]+1 Ready Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 6. "TXLRDY3,I2S Transmit Left 3 or TDM Channel 2x ReadyInterrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TXRRDY2,I2S Transmit Right 2 or TDM Channel [2x]+1 Ready Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 4. "TXLRDY2,I2S Transmit Left 2 or TDM Channel 2x ReadyInterrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TXRRDY1,I2S Transmit Right 1 or TDM Channel [2x]+1 Ready Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "TXLRDY1,I2S Transmit Left 1 or TDM Channel 2x ReadyInterrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRRDY0,I2S Transmit Right 0 or TDM Channel [2x]+1 Ready Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "TXLRDY0,I2S Transmit Left 0 or TDM Channel 2x ReadyInterrupt Mask" "0,1"
|
|
line.long 0x4 "ISRA,Interrupt Status Register A"
|
|
bitfld.long 0x4 31. "RXROVF3,I2S Receive Right 3 or TDM Channel [2x]+1 Overrun Flag (Cleared on read)" "0: Cleared when I2SMCC_ISRA is read.,1: Set when an overrun error occurs in either.."
|
|
bitfld.long 0x4 30. "RXLOVF3,I2S Receive Left 3 or TDM Channel 2x Overrun Flag (Cleared on read)" "0: Cleared when I2SMCC_ISRA is read.,1: Set when an overrun error occurs in either.."
|
|
newline
|
|
bitfld.long 0x4 29. "RXROVF2,I2S Receive Right 2 or TDM Channel [2x]+1 Overrun Flag (Cleared on read)" "0: Cleared when I2SMCC_ISRA is read.,1: Set when an overrun error occurs in either.."
|
|
bitfld.long 0x4 28. "RXLOVF2,I2S Receive Left 2 or TDM Channel 2x Overrun Flag (Cleared on read)" "0: Cleared when I2SMCC_ISRA is read.,1: Set when an overrun error occurs in either.."
|
|
newline
|
|
bitfld.long 0x4 27. "RXROVF1,I2S Receive Right 1 or TDM Channel [2x]+1 Overrun Flag (Cleared on read)" "0: Cleared when I2SMCC_ISRA is read.,1: Set when an overrun error occurs in either.."
|
|
bitfld.long 0x4 26. "RXLOVF1,I2S Receive Left 1 or TDM Channel 2x Overrun Flag (Cleared on read)" "0: Cleared when I2SMCC_ISRA is read.,1: Set when an overrun error occurs in either.."
|
|
newline
|
|
bitfld.long 0x4 25. "RXROVF0,I2S Receive Right 0 or TDM Channel [2x]+1 Overrun Flag (Cleared on read)" "0: Cleared when I2SMCC_ISRA is read.,1: Set when an overrun error occurs in either.."
|
|
bitfld.long 0x4 24. "RXLOVF0,I2S Receive Left 0 or TDM Channel 2x Overrun Flag (Cleared on read)" "0: Cleared when I2SMCC_ISRA is read.,1: Set when an overrun error occurs in either.."
|
|
newline
|
|
bitfld.long 0x4 23. "RXRRDY3,I2S Receive Right 3 or TDM Channel [2x]+1 Ready Flag (Cleared by reading I2SMCC_RHR/RHLxR)" "0: Cleared when I2SMCC_RHRxR is read or when the..,1: Set when received data is available in either.."
|
|
bitfld.long 0x4 22. "RXLRDY3,I2S Receive Left 3 or TDM Channel 2x Ready Flag (Cleared by reading I2SMCC_RHR/RHLxR)" "0: Cleared when either I2SMCC_RHLxR is read or when..,1: Set when received data is available in either.."
|
|
newline
|
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bitfld.long 0x4 21. "RXRRDY2,I2S Receive Right 2 or TDM Channel [2x]+1 Ready Flag (Cleared by reading I2SMCC_RHR/RHLxR)" "0: Cleared when I2SMCC_RHRxR is read or when the..,1: Set when received data is available in either.."
|
|
bitfld.long 0x4 20. "RXLRDY2,I2S Receive Left 2 or TDM Channel 2x Ready Flag (Cleared by reading I2SMCC_RHR/RHLxR)" "0: Cleared when either I2SMCC_RHLxR is read or when..,1: Set when received data is available in either.."
|
|
newline
|
|
bitfld.long 0x4 19. "RXRRDY1,I2S Receive Right 1 or TDM Channel [2x]+1 Ready Flag (Cleared by reading I2SMCC_RHR/RHLxR)" "0: Cleared when I2SMCC_RHRxR is read or when the..,1: Set when received data is available in either.."
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|
bitfld.long 0x4 18. "RXLRDY1,I2S Receive Left 1 or TDM Channel 2x Ready Flag (Cleared by reading I2SMCC_RHR/RHLxR)" "0: Cleared when either I2SMCC_RHLxR is read or when..,1: Set when received data is available in either.."
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|
newline
|
|
bitfld.long 0x4 17. "RXRRDY0,I2S Receive Right 0 or TDM Channel [2x]+1 Ready Flag (Cleared by reading I2SMCC_RHR/RHLxR)" "0: Cleared when I2SMCC_RHRxR is read or when the..,1: Set when received data is available in either.."
|
|
bitfld.long 0x4 16. "RXLRDY0,I2S Receive Left 0 or TDM Channel 2x Ready Flag (Cleared by reading I2SMCC_RHR/RHLxR)" "0: Cleared when either I2SMCC_RHLxR is read or when..,1: Set when received data is available in either.."
|
|
newline
|
|
bitfld.long 0x4 15. "TXRUNF3,I2S Transmit Right 3 or TDM Channel [2x]+1 Underrun Flag (Cleared on read)" "0: Cleared when the I2SMCC_ISRA is read.,1: Set when an underrun error occurs in either.."
|
|
bitfld.long 0x4 14. "TXLUNF3,I2S Transmit Left 3 or TDM Channel 2x Underrun (Cleared on read)" "0: Cleared when I2SMCC_ISRA is read.,1: Set when an underrun error occurs in either.."
|
|
newline
|
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bitfld.long 0x4 13. "TXRUNF2,I2S Transmit Right 2 or TDM Channel [2x]+1 Underrun Flag (Cleared on read)" "0: Cleared when the I2SMCC_ISRA is read.,1: Set when an underrun error occurs in either.."
|
|
bitfld.long 0x4 12. "TXLUNF2,I2S Transmit Left 2 or TDM Channel 2x Underrun (Cleared on read)" "0: Cleared when I2SMCC_ISRA is read.,1: Set when an underrun error occurs in either.."
|
|
newline
|
|
bitfld.long 0x4 11. "TXRUNF1,I2S Transmit Right 1 or TDM Channel [2x]+1 Underrun Flag (Cleared on read)" "0: Cleared when the I2SMCC_ISRA is read.,1: Set when an underrun error occurs in either.."
|
|
bitfld.long 0x4 10. "TXLUNF1,I2S Transmit Left 1 or TDM Channel 2x Underrun (Cleared on read)" "0: Cleared when I2SMCC_ISRA is read.,1: Set when an underrun error occurs in either.."
|
|
newline
|
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bitfld.long 0x4 9. "TXRUNF0,I2S Transmit Right 0 or TDM Channel [2x]+1 Underrun Flag (Cleared on read)" "0: Cleared when the I2SMCC_ISRA is read.,1: Set when an underrun error occurs in either.."
|
|
bitfld.long 0x4 8. "TXLUNF0,I2S Transmit Left 0 or TDM Channel 2x Underrun (Cleared on read)" "0: Cleared when I2SMCC_ISRA is read.,1: Set when an underrun error occurs in either.."
|
|
newline
|
|
bitfld.long 0x4 7. "TXRRDY3,I2S Transmit Right 3 or TDM Channel [2x]+1 Ready Flag (Cleared by writing I2SMCC_THR/THRxR)" "0: Cleared when either I2SMCC_THRxR is written or..,1: Set when I2SMCC_THR or I2SMCC_THLxR is empty."
|
|
bitfld.long 0x4 6. "TXLRDY3,I2S Transmit Left 3 or TDM Channel 2x Ready Flag (Cleared by writing I2SMCC_THR/THLxR)" "0: Cleared when either I2SMCC_THLxR is written or..,1: Set when I2SMCC_THR or I2SMCC_THLxR is empty."
|
|
newline
|
|
bitfld.long 0x4 5. "TXRRDY2,I2S Transmit Right 2 or TDM Channel [2x]+1 Ready Flag (Cleared by writing I2SMCC_THR/THRxR)" "0: Cleared when either I2SMCC_THRxR is written or..,1: Set when I2SMCC_THR or I2SMCC_THLxR is empty."
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|
bitfld.long 0x4 4. "TXLRDY2,I2S Transmit Left 2 or TDM Channel 2x Ready Flag (Cleared by writing I2SMCC_THR/THLxR)" "0: Cleared when either I2SMCC_THLxR is written or..,1: Set when I2SMCC_THR or I2SMCC_THLxR is empty."
|
|
newline
|
|
bitfld.long 0x4 3. "TXRRDY1,I2S Transmit Right 1 or TDM Channel [2x]+1 Ready Flag (Cleared by writing I2SMCC_THR/THRxR)" "0: Cleared when either I2SMCC_THRxR is written or..,1: Set when I2SMCC_THR or I2SMCC_THLxR is empty."
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|
bitfld.long 0x4 2. "TXLRDY1,I2S Transmit Left 1 or TDM Channel 2x Ready Flag (Cleared by writing I2SMCC_THR/THLxR)" "0: Cleared when either I2SMCC_THLxR is written or..,1: Set when I2SMCC_THR or I2SMCC_THLxR is empty."
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|
newline
|
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bitfld.long 0x4 1. "TXRRDY0,I2S Transmit Right 0 or TDM Channel [2x]+1 Ready Flag (Cleared by writing I2SMCC_THR/THRxR)" "0: Cleared when either I2SMCC_THRxR is written or..,1: Set when I2SMCC_THR or I2SMCC_THLxR is empty."
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|
bitfld.long 0x4 0. "TXLRDY0,I2S Transmit Left 0 or TDM Channel 2x Ready Flag (Cleared by writing I2SMCC_THR/THLxR)" "0: Cleared when either I2SMCC_THLxR is written or..,1: Set when I2SMCC_THR or I2SMCC_THLxR is empty."
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|
wgroup.long 0x20++0x7
|
|
line.long 0x0 "IERB,Interrupt Enable Register B"
|
|
bitfld.long 0x0 13. "RXFFFUL,RX FIFO Full Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 12. "RXFFRDY,RX FIFO Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXFFEMP,TX FIFO Empty Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 8. "TXFFRDY,TX FIFO Ready Interrupt Enable" "0,1"
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|
newline
|
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bitfld.long 0x0 0. "WERR,Write Error Interrupt Enable" "0,1"
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line.long 0x4 "IDRB,Interrupt Disable Register B"
|
|
bitfld.long 0x4 13. "RXFFFUL,RTX FIFO Full Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 12. "RXFFRDY,RX FIFO Ready Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 9. "TXFFEMP,TX FIFO Empty Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 8. "TXFFRDY,TX FIFO Ready Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "WERR,Write Error Interrupt Disable" "0,1"
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|
rgroup.long 0x28++0xB
|
|
line.long 0x0 "IMRB,Interrupt Mask Register B"
|
|
bitfld.long 0x0 13. "RXFFFUL,RX FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 12. "RXFFRDY,RX FIFO Ready Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 9. "TXFFEMP,TX FIFO Empty Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 8. "TXFFRDY,TX FIFO Ready Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "WERR,Write Error Interrupt Enable" "0,1"
|
|
line.long 0x4 "ISRB,Interrupt Status Register B"
|
|
bitfld.long 0x4 13. "RXFFFUL,RX FIFO Full Flag (Cleared on read)" "0: Cleared when I2SMCC_ISRB is read.,1: Set when RX FIFO is full. This status bit is not.."
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bitfld.long 0x4 12. "RXFFRDY,RX FIFO Ready Flag (Cleared on read)" "0: Cleared when I2SMCC_ISRB is read.,1: Set when RX FIFO is ready to be read. This.."
|
|
newline
|
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bitfld.long 0x4 9. "TXFFEMP,TX FIFO Empty Flag (Cleared on read)" "0: Cleared when I2SMCC_ISRB is read.,1: Set when TX FIFO is empty. This status bit is.."
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bitfld.long 0x4 8. "TXFFRDY,TX FIFO Ready Flag (Cleared on read)" "0: Cleared when I2SMCC_ISRB is read.,1: Set when TX FIFO is ready to be written. This.."
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|
newline
|
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bitfld.long 0x4 0. "WERR,Write Error Flag (cleared on read)" "0: Cleared when I2SMCC_ISRB is read.,1: Set when a write occurs in a protected register."
|
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line.long 0x8 "RHR,Receiver Holding Register"
|
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hexmask.long 0x8 0.--31. 1. "RHR,Receiver Holding Register"
|
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wgroup.long 0x34++0x3
|
|
line.long 0x0 "THR,Transmitter Holding Register"
|
|
hexmask.long 0x0 0.--31. 1. "THR,Transmitter Holding Register"
|
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repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0xE1620040 ad:0xE1620048 ad:0xE1620050 ad:0xE1620058)
|
|
tree "I2SMCC_RH[$1]"
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base $2
|
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rgroup.long ($2)++0x7
|
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line.long 0x0 "RHLxR,Receiver Holding Left x Register"
|
|
hexmask.long 0x0 0.--31. 1. "RHL,Receiver Holding Left"
|
|
line.long 0x4 "RHRxR,Receiver Holding Right x Register"
|
|
hexmask.long 0x4 0.--31. 1. "RHR,Receiver Holding Right"
|
|
tree.end
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0xE1620060 ad:0xE1620068 ad:0xE1620070 ad:0xE1620078)
|
|
tree "I2SMCC_TH[$1]"
|
|
base $2
|
|
wgroup.long ($2)++0x7
|
|
line.long 0x0 "THLxR,Transmitter Holding Left x Register"
|
|
hexmask.long 0x0 0.--31. 1. "THL,Transmitter Holding Left"
|
|
line.long 0x4 "THRxR,Transmitter Holding Right x Register"
|
|
hexmask.long 0x4 0.--31. 1. "THR,Transmitter Holding Right"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0xE1620000
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
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bitfld.long 0x0 2. "WPCTEN,Write Protection Control Enable" "0: Disables the write protection of the control if..,1: Enables the write protection of the control if.."
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|
newline
|
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection of the..,1: Enables the write protection of the interruption.."
|
|
bitfld.long 0x0 0. "WPCFEN,Write Protection Configuration Enable" "0: Disables the write protection of the..,1: Enables the write protection of the.."
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
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|
tree.end
|
|
tree.end
|
|
tree "ICM (Integrity Check Monitor)"
|
|
base ad:0xE081C000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CFG,Configuration Register"
|
|
bitfld.long 0x0 13.--15. "UALGO,User SHA Algorithm" "0: SHA1 algorithm processed,1: SHA256 algorithm processed,?,?,4: SHA224 algorithm processed,?,?,?"
|
|
bitfld.long 0x0 12. "UIHASH,User Initial Hash Value" "0: The secure hash standard provides the initial..,1: The initial hash value is programmable. Field.."
|
|
newline
|
|
bitfld.long 0x0 9. "DUALBUFF,Dual Input Buffer" "0: Dual Input Buffer mode is disabled.,1: Dual Input Buffer mode is enabled (better.."
|
|
bitfld.long 0x0 8. "ASCD,Automatic Switch To Compare Digest" "0: Automatic monitoring mode is disabled.,1: The ICM passes through the Main List once to.."
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "BBC,Bus Burden Control"
|
|
bitfld.long 0x0 2. "SLBDIS,Secondary List Branching Disable" "0: Branching to the Secondary List is permitted.,1: Branching to the Secondary List is forbidden."
|
|
newline
|
|
bitfld.long 0x0 1. "EOMDIS,End of Monitoring Disable" "0: End of Monitoring is permitted.,1: End of Monitoring is forbidden. The EOM bit of.."
|
|
bitfld.long 0x0 0. "WBDIS,Write-Back Disable" "0: Write-back operations are permitted.,1: Write-back operations are forbidden. Context.."
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "CTRL,Control Register"
|
|
hexmask.long.byte 0x0 12.--15. 1. "RMEN,Region Monitoring Enable"
|
|
hexmask.long.byte 0x0 8.--11. 1. "RMDIS,Region Monitoring Disable"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "REHASH,Recompute Internal Hash"
|
|
bitfld.long 0x0 2. "SWRST,Software Reset" "0: No effect,1: Resets the ICM."
|
|
newline
|
|
bitfld.long 0x0 1. "DISABLE,ICM Disable Register" "0: No effect,1: The ICM is disabled. If a region is active this.."
|
|
bitfld.long 0x0 0. "ENABLE,ICM Enable" "0: No effect,1: When set to one the ICM is activated."
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
hexmask.long.byte 0x0 12.--15. 1. "RMDIS,Region Monitoring Disabled Status"
|
|
hexmask.long.byte 0x0 8.--11. 1. "RAWRMDIS,Region Monitoring Disabled Raw Status"
|
|
newline
|
|
bitfld.long 0x0 0. "ENABLE,ICM Enable Register" "0: ICM is disabled.,1: ICM is activated."
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 24. "URAD,Undefined Register Access Detection Interrupt Enable" "0: No effect.,1: The Undefined Register Access interrupt is.."
|
|
hexmask.long.byte 0x0 20.--23. 1. "RSU,Region Status Updated Interrupt Disable"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "REC,Region End bit Condition Detected Interrupt Enable"
|
|
hexmask.long.byte 0x0 12.--15. 1. "RWC,Region Wrap Condition detected Interrupt Enable"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "RBE,Region Bus Error Interrupt Enable"
|
|
hexmask.long.byte 0x0 4.--7. 1. "RDM,Region Digest Mismatch Interrupt Enable"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "RHC,Region Hash Completed Interrupt Enable"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 24. "URAD,Undefined Register Access Detection Interrupt Disable" "0: No effect.,1: Undefined Register Access Detection interrupt is.."
|
|
hexmask.long.byte 0x4 20.--23. 1. "RSU,Region Status Updated Interrupt Disable"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--19. 1. "REC,Region End bit Condition detected Interrupt Disable"
|
|
hexmask.long.byte 0x4 12.--15. 1. "RWC,Region Wrap Condition Detected Interrupt Disable"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "RBE,Region Bus Error Interrupt Disable"
|
|
hexmask.long.byte 0x4 4.--7. 1. "RDM,Region Digest Mismatch Interrupt Disable"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "RHC,Region Hash Completed Interrupt Disable"
|
|
rgroup.long 0x18++0xB
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 24. "URAD,Undefined Register Access Detection Interrupt Mask" "0: Interrupt is disabled,1: Interrupt is enabled."
|
|
hexmask.long.byte 0x0 20.--23. 1. "RSU,Region Status Updated Interrupt Mask"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "REC,Region End bit Condition Detected Interrupt Mask"
|
|
hexmask.long.byte 0x0 12.--15. 1. "RWC,Region Wrap Condition Detected Interrupt Mask"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "RBE,Region Bus Error Interrupt Mask"
|
|
hexmask.long.byte 0x0 4.--7. 1. "RDM,Region Digest Mismatch Interrupt Mask"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "RHC,Region Hash Completed Interrupt Mask"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 24. "URAD,Undefined Register Access Detection Status" "0: No undefined register access has been detected..,1: At least one undefined register access has been.."
|
|
hexmask.long.byte 0x4 20.--23. 1. "RSU,Region Status Updated Detected"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--19. 1. "REC,Region End Bit Condition Detected"
|
|
hexmask.long.byte 0x4 12.--15. 1. "RWC,Region Wrap Condition Detected"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "RBE,Region Bus Error"
|
|
hexmask.long.byte 0x4 4.--7. 1. "RDM,Region Digest Mismatch"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "RHC,Region Hash Completed"
|
|
line.long 0x8 "UASR,Undefined Access Status Register"
|
|
bitfld.long 0x8 0.--2. "URAT,Undefined Register Access Trace" "0: Unspecified structure member set to one detected..,1: ICM_CFG modified during active monitoring.,2: ICM_DSCR modified during active monitoring.,3: ICM_HASH modified during active monitoring,4: Write-only register read access,?,?,?"
|
|
group.long 0x30++0x7
|
|
line.long 0x0 "DSCR,Region Descriptor Area Start Address Register"
|
|
hexmask.long 0x0 6.--31. 1. "DASA,Descriptor Area Start Address"
|
|
line.long 0x4 "HASH,Region Hash Area Start Address Register"
|
|
hexmask.long 0x4 7.--31. 1. "HASA,Hash Area Start Address"
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x38)++0x3
|
|
line.long 0x0 "UIHVAL[$1],User Initial Hash Value x Register"
|
|
hexmask.long 0x0 0.--31. 1. "VAL,Initial Hash Value"
|
|
repeat.end
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status (Cleared on read)" "0: No write protect violation has occurred since..,1: A write protect violation has occurred since the.."
|
|
tree.end
|
|
tree "ISC (Image Sensor Controller)"
|
|
base ad:0xE1408000
|
|
wgroup.long 0x0++0x7
|
|
line.long 0x0 "CTRLEN,Control Enable Register"
|
|
bitfld.long 0x0 9. "FUPPRO,Force Update Color Profile" "0,1"
|
|
bitfld.long 0x0 3. "HISCLR,Histogram Table Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "HISREQ,Histogram Update Request" "0,1"
|
|
bitfld.long 0x0 1. "UPPRO,Update Color Profile" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CAPTURE,Single Shot or Multiple Frame Capture Input Stream Command" "0,1"
|
|
line.long 0x4 "CTRLDIS,Control Disable Register"
|
|
bitfld.long 0x4 8. "SWRST,Software Reset" "0,1"
|
|
bitfld.long 0x4 0. "DISABLE,End Capture At Next Vertical Synchronization Detection" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "CTRLSR,Control Status Register"
|
|
bitfld.long 0x0 31. "SIP,Synchronization In Progress" "0: The double domain synchronization is terminated.,1: The double domain synchronization is in progress."
|
|
bitfld.long 0x0 4. "FIELD,Field Status (only relevant when the video stream is interlaced)" "0: The current field/segment is a top field,1: The current field/segment is a bottom field."
|
|
newline
|
|
bitfld.long 0x0 2. "HISREQ,Histogram Request Pending" "0: There is no histogram pending request.,1: Indicates that the histogram request is still.."
|
|
bitfld.long 0x0 1. "UPPRO,Profile Update Pending" "0: There is no profile update pending request.,1: Indicates that the profile update request is.."
|
|
newline
|
|
bitfld.long 0x0 0. "CAPTURE,Capture Pending" "0: Capture mode is disabled.,1: Capture is pending."
|
|
group.long 0xC++0xB
|
|
line.long 0x0 "PFE_CFG0,Parallel Front End Configuration 0 Register"
|
|
bitfld.long 0x0 31. "REP,Up Multiply with Replication" "0: Unused bits are stuck at 0.,1: Unused bits are copied from MSB."
|
|
bitfld.long 0x0 28.--30. "BPS,Bits Per Sample" "0: 12-bit input,1: 11-bit input,2: 10-bit input,3: 9-bit input,4: 8-bit input,5: 40-bit input (used for MIPI formats up to forty..,?,?"
|
|
newline
|
|
bitfld.long 0x0 27. "CCIR_REP,CCIR Replication" "0: Unused bits are stuck at 0.,1: Unused bits are copied from MSB."
|
|
hexmask.long.byte 0x0 16.--23. 1. "SKIPCNT,Frame Skipping Counter"
|
|
newline
|
|
bitfld.long 0x0 14. "MIPI,MIPI Interface Connection" "0: Input Data are coming from the physical Parallel..,1: Input Data are coming from the physical MIPI.."
|
|
bitfld.long 0x0 13. "ROWEN,Row Cropping Enable" "0: Row Cropping is disabled.,1: Row Cropping is enabled."
|
|
newline
|
|
bitfld.long 0x0 12. "COLEN,Column Cropping Enable" "0: Column Cropping is disabled.,1: Column Cropping is enabled."
|
|
bitfld.long 0x0 11. "CCIR10_8N,CCIR 10 bits or 8 bits" "0: 8-bit mode.,1: 10-bit mode."
|
|
newline
|
|
bitfld.long 0x0 10. "CCIR_CRC,CCIR656 CRC Decoder" "0: Embedded CRC is discarded.,1: Embedded CRC is decoded."
|
|
bitfld.long 0x0 9. "CCIR656,CCIR656 input mode" "0: HSYNC and VSYNC signals are used to synchronize..,1: Embedded synchronization is used."
|
|
newline
|
|
bitfld.long 0x0 8. "GATED,Gated input clock" "0: The external pixel clock is free running.,1: The external pixel clock is gated."
|
|
bitfld.long 0x0 7. "CONT,Continuous Acquisition" "0: Single Shot mode.,1: Video mode."
|
|
newline
|
|
bitfld.long 0x0 4.--6. "MODE,Parallel Front End Mode" "0: Video source is progressive.,1: Video source is interlaced two fields are..,2: Video source is interlaced two fields are..,3: Video source is interlaced two fields are..,4: Video source is interlaced one field is captured..,5: Video source is interlaced one field is captured..,6: Video source is interlaced one field is captured..,?"
|
|
bitfld.long 0x0 3. "FPOL,Field Polarity" "0: Top field is sampled when F value is 0; Bottom..,1: Top field is sampled when F value is 1; Bottom.."
|
|
newline
|
|
bitfld.long 0x0 2. "PPOL,Pixel Clock Polarity" "0: The pixel stream is sampled on the rising edge..,1: The pixel stream is sampled on the falling edge.."
|
|
bitfld.long 0x0 1. "VPOL,Vertical Synchronization Polarity" "0: VSYNC signal is active high i.e. valid pixels..,1: VSYNC signal is active low i.e. valid pixels are.."
|
|
newline
|
|
bitfld.long 0x0 0. "HPOL,Horizontal Synchronization Polarity" "0: HSYNC signal is active high i.e. valid pixels..,1: HSYNC signal is active low i.e. valid pixels are.."
|
|
line.long 0x4 "PFE_CFG1,Parallel Front End Configuration 1 Register"
|
|
hexmask.long.word 0x4 16.--31. 1. "COLMAX,Column Maximum Limit"
|
|
hexmask.long.word 0x4 0.--15. 1. "COLMIN,Column Minimum Limit"
|
|
line.long 0x8 "PFE_CFG2,Parallel Front End Configuration 2 Register"
|
|
hexmask.long.word 0x8 16.--31. 1. "ROWMAX,Row Maximum Limit"
|
|
hexmask.long.word 0x8 0.--15. 1. "ROWMIN,Row Minimum Limit"
|
|
wgroup.long 0x18++0x7
|
|
line.long 0x0 "CLKEN,Clock Enable Register"
|
|
bitfld.long 0x0 1. "MCEN,Master Clock Enable" "0: No effect.,1: Enables the master clock."
|
|
bitfld.long 0x0 0. "ICEN,ISP Clock Enable" "0: No effect.,1: Enables the ISP clock."
|
|
line.long 0x4 "CLKDIS,Clock Disable Register"
|
|
bitfld.long 0x4 9. "MCSWRST,Master Clock Software Reset" "0,1"
|
|
bitfld.long 0x4 8. "ICSWRST,ISP Clock Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "MCDIS,Master Clock Disable" "0,1"
|
|
bitfld.long 0x4 0. "ICDIS,ISP Clock Disable" "0,1"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "CLKSR,Clock Status Register"
|
|
bitfld.long 0x0 31. "SIP,Synchronization In Progress" "0: The double domain synchronization operation is..,1: The double domain synchronization operation is.."
|
|
bitfld.long 0x0 1. "MCSR,Master Clock Status Register" "0: The master clock is disabled.,1: The master clock is enabled."
|
|
newline
|
|
bitfld.long 0x0 0. "ICSR,ISP Clock Status Register" "0: The ISP clock is disabled.,1: The ISP clock is enabled."
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "CLKCFG,Clock Configuration Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "MCDIV,Master Clock Divider"
|
|
wgroup.long 0x28++0x7
|
|
line.long 0x0 "INTEN,Interrupt Enable Register"
|
|
bitfld.long 0x0 29. "GFOV,Input FIFO Overflow Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 28. "CCIRERR,CCIR Decoder Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "HDTO,Horizontal Synchronization Timeout Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 26. "VDTO,Vertical Synchronization Timeout Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "DAOV,Data Overflow Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 24. "VFPOV,Vertical Front Porch Overflow Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "RERR,Read Channel Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 16. "WERR,Write Channel Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "HISCLR,Histogram Clear Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 12. "HISDONE,Histogram Completed Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "LDONE,DMA List Done Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 8. "DDONE,DMA Done Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "DIS,Disable Completed Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "SWRST,Software Reset Completed Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "HD,Horizontal Synchronization Detection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "VD,Vertical Synchronization Detection Interrupt Enable" "0,1"
|
|
line.long 0x4 "INTDIS,Interrupt Disable Register"
|
|
bitfld.long 0x4 29. "GFOV,FIFO Overflow Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 28. "CCIRERR,CCIR Decoder Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "HDTO,Horizontal Synchronization Timeout Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 26. "VDTO,Vertical Synchronization Timeout Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "DAOV,Data Overflow Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 24. "VFPOV,Vertical Front Porch Overflow Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "RERR,Read Channel Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 16. "WERR,Write Channel Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "HISCLR,Histogram Clear Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 12. "HISDONE,Histogram Completed Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "LDONE,DMA List Done Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 8. "DDONE,DMA Done Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "DIS,Disable Completed Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 4. "SWRST,Software Reset Completed Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "HD,Horizontal Synchronization Detection Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "VD,Vertical Synchronization Detection Interrupt Disable" "0,1"
|
|
rgroup.long 0x30++0x7
|
|
line.long 0x0 "INTMASK,Interrupt Mask Register"
|
|
bitfld.long 0x0 29. "GFOV,FIFO Overflow Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 28. "CCIRERR,CCIR Decoder Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "HDTO,Horizontal Synchronization Timeout Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 26. "VDTO,Vertical Synchronization Timeout Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "DAOV,Data Overflow Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 24. "VFPOV,Vertical Front Porch Overflow Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "RERR,Read Channel Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 16. "WERR,Write Channel Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "HISCLR,Histogram Clear Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 12. "HISDONE,Histogram Completed Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "LDONE,DMA List Done Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 8. "DDONE,DMA Done Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "DIS,Disable Completed Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 4. "SWRST,Software Reset Completed Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "HD,Horizontal Synchronization Detection Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "VD,Vertical Synchronization Detection Interrupt Mask" "0,1"
|
|
line.long 0x4 "INTSR,Interrupt Status Register"
|
|
bitfld.long 0x4 29. "GFOV,FIFO Overflow Interrupt (relevant if MIPI interface is not selected) (cleared on read)" "0: No FIFO overflow detected since the last read of..,1: A FIFO overflow has been detected."
|
|
bitfld.long 0x4 28. "CCIRERR,CCIR Decoder Error Interrupt (cleared on read)" "0: No CCIR CRC error detected since the last read..,1: A CCIR CRC error has been detected."
|
|
newline
|
|
bitfld.long 0x4 27. "HDTO,Horizontal Synchronization Timeout Interrupt (cleared on read)" "0: Horizontal synchronization is detected since the..,1: No horizontal synchronization is detected."
|
|
bitfld.long 0x4 26. "VDTO,Vertical Synchronization Timeout Interrupt (cleared on read)" "0: A vertical synchronization is detected since the..,1: No vertical synchronization is detected."
|
|
newline
|
|
bitfld.long 0x4 25. "DAOV,Data Overflow Interrupt (cleared on read)" "0: No data overflow error occurred since the last..,1: A data overflow occurred."
|
|
bitfld.long 0x4 24. "VFPOV,Vertical Front Porch Overflow Interrupt (cleared on read)" "0: No vertical front porch error occurred since the..,1: The vertical synchronization has been detected.."
|
|
newline
|
|
bitfld.long 0x4 20. "RERR,Read Channel Error Interrupt (cleared on read)" "0: No read channel error since the last read of the..,1: A read channel error occurred when the ISC read.."
|
|
bitfld.long 0x4 17.--18. "WERRID,Write Channel Error Identifier" "0: An error occurred for Channel 0 (RAW/RGB/Y),1: An error occurred for Channel 1 (CbCr/Cb),2: An error occurred for Channel 2 (Cr),3: Write back channel error"
|
|
newline
|
|
bitfld.long 0x4 16. "WERR,Write Channel Error Interrupt (cleared on read)" "0: No write channel error since the last read of..,1: A write channel error occurred."
|
|
bitfld.long 0x4 13. "HISCLR,Histogram Clear Interrupt (cleared on read)" "0: No Histogram Clear interrupt has been raised..,1: The Histogram Clear interrupt has occurred."
|
|
newline
|
|
bitfld.long 0x4 12. "HISDONE,Histogram Completed Interrupt (cleared on read)" "0: No Histogram Completed interrupt has been raised..,1: The Histogram Completed interrupt has occurred."
|
|
bitfld.long 0x4 9. "LDONE,DMA List Done Interrupt (cleared on read)" "0: No DMA List Done interrupt has occurred since..,1: The DMA List Done interrupt has occurred."
|
|
newline
|
|
bitfld.long 0x4 8. "DDONE,DMA Done Interrupt (cleared on read)" "0: No DMA Transfer Done interrupt has occurred..,1: The DMA Transfer Done interrupt has occurred."
|
|
bitfld.long 0x4 5. "DIS,Disable Completed Interrupt (cleared on read)" "0: The disable has not occurred since the last read..,1: The disable has completed."
|
|
newline
|
|
bitfld.long 0x4 4. "SWRST,Software Reset Completed Interrupt (cleared on read)" "0: No software reset completion since the last read..,1: The software reset has completed."
|
|
bitfld.long 0x4 1. "HD,Horizontal Synchronization Detected Interrupt (cleared on read)" "0: No horizontal synchronization detection since..,1: A horizontal synchronization has been detected."
|
|
newline
|
|
bitfld.long 0x4 0. "VD,Vertical Synchronization Detected Interrupt (cleared on read)" "0: No vertical synchronization detection since the..,1: A vertical synchronization has been detected."
|
|
group.long 0x40++0x13
|
|
line.long 0x0 "DPC_CTRL,Defective Pixel Correction Control Register"
|
|
bitfld.long 0x0 2. "BLCEN,Black Level Correction Enable" "0: Black level correction is disabled.,1: Black level correction is enabled."
|
|
bitfld.long 0x0 1. "GDCEN,Green Disparity Correction Enable" "0: Green disparity correction is disabled.,1: Green disparity correction is enabled."
|
|
newline
|
|
bitfld.long 0x0 0. "DPCEN,Defective Pixel Correction Enable" "0: Defective pixel correction is disabled.,1: Defective pixel correction is enabled."
|
|
line.long 0x4 "DPC_CFG,Defective Pixel Correction Configuration Register"
|
|
hexmask.long.word 0x4 23.--31. 1. "BLOFST,Black Level Offset Value"
|
|
bitfld.long 0x4 20.--22. "GDCCLP,Green Disparity Clipping Value" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 17. "RE_MODE,Replacement Algorithm" "0: Median pixel is used.,1: Average pixel is used."
|
|
bitfld.long 0x4 16. "ND_MODE,Noise Detection Mode" "0: At least one detector flag is necessary to..,1: All detector flags are required to trigger the.."
|
|
newline
|
|
bitfld.long 0x4 14. "TA_ENABLE,Average Threshold Enable" "0: Average detector is disabled.,1: Average detector is enabled."
|
|
bitfld.long 0x4 13. "TC_ENABLE,Closest Pixels Threshold Enable" "0: Closest Pixels detector is disabled.,1: Closest Pixels detector is enabled."
|
|
newline
|
|
bitfld.long 0x4 12. "TM_ENABLE,Median Threshold Enable" "0: Median detector is disabled.,1: Median detector is enabled."
|
|
bitfld.long 0x4 4. "EITPOL,Edge Interpolation" "0: No edge interpolation is performed.,1: Edge interpolation is performed."
|
|
newline
|
|
bitfld.long 0x4 0.--1. "BAYCFG,Color Filter Array Pattern" "0: Starting row configuration is G R G R (red row),1: Starting row configuration is R G R G (red row),2: Starting row configuration is G B G B (blue row),3: Starting row configuration is B G B G (blue row)"
|
|
line.long 0x8 "DPC_THRESHM,Defective Pixel Correction Threshold M Register"
|
|
hexmask.long.word 0x8 0.--11. 1. "THRESHM,Median Threshold"
|
|
line.long 0xC "DPC_THRESHC,Defective Pixel Correction Threshold C Register"
|
|
hexmask.long.word 0xC 0.--11. 1. "THRESHC,Closest Pixel Threshold"
|
|
line.long 0x10 "DPC_THRESHA,Defective Pixel Correction Threshold A Register"
|
|
hexmask.long.word 0x10 0.--11. 1. "THRESHA,Average Threshold"
|
|
rgroup.long 0x54++0x3
|
|
line.long 0x0 "DPC_SR,Defective Pixel Correction Status Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "COUNTER,Defective Pixel Counter (cleared on read)"
|
|
group.long 0x58++0x3F
|
|
line.long 0x0 "WB_CTRL,White Balance Control Register"
|
|
bitfld.long 0x0 0. "ENABLE,White Balance Enable" "0: The white balance is disabled.,1: The white balance is enabled."
|
|
line.long 0x4 "WB_CFG,White Balance Configuration Register"
|
|
bitfld.long 0x4 0.--1. "BAYCFG,White Balance Bayer Configuration (Pixel Color Pattern)" "0: Starting Row configuration is G R G R (Red Row),1: Starting Row configuration is R G R G (Red Row),2: Starting Row configuration is G B G B (Blue Row),3: Starting Row configuration is B G B G (Blue Row)"
|
|
line.long 0x8 "WB_O_RGR,White Balance Offset for R. GR Register"
|
|
hexmask.long.word 0x8 16.--28. 1. "GROFST,Offset Green Component for Red Row (signed 13 bits 1:12:0)"
|
|
hexmask.long.word 0x8 0.--12. 1. "ROFST,Offset Red Component (signed 13 bits 1:12:0)"
|
|
line.long 0xC "WB_O_BGB,White Balance Offset for B. GB Register"
|
|
hexmask.long.word 0xC 16.--28. 1. "GBOFST,Offset Green Component for Blue Row (signed 13 bits 1:12:0)"
|
|
hexmask.long.word 0xC 0.--12. 1. "BOFST,Offset Blue Component (signed 13 bits 1:12:0)"
|
|
line.long 0x10 "WB_G_RGR,White Balance Gain for R. GR Register"
|
|
hexmask.long.word 0x10 16.--28. 1. "GRGAIN,Green Component (Red row) Gain (unsigned 13 bits 0:4:9)"
|
|
hexmask.long.word 0x10 0.--12. 1. "RGAIN,Red Component Gain (unsigned 13 bits 0:4:9)"
|
|
line.long 0x14 "WB_G_BGB,White Balance Gain for B. GB Register"
|
|
hexmask.long.word 0x14 16.--28. 1. "GBGAIN,Green Component (Blue Row) Gain (unsigned 13 bits 0:4:9)"
|
|
hexmask.long.word 0x14 0.--12. 1. "BGAIN,Blue Component Gain (unsigned 13 bits 0:4:9)"
|
|
line.long 0x18 "CFA_CTRL,Color Filter Array Control Register"
|
|
bitfld.long 0x18 0. "ENABLE,Color Filter Array Interpolation Enable" "0: Color Filter Array Interpolation is disabled.,1: Color Filter Array Interpolation is enabled."
|
|
line.long 0x1C "CFA_CFG,Color Filter Array Configuration Register"
|
|
bitfld.long 0x1C 10.--11. "EAL,Green Channel Edge Adaptive Level" "0: Green plane is linearly interpolated.,1: Green plane is the mean value between the..,2: Green plane is interpolated with edge adaptive..,?"
|
|
bitfld.long 0x1C 4. "EITPOL,Edge Interpolation" "0: Edges are not interpolated.,1: Edge interpolation is performed."
|
|
newline
|
|
bitfld.long 0x1C 0.--1. "BAYCFG,Bayer Color Filter Array Pattern" "0: Starting row configuration is G R G R (red row),1: Starting row configuration is R G R G (red row,2: Starting row configuration is G B G B (blue row),3: Starting row configuration is B G B G (blue row)"
|
|
line.long 0x20 "CC_CTRL,Color Correction Control Register"
|
|
bitfld.long 0x20 0. "ENABLE,Color Correction Enable" "0: Color correction is disabled.,1: Color correction is enabled."
|
|
line.long 0x24 "CC_RR_RG,Color Correction RR RG Register"
|
|
hexmask.long.word 0x24 16.--27. 1. "RGGAIN,Green Gain for Red Component (signed 12 bits 1:3:8)"
|
|
hexmask.long.word 0x24 0.--11. 1. "RRGAIN,Red Gain for Red Component (signed 12 bits 1:3:8)"
|
|
line.long 0x28 "CC_RB_OR,Color Correction RB OR Register"
|
|
hexmask.long.word 0x28 16.--28. 1. "ROFST,Red Component Offset (signed 13 bits 1:12:0)"
|
|
hexmask.long.word 0x28 0.--11. 1. "RBGAIN,Blue Gain for Red Component (signed 12 bits 1:3:8)"
|
|
line.long 0x2C "CC_GR_GG,Color Correction GR GG Register"
|
|
hexmask.long.word 0x2C 16.--27. 1. "GGGAIN,Green Gain for Green Component (signed 12 bits 1:3:8)"
|
|
hexmask.long.word 0x2C 0.--11. 1. "GRGAIN,Red Gain for Green Component (signed 12 bits 1:3:8)"
|
|
line.long 0x30 "CC_GB_OG,Color Correction GB OG Register"
|
|
hexmask.long.word 0x30 16.--28. 1. "ROFST,Green Component Offset (signed 13 bits 1:12:0)"
|
|
hexmask.long.word 0x30 0.--11. 1. "GBGAIN,Blue Gain for Green Component (signed 12 bits 1:3:8)"
|
|
line.long 0x34 "CC_BR_BG,Color Correction BR BG Register"
|
|
hexmask.long.word 0x34 16.--27. 1. "BGGAIN,Green Gain for Blue Component (signed 12 bits 1:3:8)"
|
|
hexmask.long.word 0x34 0.--11. 1. "BRGAIN,Red Gain for Blue Component (signed 12 bits 1:3:8)"
|
|
line.long 0x38 "CC_BB_OB,Color Correction BB OB Register"
|
|
hexmask.long.word 0x38 16.--28. 1. "BOFST,Blue Component Offset (signed 13 bits 1:12:0)"
|
|
hexmask.long.word 0x38 0.--11. 1. "BBGAIN,Blue Gain for Blue Component (signed 12 bits 1:3:8)"
|
|
line.long 0x3C "GAM_CTRL,Gamma Correction Control Register"
|
|
bitfld.long 0x3C 4. "BIPART,Bipartite Table Configuration" "0: Bipartite table is disabled. There are 64 points..,1: Bipartite table is enabled. There are 32 points.."
|
|
bitfld.long 0x3C 3. "RENABLE,Gamma Correction Enable for R Channel" "0: 12-bit to 10-bit compression is performed..,1: Piecewise interpolation is used to perform.."
|
|
newline
|
|
bitfld.long 0x3C 2. "GENABLE,Gamma Correction Enable for G Channel" "0: 12-bit to 10-bit compression is performed..,1: Piecewise interpolation is used to perform.."
|
|
bitfld.long 0x3C 1. "BENABLE,Gamma Correction Enable for B Channel" "0: 12-bit to 10-bit compression is performed..,1: Piecewise interpolation is used to perform.."
|
|
newline
|
|
bitfld.long 0x3C 0. "ENABLE,Gamma Correction Enable" "0: Gamma correction is disabled.,1: Gamma correction is enabled."
|
|
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x98)++0x3
|
|
line.long 0x0 "GAM_BENTRY[$1],Gamma Correction Blue Entry x"
|
|
hexmask.long.word 0x0 16.--25. 1. "BCONSTANT,Blue Color Constant for Piecewise Interpolation (unsigned 10 bits 0:10:0)"
|
|
hexmask.long.word 0x0 0.--9. 1. "BSLOPE,Blue Color Slope for Piecewise Interpolation (signed 10 bits 1:3:6)"
|
|
repeat.end
|
|
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x198)++0x3
|
|
line.long 0x0 "GAM_GENTRY[$1],Gamma Correction Green Entry x"
|
|
hexmask.long.word 0x0 16.--25. 1. "GCONSTANT,Green Color Constant for Piecewise Interpolation (unsigned 10 bits 0:10:0)"
|
|
hexmask.long.word 0x0 0.--9. 1. "GSLOPE,Green Color Slope for Piecewise Interpolation (signed 10 bits 1:3:6)"
|
|
repeat.end
|
|
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x298)++0x3
|
|
line.long 0x0 "GAM_RENTRY[$1],Gamma Correction Red Entry x"
|
|
hexmask.long.word 0x0 16.--25. 1. "RCONSTANT,Red Color Constant for Piecewise Interpolation (unsigned 10 bits 0:10:0)"
|
|
hexmask.long.word 0x0 0.--9. 1. "RSLOPE,Red Color Slope for Piecewise Interpolation (signed 10 bits 1:3:6)"
|
|
repeat.end
|
|
group.long 0x398++0x1B
|
|
line.long 0x0 "VHXS_CTRL,VHXS Control Register"
|
|
bitfld.long 0x0 1. "HXSEN,Horizontal Scaler Enable" "0: Horizontal scaler is disabled.,1: Horizontal scaler is enabled."
|
|
bitfld.long 0x0 0. "VXSEN,Vertical Scaler Enable" "0: Vertical scaler is disabled.,1: Vertical scaler is enabled."
|
|
line.long 0x4 "VHXS_SS,VHXS Source Size Register"
|
|
hexmask.long.word 0x4 16.--27. 1. "YS,Source Image Vertical Size"
|
|
hexmask.long.word 0x4 0.--11. 1. "XS,Source Image Horizontal Size"
|
|
line.long 0x8 "VHXS_DS,VHXS Destination Size Register"
|
|
hexmask.long.word 0x8 16.--27. 1. "YD,Destination Image Horizontal Size"
|
|
hexmask.long.word 0x8 0.--11. 1. "XD,Destination Image Horizontal Size"
|
|
line.long 0xC "VXS_FACT,VXS Scaling Factor Register"
|
|
hexmask.long.tbyte 0xC 0.--23. 1. "VFACT,Vertical Scaling Factor"
|
|
line.long 0x10 "HXS_FACT,HXS Scaling Factor Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. "HFACT,Horizontal Scaling Factor"
|
|
line.long 0x14 "VXS_CFG,VXS Configuration Register"
|
|
hexmask.long.byte 0x14 28.--31. 1. "FLMAX,flush latency max"
|
|
hexmask.long.byte 0x14 24.--27. 1. "FLMIN,flush latency min"
|
|
newline
|
|
hexmask.long.byte 0x14 8.--11. 1. "OFFSET,Resampling Default Phase"
|
|
bitfld.long 0x14 4. "TAP2,Bilinear Interpolation" "0: Bicubic interpolation is used.,1: Bilinear interpolation is used."
|
|
newline
|
|
bitfld.long 0x14 0.--1. "FILTCFG,Vertical Filter Initial Configuration" "0,1,2,3"
|
|
line.long 0x18 "HXS_CFG,HXS Configuration Register"
|
|
hexmask.long.byte 0x18 24.--27. 1. "FL,Flush Latency"
|
|
hexmask.long.byte 0x18 8.--11. 1. "OFFSET,Resampling Default Phase"
|
|
newline
|
|
bitfld.long 0x18 4. "TAP2,Bilinear Interpolation" "0: Bicubic interpolation is used.,1: Bilinear interpolation is used."
|
|
bitfld.long 0x18 0.--1. "FILTCFG,Horizontal Filter Initial Configuration" "0,1,2,3"
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0xE14083B4 ad:0xE14083BC ad:0xE14083C4 ad:0xE14083CC ad:0xE14083D4 ad:0xE14083DC ad:0xE14083E4 ad:0xE14083EC ad:0xE14083F4 ad:0xE14083FC ad:0xE1408404 ad:0xE140840C ad:0xE1408414 ad:0xE140841C ad:0xE1408424 ad:0xE140842C)
|
|
tree "ISC_VXS_TAP[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "VXS_TAP10PHI,VXS TAP10 Phase Register"
|
|
hexmask.long.word 0x0 16.--28. 1. "TAP1,Vertical Filter Tap 1 Coefficient"
|
|
hexmask.long.word 0x0 0.--12. 1. "TAP0,Vertical Filter Tap 0 Coefficient"
|
|
line.long 0x4 "VXS_TAP32PHI,VXS TAP32 Phase Register"
|
|
hexmask.long.word 0x4 16.--28. 1. "TAP3,Vertical Filter Tap 3 Coefficient"
|
|
hexmask.long.word 0x4 0.--12. 1. "TAP2,Vertical Filter Tap 2 Coefficient"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0xE1408434 ad:0xE140843C ad:0xE1408444 ad:0xE140844C ad:0xE1408454 ad:0xE140845C ad:0xE1408464 ad:0xE140846C ad:0xE1408474 ad:0xE140847C ad:0xE1408484 ad:0xE140848C ad:0xE1408494 ad:0xE140849C ad:0xE14084A4 ad:0xE14084AC)
|
|
tree "ISC_HXS_TAP[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "HXS_TAP10PHI,HXS TAP10 Phase Register"
|
|
hexmask.long.word 0x0 16.--28. 1. "TAP1,Vertical Filter Tap 1 Coefficient"
|
|
hexmask.long.word 0x0 0.--12. 1. "TAP0,Vertical Filter Tap 0 Coefficient"
|
|
line.long 0x4 "HXS_TAP32PHI,HXS TAP32 Phase Register"
|
|
hexmask.long.word 0x4 16.--28. 1. "TAP3,Vertical Filter Tap 3 Coefficient"
|
|
hexmask.long.word 0x4 0.--12. 1. "TAP2,Vertical Filter Tap 2 Coefficient"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0xE1408000
|
|
group.long 0x4B4++0x4B
|
|
line.long 0x0 "CSC_CTRL,Color Space Conversion Control Register"
|
|
bitfld.long 0x0 0. "ENABLE,RGB to YCbCr Color Space Conversion Enable" "0: Color space conversion is disabled.,1: Color space conversion is enabled."
|
|
line.long 0x4 "CSC_YR_YG,Color Space Conversion YR. YG Register"
|
|
hexmask.long.word 0x4 16.--27. 1. "YGGAIN,Green Gain for Luminance (signed 12 bits 1:3:8)"
|
|
hexmask.long.word 0x4 0.--11. 1. "YRGAIN,Reg Gain for Luminance (signed 12 bits 1:3:8)"
|
|
line.long 0x8 "CSC_YB_OY,Color Space Conversion YB. OY Register"
|
|
hexmask.long.word 0x8 16.--26. 1. "YOFST,Luminance Offset (11 bits signed 1:10:0)"
|
|
hexmask.long.word 0x8 0.--11. 1. "YBGAIN,Blue Gain for Luminance Component (12 bits signed 1:3:8)"
|
|
line.long 0xC "CSC_CBR_CBG,Color Space Conversion CBR CBG Register"
|
|
hexmask.long.word 0xC 16.--27. 1. "CBGGAIN,Green Gain for Blue Chrominance (signed 12 bits 1:3:8)"
|
|
hexmask.long.word 0xC 0.--11. 1. "CBRGAIN,Red Gain for Blue Chrominance (signed 12 bits 1:3:8)"
|
|
line.long 0x10 "CSC_CBB_OCB,Color Space Conversion CBB OCB Register"
|
|
hexmask.long.word 0x10 16.--26. 1. "CBOFST,Blue Chrominance Offset (signed 11 bits 1:10:0)"
|
|
hexmask.long.word 0x10 0.--11. 1. "CBBGAIN,Blue Gain for Blue Chrominance (signed 12 bits 1:3:8)"
|
|
line.long 0x14 "CSC_CRR_CRG,Color Space Conversion CRR CRG Register"
|
|
hexmask.long.word 0x14 16.--27. 1. "CRGGAIN,Green Gain for Red Chrominance (signed 12 bits 1:3:8)"
|
|
hexmask.long.word 0x14 0.--11. 1. "CRRGAIN,Red Gain for Red Chrominance (signed 12 bits 1:3:8)"
|
|
line.long 0x18 "CSC_CRB_OCR,Color Space Conversion CRB OCR Register"
|
|
hexmask.long.word 0x18 16.--26. 1. "CROFST,Red Chrominance Offset (signed 11 bits 1:10:0)"
|
|
hexmask.long.word 0x18 0.--11. 1. "CRBGAIN,Blue Gain for Red Chrominance (signed 12 bits 1:3:8)"
|
|
line.long 0x1C "CBHS_CTRL,CBHS Control Register"
|
|
bitfld.long 0x1C 0. "ENABLE,Contrast Brightness Hue and Saturation Control Enable" "0: CBHS control is disabled.,1: CBHS control is enabled."
|
|
line.long 0x20 "CBHS_CFG,CBHS Configuration Register"
|
|
bitfld.long 0x20 1.--2. "CCIRMODE,CCIR656 Byte Ordering" "0: Byte ordering Cb0 Y0 Cr0 Y1,1: Byte ordering Cr0 Y0 Cb0 Y1,2: Byte ordering Y0 Cb0 Y1 Cr0,3: Byte ordering Y0 Cr0 Y1 Cb0"
|
|
bitfld.long 0x20 0. "CCIR,CCIR656 Stream Enable" "0: Raw mode.,1: CCIR656 stream."
|
|
line.long 0x24 "CBHS_BRIGHT,CBHS Brightness Register"
|
|
hexmask.long.word 0x24 0.--10. 1. "BRIGHT,Image Brightness Control (signed 11 bits 1:10:0)"
|
|
line.long 0x28 "CBHS_CONT,CBHS Contrast Register"
|
|
hexmask.long.word 0x28 0.--11. 1. "CONTRAST,Image Contrast (unsigned 12 bits 0:4:8)"
|
|
line.long 0x2C "CBHS_HUE,CBHS Hue Register"
|
|
hexmask.long.word 0x2C 0.--8. 1. "HUE,Image Hue value (unsigned 9 bits 0:9:0)"
|
|
line.long 0x30 "CBHS_SAT,CBHS Saturation Register"
|
|
hexmask.long.word 0x30 0.--11. 1. "SATURATION,Image Saturation Value (unsigned 12 bits 0:8:4)"
|
|
line.long 0x34 "SUB422_CTRL,Subsampling 4:4:4 to 4:2:2 Control Register"
|
|
bitfld.long 0x34 0. "ENABLE,4:4:4 to 4:2:2 Chrominance Horizontal Subsampling Filter Enable" "0: Subsampler is disabled.,1: Subsampler is enabled."
|
|
line.long 0x38 "SUB422_CFG,Subsampling 4:4:4 to 4:2:2 Configuration Register"
|
|
bitfld.long 0x38 4.--5. "FILTER,Low Pass Filter Selection" "0: Cosited {1},1: Centered {1 1},2: Cosited {1 2 1},3: Centered {1 3 3 1}"
|
|
bitfld.long 0x38 1.--2. "CCIRMODE,CCIR656 Byte Ordering" "0: Byte ordering Cb0 Y0 Cr0 Y1,1: Byte ordering Cr0 Y0 Cb0 Y1,2: Byte ordering Y0 Cb0 Y1 Cr0,3: Byte ordering Y0 Cr0 Y1 Cb0"
|
|
newline
|
|
bitfld.long 0x38 0. "CCIR,CCIR656 Input Stream" "0: Raw mode.,1: CCIR mode."
|
|
line.long 0x3C "SUB420_CTRL,Subsampling 4:2:2 to 4:2:0 Control Register"
|
|
bitfld.long 0x3C 5. "MIPI420,MIPI YUV 420 8-bpp or 10-bpp Even Odd Splitter" "0: Normal mode.,1: When the MIPI interface is selected and the.."
|
|
bitfld.long 0x3C 4. "FILTER,Interlaced or Progressive Chrominance Filter" "0: Progressive filter {0.5 0.5}.,1: Field-dependent filter top field filter is {0.75.."
|
|
newline
|
|
bitfld.long 0x3C 0. "ENABLE,4:2:2 to 4:2:0 Vertical Subsampling Filter Enable (Center Aligned)" "0: Subsampler disabled.,1: Subsampler enabled."
|
|
line.long 0x40 "RLP_CFG,Rounding. Limiting and Packing Configuration Register"
|
|
hexmask.long.byte 0x40 8.--15. 1. "ALPHA,Alpha Value for Alpha-enabled RGB Mode"
|
|
bitfld.long 0x40 6.--7. "YMODE,YCbCr Memory Mapping Configuration Mode" "0: Byte 0 is Cr Byte 1 is Y(n) Byte 2 is Cb Byte 3..,1: Byte 0 is Cb Byte 1 is Y(n) Byte 2 is Cb Byte 3..,2: Byte 0 is Y(n) Byte 1 is Cr Byte 2 is Y(n+1)..,3: Byte 0 is Y (n) Byte 1 is Cb Byte 2 is Y(n+1).."
|
|
newline
|
|
bitfld.long 0x40 5. "LSH,Logical Left Shift for Pixel to 16-bit Container Mapping" "0: Logical left shift is disabled.,1: Pixel value is left-justified in a 16-bit.."
|
|
bitfld.long 0x40 4. "REP,Pixel Expansion with Replication Logic" "0: Replication is disabled.,1: Replication is enabled."
|
|
newline
|
|
hexmask.long.byte 0x40 0.--3. 1. "MODE,Rounding Limiting and Packing Mode"
|
|
line.long 0x44 "HIS_CTRL,Histogram Control Register"
|
|
bitfld.long 0x44 0. "ENABLE,Histogram Sub Module Enable" "0: Histogram disabled.,1: Histogram enabled."
|
|
line.long 0x48 "HIS_CFG,Histogram Configuration Register"
|
|
bitfld.long 0x48 8. "RAR,Histogram Reset After Read" "0: Reset after read mode is disabled.,1: Reset after read mode is enabled."
|
|
bitfld.long 0x48 4.--5. "BAYSEL,Bayer Color Component Selection" "0: Starting row configuration is G R G R (red row),1: Starting row configuration is R G R G (red row),2: Starting row configuration is G B G B (blue row,3: Starting row configuration is B G B G (blue row)"
|
|
newline
|
|
bitfld.long 0x48 0.--2. "MODE,Histogram Operating Mode" "0: Gr sampling,1: R sampling,2: Gb sampling,3: B sampling,4: Luminance-only mode,5: Raw sampling,6: Luminance only with CCIR656 10-bit or 8-bit mode,?"
|
|
group.long 0x51C++0x23
|
|
line.long 0x0 "DCFG,DMA Configuration Register"
|
|
hexmask.long.byte 0x0 20.--23. 1. "AWQOS,Write QoS Value"
|
|
hexmask.long.byte 0x0 16.--19. 1. "ARQOS,Read QoS Value"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "CMBSIZE,DMA Memory Burst Size C channel" "0: DMA single access,1: 4-beat burst access,2: 8-beat burst access,3: 16-beat burst access,4: 32-beat burst access,?,?,?"
|
|
bitfld.long 0x0 4.--6. "YMBSIZE,DMA Memory Burst Size Y channel" "0: DMA single access,1: 4-beat burst access,2: 8-beat burst access,3: 16-beat burst access,4: 32-beat burst access,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "IMODE,DMA Input Mode Selection" "0: 8 bits single channel packed,1: 16 bits single channel packed,2: 32 bits single channel packed,3: 32 bits dual channel,4: 32 bits triple channel,5: 32 bits dual channel,6: 32 bits triple channel,?"
|
|
line.long 0x4 "DCTRL,DMA Control Register"
|
|
bitfld.long 0x4 7. "DONE,Descriptor Processing Status" "0: Descriptor not processed yet.,1: Descriptor processed."
|
|
bitfld.long 0x4 6. "FIELD,Value of Captured Frame Field Signal" "0: Field value is 0.,1: Field value is 1."
|
|
newline
|
|
bitfld.long 0x4 5. "WB,Write Back Operation Enable" "0: Write Back operation is skipped.,1: Write Back operation is performed."
|
|
bitfld.long 0x4 4. "IE,Interrupt Enable" "0: DMA Done interrupt is generated.,1: DMA Done interrupt is not set."
|
|
newline
|
|
bitfld.long 0x4 1.--2. "DVIEW,Descriptor View" "0: Address {0} Stride {0} are updated,1: Address {0 1} Stride {0 1} are updated,2: Address {0 1 2} Stride {0 1 2} are updated,?"
|
|
bitfld.long 0x4 0. "DE,Descriptor Enable" "0: Descriptor disabled.,1: Descriptor enabled."
|
|
line.long 0x8 "DNDA,DMA Descriptor Address Register"
|
|
hexmask.long 0x8 2.--31. 1. "NDA,Next Descriptor Address Register"
|
|
line.long 0xC "DAD0,DMA Address 0 Register"
|
|
hexmask.long 0xC 0.--31. 1. "AD0,Channel 0 Address"
|
|
line.long 0x10 "DST0,DMA Stride 0 Register"
|
|
hexmask.long 0x10 0.--31. 1. "ST0,Channel 0 Stride"
|
|
line.long 0x14 "DAD1,DMA Address 1 Register"
|
|
hexmask.long 0x14 0.--31. 1. "AD1,Channel 1 Address"
|
|
line.long 0x18 "DST1,DMA Stride 1 Register"
|
|
hexmask.long 0x18 0.--31. 1. "ST1,Channel 1 Stride"
|
|
line.long 0x1C "DAD2,DMA Address 2 Register"
|
|
hexmask.long 0x1C 0.--31. 1. "AD2,Channel 2 Address"
|
|
line.long 0x20 "DST2,DMA Stride 2 Register"
|
|
hexmask.long 0x20 0.--31. 1. "ST2,Channel 2 Stride"
|
|
repeat 512. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x55C)++0x3
|
|
line.long 0x0 "HIS_ENTRY[$1],Histogram Entry x"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "COUNT,Entry Counter"
|
|
repeat.end
|
|
tree.end
|
|
tree "MATRIX (AHB Bus Matrix)"
|
|
base ad:0xE0804000
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "MCFG[$1],Master Configuration Register x"
|
|
bitfld.long 0x0 0.--2. "ULBT,Undefined Length Burst Type" "0: Unlimited Length Burst-No predicted end of burst..,1: Single Access-The undefined length burst is..,2: 4-beat Burst-The undefined length burst or..,3: 8-beat Burst-The undefined length burst or..,4: 16-beat Burst-The undefined length burst or..,5: 32-beat Burst-The undefined length burst or..,6: 64-beat Burst-The undefined length burst or..,7: 128-beat Burst-The undefined length burst or.."
|
|
repeat.end
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x40)++0x3
|
|
line.long 0x0 "SCFG[$1],Slave Configuration Register x"
|
|
hexmask.long.byte 0x0 18.--21. 1. "FIXED_DEFMSTR,Fixed Default Master"
|
|
bitfld.long 0x0 16.--17. "DEFMSTR_TYPE,Default Master Type" "0: No Default Master-At the end of the current..,1: Last Default Master-At the end of the current..,2: Fixed Default Master-At the end of the current..,?"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "SLOT_CYCLE,Maximum Bus Grant Duration for Masters"
|
|
repeat.end
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0xE0804080 ad:0xE0804088 ad:0xE0804090 ad:0xE0804098 ad:0xE08040A0 ad:0xE08040A8 ad:0xE08040B0 ad:0xE08040B8 ad:0xE08040C0 ad:0xE08040C8 ad:0xE08040D0 ad:0xE08040D8 ad:0xE08040E0 ad:0xE08040E8 ad:0xE08040F0 ad:0xE08040F8)
|
|
tree "MATRIX_PR[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "PRAS,Priority Register A for Slave x"
|
|
bitfld.long 0x0 30. "LQOSEN7,Latency Quality of Service Enable for Master 7" "0: Disables propagation of Latency Quality of..,1: Enables the propagation of Latency Quality of.."
|
|
bitfld.long 0x0 28.--29. "M7PR,Master 7 Priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 26. "LQOSEN6,Latency Quality of Service Enable for Master 6" "0: Disables propagation of Latency Quality of..,1: Enables the propagation of Latency Quality of.."
|
|
bitfld.long 0x0 24.--25. "M6PR,Master 6 Priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 22. "LQOSEN5,Latency Quality of Service Enable for Master 5" "0: Disables propagation of Latency Quality of..,1: Enables the propagation of Latency Quality of.."
|
|
bitfld.long 0x0 20.--21. "M5PR,Master 5 Priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 18. "LQOSEN4,Latency Quality of Service Enable for Master 4" "0: Disables propagation of Latency Quality of..,1: Enables the propagation of Latency Quality of.."
|
|
bitfld.long 0x0 16.--17. "M4PR,Master 4 Priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 14. "LQOSEN3,Latency Quality of Service Enable for Master 3" "0: Disables propagation of Latency Quality of..,1: Enables the propagation of Latency Quality of.."
|
|
bitfld.long 0x0 12.--13. "M3PR,Master 3 Priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10. "LQOSEN2,Latency Quality of Service Enable for Master 2" "0: Disables propagation of Latency Quality of..,1: Enables the propagation of Latency Quality of.."
|
|
bitfld.long 0x0 8.--9. "M2PR,Master 2 Priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 6. "LQOSEN1,Latency Quality of Service Enable for Master 1" "0: Disables propagation of Latency Quality of..,1: Enables the propagation of Latency Quality of.."
|
|
bitfld.long 0x0 4.--5. "M1PR,Master 1 Priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 2. "LQOSEN0,Latency Quality of Service Enable for Master 0" "0: Disables propagation of Latency Quality of..,1: Enables the propagation of Latency Quality of.."
|
|
bitfld.long 0x0 0.--1. "M0PR,Master 0 Priority" "0,1,2,3"
|
|
line.long 0x4 "PRBS,Priority Register B for Slave x"
|
|
bitfld.long 0x4 30. "LQOSEN15,Latency Quality of Service Enable for Master 15" "0: Disables propagation of Latency Quality of..,1: Enables the propagation of Latency Quality of.."
|
|
bitfld.long 0x4 28.--29. "M15PR,Master 15 Priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 26. "LQOSEN14,Latency Quality of Service Enable for Master 14" "0: Disables propagation of Latency Quality of..,1: Enables the propagation of Latency Quality of.."
|
|
bitfld.long 0x4 24.--25. "M14PR,Master 14 Priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 22. "LQOSEN13,Latency Quality of Service Enable for Master 13" "0: Disables propagation of Latency Quality of..,1: Enables the propagation of Latency Quality of.."
|
|
bitfld.long 0x4 20.--21. "M13PR,Master 13 Priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 18. "LQOSEN12,Latency Quality of Service Enable for Master 12" "0: Disables propagation of Latency Quality of..,1: Enables the propagation of Latency Quality of.."
|
|
bitfld.long 0x4 16.--17. "M12PR,Master 12 Priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 14. "LQOSEN11,Latency Quality of Service Enable for Master 11" "0: Disables propagation of Latency Quality of..,1: Enables the propagation of Latency Quality of.."
|
|
bitfld.long 0x4 12.--13. "M11PR,Master 11 Priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 10. "LQOSEN10,Latency Quality of Service Enable for Master 10" "0: Disables propagation of Latency Quality of..,1: Enables the propagation of Latency Quality of.."
|
|
bitfld.long 0x4 8.--9. "M10PR,Master 10 Priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 6. "LQOSEN9,Latency Quality of Service Enable for Master 9" "0: Disables propagation of Latency Quality of..,1: Enables the propagation of Latency Quality of.."
|
|
bitfld.long 0x4 4.--5. "M9PR,Master 9 Priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 2. "LQOSEN8,Latency Quality of Service Enable for Master 8" "0: Disables propagation of Latency Quality of..,1: Enables the propagation of Latency Quality of.."
|
|
bitfld.long 0x4 0.--1. "M8PR,Master 8 Priority" "0,1,2,3"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0xE0804000
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "MRCR,Master Remap Control Register"
|
|
bitfld.long 0x0 15. "RCB15,Remap Command Bit for Master 15" "0: Disables remapped address decoding for the..,1: Enables remapped address decoding for the.."
|
|
bitfld.long 0x0 14. "RCB14,Remap Command Bit for Master 14" "0: Disables remapped address decoding for the..,1: Enables remapped address decoding for the.."
|
|
newline
|
|
bitfld.long 0x0 13. "RCB13,Remap Command Bit for Master 13" "0: Disables remapped address decoding for the..,1: Enables remapped address decoding for the.."
|
|
bitfld.long 0x0 12. "RCB12,Remap Command Bit for Master 12" "0: Disables remapped address decoding for the..,1: Enables remapped address decoding for the.."
|
|
newline
|
|
bitfld.long 0x0 11. "RCB11,Remap Command Bit for Master 11" "0: Disables remapped address decoding for the..,1: Enables remapped address decoding for the.."
|
|
bitfld.long 0x0 10. "RCB10,Remap Command Bit for Master 10" "0: Disables remapped address decoding for the..,1: Enables remapped address decoding for the.."
|
|
newline
|
|
bitfld.long 0x0 9. "RCB9,Remap Command Bit for Master 9" "0: Disables remapped address decoding for the..,1: Enables remapped address decoding for the.."
|
|
bitfld.long 0x0 8. "RCB8,Remap Command Bit for Master 8" "0: Disables remapped address decoding for the..,1: Enables remapped address decoding for the.."
|
|
newline
|
|
bitfld.long 0x0 7. "RCB7,Remap Command Bit for Master 7" "0: Disables remapped address decoding for the..,1: Enables remapped address decoding for the.."
|
|
bitfld.long 0x0 6. "RCB6,Remap Command Bit for Master 6" "0: Disables remapped address decoding for the..,1: Enables remapped address decoding for the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RCB5,Remap Command Bit for Master 5" "0: Disables remapped address decoding for the..,1: Enables remapped address decoding for the.."
|
|
bitfld.long 0x0 4. "RCB4,Remap Command Bit for Master 4" "0: Disables remapped address decoding for the..,1: Enables remapped address decoding for the.."
|
|
newline
|
|
bitfld.long 0x0 3. "RCB3,Remap Command Bit for Master 3" "0: Disables remapped address decoding for the..,1: Enables remapped address decoding for the.."
|
|
bitfld.long 0x0 2. "RCB2,Remap Command Bit for Master 2" "0: Disables remapped address decoding for the..,1: Enables remapped address decoding for the.."
|
|
newline
|
|
bitfld.long 0x0 1. "RCB1,Remap Command Bit for Master 1" "0: Disables remapped address decoding for the..,1: Enables remapped address decoding for the.."
|
|
bitfld.long 0x0 0. "RCB0,Remap Command Bit for Master 0" "0: Disables remapped address decoding for the..,1: Enables remapped address decoding for the.."
|
|
wgroup.long 0x150++0x7
|
|
line.long 0x0 "MEIER,Master Error Interrupt Enable Register"
|
|
bitfld.long 0x0 15. "MERR15,Master 15 Access Error" "0: No effect.,1: Enables Master x Access Error interrupt source."
|
|
bitfld.long 0x0 14. "MERR14,Master 14 Access Error" "0: No effect.,1: Enables Master x Access Error interrupt source."
|
|
newline
|
|
bitfld.long 0x0 13. "MERR13,Master 13 Access Error" "0: No effect.,1: Enables Master x Access Error interrupt source."
|
|
bitfld.long 0x0 12. "MERR12,Master 12 Access Error" "0: No effect.,1: Enables Master x Access Error interrupt source."
|
|
newline
|
|
bitfld.long 0x0 11. "MERR11,Master 11 Access Error" "0: No effect.,1: Enables Master x Access Error interrupt source."
|
|
bitfld.long 0x0 10. "MERR10,Master 10 Access Error" "0: No effect.,1: Enables Master x Access Error interrupt source."
|
|
newline
|
|
bitfld.long 0x0 9. "MERR9,Master 9 Access Error" "0: No effect.,1: Enables Master x Access Error interrupt source."
|
|
bitfld.long 0x0 8. "MERR8,Master 8 Access Error" "0: No effect.,1: Enables Master x Access Error interrupt source."
|
|
newline
|
|
bitfld.long 0x0 7. "MERR7,Master 7 Access Error" "0: No effect.,1: Enables Master x Access Error interrupt source."
|
|
bitfld.long 0x0 6. "MERR6,Master 6 Access Error" "0: No effect.,1: Enables Master x Access Error interrupt source."
|
|
newline
|
|
bitfld.long 0x0 5. "MERR5,Master 5 Access Error" "0: No effect.,1: Enables Master x Access Error interrupt source."
|
|
bitfld.long 0x0 4. "MERR4,Master 4 Access Error" "0: No effect.,1: Enables Master x Access Error interrupt source."
|
|
newline
|
|
bitfld.long 0x0 3. "MERR3,Master 3 Access Error" "0: No effect.,1: Enables Master x Access Error interrupt source."
|
|
bitfld.long 0x0 2. "MERR2,Master 2 Access Error" "0: No effect.,1: Enables Master x Access Error interrupt source."
|
|
newline
|
|
bitfld.long 0x0 1. "MERR1,Master 1 Access Error" "0: No effect.,1: Enables Master x Access Error interrupt source."
|
|
bitfld.long 0x0 0. "MERR0,Master 0 Access Error" "0: No effect.,1: Enables Master x Access Error interrupt source."
|
|
line.long 0x4 "MEIDR,Master Error Interrupt Disable Register"
|
|
bitfld.long 0x4 15. "MERR15,Master 15 Access Error" "0: No effect.,1: Disables Master x Access Error interrupt source."
|
|
bitfld.long 0x4 14. "MERR14,Master 14 Access Error" "0: No effect.,1: Disables Master x Access Error interrupt source."
|
|
newline
|
|
bitfld.long 0x4 13. "MERR13,Master 13 Access Error" "0: No effect.,1: Disables Master x Access Error interrupt source."
|
|
bitfld.long 0x4 12. "MERR12,Master 12 Access Error" "0: No effect.,1: Disables Master x Access Error interrupt source."
|
|
newline
|
|
bitfld.long 0x4 11. "MERR11,Master 11 Access Error" "0: No effect.,1: Disables Master x Access Error interrupt source."
|
|
bitfld.long 0x4 10. "MERR10,Master 10 Access Error" "0: No effect.,1: Disables Master x Access Error interrupt source."
|
|
newline
|
|
bitfld.long 0x4 9. "MERR9,Master 9 Access Error" "0: No effect.,1: Disables Master x Access Error interrupt source."
|
|
bitfld.long 0x4 8. "MERR8,Master 8 Access Error" "0: No effect.,1: Disables Master x Access Error interrupt source."
|
|
newline
|
|
bitfld.long 0x4 7. "MERR7,Master 7 Access Error" "0: No effect.,1: Disables Master x Access Error interrupt source."
|
|
bitfld.long 0x4 6. "MERR6,Master 6 Access Error" "0: No effect.,1: Disables Master x Access Error interrupt source."
|
|
newline
|
|
bitfld.long 0x4 5. "MERR5,Master 5 Access Error" "0: No effect.,1: Disables Master x Access Error interrupt source."
|
|
bitfld.long 0x4 4. "MERR4,Master 4 Access Error" "0: No effect.,1: Disables Master x Access Error interrupt source."
|
|
newline
|
|
bitfld.long 0x4 3. "MERR3,Master 3 Access Error" "0: No effect.,1: Disables Master x Access Error interrupt source."
|
|
bitfld.long 0x4 2. "MERR2,Master 2 Access Error" "0: No effect.,1: Disables Master x Access Error interrupt source."
|
|
newline
|
|
bitfld.long 0x4 1. "MERR1,Master 1 Access Error" "0: No effect.,1: Disables Master x Access Error interrupt source."
|
|
bitfld.long 0x4 0. "MERR0,Master 0 Access Error" "0: No effect.,1: Disables Master x Access Error interrupt source."
|
|
rgroup.long 0x158++0x7
|
|
line.long 0x0 "MEIMR,Master Error Interrupt Mask Register"
|
|
bitfld.long 0x0 15. "MERR15,Master 15 Access Error" "0: Master x Access Error does not trigger any..,1: Master x Access Error triggers the MATRIX.."
|
|
bitfld.long 0x0 14. "MERR14,Master 14 Access Error" "0: Master x Access Error does not trigger any..,1: Master x Access Error triggers the MATRIX.."
|
|
newline
|
|
bitfld.long 0x0 13. "MERR13,Master 13 Access Error" "0: Master x Access Error does not trigger any..,1: Master x Access Error triggers the MATRIX.."
|
|
bitfld.long 0x0 12. "MERR12,Master 12 Access Error" "0: Master x Access Error does not trigger any..,1: Master x Access Error triggers the MATRIX.."
|
|
newline
|
|
bitfld.long 0x0 11. "MERR11,Master 11 Access Error" "0: Master x Access Error does not trigger any..,1: Master x Access Error triggers the MATRIX.."
|
|
bitfld.long 0x0 10. "MERR10,Master 10 Access Error" "0: Master x Access Error does not trigger any..,1: Master x Access Error triggers the MATRIX.."
|
|
newline
|
|
bitfld.long 0x0 9. "MERR9,Master 9 Access Error" "0: Master x Access Error does not trigger any..,1: Master x Access Error triggers the MATRIX.."
|
|
bitfld.long 0x0 8. "MERR8,Master 8 Access Error" "0: Master x Access Error does not trigger any..,1: Master x Access Error triggers the MATRIX.."
|
|
newline
|
|
bitfld.long 0x0 7. "MERR7,Master 7 Access Error" "0: Master x Access Error does not trigger any..,1: Master x Access Error triggers the MATRIX.."
|
|
bitfld.long 0x0 6. "MERR6,Master 6 Access Error" "0: Master x Access Error does not trigger any..,1: Master x Access Error triggers the MATRIX.."
|
|
newline
|
|
bitfld.long 0x0 5. "MERR5,Master 5 Access Error" "0: Master x Access Error does not trigger any..,1: Master x Access Error triggers the MATRIX.."
|
|
bitfld.long 0x0 4. "MERR4,Master 4 Access Error" "0: Master x Access Error does not trigger any..,1: Master x Access Error triggers the MATRIX.."
|
|
newline
|
|
bitfld.long 0x0 3. "MERR3,Master 3 Access Error" "0: Master x Access Error does not trigger any..,1: Master x Access Error triggers the MATRIX.."
|
|
bitfld.long 0x0 2. "MERR2,Master 2 Access Error" "0: Master x Access Error does not trigger any..,1: Master x Access Error triggers the MATRIX.."
|
|
newline
|
|
bitfld.long 0x0 1. "MERR1,Master 1 Access Error" "0: Master x Access Error does not trigger any..,1: Master x Access Error triggers the MATRIX.."
|
|
bitfld.long 0x0 0. "MERR0,Master 0 Access Error" "0: Master x Access Error does not trigger any..,1: Master x Access Error triggers the MATRIX.."
|
|
line.long 0x4 "MESR,Master Error Status Register"
|
|
bitfld.long 0x4 15. "MERR15,Master 15 Access Error" "0: No Master Access Error has occurred since the..,1: At least one Master Access Error has occurred.."
|
|
bitfld.long 0x4 14. "MERR14,Master 14 Access Error" "0: No Master Access Error has occurred since the..,1: At least one Master Access Error has occurred.."
|
|
newline
|
|
bitfld.long 0x4 13. "MERR13,Master 13 Access Error" "0: No Master Access Error has occurred since the..,1: At least one Master Access Error has occurred.."
|
|
bitfld.long 0x4 12. "MERR12,Master 12 Access Error" "0: No Master Access Error has occurred since the..,1: At least one Master Access Error has occurred.."
|
|
newline
|
|
bitfld.long 0x4 11. "MERR11,Master 11 Access Error" "0: No Master Access Error has occurred since the..,1: At least one Master Access Error has occurred.."
|
|
bitfld.long 0x4 10. "MERR10,Master 10 Access Error" "0: No Master Access Error has occurred since the..,1: At least one Master Access Error has occurred.."
|
|
newline
|
|
bitfld.long 0x4 9. "MERR9,Master 9 Access Error" "0: No Master Access Error has occurred since the..,1: At least one Master Access Error has occurred.."
|
|
bitfld.long 0x4 8. "MERR8,Master 8 Access Error" "0: No Master Access Error has occurred since the..,1: At least one Master Access Error has occurred.."
|
|
newline
|
|
bitfld.long 0x4 7. "MERR7,Master 7 Access Error" "0: No Master Access Error has occurred since the..,1: At least one Master Access Error has occurred.."
|
|
bitfld.long 0x4 6. "MERR6,Master 6 Access Error" "0: No Master Access Error has occurred since the..,1: At least one Master Access Error has occurred.."
|
|
newline
|
|
bitfld.long 0x4 5. "MERR5,Master 5 Access Error" "0: No Master Access Error has occurred since the..,1: At least one Master Access Error has occurred.."
|
|
bitfld.long 0x4 4. "MERR4,Master 4 Access Error" "0: No Master Access Error has occurred since the..,1: At least one Master Access Error has occurred.."
|
|
newline
|
|
bitfld.long 0x4 3. "MERR3,Master 3 Access Error" "0: No Master Access Error has occurred since the..,1: At least one Master Access Error has occurred.."
|
|
bitfld.long 0x4 2. "MERR2,Master 2 Access Error" "0: No Master Access Error has occurred since the..,1: At least one Master Access Error has occurred.."
|
|
newline
|
|
bitfld.long 0x4 1. "MERR1,Master 1 Access Error" "0: No Master Access Error has occurred since the..,1: At least one Master Access Error has occurred.."
|
|
bitfld.long 0x4 0. "MERR0,Master 0 Access Error" "0: No Master Access Error has occurred since the..,1: At least one Master Access Error has occurred.."
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x160)++0x3
|
|
line.long 0x0 "MEAR[$1],Master x Error Address Register"
|
|
hexmask.long 0x0 0.--31. 1. "ERRADD,Master Error Address"
|
|
repeat.end
|
|
group.long 0x1E4++0x3
|
|
line.long 0x0 "WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 7. "CFGFRZ,Configuration Freeze" "0: The MATRIX configuration is not frozen.,1: Freezes the MATRIX configuration until hardware.."
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
|
|
rgroup.long 0x1E8++0x3
|
|
line.long 0x0 "WPSR,Write Protect Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x200)++0x3
|
|
line.long 0x0 "SSR[$1],Security Slave x Register"
|
|
bitfld.long 0x0 31. "DSSOA7,Downward Security Split Offset Address for HSELx Security Region" "0: For the HSELx slave security region the security..,1: For the HSELx slave security region the security.."
|
|
bitfld.long 0x0 30. "DSSOA6,Downward Security Split Offset Address for HSELx Security Region" "0: For the HSELx slave security region the security..,1: For the HSELx slave security region the security.."
|
|
newline
|
|
bitfld.long 0x0 29. "DSSOA5,Downward Security Split Offset Address for HSELx Security Region" "0: For the HSELx slave security region the security..,1: For the HSELx slave security region the security.."
|
|
bitfld.long 0x0 28. "DSSOA4,Downward Security Split Offset Address for HSELx Security Region" "0: For the HSELx slave security region the security..,1: For the HSELx slave security region the security.."
|
|
newline
|
|
bitfld.long 0x0 27. "DSSOA3,Downward Security Split Offset Address for HSELx Security Region" "0: For the HSELx slave security region the security..,1: For the HSELx slave security region the security.."
|
|
bitfld.long 0x0 26. "DSSOA2,Downward Security Split Offset Address for HSELx Security Region" "0: For the HSELx slave security region the security..,1: For the HSELx slave security region the security.."
|
|
newline
|
|
bitfld.long 0x0 25. "DSSOA1,Downward Security Split Offset Address for HSELx Security Region" "0: For the HSELx slave security region the security..,1: For the HSELx slave security region the security.."
|
|
bitfld.long 0x0 24. "DSSOA0,Downward Security Split Offset Address for HSELx Security Region" "0: For the HSELx slave security region the security..,1: For the HSELx slave security region the security.."
|
|
newline
|
|
bitfld.long 0x0 23. "WRNSECH7,Write Not Secured for HSELx Security Region" "0: The HSELx slave security region is split into..,1: The HSELx slave security region is Not Secured.."
|
|
bitfld.long 0x0 22. "WRNSECH6,Write Not Secured for HSELx Security Region" "0: The HSELx slave security region is split into..,1: The HSELx slave security region is Not Secured.."
|
|
newline
|
|
bitfld.long 0x0 21. "WRNSECH5,Write Not Secured for HSELx Security Region" "0: The HSELx slave security region is split into..,1: The HSELx slave security region is Not Secured.."
|
|
bitfld.long 0x0 20. "WRNSECH4,Write Not Secured for HSELx Security Region" "0: The HSELx slave security region is split into..,1: The HSELx slave security region is Not Secured.."
|
|
newline
|
|
bitfld.long 0x0 19. "WRNSECH3,Write Not Secured for HSELx Security Region" "0: The HSELx slave security region is split into..,1: The HSELx slave security region is Not Secured.."
|
|
bitfld.long 0x0 18. "WRNSECH2,Write Not Secured for HSELx Security Region" "0: The HSELx slave security region is split into..,1: The HSELx slave security region is Not Secured.."
|
|
newline
|
|
bitfld.long 0x0 17. "WRNSECH1,Write Not Secured for HSELx Security Region" "0: The HSELx slave security region is split into..,1: The HSELx slave security region is Not Secured.."
|
|
bitfld.long 0x0 16. "WRNSECH0,Write Not Secured for HSELx Security Region" "0: The HSELx slave security region is split into..,1: The HSELx slave security region is Not Secured.."
|
|
newline
|
|
bitfld.long 0x0 15. "RDNSECH7,Read Not Secured for HSELx Security Region" "0: The HSELx slave security region is split into..,1: The HSELx slave security region is Not Secured.."
|
|
bitfld.long 0x0 14. "RDNSECH6,Read Not Secured for HSELx Security Region" "0: The HSELx slave security region is split into..,1: The HSELx slave security region is Not Secured.."
|
|
newline
|
|
bitfld.long 0x0 13. "RDNSECH5,Read Not Secured for HSELx Security Region" "0: The HSELx slave security region is split into..,1: The HSELx slave security region is Not Secured.."
|
|
bitfld.long 0x0 12. "RDNSECH4,Read Not Secured for HSELx Security Region" "0: The HSELx slave security region is split into..,1: The HSELx slave security region is Not Secured.."
|
|
newline
|
|
bitfld.long 0x0 11. "RDNSECH3,Read Not Secured for HSELx Security Region" "0: The HSELx slave security region is split into..,1: The HSELx slave security region is Not Secured.."
|
|
bitfld.long 0x0 10. "RDNSECH2,Read Not Secured for HSELx Security Region" "0: The HSELx slave security region is split into..,1: The HSELx slave security region is Not Secured.."
|
|
newline
|
|
bitfld.long 0x0 9. "RDNSECH1,Read Not Secured for HSELx Security Region" "0: The HSELx slave security region is split into..,1: The HSELx slave security region is Not Secured.."
|
|
bitfld.long 0x0 8. "RDNSECH0,Read Not Secured for HSELx Security Region" "0: The HSELx slave security region is split into..,1: The HSELx slave security region is Not Secured.."
|
|
newline
|
|
bitfld.long 0x0 7. "LANSECH7,Low Area Not Secured in HSELx Security Region" "0: The security of the HSELx slave area laying..,1: The HSELx slave address area laying below the.."
|
|
bitfld.long 0x0 6. "LANSECH6,Low Area Not Secured in HSELx Security Region" "0: The security of the HSELx slave area laying..,1: The HSELx slave address area laying below the.."
|
|
newline
|
|
bitfld.long 0x0 5. "LANSECH5,Low Area Not Secured in HSELx Security Region" "0: The security of the HSELx slave area laying..,1: The HSELx slave address area laying below the.."
|
|
bitfld.long 0x0 4. "LANSECH4,Low Area Not Secured in HSELx Security Region" "0: The security of the HSELx slave area laying..,1: The HSELx slave address area laying below the.."
|
|
newline
|
|
bitfld.long 0x0 3. "LANSECH3,Low Area Not Secured in HSELx Security Region" "0: The security of the HSELx slave area laying..,1: The HSELx slave address area laying below the.."
|
|
bitfld.long 0x0 2. "LANSECH2,Low Area Not Secured in HSELx Security Region" "0: The security of the HSELx slave area laying..,1: The HSELx slave address area laying below the.."
|
|
newline
|
|
bitfld.long 0x0 1. "LANSECH1,Low Area Not Secured in HSELx Security Region" "0: The security of the HSELx slave area laying..,1: The HSELx slave address area laying below the.."
|
|
bitfld.long 0x0 0. "LANSECH0,Low Area Not Secured in HSELx Security Region" "0: The security of the HSELx slave area laying..,1: The HSELx slave address area laying below the.."
|
|
repeat.end
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x240)++0x3
|
|
line.long 0x0 "SASSR[$1],Security Areas Split Slave x Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "SASPLIT7,Security Areas Split for HSELx Security Region"
|
|
hexmask.long.byte 0x0 24.--27. 1. "SASPLIT6,Security Areas Split for HSELx Security Region"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SASPLIT5,Security Areas Split for HSELx Security Region"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SASPLIT4,Security Areas Split for HSELx Security Region"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "SASPLIT3,Security Areas Split for HSELx Security Region"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SASPLIT2,Security Areas Split for HSELx Security Region"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "SASPLIT1,Security Areas Split for HSELx Security Region"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SASPLIT0,Security Areas Split for HSELx Security Region"
|
|
repeat.end
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x280)++0x3
|
|
line.long 0x0 "SRTSR[$1],Security Region Top Slave x Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "SRTOP7,HSELx Security Region Top"
|
|
hexmask.long.byte 0x0 24.--27. 1. "SRTOP6,HSELx Security Region Top"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SRTOP5,HSELx Security Region Top"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SRTOP4,HSELx Security Region Top"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "SRTOP3,HSELx Security Region Top"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SRTOP2,HSELx Security Region Top"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "SRTOP1,HSELx Security Region Top"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SRTOP0,HSELx Security Region Top"
|
|
repeat.end
|
|
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x2C0)++0x3
|
|
line.long 0x0 "SPSELR[$1],Security Peripheral Select 1 Register"
|
|
bitfld.long 0x0 31. "NSECP31,Not Secured Peripheral" "0: The selected peripheral address space is..,1: The selected peripheral address space is.."
|
|
bitfld.long 0x0 30. "NSECP30,Not Secured Peripheral" "0: The selected peripheral address space is..,1: The selected peripheral address space is.."
|
|
newline
|
|
bitfld.long 0x0 29. "NSECP29,Not Secured Peripheral" "0: The selected peripheral address space is..,1: The selected peripheral address space is.."
|
|
bitfld.long 0x0 28. "NSECP28,Not Secured Peripheral" "0: The selected peripheral address space is..,1: The selected peripheral address space is.."
|
|
newline
|
|
bitfld.long 0x0 27. "NSECP27,Not Secured Peripheral" "0: The selected peripheral address space is..,1: The selected peripheral address space is.."
|
|
bitfld.long 0x0 26. "NSECP26,Not Secured Peripheral" "0: The selected peripheral address space is..,1: The selected peripheral address space is.."
|
|
newline
|
|
bitfld.long 0x0 25. "NSECP25,Not Secured Peripheral" "0: The selected peripheral address space is..,1: The selected peripheral address space is.."
|
|
bitfld.long 0x0 24. "NSECP24,Not Secured Peripheral" "0: The selected peripheral address space is..,1: The selected peripheral address space is.."
|
|
newline
|
|
bitfld.long 0x0 23. "NSECP23,Not Secured Peripheral" "0: The selected peripheral address space is..,1: The selected peripheral address space is.."
|
|
bitfld.long 0x0 22. "NSECP22,Not Secured Peripheral" "0: The selected peripheral address space is..,1: The selected peripheral address space is.."
|
|
newline
|
|
bitfld.long 0x0 21. "NSECP21,Not Secured Peripheral" "0: The selected peripheral address space is..,1: The selected peripheral address space is.."
|
|
bitfld.long 0x0 20. "NSECP20,Not Secured Peripheral" "0: The selected peripheral address space is..,1: The selected peripheral address space is.."
|
|
newline
|
|
bitfld.long 0x0 19. "NSECP19,Not Secured Peripheral" "0: The selected peripheral address space is..,1: The selected peripheral address space is.."
|
|
bitfld.long 0x0 18. "NSECP18,Not Secured Peripheral" "0: The selected peripheral address space is..,1: The selected peripheral address space is.."
|
|
newline
|
|
bitfld.long 0x0 17. "NSECP17,Not Secured Peripheral" "0: The selected peripheral address space is..,1: The selected peripheral address space is.."
|
|
bitfld.long 0x0 16. "NSECP16,Not Secured Peripheral" "0: The selected peripheral address space is..,1: The selected peripheral address space is.."
|
|
newline
|
|
bitfld.long 0x0 15. "NSECP15,Not Secured Peripheral" "0: The selected peripheral address space is..,1: The selected peripheral address space is.."
|
|
bitfld.long 0x0 14. "NSECP14,Not Secured Peripheral" "0: The selected peripheral address space is..,1: The selected peripheral address space is.."
|
|
newline
|
|
bitfld.long 0x0 13. "NSECP13,Not Secured Peripheral" "0: The selected peripheral address space is..,1: The selected peripheral address space is.."
|
|
bitfld.long 0x0 12. "NSECP12,Not Secured Peripheral" "0: The selected peripheral address space is..,1: The selected peripheral address space is.."
|
|
newline
|
|
bitfld.long 0x0 11. "NSECP11,Not Secured Peripheral" "0: The selected peripheral address space is..,1: The selected peripheral address space is.."
|
|
bitfld.long 0x0 10. "NSECP10,Not Secured Peripheral" "0: The selected peripheral address space is..,1: The selected peripheral address space is.."
|
|
newline
|
|
bitfld.long 0x0 9. "NSECP9,Not Secured Peripheral" "0: The selected peripheral address space is..,1: The selected peripheral address space is.."
|
|
bitfld.long 0x0 8. "NSECP8,Not Secured Peripheral" "0: The selected peripheral address space is..,1: The selected peripheral address space is.."
|
|
newline
|
|
bitfld.long 0x0 7. "NSECP7,Not Secured Peripheral" "0: The selected peripheral address space is..,1: The selected peripheral address space is.."
|
|
bitfld.long 0x0 6. "NSECP6,Not Secured Peripheral" "0: The selected peripheral address space is..,1: The selected peripheral address space is.."
|
|
newline
|
|
bitfld.long 0x0 5. "NSECP5,Not Secured Peripheral" "0: The selected peripheral address space is..,1: The selected peripheral address space is.."
|
|
bitfld.long 0x0 4. "NSECP4,Not Secured Peripheral" "0: The selected peripheral address space is..,1: The selected peripheral address space is.."
|
|
newline
|
|
bitfld.long 0x0 3. "NSECP3,Not Secured Peripheral" "0: The selected peripheral address space is..,1: The selected peripheral address space is.."
|
|
bitfld.long 0x0 2. "NSECP2,Not Secured Peripheral" "0: The selected peripheral address space is..,1: The selected peripheral address space is.."
|
|
newline
|
|
bitfld.long 0x0 1. "NSECP1,Not Secured Peripheral" "0: The selected peripheral address space is..,1: The selected peripheral address space is.."
|
|
bitfld.long 0x0 0. "NSECP0,Not Secured Peripheral" "0: The selected peripheral address space is..,1: The selected peripheral address space is.."
|
|
repeat.end
|
|
tree.end
|
|
tree "MCAN (Controller Area Network)"
|
|
base ad:0x0
|
|
tree "MCAN0"
|
|
base ad:0xE0828000
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "ENDN,Endian Register"
|
|
hexmask.long 0x0 0.--31. 1. "ETV,Endianness Test Value"
|
|
group.long 0x8++0x27
|
|
line.long 0x0 "CUST,Customer Register"
|
|
hexmask.long 0x0 0.--31. 1. "CSV,Customer-specific Value"
|
|
line.long 0x4 "DBTP,Data Bit Timing and Prescaler Register"
|
|
bitfld.long 0x4 23. "TDC,Transmitter Delay Compensation" "0: Transmitter Delay Compensation disabled.,1: Transmitter Delay Compensation enabled."
|
|
hexmask.long.byte 0x4 16.--20. 1. "DBRP,Data Bit Rate Prescaler"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--12. 1. "DTSEG1,Data Time Segment Before Sample Point"
|
|
hexmask.long.byte 0x4 4.--7. 1. "DTSEG2,Data Time Segment After Sample Point"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "DSJW,Data (Re) Synchronization Jump Width" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "TEST,Test Register"
|
|
bitfld.long 0x8 7. "RX,Receive Pin (read-only)" "0: The CAN bus is dominant (CANRX = '0').,1: The CAN bus is recessive (CANRX = '1')."
|
|
bitfld.long 0x8 5.--6. "TX,Control of Transmit Pin (read/write)" "0: Reset value CANTX controlled by the CAN Core..,1: Sample Point can be monitored at pin CANTX.,2: Dominant ('0') level at pin CANTX.,3: Recessive ('1') at pin CANTX."
|
|
newline
|
|
bitfld.long 0x8 4. "LBCK,Loop Back Mode (read/write)" "0: Reset value. Loop Back mode is disabled.,1: Loop Back mode is enabled (see Section 6.1.9.."
|
|
line.long 0xC "RWD,RAM Watchdog Register"
|
|
hexmask.long.byte 0xC 8.--15. 1. "WDV,Watchdog Value (read-only)"
|
|
hexmask.long.byte 0xC 0.--7. 1. "WDC,Watchdog Configuration (read/write)"
|
|
line.long 0x10 "CCCR,CC Control Register"
|
|
bitfld.long 0x10 15. "NISO,Non-ISO Operation" "0: CAN FD frame format according to ISO11898-1..,1: CAN FD frame format according to Bosch CAN FD.."
|
|
bitfld.long 0x10 14. "TXP,Transmit Pause (read/write write protection)" "0: Transmit pause disabled.,1: Transmit pause enabled."
|
|
newline
|
|
bitfld.long 0x10 13. "EFBI,Edge Filtering during Bus Integration (read/write write protection)" "0: Edge filtering is disabled.,1: Edge filtering is enabled. Two consecutive.."
|
|
bitfld.long 0x10 12. "PXHD,Protocol Exception Event Handling (read/write write protection)" "0: Protocol exception handling enabled.,1: Protocol exception handling disabled."
|
|
newline
|
|
bitfld.long 0x10 9. "BRSE,Bit Rate Switching Enable (read/write write protection)" "0: Bit rate switching for transmissions disabled.,1: Bit rate switching for transmissions enabled."
|
|
bitfld.long 0x10 8. "FDOE,CAN FD Operation Enable (read/write write protection)" "0: FD operation disabled.,1: FD operation enabled."
|
|
newline
|
|
bitfld.long 0x10 7. "TEST,Test Mode Enable (read/write write protection against '1')" "0: Normal operation MCAN_TEST register holds reset..,1: Test mode write access to MCAN_TEST register.."
|
|
bitfld.long 0x10 6. "DAR,Disable Automatic Retransmission (read/write write protection)" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled."
|
|
newline
|
|
bitfld.long 0x10 5. "MON,Bus Monitoring Mode (read/write write protection against '1')" "0: Bus Monitoring mode is disabled.,1: Bus Monitoring mode is enabled."
|
|
bitfld.long 0x10 4. "CSR,Clock Stop Request (read/write)" "0: No clock stop is requested.,1: Clock stop requested. When clock stop is.."
|
|
newline
|
|
bitfld.long 0x10 3. "CSA,Clock Stop Acknowledge (read-only)" "0: No clock stop acknowledged.,1: MCAN may be set in power down by stopping the.."
|
|
bitfld.long 0x10 2. "ASM,Restricted Operation Mode (read/write write protection against '1')" "0: Normal CAN operation.,1: Restricted Operation mode active."
|
|
newline
|
|
bitfld.long 0x10 1. "CCE,Configuration Change Enable (read/write write protection)" "0: The processor has no write access to the..,1: The processor has write access to the protected.."
|
|
bitfld.long 0x10 0. "INIT,Initialization (read/write)" "0: Normal operation.,1: Initialization is started."
|
|
line.long 0x14 "NBTP,Nominal Bit Timing and Prescaler Register"
|
|
hexmask.long.byte 0x14 25.--31. 1. "NSJW,Nominal (Re) Synchronization Jump Width"
|
|
hexmask.long.word 0x14 16.--24. 1. "NBRP,Nominal Bit Rate Prescaler"
|
|
newline
|
|
hexmask.long.byte 0x14 8.--15. 1. "NTSEG1,Nominal Time Segment Before Sample Point"
|
|
hexmask.long.byte 0x14 0.--6. 1. "NTSEG2,Nominal Time Segment After Sample Point"
|
|
line.long 0x18 "TSCC,Timestamp Counter Configuration Register"
|
|
hexmask.long.byte 0x18 16.--19. 1. "TCP,Timestamp Counter Prescaler"
|
|
bitfld.long 0x18 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter value used,3: Timestamp counter value always 0x0000"
|
|
line.long 0x1C "TSCV,Timestamp Counter Value Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. "TSC,Timestamp Counter (cleared on write)"
|
|
line.long 0x20 "TOCC,Timeout Counter Configuration Register"
|
|
hexmask.long.word 0x20 16.--31. 1. "TOP,Timeout Period"
|
|
bitfld.long 0x20 1.--2. "TOS,Timeout Select" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,2: Timeout controlled by Receive FIFO 0,3: Timeout controlled by Receive FIFO 1"
|
|
newline
|
|
bitfld.long 0x20 0. "ETOC,Enable Timeout Counter" "0: Timeout Counter disabled.,1: Timeout Counter enabled."
|
|
line.long 0x24 "TOCV,Timeout Counter Value Register"
|
|
hexmask.long.word 0x24 0.--15. 1. "TOC,Timeout Counter (cleared on write)"
|
|
rgroup.long 0x40++0x7
|
|
line.long 0x0 "ECR,Error Counter Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging (cleared on read)"
|
|
bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter"
|
|
line.long 0x4 "PSR,Protocol Status Register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value"
|
|
bitfld.long 0x4 14. "PXE,Protocol Exception Event (cleared on read)" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
|
|
newline
|
|
bitfld.long 0x4 13. "RFDF,Received a CAN FD Message (cleared on read)" "0: Since this bit was reset by the CPU no CAN FD..,1: Message in CAN FD format with FDF flag set has.."
|
|
bitfld.long 0x4 12. "RBRS,BRS Flag of Last Received CAN FD Message (cleared on read)" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set."
|
|
newline
|
|
bitfld.long 0x4 11. "RESI,ESI Flag of Last Received CAN FD Message (cleared on read)" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set."
|
|
bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code (set to 111 on read)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The MCAN is not Bus_Off.,1: The MCAN is in Bus_Off state."
|
|
bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
|
|
newline
|
|
bitfld.long 0x4 5. "EP,Error Passive" "0: The MCAN is in the Error_Active state. It..,1: The MCAN is in the Error_Passive state."
|
|
bitfld.long 0x4 3.--4. "ACT,Activity" "0: Node is synchronizing on CAN communication,1: Node is neither receiver nor transmitter,2: Node is operating as receiver,3: Node is operating as transmitter"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "LEC,Last Error Code (set to 111 on read)" "0: No error occurred since LEC has been reset by..,1: More than 5 equal bits in a sequence have..,2: A fixed format part of a received frame has the..,3: The message transmitted by the MCAN was not..,4: During transmission of a message (with the..,5: During transmission of a message (or acknowledge..,6: The CRC check sum of a received message was..,7: Any read access to the Protocol Status Register.."
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "TDCR,Transmit Delay Compensation Register"
|
|
hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset"
|
|
hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter"
|
|
group.long 0x50++0xF
|
|
line.long 0x0 "IR,Interrupt Register"
|
|
bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0: No access to reserved address occurred,1: Access to reserved address occurred"
|
|
bitfld.long 0x0 28. "PED,Protocol Error in Data Phase" "0: No protocol error in data phase,1: Protocol error in data phase detected.."
|
|
newline
|
|
bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.."
|
|
bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred.,1: Message RAM Watchdog event due to missing READY."
|
|
newline
|
|
bitfld.long 0x0 25. "BO,Bus_Off Status" "0: Bus_Off status unchanged.,1: Bus_Off status changed."
|
|
bitfld.long 0x0 24. "EW,Warning Status" "0: Error_Warning status unchanged.,1: Error_Warning status changed."
|
|
newline
|
|
bitfld.long 0x0 23. "EP,Error Passive" "0: Error_Passive status unchanged.,1: Error_Passive status changed."
|
|
bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0: CAN Error Logging Counter did not overflow.,1: Overflow of CAN Error Logging Counter occurred."
|
|
newline
|
|
bitfld.long 0x0 19. "DRX,Message stored to Dedicated Receive Buffer" "0: No Receive Buffer updated.,1: At least one received message stored into a.."
|
|
bitfld.long 0x0 18. "TOO,Timeout Occurred" "0: No timeout.,1: Timeout reached."
|
|
newline
|
|
bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0: No Message RAM access failure occurred.,1: Message RAM access failure occurred."
|
|
bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around.,1: Timestamp counter wrapped around."
|
|
newline
|
|
bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost.,1: Tx Event FIFO element lost also set after write.."
|
|
bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0: Tx Event FIFO not full.,1: Tx Event FIFO full."
|
|
newline
|
|
bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO fill level below watermark.,1: Tx Event FIFO fill level reached watermark."
|
|
bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0: Tx Event FIFO unchanged.,1: Tx Handler wrote Tx Event FIFO element."
|
|
newline
|
|
bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty.,1: Tx FIFO empty."
|
|
bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished.,1: Transmission cancellation finished."
|
|
newline
|
|
bitfld.long 0x0 9. "TC,Transmission Completed" "0: No transmission completed.,1: Transmission completed."
|
|
bitfld.long 0x0 8. "HPM,High Priority Message" "0: No high priority message received.,1: High priority message received."
|
|
newline
|
|
bitfld.long 0x0 7. "RF1L,Receive FIFO 1 Message Lost" "0: No Receive FIFO 1 message lost.,1: Receive FIFO 1 message lost also set after write.."
|
|
bitfld.long 0x0 6. "RF1F,Receive FIFO 1 Full" "0: Receive FIFO 1 not full.,1: Receive FIFO 1 full."
|
|
newline
|
|
bitfld.long 0x0 5. "RF1W,Receive FIFO 1 Watermark Reached" "0: Receive FIFO 1 fill level below watermark.,1: Receive FIFO 1 fill level reached watermark."
|
|
bitfld.long 0x0 4. "RF1N,Receive FIFO 1 New Message" "0: No new message written to Receive FIFO 1.,1: New message written to Receive FIFO 1."
|
|
newline
|
|
bitfld.long 0x0 3. "RF0L,Receive FIFO 0 Message Lost" "0: No Receive FIFO 0 message lost.,1: Receive FIFO 0 message lost also set after write.."
|
|
bitfld.long 0x0 2. "RF0F,Receive FIFO 0 Full" "0: Receive FIFO 0 not full.,1: Receive FIFO 0 full."
|
|
newline
|
|
bitfld.long 0x0 1. "RF0W,Receive FIFO 0 Watermark Reached" "0: Receive FIFO 0 fill level below watermark.,1: Receive FIFO 0 fill level reached watermark."
|
|
bitfld.long 0x0 0. "RF0N,Receive FIFO 0 New Message" "0: No new message written to Receive FIFO 0.,1: New message written to Receive FIFO 0."
|
|
line.long 0x4 "IE,Interrupt Enable Register"
|
|
bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0,1"
|
|
bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0,1"
|
|
bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Receive Buffer Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RF1LE,Receive FIFO 1 Message Lost Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 6. "RF1FE,Receive FIFO 1 Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RF1WE,Receive FIFO 1 Watermark Reached Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 4. "RF1NE,Receive FIFO 1 New Message Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RF0LE,Receive FIFO 0 Message Lost Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 2. "RF0FE,Receive FIFO 0 Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RF0WE,Receive FIFO 0 Watermark Reached Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 0. "RF0NE,Receive FIFO 0 New Message Interrupt Enable" "0,1"
|
|
line.long 0x8 "ILS,Interrupt Line Select Register"
|
|
bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0,1"
|
|
bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0,1"
|
|
bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0,1"
|
|
bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0,1"
|
|
bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Receive Buffer Interrupt Line" "0,1"
|
|
bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1"
|
|
bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1"
|
|
bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0,1"
|
|
bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "RF1LL,Receive FIFO 1 Message Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 6. "RF1FL,Receive FIFO 1 Full Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "RF1WL,Receive FIFO 1 Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 4. "RF1NL,Receive FIFO 1 New Message Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "RF0LL,Receive FIFO 0 Message Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 2. "RF0FL,Receive FIFO 0 Full Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "RF0WL,Receive FIFO 0 Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 0. "RF0NL,Receive FIFO 0 New Message Interrupt Line" "0,1"
|
|
line.long 0xC "ILE,Interrupt Line Enable Register"
|
|
bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line MCAN_INT1 disabled.,1: Interrupt line MCAN_INT1 enabled."
|
|
bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line MCAN_INT0 disabled.,1: Interrupt line MCAN_INT0 enabled."
|
|
group.long 0x80++0xB
|
|
line.long 0x0 "GFC,Global Filter Configuration Register"
|
|
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
|
|
bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
|
|
newline
|
|
bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs.,1: Reject all remote frames with 11-bit standard IDs."
|
|
bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs.,1: Reject all remote frames with 29-bit extended IDs."
|
|
line.long 0x4 "SIDFC,Standard ID Filter Configuration Register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard"
|
|
hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address"
|
|
line.long 0x8 "XIDFC,Extended ID Filter Configuration Register"
|
|
hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended"
|
|
hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address"
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "XIDAM,Extended ID AND Mask Register"
|
|
hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask"
|
|
rgroup.long 0x94++0x3
|
|
line.long 0x0 "HPMS,High Priority Message Status Register"
|
|
bitfld.long 0x0 15. "FLST,Filter List" "0: Standard filter list,1: Extended filter list"
|
|
hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected.,1: FIFO message lost.,2: Message stored in FIFO 0.,3: Message stored in FIFO 1."
|
|
hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index"
|
|
group.long 0x98++0xB
|
|
line.long 0x0 "NDAT1,New Data 1 Register"
|
|
bitfld.long 0x0 31. "ND31,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 30. "ND30,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 29. "ND29,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 28. "ND28,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 27. "ND27,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 26. "ND26,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 25. "ND25,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 24. "ND24,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 23. "ND23,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 22. "ND22,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 21. "ND21,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 20. "ND20,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 19. "ND19,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 18. "ND18,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 17. "ND17,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 16. "ND16,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 15. "ND15,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 14. "ND14,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 13. "ND13,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 12. "ND12,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 11. "ND11,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 10. "ND10,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 9. "ND9,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 8. "ND8,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 7. "ND7,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 6. "ND6,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 5. "ND5,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 4. "ND4,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 3. "ND3,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 2. "ND2,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 1. "ND1,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 0. "ND0,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
line.long 0x4 "NDAT2,New Data 2 Register"
|
|
bitfld.long 0x4 31. "ND63,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 30. "ND62,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 29. "ND61,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 28. "ND60,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 27. "ND59,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 26. "ND58,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 25. "ND57,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 24. "ND56,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 23. "ND55,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 22. "ND54,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 21. "ND53,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 20. "ND52,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 19. "ND51,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 18. "ND50,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 17. "ND49,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 16. "ND48,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 15. "ND47,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 14. "ND46,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 13. "ND45,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 12. "ND44,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 11. "ND43,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 10. "ND42,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 9. "ND41,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 8. "ND40,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 7. "ND39,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 6. "ND38,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 5. "ND37,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 4. "ND36,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 3. "ND35,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 2. "ND34,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 1. "ND33,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 0. "ND32,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
line.long 0x8 "RXF0C,Receive FIFO 0 Configuration Register"
|
|
bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0: FIFO 0 Blocking mode.,1: FIFO 0 Overwrite mode."
|
|
hexmask.long.byte 0x8 24.--30. 1. "F0WM,Receive FIFO 0 Watermark"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "F0S,Receive FIFO 0 Size"
|
|
hexmask.long.word 0x8 2.--15. 1. "F0SA,Receive FIFO 0 Start Address"
|
|
rgroup.long 0xA4++0x3
|
|
line.long 0x0 "RXF0S,Receive FIFO 0 Status Register"
|
|
bitfld.long 0x0 25. "RF0L,Receive FIFO 0 Message Lost" "0: No Receive FIFO 0 message lost,1: Receive FIFO 0 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F0F,Receive FIFO 0 Full" "0: Receive FIFO 0 not full.,1: Receive FIFO 0 full."
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "F0PI,Receive FIFO 0 Put Index"
|
|
hexmask.long.byte 0x0 8.--13. 1. "F0GI,Receive FIFO 0 Get Index"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "F0FL,Receive FIFO 0 Fill Level"
|
|
group.long 0xA8++0xB
|
|
line.long 0x0 "RXF0A,Receive FIFO 0 Acknowledge Register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F0AI,Receive FIFO 0 Acknowledge Index"
|
|
line.long 0x4 "RXBC,Receive Rx Buffer Configuration Register"
|
|
hexmask.long.word 0x4 2.--15. 1. "RBSA,Receive Buffer Start Address"
|
|
line.long 0x8 "RXF1C,Receive FIFO 1 Configuration Register"
|
|
bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0: FIFO 1 Blocking mode.,1: FIFO 1 Overwrite mode."
|
|
hexmask.long.byte 0x8 24.--30. 1. "F1WM,Receive FIFO 1 Watermark"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "F1S,Receive FIFO 1 Size"
|
|
hexmask.long.word 0x8 2.--15. 1. "F1SA,Receive FIFO 1 Start Address"
|
|
rgroup.long 0xB4++0x3
|
|
line.long 0x0 "RXF1S,Receive FIFO 1 Status Register"
|
|
bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0: Idle state wait for reception of debug messages..,1: Debug message A received.,2: Debug messages A B received.,3: Debug messages A B C received DMA request is set."
|
|
bitfld.long 0x0 25. "RF1L,Receive FIFO 1 Message Lost" "0: No Receive FIFO 1 message lost.,1: Receive FIFO 1 message lost also set after write.."
|
|
newline
|
|
bitfld.long 0x0 24. "F1F,Receive FIFO 1 Full" "0: Receive FIFO 1 not full.,1: Receive FIFO 1 full."
|
|
hexmask.long.byte 0x0 16.--21. 1. "F1PI,Receive FIFO 1 Put Index"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "F1GI,Receive FIFO 1 Get Index"
|
|
hexmask.long.byte 0x0 0.--6. 1. "F1FL,Receive FIFO 1 Fill Level"
|
|
group.long 0xB8++0xB
|
|
line.long 0x0 "RXF1A,Receive FIFO 1 Acknowledge Register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Receive FIFO 1 Acknowledge Index"
|
|
line.long 0x4 "RXESC,Receive Buffer / FIFO Element Size Configuration Register"
|
|
bitfld.long 0x4 8.--10. "RBDS,Receive Buffer Data Field Size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field"
|
|
bitfld.long 0x4 4.--6. "F1DS,Receive FIFO 1 Data Field Size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "F0DS,Receive FIFO 0 Data Field Size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field"
|
|
line.long 0x8 "TXBC,Transmit Buffer Configuration Register"
|
|
bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation.,1: Tx Queue operation."
|
|
hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers"
|
|
hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address"
|
|
rgroup.long 0xC4++0x3
|
|
line.long 0x0 "TXFQS,Transmit FIFO/Queue Status Register"
|
|
bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full.,1: Tx FIFO/Queue full."
|
|
hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index"
|
|
hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level"
|
|
group.long 0xC8++0x3
|
|
line.long 0x0 "TXESC,Transmit Buffer Element Size Configuration Register"
|
|
bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48- byte data field,7: 64-byte data field"
|
|
rgroup.long 0xCC++0x3
|
|
line.long 0x0 "TXBRP,Transmit Buffer Request Pending Register"
|
|
bitfld.long 0x0 31. "TRP31,Transmission Request Pending for Buffer 31" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 30. "TRP30,Transmission Request Pending for Buffer 30" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 29. "TRP29,Transmission Request Pending for Buffer 29" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 28. "TRP28,Transmission Request Pending for Buffer 28" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 27. "TRP27,Transmission Request Pending for Buffer 27" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 26. "TRP26,Transmission Request Pending for Buffer 26" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 25. "TRP25,Transmission Request Pending for Buffer 25" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 24. "TRP24,Transmission Request Pending for Buffer 24" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 23. "TRP23,Transmission Request Pending for Buffer 23" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 22. "TRP22,Transmission Request Pending for Buffer 22" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 21. "TRP21,Transmission Request Pending for Buffer 21" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 20. "TRP20,Transmission Request Pending for Buffer 20" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 19. "TRP19,Transmission Request Pending for Buffer 19" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 18. "TRP18,Transmission Request Pending for Buffer 18" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 17. "TRP17,Transmission Request Pending for Buffer 17" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 16. "TRP16,Transmission Request Pending for Buffer 16" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 15. "TRP15,Transmission Request Pending for Buffer 15" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 14. "TRP14,Transmission Request Pending for Buffer 14" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 13. "TRP13,Transmission Request Pending for Buffer 13" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 12. "TRP12,Transmission Request Pending for Buffer 12" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 11. "TRP11,Transmission Request Pending for Buffer 11" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 10. "TRP10,Transmission Request Pending for Buffer 10" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 9. "TRP9,Transmission Request Pending for Buffer 9" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 8. "TRP8,Transmission Request Pending for Buffer 8" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 7. "TRP7,Transmission Request Pending for Buffer 7" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 6. "TRP6,Transmission Request Pending for Buffer 6" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 5. "TRP5,Transmission Request Pending for Buffer 5" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 4. "TRP4,Transmission Request Pending for Buffer 4" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 3. "TRP3,Transmission Request Pending for Buffer 3" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 2. "TRP2,Transmission Request Pending for Buffer 2" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 1. "TRP1,Transmission Request Pending for Buffer 1" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 0. "TRP0,Transmission Request Pending for Buffer 0" "0: No transmission request pending,1: Transmission request pending"
|
|
group.long 0xD0++0x7
|
|
line.long 0x0 "TXBAR,Transmit Buffer Add Request Register"
|
|
bitfld.long 0x0 31. "AR31,Add Request for Transmit Buffer 31" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 30. "AR30,Add Request for Transmit Buffer 30" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 29. "AR29,Add Request for Transmit Buffer 29" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 28. "AR28,Add Request for Transmit Buffer 28" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 27. "AR27,Add Request for Transmit Buffer 27" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 26. "AR26,Add Request for Transmit Buffer 26" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 25. "AR25,Add Request for Transmit Buffer 25" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 24. "AR24,Add Request for Transmit Buffer 24" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 23. "AR23,Add Request for Transmit Buffer 23" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 22. "AR22,Add Request for Transmit Buffer 22" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 21. "AR21,Add Request for Transmit Buffer 21" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 20. "AR20,Add Request for Transmit Buffer 20" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 19. "AR19,Add Request for Transmit Buffer 19" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 18. "AR18,Add Request for Transmit Buffer 18" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 17. "AR17,Add Request for Transmit Buffer 17" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 16. "AR16,Add Request for Transmit Buffer 16" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 15. "AR15,Add Request for Transmit Buffer 15" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 14. "AR14,Add Request for Transmit Buffer 14" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 13. "AR13,Add Request for Transmit Buffer 13" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 12. "AR12,Add Request for Transmit Buffer 12" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 11. "AR11,Add Request for Transmit Buffer 11" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 10. "AR10,Add Request for Transmit Buffer 10" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 9. "AR9,Add Request for Transmit Buffer 9" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 8. "AR8,Add Request for Transmit Buffer 8" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 7. "AR7,Add Request for Transmit Buffer 7" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 6. "AR6,Add Request for Transmit Buffer 6" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 5. "AR5,Add Request for Transmit Buffer 5" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 4. "AR4,Add Request for Transmit Buffer 4" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 3. "AR3,Add Request for Transmit Buffer 3" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 2. "AR2,Add Request for Transmit Buffer 2" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 1. "AR1,Add Request for Transmit Buffer 1" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 0. "AR0,Add Request for Transmit Buffer 0" "0: No transmission request added.,1: Transmission requested added."
|
|
line.long 0x4 "TXBCR,Transmit Buffer Cancellation Request Register"
|
|
bitfld.long 0x4 31. "CR31,Cancellation Request for Transmit Buffer 31" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 30. "CR30,Cancellation Request for Transmit Buffer 30" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 29. "CR29,Cancellation Request for Transmit Buffer 29" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 28. "CR28,Cancellation Request for Transmit Buffer 28" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 27. "CR27,Cancellation Request for Transmit Buffer 27" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 26. "CR26,Cancellation Request for Transmit Buffer 26" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 25. "CR25,Cancellation Request for Transmit Buffer 25" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 24. "CR24,Cancellation Request for Transmit Buffer 24" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 23. "CR23,Cancellation Request for Transmit Buffer 23" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 22. "CR22,Cancellation Request for Transmit Buffer 22" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 21. "CR21,Cancellation Request for Transmit Buffer 21" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 20. "CR20,Cancellation Request for Transmit Buffer 20" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 19. "CR19,Cancellation Request for Transmit Buffer 19" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 18. "CR18,Cancellation Request for Transmit Buffer 18" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 17. "CR17,Cancellation Request for Transmit Buffer 17" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 16. "CR16,Cancellation Request for Transmit Buffer 16" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 15. "CR15,Cancellation Request for Transmit Buffer 15" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 14. "CR14,Cancellation Request for Transmit Buffer 14" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 13. "CR13,Cancellation Request for Transmit Buffer 13" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 12. "CR12,Cancellation Request for Transmit Buffer 12" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 11. "CR11,Cancellation Request for Transmit Buffer 11" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 10. "CR10,Cancellation Request for Transmit Buffer 10" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 9. "CR9,Cancellation Request for Transmit Buffer 9" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 8. "CR8,Cancellation Request for Transmit Buffer 8" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 7. "CR7,Cancellation Request for Transmit Buffer 7" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 6. "CR6,Cancellation Request for Transmit Buffer 6" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 5. "CR5,Cancellation Request for Transmit Buffer 5" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 4. "CR4,Cancellation Request for Transmit Buffer 4" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 3. "CR3,Cancellation Request for Transmit Buffer 3" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 2. "CR2,Cancellation Request for Transmit Buffer 2" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 1. "CR1,Cancellation Request for Transmit Buffer 1" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 0. "CR0,Cancellation Request for Transmit Buffer 0" "0: No cancellation pending.,1: Cancellation pending."
|
|
rgroup.long 0xD8++0x7
|
|
line.long 0x0 "TXBTO,Transmit Buffer Transmission Occurred Register"
|
|
bitfld.long 0x0 31. "TO31,Transmission Occurred for Buffer 31" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 30. "TO30,Transmission Occurred for Buffer 30" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 29. "TO29,Transmission Occurred for Buffer 29" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 28. "TO28,Transmission Occurred for Buffer 28" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 27. "TO27,Transmission Occurred for Buffer 27" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 26. "TO26,Transmission Occurred for Buffer 26" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 25. "TO25,Transmission Occurred for Buffer 25" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 24. "TO24,Transmission Occurred for Buffer 24" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 23. "TO23,Transmission Occurred for Buffer 23" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 22. "TO22,Transmission Occurred for Buffer 22" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 21. "TO21,Transmission Occurred for Buffer 21" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 20. "TO20,Transmission Occurred for Buffer 20" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 19. "TO19,Transmission Occurred for Buffer 19" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 18. "TO18,Transmission Occurred for Buffer 18" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 17. "TO17,Transmission Occurred for Buffer 17" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 16. "TO16,Transmission Occurred for Buffer 16" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 15. "TO15,Transmission Occurred for Buffer 15" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 14. "TO14,Transmission Occurred for Buffer 14" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 13. "TO13,Transmission Occurred for Buffer 13" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 12. "TO12,Transmission Occurred for Buffer 12" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 11. "TO11,Transmission Occurred for Buffer 11" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 10. "TO10,Transmission Occurred for Buffer 10" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 9. "TO9,Transmission Occurred for Buffer 9" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 8. "TO8,Transmission Occurred for Buffer 8" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 7. "TO7,Transmission Occurred for Buffer 7" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 6. "TO6,Transmission Occurred for Buffer 6" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 5. "TO5,Transmission Occurred for Buffer 5" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 4. "TO4,Transmission Occurred for Buffer 4" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 3. "TO3,Transmission Occurred for Buffer 3" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 2. "TO2,Transmission Occurred for Buffer 2" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 1. "TO1,Transmission Occurred for Buffer 1" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 0. "TO0,Transmission Occurred for Buffer 0" "0: No transmission occurred.,1: Transmission occurred."
|
|
line.long 0x4 "TXBCF,Transmit Buffer Cancellation Finished Register"
|
|
bitfld.long 0x4 31. "CF31,Cancellation Finished for Transmit Buffer 31" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 30. "CF30,Cancellation Finished for Transmit Buffer 30" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 29. "CF29,Cancellation Finished for Transmit Buffer 29" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 28. "CF28,Cancellation Finished for Transmit Buffer 28" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 27. "CF27,Cancellation Finished for Transmit Buffer 27" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 26. "CF26,Cancellation Finished for Transmit Buffer 26" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 25. "CF25,Cancellation Finished for Transmit Buffer 25" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 24. "CF24,Cancellation Finished for Transmit Buffer 24" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 23. "CF23,Cancellation Finished for Transmit Buffer 23" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 22. "CF22,Cancellation Finished for Transmit Buffer 22" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 21. "CF21,Cancellation Finished for Transmit Buffer 21" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 20. "CF20,Cancellation Finished for Transmit Buffer 20" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 19. "CF19,Cancellation Finished for Transmit Buffer 19" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 18. "CF18,Cancellation Finished for Transmit Buffer 18" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 17. "CF17,Cancellation Finished for Transmit Buffer 17" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 16. "CF16,Cancellation Finished for Transmit Buffer 16" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 15. "CF15,Cancellation Finished for Transmit Buffer 15" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 14. "CF14,Cancellation Finished for Transmit Buffer 14" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 13. "CF13,Cancellation Finished for Transmit Buffer 13" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 12. "CF12,Cancellation Finished for Transmit Buffer 12" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 11. "CF11,Cancellation Finished for Transmit Buffer 11" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 10. "CF10,Cancellation Finished for Transmit Buffer 10" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 9. "CF9,Cancellation Finished for Transmit Buffer 9" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 8. "CF8,Cancellation Finished for Transmit Buffer 8" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 7. "CF7,Cancellation Finished for Transmit Buffer 7" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 6. "CF6,Cancellation Finished for Transmit Buffer 6" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
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bitfld.long 0x4 5. "CF5,Cancellation Finished for Transmit Buffer 5" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 4. "CF4,Cancellation Finished for Transmit Buffer 4" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
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bitfld.long 0x4 3. "CF3,Cancellation Finished for Transmit Buffer 3" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 2. "CF2,Cancellation Finished for Transmit Buffer 2" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
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bitfld.long 0x4 1. "CF1,Cancellation Finished for Transmit Buffer 1" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 0. "CF0,Cancellation Finished for Transmit Buffer 0" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
group.long 0xE0++0x7
|
|
line.long 0x0 "TXBTIE,Transmit Buffer Transmission Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable for Buffer 31" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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|
bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable for Buffer 30" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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|
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bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable for Buffer 29" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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|
bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable for Buffer 28" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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|
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bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable for Buffer 27" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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|
bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable for Buffer 26" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable for Buffer 25" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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|
bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable for Buffer 24" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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|
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bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable for Buffer 23" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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|
bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable for Buffer 22" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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|
newline
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bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable for Buffer 21" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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|
bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable for Buffer 20" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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|
newline
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bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable for Buffer 19" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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|
bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable for Buffer 18" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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|
newline
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bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable for Buffer 17" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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|
bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable for Buffer 16" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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|
newline
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bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable for Buffer 15" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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|
bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable for Buffer 14" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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|
newline
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bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable for Buffer 13" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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|
bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable for Buffer 12" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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|
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bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable for Buffer 11" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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|
bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable for Buffer 10" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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newline
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bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable for Buffer 9" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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|
bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable for Buffer 8" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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|
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bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable for Buffer 7" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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|
bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable for Buffer 6" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable for Buffer 5" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable for Buffer 4" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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|
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bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable for Buffer 3" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable for Buffer 2" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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|
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bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable for Buffer 1" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable for Buffer 0" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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|
line.long 0x4 "TXBCIE,Transmit Buffer Cancellation Finished Interrupt Enable Register"
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bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable for Transmit Buffer 31" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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|
bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable for Transmit Buffer 30" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable for Transmit Buffer 29" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable for Transmit Buffer 28" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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|
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bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable for Transmit Buffer 27" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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|
bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable for Transmit Buffer 26" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable for Transmit Buffer 25" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable for Transmit Buffer 24" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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|
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bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable for Transmit Buffer 23" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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|
bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable for Transmit Buffer 22" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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|
newline
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bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable for Transmit Buffer 21" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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|
bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable for Transmit Buffer 20" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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|
newline
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bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable for Transmit Buffer 19" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable for Transmit Buffer 18" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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newline
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bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable for Transmit Buffer 17" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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|
bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable for Transmit Buffer 16" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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|
newline
|
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bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable for Transmit Buffer 15" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable for Transmit Buffer 14" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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|
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bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable for Transmit Buffer 13" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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|
bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable for Transmit Buffer 12" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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|
newline
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bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable for Transmit Buffer 11" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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|
bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable for Transmit Buffer 10" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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|
newline
|
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bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable for Transmit Buffer 9" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable for Transmit Buffer 8" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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|
newline
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bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable for Transmit Buffer 7" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable for Transmit Buffer 6" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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newline
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bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable for Transmit Buffer 5" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable for Transmit Buffer 4" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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newline
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bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable for Transmit Buffer 3" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable for Transmit Buffer 2" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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newline
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bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable for Transmit Buffer 1" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable for Transmit Buffer 0" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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group.long 0xF0++0x3
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line.long 0x0 "TXEFC,Transmit Event FIFO Configuration Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark"
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|
hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size"
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newline
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hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address"
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|
rgroup.long 0xF4++0x3
|
|
line.long 0x0 "TXEFS,Transmit Event FIFO Status Register"
|
|
bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.."
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|
bitfld.long 0x0 24. "EFF,Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full"
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newline
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hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index"
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|
hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index"
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|
newline
|
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hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level"
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|
group.long 0xF8++0x3
|
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line.long 0x0 "TXEFA,Transmit Event FIFO Acknowledge Register"
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hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index"
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tree.end
|
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tree "MCAN1"
|
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base ad:0xE082C000
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rgroup.long 0x4++0x3
|
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line.long 0x0 "ENDN,Endian Register"
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hexmask.long 0x0 0.--31. 1. "ETV,Endianness Test Value"
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group.long 0x8++0x27
|
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line.long 0x0 "CUST,Customer Register"
|
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hexmask.long 0x0 0.--31. 1. "CSV,Customer-specific Value"
|
|
line.long 0x4 "DBTP,Data Bit Timing and Prescaler Register"
|
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bitfld.long 0x4 23. "TDC,Transmitter Delay Compensation" "0: Transmitter Delay Compensation disabled.,1: Transmitter Delay Compensation enabled."
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|
hexmask.long.byte 0x4 16.--20. 1. "DBRP,Data Bit Rate Prescaler"
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|
newline
|
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hexmask.long.byte 0x4 8.--12. 1. "DTSEG1,Data Time Segment Before Sample Point"
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hexmask.long.byte 0x4 4.--7. 1. "DTSEG2,Data Time Segment After Sample Point"
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newline
|
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bitfld.long 0x4 0.--2. "DSJW,Data (Re) Synchronization Jump Width" "0,1,2,3,4,5,6,7"
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line.long 0x8 "TEST,Test Register"
|
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bitfld.long 0x8 7. "RX,Receive Pin (read-only)" "0: The CAN bus is dominant (CANRX = '0').,1: The CAN bus is recessive (CANRX = '1')."
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bitfld.long 0x8 5.--6. "TX,Control of Transmit Pin (read/write)" "0: Reset value CANTX controlled by the CAN Core..,1: Sample Point can be monitored at pin CANTX.,2: Dominant ('0') level at pin CANTX.,3: Recessive ('1') at pin CANTX."
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newline
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bitfld.long 0x8 4. "LBCK,Loop Back Mode (read/write)" "0: Reset value. Loop Back mode is disabled.,1: Loop Back mode is enabled (see Section 6.1.9.."
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line.long 0xC "RWD,RAM Watchdog Register"
|
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hexmask.long.byte 0xC 8.--15. 1. "WDV,Watchdog Value (read-only)"
|
|
hexmask.long.byte 0xC 0.--7. 1. "WDC,Watchdog Configuration (read/write)"
|
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line.long 0x10 "CCCR,CC Control Register"
|
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bitfld.long 0x10 15. "NISO,Non-ISO Operation" "0: CAN FD frame format according to ISO11898-1..,1: CAN FD frame format according to Bosch CAN FD.."
|
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bitfld.long 0x10 14. "TXP,Transmit Pause (read/write write protection)" "0: Transmit pause disabled.,1: Transmit pause enabled."
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|
newline
|
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bitfld.long 0x10 13. "EFBI,Edge Filtering during Bus Integration (read/write write protection)" "0: Edge filtering is disabled.,1: Edge filtering is enabled. Two consecutive.."
|
|
bitfld.long 0x10 12. "PXHD,Protocol Exception Event Handling (read/write write protection)" "0: Protocol exception handling enabled.,1: Protocol exception handling disabled."
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|
newline
|
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bitfld.long 0x10 9. "BRSE,Bit Rate Switching Enable (read/write write protection)" "0: Bit rate switching for transmissions disabled.,1: Bit rate switching for transmissions enabled."
|
|
bitfld.long 0x10 8. "FDOE,CAN FD Operation Enable (read/write write protection)" "0: FD operation disabled.,1: FD operation enabled."
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newline
|
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bitfld.long 0x10 7. "TEST,Test Mode Enable (read/write write protection against '1')" "0: Normal operation MCAN_TEST register holds reset..,1: Test mode write access to MCAN_TEST register.."
|
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bitfld.long 0x10 6. "DAR,Disable Automatic Retransmission (read/write write protection)" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled."
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|
newline
|
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bitfld.long 0x10 5. "MON,Bus Monitoring Mode (read/write write protection against '1')" "0: Bus Monitoring mode is disabled.,1: Bus Monitoring mode is enabled."
|
|
bitfld.long 0x10 4. "CSR,Clock Stop Request (read/write)" "0: No clock stop is requested.,1: Clock stop requested. When clock stop is.."
|
|
newline
|
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bitfld.long 0x10 3. "CSA,Clock Stop Acknowledge (read-only)" "0: No clock stop acknowledged.,1: MCAN may be set in power down by stopping the.."
|
|
bitfld.long 0x10 2. "ASM,Restricted Operation Mode (read/write write protection against '1')" "0: Normal CAN operation.,1: Restricted Operation mode active."
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newline
|
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bitfld.long 0x10 1. "CCE,Configuration Change Enable (read/write write protection)" "0: The processor has no write access to the..,1: The processor has write access to the protected.."
|
|
bitfld.long 0x10 0. "INIT,Initialization (read/write)" "0: Normal operation.,1: Initialization is started."
|
|
line.long 0x14 "NBTP,Nominal Bit Timing and Prescaler Register"
|
|
hexmask.long.byte 0x14 25.--31. 1. "NSJW,Nominal (Re) Synchronization Jump Width"
|
|
hexmask.long.word 0x14 16.--24. 1. "NBRP,Nominal Bit Rate Prescaler"
|
|
newline
|
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hexmask.long.byte 0x14 8.--15. 1. "NTSEG1,Nominal Time Segment Before Sample Point"
|
|
hexmask.long.byte 0x14 0.--6. 1. "NTSEG2,Nominal Time Segment After Sample Point"
|
|
line.long 0x18 "TSCC,Timestamp Counter Configuration Register"
|
|
hexmask.long.byte 0x18 16.--19. 1. "TCP,Timestamp Counter Prescaler"
|
|
bitfld.long 0x18 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter value used,3: Timestamp counter value always 0x0000"
|
|
line.long 0x1C "TSCV,Timestamp Counter Value Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. "TSC,Timestamp Counter (cleared on write)"
|
|
line.long 0x20 "TOCC,Timeout Counter Configuration Register"
|
|
hexmask.long.word 0x20 16.--31. 1. "TOP,Timeout Period"
|
|
bitfld.long 0x20 1.--2. "TOS,Timeout Select" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,2: Timeout controlled by Receive FIFO 0,3: Timeout controlled by Receive FIFO 1"
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|
newline
|
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bitfld.long 0x20 0. "ETOC,Enable Timeout Counter" "0: Timeout Counter disabled.,1: Timeout Counter enabled."
|
|
line.long 0x24 "TOCV,Timeout Counter Value Register"
|
|
hexmask.long.word 0x24 0.--15. 1. "TOC,Timeout Counter (cleared on write)"
|
|
rgroup.long 0x40++0x7
|
|
line.long 0x0 "ECR,Error Counter Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging (cleared on read)"
|
|
bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter"
|
|
line.long 0x4 "PSR,Protocol Status Register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value"
|
|
bitfld.long 0x4 14. "PXE,Protocol Exception Event (cleared on read)" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
|
|
newline
|
|
bitfld.long 0x4 13. "RFDF,Received a CAN FD Message (cleared on read)" "0: Since this bit was reset by the CPU no CAN FD..,1: Message in CAN FD format with FDF flag set has.."
|
|
bitfld.long 0x4 12. "RBRS,BRS Flag of Last Received CAN FD Message (cleared on read)" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set."
|
|
newline
|
|
bitfld.long 0x4 11. "RESI,ESI Flag of Last Received CAN FD Message (cleared on read)" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set."
|
|
bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code (set to 111 on read)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The MCAN is not Bus_Off.,1: The MCAN is in Bus_Off state."
|
|
bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
|
|
newline
|
|
bitfld.long 0x4 5. "EP,Error Passive" "0: The MCAN is in the Error_Active state. It..,1: The MCAN is in the Error_Passive state."
|
|
bitfld.long 0x4 3.--4. "ACT,Activity" "0: Node is synchronizing on CAN communication,1: Node is neither receiver nor transmitter,2: Node is operating as receiver,3: Node is operating as transmitter"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "LEC,Last Error Code (set to 111 on read)" "0: No error occurred since LEC has been reset by..,1: More than 5 equal bits in a sequence have..,2: A fixed format part of a received frame has the..,3: The message transmitted by the MCAN was not..,4: During transmission of a message (with the..,5: During transmission of a message (or acknowledge..,6: The CRC check sum of a received message was..,7: Any read access to the Protocol Status Register.."
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "TDCR,Transmit Delay Compensation Register"
|
|
hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset"
|
|
hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter"
|
|
group.long 0x50++0xF
|
|
line.long 0x0 "IR,Interrupt Register"
|
|
bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0: No access to reserved address occurred,1: Access to reserved address occurred"
|
|
bitfld.long 0x0 28. "PED,Protocol Error in Data Phase" "0: No protocol error in data phase,1: Protocol error in data phase detected.."
|
|
newline
|
|
bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.."
|
|
bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred.,1: Message RAM Watchdog event due to missing READY."
|
|
newline
|
|
bitfld.long 0x0 25. "BO,Bus_Off Status" "0: Bus_Off status unchanged.,1: Bus_Off status changed."
|
|
bitfld.long 0x0 24. "EW,Warning Status" "0: Error_Warning status unchanged.,1: Error_Warning status changed."
|
|
newline
|
|
bitfld.long 0x0 23. "EP,Error Passive" "0: Error_Passive status unchanged.,1: Error_Passive status changed."
|
|
bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0: CAN Error Logging Counter did not overflow.,1: Overflow of CAN Error Logging Counter occurred."
|
|
newline
|
|
bitfld.long 0x0 19. "DRX,Message stored to Dedicated Receive Buffer" "0: No Receive Buffer updated.,1: At least one received message stored into a.."
|
|
bitfld.long 0x0 18. "TOO,Timeout Occurred" "0: No timeout.,1: Timeout reached."
|
|
newline
|
|
bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0: No Message RAM access failure occurred.,1: Message RAM access failure occurred."
|
|
bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around.,1: Timestamp counter wrapped around."
|
|
newline
|
|
bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost.,1: Tx Event FIFO element lost also set after write.."
|
|
bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0: Tx Event FIFO not full.,1: Tx Event FIFO full."
|
|
newline
|
|
bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO fill level below watermark.,1: Tx Event FIFO fill level reached watermark."
|
|
bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0: Tx Event FIFO unchanged.,1: Tx Handler wrote Tx Event FIFO element."
|
|
newline
|
|
bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty.,1: Tx FIFO empty."
|
|
bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished.,1: Transmission cancellation finished."
|
|
newline
|
|
bitfld.long 0x0 9. "TC,Transmission Completed" "0: No transmission completed.,1: Transmission completed."
|
|
bitfld.long 0x0 8. "HPM,High Priority Message" "0: No high priority message received.,1: High priority message received."
|
|
newline
|
|
bitfld.long 0x0 7. "RF1L,Receive FIFO 1 Message Lost" "0: No Receive FIFO 1 message lost.,1: Receive FIFO 1 message lost also set after write.."
|
|
bitfld.long 0x0 6. "RF1F,Receive FIFO 1 Full" "0: Receive FIFO 1 not full.,1: Receive FIFO 1 full."
|
|
newline
|
|
bitfld.long 0x0 5. "RF1W,Receive FIFO 1 Watermark Reached" "0: Receive FIFO 1 fill level below watermark.,1: Receive FIFO 1 fill level reached watermark."
|
|
bitfld.long 0x0 4. "RF1N,Receive FIFO 1 New Message" "0: No new message written to Receive FIFO 1.,1: New message written to Receive FIFO 1."
|
|
newline
|
|
bitfld.long 0x0 3. "RF0L,Receive FIFO 0 Message Lost" "0: No Receive FIFO 0 message lost.,1: Receive FIFO 0 message lost also set after write.."
|
|
bitfld.long 0x0 2. "RF0F,Receive FIFO 0 Full" "0: Receive FIFO 0 not full.,1: Receive FIFO 0 full."
|
|
newline
|
|
bitfld.long 0x0 1. "RF0W,Receive FIFO 0 Watermark Reached" "0: Receive FIFO 0 fill level below watermark.,1: Receive FIFO 0 fill level reached watermark."
|
|
bitfld.long 0x0 0. "RF0N,Receive FIFO 0 New Message" "0: No new message written to Receive FIFO 0.,1: New message written to Receive FIFO 0."
|
|
line.long 0x4 "IE,Interrupt Enable Register"
|
|
bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0,1"
|
|
bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0,1"
|
|
bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Receive Buffer Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RF1LE,Receive FIFO 1 Message Lost Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 6. "RF1FE,Receive FIFO 1 Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RF1WE,Receive FIFO 1 Watermark Reached Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 4. "RF1NE,Receive FIFO 1 New Message Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RF0LE,Receive FIFO 0 Message Lost Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 2. "RF0FE,Receive FIFO 0 Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RF0WE,Receive FIFO 0 Watermark Reached Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 0. "RF0NE,Receive FIFO 0 New Message Interrupt Enable" "0,1"
|
|
line.long 0x8 "ILS,Interrupt Line Select Register"
|
|
bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0,1"
|
|
bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0,1"
|
|
bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0,1"
|
|
bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0,1"
|
|
bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Receive Buffer Interrupt Line" "0,1"
|
|
bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1"
|
|
bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1"
|
|
bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0,1"
|
|
bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "RF1LL,Receive FIFO 1 Message Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 6. "RF1FL,Receive FIFO 1 Full Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "RF1WL,Receive FIFO 1 Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 4. "RF1NL,Receive FIFO 1 New Message Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "RF0LL,Receive FIFO 0 Message Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 2. "RF0FL,Receive FIFO 0 Full Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "RF0WL,Receive FIFO 0 Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 0. "RF0NL,Receive FIFO 0 New Message Interrupt Line" "0,1"
|
|
line.long 0xC "ILE,Interrupt Line Enable Register"
|
|
bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line MCAN_INT1 disabled.,1: Interrupt line MCAN_INT1 enabled."
|
|
bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line MCAN_INT0 disabled.,1: Interrupt line MCAN_INT0 enabled."
|
|
group.long 0x80++0xB
|
|
line.long 0x0 "GFC,Global Filter Configuration Register"
|
|
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
|
|
bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
|
|
newline
|
|
bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs.,1: Reject all remote frames with 11-bit standard IDs."
|
|
bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs.,1: Reject all remote frames with 29-bit extended IDs."
|
|
line.long 0x4 "SIDFC,Standard ID Filter Configuration Register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard"
|
|
hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address"
|
|
line.long 0x8 "XIDFC,Extended ID Filter Configuration Register"
|
|
hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended"
|
|
hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address"
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "XIDAM,Extended ID AND Mask Register"
|
|
hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask"
|
|
rgroup.long 0x94++0x3
|
|
line.long 0x0 "HPMS,High Priority Message Status Register"
|
|
bitfld.long 0x0 15. "FLST,Filter List" "0: Standard filter list,1: Extended filter list"
|
|
hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected.,1: FIFO message lost.,2: Message stored in FIFO 0.,3: Message stored in FIFO 1."
|
|
hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index"
|
|
group.long 0x98++0xB
|
|
line.long 0x0 "NDAT1,New Data 1 Register"
|
|
bitfld.long 0x0 31. "ND31,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 30. "ND30,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 29. "ND29,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 28. "ND28,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 27. "ND27,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 26. "ND26,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 25. "ND25,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 24. "ND24,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 23. "ND23,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 22. "ND22,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 21. "ND21,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 20. "ND20,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 19. "ND19,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 18. "ND18,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 17. "ND17,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 16. "ND16,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 15. "ND15,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 14. "ND14,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 13. "ND13,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 12. "ND12,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 11. "ND11,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 10. "ND10,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 9. "ND9,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 8. "ND8,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 7. "ND7,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 6. "ND6,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 5. "ND5,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 4. "ND4,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 3. "ND3,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 2. "ND2,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 1. "ND1,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 0. "ND0,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
line.long 0x4 "NDAT2,New Data 2 Register"
|
|
bitfld.long 0x4 31. "ND63,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 30. "ND62,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 29. "ND61,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 28. "ND60,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 27. "ND59,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 26. "ND58,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 25. "ND57,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 24. "ND56,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 23. "ND55,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 22. "ND54,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 21. "ND53,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 20. "ND52,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 19. "ND51,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 18. "ND50,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 17. "ND49,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 16. "ND48,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 15. "ND47,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 14. "ND46,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 13. "ND45,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 12. "ND44,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 11. "ND43,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 10. "ND42,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 9. "ND41,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 8. "ND40,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 7. "ND39,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 6. "ND38,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 5. "ND37,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 4. "ND36,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 3. "ND35,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 2. "ND34,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 1. "ND33,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 0. "ND32,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
line.long 0x8 "RXF0C,Receive FIFO 0 Configuration Register"
|
|
bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0: FIFO 0 Blocking mode.,1: FIFO 0 Overwrite mode."
|
|
hexmask.long.byte 0x8 24.--30. 1. "F0WM,Receive FIFO 0 Watermark"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "F0S,Receive FIFO 0 Size"
|
|
hexmask.long.word 0x8 2.--15. 1. "F0SA,Receive FIFO 0 Start Address"
|
|
rgroup.long 0xA4++0x3
|
|
line.long 0x0 "RXF0S,Receive FIFO 0 Status Register"
|
|
bitfld.long 0x0 25. "RF0L,Receive FIFO 0 Message Lost" "0: No Receive FIFO 0 message lost,1: Receive FIFO 0 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F0F,Receive FIFO 0 Full" "0: Receive FIFO 0 not full.,1: Receive FIFO 0 full."
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "F0PI,Receive FIFO 0 Put Index"
|
|
hexmask.long.byte 0x0 8.--13. 1. "F0GI,Receive FIFO 0 Get Index"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "F0FL,Receive FIFO 0 Fill Level"
|
|
group.long 0xA8++0xB
|
|
line.long 0x0 "RXF0A,Receive FIFO 0 Acknowledge Register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F0AI,Receive FIFO 0 Acknowledge Index"
|
|
line.long 0x4 "RXBC,Receive Rx Buffer Configuration Register"
|
|
hexmask.long.word 0x4 2.--15. 1. "RBSA,Receive Buffer Start Address"
|
|
line.long 0x8 "RXF1C,Receive FIFO 1 Configuration Register"
|
|
bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0: FIFO 1 Blocking mode.,1: FIFO 1 Overwrite mode."
|
|
hexmask.long.byte 0x8 24.--30. 1. "F1WM,Receive FIFO 1 Watermark"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "F1S,Receive FIFO 1 Size"
|
|
hexmask.long.word 0x8 2.--15. 1. "F1SA,Receive FIFO 1 Start Address"
|
|
rgroup.long 0xB4++0x3
|
|
line.long 0x0 "RXF1S,Receive FIFO 1 Status Register"
|
|
bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0: Idle state wait for reception of debug messages..,1: Debug message A received.,2: Debug messages A B received.,3: Debug messages A B C received DMA request is set."
|
|
bitfld.long 0x0 25. "RF1L,Receive FIFO 1 Message Lost" "0: No Receive FIFO 1 message lost.,1: Receive FIFO 1 message lost also set after write.."
|
|
newline
|
|
bitfld.long 0x0 24. "F1F,Receive FIFO 1 Full" "0: Receive FIFO 1 not full.,1: Receive FIFO 1 full."
|
|
hexmask.long.byte 0x0 16.--21. 1. "F1PI,Receive FIFO 1 Put Index"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "F1GI,Receive FIFO 1 Get Index"
|
|
hexmask.long.byte 0x0 0.--6. 1. "F1FL,Receive FIFO 1 Fill Level"
|
|
group.long 0xB8++0xB
|
|
line.long 0x0 "RXF1A,Receive FIFO 1 Acknowledge Register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Receive FIFO 1 Acknowledge Index"
|
|
line.long 0x4 "RXESC,Receive Buffer / FIFO Element Size Configuration Register"
|
|
bitfld.long 0x4 8.--10. "RBDS,Receive Buffer Data Field Size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field"
|
|
bitfld.long 0x4 4.--6. "F1DS,Receive FIFO 1 Data Field Size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "F0DS,Receive FIFO 0 Data Field Size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field"
|
|
line.long 0x8 "TXBC,Transmit Buffer Configuration Register"
|
|
bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation.,1: Tx Queue operation."
|
|
hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers"
|
|
hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address"
|
|
rgroup.long 0xC4++0x3
|
|
line.long 0x0 "TXFQS,Transmit FIFO/Queue Status Register"
|
|
bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full.,1: Tx FIFO/Queue full."
|
|
hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index"
|
|
hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level"
|
|
group.long 0xC8++0x3
|
|
line.long 0x0 "TXESC,Transmit Buffer Element Size Configuration Register"
|
|
bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48- byte data field,7: 64-byte data field"
|
|
rgroup.long 0xCC++0x3
|
|
line.long 0x0 "TXBRP,Transmit Buffer Request Pending Register"
|
|
bitfld.long 0x0 31. "TRP31,Transmission Request Pending for Buffer 31" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 30. "TRP30,Transmission Request Pending for Buffer 30" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 29. "TRP29,Transmission Request Pending for Buffer 29" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 28. "TRP28,Transmission Request Pending for Buffer 28" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 27. "TRP27,Transmission Request Pending for Buffer 27" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 26. "TRP26,Transmission Request Pending for Buffer 26" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 25. "TRP25,Transmission Request Pending for Buffer 25" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 24. "TRP24,Transmission Request Pending for Buffer 24" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 23. "TRP23,Transmission Request Pending for Buffer 23" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 22. "TRP22,Transmission Request Pending for Buffer 22" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 21. "TRP21,Transmission Request Pending for Buffer 21" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 20. "TRP20,Transmission Request Pending for Buffer 20" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 19. "TRP19,Transmission Request Pending for Buffer 19" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 18. "TRP18,Transmission Request Pending for Buffer 18" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 17. "TRP17,Transmission Request Pending for Buffer 17" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 16. "TRP16,Transmission Request Pending for Buffer 16" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 15. "TRP15,Transmission Request Pending for Buffer 15" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 14. "TRP14,Transmission Request Pending for Buffer 14" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 13. "TRP13,Transmission Request Pending for Buffer 13" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 12. "TRP12,Transmission Request Pending for Buffer 12" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 11. "TRP11,Transmission Request Pending for Buffer 11" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 10. "TRP10,Transmission Request Pending for Buffer 10" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 9. "TRP9,Transmission Request Pending for Buffer 9" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 8. "TRP8,Transmission Request Pending for Buffer 8" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 7. "TRP7,Transmission Request Pending for Buffer 7" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 6. "TRP6,Transmission Request Pending for Buffer 6" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 5. "TRP5,Transmission Request Pending for Buffer 5" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 4. "TRP4,Transmission Request Pending for Buffer 4" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 3. "TRP3,Transmission Request Pending for Buffer 3" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 2. "TRP2,Transmission Request Pending for Buffer 2" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 1. "TRP1,Transmission Request Pending for Buffer 1" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 0. "TRP0,Transmission Request Pending for Buffer 0" "0: No transmission request pending,1: Transmission request pending"
|
|
group.long 0xD0++0x7
|
|
line.long 0x0 "TXBAR,Transmit Buffer Add Request Register"
|
|
bitfld.long 0x0 31. "AR31,Add Request for Transmit Buffer 31" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 30. "AR30,Add Request for Transmit Buffer 30" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 29. "AR29,Add Request for Transmit Buffer 29" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 28. "AR28,Add Request for Transmit Buffer 28" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 27. "AR27,Add Request for Transmit Buffer 27" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 26. "AR26,Add Request for Transmit Buffer 26" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 25. "AR25,Add Request for Transmit Buffer 25" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 24. "AR24,Add Request for Transmit Buffer 24" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 23. "AR23,Add Request for Transmit Buffer 23" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 22. "AR22,Add Request for Transmit Buffer 22" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 21. "AR21,Add Request for Transmit Buffer 21" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 20. "AR20,Add Request for Transmit Buffer 20" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 19. "AR19,Add Request for Transmit Buffer 19" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 18. "AR18,Add Request for Transmit Buffer 18" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 17. "AR17,Add Request for Transmit Buffer 17" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 16. "AR16,Add Request for Transmit Buffer 16" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 15. "AR15,Add Request for Transmit Buffer 15" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 14. "AR14,Add Request for Transmit Buffer 14" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 13. "AR13,Add Request for Transmit Buffer 13" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 12. "AR12,Add Request for Transmit Buffer 12" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 11. "AR11,Add Request for Transmit Buffer 11" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 10. "AR10,Add Request for Transmit Buffer 10" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 9. "AR9,Add Request for Transmit Buffer 9" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 8. "AR8,Add Request for Transmit Buffer 8" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 7. "AR7,Add Request for Transmit Buffer 7" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 6. "AR6,Add Request for Transmit Buffer 6" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 5. "AR5,Add Request for Transmit Buffer 5" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 4. "AR4,Add Request for Transmit Buffer 4" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 3. "AR3,Add Request for Transmit Buffer 3" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 2. "AR2,Add Request for Transmit Buffer 2" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 1. "AR1,Add Request for Transmit Buffer 1" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 0. "AR0,Add Request for Transmit Buffer 0" "0: No transmission request added.,1: Transmission requested added."
|
|
line.long 0x4 "TXBCR,Transmit Buffer Cancellation Request Register"
|
|
bitfld.long 0x4 31. "CR31,Cancellation Request for Transmit Buffer 31" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 30. "CR30,Cancellation Request for Transmit Buffer 30" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 29. "CR29,Cancellation Request for Transmit Buffer 29" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 28. "CR28,Cancellation Request for Transmit Buffer 28" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 27. "CR27,Cancellation Request for Transmit Buffer 27" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 26. "CR26,Cancellation Request for Transmit Buffer 26" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 25. "CR25,Cancellation Request for Transmit Buffer 25" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 24. "CR24,Cancellation Request for Transmit Buffer 24" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 23. "CR23,Cancellation Request for Transmit Buffer 23" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 22. "CR22,Cancellation Request for Transmit Buffer 22" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 21. "CR21,Cancellation Request for Transmit Buffer 21" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 20. "CR20,Cancellation Request for Transmit Buffer 20" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 19. "CR19,Cancellation Request for Transmit Buffer 19" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 18. "CR18,Cancellation Request for Transmit Buffer 18" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 17. "CR17,Cancellation Request for Transmit Buffer 17" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 16. "CR16,Cancellation Request for Transmit Buffer 16" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 15. "CR15,Cancellation Request for Transmit Buffer 15" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 14. "CR14,Cancellation Request for Transmit Buffer 14" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 13. "CR13,Cancellation Request for Transmit Buffer 13" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 12. "CR12,Cancellation Request for Transmit Buffer 12" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 11. "CR11,Cancellation Request for Transmit Buffer 11" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 10. "CR10,Cancellation Request for Transmit Buffer 10" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 9. "CR9,Cancellation Request for Transmit Buffer 9" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 8. "CR8,Cancellation Request for Transmit Buffer 8" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 7. "CR7,Cancellation Request for Transmit Buffer 7" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 6. "CR6,Cancellation Request for Transmit Buffer 6" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 5. "CR5,Cancellation Request for Transmit Buffer 5" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 4. "CR4,Cancellation Request for Transmit Buffer 4" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 3. "CR3,Cancellation Request for Transmit Buffer 3" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 2. "CR2,Cancellation Request for Transmit Buffer 2" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 1. "CR1,Cancellation Request for Transmit Buffer 1" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 0. "CR0,Cancellation Request for Transmit Buffer 0" "0: No cancellation pending.,1: Cancellation pending."
|
|
rgroup.long 0xD8++0x7
|
|
line.long 0x0 "TXBTO,Transmit Buffer Transmission Occurred Register"
|
|
bitfld.long 0x0 31. "TO31,Transmission Occurred for Buffer 31" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 30. "TO30,Transmission Occurred for Buffer 30" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 29. "TO29,Transmission Occurred for Buffer 29" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 28. "TO28,Transmission Occurred for Buffer 28" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 27. "TO27,Transmission Occurred for Buffer 27" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 26. "TO26,Transmission Occurred for Buffer 26" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 25. "TO25,Transmission Occurred for Buffer 25" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 24. "TO24,Transmission Occurred for Buffer 24" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 23. "TO23,Transmission Occurred for Buffer 23" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 22. "TO22,Transmission Occurred for Buffer 22" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 21. "TO21,Transmission Occurred for Buffer 21" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 20. "TO20,Transmission Occurred for Buffer 20" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 19. "TO19,Transmission Occurred for Buffer 19" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 18. "TO18,Transmission Occurred for Buffer 18" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 17. "TO17,Transmission Occurred for Buffer 17" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 16. "TO16,Transmission Occurred for Buffer 16" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 15. "TO15,Transmission Occurred for Buffer 15" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 14. "TO14,Transmission Occurred for Buffer 14" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 13. "TO13,Transmission Occurred for Buffer 13" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 12. "TO12,Transmission Occurred for Buffer 12" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 11. "TO11,Transmission Occurred for Buffer 11" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 10. "TO10,Transmission Occurred for Buffer 10" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 9. "TO9,Transmission Occurred for Buffer 9" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 8. "TO8,Transmission Occurred for Buffer 8" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 7. "TO7,Transmission Occurred for Buffer 7" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 6. "TO6,Transmission Occurred for Buffer 6" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 5. "TO5,Transmission Occurred for Buffer 5" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 4. "TO4,Transmission Occurred for Buffer 4" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 3. "TO3,Transmission Occurred for Buffer 3" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 2. "TO2,Transmission Occurred for Buffer 2" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 1. "TO1,Transmission Occurred for Buffer 1" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 0. "TO0,Transmission Occurred for Buffer 0" "0: No transmission occurred.,1: Transmission occurred."
|
|
line.long 0x4 "TXBCF,Transmit Buffer Cancellation Finished Register"
|
|
bitfld.long 0x4 31. "CF31,Cancellation Finished for Transmit Buffer 31" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 30. "CF30,Cancellation Finished for Transmit Buffer 30" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 29. "CF29,Cancellation Finished for Transmit Buffer 29" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 28. "CF28,Cancellation Finished for Transmit Buffer 28" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 27. "CF27,Cancellation Finished for Transmit Buffer 27" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 26. "CF26,Cancellation Finished for Transmit Buffer 26" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 25. "CF25,Cancellation Finished for Transmit Buffer 25" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 24. "CF24,Cancellation Finished for Transmit Buffer 24" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 23. "CF23,Cancellation Finished for Transmit Buffer 23" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 22. "CF22,Cancellation Finished for Transmit Buffer 22" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 21. "CF21,Cancellation Finished for Transmit Buffer 21" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 20. "CF20,Cancellation Finished for Transmit Buffer 20" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
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|
|
bitfld.long 0x4 19. "CF19,Cancellation Finished for Transmit Buffer 19" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 18. "CF18,Cancellation Finished for Transmit Buffer 18" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 17. "CF17,Cancellation Finished for Transmit Buffer 17" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 16. "CF16,Cancellation Finished for Transmit Buffer 16" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
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|
bitfld.long 0x4 15. "CF15,Cancellation Finished for Transmit Buffer 15" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 14. "CF14,Cancellation Finished for Transmit Buffer 14" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 13. "CF13,Cancellation Finished for Transmit Buffer 13" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 12. "CF12,Cancellation Finished for Transmit Buffer 12" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
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bitfld.long 0x4 11. "CF11,Cancellation Finished for Transmit Buffer 11" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 10. "CF10,Cancellation Finished for Transmit Buffer 10" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
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bitfld.long 0x4 9. "CF9,Cancellation Finished for Transmit Buffer 9" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 8. "CF8,Cancellation Finished for Transmit Buffer 8" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
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bitfld.long 0x4 7. "CF7,Cancellation Finished for Transmit Buffer 7" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 6. "CF6,Cancellation Finished for Transmit Buffer 6" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
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bitfld.long 0x4 5. "CF5,Cancellation Finished for Transmit Buffer 5" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 4. "CF4,Cancellation Finished for Transmit Buffer 4" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
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bitfld.long 0x4 3. "CF3,Cancellation Finished for Transmit Buffer 3" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 2. "CF2,Cancellation Finished for Transmit Buffer 2" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
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bitfld.long 0x4 1. "CF1,Cancellation Finished for Transmit Buffer 1" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 0. "CF0,Cancellation Finished for Transmit Buffer 0" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
group.long 0xE0++0x7
|
|
line.long 0x0 "TXBTIE,Transmit Buffer Transmission Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable for Buffer 31" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable for Buffer 30" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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|
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bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable for Buffer 29" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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|
bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable for Buffer 28" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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newline
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bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable for Buffer 27" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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|
bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable for Buffer 26" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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newline
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bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable for Buffer 25" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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|
bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable for Buffer 24" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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|
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bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable for Buffer 23" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable for Buffer 22" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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newline
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bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable for Buffer 21" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable for Buffer 20" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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newline
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bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable for Buffer 19" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable for Buffer 18" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable for Buffer 17" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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|
bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable for Buffer 16" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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newline
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bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable for Buffer 15" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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|
bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable for Buffer 14" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable for Buffer 13" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable for Buffer 12" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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newline
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bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable for Buffer 11" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable for Buffer 10" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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newline
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bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable for Buffer 9" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable for Buffer 8" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable for Buffer 7" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable for Buffer 6" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable for Buffer 5" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable for Buffer 4" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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newline
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bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable for Buffer 3" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable for Buffer 2" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
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newline
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bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable for Buffer 1" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable for Buffer 0" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
line.long 0x4 "TXBCIE,Transmit Buffer Cancellation Finished Interrupt Enable Register"
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bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable for Transmit Buffer 31" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable for Transmit Buffer 30" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable for Transmit Buffer 29" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable for Transmit Buffer 28" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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newline
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bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable for Transmit Buffer 27" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable for Transmit Buffer 26" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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newline
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bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable for Transmit Buffer 25" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable for Transmit Buffer 24" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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newline
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bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable for Transmit Buffer 23" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable for Transmit Buffer 22" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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newline
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bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable for Transmit Buffer 21" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable for Transmit Buffer 20" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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newline
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bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable for Transmit Buffer 19" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable for Transmit Buffer 18" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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newline
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bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable for Transmit Buffer 17" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable for Transmit Buffer 16" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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newline
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bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable for Transmit Buffer 15" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable for Transmit Buffer 14" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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newline
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bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable for Transmit Buffer 13" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable for Transmit Buffer 12" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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newline
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bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable for Transmit Buffer 11" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable for Transmit Buffer 10" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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newline
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bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable for Transmit Buffer 9" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable for Transmit Buffer 8" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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newline
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bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable for Transmit Buffer 7" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable for Transmit Buffer 6" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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newline
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bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable for Transmit Buffer 5" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable for Transmit Buffer 4" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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newline
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bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable for Transmit Buffer 3" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable for Transmit Buffer 2" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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newline
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bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable for Transmit Buffer 1" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable for Transmit Buffer 0" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
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group.long 0xF0++0x3
|
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line.long 0x0 "TXEFC,Transmit Event FIFO Configuration Register"
|
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hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark"
|
|
hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size"
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|
newline
|
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hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address"
|
|
rgroup.long 0xF4++0x3
|
|
line.long 0x0 "TXEFS,Transmit Event FIFO Status Register"
|
|
bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.."
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|
bitfld.long 0x0 24. "EFF,Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full"
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newline
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hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index"
|
|
hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index"
|
|
newline
|
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hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level"
|
|
group.long 0xF8++0x3
|
|
line.long 0x0 "TXEFA,Transmit Event FIFO Acknowledge Register"
|
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hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index"
|
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tree.end
|
|
tree "MCAN2"
|
|
base ad:0xE0830000
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "ENDN,Endian Register"
|
|
hexmask.long 0x0 0.--31. 1. "ETV,Endianness Test Value"
|
|
group.long 0x8++0x27
|
|
line.long 0x0 "CUST,Customer Register"
|
|
hexmask.long 0x0 0.--31. 1. "CSV,Customer-specific Value"
|
|
line.long 0x4 "DBTP,Data Bit Timing and Prescaler Register"
|
|
bitfld.long 0x4 23. "TDC,Transmitter Delay Compensation" "0: Transmitter Delay Compensation disabled.,1: Transmitter Delay Compensation enabled."
|
|
hexmask.long.byte 0x4 16.--20. 1. "DBRP,Data Bit Rate Prescaler"
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|
newline
|
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hexmask.long.byte 0x4 8.--12. 1. "DTSEG1,Data Time Segment Before Sample Point"
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|
hexmask.long.byte 0x4 4.--7. 1. "DTSEG2,Data Time Segment After Sample Point"
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|
newline
|
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bitfld.long 0x4 0.--2. "DSJW,Data (Re) Synchronization Jump Width" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "TEST,Test Register"
|
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bitfld.long 0x8 7. "RX,Receive Pin (read-only)" "0: The CAN bus is dominant (CANRX = '0').,1: The CAN bus is recessive (CANRX = '1')."
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bitfld.long 0x8 5.--6. "TX,Control of Transmit Pin (read/write)" "0: Reset value CANTX controlled by the CAN Core..,1: Sample Point can be monitored at pin CANTX.,2: Dominant ('0') level at pin CANTX.,3: Recessive ('1') at pin CANTX."
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newline
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bitfld.long 0x8 4. "LBCK,Loop Back Mode (read/write)" "0: Reset value. Loop Back mode is disabled.,1: Loop Back mode is enabled (see Section 6.1.9.."
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|
line.long 0xC "RWD,RAM Watchdog Register"
|
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hexmask.long.byte 0xC 8.--15. 1. "WDV,Watchdog Value (read-only)"
|
|
hexmask.long.byte 0xC 0.--7. 1. "WDC,Watchdog Configuration (read/write)"
|
|
line.long 0x10 "CCCR,CC Control Register"
|
|
bitfld.long 0x10 15. "NISO,Non-ISO Operation" "0: CAN FD frame format according to ISO11898-1..,1: CAN FD frame format according to Bosch CAN FD.."
|
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bitfld.long 0x10 14. "TXP,Transmit Pause (read/write write protection)" "0: Transmit pause disabled.,1: Transmit pause enabled."
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newline
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bitfld.long 0x10 13. "EFBI,Edge Filtering during Bus Integration (read/write write protection)" "0: Edge filtering is disabled.,1: Edge filtering is enabled. Two consecutive.."
|
|
bitfld.long 0x10 12. "PXHD,Protocol Exception Event Handling (read/write write protection)" "0: Protocol exception handling enabled.,1: Protocol exception handling disabled."
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|
newline
|
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bitfld.long 0x10 9. "BRSE,Bit Rate Switching Enable (read/write write protection)" "0: Bit rate switching for transmissions disabled.,1: Bit rate switching for transmissions enabled."
|
|
bitfld.long 0x10 8. "FDOE,CAN FD Operation Enable (read/write write protection)" "0: FD operation disabled.,1: FD operation enabled."
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newline
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bitfld.long 0x10 7. "TEST,Test Mode Enable (read/write write protection against '1')" "0: Normal operation MCAN_TEST register holds reset..,1: Test mode write access to MCAN_TEST register.."
|
|
bitfld.long 0x10 6. "DAR,Disable Automatic Retransmission (read/write write protection)" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled."
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|
newline
|
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bitfld.long 0x10 5. "MON,Bus Monitoring Mode (read/write write protection against '1')" "0: Bus Monitoring mode is disabled.,1: Bus Monitoring mode is enabled."
|
|
bitfld.long 0x10 4. "CSR,Clock Stop Request (read/write)" "0: No clock stop is requested.,1: Clock stop requested. When clock stop is.."
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newline
|
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bitfld.long 0x10 3. "CSA,Clock Stop Acknowledge (read-only)" "0: No clock stop acknowledged.,1: MCAN may be set in power down by stopping the.."
|
|
bitfld.long 0x10 2. "ASM,Restricted Operation Mode (read/write write protection against '1')" "0: Normal CAN operation.,1: Restricted Operation mode active."
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newline
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bitfld.long 0x10 1. "CCE,Configuration Change Enable (read/write write protection)" "0: The processor has no write access to the..,1: The processor has write access to the protected.."
|
|
bitfld.long 0x10 0. "INIT,Initialization (read/write)" "0: Normal operation.,1: Initialization is started."
|
|
line.long 0x14 "NBTP,Nominal Bit Timing and Prescaler Register"
|
|
hexmask.long.byte 0x14 25.--31. 1. "NSJW,Nominal (Re) Synchronization Jump Width"
|
|
hexmask.long.word 0x14 16.--24. 1. "NBRP,Nominal Bit Rate Prescaler"
|
|
newline
|
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hexmask.long.byte 0x14 8.--15. 1. "NTSEG1,Nominal Time Segment Before Sample Point"
|
|
hexmask.long.byte 0x14 0.--6. 1. "NTSEG2,Nominal Time Segment After Sample Point"
|
|
line.long 0x18 "TSCC,Timestamp Counter Configuration Register"
|
|
hexmask.long.byte 0x18 16.--19. 1. "TCP,Timestamp Counter Prescaler"
|
|
bitfld.long 0x18 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter value used,3: Timestamp counter value always 0x0000"
|
|
line.long 0x1C "TSCV,Timestamp Counter Value Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. "TSC,Timestamp Counter (cleared on write)"
|
|
line.long 0x20 "TOCC,Timeout Counter Configuration Register"
|
|
hexmask.long.word 0x20 16.--31. 1. "TOP,Timeout Period"
|
|
bitfld.long 0x20 1.--2. "TOS,Timeout Select" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,2: Timeout controlled by Receive FIFO 0,3: Timeout controlled by Receive FIFO 1"
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|
newline
|
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bitfld.long 0x20 0. "ETOC,Enable Timeout Counter" "0: Timeout Counter disabled.,1: Timeout Counter enabled."
|
|
line.long 0x24 "TOCV,Timeout Counter Value Register"
|
|
hexmask.long.word 0x24 0.--15. 1. "TOC,Timeout Counter (cleared on write)"
|
|
rgroup.long 0x40++0x7
|
|
line.long 0x0 "ECR,Error Counter Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging (cleared on read)"
|
|
bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.."
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|
newline
|
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hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter"
|
|
line.long 0x4 "PSR,Protocol Status Register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value"
|
|
bitfld.long 0x4 14. "PXE,Protocol Exception Event (cleared on read)" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
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|
newline
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bitfld.long 0x4 13. "RFDF,Received a CAN FD Message (cleared on read)" "0: Since this bit was reset by the CPU no CAN FD..,1: Message in CAN FD format with FDF flag set has.."
|
|
bitfld.long 0x4 12. "RBRS,BRS Flag of Last Received CAN FD Message (cleared on read)" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set."
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|
newline
|
|
bitfld.long 0x4 11. "RESI,ESI Flag of Last Received CAN FD Message (cleared on read)" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set."
|
|
bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code (set to 111 on read)" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The MCAN is not Bus_Off.,1: The MCAN is in Bus_Off state."
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bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
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newline
|
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bitfld.long 0x4 5. "EP,Error Passive" "0: The MCAN is in the Error_Active state. It..,1: The MCAN is in the Error_Passive state."
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|
bitfld.long 0x4 3.--4. "ACT,Activity" "0: Node is synchronizing on CAN communication,1: Node is neither receiver nor transmitter,2: Node is operating as receiver,3: Node is operating as transmitter"
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newline
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bitfld.long 0x4 0.--2. "LEC,Last Error Code (set to 111 on read)" "0: No error occurred since LEC has been reset by..,1: More than 5 equal bits in a sequence have..,2: A fixed format part of a received frame has the..,3: The message transmitted by the MCAN was not..,4: During transmission of a message (with the..,5: During transmission of a message (or acknowledge..,6: The CRC check sum of a received message was..,7: Any read access to the Protocol Status Register.."
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group.long 0x48++0x3
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|
line.long 0x0 "TDCR,Transmit Delay Compensation Register"
|
|
hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset"
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hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter"
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group.long 0x50++0xF
|
|
line.long 0x0 "IR,Interrupt Register"
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|
bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0: No access to reserved address occurred,1: Access to reserved address occurred"
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|
bitfld.long 0x0 28. "PED,Protocol Error in Data Phase" "0: No protocol error in data phase,1: Protocol error in data phase detected.."
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newline
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bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.."
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|
bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred.,1: Message RAM Watchdog event due to missing READY."
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newline
|
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bitfld.long 0x0 25. "BO,Bus_Off Status" "0: Bus_Off status unchanged.,1: Bus_Off status changed."
|
|
bitfld.long 0x0 24. "EW,Warning Status" "0: Error_Warning status unchanged.,1: Error_Warning status changed."
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newline
|
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bitfld.long 0x0 23. "EP,Error Passive" "0: Error_Passive status unchanged.,1: Error_Passive status changed."
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|
bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0: CAN Error Logging Counter did not overflow.,1: Overflow of CAN Error Logging Counter occurred."
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newline
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bitfld.long 0x0 19. "DRX,Message stored to Dedicated Receive Buffer" "0: No Receive Buffer updated.,1: At least one received message stored into a.."
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|
bitfld.long 0x0 18. "TOO,Timeout Occurred" "0: No timeout.,1: Timeout reached."
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newline
|
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bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0: No Message RAM access failure occurred.,1: Message RAM access failure occurred."
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bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around.,1: Timestamp counter wrapped around."
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newline
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bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost.,1: Tx Event FIFO element lost also set after write.."
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bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0: Tx Event FIFO not full.,1: Tx Event FIFO full."
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newline
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bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO fill level below watermark.,1: Tx Event FIFO fill level reached watermark."
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bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0: Tx Event FIFO unchanged.,1: Tx Handler wrote Tx Event FIFO element."
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newline
|
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bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty.,1: Tx FIFO empty."
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bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished.,1: Transmission cancellation finished."
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newline
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bitfld.long 0x0 9. "TC,Transmission Completed" "0: No transmission completed.,1: Transmission completed."
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bitfld.long 0x0 8. "HPM,High Priority Message" "0: No high priority message received.,1: High priority message received."
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newline
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bitfld.long 0x0 7. "RF1L,Receive FIFO 1 Message Lost" "0: No Receive FIFO 1 message lost.,1: Receive FIFO 1 message lost also set after write.."
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bitfld.long 0x0 6. "RF1F,Receive FIFO 1 Full" "0: Receive FIFO 1 not full.,1: Receive FIFO 1 full."
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newline
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bitfld.long 0x0 5. "RF1W,Receive FIFO 1 Watermark Reached" "0: Receive FIFO 1 fill level below watermark.,1: Receive FIFO 1 fill level reached watermark."
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bitfld.long 0x0 4. "RF1N,Receive FIFO 1 New Message" "0: No new message written to Receive FIFO 1.,1: New message written to Receive FIFO 1."
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newline
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bitfld.long 0x0 3. "RF0L,Receive FIFO 0 Message Lost" "0: No Receive FIFO 0 message lost.,1: Receive FIFO 0 message lost also set after write.."
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bitfld.long 0x0 2. "RF0F,Receive FIFO 0 Full" "0: Receive FIFO 0 not full.,1: Receive FIFO 0 full."
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newline
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bitfld.long 0x0 1. "RF0W,Receive FIFO 0 Watermark Reached" "0: Receive FIFO 0 fill level below watermark.,1: Receive FIFO 0 fill level reached watermark."
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bitfld.long 0x0 0. "RF0N,Receive FIFO 0 New Message" "0: No new message written to Receive FIFO 0.,1: New message written to Receive FIFO 0."
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line.long 0x4 "IE,Interrupt Enable Register"
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bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0,1"
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bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0,1"
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newline
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bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0,1"
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bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0,1"
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newline
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bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0,1"
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bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0,1"
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newline
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bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0,1"
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bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1"
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newline
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bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Receive Buffer Interrupt Enable" "0,1"
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bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1"
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newline
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bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1"
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bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1"
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newline
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bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1"
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bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1"
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newline
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bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0,1"
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bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1"
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newline
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bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1"
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bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1"
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newline
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bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0,1"
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bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0,1"
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newline
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bitfld.long 0x4 7. "RF1LE,Receive FIFO 1 Message Lost Interrupt Enable" "0,1"
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bitfld.long 0x4 6. "RF1FE,Receive FIFO 1 Full Interrupt Enable" "0,1"
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newline
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bitfld.long 0x4 5. "RF1WE,Receive FIFO 1 Watermark Reached Interrupt Enable" "0,1"
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bitfld.long 0x4 4. "RF1NE,Receive FIFO 1 New Message Interrupt Enable" "0,1"
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newline
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bitfld.long 0x4 3. "RF0LE,Receive FIFO 0 Message Lost Interrupt Enable" "0,1"
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bitfld.long 0x4 2. "RF0FE,Receive FIFO 0 Full Interrupt Enable" "0,1"
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newline
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bitfld.long 0x4 1. "RF0WE,Receive FIFO 0 Watermark Reached Interrupt Enable" "0,1"
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bitfld.long 0x4 0. "RF0NE,Receive FIFO 0 New Message Interrupt Enable" "0,1"
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line.long 0x8 "ILS,Interrupt Line Select Register"
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bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0,1"
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bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0,1"
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newline
|
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bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0,1"
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bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0,1"
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newline
|
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bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0,1"
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bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0,1"
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newline
|
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bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0,1"
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bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1"
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newline
|
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bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Receive Buffer Interrupt Line" "0,1"
|
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bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0,1"
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newline
|
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bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1"
|
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bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1"
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newline
|
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bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1"
|
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bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1"
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newline
|
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bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1"
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bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1"
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newline
|
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bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1"
|
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bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0,1"
|
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newline
|
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bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0,1"
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bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0,1"
|
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newline
|
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bitfld.long 0x8 7. "RF1LL,Receive FIFO 1 Message Lost Interrupt Line" "0,1"
|
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bitfld.long 0x8 6. "RF1FL,Receive FIFO 1 Full Interrupt Line" "0,1"
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newline
|
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bitfld.long 0x8 5. "RF1WL,Receive FIFO 1 Watermark Reached Interrupt Line" "0,1"
|
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bitfld.long 0x8 4. "RF1NL,Receive FIFO 1 New Message Interrupt Line" "0,1"
|
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newline
|
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bitfld.long 0x8 3. "RF0LL,Receive FIFO 0 Message Lost Interrupt Line" "0,1"
|
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bitfld.long 0x8 2. "RF0FL,Receive FIFO 0 Full Interrupt Line" "0,1"
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newline
|
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bitfld.long 0x8 1. "RF0WL,Receive FIFO 0 Watermark Reached Interrupt Line" "0,1"
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bitfld.long 0x8 0. "RF0NL,Receive FIFO 0 New Message Interrupt Line" "0,1"
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line.long 0xC "ILE,Interrupt Line Enable Register"
|
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bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line MCAN_INT1 disabled.,1: Interrupt line MCAN_INT1 enabled."
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bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line MCAN_INT0 disabled.,1: Interrupt line MCAN_INT0 enabled."
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group.long 0x80++0xB
|
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line.long 0x0 "GFC,Global Filter Configuration Register"
|
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bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
|
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bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
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newline
|
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bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs.,1: Reject all remote frames with 11-bit standard IDs."
|
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bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs.,1: Reject all remote frames with 29-bit extended IDs."
|
|
line.long 0x4 "SIDFC,Standard ID Filter Configuration Register"
|
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hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard"
|
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hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address"
|
|
line.long 0x8 "XIDFC,Extended ID Filter Configuration Register"
|
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hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended"
|
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hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address"
|
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group.long 0x90++0x3
|
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line.long 0x0 "XIDAM,Extended ID AND Mask Register"
|
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hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask"
|
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rgroup.long 0x94++0x3
|
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line.long 0x0 "HPMS,High Priority Message Status Register"
|
|
bitfld.long 0x0 15. "FLST,Filter List" "0: Standard filter list,1: Extended filter list"
|
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hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index"
|
|
newline
|
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bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected.,1: FIFO message lost.,2: Message stored in FIFO 0.,3: Message stored in FIFO 1."
|
|
hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index"
|
|
group.long 0x98++0xB
|
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line.long 0x0 "NDAT1,New Data 1 Register"
|
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bitfld.long 0x0 31. "ND31,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
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bitfld.long 0x0 30. "ND30,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
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newline
|
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bitfld.long 0x0 29. "ND29,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
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bitfld.long 0x0 28. "ND28,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
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bitfld.long 0x0 27. "ND27,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
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bitfld.long 0x0 26. "ND26,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
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bitfld.long 0x0 25. "ND25,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
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bitfld.long 0x0 24. "ND24,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 23. "ND23,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 22. "ND22,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
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bitfld.long 0x0 21. "ND21,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 20. "ND20,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 19. "ND19,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 18. "ND18,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 17. "ND17,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 16. "ND16,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 15. "ND15,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 14. "ND14,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 13. "ND13,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 12. "ND12,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 11. "ND11,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 10. "ND10,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 9. "ND9,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 8. "ND8,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 7. "ND7,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 6. "ND6,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 5. "ND5,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 4. "ND4,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 3. "ND3,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 2. "ND2,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 1. "ND1,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 0. "ND0,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
line.long 0x4 "NDAT2,New Data 2 Register"
|
|
bitfld.long 0x4 31. "ND63,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 30. "ND62,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 29. "ND61,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 28. "ND60,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 27. "ND59,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 26. "ND58,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 25. "ND57,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 24. "ND56,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 23. "ND55,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 22. "ND54,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 21. "ND53,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 20. "ND52,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 19. "ND51,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 18. "ND50,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 17. "ND49,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 16. "ND48,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 15. "ND47,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 14. "ND46,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 13. "ND45,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 12. "ND44,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 11. "ND43,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 10. "ND42,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 9. "ND41,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 8. "ND40,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 7. "ND39,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 6. "ND38,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 5. "ND37,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 4. "ND36,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 3. "ND35,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 2. "ND34,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 1. "ND33,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 0. "ND32,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
line.long 0x8 "RXF0C,Receive FIFO 0 Configuration Register"
|
|
bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0: FIFO 0 Blocking mode.,1: FIFO 0 Overwrite mode."
|
|
hexmask.long.byte 0x8 24.--30. 1. "F0WM,Receive FIFO 0 Watermark"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "F0S,Receive FIFO 0 Size"
|
|
hexmask.long.word 0x8 2.--15. 1. "F0SA,Receive FIFO 0 Start Address"
|
|
rgroup.long 0xA4++0x3
|
|
line.long 0x0 "RXF0S,Receive FIFO 0 Status Register"
|
|
bitfld.long 0x0 25. "RF0L,Receive FIFO 0 Message Lost" "0: No Receive FIFO 0 message lost,1: Receive FIFO 0 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F0F,Receive FIFO 0 Full" "0: Receive FIFO 0 not full.,1: Receive FIFO 0 full."
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "F0PI,Receive FIFO 0 Put Index"
|
|
hexmask.long.byte 0x0 8.--13. 1. "F0GI,Receive FIFO 0 Get Index"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "F0FL,Receive FIFO 0 Fill Level"
|
|
group.long 0xA8++0xB
|
|
line.long 0x0 "RXF0A,Receive FIFO 0 Acknowledge Register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F0AI,Receive FIFO 0 Acknowledge Index"
|
|
line.long 0x4 "RXBC,Receive Rx Buffer Configuration Register"
|
|
hexmask.long.word 0x4 2.--15. 1. "RBSA,Receive Buffer Start Address"
|
|
line.long 0x8 "RXF1C,Receive FIFO 1 Configuration Register"
|
|
bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0: FIFO 1 Blocking mode.,1: FIFO 1 Overwrite mode."
|
|
hexmask.long.byte 0x8 24.--30. 1. "F1WM,Receive FIFO 1 Watermark"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "F1S,Receive FIFO 1 Size"
|
|
hexmask.long.word 0x8 2.--15. 1. "F1SA,Receive FIFO 1 Start Address"
|
|
rgroup.long 0xB4++0x3
|
|
line.long 0x0 "RXF1S,Receive FIFO 1 Status Register"
|
|
bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0: Idle state wait for reception of debug messages..,1: Debug message A received.,2: Debug messages A B received.,3: Debug messages A B C received DMA request is set."
|
|
bitfld.long 0x0 25. "RF1L,Receive FIFO 1 Message Lost" "0: No Receive FIFO 1 message lost.,1: Receive FIFO 1 message lost also set after write.."
|
|
newline
|
|
bitfld.long 0x0 24. "F1F,Receive FIFO 1 Full" "0: Receive FIFO 1 not full.,1: Receive FIFO 1 full."
|
|
hexmask.long.byte 0x0 16.--21. 1. "F1PI,Receive FIFO 1 Put Index"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "F1GI,Receive FIFO 1 Get Index"
|
|
hexmask.long.byte 0x0 0.--6. 1. "F1FL,Receive FIFO 1 Fill Level"
|
|
group.long 0xB8++0xB
|
|
line.long 0x0 "RXF1A,Receive FIFO 1 Acknowledge Register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Receive FIFO 1 Acknowledge Index"
|
|
line.long 0x4 "RXESC,Receive Buffer / FIFO Element Size Configuration Register"
|
|
bitfld.long 0x4 8.--10. "RBDS,Receive Buffer Data Field Size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field"
|
|
bitfld.long 0x4 4.--6. "F1DS,Receive FIFO 1 Data Field Size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "F0DS,Receive FIFO 0 Data Field Size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field"
|
|
line.long 0x8 "TXBC,Transmit Buffer Configuration Register"
|
|
bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation.,1: Tx Queue operation."
|
|
hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers"
|
|
hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address"
|
|
rgroup.long 0xC4++0x3
|
|
line.long 0x0 "TXFQS,Transmit FIFO/Queue Status Register"
|
|
bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full.,1: Tx FIFO/Queue full."
|
|
hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index"
|
|
hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level"
|
|
group.long 0xC8++0x3
|
|
line.long 0x0 "TXESC,Transmit Buffer Element Size Configuration Register"
|
|
bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48- byte data field,7: 64-byte data field"
|
|
rgroup.long 0xCC++0x3
|
|
line.long 0x0 "TXBRP,Transmit Buffer Request Pending Register"
|
|
bitfld.long 0x0 31. "TRP31,Transmission Request Pending for Buffer 31" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 30. "TRP30,Transmission Request Pending for Buffer 30" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 29. "TRP29,Transmission Request Pending for Buffer 29" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 28. "TRP28,Transmission Request Pending for Buffer 28" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 27. "TRP27,Transmission Request Pending for Buffer 27" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 26. "TRP26,Transmission Request Pending for Buffer 26" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 25. "TRP25,Transmission Request Pending for Buffer 25" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 24. "TRP24,Transmission Request Pending for Buffer 24" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 23. "TRP23,Transmission Request Pending for Buffer 23" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 22. "TRP22,Transmission Request Pending for Buffer 22" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 21. "TRP21,Transmission Request Pending for Buffer 21" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 20. "TRP20,Transmission Request Pending for Buffer 20" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 19. "TRP19,Transmission Request Pending for Buffer 19" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 18. "TRP18,Transmission Request Pending for Buffer 18" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 17. "TRP17,Transmission Request Pending for Buffer 17" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 16. "TRP16,Transmission Request Pending for Buffer 16" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 15. "TRP15,Transmission Request Pending for Buffer 15" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 14. "TRP14,Transmission Request Pending for Buffer 14" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 13. "TRP13,Transmission Request Pending for Buffer 13" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 12. "TRP12,Transmission Request Pending for Buffer 12" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 11. "TRP11,Transmission Request Pending for Buffer 11" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 10. "TRP10,Transmission Request Pending for Buffer 10" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 9. "TRP9,Transmission Request Pending for Buffer 9" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 8. "TRP8,Transmission Request Pending for Buffer 8" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 7. "TRP7,Transmission Request Pending for Buffer 7" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 6. "TRP6,Transmission Request Pending for Buffer 6" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 5. "TRP5,Transmission Request Pending for Buffer 5" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 4. "TRP4,Transmission Request Pending for Buffer 4" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 3. "TRP3,Transmission Request Pending for Buffer 3" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 2. "TRP2,Transmission Request Pending for Buffer 2" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 1. "TRP1,Transmission Request Pending for Buffer 1" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 0. "TRP0,Transmission Request Pending for Buffer 0" "0: No transmission request pending,1: Transmission request pending"
|
|
group.long 0xD0++0x7
|
|
line.long 0x0 "TXBAR,Transmit Buffer Add Request Register"
|
|
bitfld.long 0x0 31. "AR31,Add Request for Transmit Buffer 31" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 30. "AR30,Add Request for Transmit Buffer 30" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 29. "AR29,Add Request for Transmit Buffer 29" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 28. "AR28,Add Request for Transmit Buffer 28" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 27. "AR27,Add Request for Transmit Buffer 27" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 26. "AR26,Add Request for Transmit Buffer 26" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 25. "AR25,Add Request for Transmit Buffer 25" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 24. "AR24,Add Request for Transmit Buffer 24" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 23. "AR23,Add Request for Transmit Buffer 23" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 22. "AR22,Add Request for Transmit Buffer 22" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 21. "AR21,Add Request for Transmit Buffer 21" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 20. "AR20,Add Request for Transmit Buffer 20" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 19. "AR19,Add Request for Transmit Buffer 19" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 18. "AR18,Add Request for Transmit Buffer 18" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 17. "AR17,Add Request for Transmit Buffer 17" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 16. "AR16,Add Request for Transmit Buffer 16" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 15. "AR15,Add Request for Transmit Buffer 15" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 14. "AR14,Add Request for Transmit Buffer 14" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 13. "AR13,Add Request for Transmit Buffer 13" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 12. "AR12,Add Request for Transmit Buffer 12" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 11. "AR11,Add Request for Transmit Buffer 11" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 10. "AR10,Add Request for Transmit Buffer 10" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 9. "AR9,Add Request for Transmit Buffer 9" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 8. "AR8,Add Request for Transmit Buffer 8" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 7. "AR7,Add Request for Transmit Buffer 7" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 6. "AR6,Add Request for Transmit Buffer 6" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 5. "AR5,Add Request for Transmit Buffer 5" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 4. "AR4,Add Request for Transmit Buffer 4" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 3. "AR3,Add Request for Transmit Buffer 3" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 2. "AR2,Add Request for Transmit Buffer 2" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 1. "AR1,Add Request for Transmit Buffer 1" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 0. "AR0,Add Request for Transmit Buffer 0" "0: No transmission request added.,1: Transmission requested added."
|
|
line.long 0x4 "TXBCR,Transmit Buffer Cancellation Request Register"
|
|
bitfld.long 0x4 31. "CR31,Cancellation Request for Transmit Buffer 31" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 30. "CR30,Cancellation Request for Transmit Buffer 30" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 29. "CR29,Cancellation Request for Transmit Buffer 29" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 28. "CR28,Cancellation Request for Transmit Buffer 28" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 27. "CR27,Cancellation Request for Transmit Buffer 27" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 26. "CR26,Cancellation Request for Transmit Buffer 26" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 25. "CR25,Cancellation Request for Transmit Buffer 25" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 24. "CR24,Cancellation Request for Transmit Buffer 24" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 23. "CR23,Cancellation Request for Transmit Buffer 23" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 22. "CR22,Cancellation Request for Transmit Buffer 22" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 21. "CR21,Cancellation Request for Transmit Buffer 21" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 20. "CR20,Cancellation Request for Transmit Buffer 20" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 19. "CR19,Cancellation Request for Transmit Buffer 19" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 18. "CR18,Cancellation Request for Transmit Buffer 18" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 17. "CR17,Cancellation Request for Transmit Buffer 17" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 16. "CR16,Cancellation Request for Transmit Buffer 16" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 15. "CR15,Cancellation Request for Transmit Buffer 15" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 14. "CR14,Cancellation Request for Transmit Buffer 14" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 13. "CR13,Cancellation Request for Transmit Buffer 13" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 12. "CR12,Cancellation Request for Transmit Buffer 12" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 11. "CR11,Cancellation Request for Transmit Buffer 11" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 10. "CR10,Cancellation Request for Transmit Buffer 10" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 9. "CR9,Cancellation Request for Transmit Buffer 9" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 8. "CR8,Cancellation Request for Transmit Buffer 8" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 7. "CR7,Cancellation Request for Transmit Buffer 7" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 6. "CR6,Cancellation Request for Transmit Buffer 6" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 5. "CR5,Cancellation Request for Transmit Buffer 5" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 4. "CR4,Cancellation Request for Transmit Buffer 4" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 3. "CR3,Cancellation Request for Transmit Buffer 3" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 2. "CR2,Cancellation Request for Transmit Buffer 2" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 1. "CR1,Cancellation Request for Transmit Buffer 1" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 0. "CR0,Cancellation Request for Transmit Buffer 0" "0: No cancellation pending.,1: Cancellation pending."
|
|
rgroup.long 0xD8++0x7
|
|
line.long 0x0 "TXBTO,Transmit Buffer Transmission Occurred Register"
|
|
bitfld.long 0x0 31. "TO31,Transmission Occurred for Buffer 31" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 30. "TO30,Transmission Occurred for Buffer 30" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 29. "TO29,Transmission Occurred for Buffer 29" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 28. "TO28,Transmission Occurred for Buffer 28" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 27. "TO27,Transmission Occurred for Buffer 27" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 26. "TO26,Transmission Occurred for Buffer 26" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 25. "TO25,Transmission Occurred for Buffer 25" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 24. "TO24,Transmission Occurred for Buffer 24" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 23. "TO23,Transmission Occurred for Buffer 23" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 22. "TO22,Transmission Occurred for Buffer 22" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 21. "TO21,Transmission Occurred for Buffer 21" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 20. "TO20,Transmission Occurred for Buffer 20" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 19. "TO19,Transmission Occurred for Buffer 19" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 18. "TO18,Transmission Occurred for Buffer 18" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 17. "TO17,Transmission Occurred for Buffer 17" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 16. "TO16,Transmission Occurred for Buffer 16" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 15. "TO15,Transmission Occurred for Buffer 15" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 14. "TO14,Transmission Occurred for Buffer 14" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 13. "TO13,Transmission Occurred for Buffer 13" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 12. "TO12,Transmission Occurred for Buffer 12" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 11. "TO11,Transmission Occurred for Buffer 11" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 10. "TO10,Transmission Occurred for Buffer 10" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 9. "TO9,Transmission Occurred for Buffer 9" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 8. "TO8,Transmission Occurred for Buffer 8" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 7. "TO7,Transmission Occurred for Buffer 7" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 6. "TO6,Transmission Occurred for Buffer 6" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 5. "TO5,Transmission Occurred for Buffer 5" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 4. "TO4,Transmission Occurred for Buffer 4" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 3. "TO3,Transmission Occurred for Buffer 3" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 2. "TO2,Transmission Occurred for Buffer 2" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 1. "TO1,Transmission Occurred for Buffer 1" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 0. "TO0,Transmission Occurred for Buffer 0" "0: No transmission occurred.,1: Transmission occurred."
|
|
line.long 0x4 "TXBCF,Transmit Buffer Cancellation Finished Register"
|
|
bitfld.long 0x4 31. "CF31,Cancellation Finished for Transmit Buffer 31" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 30. "CF30,Cancellation Finished for Transmit Buffer 30" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 29. "CF29,Cancellation Finished for Transmit Buffer 29" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 28. "CF28,Cancellation Finished for Transmit Buffer 28" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 27. "CF27,Cancellation Finished for Transmit Buffer 27" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 26. "CF26,Cancellation Finished for Transmit Buffer 26" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 25. "CF25,Cancellation Finished for Transmit Buffer 25" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 24. "CF24,Cancellation Finished for Transmit Buffer 24" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 23. "CF23,Cancellation Finished for Transmit Buffer 23" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 22. "CF22,Cancellation Finished for Transmit Buffer 22" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 21. "CF21,Cancellation Finished for Transmit Buffer 21" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 20. "CF20,Cancellation Finished for Transmit Buffer 20" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 19. "CF19,Cancellation Finished for Transmit Buffer 19" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 18. "CF18,Cancellation Finished for Transmit Buffer 18" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 17. "CF17,Cancellation Finished for Transmit Buffer 17" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 16. "CF16,Cancellation Finished for Transmit Buffer 16" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 15. "CF15,Cancellation Finished for Transmit Buffer 15" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 14. "CF14,Cancellation Finished for Transmit Buffer 14" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 13. "CF13,Cancellation Finished for Transmit Buffer 13" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 12. "CF12,Cancellation Finished for Transmit Buffer 12" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 11. "CF11,Cancellation Finished for Transmit Buffer 11" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 10. "CF10,Cancellation Finished for Transmit Buffer 10" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 9. "CF9,Cancellation Finished for Transmit Buffer 9" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 8. "CF8,Cancellation Finished for Transmit Buffer 8" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 7. "CF7,Cancellation Finished for Transmit Buffer 7" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 6. "CF6,Cancellation Finished for Transmit Buffer 6" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 5. "CF5,Cancellation Finished for Transmit Buffer 5" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 4. "CF4,Cancellation Finished for Transmit Buffer 4" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 3. "CF3,Cancellation Finished for Transmit Buffer 3" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 2. "CF2,Cancellation Finished for Transmit Buffer 2" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 1. "CF1,Cancellation Finished for Transmit Buffer 1" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 0. "CF0,Cancellation Finished for Transmit Buffer 0" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
group.long 0xE0++0x7
|
|
line.long 0x0 "TXBTIE,Transmit Buffer Transmission Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable for Buffer 31" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable for Buffer 30" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable for Buffer 29" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable for Buffer 28" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable for Buffer 27" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable for Buffer 26" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable for Buffer 25" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable for Buffer 24" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable for Buffer 23" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable for Buffer 22" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable for Buffer 21" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable for Buffer 20" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable for Buffer 19" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable for Buffer 18" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable for Buffer 17" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable for Buffer 16" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable for Buffer 15" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable for Buffer 14" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable for Buffer 13" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable for Buffer 12" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable for Buffer 11" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable for Buffer 10" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable for Buffer 9" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable for Buffer 8" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable for Buffer 7" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable for Buffer 6" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable for Buffer 5" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable for Buffer 4" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable for Buffer 3" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable for Buffer 2" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
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bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable for Buffer 1" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable for Buffer 0" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
line.long 0x4 "TXBCIE,Transmit Buffer Cancellation Finished Interrupt Enable Register"
|
|
bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable for Transmit Buffer 31" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable for Transmit Buffer 30" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
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bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable for Transmit Buffer 29" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable for Transmit Buffer 28" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
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bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable for Transmit Buffer 27" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable for Transmit Buffer 26" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
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bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable for Transmit Buffer 25" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable for Transmit Buffer 24" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
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bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable for Transmit Buffer 23" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable for Transmit Buffer 22" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
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bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable for Transmit Buffer 21" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable for Transmit Buffer 20" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
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bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable for Transmit Buffer 19" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable for Transmit Buffer 18" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
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bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable for Transmit Buffer 17" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable for Transmit Buffer 16" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
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bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable for Transmit Buffer 15" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable for Transmit Buffer 14" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable for Transmit Buffer 13" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable for Transmit Buffer 12" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable for Transmit Buffer 11" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable for Transmit Buffer 10" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable for Transmit Buffer 9" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable for Transmit Buffer 8" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable for Transmit Buffer 7" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable for Transmit Buffer 6" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable for Transmit Buffer 5" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable for Transmit Buffer 4" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable for Transmit Buffer 3" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable for Transmit Buffer 2" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable for Transmit Buffer 1" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable for Transmit Buffer 0" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
group.long 0xF0++0x3
|
|
line.long 0x0 "TXEFC,Transmit Event FIFO Configuration Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark"
|
|
hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size"
|
|
newline
|
|
hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address"
|
|
rgroup.long 0xF4++0x3
|
|
line.long 0x0 "TXEFS,Transmit Event FIFO Status Register"
|
|
bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.."
|
|
bitfld.long 0x0 24. "EFF,Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index"
|
|
hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level"
|
|
group.long 0xF8++0x3
|
|
line.long 0x0 "TXEFA,Transmit Event FIFO Acknowledge Register"
|
|
hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index"
|
|
tree.end
|
|
tree "MCAN3"
|
|
base ad:0xE0834000
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "ENDN,Endian Register"
|
|
hexmask.long 0x0 0.--31. 1. "ETV,Endianness Test Value"
|
|
group.long 0x8++0x27
|
|
line.long 0x0 "CUST,Customer Register"
|
|
hexmask.long 0x0 0.--31. 1. "CSV,Customer-specific Value"
|
|
line.long 0x4 "DBTP,Data Bit Timing and Prescaler Register"
|
|
bitfld.long 0x4 23. "TDC,Transmitter Delay Compensation" "0: Transmitter Delay Compensation disabled.,1: Transmitter Delay Compensation enabled."
|
|
hexmask.long.byte 0x4 16.--20. 1. "DBRP,Data Bit Rate Prescaler"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--12. 1. "DTSEG1,Data Time Segment Before Sample Point"
|
|
hexmask.long.byte 0x4 4.--7. 1. "DTSEG2,Data Time Segment After Sample Point"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "DSJW,Data (Re) Synchronization Jump Width" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "TEST,Test Register"
|
|
bitfld.long 0x8 7. "RX,Receive Pin (read-only)" "0: The CAN bus is dominant (CANRX = '0').,1: The CAN bus is recessive (CANRX = '1')."
|
|
bitfld.long 0x8 5.--6. "TX,Control of Transmit Pin (read/write)" "0: Reset value CANTX controlled by the CAN Core..,1: Sample Point can be monitored at pin CANTX.,2: Dominant ('0') level at pin CANTX.,3: Recessive ('1') at pin CANTX."
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|
newline
|
|
bitfld.long 0x8 4. "LBCK,Loop Back Mode (read/write)" "0: Reset value. Loop Back mode is disabled.,1: Loop Back mode is enabled (see Section 6.1.9.."
|
|
line.long 0xC "RWD,RAM Watchdog Register"
|
|
hexmask.long.byte 0xC 8.--15. 1. "WDV,Watchdog Value (read-only)"
|
|
hexmask.long.byte 0xC 0.--7. 1. "WDC,Watchdog Configuration (read/write)"
|
|
line.long 0x10 "CCCR,CC Control Register"
|
|
bitfld.long 0x10 15. "NISO,Non-ISO Operation" "0: CAN FD frame format according to ISO11898-1..,1: CAN FD frame format according to Bosch CAN FD.."
|
|
bitfld.long 0x10 14. "TXP,Transmit Pause (read/write write protection)" "0: Transmit pause disabled.,1: Transmit pause enabled."
|
|
newline
|
|
bitfld.long 0x10 13. "EFBI,Edge Filtering during Bus Integration (read/write write protection)" "0: Edge filtering is disabled.,1: Edge filtering is enabled. Two consecutive.."
|
|
bitfld.long 0x10 12. "PXHD,Protocol Exception Event Handling (read/write write protection)" "0: Protocol exception handling enabled.,1: Protocol exception handling disabled."
|
|
newline
|
|
bitfld.long 0x10 9. "BRSE,Bit Rate Switching Enable (read/write write protection)" "0: Bit rate switching for transmissions disabled.,1: Bit rate switching for transmissions enabled."
|
|
bitfld.long 0x10 8. "FDOE,CAN FD Operation Enable (read/write write protection)" "0: FD operation disabled.,1: FD operation enabled."
|
|
newline
|
|
bitfld.long 0x10 7. "TEST,Test Mode Enable (read/write write protection against '1')" "0: Normal operation MCAN_TEST register holds reset..,1: Test mode write access to MCAN_TEST register.."
|
|
bitfld.long 0x10 6. "DAR,Disable Automatic Retransmission (read/write write protection)" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled."
|
|
newline
|
|
bitfld.long 0x10 5. "MON,Bus Monitoring Mode (read/write write protection against '1')" "0: Bus Monitoring mode is disabled.,1: Bus Monitoring mode is enabled."
|
|
bitfld.long 0x10 4. "CSR,Clock Stop Request (read/write)" "0: No clock stop is requested.,1: Clock stop requested. When clock stop is.."
|
|
newline
|
|
bitfld.long 0x10 3. "CSA,Clock Stop Acknowledge (read-only)" "0: No clock stop acknowledged.,1: MCAN may be set in power down by stopping the.."
|
|
bitfld.long 0x10 2. "ASM,Restricted Operation Mode (read/write write protection against '1')" "0: Normal CAN operation.,1: Restricted Operation mode active."
|
|
newline
|
|
bitfld.long 0x10 1. "CCE,Configuration Change Enable (read/write write protection)" "0: The processor has no write access to the..,1: The processor has write access to the protected.."
|
|
bitfld.long 0x10 0. "INIT,Initialization (read/write)" "0: Normal operation.,1: Initialization is started."
|
|
line.long 0x14 "NBTP,Nominal Bit Timing and Prescaler Register"
|
|
hexmask.long.byte 0x14 25.--31. 1. "NSJW,Nominal (Re) Synchronization Jump Width"
|
|
hexmask.long.word 0x14 16.--24. 1. "NBRP,Nominal Bit Rate Prescaler"
|
|
newline
|
|
hexmask.long.byte 0x14 8.--15. 1. "NTSEG1,Nominal Time Segment Before Sample Point"
|
|
hexmask.long.byte 0x14 0.--6. 1. "NTSEG2,Nominal Time Segment After Sample Point"
|
|
line.long 0x18 "TSCC,Timestamp Counter Configuration Register"
|
|
hexmask.long.byte 0x18 16.--19. 1. "TCP,Timestamp Counter Prescaler"
|
|
bitfld.long 0x18 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter value used,3: Timestamp counter value always 0x0000"
|
|
line.long 0x1C "TSCV,Timestamp Counter Value Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. "TSC,Timestamp Counter (cleared on write)"
|
|
line.long 0x20 "TOCC,Timeout Counter Configuration Register"
|
|
hexmask.long.word 0x20 16.--31. 1. "TOP,Timeout Period"
|
|
bitfld.long 0x20 1.--2. "TOS,Timeout Select" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,2: Timeout controlled by Receive FIFO 0,3: Timeout controlled by Receive FIFO 1"
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|
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bitfld.long 0x20 0. "ETOC,Enable Timeout Counter" "0: Timeout Counter disabled.,1: Timeout Counter enabled."
|
|
line.long 0x24 "TOCV,Timeout Counter Value Register"
|
|
hexmask.long.word 0x24 0.--15. 1. "TOC,Timeout Counter (cleared on write)"
|
|
rgroup.long 0x40++0x7
|
|
line.long 0x0 "ECR,Error Counter Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging (cleared on read)"
|
|
bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.."
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|
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|
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hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter"
|
|
line.long 0x4 "PSR,Protocol Status Register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value"
|
|
bitfld.long 0x4 14. "PXE,Protocol Exception Event (cleared on read)" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
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bitfld.long 0x4 13. "RFDF,Received a CAN FD Message (cleared on read)" "0: Since this bit was reset by the CPU no CAN FD..,1: Message in CAN FD format with FDF flag set has.."
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|
bitfld.long 0x4 12. "RBRS,BRS Flag of Last Received CAN FD Message (cleared on read)" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set."
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bitfld.long 0x4 11. "RESI,ESI Flag of Last Received CAN FD Message (cleared on read)" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set."
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bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code (set to 111 on read)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The MCAN is not Bus_Off.,1: The MCAN is in Bus_Off state."
|
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bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
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bitfld.long 0x4 5. "EP,Error Passive" "0: The MCAN is in the Error_Active state. It..,1: The MCAN is in the Error_Passive state."
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|
bitfld.long 0x4 3.--4. "ACT,Activity" "0: Node is synchronizing on CAN communication,1: Node is neither receiver nor transmitter,2: Node is operating as receiver,3: Node is operating as transmitter"
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bitfld.long 0x4 0.--2. "LEC,Last Error Code (set to 111 on read)" "0: No error occurred since LEC has been reset by..,1: More than 5 equal bits in a sequence have..,2: A fixed format part of a received frame has the..,3: The message transmitted by the MCAN was not..,4: During transmission of a message (with the..,5: During transmission of a message (or acknowledge..,6: The CRC check sum of a received message was..,7: Any read access to the Protocol Status Register.."
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|
group.long 0x48++0x3
|
|
line.long 0x0 "TDCR,Transmit Delay Compensation Register"
|
|
hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset"
|
|
hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter"
|
|
group.long 0x50++0xF
|
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line.long 0x0 "IR,Interrupt Register"
|
|
bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0: No access to reserved address occurred,1: Access to reserved address occurred"
|
|
bitfld.long 0x0 28. "PED,Protocol Error in Data Phase" "0: No protocol error in data phase,1: Protocol error in data phase detected.."
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bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.."
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|
bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred.,1: Message RAM Watchdog event due to missing READY."
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|
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bitfld.long 0x0 25. "BO,Bus_Off Status" "0: Bus_Off status unchanged.,1: Bus_Off status changed."
|
|
bitfld.long 0x0 24. "EW,Warning Status" "0: Error_Warning status unchanged.,1: Error_Warning status changed."
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bitfld.long 0x0 23. "EP,Error Passive" "0: Error_Passive status unchanged.,1: Error_Passive status changed."
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|
bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0: CAN Error Logging Counter did not overflow.,1: Overflow of CAN Error Logging Counter occurred."
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bitfld.long 0x0 19. "DRX,Message stored to Dedicated Receive Buffer" "0: No Receive Buffer updated.,1: At least one received message stored into a.."
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|
bitfld.long 0x0 18. "TOO,Timeout Occurred" "0: No timeout.,1: Timeout reached."
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bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0: No Message RAM access failure occurred.,1: Message RAM access failure occurred."
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|
bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around.,1: Timestamp counter wrapped around."
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|
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bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost.,1: Tx Event FIFO element lost also set after write.."
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|
bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0: Tx Event FIFO not full.,1: Tx Event FIFO full."
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bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO fill level below watermark.,1: Tx Event FIFO fill level reached watermark."
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|
bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0: Tx Event FIFO unchanged.,1: Tx Handler wrote Tx Event FIFO element."
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bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty.,1: Tx FIFO empty."
|
|
bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished.,1: Transmission cancellation finished."
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|
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bitfld.long 0x0 9. "TC,Transmission Completed" "0: No transmission completed.,1: Transmission completed."
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|
bitfld.long 0x0 8. "HPM,High Priority Message" "0: No high priority message received.,1: High priority message received."
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bitfld.long 0x0 7. "RF1L,Receive FIFO 1 Message Lost" "0: No Receive FIFO 1 message lost.,1: Receive FIFO 1 message lost also set after write.."
|
|
bitfld.long 0x0 6. "RF1F,Receive FIFO 1 Full" "0: Receive FIFO 1 not full.,1: Receive FIFO 1 full."
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bitfld.long 0x0 5. "RF1W,Receive FIFO 1 Watermark Reached" "0: Receive FIFO 1 fill level below watermark.,1: Receive FIFO 1 fill level reached watermark."
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bitfld.long 0x0 4. "RF1N,Receive FIFO 1 New Message" "0: No new message written to Receive FIFO 1.,1: New message written to Receive FIFO 1."
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newline
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bitfld.long 0x0 3. "RF0L,Receive FIFO 0 Message Lost" "0: No Receive FIFO 0 message lost.,1: Receive FIFO 0 message lost also set after write.."
|
|
bitfld.long 0x0 2. "RF0F,Receive FIFO 0 Full" "0: Receive FIFO 0 not full.,1: Receive FIFO 0 full."
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newline
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bitfld.long 0x0 1. "RF0W,Receive FIFO 0 Watermark Reached" "0: Receive FIFO 0 fill level below watermark.,1: Receive FIFO 0 fill level reached watermark."
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|
bitfld.long 0x0 0. "RF0N,Receive FIFO 0 New Message" "0: No new message written to Receive FIFO 0.,1: New message written to Receive FIFO 0."
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|
line.long 0x4 "IE,Interrupt Enable Register"
|
|
bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0,1"
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|
bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0,1"
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newline
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bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0,1"
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|
bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0,1"
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|
bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Receive Buffer Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1"
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|
newline
|
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bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0,1"
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|
bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x4 7. "RF1LE,Receive FIFO 1 Message Lost Interrupt Enable" "0,1"
|
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bitfld.long 0x4 6. "RF1FE,Receive FIFO 1 Full Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x4 5. "RF1WE,Receive FIFO 1 Watermark Reached Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 4. "RF1NE,Receive FIFO 1 New Message Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x4 3. "RF0LE,Receive FIFO 0 Message Lost Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 2. "RF0FE,Receive FIFO 0 Full Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x4 1. "RF0WE,Receive FIFO 0 Watermark Reached Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 0. "RF0NE,Receive FIFO 0 New Message Interrupt Enable" "0,1"
|
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line.long 0x8 "ILS,Interrupt Line Select Register"
|
|
bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0,1"
|
|
bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0,1"
|
|
newline
|
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bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0,1"
|
|
bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0,1"
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newline
|
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bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0,1"
|
|
bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0,1"
|
|
bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Receive Buffer Interrupt Line" "0,1"
|
|
bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1"
|
|
bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1"
|
|
bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0,1"
|
|
bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0x8 7. "RF1LL,Receive FIFO 1 Message Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 6. "RF1FL,Receive FIFO 1 Full Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0x8 5. "RF1WL,Receive FIFO 1 Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 4. "RF1NL,Receive FIFO 1 New Message Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0x8 3. "RF0LL,Receive FIFO 0 Message Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 2. "RF0FL,Receive FIFO 0 Full Interrupt Line" "0,1"
|
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newline
|
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bitfld.long 0x8 1. "RF0WL,Receive FIFO 0 Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 0. "RF0NL,Receive FIFO 0 New Message Interrupt Line" "0,1"
|
|
line.long 0xC "ILE,Interrupt Line Enable Register"
|
|
bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line MCAN_INT1 disabled.,1: Interrupt line MCAN_INT1 enabled."
|
|
bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line MCAN_INT0 disabled.,1: Interrupt line MCAN_INT0 enabled."
|
|
group.long 0x80++0xB
|
|
line.long 0x0 "GFC,Global Filter Configuration Register"
|
|
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
|
|
bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
|
|
newline
|
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bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs.,1: Reject all remote frames with 11-bit standard IDs."
|
|
bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs.,1: Reject all remote frames with 29-bit extended IDs."
|
|
line.long 0x4 "SIDFC,Standard ID Filter Configuration Register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard"
|
|
hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address"
|
|
line.long 0x8 "XIDFC,Extended ID Filter Configuration Register"
|
|
hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended"
|
|
hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address"
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "XIDAM,Extended ID AND Mask Register"
|
|
hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask"
|
|
rgroup.long 0x94++0x3
|
|
line.long 0x0 "HPMS,High Priority Message Status Register"
|
|
bitfld.long 0x0 15. "FLST,Filter List" "0: Standard filter list,1: Extended filter list"
|
|
hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected.,1: FIFO message lost.,2: Message stored in FIFO 0.,3: Message stored in FIFO 1."
|
|
hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index"
|
|
group.long 0x98++0xB
|
|
line.long 0x0 "NDAT1,New Data 1 Register"
|
|
bitfld.long 0x0 31. "ND31,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 30. "ND30,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
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bitfld.long 0x0 29. "ND29,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 28. "ND28,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
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bitfld.long 0x0 27. "ND27,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 26. "ND26,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
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bitfld.long 0x0 25. "ND25,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 24. "ND24,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
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bitfld.long 0x0 23. "ND23,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 22. "ND22,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
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bitfld.long 0x0 21. "ND21,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 20. "ND20,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 19. "ND19,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 18. "ND18,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 17. "ND17,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 16. "ND16,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 15. "ND15,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 14. "ND14,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 13. "ND13,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 12. "ND12,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 11. "ND11,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 10. "ND10,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 9. "ND9,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 8. "ND8,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 7. "ND7,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 6. "ND6,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 5. "ND5,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 4. "ND4,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 3. "ND3,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 2. "ND2,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 1. "ND1,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 0. "ND0,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
line.long 0x4 "NDAT2,New Data 2 Register"
|
|
bitfld.long 0x4 31. "ND63,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 30. "ND62,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 29. "ND61,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 28. "ND60,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 27. "ND59,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 26. "ND58,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 25. "ND57,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 24. "ND56,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 23. "ND55,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 22. "ND54,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 21. "ND53,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 20. "ND52,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 19. "ND51,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 18. "ND50,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 17. "ND49,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 16. "ND48,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 15. "ND47,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 14. "ND46,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 13. "ND45,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 12. "ND44,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 11. "ND43,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 10. "ND42,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 9. "ND41,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 8. "ND40,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 7. "ND39,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 6. "ND38,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 5. "ND37,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 4. "ND36,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 3. "ND35,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 2. "ND34,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 1. "ND33,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 0. "ND32,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
line.long 0x8 "RXF0C,Receive FIFO 0 Configuration Register"
|
|
bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0: FIFO 0 Blocking mode.,1: FIFO 0 Overwrite mode."
|
|
hexmask.long.byte 0x8 24.--30. 1. "F0WM,Receive FIFO 0 Watermark"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "F0S,Receive FIFO 0 Size"
|
|
hexmask.long.word 0x8 2.--15. 1. "F0SA,Receive FIFO 0 Start Address"
|
|
rgroup.long 0xA4++0x3
|
|
line.long 0x0 "RXF0S,Receive FIFO 0 Status Register"
|
|
bitfld.long 0x0 25. "RF0L,Receive FIFO 0 Message Lost" "0: No Receive FIFO 0 message lost,1: Receive FIFO 0 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F0F,Receive FIFO 0 Full" "0: Receive FIFO 0 not full.,1: Receive FIFO 0 full."
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "F0PI,Receive FIFO 0 Put Index"
|
|
hexmask.long.byte 0x0 8.--13. 1. "F0GI,Receive FIFO 0 Get Index"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "F0FL,Receive FIFO 0 Fill Level"
|
|
group.long 0xA8++0xB
|
|
line.long 0x0 "RXF0A,Receive FIFO 0 Acknowledge Register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F0AI,Receive FIFO 0 Acknowledge Index"
|
|
line.long 0x4 "RXBC,Receive Rx Buffer Configuration Register"
|
|
hexmask.long.word 0x4 2.--15. 1. "RBSA,Receive Buffer Start Address"
|
|
line.long 0x8 "RXF1C,Receive FIFO 1 Configuration Register"
|
|
bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0: FIFO 1 Blocking mode.,1: FIFO 1 Overwrite mode."
|
|
hexmask.long.byte 0x8 24.--30. 1. "F1WM,Receive FIFO 1 Watermark"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "F1S,Receive FIFO 1 Size"
|
|
hexmask.long.word 0x8 2.--15. 1. "F1SA,Receive FIFO 1 Start Address"
|
|
rgroup.long 0xB4++0x3
|
|
line.long 0x0 "RXF1S,Receive FIFO 1 Status Register"
|
|
bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0: Idle state wait for reception of debug messages..,1: Debug message A received.,2: Debug messages A B received.,3: Debug messages A B C received DMA request is set."
|
|
bitfld.long 0x0 25. "RF1L,Receive FIFO 1 Message Lost" "0: No Receive FIFO 1 message lost.,1: Receive FIFO 1 message lost also set after write.."
|
|
newline
|
|
bitfld.long 0x0 24. "F1F,Receive FIFO 1 Full" "0: Receive FIFO 1 not full.,1: Receive FIFO 1 full."
|
|
hexmask.long.byte 0x0 16.--21. 1. "F1PI,Receive FIFO 1 Put Index"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "F1GI,Receive FIFO 1 Get Index"
|
|
hexmask.long.byte 0x0 0.--6. 1. "F1FL,Receive FIFO 1 Fill Level"
|
|
group.long 0xB8++0xB
|
|
line.long 0x0 "RXF1A,Receive FIFO 1 Acknowledge Register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Receive FIFO 1 Acknowledge Index"
|
|
line.long 0x4 "RXESC,Receive Buffer / FIFO Element Size Configuration Register"
|
|
bitfld.long 0x4 8.--10. "RBDS,Receive Buffer Data Field Size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field"
|
|
bitfld.long 0x4 4.--6. "F1DS,Receive FIFO 1 Data Field Size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "F0DS,Receive FIFO 0 Data Field Size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field"
|
|
line.long 0x8 "TXBC,Transmit Buffer Configuration Register"
|
|
bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation.,1: Tx Queue operation."
|
|
hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers"
|
|
hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address"
|
|
rgroup.long 0xC4++0x3
|
|
line.long 0x0 "TXFQS,Transmit FIFO/Queue Status Register"
|
|
bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full.,1: Tx FIFO/Queue full."
|
|
hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index"
|
|
hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level"
|
|
group.long 0xC8++0x3
|
|
line.long 0x0 "TXESC,Transmit Buffer Element Size Configuration Register"
|
|
bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48- byte data field,7: 64-byte data field"
|
|
rgroup.long 0xCC++0x3
|
|
line.long 0x0 "TXBRP,Transmit Buffer Request Pending Register"
|
|
bitfld.long 0x0 31. "TRP31,Transmission Request Pending for Buffer 31" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 30. "TRP30,Transmission Request Pending for Buffer 30" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 29. "TRP29,Transmission Request Pending for Buffer 29" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 28. "TRP28,Transmission Request Pending for Buffer 28" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 27. "TRP27,Transmission Request Pending for Buffer 27" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 26. "TRP26,Transmission Request Pending for Buffer 26" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 25. "TRP25,Transmission Request Pending for Buffer 25" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 24. "TRP24,Transmission Request Pending for Buffer 24" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 23. "TRP23,Transmission Request Pending for Buffer 23" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 22. "TRP22,Transmission Request Pending for Buffer 22" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 21. "TRP21,Transmission Request Pending for Buffer 21" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 20. "TRP20,Transmission Request Pending for Buffer 20" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 19. "TRP19,Transmission Request Pending for Buffer 19" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 18. "TRP18,Transmission Request Pending for Buffer 18" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 17. "TRP17,Transmission Request Pending for Buffer 17" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 16. "TRP16,Transmission Request Pending for Buffer 16" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 15. "TRP15,Transmission Request Pending for Buffer 15" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 14. "TRP14,Transmission Request Pending for Buffer 14" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 13. "TRP13,Transmission Request Pending for Buffer 13" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 12. "TRP12,Transmission Request Pending for Buffer 12" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 11. "TRP11,Transmission Request Pending for Buffer 11" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 10. "TRP10,Transmission Request Pending for Buffer 10" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 9. "TRP9,Transmission Request Pending for Buffer 9" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 8. "TRP8,Transmission Request Pending for Buffer 8" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 7. "TRP7,Transmission Request Pending for Buffer 7" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 6. "TRP6,Transmission Request Pending for Buffer 6" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 5. "TRP5,Transmission Request Pending for Buffer 5" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 4. "TRP4,Transmission Request Pending for Buffer 4" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 3. "TRP3,Transmission Request Pending for Buffer 3" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 2. "TRP2,Transmission Request Pending for Buffer 2" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 1. "TRP1,Transmission Request Pending for Buffer 1" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 0. "TRP0,Transmission Request Pending for Buffer 0" "0: No transmission request pending,1: Transmission request pending"
|
|
group.long 0xD0++0x7
|
|
line.long 0x0 "TXBAR,Transmit Buffer Add Request Register"
|
|
bitfld.long 0x0 31. "AR31,Add Request for Transmit Buffer 31" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 30. "AR30,Add Request for Transmit Buffer 30" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 29. "AR29,Add Request for Transmit Buffer 29" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 28. "AR28,Add Request for Transmit Buffer 28" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 27. "AR27,Add Request for Transmit Buffer 27" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 26. "AR26,Add Request for Transmit Buffer 26" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 25. "AR25,Add Request for Transmit Buffer 25" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 24. "AR24,Add Request for Transmit Buffer 24" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 23. "AR23,Add Request for Transmit Buffer 23" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 22. "AR22,Add Request for Transmit Buffer 22" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 21. "AR21,Add Request for Transmit Buffer 21" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 20. "AR20,Add Request for Transmit Buffer 20" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 19. "AR19,Add Request for Transmit Buffer 19" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 18. "AR18,Add Request for Transmit Buffer 18" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 17. "AR17,Add Request for Transmit Buffer 17" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 16. "AR16,Add Request for Transmit Buffer 16" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 15. "AR15,Add Request for Transmit Buffer 15" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 14. "AR14,Add Request for Transmit Buffer 14" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 13. "AR13,Add Request for Transmit Buffer 13" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 12. "AR12,Add Request for Transmit Buffer 12" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 11. "AR11,Add Request for Transmit Buffer 11" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 10. "AR10,Add Request for Transmit Buffer 10" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 9. "AR9,Add Request for Transmit Buffer 9" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 8. "AR8,Add Request for Transmit Buffer 8" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 7. "AR7,Add Request for Transmit Buffer 7" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 6. "AR6,Add Request for Transmit Buffer 6" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 5. "AR5,Add Request for Transmit Buffer 5" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 4. "AR4,Add Request for Transmit Buffer 4" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 3. "AR3,Add Request for Transmit Buffer 3" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 2. "AR2,Add Request for Transmit Buffer 2" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 1. "AR1,Add Request for Transmit Buffer 1" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 0. "AR0,Add Request for Transmit Buffer 0" "0: No transmission request added.,1: Transmission requested added."
|
|
line.long 0x4 "TXBCR,Transmit Buffer Cancellation Request Register"
|
|
bitfld.long 0x4 31. "CR31,Cancellation Request for Transmit Buffer 31" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 30. "CR30,Cancellation Request for Transmit Buffer 30" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 29. "CR29,Cancellation Request for Transmit Buffer 29" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 28. "CR28,Cancellation Request for Transmit Buffer 28" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 27. "CR27,Cancellation Request for Transmit Buffer 27" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 26. "CR26,Cancellation Request for Transmit Buffer 26" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 25. "CR25,Cancellation Request for Transmit Buffer 25" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 24. "CR24,Cancellation Request for Transmit Buffer 24" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 23. "CR23,Cancellation Request for Transmit Buffer 23" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 22. "CR22,Cancellation Request for Transmit Buffer 22" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 21. "CR21,Cancellation Request for Transmit Buffer 21" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 20. "CR20,Cancellation Request for Transmit Buffer 20" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 19. "CR19,Cancellation Request for Transmit Buffer 19" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 18. "CR18,Cancellation Request for Transmit Buffer 18" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 17. "CR17,Cancellation Request for Transmit Buffer 17" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 16. "CR16,Cancellation Request for Transmit Buffer 16" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 15. "CR15,Cancellation Request for Transmit Buffer 15" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 14. "CR14,Cancellation Request for Transmit Buffer 14" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 13. "CR13,Cancellation Request for Transmit Buffer 13" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 12. "CR12,Cancellation Request for Transmit Buffer 12" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 11. "CR11,Cancellation Request for Transmit Buffer 11" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 10. "CR10,Cancellation Request for Transmit Buffer 10" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 9. "CR9,Cancellation Request for Transmit Buffer 9" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 8. "CR8,Cancellation Request for Transmit Buffer 8" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 7. "CR7,Cancellation Request for Transmit Buffer 7" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 6. "CR6,Cancellation Request for Transmit Buffer 6" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 5. "CR5,Cancellation Request for Transmit Buffer 5" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 4. "CR4,Cancellation Request for Transmit Buffer 4" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 3. "CR3,Cancellation Request for Transmit Buffer 3" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 2. "CR2,Cancellation Request for Transmit Buffer 2" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 1. "CR1,Cancellation Request for Transmit Buffer 1" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 0. "CR0,Cancellation Request for Transmit Buffer 0" "0: No cancellation pending.,1: Cancellation pending."
|
|
rgroup.long 0xD8++0x7
|
|
line.long 0x0 "TXBTO,Transmit Buffer Transmission Occurred Register"
|
|
bitfld.long 0x0 31. "TO31,Transmission Occurred for Buffer 31" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 30. "TO30,Transmission Occurred for Buffer 30" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 29. "TO29,Transmission Occurred for Buffer 29" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 28. "TO28,Transmission Occurred for Buffer 28" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 27. "TO27,Transmission Occurred for Buffer 27" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 26. "TO26,Transmission Occurred for Buffer 26" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 25. "TO25,Transmission Occurred for Buffer 25" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 24. "TO24,Transmission Occurred for Buffer 24" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 23. "TO23,Transmission Occurred for Buffer 23" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 22. "TO22,Transmission Occurred for Buffer 22" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 21. "TO21,Transmission Occurred for Buffer 21" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 20. "TO20,Transmission Occurred for Buffer 20" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 19. "TO19,Transmission Occurred for Buffer 19" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 18. "TO18,Transmission Occurred for Buffer 18" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 17. "TO17,Transmission Occurred for Buffer 17" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 16. "TO16,Transmission Occurred for Buffer 16" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 15. "TO15,Transmission Occurred for Buffer 15" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 14. "TO14,Transmission Occurred for Buffer 14" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 13. "TO13,Transmission Occurred for Buffer 13" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 12. "TO12,Transmission Occurred for Buffer 12" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 11. "TO11,Transmission Occurred for Buffer 11" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 10. "TO10,Transmission Occurred for Buffer 10" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 9. "TO9,Transmission Occurred for Buffer 9" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 8. "TO8,Transmission Occurred for Buffer 8" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 7. "TO7,Transmission Occurred for Buffer 7" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 6. "TO6,Transmission Occurred for Buffer 6" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 5. "TO5,Transmission Occurred for Buffer 5" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 4. "TO4,Transmission Occurred for Buffer 4" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 3. "TO3,Transmission Occurred for Buffer 3" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 2. "TO2,Transmission Occurred for Buffer 2" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 1. "TO1,Transmission Occurred for Buffer 1" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 0. "TO0,Transmission Occurred for Buffer 0" "0: No transmission occurred.,1: Transmission occurred."
|
|
line.long 0x4 "TXBCF,Transmit Buffer Cancellation Finished Register"
|
|
bitfld.long 0x4 31. "CF31,Cancellation Finished for Transmit Buffer 31" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 30. "CF30,Cancellation Finished for Transmit Buffer 30" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 29. "CF29,Cancellation Finished for Transmit Buffer 29" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 28. "CF28,Cancellation Finished for Transmit Buffer 28" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 27. "CF27,Cancellation Finished for Transmit Buffer 27" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 26. "CF26,Cancellation Finished for Transmit Buffer 26" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 25. "CF25,Cancellation Finished for Transmit Buffer 25" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 24. "CF24,Cancellation Finished for Transmit Buffer 24" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 23. "CF23,Cancellation Finished for Transmit Buffer 23" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 22. "CF22,Cancellation Finished for Transmit Buffer 22" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 21. "CF21,Cancellation Finished for Transmit Buffer 21" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 20. "CF20,Cancellation Finished for Transmit Buffer 20" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 19. "CF19,Cancellation Finished for Transmit Buffer 19" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 18. "CF18,Cancellation Finished for Transmit Buffer 18" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 17. "CF17,Cancellation Finished for Transmit Buffer 17" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 16. "CF16,Cancellation Finished for Transmit Buffer 16" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 15. "CF15,Cancellation Finished for Transmit Buffer 15" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 14. "CF14,Cancellation Finished for Transmit Buffer 14" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 13. "CF13,Cancellation Finished for Transmit Buffer 13" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 12. "CF12,Cancellation Finished for Transmit Buffer 12" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 11. "CF11,Cancellation Finished for Transmit Buffer 11" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 10. "CF10,Cancellation Finished for Transmit Buffer 10" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 9. "CF9,Cancellation Finished for Transmit Buffer 9" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 8. "CF8,Cancellation Finished for Transmit Buffer 8" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 7. "CF7,Cancellation Finished for Transmit Buffer 7" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 6. "CF6,Cancellation Finished for Transmit Buffer 6" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 5. "CF5,Cancellation Finished for Transmit Buffer 5" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 4. "CF4,Cancellation Finished for Transmit Buffer 4" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 3. "CF3,Cancellation Finished for Transmit Buffer 3" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 2. "CF2,Cancellation Finished for Transmit Buffer 2" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 1. "CF1,Cancellation Finished for Transmit Buffer 1" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 0. "CF0,Cancellation Finished for Transmit Buffer 0" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
group.long 0xE0++0x7
|
|
line.long 0x0 "TXBTIE,Transmit Buffer Transmission Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable for Buffer 31" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable for Buffer 30" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable for Buffer 29" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable for Buffer 28" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable for Buffer 27" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable for Buffer 26" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable for Buffer 25" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable for Buffer 24" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable for Buffer 23" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable for Buffer 22" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable for Buffer 21" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable for Buffer 20" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable for Buffer 19" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable for Buffer 18" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable for Buffer 17" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable for Buffer 16" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable for Buffer 15" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable for Buffer 14" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable for Buffer 13" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable for Buffer 12" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable for Buffer 11" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable for Buffer 10" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable for Buffer 9" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable for Buffer 8" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable for Buffer 7" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable for Buffer 6" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable for Buffer 5" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable for Buffer 4" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable for Buffer 3" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable for Buffer 2" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable for Buffer 1" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable for Buffer 0" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
line.long 0x4 "TXBCIE,Transmit Buffer Cancellation Finished Interrupt Enable Register"
|
|
bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable for Transmit Buffer 31" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable for Transmit Buffer 30" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable for Transmit Buffer 29" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable for Transmit Buffer 28" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable for Transmit Buffer 27" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable for Transmit Buffer 26" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable for Transmit Buffer 25" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable for Transmit Buffer 24" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable for Transmit Buffer 23" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable for Transmit Buffer 22" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable for Transmit Buffer 21" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable for Transmit Buffer 20" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable for Transmit Buffer 19" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable for Transmit Buffer 18" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable for Transmit Buffer 17" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable for Transmit Buffer 16" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable for Transmit Buffer 15" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable for Transmit Buffer 14" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable for Transmit Buffer 13" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable for Transmit Buffer 12" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable for Transmit Buffer 11" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable for Transmit Buffer 10" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable for Transmit Buffer 9" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable for Transmit Buffer 8" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable for Transmit Buffer 7" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable for Transmit Buffer 6" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable for Transmit Buffer 5" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable for Transmit Buffer 4" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable for Transmit Buffer 3" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable for Transmit Buffer 2" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable for Transmit Buffer 1" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable for Transmit Buffer 0" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
group.long 0xF0++0x3
|
|
line.long 0x0 "TXEFC,Transmit Event FIFO Configuration Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark"
|
|
hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size"
|
|
newline
|
|
hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address"
|
|
rgroup.long 0xF4++0x3
|
|
line.long 0x0 "TXEFS,Transmit Event FIFO Status Register"
|
|
bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.."
|
|
bitfld.long 0x0 24. "EFF,Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index"
|
|
hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level"
|
|
group.long 0xF8++0x3
|
|
line.long 0x0 "TXEFA,Transmit Event FIFO Acknowledge Register"
|
|
hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index"
|
|
tree.end
|
|
tree "MCAN4"
|
|
base ad:0xE0838000
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "ENDN,Endian Register"
|
|
hexmask.long 0x0 0.--31. 1. "ETV,Endianness Test Value"
|
|
group.long 0x8++0x27
|
|
line.long 0x0 "CUST,Customer Register"
|
|
hexmask.long 0x0 0.--31. 1. "CSV,Customer-specific Value"
|
|
line.long 0x4 "DBTP,Data Bit Timing and Prescaler Register"
|
|
bitfld.long 0x4 23. "TDC,Transmitter Delay Compensation" "0: Transmitter Delay Compensation disabled.,1: Transmitter Delay Compensation enabled."
|
|
hexmask.long.byte 0x4 16.--20. 1. "DBRP,Data Bit Rate Prescaler"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--12. 1. "DTSEG1,Data Time Segment Before Sample Point"
|
|
hexmask.long.byte 0x4 4.--7. 1. "DTSEG2,Data Time Segment After Sample Point"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "DSJW,Data (Re) Synchronization Jump Width" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "TEST,Test Register"
|
|
bitfld.long 0x8 7. "RX,Receive Pin (read-only)" "0: The CAN bus is dominant (CANRX = '0').,1: The CAN bus is recessive (CANRX = '1')."
|
|
bitfld.long 0x8 5.--6. "TX,Control of Transmit Pin (read/write)" "0: Reset value CANTX controlled by the CAN Core..,1: Sample Point can be monitored at pin CANTX.,2: Dominant ('0') level at pin CANTX.,3: Recessive ('1') at pin CANTX."
|
|
newline
|
|
bitfld.long 0x8 4. "LBCK,Loop Back Mode (read/write)" "0: Reset value. Loop Back mode is disabled.,1: Loop Back mode is enabled (see Section 6.1.9.."
|
|
line.long 0xC "RWD,RAM Watchdog Register"
|
|
hexmask.long.byte 0xC 8.--15. 1. "WDV,Watchdog Value (read-only)"
|
|
hexmask.long.byte 0xC 0.--7. 1. "WDC,Watchdog Configuration (read/write)"
|
|
line.long 0x10 "CCCR,CC Control Register"
|
|
bitfld.long 0x10 15. "NISO,Non-ISO Operation" "0: CAN FD frame format according to ISO11898-1..,1: CAN FD frame format according to Bosch CAN FD.."
|
|
bitfld.long 0x10 14. "TXP,Transmit Pause (read/write write protection)" "0: Transmit pause disabled.,1: Transmit pause enabled."
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|
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bitfld.long 0x10 13. "EFBI,Edge Filtering during Bus Integration (read/write write protection)" "0: Edge filtering is disabled.,1: Edge filtering is enabled. Two consecutive.."
|
|
bitfld.long 0x10 12. "PXHD,Protocol Exception Event Handling (read/write write protection)" "0: Protocol exception handling enabled.,1: Protocol exception handling disabled."
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|
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bitfld.long 0x10 9. "BRSE,Bit Rate Switching Enable (read/write write protection)" "0: Bit rate switching for transmissions disabled.,1: Bit rate switching for transmissions enabled."
|
|
bitfld.long 0x10 8. "FDOE,CAN FD Operation Enable (read/write write protection)" "0: FD operation disabled.,1: FD operation enabled."
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bitfld.long 0x10 7. "TEST,Test Mode Enable (read/write write protection against '1')" "0: Normal operation MCAN_TEST register holds reset..,1: Test mode write access to MCAN_TEST register.."
|
|
bitfld.long 0x10 6. "DAR,Disable Automatic Retransmission (read/write write protection)" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled."
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bitfld.long 0x10 5. "MON,Bus Monitoring Mode (read/write write protection against '1')" "0: Bus Monitoring mode is disabled.,1: Bus Monitoring mode is enabled."
|
|
bitfld.long 0x10 4. "CSR,Clock Stop Request (read/write)" "0: No clock stop is requested.,1: Clock stop requested. When clock stop is.."
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bitfld.long 0x10 3. "CSA,Clock Stop Acknowledge (read-only)" "0: No clock stop acknowledged.,1: MCAN may be set in power down by stopping the.."
|
|
bitfld.long 0x10 2. "ASM,Restricted Operation Mode (read/write write protection against '1')" "0: Normal CAN operation.,1: Restricted Operation mode active."
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bitfld.long 0x10 1. "CCE,Configuration Change Enable (read/write write protection)" "0: The processor has no write access to the..,1: The processor has write access to the protected.."
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|
bitfld.long 0x10 0. "INIT,Initialization (read/write)" "0: Normal operation.,1: Initialization is started."
|
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line.long 0x14 "NBTP,Nominal Bit Timing and Prescaler Register"
|
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hexmask.long.byte 0x14 25.--31. 1. "NSJW,Nominal (Re) Synchronization Jump Width"
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hexmask.long.word 0x14 16.--24. 1. "NBRP,Nominal Bit Rate Prescaler"
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hexmask.long.byte 0x14 8.--15. 1. "NTSEG1,Nominal Time Segment Before Sample Point"
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hexmask.long.byte 0x14 0.--6. 1. "NTSEG2,Nominal Time Segment After Sample Point"
|
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line.long 0x18 "TSCC,Timestamp Counter Configuration Register"
|
|
hexmask.long.byte 0x18 16.--19. 1. "TCP,Timestamp Counter Prescaler"
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bitfld.long 0x18 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter value used,3: Timestamp counter value always 0x0000"
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line.long 0x1C "TSCV,Timestamp Counter Value Register"
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hexmask.long.word 0x1C 0.--15. 1. "TSC,Timestamp Counter (cleared on write)"
|
|
line.long 0x20 "TOCC,Timeout Counter Configuration Register"
|
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hexmask.long.word 0x20 16.--31. 1. "TOP,Timeout Period"
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bitfld.long 0x20 1.--2. "TOS,Timeout Select" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,2: Timeout controlled by Receive FIFO 0,3: Timeout controlled by Receive FIFO 1"
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bitfld.long 0x20 0. "ETOC,Enable Timeout Counter" "0: Timeout Counter disabled.,1: Timeout Counter enabled."
|
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line.long 0x24 "TOCV,Timeout Counter Value Register"
|
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hexmask.long.word 0x24 0.--15. 1. "TOC,Timeout Counter (cleared on write)"
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rgroup.long 0x40++0x7
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line.long 0x0 "ECR,Error Counter Register"
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hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging (cleared on read)"
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bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.."
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hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter"
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hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter"
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line.long 0x4 "PSR,Protocol Status Register"
|
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hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value"
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bitfld.long 0x4 14. "PXE,Protocol Exception Event (cleared on read)" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
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bitfld.long 0x4 13. "RFDF,Received a CAN FD Message (cleared on read)" "0: Since this bit was reset by the CPU no CAN FD..,1: Message in CAN FD format with FDF flag set has.."
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bitfld.long 0x4 12. "RBRS,BRS Flag of Last Received CAN FD Message (cleared on read)" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set."
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bitfld.long 0x4 11. "RESI,ESI Flag of Last Received CAN FD Message (cleared on read)" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set."
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bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code (set to 111 on read)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The MCAN is not Bus_Off.,1: The MCAN is in Bus_Off state."
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bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
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bitfld.long 0x4 5. "EP,Error Passive" "0: The MCAN is in the Error_Active state. It..,1: The MCAN is in the Error_Passive state."
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bitfld.long 0x4 3.--4. "ACT,Activity" "0: Node is synchronizing on CAN communication,1: Node is neither receiver nor transmitter,2: Node is operating as receiver,3: Node is operating as transmitter"
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bitfld.long 0x4 0.--2. "LEC,Last Error Code (set to 111 on read)" "0: No error occurred since LEC has been reset by..,1: More than 5 equal bits in a sequence have..,2: A fixed format part of a received frame has the..,3: The message transmitted by the MCAN was not..,4: During transmission of a message (with the..,5: During transmission of a message (or acknowledge..,6: The CRC check sum of a received message was..,7: Any read access to the Protocol Status Register.."
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group.long 0x48++0x3
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line.long 0x0 "TDCR,Transmit Delay Compensation Register"
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hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset"
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hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter"
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group.long 0x50++0xF
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line.long 0x0 "IR,Interrupt Register"
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bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0: No access to reserved address occurred,1: Access to reserved address occurred"
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bitfld.long 0x0 28. "PED,Protocol Error in Data Phase" "0: No protocol error in data phase,1: Protocol error in data phase detected.."
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bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.."
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bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred.,1: Message RAM Watchdog event due to missing READY."
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bitfld.long 0x0 25. "BO,Bus_Off Status" "0: Bus_Off status unchanged.,1: Bus_Off status changed."
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|
bitfld.long 0x0 24. "EW,Warning Status" "0: Error_Warning status unchanged.,1: Error_Warning status changed."
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bitfld.long 0x0 23. "EP,Error Passive" "0: Error_Passive status unchanged.,1: Error_Passive status changed."
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|
bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0: CAN Error Logging Counter did not overflow.,1: Overflow of CAN Error Logging Counter occurred."
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bitfld.long 0x0 19. "DRX,Message stored to Dedicated Receive Buffer" "0: No Receive Buffer updated.,1: At least one received message stored into a.."
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bitfld.long 0x0 18. "TOO,Timeout Occurred" "0: No timeout.,1: Timeout reached."
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bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0: No Message RAM access failure occurred.,1: Message RAM access failure occurred."
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bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around.,1: Timestamp counter wrapped around."
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bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost.,1: Tx Event FIFO element lost also set after write.."
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bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0: Tx Event FIFO not full.,1: Tx Event FIFO full."
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bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO fill level below watermark.,1: Tx Event FIFO fill level reached watermark."
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bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0: Tx Event FIFO unchanged.,1: Tx Handler wrote Tx Event FIFO element."
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bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty.,1: Tx FIFO empty."
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bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished.,1: Transmission cancellation finished."
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bitfld.long 0x0 9. "TC,Transmission Completed" "0: No transmission completed.,1: Transmission completed."
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bitfld.long 0x0 8. "HPM,High Priority Message" "0: No high priority message received.,1: High priority message received."
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bitfld.long 0x0 7. "RF1L,Receive FIFO 1 Message Lost" "0: No Receive FIFO 1 message lost.,1: Receive FIFO 1 message lost also set after write.."
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bitfld.long 0x0 6. "RF1F,Receive FIFO 1 Full" "0: Receive FIFO 1 not full.,1: Receive FIFO 1 full."
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bitfld.long 0x0 5. "RF1W,Receive FIFO 1 Watermark Reached" "0: Receive FIFO 1 fill level below watermark.,1: Receive FIFO 1 fill level reached watermark."
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bitfld.long 0x0 4. "RF1N,Receive FIFO 1 New Message" "0: No new message written to Receive FIFO 1.,1: New message written to Receive FIFO 1."
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bitfld.long 0x0 3. "RF0L,Receive FIFO 0 Message Lost" "0: No Receive FIFO 0 message lost.,1: Receive FIFO 0 message lost also set after write.."
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bitfld.long 0x0 2. "RF0F,Receive FIFO 0 Full" "0: Receive FIFO 0 not full.,1: Receive FIFO 0 full."
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newline
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bitfld.long 0x0 1. "RF0W,Receive FIFO 0 Watermark Reached" "0: Receive FIFO 0 fill level below watermark.,1: Receive FIFO 0 fill level reached watermark."
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bitfld.long 0x0 0. "RF0N,Receive FIFO 0 New Message" "0: No new message written to Receive FIFO 0.,1: New message written to Receive FIFO 0."
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line.long 0x4 "IE,Interrupt Enable Register"
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bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0,1"
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bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0,1"
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newline
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bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0,1"
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bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0,1"
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newline
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bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0,1"
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bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0,1"
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newline
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bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0,1"
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bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Receive Buffer Interrupt Enable" "0,1"
|
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bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1"
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newline
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bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1"
|
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bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1"
|
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bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1"
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bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0,1"
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bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1"
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newline
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bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1"
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bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0,1"
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bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0,1"
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newline
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bitfld.long 0x4 7. "RF1LE,Receive FIFO 1 Message Lost Interrupt Enable" "0,1"
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bitfld.long 0x4 6. "RF1FE,Receive FIFO 1 Full Interrupt Enable" "0,1"
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newline
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bitfld.long 0x4 5. "RF1WE,Receive FIFO 1 Watermark Reached Interrupt Enable" "0,1"
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bitfld.long 0x4 4. "RF1NE,Receive FIFO 1 New Message Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x4 3. "RF0LE,Receive FIFO 0 Message Lost Interrupt Enable" "0,1"
|
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bitfld.long 0x4 2. "RF0FE,Receive FIFO 0 Full Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x4 1. "RF0WE,Receive FIFO 0 Watermark Reached Interrupt Enable" "0,1"
|
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bitfld.long 0x4 0. "RF0NE,Receive FIFO 0 New Message Interrupt Enable" "0,1"
|
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line.long 0x8 "ILS,Interrupt Line Select Register"
|
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bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0,1"
|
|
bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0,1"
|
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newline
|
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bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0,1"
|
|
bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0,1"
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newline
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bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0,1"
|
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bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0,1"
|
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newline
|
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bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0,1"
|
|
bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1"
|
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newline
|
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bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Receive Buffer Interrupt Line" "0,1"
|
|
bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0,1"
|
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newline
|
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bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1"
|
|
bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1"
|
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newline
|
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bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1"
|
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bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1"
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newline
|
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bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1"
|
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newline
|
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bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1"
|
|
bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0,1"
|
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newline
|
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bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0,1"
|
|
bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0,1"
|
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newline
|
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bitfld.long 0x8 7. "RF1LL,Receive FIFO 1 Message Lost Interrupt Line" "0,1"
|
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bitfld.long 0x8 6. "RF1FL,Receive FIFO 1 Full Interrupt Line" "0,1"
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bitfld.long 0x8 5. "RF1WL,Receive FIFO 1 Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 4. "RF1NL,Receive FIFO 1 New Message Interrupt Line" "0,1"
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newline
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bitfld.long 0x8 3. "RF0LL,Receive FIFO 0 Message Lost Interrupt Line" "0,1"
|
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bitfld.long 0x8 2. "RF0FL,Receive FIFO 0 Full Interrupt Line" "0,1"
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newline
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bitfld.long 0x8 1. "RF0WL,Receive FIFO 0 Watermark Reached Interrupt Line" "0,1"
|
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bitfld.long 0x8 0. "RF0NL,Receive FIFO 0 New Message Interrupt Line" "0,1"
|
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line.long 0xC "ILE,Interrupt Line Enable Register"
|
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bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line MCAN_INT1 disabled.,1: Interrupt line MCAN_INT1 enabled."
|
|
bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line MCAN_INT0 disabled.,1: Interrupt line MCAN_INT0 enabled."
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|
group.long 0x80++0xB
|
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line.long 0x0 "GFC,Global Filter Configuration Register"
|
|
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
|
|
bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
|
|
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bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs.,1: Reject all remote frames with 11-bit standard IDs."
|
|
bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs.,1: Reject all remote frames with 29-bit extended IDs."
|
|
line.long 0x4 "SIDFC,Standard ID Filter Configuration Register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard"
|
|
hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address"
|
|
line.long 0x8 "XIDFC,Extended ID Filter Configuration Register"
|
|
hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended"
|
|
hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address"
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "XIDAM,Extended ID AND Mask Register"
|
|
hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask"
|
|
rgroup.long 0x94++0x3
|
|
line.long 0x0 "HPMS,High Priority Message Status Register"
|
|
bitfld.long 0x0 15. "FLST,Filter List" "0: Standard filter list,1: Extended filter list"
|
|
hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index"
|
|
newline
|
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bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected.,1: FIFO message lost.,2: Message stored in FIFO 0.,3: Message stored in FIFO 1."
|
|
hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index"
|
|
group.long 0x98++0xB
|
|
line.long 0x0 "NDAT1,New Data 1 Register"
|
|
bitfld.long 0x0 31. "ND31,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 30. "ND30,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
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newline
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bitfld.long 0x0 29. "ND29,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 28. "ND28,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
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newline
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bitfld.long 0x0 27. "ND27,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 26. "ND26,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
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newline
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bitfld.long 0x0 25. "ND25,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 24. "ND24,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
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newline
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bitfld.long 0x0 23. "ND23,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
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|
bitfld.long 0x0 22. "ND22,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
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newline
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bitfld.long 0x0 21. "ND21,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 20. "ND20,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
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|
newline
|
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bitfld.long 0x0 19. "ND19,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 18. "ND18,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
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bitfld.long 0x0 17. "ND17,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 16. "ND16,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
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newline
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bitfld.long 0x0 15. "ND15,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 14. "ND14,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
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|
newline
|
|
bitfld.long 0x0 13. "ND13,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 12. "ND12,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 11. "ND11,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 10. "ND10,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 9. "ND9,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 8. "ND8,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 7. "ND7,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 6. "ND6,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 5. "ND5,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 4. "ND4,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 3. "ND3,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 2. "ND2,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 1. "ND1,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 0. "ND0,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
line.long 0x4 "NDAT2,New Data 2 Register"
|
|
bitfld.long 0x4 31. "ND63,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 30. "ND62,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 29. "ND61,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 28. "ND60,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 27. "ND59,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 26. "ND58,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 25. "ND57,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 24. "ND56,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 23. "ND55,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 22. "ND54,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 21. "ND53,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 20. "ND52,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 19. "ND51,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 18. "ND50,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 17. "ND49,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 16. "ND48,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 15. "ND47,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 14. "ND46,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 13. "ND45,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 12. "ND44,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 11. "ND43,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 10. "ND42,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 9. "ND41,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 8. "ND40,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 7. "ND39,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 6. "ND38,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 5. "ND37,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 4. "ND36,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 3. "ND35,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 2. "ND34,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 1. "ND33,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 0. "ND32,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
line.long 0x8 "RXF0C,Receive FIFO 0 Configuration Register"
|
|
bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0: FIFO 0 Blocking mode.,1: FIFO 0 Overwrite mode."
|
|
hexmask.long.byte 0x8 24.--30. 1. "F0WM,Receive FIFO 0 Watermark"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "F0S,Receive FIFO 0 Size"
|
|
hexmask.long.word 0x8 2.--15. 1. "F0SA,Receive FIFO 0 Start Address"
|
|
rgroup.long 0xA4++0x3
|
|
line.long 0x0 "RXF0S,Receive FIFO 0 Status Register"
|
|
bitfld.long 0x0 25. "RF0L,Receive FIFO 0 Message Lost" "0: No Receive FIFO 0 message lost,1: Receive FIFO 0 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F0F,Receive FIFO 0 Full" "0: Receive FIFO 0 not full.,1: Receive FIFO 0 full."
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "F0PI,Receive FIFO 0 Put Index"
|
|
hexmask.long.byte 0x0 8.--13. 1. "F0GI,Receive FIFO 0 Get Index"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "F0FL,Receive FIFO 0 Fill Level"
|
|
group.long 0xA8++0xB
|
|
line.long 0x0 "RXF0A,Receive FIFO 0 Acknowledge Register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F0AI,Receive FIFO 0 Acknowledge Index"
|
|
line.long 0x4 "RXBC,Receive Rx Buffer Configuration Register"
|
|
hexmask.long.word 0x4 2.--15. 1. "RBSA,Receive Buffer Start Address"
|
|
line.long 0x8 "RXF1C,Receive FIFO 1 Configuration Register"
|
|
bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0: FIFO 1 Blocking mode.,1: FIFO 1 Overwrite mode."
|
|
hexmask.long.byte 0x8 24.--30. 1. "F1WM,Receive FIFO 1 Watermark"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "F1S,Receive FIFO 1 Size"
|
|
hexmask.long.word 0x8 2.--15. 1. "F1SA,Receive FIFO 1 Start Address"
|
|
rgroup.long 0xB4++0x3
|
|
line.long 0x0 "RXF1S,Receive FIFO 1 Status Register"
|
|
bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0: Idle state wait for reception of debug messages..,1: Debug message A received.,2: Debug messages A B received.,3: Debug messages A B C received DMA request is set."
|
|
bitfld.long 0x0 25. "RF1L,Receive FIFO 1 Message Lost" "0: No Receive FIFO 1 message lost.,1: Receive FIFO 1 message lost also set after write.."
|
|
newline
|
|
bitfld.long 0x0 24. "F1F,Receive FIFO 1 Full" "0: Receive FIFO 1 not full.,1: Receive FIFO 1 full."
|
|
hexmask.long.byte 0x0 16.--21. 1. "F1PI,Receive FIFO 1 Put Index"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "F1GI,Receive FIFO 1 Get Index"
|
|
hexmask.long.byte 0x0 0.--6. 1. "F1FL,Receive FIFO 1 Fill Level"
|
|
group.long 0xB8++0xB
|
|
line.long 0x0 "RXF1A,Receive FIFO 1 Acknowledge Register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Receive FIFO 1 Acknowledge Index"
|
|
line.long 0x4 "RXESC,Receive Buffer / FIFO Element Size Configuration Register"
|
|
bitfld.long 0x4 8.--10. "RBDS,Receive Buffer Data Field Size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field"
|
|
bitfld.long 0x4 4.--6. "F1DS,Receive FIFO 1 Data Field Size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "F0DS,Receive FIFO 0 Data Field Size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field"
|
|
line.long 0x8 "TXBC,Transmit Buffer Configuration Register"
|
|
bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation.,1: Tx Queue operation."
|
|
hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers"
|
|
hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address"
|
|
rgroup.long 0xC4++0x3
|
|
line.long 0x0 "TXFQS,Transmit FIFO/Queue Status Register"
|
|
bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full.,1: Tx FIFO/Queue full."
|
|
hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index"
|
|
hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level"
|
|
group.long 0xC8++0x3
|
|
line.long 0x0 "TXESC,Transmit Buffer Element Size Configuration Register"
|
|
bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48- byte data field,7: 64-byte data field"
|
|
rgroup.long 0xCC++0x3
|
|
line.long 0x0 "TXBRP,Transmit Buffer Request Pending Register"
|
|
bitfld.long 0x0 31. "TRP31,Transmission Request Pending for Buffer 31" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 30. "TRP30,Transmission Request Pending for Buffer 30" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 29. "TRP29,Transmission Request Pending for Buffer 29" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 28. "TRP28,Transmission Request Pending for Buffer 28" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 27. "TRP27,Transmission Request Pending for Buffer 27" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 26. "TRP26,Transmission Request Pending for Buffer 26" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 25. "TRP25,Transmission Request Pending for Buffer 25" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 24. "TRP24,Transmission Request Pending for Buffer 24" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 23. "TRP23,Transmission Request Pending for Buffer 23" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 22. "TRP22,Transmission Request Pending for Buffer 22" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 21. "TRP21,Transmission Request Pending for Buffer 21" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 20. "TRP20,Transmission Request Pending for Buffer 20" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 19. "TRP19,Transmission Request Pending for Buffer 19" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 18. "TRP18,Transmission Request Pending for Buffer 18" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 17. "TRP17,Transmission Request Pending for Buffer 17" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 16. "TRP16,Transmission Request Pending for Buffer 16" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 15. "TRP15,Transmission Request Pending for Buffer 15" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 14. "TRP14,Transmission Request Pending for Buffer 14" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 13. "TRP13,Transmission Request Pending for Buffer 13" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 12. "TRP12,Transmission Request Pending for Buffer 12" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 11. "TRP11,Transmission Request Pending for Buffer 11" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 10. "TRP10,Transmission Request Pending for Buffer 10" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 9. "TRP9,Transmission Request Pending for Buffer 9" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 8. "TRP8,Transmission Request Pending for Buffer 8" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 7. "TRP7,Transmission Request Pending for Buffer 7" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 6. "TRP6,Transmission Request Pending for Buffer 6" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 5. "TRP5,Transmission Request Pending for Buffer 5" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 4. "TRP4,Transmission Request Pending for Buffer 4" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 3. "TRP3,Transmission Request Pending for Buffer 3" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 2. "TRP2,Transmission Request Pending for Buffer 2" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 1. "TRP1,Transmission Request Pending for Buffer 1" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 0. "TRP0,Transmission Request Pending for Buffer 0" "0: No transmission request pending,1: Transmission request pending"
|
|
group.long 0xD0++0x7
|
|
line.long 0x0 "TXBAR,Transmit Buffer Add Request Register"
|
|
bitfld.long 0x0 31. "AR31,Add Request for Transmit Buffer 31" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 30. "AR30,Add Request for Transmit Buffer 30" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 29. "AR29,Add Request for Transmit Buffer 29" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 28. "AR28,Add Request for Transmit Buffer 28" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 27. "AR27,Add Request for Transmit Buffer 27" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 26. "AR26,Add Request for Transmit Buffer 26" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 25. "AR25,Add Request for Transmit Buffer 25" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 24. "AR24,Add Request for Transmit Buffer 24" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 23. "AR23,Add Request for Transmit Buffer 23" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 22. "AR22,Add Request for Transmit Buffer 22" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 21. "AR21,Add Request for Transmit Buffer 21" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 20. "AR20,Add Request for Transmit Buffer 20" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 19. "AR19,Add Request for Transmit Buffer 19" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 18. "AR18,Add Request for Transmit Buffer 18" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 17. "AR17,Add Request for Transmit Buffer 17" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 16. "AR16,Add Request for Transmit Buffer 16" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 15. "AR15,Add Request for Transmit Buffer 15" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 14. "AR14,Add Request for Transmit Buffer 14" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 13. "AR13,Add Request for Transmit Buffer 13" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 12. "AR12,Add Request for Transmit Buffer 12" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 11. "AR11,Add Request for Transmit Buffer 11" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 10. "AR10,Add Request for Transmit Buffer 10" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 9. "AR9,Add Request for Transmit Buffer 9" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 8. "AR8,Add Request for Transmit Buffer 8" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 7. "AR7,Add Request for Transmit Buffer 7" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 6. "AR6,Add Request for Transmit Buffer 6" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 5. "AR5,Add Request for Transmit Buffer 5" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 4. "AR4,Add Request for Transmit Buffer 4" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 3. "AR3,Add Request for Transmit Buffer 3" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 2. "AR2,Add Request for Transmit Buffer 2" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 1. "AR1,Add Request for Transmit Buffer 1" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 0. "AR0,Add Request for Transmit Buffer 0" "0: No transmission request added.,1: Transmission requested added."
|
|
line.long 0x4 "TXBCR,Transmit Buffer Cancellation Request Register"
|
|
bitfld.long 0x4 31. "CR31,Cancellation Request for Transmit Buffer 31" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 30. "CR30,Cancellation Request for Transmit Buffer 30" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 29. "CR29,Cancellation Request for Transmit Buffer 29" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 28. "CR28,Cancellation Request for Transmit Buffer 28" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 27. "CR27,Cancellation Request for Transmit Buffer 27" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 26. "CR26,Cancellation Request for Transmit Buffer 26" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 25. "CR25,Cancellation Request for Transmit Buffer 25" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 24. "CR24,Cancellation Request for Transmit Buffer 24" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 23. "CR23,Cancellation Request for Transmit Buffer 23" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 22. "CR22,Cancellation Request for Transmit Buffer 22" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 21. "CR21,Cancellation Request for Transmit Buffer 21" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 20. "CR20,Cancellation Request for Transmit Buffer 20" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 19. "CR19,Cancellation Request for Transmit Buffer 19" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 18. "CR18,Cancellation Request for Transmit Buffer 18" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 17. "CR17,Cancellation Request for Transmit Buffer 17" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 16. "CR16,Cancellation Request for Transmit Buffer 16" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 15. "CR15,Cancellation Request for Transmit Buffer 15" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 14. "CR14,Cancellation Request for Transmit Buffer 14" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 13. "CR13,Cancellation Request for Transmit Buffer 13" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 12. "CR12,Cancellation Request for Transmit Buffer 12" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 11. "CR11,Cancellation Request for Transmit Buffer 11" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 10. "CR10,Cancellation Request for Transmit Buffer 10" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 9. "CR9,Cancellation Request for Transmit Buffer 9" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 8. "CR8,Cancellation Request for Transmit Buffer 8" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 7. "CR7,Cancellation Request for Transmit Buffer 7" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 6. "CR6,Cancellation Request for Transmit Buffer 6" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 5. "CR5,Cancellation Request for Transmit Buffer 5" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 4. "CR4,Cancellation Request for Transmit Buffer 4" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 3. "CR3,Cancellation Request for Transmit Buffer 3" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 2. "CR2,Cancellation Request for Transmit Buffer 2" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 1. "CR1,Cancellation Request for Transmit Buffer 1" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 0. "CR0,Cancellation Request for Transmit Buffer 0" "0: No cancellation pending.,1: Cancellation pending."
|
|
rgroup.long 0xD8++0x7
|
|
line.long 0x0 "TXBTO,Transmit Buffer Transmission Occurred Register"
|
|
bitfld.long 0x0 31. "TO31,Transmission Occurred for Buffer 31" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 30. "TO30,Transmission Occurred for Buffer 30" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 29. "TO29,Transmission Occurred for Buffer 29" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 28. "TO28,Transmission Occurred for Buffer 28" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 27. "TO27,Transmission Occurred for Buffer 27" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 26. "TO26,Transmission Occurred for Buffer 26" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 25. "TO25,Transmission Occurred for Buffer 25" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 24. "TO24,Transmission Occurred for Buffer 24" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 23. "TO23,Transmission Occurred for Buffer 23" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 22. "TO22,Transmission Occurred for Buffer 22" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 21. "TO21,Transmission Occurred for Buffer 21" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 20. "TO20,Transmission Occurred for Buffer 20" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 19. "TO19,Transmission Occurred for Buffer 19" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 18. "TO18,Transmission Occurred for Buffer 18" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 17. "TO17,Transmission Occurred for Buffer 17" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 16. "TO16,Transmission Occurred for Buffer 16" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 15. "TO15,Transmission Occurred for Buffer 15" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 14. "TO14,Transmission Occurred for Buffer 14" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 13. "TO13,Transmission Occurred for Buffer 13" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 12. "TO12,Transmission Occurred for Buffer 12" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 11. "TO11,Transmission Occurred for Buffer 11" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 10. "TO10,Transmission Occurred for Buffer 10" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 9. "TO9,Transmission Occurred for Buffer 9" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 8. "TO8,Transmission Occurred for Buffer 8" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 7. "TO7,Transmission Occurred for Buffer 7" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 6. "TO6,Transmission Occurred for Buffer 6" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 5. "TO5,Transmission Occurred for Buffer 5" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 4. "TO4,Transmission Occurred for Buffer 4" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 3. "TO3,Transmission Occurred for Buffer 3" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 2. "TO2,Transmission Occurred for Buffer 2" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 1. "TO1,Transmission Occurred for Buffer 1" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 0. "TO0,Transmission Occurred for Buffer 0" "0: No transmission occurred.,1: Transmission occurred."
|
|
line.long 0x4 "TXBCF,Transmit Buffer Cancellation Finished Register"
|
|
bitfld.long 0x4 31. "CF31,Cancellation Finished for Transmit Buffer 31" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 30. "CF30,Cancellation Finished for Transmit Buffer 30" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 29. "CF29,Cancellation Finished for Transmit Buffer 29" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 28. "CF28,Cancellation Finished for Transmit Buffer 28" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 27. "CF27,Cancellation Finished for Transmit Buffer 27" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 26. "CF26,Cancellation Finished for Transmit Buffer 26" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 25. "CF25,Cancellation Finished for Transmit Buffer 25" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 24. "CF24,Cancellation Finished for Transmit Buffer 24" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 23. "CF23,Cancellation Finished for Transmit Buffer 23" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 22. "CF22,Cancellation Finished for Transmit Buffer 22" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 21. "CF21,Cancellation Finished for Transmit Buffer 21" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 20. "CF20,Cancellation Finished for Transmit Buffer 20" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 19. "CF19,Cancellation Finished for Transmit Buffer 19" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 18. "CF18,Cancellation Finished for Transmit Buffer 18" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 17. "CF17,Cancellation Finished for Transmit Buffer 17" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 16. "CF16,Cancellation Finished for Transmit Buffer 16" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 15. "CF15,Cancellation Finished for Transmit Buffer 15" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 14. "CF14,Cancellation Finished for Transmit Buffer 14" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 13. "CF13,Cancellation Finished for Transmit Buffer 13" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 12. "CF12,Cancellation Finished for Transmit Buffer 12" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 11. "CF11,Cancellation Finished for Transmit Buffer 11" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 10. "CF10,Cancellation Finished for Transmit Buffer 10" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 9. "CF9,Cancellation Finished for Transmit Buffer 9" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 8. "CF8,Cancellation Finished for Transmit Buffer 8" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 7. "CF7,Cancellation Finished for Transmit Buffer 7" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 6. "CF6,Cancellation Finished for Transmit Buffer 6" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 5. "CF5,Cancellation Finished for Transmit Buffer 5" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 4. "CF4,Cancellation Finished for Transmit Buffer 4" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 3. "CF3,Cancellation Finished for Transmit Buffer 3" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 2. "CF2,Cancellation Finished for Transmit Buffer 2" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 1. "CF1,Cancellation Finished for Transmit Buffer 1" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 0. "CF0,Cancellation Finished for Transmit Buffer 0" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
group.long 0xE0++0x7
|
|
line.long 0x0 "TXBTIE,Transmit Buffer Transmission Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable for Buffer 31" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable for Buffer 30" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable for Buffer 29" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable for Buffer 28" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable for Buffer 27" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable for Buffer 26" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable for Buffer 25" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable for Buffer 24" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable for Buffer 23" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable for Buffer 22" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable for Buffer 21" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable for Buffer 20" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable for Buffer 19" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable for Buffer 18" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable for Buffer 17" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable for Buffer 16" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable for Buffer 15" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable for Buffer 14" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable for Buffer 13" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable for Buffer 12" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable for Buffer 11" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable for Buffer 10" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable for Buffer 9" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable for Buffer 8" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable for Buffer 7" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable for Buffer 6" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable for Buffer 5" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable for Buffer 4" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable for Buffer 3" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable for Buffer 2" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable for Buffer 1" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable for Buffer 0" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
line.long 0x4 "TXBCIE,Transmit Buffer Cancellation Finished Interrupt Enable Register"
|
|
bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable for Transmit Buffer 31" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable for Transmit Buffer 30" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable for Transmit Buffer 29" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable for Transmit Buffer 28" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable for Transmit Buffer 27" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable for Transmit Buffer 26" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable for Transmit Buffer 25" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable for Transmit Buffer 24" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable for Transmit Buffer 23" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable for Transmit Buffer 22" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable for Transmit Buffer 21" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable for Transmit Buffer 20" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable for Transmit Buffer 19" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable for Transmit Buffer 18" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable for Transmit Buffer 17" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable for Transmit Buffer 16" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable for Transmit Buffer 15" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable for Transmit Buffer 14" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable for Transmit Buffer 13" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable for Transmit Buffer 12" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable for Transmit Buffer 11" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable for Transmit Buffer 10" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable for Transmit Buffer 9" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable for Transmit Buffer 8" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable for Transmit Buffer 7" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable for Transmit Buffer 6" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable for Transmit Buffer 5" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable for Transmit Buffer 4" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable for Transmit Buffer 3" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable for Transmit Buffer 2" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable for Transmit Buffer 1" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable for Transmit Buffer 0" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
group.long 0xF0++0x3
|
|
line.long 0x0 "TXEFC,Transmit Event FIFO Configuration Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark"
|
|
hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size"
|
|
newline
|
|
hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address"
|
|
rgroup.long 0xF4++0x3
|
|
line.long 0x0 "TXEFS,Transmit Event FIFO Status Register"
|
|
bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.."
|
|
bitfld.long 0x0 24. "EFF,Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index"
|
|
hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level"
|
|
group.long 0xF8++0x3
|
|
line.long 0x0 "TXEFA,Transmit Event FIFO Acknowledge Register"
|
|
hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index"
|
|
tree.end
|
|
tree "MCAN5"
|
|
base ad:0xE083C000
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "ENDN,Endian Register"
|
|
hexmask.long 0x0 0.--31. 1. "ETV,Endianness Test Value"
|
|
group.long 0x8++0x27
|
|
line.long 0x0 "CUST,Customer Register"
|
|
hexmask.long 0x0 0.--31. 1. "CSV,Customer-specific Value"
|
|
line.long 0x4 "DBTP,Data Bit Timing and Prescaler Register"
|
|
bitfld.long 0x4 23. "TDC,Transmitter Delay Compensation" "0: Transmitter Delay Compensation disabled.,1: Transmitter Delay Compensation enabled."
|
|
hexmask.long.byte 0x4 16.--20. 1. "DBRP,Data Bit Rate Prescaler"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--12. 1. "DTSEG1,Data Time Segment Before Sample Point"
|
|
hexmask.long.byte 0x4 4.--7. 1. "DTSEG2,Data Time Segment After Sample Point"
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|
newline
|
|
bitfld.long 0x4 0.--2. "DSJW,Data (Re) Synchronization Jump Width" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "TEST,Test Register"
|
|
bitfld.long 0x8 7. "RX,Receive Pin (read-only)" "0: The CAN bus is dominant (CANRX = '0').,1: The CAN bus is recessive (CANRX = '1')."
|
|
bitfld.long 0x8 5.--6. "TX,Control of Transmit Pin (read/write)" "0: Reset value CANTX controlled by the CAN Core..,1: Sample Point can be monitored at pin CANTX.,2: Dominant ('0') level at pin CANTX.,3: Recessive ('1') at pin CANTX."
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|
newline
|
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bitfld.long 0x8 4. "LBCK,Loop Back Mode (read/write)" "0: Reset value. Loop Back mode is disabled.,1: Loop Back mode is enabled (see Section 6.1.9.."
|
|
line.long 0xC "RWD,RAM Watchdog Register"
|
|
hexmask.long.byte 0xC 8.--15. 1. "WDV,Watchdog Value (read-only)"
|
|
hexmask.long.byte 0xC 0.--7. 1. "WDC,Watchdog Configuration (read/write)"
|
|
line.long 0x10 "CCCR,CC Control Register"
|
|
bitfld.long 0x10 15. "NISO,Non-ISO Operation" "0: CAN FD frame format according to ISO11898-1..,1: CAN FD frame format according to Bosch CAN FD.."
|
|
bitfld.long 0x10 14. "TXP,Transmit Pause (read/write write protection)" "0: Transmit pause disabled.,1: Transmit pause enabled."
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|
newline
|
|
bitfld.long 0x10 13. "EFBI,Edge Filtering during Bus Integration (read/write write protection)" "0: Edge filtering is disabled.,1: Edge filtering is enabled. Two consecutive.."
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|
bitfld.long 0x10 12. "PXHD,Protocol Exception Event Handling (read/write write protection)" "0: Protocol exception handling enabled.,1: Protocol exception handling disabled."
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|
newline
|
|
bitfld.long 0x10 9. "BRSE,Bit Rate Switching Enable (read/write write protection)" "0: Bit rate switching for transmissions disabled.,1: Bit rate switching for transmissions enabled."
|
|
bitfld.long 0x10 8. "FDOE,CAN FD Operation Enable (read/write write protection)" "0: FD operation disabled.,1: FD operation enabled."
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|
newline
|
|
bitfld.long 0x10 7. "TEST,Test Mode Enable (read/write write protection against '1')" "0: Normal operation MCAN_TEST register holds reset..,1: Test mode write access to MCAN_TEST register.."
|
|
bitfld.long 0x10 6. "DAR,Disable Automatic Retransmission (read/write write protection)" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled."
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newline
|
|
bitfld.long 0x10 5. "MON,Bus Monitoring Mode (read/write write protection against '1')" "0: Bus Monitoring mode is disabled.,1: Bus Monitoring mode is enabled."
|
|
bitfld.long 0x10 4. "CSR,Clock Stop Request (read/write)" "0: No clock stop is requested.,1: Clock stop requested. When clock stop is.."
|
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newline
|
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bitfld.long 0x10 3. "CSA,Clock Stop Acknowledge (read-only)" "0: No clock stop acknowledged.,1: MCAN may be set in power down by stopping the.."
|
|
bitfld.long 0x10 2. "ASM,Restricted Operation Mode (read/write write protection against '1')" "0: Normal CAN operation.,1: Restricted Operation mode active."
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newline
|
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bitfld.long 0x10 1. "CCE,Configuration Change Enable (read/write write protection)" "0: The processor has no write access to the..,1: The processor has write access to the protected.."
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|
bitfld.long 0x10 0. "INIT,Initialization (read/write)" "0: Normal operation.,1: Initialization is started."
|
|
line.long 0x14 "NBTP,Nominal Bit Timing and Prescaler Register"
|
|
hexmask.long.byte 0x14 25.--31. 1. "NSJW,Nominal (Re) Synchronization Jump Width"
|
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hexmask.long.word 0x14 16.--24. 1. "NBRP,Nominal Bit Rate Prescaler"
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newline
|
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hexmask.long.byte 0x14 8.--15. 1. "NTSEG1,Nominal Time Segment Before Sample Point"
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|
hexmask.long.byte 0x14 0.--6. 1. "NTSEG2,Nominal Time Segment After Sample Point"
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line.long 0x18 "TSCC,Timestamp Counter Configuration Register"
|
|
hexmask.long.byte 0x18 16.--19. 1. "TCP,Timestamp Counter Prescaler"
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bitfld.long 0x18 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter value used,3: Timestamp counter value always 0x0000"
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line.long 0x1C "TSCV,Timestamp Counter Value Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. "TSC,Timestamp Counter (cleared on write)"
|
|
line.long 0x20 "TOCC,Timeout Counter Configuration Register"
|
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hexmask.long.word 0x20 16.--31. 1. "TOP,Timeout Period"
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|
bitfld.long 0x20 1.--2. "TOS,Timeout Select" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,2: Timeout controlled by Receive FIFO 0,3: Timeout controlled by Receive FIFO 1"
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newline
|
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bitfld.long 0x20 0. "ETOC,Enable Timeout Counter" "0: Timeout Counter disabled.,1: Timeout Counter enabled."
|
|
line.long 0x24 "TOCV,Timeout Counter Value Register"
|
|
hexmask.long.word 0x24 0.--15. 1. "TOC,Timeout Counter (cleared on write)"
|
|
rgroup.long 0x40++0x7
|
|
line.long 0x0 "ECR,Error Counter Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging (cleared on read)"
|
|
bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.."
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newline
|
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hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter"
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|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter"
|
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line.long 0x4 "PSR,Protocol Status Register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value"
|
|
bitfld.long 0x4 14. "PXE,Protocol Exception Event (cleared on read)" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
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newline
|
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bitfld.long 0x4 13. "RFDF,Received a CAN FD Message (cleared on read)" "0: Since this bit was reset by the CPU no CAN FD..,1: Message in CAN FD format with FDF flag set has.."
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|
bitfld.long 0x4 12. "RBRS,BRS Flag of Last Received CAN FD Message (cleared on read)" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set."
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|
newline
|
|
bitfld.long 0x4 11. "RESI,ESI Flag of Last Received CAN FD Message (cleared on read)" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set."
|
|
bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code (set to 111 on read)" "0,1,2,3,4,5,6,7"
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|
newline
|
|
bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The MCAN is not Bus_Off.,1: The MCAN is in Bus_Off state."
|
|
bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
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newline
|
|
bitfld.long 0x4 5. "EP,Error Passive" "0: The MCAN is in the Error_Active state. It..,1: The MCAN is in the Error_Passive state."
|
|
bitfld.long 0x4 3.--4. "ACT,Activity" "0: Node is synchronizing on CAN communication,1: Node is neither receiver nor transmitter,2: Node is operating as receiver,3: Node is operating as transmitter"
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|
newline
|
|
bitfld.long 0x4 0.--2. "LEC,Last Error Code (set to 111 on read)" "0: No error occurred since LEC has been reset by..,1: More than 5 equal bits in a sequence have..,2: A fixed format part of a received frame has the..,3: The message transmitted by the MCAN was not..,4: During transmission of a message (with the..,5: During transmission of a message (or acknowledge..,6: The CRC check sum of a received message was..,7: Any read access to the Protocol Status Register.."
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|
group.long 0x48++0x3
|
|
line.long 0x0 "TDCR,Transmit Delay Compensation Register"
|
|
hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset"
|
|
hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter"
|
|
group.long 0x50++0xF
|
|
line.long 0x0 "IR,Interrupt Register"
|
|
bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0: No access to reserved address occurred,1: Access to reserved address occurred"
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bitfld.long 0x0 28. "PED,Protocol Error in Data Phase" "0: No protocol error in data phase,1: Protocol error in data phase detected.."
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newline
|
|
bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.."
|
|
bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred.,1: Message RAM Watchdog event due to missing READY."
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|
newline
|
|
bitfld.long 0x0 25. "BO,Bus_Off Status" "0: Bus_Off status unchanged.,1: Bus_Off status changed."
|
|
bitfld.long 0x0 24. "EW,Warning Status" "0: Error_Warning status unchanged.,1: Error_Warning status changed."
|
|
newline
|
|
bitfld.long 0x0 23. "EP,Error Passive" "0: Error_Passive status unchanged.,1: Error_Passive status changed."
|
|
bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0: CAN Error Logging Counter did not overflow.,1: Overflow of CAN Error Logging Counter occurred."
|
|
newline
|
|
bitfld.long 0x0 19. "DRX,Message stored to Dedicated Receive Buffer" "0: No Receive Buffer updated.,1: At least one received message stored into a.."
|
|
bitfld.long 0x0 18. "TOO,Timeout Occurred" "0: No timeout.,1: Timeout reached."
|
|
newline
|
|
bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0: No Message RAM access failure occurred.,1: Message RAM access failure occurred."
|
|
bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around.,1: Timestamp counter wrapped around."
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newline
|
|
bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost.,1: Tx Event FIFO element lost also set after write.."
|
|
bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0: Tx Event FIFO not full.,1: Tx Event FIFO full."
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newline
|
|
bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO fill level below watermark.,1: Tx Event FIFO fill level reached watermark."
|
|
bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0: Tx Event FIFO unchanged.,1: Tx Handler wrote Tx Event FIFO element."
|
|
newline
|
|
bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty.,1: Tx FIFO empty."
|
|
bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished.,1: Transmission cancellation finished."
|
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newline
|
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bitfld.long 0x0 9. "TC,Transmission Completed" "0: No transmission completed.,1: Transmission completed."
|
|
bitfld.long 0x0 8. "HPM,High Priority Message" "0: No high priority message received.,1: High priority message received."
|
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newline
|
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bitfld.long 0x0 7. "RF1L,Receive FIFO 1 Message Lost" "0: No Receive FIFO 1 message lost.,1: Receive FIFO 1 message lost also set after write.."
|
|
bitfld.long 0x0 6. "RF1F,Receive FIFO 1 Full" "0: Receive FIFO 1 not full.,1: Receive FIFO 1 full."
|
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newline
|
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bitfld.long 0x0 5. "RF1W,Receive FIFO 1 Watermark Reached" "0: Receive FIFO 1 fill level below watermark.,1: Receive FIFO 1 fill level reached watermark."
|
|
bitfld.long 0x0 4. "RF1N,Receive FIFO 1 New Message" "0: No new message written to Receive FIFO 1.,1: New message written to Receive FIFO 1."
|
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newline
|
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bitfld.long 0x0 3. "RF0L,Receive FIFO 0 Message Lost" "0: No Receive FIFO 0 message lost.,1: Receive FIFO 0 message lost also set after write.."
|
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bitfld.long 0x0 2. "RF0F,Receive FIFO 0 Full" "0: Receive FIFO 0 not full.,1: Receive FIFO 0 full."
|
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newline
|
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bitfld.long 0x0 1. "RF0W,Receive FIFO 0 Watermark Reached" "0: Receive FIFO 0 fill level below watermark.,1: Receive FIFO 0 fill level reached watermark."
|
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bitfld.long 0x0 0. "RF0N,Receive FIFO 0 New Message" "0: No new message written to Receive FIFO 0.,1: New message written to Receive FIFO 0."
|
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line.long 0x4 "IE,Interrupt Enable Register"
|
|
bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0,1"
|
|
bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0,1"
|
|
bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Receive Buffer Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RF1LE,Receive FIFO 1 Message Lost Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 6. "RF1FE,Receive FIFO 1 Full Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x4 5. "RF1WE,Receive FIFO 1 Watermark Reached Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 4. "RF1NE,Receive FIFO 1 New Message Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RF0LE,Receive FIFO 0 Message Lost Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 2. "RF0FE,Receive FIFO 0 Full Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "RF0WE,Receive FIFO 0 Watermark Reached Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 0. "RF0NE,Receive FIFO 0 New Message Interrupt Enable" "0,1"
|
|
line.long 0x8 "ILS,Interrupt Line Select Register"
|
|
bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0,1"
|
|
bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0,1"
|
|
bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0,1"
|
|
bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0,1"
|
|
bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Receive Buffer Interrupt Line" "0,1"
|
|
bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1"
|
|
bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1"
|
|
bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0,1"
|
|
bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "RF1LL,Receive FIFO 1 Message Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 6. "RF1FL,Receive FIFO 1 Full Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "RF1WL,Receive FIFO 1 Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 4. "RF1NL,Receive FIFO 1 New Message Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "RF0LL,Receive FIFO 0 Message Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 2. "RF0FL,Receive FIFO 0 Full Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "RF0WL,Receive FIFO 0 Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 0. "RF0NL,Receive FIFO 0 New Message Interrupt Line" "0,1"
|
|
line.long 0xC "ILE,Interrupt Line Enable Register"
|
|
bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line MCAN_INT1 disabled.,1: Interrupt line MCAN_INT1 enabled."
|
|
bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line MCAN_INT0 disabled.,1: Interrupt line MCAN_INT0 enabled."
|
|
group.long 0x80++0xB
|
|
line.long 0x0 "GFC,Global Filter Configuration Register"
|
|
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
|
|
bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
|
|
newline
|
|
bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs.,1: Reject all remote frames with 11-bit standard IDs."
|
|
bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs.,1: Reject all remote frames with 29-bit extended IDs."
|
|
line.long 0x4 "SIDFC,Standard ID Filter Configuration Register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard"
|
|
hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address"
|
|
line.long 0x8 "XIDFC,Extended ID Filter Configuration Register"
|
|
hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended"
|
|
hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address"
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "XIDAM,Extended ID AND Mask Register"
|
|
hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask"
|
|
rgroup.long 0x94++0x3
|
|
line.long 0x0 "HPMS,High Priority Message Status Register"
|
|
bitfld.long 0x0 15. "FLST,Filter List" "0: Standard filter list,1: Extended filter list"
|
|
hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected.,1: FIFO message lost.,2: Message stored in FIFO 0.,3: Message stored in FIFO 1."
|
|
hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index"
|
|
group.long 0x98++0xB
|
|
line.long 0x0 "NDAT1,New Data 1 Register"
|
|
bitfld.long 0x0 31. "ND31,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 30. "ND30,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 29. "ND29,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 28. "ND28,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 27. "ND27,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 26. "ND26,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 25. "ND25,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 24. "ND24,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 23. "ND23,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 22. "ND22,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 21. "ND21,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 20. "ND20,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 19. "ND19,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 18. "ND18,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 17. "ND17,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 16. "ND16,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 15. "ND15,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 14. "ND14,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 13. "ND13,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 12. "ND12,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 11. "ND11,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 10. "ND10,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 9. "ND9,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 8. "ND8,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 7. "ND7,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 6. "ND6,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 5. "ND5,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 4. "ND4,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 3. "ND3,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 2. "ND2,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
newline
|
|
bitfld.long 0x0 1. "ND1,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
bitfld.long 0x0 0. "ND0,New Data" "0: Receive Buffer not updated,1: Receive Buffer updated from new message"
|
|
line.long 0x4 "NDAT2,New Data 2 Register"
|
|
bitfld.long 0x4 31. "ND63,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 30. "ND62,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 29. "ND61,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 28. "ND60,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 27. "ND59,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 26. "ND58,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 25. "ND57,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 24. "ND56,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 23. "ND55,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 22. "ND54,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 21. "ND53,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 20. "ND52,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 19. "ND51,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 18. "ND50,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 17. "ND49,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 16. "ND48,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 15. "ND47,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 14. "ND46,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 13. "ND45,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 12. "ND44,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 11. "ND43,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 10. "ND42,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 9. "ND41,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 8. "ND40,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 7. "ND39,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 6. "ND38,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 5. "ND37,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 4. "ND36,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 3. "ND35,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 2. "ND34,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
newline
|
|
bitfld.long 0x4 1. "ND33,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
bitfld.long 0x4 0. "ND32,New Data" "0: Receive Buffer not updated.,1: Receive Buffer updated from new message."
|
|
line.long 0x8 "RXF0C,Receive FIFO 0 Configuration Register"
|
|
bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0: FIFO 0 Blocking mode.,1: FIFO 0 Overwrite mode."
|
|
hexmask.long.byte 0x8 24.--30. 1. "F0WM,Receive FIFO 0 Watermark"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "F0S,Receive FIFO 0 Size"
|
|
hexmask.long.word 0x8 2.--15. 1. "F0SA,Receive FIFO 0 Start Address"
|
|
rgroup.long 0xA4++0x3
|
|
line.long 0x0 "RXF0S,Receive FIFO 0 Status Register"
|
|
bitfld.long 0x0 25. "RF0L,Receive FIFO 0 Message Lost" "0: No Receive FIFO 0 message lost,1: Receive FIFO 0 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F0F,Receive FIFO 0 Full" "0: Receive FIFO 0 not full.,1: Receive FIFO 0 full."
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "F0PI,Receive FIFO 0 Put Index"
|
|
hexmask.long.byte 0x0 8.--13. 1. "F0GI,Receive FIFO 0 Get Index"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "F0FL,Receive FIFO 0 Fill Level"
|
|
group.long 0xA8++0xB
|
|
line.long 0x0 "RXF0A,Receive FIFO 0 Acknowledge Register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F0AI,Receive FIFO 0 Acknowledge Index"
|
|
line.long 0x4 "RXBC,Receive Rx Buffer Configuration Register"
|
|
hexmask.long.word 0x4 2.--15. 1. "RBSA,Receive Buffer Start Address"
|
|
line.long 0x8 "RXF1C,Receive FIFO 1 Configuration Register"
|
|
bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0: FIFO 1 Blocking mode.,1: FIFO 1 Overwrite mode."
|
|
hexmask.long.byte 0x8 24.--30. 1. "F1WM,Receive FIFO 1 Watermark"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "F1S,Receive FIFO 1 Size"
|
|
hexmask.long.word 0x8 2.--15. 1. "F1SA,Receive FIFO 1 Start Address"
|
|
rgroup.long 0xB4++0x3
|
|
line.long 0x0 "RXF1S,Receive FIFO 1 Status Register"
|
|
bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0: Idle state wait for reception of debug messages..,1: Debug message A received.,2: Debug messages A B received.,3: Debug messages A B C received DMA request is set."
|
|
bitfld.long 0x0 25. "RF1L,Receive FIFO 1 Message Lost" "0: No Receive FIFO 1 message lost.,1: Receive FIFO 1 message lost also set after write.."
|
|
newline
|
|
bitfld.long 0x0 24. "F1F,Receive FIFO 1 Full" "0: Receive FIFO 1 not full.,1: Receive FIFO 1 full."
|
|
hexmask.long.byte 0x0 16.--21. 1. "F1PI,Receive FIFO 1 Put Index"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "F1GI,Receive FIFO 1 Get Index"
|
|
hexmask.long.byte 0x0 0.--6. 1. "F1FL,Receive FIFO 1 Fill Level"
|
|
group.long 0xB8++0xB
|
|
line.long 0x0 "RXF1A,Receive FIFO 1 Acknowledge Register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Receive FIFO 1 Acknowledge Index"
|
|
line.long 0x4 "RXESC,Receive Buffer / FIFO Element Size Configuration Register"
|
|
bitfld.long 0x4 8.--10. "RBDS,Receive Buffer Data Field Size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field"
|
|
bitfld.long 0x4 4.--6. "F1DS,Receive FIFO 1 Data Field Size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "F0DS,Receive FIFO 0 Data Field Size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field"
|
|
line.long 0x8 "TXBC,Transmit Buffer Configuration Register"
|
|
bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation.,1: Tx Queue operation."
|
|
hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers"
|
|
hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address"
|
|
rgroup.long 0xC4++0x3
|
|
line.long 0x0 "TXFQS,Transmit FIFO/Queue Status Register"
|
|
bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full.,1: Tx FIFO/Queue full."
|
|
hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index"
|
|
hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level"
|
|
group.long 0xC8++0x3
|
|
line.long 0x0 "TXESC,Transmit Buffer Element Size Configuration Register"
|
|
bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48- byte data field,7: 64-byte data field"
|
|
rgroup.long 0xCC++0x3
|
|
line.long 0x0 "TXBRP,Transmit Buffer Request Pending Register"
|
|
bitfld.long 0x0 31. "TRP31,Transmission Request Pending for Buffer 31" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 30. "TRP30,Transmission Request Pending for Buffer 30" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 29. "TRP29,Transmission Request Pending for Buffer 29" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 28. "TRP28,Transmission Request Pending for Buffer 28" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 27. "TRP27,Transmission Request Pending for Buffer 27" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 26. "TRP26,Transmission Request Pending for Buffer 26" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 25. "TRP25,Transmission Request Pending for Buffer 25" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 24. "TRP24,Transmission Request Pending for Buffer 24" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 23. "TRP23,Transmission Request Pending for Buffer 23" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 22. "TRP22,Transmission Request Pending for Buffer 22" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 21. "TRP21,Transmission Request Pending for Buffer 21" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 20. "TRP20,Transmission Request Pending for Buffer 20" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 19. "TRP19,Transmission Request Pending for Buffer 19" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 18. "TRP18,Transmission Request Pending for Buffer 18" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 17. "TRP17,Transmission Request Pending for Buffer 17" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 16. "TRP16,Transmission Request Pending for Buffer 16" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 15. "TRP15,Transmission Request Pending for Buffer 15" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 14. "TRP14,Transmission Request Pending for Buffer 14" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 13. "TRP13,Transmission Request Pending for Buffer 13" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 12. "TRP12,Transmission Request Pending for Buffer 12" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 11. "TRP11,Transmission Request Pending for Buffer 11" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 10. "TRP10,Transmission Request Pending for Buffer 10" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 9. "TRP9,Transmission Request Pending for Buffer 9" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 8. "TRP8,Transmission Request Pending for Buffer 8" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 7. "TRP7,Transmission Request Pending for Buffer 7" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 6. "TRP6,Transmission Request Pending for Buffer 6" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 5. "TRP5,Transmission Request Pending for Buffer 5" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 4. "TRP4,Transmission Request Pending for Buffer 4" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 3. "TRP3,Transmission Request Pending for Buffer 3" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 2. "TRP2,Transmission Request Pending for Buffer 2" "0: No transmission request pending,1: Transmission request pending"
|
|
newline
|
|
bitfld.long 0x0 1. "TRP1,Transmission Request Pending for Buffer 1" "0: No transmission request pending,1: Transmission request pending"
|
|
bitfld.long 0x0 0. "TRP0,Transmission Request Pending for Buffer 0" "0: No transmission request pending,1: Transmission request pending"
|
|
group.long 0xD0++0x7
|
|
line.long 0x0 "TXBAR,Transmit Buffer Add Request Register"
|
|
bitfld.long 0x0 31. "AR31,Add Request for Transmit Buffer 31" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 30. "AR30,Add Request for Transmit Buffer 30" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 29. "AR29,Add Request for Transmit Buffer 29" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 28. "AR28,Add Request for Transmit Buffer 28" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 27. "AR27,Add Request for Transmit Buffer 27" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 26. "AR26,Add Request for Transmit Buffer 26" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 25. "AR25,Add Request for Transmit Buffer 25" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 24. "AR24,Add Request for Transmit Buffer 24" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 23. "AR23,Add Request for Transmit Buffer 23" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 22. "AR22,Add Request for Transmit Buffer 22" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 21. "AR21,Add Request for Transmit Buffer 21" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 20. "AR20,Add Request for Transmit Buffer 20" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 19. "AR19,Add Request for Transmit Buffer 19" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 18. "AR18,Add Request for Transmit Buffer 18" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 17. "AR17,Add Request for Transmit Buffer 17" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 16. "AR16,Add Request for Transmit Buffer 16" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 15. "AR15,Add Request for Transmit Buffer 15" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 14. "AR14,Add Request for Transmit Buffer 14" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 13. "AR13,Add Request for Transmit Buffer 13" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 12. "AR12,Add Request for Transmit Buffer 12" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 11. "AR11,Add Request for Transmit Buffer 11" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 10. "AR10,Add Request for Transmit Buffer 10" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 9. "AR9,Add Request for Transmit Buffer 9" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 8. "AR8,Add Request for Transmit Buffer 8" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 7. "AR7,Add Request for Transmit Buffer 7" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 6. "AR6,Add Request for Transmit Buffer 6" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 5. "AR5,Add Request for Transmit Buffer 5" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 4. "AR4,Add Request for Transmit Buffer 4" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 3. "AR3,Add Request for Transmit Buffer 3" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 2. "AR2,Add Request for Transmit Buffer 2" "0: No transmission request added.,1: Transmission requested added."
|
|
newline
|
|
bitfld.long 0x0 1. "AR1,Add Request for Transmit Buffer 1" "0: No transmission request added.,1: Transmission requested added."
|
|
bitfld.long 0x0 0. "AR0,Add Request for Transmit Buffer 0" "0: No transmission request added.,1: Transmission requested added."
|
|
line.long 0x4 "TXBCR,Transmit Buffer Cancellation Request Register"
|
|
bitfld.long 0x4 31. "CR31,Cancellation Request for Transmit Buffer 31" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 30. "CR30,Cancellation Request for Transmit Buffer 30" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 29. "CR29,Cancellation Request for Transmit Buffer 29" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 28. "CR28,Cancellation Request for Transmit Buffer 28" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 27. "CR27,Cancellation Request for Transmit Buffer 27" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 26. "CR26,Cancellation Request for Transmit Buffer 26" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 25. "CR25,Cancellation Request for Transmit Buffer 25" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 24. "CR24,Cancellation Request for Transmit Buffer 24" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 23. "CR23,Cancellation Request for Transmit Buffer 23" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 22. "CR22,Cancellation Request for Transmit Buffer 22" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 21. "CR21,Cancellation Request for Transmit Buffer 21" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 20. "CR20,Cancellation Request for Transmit Buffer 20" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 19. "CR19,Cancellation Request for Transmit Buffer 19" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 18. "CR18,Cancellation Request for Transmit Buffer 18" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 17. "CR17,Cancellation Request for Transmit Buffer 17" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 16. "CR16,Cancellation Request for Transmit Buffer 16" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 15. "CR15,Cancellation Request for Transmit Buffer 15" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 14. "CR14,Cancellation Request for Transmit Buffer 14" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 13. "CR13,Cancellation Request for Transmit Buffer 13" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 12. "CR12,Cancellation Request for Transmit Buffer 12" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 11. "CR11,Cancellation Request for Transmit Buffer 11" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 10. "CR10,Cancellation Request for Transmit Buffer 10" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 9. "CR9,Cancellation Request for Transmit Buffer 9" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 8. "CR8,Cancellation Request for Transmit Buffer 8" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 7. "CR7,Cancellation Request for Transmit Buffer 7" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 6. "CR6,Cancellation Request for Transmit Buffer 6" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 5. "CR5,Cancellation Request for Transmit Buffer 5" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 4. "CR4,Cancellation Request for Transmit Buffer 4" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 3. "CR3,Cancellation Request for Transmit Buffer 3" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 2. "CR2,Cancellation Request for Transmit Buffer 2" "0: No cancellation pending.,1: Cancellation pending."
|
|
newline
|
|
bitfld.long 0x4 1. "CR1,Cancellation Request for Transmit Buffer 1" "0: No cancellation pending.,1: Cancellation pending."
|
|
bitfld.long 0x4 0. "CR0,Cancellation Request for Transmit Buffer 0" "0: No cancellation pending.,1: Cancellation pending."
|
|
rgroup.long 0xD8++0x7
|
|
line.long 0x0 "TXBTO,Transmit Buffer Transmission Occurred Register"
|
|
bitfld.long 0x0 31. "TO31,Transmission Occurred for Buffer 31" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 30. "TO30,Transmission Occurred for Buffer 30" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 29. "TO29,Transmission Occurred for Buffer 29" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 28. "TO28,Transmission Occurred for Buffer 28" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 27. "TO27,Transmission Occurred for Buffer 27" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 26. "TO26,Transmission Occurred for Buffer 26" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 25. "TO25,Transmission Occurred for Buffer 25" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 24. "TO24,Transmission Occurred for Buffer 24" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 23. "TO23,Transmission Occurred for Buffer 23" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 22. "TO22,Transmission Occurred for Buffer 22" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 21. "TO21,Transmission Occurred for Buffer 21" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 20. "TO20,Transmission Occurred for Buffer 20" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 19. "TO19,Transmission Occurred for Buffer 19" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 18. "TO18,Transmission Occurred for Buffer 18" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 17. "TO17,Transmission Occurred for Buffer 17" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 16. "TO16,Transmission Occurred for Buffer 16" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 15. "TO15,Transmission Occurred for Buffer 15" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 14. "TO14,Transmission Occurred for Buffer 14" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 13. "TO13,Transmission Occurred for Buffer 13" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 12. "TO12,Transmission Occurred for Buffer 12" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 11. "TO11,Transmission Occurred for Buffer 11" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 10. "TO10,Transmission Occurred for Buffer 10" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 9. "TO9,Transmission Occurred for Buffer 9" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 8. "TO8,Transmission Occurred for Buffer 8" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 7. "TO7,Transmission Occurred for Buffer 7" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 6. "TO6,Transmission Occurred for Buffer 6" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 5. "TO5,Transmission Occurred for Buffer 5" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 4. "TO4,Transmission Occurred for Buffer 4" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 3. "TO3,Transmission Occurred for Buffer 3" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 2. "TO2,Transmission Occurred for Buffer 2" "0: No transmission occurred.,1: Transmission occurred."
|
|
newline
|
|
bitfld.long 0x0 1. "TO1,Transmission Occurred for Buffer 1" "0: No transmission occurred.,1: Transmission occurred."
|
|
bitfld.long 0x0 0. "TO0,Transmission Occurred for Buffer 0" "0: No transmission occurred.,1: Transmission occurred."
|
|
line.long 0x4 "TXBCF,Transmit Buffer Cancellation Finished Register"
|
|
bitfld.long 0x4 31. "CF31,Cancellation Finished for Transmit Buffer 31" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 30. "CF30,Cancellation Finished for Transmit Buffer 30" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 29. "CF29,Cancellation Finished for Transmit Buffer 29" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 28. "CF28,Cancellation Finished for Transmit Buffer 28" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 27. "CF27,Cancellation Finished for Transmit Buffer 27" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 26. "CF26,Cancellation Finished for Transmit Buffer 26" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 25. "CF25,Cancellation Finished for Transmit Buffer 25" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 24. "CF24,Cancellation Finished for Transmit Buffer 24" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 23. "CF23,Cancellation Finished for Transmit Buffer 23" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 22. "CF22,Cancellation Finished for Transmit Buffer 22" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 21. "CF21,Cancellation Finished for Transmit Buffer 21" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 20. "CF20,Cancellation Finished for Transmit Buffer 20" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 19. "CF19,Cancellation Finished for Transmit Buffer 19" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 18. "CF18,Cancellation Finished for Transmit Buffer 18" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 17. "CF17,Cancellation Finished for Transmit Buffer 17" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 16. "CF16,Cancellation Finished for Transmit Buffer 16" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 15. "CF15,Cancellation Finished for Transmit Buffer 15" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 14. "CF14,Cancellation Finished for Transmit Buffer 14" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 13. "CF13,Cancellation Finished for Transmit Buffer 13" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 12. "CF12,Cancellation Finished for Transmit Buffer 12" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 11. "CF11,Cancellation Finished for Transmit Buffer 11" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 10. "CF10,Cancellation Finished for Transmit Buffer 10" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 9. "CF9,Cancellation Finished for Transmit Buffer 9" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 8. "CF8,Cancellation Finished for Transmit Buffer 8" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 7. "CF7,Cancellation Finished for Transmit Buffer 7" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 6. "CF6,Cancellation Finished for Transmit Buffer 6" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 5. "CF5,Cancellation Finished for Transmit Buffer 5" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 4. "CF4,Cancellation Finished for Transmit Buffer 4" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 3. "CF3,Cancellation Finished for Transmit Buffer 3" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 2. "CF2,Cancellation Finished for Transmit Buffer 2" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
newline
|
|
bitfld.long 0x4 1. "CF1,Cancellation Finished for Transmit Buffer 1" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
bitfld.long 0x4 0. "CF0,Cancellation Finished for Transmit Buffer 0" "0: No transmit buffer cancellation.,1: Transmit buffer cancellation finished."
|
|
group.long 0xE0++0x7
|
|
line.long 0x0 "TXBTIE,Transmit Buffer Transmission Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable for Buffer 31" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable for Buffer 30" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable for Buffer 29" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable for Buffer 28" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable for Buffer 27" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable for Buffer 26" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable for Buffer 25" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable for Buffer 24" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable for Buffer 23" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable for Buffer 22" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable for Buffer 21" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable for Buffer 20" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable for Buffer 19" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable for Buffer 18" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable for Buffer 17" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable for Buffer 16" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable for Buffer 15" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable for Buffer 14" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable for Buffer 13" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable for Buffer 12" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable for Buffer 11" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable for Buffer 10" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable for Buffer 9" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable for Buffer 8" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable for Buffer 7" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable for Buffer 6" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable for Buffer 5" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable for Buffer 4" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable for Buffer 3" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable for Buffer 2" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
newline
|
|
bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable for Buffer 1" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable for Buffer 0" "0: Transmission interrupt disabled,1: Transmission interrupt enable"
|
|
line.long 0x4 "TXBCIE,Transmit Buffer Cancellation Finished Interrupt Enable Register"
|
|
bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable for Transmit Buffer 31" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable for Transmit Buffer 30" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable for Transmit Buffer 29" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable for Transmit Buffer 28" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable for Transmit Buffer 27" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable for Transmit Buffer 26" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable for Transmit Buffer 25" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable for Transmit Buffer 24" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable for Transmit Buffer 23" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable for Transmit Buffer 22" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable for Transmit Buffer 21" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable for Transmit Buffer 20" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable for Transmit Buffer 19" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable for Transmit Buffer 18" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable for Transmit Buffer 17" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable for Transmit Buffer 16" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable for Transmit Buffer 15" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable for Transmit Buffer 14" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable for Transmit Buffer 13" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable for Transmit Buffer 12" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable for Transmit Buffer 11" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable for Transmit Buffer 10" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable for Transmit Buffer 9" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable for Transmit Buffer 8" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable for Transmit Buffer 7" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable for Transmit Buffer 6" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable for Transmit Buffer 5" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable for Transmit Buffer 4" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable for Transmit Buffer 3" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable for Transmit Buffer 2" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
newline
|
|
bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable for Transmit Buffer 1" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable for Transmit Buffer 0" "0: Cancellation finished interrupt disabled.,1: Cancellation finished interrupt enabled."
|
|
group.long 0xF0++0x3
|
|
line.long 0x0 "TXEFC,Transmit Event FIFO Configuration Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark"
|
|
hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size"
|
|
newline
|
|
hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address"
|
|
rgroup.long 0xF4++0x3
|
|
line.long 0x0 "TXEFS,Transmit Event FIFO Status Register"
|
|
bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write.."
|
|
bitfld.long 0x0 24. "EFF,Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index"
|
|
hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level"
|
|
group.long 0xF8++0x3
|
|
line.long 0x0 "TXEFA,Transmit Event FIFO Acknowledge Register"
|
|
hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index"
|
|
tree.end
|
|
tree.end
|
|
tree "NICGPV (NIC-400 Global Programmers View)"
|
|
base ad:0xE8B00000
|
|
repeat 15. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE)(list ad:0xE8B02000 ad:0xE8B03000 ad:0xE8B04000 ad:0xE8B05000 ad:0xE8B06000 ad:0xE8B07000 ad:0xE8B08000 ad:0xE8B09000 ad:0xE8B0A000 ad:0xE8B0B000 ad:0xE8B0C000 ad:0xE8B0D000 ad:0xE8B0E000 ad:0xE8B0F000 ad:0xE8B10000)
|
|
tree "NICGPV_AMIB[$1]"
|
|
base $2
|
|
group.long ($2+0x8)++0x3
|
|
line.long 0x0 "AMIB_FN_MOD_BM_ISS,AMIB Bus Matrix Issuing Functionality Modification Register"
|
|
bitfld.long 0x0 1. "WRITE_ISS_OVERRIDE,Write Issuing Override" "0: No effect,1: Write issuing capability is limited to one.."
|
|
bitfld.long 0x0 0. "READ_ISS_OVERRIDE,Read Issuing Override" "0: No effect,1: Read issuing capability is limited to one.."
|
|
tree.end
|
|
repeat.end
|
|
repeat 11. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA)(list ad:0xE8B42000 ad:0xE8B43000 ad:0xE8B44000 ad:0xE8B45000 ad:0xE8B46000 ad:0xE8B47000 ad:0xE8B48000 ad:0xE8B49000 ad:0xE8B4A000 ad:0xE8B4B000 ad:0xE8B4C000)
|
|
tree "NICGPV_ASIB[$1]"
|
|
base $2
|
|
group.long ($2+0x100)++0x7
|
|
line.long 0x0 "ASIB_READ_QOS,ASIB Read Channel QoS Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "RD_QOS,Read QoS"
|
|
line.long 0x4 "ASIB_WRITE_QOS,ASIB Write Channel QoS Register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "WR_QOS,Write QoS"
|
|
group.long ($2+0x10C)++0x2F
|
|
line.long 0x0 "ASIB_QOS_CNTL,ASIB QoS Control Register"
|
|
bitfld.long 0x0 20. "MODE_AR_FC,AR Feedback Control Mode" "0: Transaction latency,1: Address latency"
|
|
bitfld.long 0x0 16. "MODE_AW_FC,AW Feedback Control Mode" "0: Transaction latency,1: Address latency"
|
|
newline
|
|
bitfld.long 0x0 7. "EN_AWAR_OT,AWAR Outstanding Transactions Enable" "0: Disable combined regulation of outstanding..,1: Enable combined regulation of outstanding.."
|
|
bitfld.long 0x0 6. "EN_AR_OT,AR Outstanding Transactions Enable" "0: Disable regulation of outstanding read..,1: Enable regulation of outstanding read.."
|
|
newline
|
|
bitfld.long 0x0 5. "EN_AW_OT,AW Outstanding Transactions Enable" "0: Disable regulation of outstanding write..,1: Enable regulation of outstanding write.."
|
|
bitfld.long 0x0 4. "EN_AR_FC,AR Feedback Control Enable" "0: Disable regulation of AR transaction or address..,1: Enable regulation of AR transaction or address.."
|
|
newline
|
|
bitfld.long 0x0 3. "EN_AW_FC,AW Feedback Control Enable" "0: Disable regulation of AW transaction or address..,1: Enable regulation of AW transaction or address.."
|
|
bitfld.long 0x0 2. "EN_AWAR_RATE,AW and AR Rates Enable" "0: Disable combined AW and AR rate regulation.,1: Enable combined AW and AR rate regulation."
|
|
newline
|
|
bitfld.long 0x0 1. "EN_AR_RATE,AR Rate Enable" "0: Disable AR rate regulation.,1: Enable AR rate regulation."
|
|
bitfld.long 0x0 0. "EN_AW_RATE,AW Rate Enable" "0: Disable AW rate regulation.,1: Enable AW rate regulation."
|
|
line.long 0x4 "ASIB_MAX_OT,ASIB Maximum Number of Outstanding Transactions Register"
|
|
hexmask.long.byte 0x4 24.--29. 1. "AR_MAX_OTI,AR Maximum Outstanding Transaction Integer"
|
|
hexmask.long.byte 0x4 16.--23. 1. "AR_MAX_OTF,AR Maximum Outstanding Transaction Fraction"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--13. 1. "AW_MAX_OTI,AW Maximum Outstanding Transaction Integer"
|
|
hexmask.long.byte 0x4 0.--7. 1. "AW_MAX_OTF,AW Maximum Outstanding Transaction Fraction"
|
|
line.long 0x8 "ASIB_MAX_COMB_OT,ASIB Maximum Combined Outstanding Transactions Register"
|
|
hexmask.long.byte 0x8 8.--14. 1. "AWAR_MAX_OTI,AW and AR Combined Maximum Outstanding Transactions Integer"
|
|
hexmask.long.byte 0x8 0.--7. 1. "AWAR_MAX_OTF,AW and AR Combined Maximum Outstanding Transactions Fraction"
|
|
line.long 0xC "ASIB_AW_P,ASIB Write Address Channel Peak Rate Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. "AW_P,AW Channel Peak Rate"
|
|
line.long 0x10 "ASIB_AW_B,ASIB Write Address Channel Burstiness Allowance Register"
|
|
hexmask.long.word 0x10 0.--15. 1. "AW_B,AW Channel Burstiness"
|
|
line.long 0x14 "ASIB_AW_R,ASIB Write Address Channel Average Rate Register"
|
|
hexmask.long.word 0x14 20.--31. 1. "AW_R,AW Channel Average Rate"
|
|
line.long 0x18 "ASIB_AR_P,ASIB Read Address Channel Peak Rate Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. "AR_P,AR Channel Peak Rate"
|
|
line.long 0x1C "ASIB_AR_B,ASIB Read Address Channel Burstiness Allowance Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. "AR_B,AR Channel Burstiness"
|
|
line.long 0x20 "ASIB_AR_R,ASIB Read Address Channel Average Rate Register"
|
|
hexmask.long.word 0x20 20.--31. 1. "AR_R,AR Channel Average Rate"
|
|
line.long 0x24 "ASIB_TARGET_FC,ASIB Feedback Controlled Target Register"
|
|
hexmask.long.word 0x24 16.--27. 1. "AR_TGT_LATENCY,AR Channel Target Latency"
|
|
hexmask.long.word 0x24 0.--11. 1. "AW_TGT_LATENCY,AW Channel Target Latency"
|
|
line.long 0x28 "ASIB_KI_FC,ASIB Feedback Controlled Scale Register"
|
|
bitfld.long 0x28 8.--10. "AR_KI,AW QOS Scale Factor" "0: 2-3,1: 2-4,2: 2-5,3: 2-6,4: 2-7,5: 2-8,6: 2-9,7: 2-10"
|
|
bitfld.long 0x28 0.--2. "AW_KI,AR QOS Scale Factor" "0: 2-3,1: 2-4,2: 2-5,3: 2-6,4: 2-7,5: 2-8,6: 2-9,7: 2-10"
|
|
line.long 0x2C "ASIB_QOS_RANGE,ASIB QoS Range Register"
|
|
hexmask.long.byte 0x2C 24.--27. 1. "AR_MAX_QOS,AR Maximum QOS"
|
|
hexmask.long.byte 0x2C 16.--19. 1. "AR_MIN_QOS,AR Minimum QOS"
|
|
newline
|
|
hexmask.long.byte 0x2C 8.--11. 1. "AW_MAX_QOS,AW Maximum QOS"
|
|
hexmask.long.byte 0x2C 0.--3. 1. "AW_MIN_QOS,AW Minimum QOS"
|
|
tree.end
|
|
repeat.end
|
|
repeat 2. (list 0x0 0x1)(list ad:0xE8BC2000 ad:0xE8BC3000)
|
|
tree "NICGPV_IB[$1]"
|
|
base $2
|
|
group.long ($2+0x8)++0x3
|
|
line.long 0x0 "IB_FN_MOD_BM_ISS,IB Bus Matrix Issuing Functionality Modification Register"
|
|
bitfld.long 0x0 0.--1. "FN_MODE,Issuing Functionality" "0: Read issuing,1: Write issuing,?,?"
|
|
group.long ($2+0x20)++0x7
|
|
line.long 0x0 "IB_SYNC_MODE,IB Clock Boundary Synchronization Scheme Register"
|
|
bitfld.long 0x0 0.--2. "SYNC_MODE,Read Issuing" "0: Sync 1:1,1: Sync m:1,2: Sync 1:n,3: Sync m:n,4: Async.,?,?,?"
|
|
line.long 0x4 "IB_FN_MOD2_BP_MRG,IB Bypass Merge register"
|
|
bitfld.long 0x4 0. "BP_MRG,Bypass Merge" "0,1"
|
|
group.long ($2+0x2C)++0x3
|
|
line.long 0x0 "IB_FN_MOD_LB,IB Long Burst Functionality Modification Register"
|
|
bitfld.long 0x0 0. "LB_MODE,Long Burst Mode" "0: Long bursts cannot be generated at the output of..,1: Long bursts can be generated at the output of.."
|
|
group.long ($2+0x40)++0x3
|
|
line.long 0x0 "IB_WR_TIDEMARK,IB Tidemark Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "WR_TIDEMARK,WR Tidemark Value"
|
|
group.long ($2+0x108)++0x3
|
|
line.long 0x0 "IB_FN_MOD,IB Issuing Functionality Modification Register"
|
|
bitfld.long 0x0 0.--1. "FN_MODE,Issuing Functionality Mode" "0: Read issuing,1: Write issuing,?,?"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "OTPC (OTP Memory Controller)"
|
|
base ad:0xE8C00000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Programming Key"
|
|
bitfld.long 0x0 15. "REFRESH,Refresh the Area" "0: No effect.,1: Starts a refresh of the area."
|
|
newline
|
|
bitfld.long 0x0 9. "KBSTOP,Key Bus Transfer Stop" "0: No effect.,1: Stops an on-going transfer on the Master Key bus."
|
|
bitfld.long 0x0 8. "KBSTART,Key Bus Transfer Start" "0: No effect.,1: Starts a transfer through the Master Key bus."
|
|
newline
|
|
bitfld.long 0x0 7. "FLUSH,Flush Temporary Registers" "0: No effect.,1: Starts a flush of the temporary registers used.."
|
|
bitfld.long 0x0 6. "READ,Read Packet" "0: No effect.,1: Starts a read sequence of the selected packet."
|
|
newline
|
|
bitfld.long 0x0 4. "HIDE,Hide Packet" "0: No effect.,1: The selected packet is not readable anymore.."
|
|
bitfld.long 0x0 2. "INVLD,Invalidate Packet" "0: No effect.,1: Invalidates the selected packet."
|
|
newline
|
|
bitfld.long 0x0 1. "CKSGEN,Generate Checksum" "0: No effect.,1: Generates and programs the selected packet.."
|
|
bitfld.long 0x0 0. "PGM,Program Packet" "0: No effect.,1: The selected packet is written."
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "MR,Mode Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "ADDR,Address"
|
|
bitfld.long 0x0 15. "LOCK,Lock Register" "0: The OTPC_MR register is unlocked; write access..,1: The OTPC_MR register is locked; write access.."
|
|
newline
|
|
bitfld.long 0x0 12.--13. "KBDST,Key Bus Destination" "0: No destination selected (no transfer can occur).,1: The AES is the destination of the key transfer.,2: The TrustZone AES Bridge is the destination of..,3: The TDES is the destination of the key transfer."
|
|
bitfld.long 0x0 9. "WRDIS,Write Disable" "0: The write capability of the OTPC_DR register is..,1: The write capability of the OTPC_DR register is.."
|
|
newline
|
|
bitfld.long 0x0 8. "RDDIS,Read Disable" "0: The read capability of the OTPC_HR and OTPC_DR..,1: The read capability of the OTPC_HR and OTPC_DR.."
|
|
bitfld.long 0x0 7. "EMUL,Emulation Enable" "0: The Emulation mode of the User area is disabled..,1: The Emulation mode of the User area is enabled.."
|
|
newline
|
|
bitfld.long 0x0 4. "NPCKT,New Packet" "0: Updates the packet defined at the ADDR address.,1: Creates a new packet."
|
|
bitfld.long 0x0 0. "UHCRRDIS,User Hardware Configuration Register Read Disable" "0: The User Hardware Configuration register can be..,1: The User Hardware Configuration register cannot.."
|
|
line.long 0x4 "AR,Address Register"
|
|
bitfld.long 0x4 16. "INCRT,Increment Type" "0: Increment DADDR after a read of OTPC_DR.,1: Increment DADDR after a write of OTPC_DR."
|
|
hexmask.long.byte 0x4 0.--7. 1. "DADDR,Data Address"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 9. "ONEF,One Found" "0: No bit at '1' found during the last packet read.,1: At least one '1' has been found during the last.."
|
|
bitfld.long 0x0 8. "HIDE,Hiding On-Going" "0: No packet hiding is on-going.,1: A packet hiding is on-going."
|
|
newline
|
|
bitfld.long 0x0 7. "FLUSH,Flush On-Going" "0: The temporary registers are not flushed.,1: The temporary registers are being flushed."
|
|
bitfld.long 0x0 6. "READ,Read On-Going" "0: No packet read is on-going.,1: A packet read is running."
|
|
newline
|
|
bitfld.long 0x0 5. "SKBB,Slave Key Bus Busy" "0: The Slave Key bus is not busy.,1: The Slave Key bus is busy."
|
|
bitfld.long 0x0 4. "MKBB,Master Key Bus Busy" "0: The Master Key bus is not busy.,1: The Master Key bus is busy."
|
|
newline
|
|
bitfld.long 0x0 3. "EMUL,Emulation Enabled" "0: The User area Emulation mode is disabled.,1: The User area Emulation mode is enabled."
|
|
bitfld.long 0x0 2. "INVLD,Invalidation On-Going" "0: No packet invalidation is on-going.,1: A packet invalidation is running."
|
|
newline
|
|
bitfld.long 0x0 1. "LOCK,Lock On-Going" "0: No packet locking is on-going.,1: A packet locking is running."
|
|
bitfld.long 0x0 0. "PGM,Programming On-Going" "0: No packet programming is on-going.,1: A packet programming is running."
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 28. "SECE,Security and/or Safety Event Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 16. "KBERR,Key Bus Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "HDERR,Hide Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 13. "COERR,Corruption Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "CKERR,Checksum Check Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 11. "EORF,End Of Refresh Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EOH,End Of Hide Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 9. "EOF,End Of Flush Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "EOR,End Of Read Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 7. "WERR,Write Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "IVERR,Invalidation Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 5. "LKERR,Locking Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PGERR,Programming Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 3. "EOKT,End Of Key Transfer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EOI,End Of Invalidation Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "EOL,End Of Locking Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EOP,End Of Programming Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 28. "SECE,Security and/or Safety Event Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 16. "KBERR,Key Bus Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "HDERR,Hide Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 13. "COERR,Corruption Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CKERR,Checksum Check Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 11. "EORF,End Of Refresh Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "EOH,End Of Hide Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 9. "EOF,End Of Flush Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "EOR,End Of Read Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 7. "WERR,Write Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "IVERR,Invalidation Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 5. "LKERR,Locking Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "PGERR,Programming Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 3. "EOKT,End Of Key Transfer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "EOI,End Of Invalidation Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 1. "EOL,End Of Locking Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "EOP,End Of Programming Interrupt Disable" "0,1"
|
|
rgroup.long 0x18++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 28. "SECE,Security and/or Safety Event Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 16. "KBERR,Key Bus Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "HDERR,Hide Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 13. "COERR,Corruption Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "CKERR,Checksum Check Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 11. "EORF,End Of Refresh Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EOH,End Of Hide Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 9. "EOF,End Of Flush Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "EOR,End Of Read Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 7. "WERR,Write Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "IVERR,Invalidation Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 5. "LKERR,Locking Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PGERR,Programming Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 3. "EOKT,End Of Key Transfer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EOI,End Of Invalidation Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 1. "EOL,End Of Locking Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EOP,End Of Programming Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 28. "SECE,Security and/or Safety Event (cleared on read)" "0: No security or safety event occurred since the..,1: One or more safety or security event occurred.."
|
|
bitfld.long 0x4 16. "KBERR,Key Bus Error (cleared on read)" "0: No error happened on the Key bus since the last..,1: An error happened on the Key bus since the last.."
|
|
newline
|
|
bitfld.long 0x4 14. "HDERR,Hide Error (cleared on read)" "0: No hiding error occurred since the last read of..,1: A hiding error occurred since the last read of.."
|
|
bitfld.long 0x4 13. "COERR,Corruption Error (cleared on read)" "0: No corruption occurred during the last start-up..,1: A corruption occurred since the last read of.."
|
|
newline
|
|
bitfld.long 0x4 12. "CKERR,Checksum Check Error (cleared on read)" "0: No checksum check failure occurred during last..,1: A checksum check failure occurred since the last.."
|
|
bitfld.long 0x4 11. "EORF,End Of Refresh (cleared on read)" "0: No refresh sequence completion since the last..,1: At least one refresh sequence completion since.."
|
|
newline
|
|
bitfld.long 0x4 10. "EOH,End Of Hide (cleared on read)" "0: No hiding sequence completion since the last..,1: At least one hiding sequence completion since.."
|
|
bitfld.long 0x4 9. "EOF,End Of Flush (cleared on read)" "0: No flush of the temporary registers since the..,1: At least one flush hof the temporary registers.."
|
|
newline
|
|
bitfld.long 0x4 8. "EOR,End Of Read (cleared on read)" "0: No reading sequence completion since the last..,1: At least one reading sequence completion since.."
|
|
bitfld.long 0x4 7. "WERR,Write Error (cleared on read)" "0: No write error occurred since the last read of..,1: A write error occurred since the last read of.."
|
|
newline
|
|
bitfld.long 0x4 6. "IVERR,Invalidation Error (cleared on read)" "0: No invalidation failure occurred during last..,1: A invalidation failure occurred since the last.."
|
|
bitfld.long 0x4 5. "LKERR,Locking Error (cleared on read)" "0: No locking failure occurred during last locking..,1: A locking failure occurred since the last read.."
|
|
newline
|
|
bitfld.long 0x4 4. "PGERR,Programming Error (cleared on read)" "0: No programming failure occurred during last..,1: A programming failure occurred since the last.."
|
|
bitfld.long 0x4 3. "EOKT,End Of Key Transfer (cleared on read)" "0: No key transfer completion since the last read..,1: At least one key transfer has been completed on.."
|
|
newline
|
|
bitfld.long 0x4 2. "EOI,End Of Invalidation (cleared on read)" "0: No invalidation sequence completion since the..,1: At least one invalidation sequence completion.."
|
|
bitfld.long 0x4 1. "EOL,End Of Locking (cleared on read)" "0: No locking sequence completion since the last..,1: At least one locking sequence completion since.."
|
|
newline
|
|
bitfld.long 0x4 0. "EOP,End Of Programming (cleared on read)" "0: No programming sequence completion since the..,1: At least one programming sequence completion.."
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "HR,Header Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "CHECKSUM,Packet Checksum"
|
|
hexmask.long.byte 0x0 8.--15. 1. "SIZE,Packet Size"
|
|
newline
|
|
bitfld.long 0x0 7. "ONE,One" "0,1"
|
|
bitfld.long 0x0 6. "SECURE,Secure Packet" "0: The packet is not part of the secure world.,1: The packet is part of the secure world."
|
|
newline
|
|
bitfld.long 0x0 4.--5. "INVLD,Invalid Status" "0,1,2,3"
|
|
bitfld.long 0x0 3. "LOCK,Lock Status" "0: The packet is not locked.,1: The packet is locked."
|
|
newline
|
|
bitfld.long 0x0 0.--2. "PACKET,Packet Type" "?,1: Regular packet accessible through the User..,2: Key packet accessible only through the Key Buses,3: Boot Configuration packet,4: Secure Boot Configuration packet,5: Hardware Configuration packet,6: Custom packet,?"
|
|
line.long 0x4 "DR,Data Register"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Packet Data"
|
|
rgroup.long 0x30++0xB
|
|
line.long 0x0 "BAR,Boot Addresses Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "SBCADDR,Secure Boot Configuration Address"
|
|
hexmask.long.word 0x0 0.--15. 1. "BCADDR,Boot Configuration Address"
|
|
line.long 0x4 "CAR,Custom Address Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "CADDR,Custom Address"
|
|
line.long 0x8 "SCAR,Secure Custom Address Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "SCADDR,Secure Custom Address"
|
|
rgroup.long 0x50++0x7
|
|
line.long 0x0 "UHC0R,User Hardware Configuration 0 Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "SECDBG,Secure Debug"
|
|
hexmask.long.byte 0x0 0.--7. 1. "JTAGDIS,JTAG Disable"
|
|
line.long 0x4 "UHC1R,User Hardware Configuration 1 Register"
|
|
bitfld.long 0x4 17. "URFDIS,User Refresh Disable" "0: The OTPC_CR.REFRESH bit is fully functional.,1: The OTPC_CR.REFRESH bit is only functional in.."
|
|
bitfld.long 0x4 16. "CPGDIS,Custom Packet Program Disable" "0: The programming of Custom Special Packet is..,1: The programming of Custom Special Packet is.."
|
|
newline
|
|
bitfld.long 0x4 15. "CLKDIS,Custom Packet Lock Disable" "0: The generation of the checksum (lock) of the..,1: The generation of the checksum (lock) of the.."
|
|
bitfld.long 0x4 14. "CINVDIS,Custom Packet Invalidation Disable" "0: The invalidation of the Custom Special Packet is..,1: The invalidation of the Custom Special Packet is.."
|
|
newline
|
|
bitfld.long 0x4 13. "SCPGDIS,Secure Custom Packet Program Disable" "0: The programming of Secure Custom Special Packet..,1: The programming of Secure Custom Special Packet.."
|
|
bitfld.long 0x4 12. "SCLKDIS,Secure Custom Packet Lock Disable" "0: The generation of the checksum (lock) of the..,1: The generation of the checksum (lock) of the.."
|
|
newline
|
|
bitfld.long 0x4 11. "SCINVDIS,Secure Custom Packet Invalidation Disable" "0: The invalidation of the Secure Custom Special..,1: The invalidation of the Secure Custom Special.."
|
|
bitfld.long 0x4 10. "SBCPGDIS,Secure Boot Configuration Packet Program Disable" "0: The programming of Secure Boot Configuration..,1: The programming of Secure Boot Configuration.."
|
|
newline
|
|
bitfld.long 0x4 9. "SBCLKDIS,Secure Boot Configuration Packet Lock Disable" "0: The generation of the checksum (lock) of the..,1: The generation of the checksum (lock) of the.."
|
|
bitfld.long 0x4 8. "SBCINVDIS,Secure Boot Configuration Packet Invalidation Disable" "0: The invalidation of the Secure Boot..,1: The invalidation of the Secure Boot.."
|
|
newline
|
|
bitfld.long 0x4 7. "BCPGDIS,Boot Configuration Packet Program Disable" "0: The programming of Boot Configuration Special..,1: The programming of Boot Configuration Special.."
|
|
bitfld.long 0x4 6. "BCLKDIS,Boot Configuration Packet Lock Disable" "0: The generation of the checksum (lock) of the..,1: The generation of the checksum (lock) of the.."
|
|
newline
|
|
bitfld.long 0x4 5. "BCINVDIS,Boot Configuration Packet Invalidation Disable" "0: The invalidation of the Boot Configuration..,1: The invalidation of the Boot Configuration.."
|
|
bitfld.long 0x4 4. "UHCPGDIS,User Hardware Configuration Packet Program Disable" "0: The programming of User Hardware Configuration..,1: The programming of User Hardware Configuration.."
|
|
newline
|
|
bitfld.long 0x4 3. "UHCLKDIS,User Hardware Configuration Packet Lock Disable" "0: The generation of the checksum (lock) of the..,1: The generation of the checksum (lock) of the.."
|
|
bitfld.long 0x4 2. "UHCINVDIS,User Hardware Configuration Packet Invalidation Disable" "0: The invalidation of the User Hardware..,1: The invalidation of the User Hardware.."
|
|
newline
|
|
bitfld.long 0x4 1. "UPGDIS,User programming Disable" "0: The OTPC_CR.PGM bit is fully functional.,1: The OTPC_CR.PGM bit is not functional."
|
|
bitfld.long 0x4 0. "URDDIS,User Read Disable" "0: The OTPC_CR.READ bit is fully functional.,1: The OTPC_CR.READ bit is not functional."
|
|
rgroup.long 0x60++0xF
|
|
line.long 0x0 "UID0R,Product UID 0 Register"
|
|
hexmask.long 0x0 0.--31. 1. "UID,Unique Product ID"
|
|
line.long 0x4 "UID1R,Product UID 1 Register"
|
|
hexmask.long 0x4 0.--31. 1. "UID,Unique Product ID"
|
|
line.long 0x8 "UID2R,Product UID 2 Register"
|
|
hexmask.long 0x8 0.--31. 1. "UID,Unique Product ID"
|
|
line.long 0xC "UID3R,Product UID 3 Register"
|
|
hexmask.long 0xC 0.--31. 1. "UID,Unique Product ID"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 4. "FIRSTE,First Error Report Enable" "0: The last write protection violation source is..,1: Only the first write protection violation source.."
|
|
newline
|
|
bitfld.long 0x0 2. "WPCTEN,Write Protection Control Enable" "0: Disables the write protection of the control if..,1: Enables the write protection of the control if.."
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection of the..,1: Enables the write protection of the interruption.."
|
|
newline
|
|
bitfld.long 0x0 0. "WPCFEN,Write Protection Configuration Enable" "0: Disables the write protection of the..,1: Enables the write protection of the.."
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
bitfld.long 0x0 31. "ECLASS,Software Error Class" "0: An abnormal access that does not have any impact.,1: An abnormal access that may have an impact."
|
|
hexmask.long.byte 0x0 24.--27. 1. "SWETYP,Software Error Type"
|
|
newline
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 3. "SWE,Software Control Error (cleared on read)" "0: No software error has occurred since the last..,1: A software error has occurred since the last.."
|
|
newline
|
|
bitfld.long 0x0 2. "SEQE,Internal Sequencer Error (cleared on read)" "0: No peripheral internal sequencer error has..,1: A peripheral internal sequencer error has.."
|
|
bitfld.long 0x0 1. "CGD,Clock Glitch Detected (cleared on read)" "0: No clock glitch has occurred since the last read..,1: A clock glitch has occurred since the last read.."
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status (cleared on read)" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
|
|
tree.end
|
|
tree "PDMC (Pulse Density Microphone Controller)"
|
|
base ad:0x0
|
|
tree "PDMC0"
|
|
base ad:0xE1608000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0: No effect.,1: Resets the PDMC interface."
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "MR,Mode Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "CHUNK,Chunk Size"
|
|
hexmask.long.byte 0x0 24.--27. 1. "SINC_OSR,SINC Filter Oversampling Ratio"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SINCORDER,SINC Filter Order"
|
|
bitfld.long 0x0 16.--17. "OSR,Audio Oversampling Ratio" "?,1: OSR is 64.,2: OSR is 128.,3: OSR is 256."
|
|
newline
|
|
bitfld.long 0x0 3. "PDMCEN3,PDMC Channel 3 Enable" "0: PDMC is disabled.,1: PDMC is enabled."
|
|
bitfld.long 0x0 2. "PDMCEN2,PDMC Channel 2 Enable" "0: PDMC is disabled.,1: PDMC is enabled."
|
|
newline
|
|
bitfld.long 0x0 1. "PDMCEN1,PDMC Channel 1 Enable" "0: PDMC is disabled.,1: PDMC is enabled."
|
|
bitfld.long 0x0 0. "PDMCEN0,PDMC Channel 0 Enable" "0: PDMC is disabled.,1: PDMC is enabled."
|
|
line.long 0x4 "CFGR,Configuration Register"
|
|
bitfld.long 0x4 22. "PDMSEL3,PDM Microphone Source Selection" "0: PDMSELx corresponds to PMDC_DS0.,1: PDMSELx corresponds to PMDC_DS1."
|
|
bitfld.long 0x4 20. "PDMSEL2,PDM Microphone Source Selection" "0: PDMSELx corresponds to PMDC_DS0.,1: PDMSELx corresponds to PMDC_DS1."
|
|
newline
|
|
bitfld.long 0x4 18. "PDMSEL1,PDM Microphone Source Selection" "0: PDMSELx corresponds to PMDC_DS0.,1: PDMSELx corresponds to PMDC_DS1."
|
|
bitfld.long 0x4 16. "PDMSEL0,PDM Microphone Source Selection" "0: PDMSELx corresponds to PMDC_DS0.,1: PDMSELx corresponds to PMDC_DS1."
|
|
newline
|
|
bitfld.long 0x4 6. "BSSEL3,Bitstream Source Selection" "0: The selected PDMC_DSx source is sampled on..,1: The selected PDMC_DSx source is sampled on.."
|
|
bitfld.long 0x4 4. "BSSEL2,Bitstream Source Selection" "0: The selected PDMC_DSx source is sampled on..,1: The selected PDMC_DSx source is sampled on.."
|
|
newline
|
|
bitfld.long 0x4 2. "BSSEL1,Bitstream Source Selection" "0: The selected PDMC_DSx source is sampled on..,1: The selected PDMC_DSx source is sampled on.."
|
|
bitfld.long 0x4 0. "BSSEL0,Bitstream Source Selection" "0: The selected PDMC_DSx source is sampled on..,1: The selected PDMC_DSx source is sampled on.."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "RHR,Receive Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CHANNEL,Channel Index of Data"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Converted Data"
|
|
wgroup.long 0x14++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 28. "WPERR,Write Protection Error Enable" "0,1"
|
|
bitfld.long 0x0 5. "RXOVR,Receive Over Flow Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXUDR,Receive Under Flow Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 3. "RXCHUNK,Receive FIFO Chunk Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXFULL,Receive FIFO Full Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "RXEMPTY,Receive FIFO Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,Receive Ready Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 28. "WPERR,Write Protection Error Disable" "0,1"
|
|
bitfld.long 0x4 5. "RXOVR,Receive Over Flow Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXUDR,Receive Under Flow Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 3. "RXCHUNK,Receive FIFO Chunk Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXFULL,Receive FIFO Full Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 1. "RXEMPTY,Receive FIFO Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,Receive Ready Interrupt Disable" "0,1"
|
|
rgroup.long 0x1C++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 28. "WPERR,Write Protection Error Mask" "0,1"
|
|
bitfld.long 0x0 5. "RXOVR,Receive Over Flow Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXUDR,Receive Under Flow Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 3. "RXCHUNK,Receive FIFO Chunk Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXFULL,Receive FIFO Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 1. "RXEMPTY,Receive FIFO Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,Receive Ready Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 28. "WPERR,Write Protection Error Status (cleared on read)" "0: No write protection error event occurred since..,1: At least one write protection error event.."
|
|
bitfld.long 0x4 18. "SECE,Security and/or Safety Event (cleared on read)" "0: No security or safety event has occurred since..,1: One or more safety or security event occurred.."
|
|
newline
|
|
bitfld.long 0x4 5. "RXOVR,Receive Over Flow Interrupt Status (cleared on read)" "0: No overflow event occurred since the last read..,1: At least one overflow event occurred since the.."
|
|
bitfld.long 0x4 4. "RXUDR,Receive Under Flow Interrupt Status (cleared on read)" "0: No underflow event occurred since the last read..,1: At least one underflow event occurred since the.."
|
|
newline
|
|
bitfld.long 0x4 3. "RXCHUNK,Receive FIFO Chunk Interrupt Status" "0: There is less than PDMC_MR.CHUNK data in the RX..,1: At least PDMC_MR.CHUNK data can be read in the.."
|
|
bitfld.long 0x4 2. "RXFULL,Receive FIFO Full Interrupt Status" "0: The RX FIFO is not full and can still receive..,1: The RX FIFO is full and cannot receive more data."
|
|
newline
|
|
bitfld.long 0x4 1. "RXEMPTY,Receive FIFO Empty Interrupt Status" "0: At least one data is in the RX FIFO.,1: The RX FIFO is empty."
|
|
bitfld.long 0x4 0. "RXRDY,Receive Ready Interrupt Status" "0: There is no data in the RX FIFO.,1: At least one data is in the RX FIFO and can be.."
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables write protection if WPKEY corresponds..,1: Enables write protection if WPKEY corresponds to.."
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPSRC,Write Protection Source"
|
|
bitfld.long 0x0 2. "SEQE,Internal Sequencer Error" "0: No peripheral internal sequencer error has..,1: A peripheral internal sequencer error has.."
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
|
|
tree.end
|
|
tree "PDMC1"
|
|
base ad:0xE160C000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0: No effect.,1: Resets the PDMC interface."
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "MR,Mode Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "CHUNK,Chunk Size"
|
|
hexmask.long.byte 0x0 24.--27. 1. "SINC_OSR,SINC Filter Oversampling Ratio"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SINCORDER,SINC Filter Order"
|
|
bitfld.long 0x0 16.--17. "OSR,Audio Oversampling Ratio" "?,1: OSR is 64.,2: OSR is 128.,3: OSR is 256."
|
|
newline
|
|
bitfld.long 0x0 3. "PDMCEN3,PDMC Channel 3 Enable" "0: PDMC is disabled.,1: PDMC is enabled."
|
|
bitfld.long 0x0 2. "PDMCEN2,PDMC Channel 2 Enable" "0: PDMC is disabled.,1: PDMC is enabled."
|
|
newline
|
|
bitfld.long 0x0 1. "PDMCEN1,PDMC Channel 1 Enable" "0: PDMC is disabled.,1: PDMC is enabled."
|
|
bitfld.long 0x0 0. "PDMCEN0,PDMC Channel 0 Enable" "0: PDMC is disabled.,1: PDMC is enabled."
|
|
line.long 0x4 "CFGR,Configuration Register"
|
|
bitfld.long 0x4 22. "PDMSEL3,PDM Microphone Source Selection" "0: PDMSELx corresponds to PMDC_DS0.,1: PDMSELx corresponds to PMDC_DS1."
|
|
bitfld.long 0x4 20. "PDMSEL2,PDM Microphone Source Selection" "0: PDMSELx corresponds to PMDC_DS0.,1: PDMSELx corresponds to PMDC_DS1."
|
|
newline
|
|
bitfld.long 0x4 18. "PDMSEL1,PDM Microphone Source Selection" "0: PDMSELx corresponds to PMDC_DS0.,1: PDMSELx corresponds to PMDC_DS1."
|
|
bitfld.long 0x4 16. "PDMSEL0,PDM Microphone Source Selection" "0: PDMSELx corresponds to PMDC_DS0.,1: PDMSELx corresponds to PMDC_DS1."
|
|
newline
|
|
bitfld.long 0x4 6. "BSSEL3,Bitstream Source Selection" "0: The selected PDMC_DSx source is sampled on..,1: The selected PDMC_DSx source is sampled on.."
|
|
bitfld.long 0x4 4. "BSSEL2,Bitstream Source Selection" "0: The selected PDMC_DSx source is sampled on..,1: The selected PDMC_DSx source is sampled on.."
|
|
newline
|
|
bitfld.long 0x4 2. "BSSEL1,Bitstream Source Selection" "0: The selected PDMC_DSx source is sampled on..,1: The selected PDMC_DSx source is sampled on.."
|
|
bitfld.long 0x4 0. "BSSEL0,Bitstream Source Selection" "0: The selected PDMC_DSx source is sampled on..,1: The selected PDMC_DSx source is sampled on.."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "RHR,Receive Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CHANNEL,Channel Index of Data"
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|
hexmask.long.tbyte 0x0 0.--23. 1. "DATA,Converted Data"
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|
wgroup.long 0x14++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
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|
bitfld.long 0x0 28. "WPERR,Write Protection Error Enable" "0,1"
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|
bitfld.long 0x0 5. "RXOVR,Receive Over Flow Interrupt Enable" "0,1"
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|
newline
|
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bitfld.long 0x0 4. "RXUDR,Receive Under Flow Interrupt Enable" "0,1"
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|
bitfld.long 0x0 3. "RXCHUNK,Receive FIFO Chunk Interrupt Enable" "0,1"
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|
newline
|
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bitfld.long 0x0 2. "RXFULL,Receive FIFO Full Interrupt Enable" "0,1"
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|
bitfld.long 0x0 1. "RXEMPTY,Receive FIFO Empty Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,Receive Ready Interrupt Enable" "0,1"
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|
line.long 0x4 "IDR,Interrupt Disable Register"
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|
bitfld.long 0x4 28. "WPERR,Write Protection Error Disable" "0,1"
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|
bitfld.long 0x4 5. "RXOVR,Receive Over Flow Interrupt Disable" "0,1"
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|
newline
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bitfld.long 0x4 4. "RXUDR,Receive Under Flow Interrupt Disable" "0,1"
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|
bitfld.long 0x4 3. "RXCHUNK,Receive FIFO Chunk Interrupt Disable" "0,1"
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|
newline
|
|
bitfld.long 0x4 2. "RXFULL,Receive FIFO Full Interrupt Disable" "0,1"
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|
bitfld.long 0x4 1. "RXEMPTY,Receive FIFO Empty Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 0. "RXRDY,Receive Ready Interrupt Disable" "0,1"
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|
rgroup.long 0x1C++0x7
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|
line.long 0x0 "IMR,Interrupt Mask Register"
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|
bitfld.long 0x0 28. "WPERR,Write Protection Error Mask" "0,1"
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|
bitfld.long 0x0 5. "RXOVR,Receive Over Flow Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 4. "RXUDR,Receive Under Flow Interrupt Mask" "0,1"
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|
bitfld.long 0x0 3. "RXCHUNK,Receive FIFO Chunk Interrupt Mask" "0,1"
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|
newline
|
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bitfld.long 0x0 2. "RXFULL,Receive FIFO Full Interrupt Mask" "0,1"
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|
bitfld.long 0x0 1. "RXEMPTY,Receive FIFO Empty Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,Receive Ready Interrupt Mask" "0,1"
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|
line.long 0x4 "ISR,Interrupt Status Register"
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bitfld.long 0x4 28. "WPERR,Write Protection Error Status (cleared on read)" "0: No write protection error event occurred since..,1: At least one write protection error event.."
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|
bitfld.long 0x4 18. "SECE,Security and/or Safety Event (cleared on read)" "0: No security or safety event has occurred since..,1: One or more safety or security event occurred.."
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newline
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bitfld.long 0x4 5. "RXOVR,Receive Over Flow Interrupt Status (cleared on read)" "0: No overflow event occurred since the last read..,1: At least one overflow event occurred since the.."
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bitfld.long 0x4 4. "RXUDR,Receive Under Flow Interrupt Status (cleared on read)" "0: No underflow event occurred since the last read..,1: At least one underflow event occurred since the.."
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newline
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bitfld.long 0x4 3. "RXCHUNK,Receive FIFO Chunk Interrupt Status" "0: There is less than PDMC_MR.CHUNK data in the RX..,1: At least PDMC_MR.CHUNK data can be read in the.."
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bitfld.long 0x4 2. "RXFULL,Receive FIFO Full Interrupt Status" "0: The RX FIFO is not full and can still receive..,1: The RX FIFO is full and cannot receive more data."
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newline
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bitfld.long 0x4 1. "RXEMPTY,Receive FIFO Empty Interrupt Status" "0: At least one data is in the RX FIFO.,1: The RX FIFO is empty."
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bitfld.long 0x4 0. "RXRDY,Receive Ready Interrupt Status" "0: There is no data in the RX FIFO.,1: At least one data is in the RX FIFO and can be.."
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group.long 0x2C++0x3
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line.long 0x0 "WPMR,Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
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newline
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables write protection if WPKEY corresponds..,1: Enables write protection if WPKEY corresponds to.."
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rgroup.long 0x30++0x3
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line.long 0x0 "WPSR,Write Protection Status Register"
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hexmask.long.word 0x0 8.--23. 1. "WPSRC,Write Protection Source"
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bitfld.long 0x0 2. "SEQE,Internal Sequencer Error" "0: No peripheral internal sequencer error has..,1: A peripheral internal sequencer error has.."
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newline
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
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tree.end
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tree.end
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tree "PIO (Parallel Input/Output Controller)"
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base ad:0xE0014000
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repeat 5. (list 0x0 0x1 0x2 0x3 0x4)(list ad:0xE0014000 ad:0xE0014040 ad:0xE0014080 ad:0xE00140C0 ad:0xE0014100)
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tree "PIO_GROUP[$1]"
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base $2
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group.long ($2)++0x7
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line.long 0x0 "MSKR,PIO Mask Register"
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bitfld.long 0x0 31. "MSK31,PIO Line y Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 30. "MSK30,PIO Line y Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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newline
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bitfld.long 0x0 29. "MSK29,PIO Line y Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 28. "MSK28,PIO Line y Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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newline
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bitfld.long 0x0 27. "MSK27,PIO Line y Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 26. "MSK26,PIO Line y Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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newline
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bitfld.long 0x0 25. "MSK25,PIO Line y Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 24. "MSK24,PIO Line y Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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newline
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bitfld.long 0x0 23. "MSK23,PIO Line y Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 22. "MSK22,PIO Line y Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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newline
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bitfld.long 0x0 21. "MSK21,PIO Line y Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 20. "MSK20,PIO Line y Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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newline
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bitfld.long 0x0 19. "MSK19,PIO Line y Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 18. "MSK18,PIO Line y Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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newline
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bitfld.long 0x0 17. "MSK17,PIO Line y Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 16. "MSK16,PIO Line y Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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newline
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bitfld.long 0x0 15. "MSK15,PIO Line y Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 14. "MSK14,PIO Line y Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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newline
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bitfld.long 0x0 13. "MSK13,PIO Line y Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 12. "MSK12,PIO Line y Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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newline
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bitfld.long 0x0 11. "MSK11,PIO Line y Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 10. "MSK10,PIO Line y Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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newline
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bitfld.long 0x0 9. "MSK9,PIO Line y Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 8. "MSK8,PIO Line y Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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newline
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bitfld.long 0x0 7. "MSK7,PIO Line y Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 6. "MSK6,PIO Line y Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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newline
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bitfld.long 0x0 5. "MSK5,PIO Line y Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 4. "MSK4,PIO Line y Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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newline
|
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bitfld.long 0x0 3. "MSK3,PIO Line y Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 2. "MSK2,PIO Line y Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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newline
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bitfld.long 0x0 1. "MSK1,PIO Line y Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 0. "MSK0,PIO Line y Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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line.long 0x4 "CFGR,PIO Configuration Register"
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bitfld.long 0x4 30. "ICFS,Interrupt Configuration Freeze Status (read-only)" "0: The fields are not frozen and can be written for..,1: The fields are frozen and cannot be written for.."
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bitfld.long 0x4 29. "PCFS,Physical Configuration Freeze Status (read-only)" "0: The fields are not frozen and can be written for..,1: The fields are frozen and cannot be written for.."
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newline
|
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bitfld.long 0x4 24.--26. "EVTSEL,Event Selection" "0: Event detection on input falling edge,1: Event detection on input rising edge,2: Event detection on input both edge,3: Event detection on low level input,4: Event detection on high level input,?,?,?"
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bitfld.long 0x4 16.--17. "DRVSTR,Drive Strength" "0: Low drive,1: Low drive,2: Medium drive,3: High drive"
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newline
|
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bitfld.long 0x4 15. "SCHMITT,Schmitt Trigger" "0: Schmitt trigger is enabled for the selected I/O..,1: Schmitt trigger is disabled for the selected I/O.."
|
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bitfld.long 0x4 14. "OPD,Open-Drain" "0: The open-drain is disabled for the selected I/O..,1: The open-drain is enabled for the selected I/O.."
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|
newline
|
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bitfld.long 0x4 13. "IFSCEN,Input Filter Slow Clock Enable" "0: The glitch filter is able to filter glitches..,1: The debouncing filter is able to filter pulses.."
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bitfld.long 0x4 12. "IFEN,Input Filter Enable" "0: The input filter is disabled for the selected..,1: The input filter is enabled for the selected I/O.."
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newline
|
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bitfld.long 0x4 11. "SR,Slew Rate" "0: Slew rate control is disabled for the selected..,1: Slew rate control is enabled for the selected.."
|
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bitfld.long 0x4 10. "PDEN,Pull-Down Enable" "0: Pull-Down is disabled for the selected I/O lines.,1: Pull-Down is enabled for the selected I/O lines.."
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newline
|
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bitfld.long 0x4 9. "PUEN,Pull-Up Enable" "0: Pull-Up is disabled for the selected I/O lines.,1: Pull-Up is enabled for the selected I/O lines."
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bitfld.long 0x4 8. "DIR,Direction" "0: The selected I/O lines are pure inputs.,1: The selected I/O lines are enabled in output."
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newline
|
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bitfld.long 0x4 0.--2. "FUNC,I/O Line Function" "0: Select the PIO mode for the selected I/O lines.,1: Select the peripheral A for the selected I/O..,2: Select the peripheral B for the selected I/O..,3: Select the peripheral C for the selected I/O..,4: Select the peripheral D for the selected I/O..,5: Select the peripheral E for the selected I/O..,6: Select the peripheral F for the selected I/O..,7: Select the peripheral G for the selected I/O.."
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rgroup.long ($2+0x8)++0x7
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line.long 0x0 "PDSR,PIO Pin Data Status Register"
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bitfld.long 0x0 31. "P31,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 30. "P30,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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newline
|
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bitfld.long 0x0 29. "P29,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 28. "P28,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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newline
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bitfld.long 0x0 27. "P27,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 26. "P26,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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newline
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bitfld.long 0x0 25. "P25,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 24. "P24,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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newline
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bitfld.long 0x0 23. "P23,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 22. "P22,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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newline
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bitfld.long 0x0 21. "P21,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 20. "P20,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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newline
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bitfld.long 0x0 19. "P19,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 18. "P18,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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newline
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bitfld.long 0x0 17. "P17,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 16. "P16,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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newline
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bitfld.long 0x0 15. "P15,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 14. "P14,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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newline
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bitfld.long 0x0 13. "P13,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 12. "P12,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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newline
|
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bitfld.long 0x0 11. "P11,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 10. "P10,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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newline
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bitfld.long 0x0 9. "P9,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 8. "P8,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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newline
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bitfld.long 0x0 7. "P7,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 6. "P6,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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newline
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bitfld.long 0x0 5. "P5,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 4. "P4,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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newline
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bitfld.long 0x0 3. "P3,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 2. "P2,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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newline
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bitfld.long 0x0 1. "P1,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 0. "P0,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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line.long 0x4 "LOCKSR,PIO Lock Status Register"
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bitfld.long 0x4 31. "P31,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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bitfld.long 0x4 30. "P30,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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newline
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bitfld.long 0x4 29. "P29,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
|
|
bitfld.long 0x4 28. "P28,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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|
newline
|
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bitfld.long 0x4 27. "P27,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
|
|
bitfld.long 0x4 26. "P26,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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|
newline
|
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bitfld.long 0x4 25. "P25,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
|
|
bitfld.long 0x4 24. "P24,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
|
|
newline
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bitfld.long 0x4 23. "P23,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
|
|
bitfld.long 0x4 22. "P22,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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|
newline
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bitfld.long 0x4 21. "P21,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
|
|
bitfld.long 0x4 20. "P20,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
|
|
newline
|
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bitfld.long 0x4 19. "P19,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
|
|
bitfld.long 0x4 18. "P18,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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|
newline
|
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bitfld.long 0x4 17. "P17,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
|
|
bitfld.long 0x4 16. "P16,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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|
newline
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bitfld.long 0x4 15. "P15,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
|
|
bitfld.long 0x4 14. "P14,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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|
newline
|
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bitfld.long 0x4 13. "P13,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
|
|
bitfld.long 0x4 12. "P12,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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|
newline
|
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bitfld.long 0x4 11. "P11,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
|
|
bitfld.long 0x4 10. "P10,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
|
|
newline
|
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bitfld.long 0x4 9. "P9,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
|
|
bitfld.long 0x4 8. "P8,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
|
|
newline
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bitfld.long 0x4 7. "P7,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
|
|
bitfld.long 0x4 6. "P6,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
|
|
newline
|
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bitfld.long 0x4 5. "P5,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
|
|
bitfld.long 0x4 4. "P4,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
|
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newline
|
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bitfld.long 0x4 3. "P3,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
|
|
bitfld.long 0x4 2. "P2,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
|
|
newline
|
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bitfld.long 0x4 1. "P1,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
|
|
bitfld.long 0x4 0. "P0,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
|
|
wgroup.long ($2+0x10)++0x7
|
|
line.long 0x0 "SODR,PIO Set Output Data Register"
|
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bitfld.long 0x0 31. "P31,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
|
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bitfld.long 0x0 30. "P30,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
|
|
newline
|
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bitfld.long 0x0 29. "P29,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
|
|
bitfld.long 0x0 28. "P28,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
|
|
newline
|
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bitfld.long 0x0 27. "P27,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
|
|
bitfld.long 0x0 26. "P26,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
|
|
newline
|
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bitfld.long 0x0 25. "P25,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
|
|
bitfld.long 0x0 24. "P24,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
|
|
newline
|
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bitfld.long 0x0 23. "P23,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
|
|
bitfld.long 0x0 22. "P22,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
|
|
newline
|
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bitfld.long 0x0 21. "P21,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
|
|
bitfld.long 0x0 20. "P20,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
|
|
newline
|
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bitfld.long 0x0 19. "P19,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
|
|
bitfld.long 0x0 18. "P18,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
|
|
newline
|
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bitfld.long 0x0 17. "P17,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
|
|
bitfld.long 0x0 16. "P16,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
|
|
newline
|
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bitfld.long 0x0 15. "P15,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
|
|
bitfld.long 0x0 14. "P14,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
|
|
newline
|
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bitfld.long 0x0 13. "P13,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
|
|
bitfld.long 0x0 12. "P12,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
|
|
newline
|
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bitfld.long 0x0 11. "P11,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
|
|
bitfld.long 0x0 10. "P10,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
|
|
newline
|
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bitfld.long 0x0 9. "P9,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
|
|
bitfld.long 0x0 8. "P8,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
|
|
newline
|
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bitfld.long 0x0 7. "P7,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
|
|
bitfld.long 0x0 6. "P6,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
|
|
newline
|
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bitfld.long 0x0 5. "P5,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
|
|
bitfld.long 0x0 4. "P4,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
|
|
newline
|
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bitfld.long 0x0 3. "P3,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
|
|
bitfld.long 0x0 2. "P2,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
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|
newline
|
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bitfld.long 0x0 1. "P1,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
|
|
bitfld.long 0x0 0. "P0,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
|
|
line.long 0x4 "CODR,PIO Clear Output Data Register"
|
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bitfld.long 0x4 31. "P31,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
|
|
bitfld.long 0x4 30. "P30,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
|
|
newline
|
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bitfld.long 0x4 29. "P29,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
|
|
bitfld.long 0x4 28. "P28,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
|
|
newline
|
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bitfld.long 0x4 27. "P27,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
|
|
bitfld.long 0x4 26. "P26,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
|
|
newline
|
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bitfld.long 0x4 25. "P25,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
|
|
bitfld.long 0x4 24. "P24,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
|
|
newline
|
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bitfld.long 0x4 23. "P23,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
|
|
bitfld.long 0x4 22. "P22,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
|
|
newline
|
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bitfld.long 0x4 21. "P21,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
|
|
bitfld.long 0x4 20. "P20,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
|
|
newline
|
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bitfld.long 0x4 19. "P19,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
|
|
bitfld.long 0x4 18. "P18,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
|
|
newline
|
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bitfld.long 0x4 17. "P17,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
|
|
bitfld.long 0x4 16. "P16,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
|
|
bitfld.long 0x4 14. "P14,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
|
|
newline
|
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bitfld.long 0x4 13. "P13,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
|
|
bitfld.long 0x4 12. "P12,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
|
|
newline
|
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bitfld.long 0x4 11. "P11,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
|
|
bitfld.long 0x4 10. "P10,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
|
|
newline
|
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bitfld.long 0x4 9. "P9,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
|
|
bitfld.long 0x4 8. "P8,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
|
|
bitfld.long 0x4 6. "P6,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
|
|
newline
|
|
bitfld.long 0x4 5. "P5,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
|
|
bitfld.long 0x4 4. "P4,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
|
|
bitfld.long 0x4 2. "P2,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
|
|
newline
|
|
bitfld.long 0x4 1. "P1,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
|
|
bitfld.long 0x4 0. "P0,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
|
|
group.long ($2+0x18)++0x3
|
|
line.long 0x0 "ODSR,PIO Output Data Status Register"
|
|
bitfld.long 0x0 31. "P31,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
|
|
bitfld.long 0x0 30. "P30,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
|
|
newline
|
|
bitfld.long 0x0 29. "P29,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
|
|
bitfld.long 0x0 28. "P28,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
|
|
bitfld.long 0x0 26. "P26,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
|
|
newline
|
|
bitfld.long 0x0 25. "P25,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
|
|
bitfld.long 0x0 24. "P24,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
|
|
bitfld.long 0x0 22. "P22,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
|
|
newline
|
|
bitfld.long 0x0 21. "P21,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
|
|
bitfld.long 0x0 20. "P20,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
|
|
bitfld.long 0x0 18. "P18,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
|
|
newline
|
|
bitfld.long 0x0 17. "P17,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
|
|
bitfld.long 0x0 16. "P16,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
|
|
bitfld.long 0x0 14. "P14,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
|
|
newline
|
|
bitfld.long 0x0 13. "P13,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
|
|
bitfld.long 0x0 12. "P12,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
|
|
bitfld.long 0x0 10. "P10,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
|
|
newline
|
|
bitfld.long 0x0 9. "P9,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
|
|
bitfld.long 0x0 8. "P8,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
|
|
bitfld.long 0x0 6. "P6,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
|
|
newline
|
|
bitfld.long 0x0 5. "P5,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
|
|
bitfld.long 0x0 4. "P4,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
|
|
bitfld.long 0x0 2. "P2,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
|
|
newline
|
|
bitfld.long 0x0 1. "P1,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
|
|
bitfld.long 0x0 0. "P0,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
|
|
wgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "IER,PIO Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "P31,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
|
|
bitfld.long 0x0 30. "P30,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
|
|
newline
|
|
bitfld.long 0x0 29. "P29,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
|
|
bitfld.long 0x0 28. "P28,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
|
|
bitfld.long 0x0 26. "P26,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
|
|
newline
|
|
bitfld.long 0x0 25. "P25,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
|
|
bitfld.long 0x0 24. "P24,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
|
|
newline
|
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bitfld.long 0x0 23. "P23,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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bitfld.long 0x0 22. "P22,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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newline
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bitfld.long 0x0 21. "P21,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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bitfld.long 0x0 20. "P20,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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newline
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bitfld.long 0x0 19. "P19,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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bitfld.long 0x0 18. "P18,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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newline
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bitfld.long 0x0 17. "P17,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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bitfld.long 0x0 16. "P16,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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newline
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bitfld.long 0x0 15. "P15,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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bitfld.long 0x0 14. "P14,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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newline
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bitfld.long 0x0 13. "P13,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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bitfld.long 0x0 12. "P12,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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newline
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bitfld.long 0x0 11. "P11,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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bitfld.long 0x0 10. "P10,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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newline
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bitfld.long 0x0 9. "P9,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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bitfld.long 0x0 8. "P8,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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newline
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bitfld.long 0x0 7. "P7,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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bitfld.long 0x0 6. "P6,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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newline
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bitfld.long 0x0 5. "P5,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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bitfld.long 0x0 4. "P4,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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newline
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bitfld.long 0x0 3. "P3,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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bitfld.long 0x0 2. "P2,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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newline
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bitfld.long 0x0 1. "P1,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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bitfld.long 0x0 0. "P0,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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line.long 0x4 "IDR,PIO Interrupt Disable Register"
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bitfld.long 0x4 31. "P31,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
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bitfld.long 0x4 30. "P30,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
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newline
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bitfld.long 0x4 29. "P29,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
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bitfld.long 0x4 28. "P28,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
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newline
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bitfld.long 0x4 27. "P27,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
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bitfld.long 0x4 26. "P26,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
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newline
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bitfld.long 0x4 25. "P25,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
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bitfld.long 0x4 24. "P24,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
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newline
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bitfld.long 0x4 23. "P23,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
|
|
bitfld.long 0x4 22. "P22,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
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newline
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bitfld.long 0x4 21. "P21,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
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bitfld.long 0x4 20. "P20,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
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newline
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bitfld.long 0x4 19. "P19,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
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|
bitfld.long 0x4 18. "P18,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
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newline
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bitfld.long 0x4 17. "P17,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
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|
bitfld.long 0x4 16. "P16,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
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|
newline
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bitfld.long 0x4 15. "P15,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
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|
bitfld.long 0x4 14. "P14,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
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newline
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bitfld.long 0x4 13. "P13,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
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|
bitfld.long 0x4 12. "P12,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
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newline
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bitfld.long 0x4 11. "P11,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
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bitfld.long 0x4 10. "P10,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
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newline
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bitfld.long 0x4 9. "P9,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
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|
bitfld.long 0x4 8. "P8,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
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newline
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bitfld.long 0x4 7. "P7,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
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|
bitfld.long 0x4 6. "P6,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
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newline
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bitfld.long 0x4 5. "P5,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
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|
bitfld.long 0x4 4. "P4,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
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newline
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bitfld.long 0x4 3. "P3,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
|
|
bitfld.long 0x4 2. "P2,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
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|
newline
|
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bitfld.long 0x4 1. "P1,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
|
|
bitfld.long 0x4 0. "P0,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
|
|
rgroup.long ($2+0x28)++0x7
|
|
line.long 0x0 "IMR,PIO Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "P31,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
|
|
bitfld.long 0x0 30. "P30,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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newline
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bitfld.long 0x0 29. "P29,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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|
bitfld.long 0x0 28. "P28,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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newline
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bitfld.long 0x0 27. "P27,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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|
bitfld.long 0x0 26. "P26,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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newline
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bitfld.long 0x0 25. "P25,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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|
bitfld.long 0x0 24. "P24,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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newline
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bitfld.long 0x0 23. "P23,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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bitfld.long 0x0 22. "P22,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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newline
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bitfld.long 0x0 21. "P21,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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bitfld.long 0x0 20. "P20,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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newline
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bitfld.long 0x0 19. "P19,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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bitfld.long 0x0 18. "P18,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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newline
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bitfld.long 0x0 17. "P17,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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bitfld.long 0x0 16. "P16,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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newline
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bitfld.long 0x0 15. "P15,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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bitfld.long 0x0 14. "P14,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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newline
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bitfld.long 0x0 13. "P13,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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bitfld.long 0x0 12. "P12,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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newline
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bitfld.long 0x0 11. "P11,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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bitfld.long 0x0 10. "P10,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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newline
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bitfld.long 0x0 9. "P9,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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bitfld.long 0x0 8. "P8,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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newline
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bitfld.long 0x0 7. "P7,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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bitfld.long 0x0 6. "P6,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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newline
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bitfld.long 0x0 5. "P5,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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|
bitfld.long 0x0 4. "P4,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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newline
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bitfld.long 0x0 3. "P3,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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bitfld.long 0x0 2. "P2,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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newline
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bitfld.long 0x0 1. "P1,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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bitfld.long 0x0 0. "P0,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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line.long 0x4 "ISR,PIO Interrupt Status Register"
|
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bitfld.long 0x4 31. "P31,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
|
|
bitfld.long 0x4 30. "P30,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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newline
|
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bitfld.long 0x4 29. "P29,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
|
|
bitfld.long 0x4 28. "P28,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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newline
|
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bitfld.long 0x4 27. "P27,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
|
|
bitfld.long 0x4 26. "P26,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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newline
|
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bitfld.long 0x4 25. "P25,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
|
|
bitfld.long 0x4 24. "P24,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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|
newline
|
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bitfld.long 0x4 23. "P23,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
|
|
bitfld.long 0x4 22. "P22,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
|
|
newline
|
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bitfld.long 0x4 21. "P21,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
|
|
bitfld.long 0x4 20. "P20,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
|
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newline
|
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bitfld.long 0x4 19. "P19,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
|
|
bitfld.long 0x4 18. "P18,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
|
|
newline
|
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bitfld.long 0x4 17. "P17,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
|
|
bitfld.long 0x4 16. "P16,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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|
newline
|
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bitfld.long 0x4 15. "P15,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
|
|
bitfld.long 0x4 14. "P14,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
|
|
newline
|
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bitfld.long 0x4 13. "P13,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
|
|
bitfld.long 0x4 12. "P12,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
|
|
newline
|
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bitfld.long 0x4 11. "P11,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
|
|
bitfld.long 0x4 10. "P10,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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newline
|
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bitfld.long 0x4 9. "P9,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
|
|
bitfld.long 0x4 8. "P8,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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newline
|
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bitfld.long 0x4 7. "P7,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
|
|
bitfld.long 0x4 6. "P6,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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newline
|
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bitfld.long 0x4 5. "P5,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
|
|
bitfld.long 0x4 4. "P4,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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newline
|
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bitfld.long 0x4 3. "P3,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
|
|
bitfld.long 0x4 2. "P2,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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newline
|
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bitfld.long 0x4 1. "P1,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
|
|
bitfld.long 0x4 0. "P0,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
|
|
wgroup.long ($2+0x3C)++0x3
|
|
line.long 0x0 "IOFR,PIO I/O Freeze Configuration Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "FRZKEY,Freeze Key"
|
|
bitfld.long 0x0 1. "FINT,Freeze Interrupt Configuration" "0: No effect.,1: Freezes the following configuration fields of.."
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newline
|
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bitfld.long 0x0 0. "FPHY,Freeze Physical Configuration" "0: No effect.,1: Freezes the following configuration fields of.."
|
|
tree.end
|
|
repeat.end
|
|
base ad:0xE0014000
|
|
group.long 0x5E0++0x3
|
|
line.long 0x0 "WPMR,PIO Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
|
|
rgroup.long 0x5E4++0x3
|
|
line.long 0x0 "WPSR,PIO Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
|
|
repeat 5. (list 0x0 0x1 0x2 0x3 0x4)(list ad:0xE0015000 ad:0xE0015040 ad:0xE0015080 ad:0xE00150C0 ad:0xE0015100)
|
|
tree "PIO_SGROUP[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "S_PIO_MSKR,Secure PIO Mask Register"
|
|
bitfld.long 0x0 31. "MSK31,PIO Line y Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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|
bitfld.long 0x0 30. "MSK30,PIO Line y Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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newline
|
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bitfld.long 0x0 29. "MSK29,PIO Line y Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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|
bitfld.long 0x0 28. "MSK28,PIO Line y Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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newline
|
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bitfld.long 0x0 27. "MSK27,PIO Line y Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
|
|
bitfld.long 0x0 26. "MSK26,PIO Line y Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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newline
|
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bitfld.long 0x0 25. "MSK25,PIO Line y Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
|
|
bitfld.long 0x0 24. "MSK24,PIO Line y Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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newline
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bitfld.long 0x0 23. "MSK23,PIO Line y Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 22. "MSK22,PIO Line y Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 21. "MSK21,PIO Line y Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 20. "MSK20,PIO Line y Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 19. "MSK19,PIO Line y Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 18. "MSK18,PIO Line y Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 17. "MSK17,PIO Line y Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 16. "MSK16,PIO Line y Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 15. "MSK15,PIO Line y Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 14. "MSK14,PIO Line y Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 13. "MSK13,PIO Line y Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 12. "MSK12,PIO Line y Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 11. "MSK11,PIO Line y Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 10. "MSK10,PIO Line y Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 9. "MSK9,PIO Line y Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 8. "MSK8,PIO Line y Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 7. "MSK7,PIO Line y Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 6. "MSK6,PIO Line y Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 5. "MSK5,PIO Line y Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 4. "MSK4,PIO Line y Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 3. "MSK3,PIO Line y Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 2. "MSK2,PIO Line y Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 1. "MSK1,PIO Line y Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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bitfld.long 0x0 0. "MSK0,PIO Line y Mask" "0: Writing the S_PIO_CFGRx S_PIO_ODSRx or..,1: Writing the S_PIO_CFGRx S_PIO_ODSRx or.."
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line.long 0x4 "S_PIO_CFGR,Secure PIO Configuration Register"
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bitfld.long 0x4 30. "ICFS,Interrupt Configuration Freeze Status (read-only)" "0: The fields are not frozen and can be written for..,1: The fields are frozen and cannot be written for.."
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bitfld.long 0x4 29. "PCFS,Physical Configuration Freeze Status (read-only)" "0: The fields are not frozen and can be written for..,1: The fields are frozen and cannot be written for.."
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bitfld.long 0x4 24.--26. "EVTSEL,Event Selection" "0: Event detection on input falling edge,1: Event detection on input rising edge,2: Event detection on input both edge,3: Event detection on low level input,4: Event detection on high level input,?,?,?"
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bitfld.long 0x4 16.--17. "DRVSTR,Drive Strength" "0: Low drive,?,2: Medium drive,3: High drive"
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bitfld.long 0x4 15. "SCHMITT,Schmitt Trigger" "0: Schmitt trigger is enabled for the selected I/O..,1: Schmitt trigger is disabled for the selected I/O.."
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bitfld.long 0x4 14. "OPD,Open-Drain" "0: The open-drain is disabled for the selected I/O..,1: The open-drain is enabled for the selected I/O.."
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bitfld.long 0x4 13. "IFSCEN,Input Filter Slow Clock Enable" "0: The glitch filter is able to filter glitches..,1: The debouncing filter is able to filter pulses.."
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bitfld.long 0x4 12. "IFEN,Input Filter Enable" "0: The input filter is disabled for the selected..,1: The input filter is enabled for the selected I/O.."
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bitfld.long 0x4 11. "SR,Slew Rate" "0: Slew rate control is disabled for the selected..,1: Slew rate control is enabled for the selected.."
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bitfld.long 0x4 10. "PDEN,Pull-Down Enable" "0: Pull-Down is disabled for the selected I/O lines.,1: Pull-Down is enabled for the selected I/O lines.."
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bitfld.long 0x4 9. "PUEN,Pull-Up Enable" "0: Pull-Up is disabled for the selected I/O lines.,1: Pull-Up is enabled for the selected I/O lines."
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bitfld.long 0x4 8. "DIR,Direction" "0: The selected I/O lines are pure inputs.,1: The selected I/O lines are enabled in output."
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bitfld.long 0x4 0.--2. "FUNC,I/O Line Function" "0: Select the PIO mode for the selected I/O lines.,1: Select the peripheral A for the selected I/O..,2: Select the peripheral B for the selected I/O..,3: Select the peripheral C for the selected I/O..,4: Select the peripheral D for the selected I/O..,5: Select the peripheral E for the selected I/O..,6: Select the peripheral F for the selected I/O..,7: Select the peripheral G for the selected I/O.."
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rgroup.long ($2+0x8)++0x7
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line.long 0x0 "S_PIO_PDSR,Secure PIO Pin Data Status Register"
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bitfld.long 0x0 31. "P31,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 30. "P30,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 29. "P29,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 28. "P28,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 27. "P27,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 26. "P26,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 25. "P25,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 24. "P24,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 23. "P23,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 22. "P22,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 21. "P21,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 20. "P20,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 19. "P19,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 18. "P18,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 17. "P17,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 16. "P16,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 15. "P15,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 14. "P14,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 13. "P13,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 12. "P12,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 11. "P11,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 10. "P10,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 9. "P9,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 8. "P8,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 7. "P7,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 6. "P6,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 5. "P5,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 4. "P4,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 3. "P3,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 2. "P2,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 1. "P1,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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bitfld.long 0x0 0. "P0,Input Data Status" "0: The I/O line of the I/O group x is at level 0.,1: The I/O line of the I/O group x is at level 1."
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line.long 0x4 "S_PIO_LOCKSR,Secure PIO Lock Status Register"
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bitfld.long 0x4 31. "P31,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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bitfld.long 0x4 30. "P30,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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bitfld.long 0x4 29. "P29,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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bitfld.long 0x4 28. "P28,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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bitfld.long 0x4 27. "P27,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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bitfld.long 0x4 26. "P26,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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bitfld.long 0x4 25. "P25,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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bitfld.long 0x4 24. "P24,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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bitfld.long 0x4 23. "P23,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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bitfld.long 0x4 22. "P22,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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bitfld.long 0x4 21. "P21,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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bitfld.long 0x4 20. "P20,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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bitfld.long 0x4 19. "P19,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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bitfld.long 0x4 18. "P18,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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bitfld.long 0x4 17. "P17,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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bitfld.long 0x4 16. "P16,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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bitfld.long 0x4 15. "P15,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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bitfld.long 0x4 14. "P14,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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bitfld.long 0x4 13. "P13,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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bitfld.long 0x4 12. "P12,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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bitfld.long 0x4 11. "P11,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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bitfld.long 0x4 10. "P10,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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bitfld.long 0x4 9. "P9,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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bitfld.long 0x4 8. "P8,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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bitfld.long 0x4 7. "P7,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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bitfld.long 0x4 6. "P6,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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bitfld.long 0x4 5. "P5,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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bitfld.long 0x4 4. "P4,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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bitfld.long 0x4 3. "P3,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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bitfld.long 0x4 2. "P2,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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bitfld.long 0x4 1. "P1,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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bitfld.long 0x4 0. "P0,Lock Status" "0: The I/O line of the I/O group x is not locked.,1: The I/O line of the I/O group x is locked."
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wgroup.long ($2+0x10)++0x7
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line.long 0x0 "S_PIO_SODR,Secure PIO Set Output Data Register"
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bitfld.long 0x0 31. "P31,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
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bitfld.long 0x0 30. "P30,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
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bitfld.long 0x0 29. "P29,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
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bitfld.long 0x0 28. "P28,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
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bitfld.long 0x0 27. "P27,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
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bitfld.long 0x0 26. "P26,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
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bitfld.long 0x0 25. "P25,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
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bitfld.long 0x0 24. "P24,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
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bitfld.long 0x0 23. "P23,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
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bitfld.long 0x0 22. "P22,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
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bitfld.long 0x0 21. "P21,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
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bitfld.long 0x0 20. "P20,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
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bitfld.long 0x0 19. "P19,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
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bitfld.long 0x0 18. "P18,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
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bitfld.long 0x0 17. "P17,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
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bitfld.long 0x0 16. "P16,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
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bitfld.long 0x0 15. "P15,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
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bitfld.long 0x0 14. "P14,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
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newline
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bitfld.long 0x0 13. "P13,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
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bitfld.long 0x0 12. "P12,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
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newline
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bitfld.long 0x0 11. "P11,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
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bitfld.long 0x0 10. "P10,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
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newline
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bitfld.long 0x0 9. "P9,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
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bitfld.long 0x0 8. "P8,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
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newline
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bitfld.long 0x0 7. "P7,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
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bitfld.long 0x0 6. "P6,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
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newline
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bitfld.long 0x0 5. "P5,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
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bitfld.long 0x0 4. "P4,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
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newline
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bitfld.long 0x0 3. "P3,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
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|
bitfld.long 0x0 2. "P2,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
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newline
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bitfld.long 0x0 1. "P1,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
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bitfld.long 0x0 0. "P0,Set Output Data" "0: No effect.,1: Sets the data to be driven on the I/O line of.."
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|
line.long 0x4 "S_PIO_CODR,Secure PIO Clear Output Data Register"
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bitfld.long 0x4 31. "P31,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
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bitfld.long 0x4 30. "P30,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
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newline
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bitfld.long 0x4 29. "P29,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
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bitfld.long 0x4 28. "P28,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
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newline
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bitfld.long 0x4 27. "P27,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
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bitfld.long 0x4 26. "P26,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
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newline
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bitfld.long 0x4 25. "P25,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
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bitfld.long 0x4 24. "P24,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
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newline
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bitfld.long 0x4 23. "P23,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
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bitfld.long 0x4 22. "P22,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
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newline
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bitfld.long 0x4 21. "P21,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
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bitfld.long 0x4 20. "P20,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
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newline
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bitfld.long 0x4 19. "P19,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
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bitfld.long 0x4 18. "P18,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
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newline
|
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bitfld.long 0x4 17. "P17,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
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bitfld.long 0x4 16. "P16,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
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newline
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bitfld.long 0x4 15. "P15,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
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bitfld.long 0x4 14. "P14,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
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|
newline
|
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bitfld.long 0x4 13. "P13,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
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bitfld.long 0x4 12. "P12,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
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newline
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bitfld.long 0x4 11. "P11,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
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bitfld.long 0x4 10. "P10,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
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newline
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bitfld.long 0x4 9. "P9,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
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bitfld.long 0x4 8. "P8,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
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newline
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bitfld.long 0x4 7. "P7,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
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bitfld.long 0x4 6. "P6,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
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newline
|
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bitfld.long 0x4 5. "P5,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
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bitfld.long 0x4 4. "P4,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
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newline
|
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bitfld.long 0x4 3. "P3,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
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bitfld.long 0x4 2. "P2,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
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newline
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bitfld.long 0x4 1. "P1,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
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bitfld.long 0x4 0. "P0,Clear Output Data" "0: No effect.,1: Clears the data to be driven on the I/O line of.."
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|
group.long ($2+0x18)++0x3
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line.long 0x0 "S_PIO_ODSR,Secure PIO Output Data Status Register"
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bitfld.long 0x0 31. "P31,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
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bitfld.long 0x0 30. "P30,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
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newline
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bitfld.long 0x0 29. "P29,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
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bitfld.long 0x0 28. "P28,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
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|
newline
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bitfld.long 0x0 27. "P27,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
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bitfld.long 0x0 26. "P26,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
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newline
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bitfld.long 0x0 25. "P25,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
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bitfld.long 0x0 24. "P24,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
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newline
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bitfld.long 0x0 23. "P23,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
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bitfld.long 0x0 22. "P22,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
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newline
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bitfld.long 0x0 21. "P21,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
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bitfld.long 0x0 20. "P20,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
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newline
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bitfld.long 0x0 19. "P19,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
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bitfld.long 0x0 18. "P18,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
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newline
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bitfld.long 0x0 17. "P17,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
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bitfld.long 0x0 16. "P16,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
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newline
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bitfld.long 0x0 15. "P15,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
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bitfld.long 0x0 14. "P14,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
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newline
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bitfld.long 0x0 13. "P13,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
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bitfld.long 0x0 12. "P12,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
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newline
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bitfld.long 0x0 11. "P11,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
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bitfld.long 0x0 10. "P10,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
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newline
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bitfld.long 0x0 9. "P9,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
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bitfld.long 0x0 8. "P8,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
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newline
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bitfld.long 0x0 7. "P7,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
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bitfld.long 0x0 6. "P6,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
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newline
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bitfld.long 0x0 5. "P5,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
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bitfld.long 0x0 4. "P4,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
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newline
|
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bitfld.long 0x0 3. "P3,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
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bitfld.long 0x0 2. "P2,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
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newline
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bitfld.long 0x0 1. "P1,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
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bitfld.long 0x0 0. "P0,Output Data Status" "0: The data to be driven on the I/O line of the I/O..,1: The data to be driven on the I/O line of the I/O.."
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wgroup.long ($2+0x20)++0x7
|
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line.long 0x0 "S_PIO_IER,Secure PIO Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "P31,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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|
bitfld.long 0x0 30. "P30,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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newline
|
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bitfld.long 0x0 29. "P29,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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bitfld.long 0x0 28. "P28,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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|
newline
|
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bitfld.long 0x0 27. "P27,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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bitfld.long 0x0 26. "P26,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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newline
|
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bitfld.long 0x0 25. "P25,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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bitfld.long 0x0 24. "P24,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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newline
|
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bitfld.long 0x0 23. "P23,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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bitfld.long 0x0 22. "P22,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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newline
|
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bitfld.long 0x0 21. "P21,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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bitfld.long 0x0 20. "P20,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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|
newline
|
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bitfld.long 0x0 19. "P19,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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|
bitfld.long 0x0 18. "P18,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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|
newline
|
|
bitfld.long 0x0 17. "P17,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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bitfld.long 0x0 16. "P16,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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newline
|
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bitfld.long 0x0 15. "P15,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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bitfld.long 0x0 14. "P14,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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|
newline
|
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bitfld.long 0x0 13. "P13,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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bitfld.long 0x0 12. "P12,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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|
newline
|
|
bitfld.long 0x0 11. "P11,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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|
bitfld.long 0x0 10. "P10,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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|
newline
|
|
bitfld.long 0x0 9. "P9,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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|
bitfld.long 0x0 8. "P8,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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|
newline
|
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bitfld.long 0x0 7. "P7,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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|
bitfld.long 0x0 6. "P6,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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|
newline
|
|
bitfld.long 0x0 5. "P5,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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|
bitfld.long 0x0 4. "P4,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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|
newline
|
|
bitfld.long 0x0 3. "P3,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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|
bitfld.long 0x0 2. "P2,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
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|
newline
|
|
bitfld.long 0x0 1. "P1,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
|
|
bitfld.long 0x0 0. "P0,Input Change Interrupt Enable" "0: No effect.,1: Enables the Input Change interrupt on the I/O.."
|
|
line.long 0x4 "S_PIO_IDR,Secure PIO Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "P31,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
|
|
bitfld.long 0x4 30. "P30,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
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|
newline
|
|
bitfld.long 0x4 29. "P29,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
|
|
bitfld.long 0x4 28. "P28,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
|
|
bitfld.long 0x4 26. "P26,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
|
|
newline
|
|
bitfld.long 0x4 25. "P25,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
|
|
bitfld.long 0x4 24. "P24,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
|
|
bitfld.long 0x4 22. "P22,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
|
|
newline
|
|
bitfld.long 0x4 21. "P21,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
|
|
bitfld.long 0x4 20. "P20,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
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|
newline
|
|
bitfld.long 0x4 19. "P19,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
|
|
bitfld.long 0x4 18. "P18,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
|
|
newline
|
|
bitfld.long 0x4 17. "P17,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
|
|
bitfld.long 0x4 16. "P16,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
|
|
bitfld.long 0x4 14. "P14,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
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|
newline
|
|
bitfld.long 0x4 13. "P13,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
|
|
bitfld.long 0x4 12. "P12,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
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|
newline
|
|
bitfld.long 0x4 11. "P11,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
|
|
bitfld.long 0x4 10. "P10,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
|
|
newline
|
|
bitfld.long 0x4 9. "P9,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
|
|
bitfld.long 0x4 8. "P8,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
|
|
bitfld.long 0x4 6. "P6,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
|
|
newline
|
|
bitfld.long 0x4 5. "P5,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
|
|
bitfld.long 0x4 4. "P4,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
|
|
bitfld.long 0x4 2. "P2,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
|
|
newline
|
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bitfld.long 0x4 1. "P1,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
|
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bitfld.long 0x4 0. "P0,Input Change Interrupt Disable" "0: No effect.,1: Disables the Input Change interrupt on the I/O.."
|
|
rgroup.long ($2+0x28)++0x7
|
|
line.long 0x0 "S_PIO_IMR,Secure PIO Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "P31,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
|
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bitfld.long 0x0 30. "P30,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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newline
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bitfld.long 0x0 29. "P29,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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bitfld.long 0x0 28. "P28,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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newline
|
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bitfld.long 0x0 27. "P27,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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bitfld.long 0x0 26. "P26,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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newline
|
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bitfld.long 0x0 25. "P25,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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bitfld.long 0x0 24. "P24,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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newline
|
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bitfld.long 0x0 23. "P23,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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bitfld.long 0x0 22. "P22,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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newline
|
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bitfld.long 0x0 21. "P21,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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bitfld.long 0x0 20. "P20,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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newline
|
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bitfld.long 0x0 19. "P19,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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bitfld.long 0x0 18. "P18,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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newline
|
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bitfld.long 0x0 17. "P17,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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bitfld.long 0x0 16. "P16,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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newline
|
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bitfld.long 0x0 15. "P15,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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bitfld.long 0x0 14. "P14,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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newline
|
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bitfld.long 0x0 13. "P13,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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bitfld.long 0x0 12. "P12,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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newline
|
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bitfld.long 0x0 11. "P11,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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bitfld.long 0x0 10. "P10,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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newline
|
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bitfld.long 0x0 9. "P9,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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bitfld.long 0x0 8. "P8,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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newline
|
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bitfld.long 0x0 7. "P7,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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bitfld.long 0x0 6. "P6,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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newline
|
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bitfld.long 0x0 5. "P5,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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bitfld.long 0x0 4. "P4,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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newline
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bitfld.long 0x0 3. "P3,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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bitfld.long 0x0 2. "P2,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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newline
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bitfld.long 0x0 1. "P1,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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bitfld.long 0x0 0. "P0,Input Change Interrupt Mask" "0: Input Change interrupt is disabled on the I/O..,1: Input Change interrupt is enabled on the I/O.."
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line.long 0x4 "S_PIO_ISR,Secure PIO Interrupt Status Register"
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bitfld.long 0x4 31. "P31,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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bitfld.long 0x4 30. "P30,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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newline
|
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bitfld.long 0x4 29. "P29,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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bitfld.long 0x4 28. "P28,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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newline
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bitfld.long 0x4 27. "P27,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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bitfld.long 0x4 26. "P26,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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newline
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bitfld.long 0x4 25. "P25,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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bitfld.long 0x4 24. "P24,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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newline
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bitfld.long 0x4 23. "P23,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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bitfld.long 0x4 22. "P22,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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newline
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bitfld.long 0x4 21. "P21,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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bitfld.long 0x4 20. "P20,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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newline
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bitfld.long 0x4 19. "P19,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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bitfld.long 0x4 18. "P18,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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newline
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bitfld.long 0x4 17. "P17,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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bitfld.long 0x4 16. "P16,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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newline
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bitfld.long 0x4 15. "P15,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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bitfld.long 0x4 14. "P14,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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newline
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bitfld.long 0x4 13. "P13,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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bitfld.long 0x4 12. "P12,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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newline
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bitfld.long 0x4 11. "P11,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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bitfld.long 0x4 10. "P10,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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newline
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bitfld.long 0x4 9. "P9,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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bitfld.long 0x4 8. "P8,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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newline
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bitfld.long 0x4 7. "P7,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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bitfld.long 0x4 6. "P6,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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newline
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bitfld.long 0x4 5. "P5,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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bitfld.long 0x4 4. "P4,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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newline
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bitfld.long 0x4 3. "P3,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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bitfld.long 0x4 2. "P2,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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newline
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bitfld.long 0x4 1. "P1,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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bitfld.long 0x4 0. "P0,Input Change Interrupt Status" "0: No input change has been detected on the I/O..,1: At least one input change has been detected on.."
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wgroup.long ($2+0x30)++0x7
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line.long 0x0 "S_PIO_SIONR,Secure PIO Set I/O Non-Secure Register"
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bitfld.long 0x0 31. "P31,Set I/O Non-Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in.."
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bitfld.long 0x0 30. "P30,Set I/O Non-Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in.."
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newline
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bitfld.long 0x0 29. "P29,Set I/O Non-Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in.."
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bitfld.long 0x0 28. "P28,Set I/O Non-Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in.."
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newline
|
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bitfld.long 0x0 27. "P27,Set I/O Non-Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in.."
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bitfld.long 0x0 26. "P26,Set I/O Non-Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in.."
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newline
|
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bitfld.long 0x0 25. "P25,Set I/O Non-Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in.."
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bitfld.long 0x0 24. "P24,Set I/O Non-Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in.."
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newline
|
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bitfld.long 0x0 23. "P23,Set I/O Non-Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in.."
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bitfld.long 0x0 22. "P22,Set I/O Non-Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in.."
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|
newline
|
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bitfld.long 0x0 21. "P21,Set I/O Non-Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in.."
|
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bitfld.long 0x0 20. "P20,Set I/O Non-Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in.."
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|
newline
|
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bitfld.long 0x0 19. "P19,Set I/O Non-Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in.."
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bitfld.long 0x0 18. "P18,Set I/O Non-Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in.."
|
|
newline
|
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bitfld.long 0x0 17. "P17,Set I/O Non-Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in.."
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bitfld.long 0x0 16. "P16,Set I/O Non-Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in.."
|
|
newline
|
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bitfld.long 0x0 15. "P15,Set I/O Non-Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in.."
|
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bitfld.long 0x0 14. "P14,Set I/O Non-Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in.."
|
|
newline
|
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bitfld.long 0x0 13. "P13,Set I/O Non-Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in.."
|
|
bitfld.long 0x0 12. "P12,Set I/O Non-Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in.."
|
|
newline
|
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bitfld.long 0x0 11. "P11,Set I/O Non-Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in.."
|
|
bitfld.long 0x0 10. "P10,Set I/O Non-Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in.."
|
|
newline
|
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bitfld.long 0x0 9. "P9,Set I/O Non-Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in.."
|
|
bitfld.long 0x0 8. "P8,Set I/O Non-Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in.."
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Set I/O Non-Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in.."
|
|
bitfld.long 0x0 6. "P6,Set I/O Non-Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in.."
|
|
newline
|
|
bitfld.long 0x0 5. "P5,Set I/O Non-Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in.."
|
|
bitfld.long 0x0 4. "P4,Set I/O Non-Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in.."
|
|
newline
|
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bitfld.long 0x0 3. "P3,Set I/O Non-Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in.."
|
|
bitfld.long 0x0 2. "P2,Set I/O Non-Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in.."
|
|
newline
|
|
bitfld.long 0x0 1. "P1,Set I/O Non-Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in.."
|
|
bitfld.long 0x0 0. "P0,Set I/O Non-Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in.."
|
|
line.long 0x4 "S_PIO_SIOSR,Secure PIO Set I/O Secure Register"
|
|
bitfld.long 0x4 31. "P31,Set I/O Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in Secure.."
|
|
bitfld.long 0x4 30. "P30,Set I/O Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in Secure.."
|
|
newline
|
|
bitfld.long 0x4 29. "P29,Set I/O Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in Secure.."
|
|
bitfld.long 0x4 28. "P28,Set I/O Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in Secure.."
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Set I/O Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in Secure.."
|
|
bitfld.long 0x4 26. "P26,Set I/O Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in Secure.."
|
|
newline
|
|
bitfld.long 0x4 25. "P25,Set I/O Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in Secure.."
|
|
bitfld.long 0x4 24. "P24,Set I/O Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in Secure.."
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Set I/O Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in Secure.."
|
|
bitfld.long 0x4 22. "P22,Set I/O Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in Secure.."
|
|
newline
|
|
bitfld.long 0x4 21. "P21,Set I/O Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in Secure.."
|
|
bitfld.long 0x4 20. "P20,Set I/O Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in Secure.."
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Set I/O Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in Secure.."
|
|
bitfld.long 0x4 18. "P18,Set I/O Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in Secure.."
|
|
newline
|
|
bitfld.long 0x4 17. "P17,Set I/O Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in Secure.."
|
|
bitfld.long 0x4 16. "P16,Set I/O Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in Secure.."
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Set I/O Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in Secure.."
|
|
bitfld.long 0x4 14. "P14,Set I/O Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in Secure.."
|
|
newline
|
|
bitfld.long 0x4 13. "P13,Set I/O Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in Secure.."
|
|
bitfld.long 0x4 12. "P12,Set I/O Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in Secure.."
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Set I/O Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in Secure.."
|
|
bitfld.long 0x4 10. "P10,Set I/O Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in Secure.."
|
|
newline
|
|
bitfld.long 0x4 9. "P9,Set I/O Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in Secure.."
|
|
bitfld.long 0x4 8. "P8,Set I/O Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in Secure.."
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Set I/O Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in Secure.."
|
|
bitfld.long 0x4 6. "P6,Set I/O Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in Secure.."
|
|
newline
|
|
bitfld.long 0x4 5. "P5,Set I/O Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in Secure.."
|
|
bitfld.long 0x4 4. "P4,Set I/O Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in Secure.."
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Set I/O Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in Secure.."
|
|
bitfld.long 0x4 2. "P2,Set I/O Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in Secure.."
|
|
newline
|
|
bitfld.long 0x4 1. "P1,Set I/O Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in Secure.."
|
|
bitfld.long 0x4 0. "P0,Set I/O Secure" "0: No effect.,1: Sets the I/O line of the I/O group x in Secure.."
|
|
rgroup.long ($2+0x38)++0x3
|
|
line.long 0x0 "S_PIO_IOSSR,Secure PIO I/O Security Status Register"
|
|
bitfld.long 0x0 31. "P31,I/O Security Status" "0: The I/O line of the I/O group x is in Secure mode.,1: The I/O line of the I/O group x is in Non-Secure.."
|
|
bitfld.long 0x0 30. "P30,I/O Security Status" "0: The I/O line of the I/O group x is in Secure mode.,1: The I/O line of the I/O group x is in Non-Secure.."
|
|
newline
|
|
bitfld.long 0x0 29. "P29,I/O Security Status" "0: The I/O line of the I/O group x is in Secure mode.,1: The I/O line of the I/O group x is in Non-Secure.."
|
|
bitfld.long 0x0 28. "P28,I/O Security Status" "0: The I/O line of the I/O group x is in Secure mode.,1: The I/O line of the I/O group x is in Non-Secure.."
|
|
newline
|
|
bitfld.long 0x0 27. "P27,I/O Security Status" "0: The I/O line of the I/O group x is in Secure mode.,1: The I/O line of the I/O group x is in Non-Secure.."
|
|
bitfld.long 0x0 26. "P26,I/O Security Status" "0: The I/O line of the I/O group x is in Secure mode.,1: The I/O line of the I/O group x is in Non-Secure.."
|
|
newline
|
|
bitfld.long 0x0 25. "P25,I/O Security Status" "0: The I/O line of the I/O group x is in Secure mode.,1: The I/O line of the I/O group x is in Non-Secure.."
|
|
bitfld.long 0x0 24. "P24,I/O Security Status" "0: The I/O line of the I/O group x is in Secure mode.,1: The I/O line of the I/O group x is in Non-Secure.."
|
|
newline
|
|
bitfld.long 0x0 23. "P23,I/O Security Status" "0: The I/O line of the I/O group x is in Secure mode.,1: The I/O line of the I/O group x is in Non-Secure.."
|
|
bitfld.long 0x0 22. "P22,I/O Security Status" "0: The I/O line of the I/O group x is in Secure mode.,1: The I/O line of the I/O group x is in Non-Secure.."
|
|
newline
|
|
bitfld.long 0x0 21. "P21,I/O Security Status" "0: The I/O line of the I/O group x is in Secure mode.,1: The I/O line of the I/O group x is in Non-Secure.."
|
|
bitfld.long 0x0 20. "P20,I/O Security Status" "0: The I/O line of the I/O group x is in Secure mode.,1: The I/O line of the I/O group x is in Non-Secure.."
|
|
newline
|
|
bitfld.long 0x0 19. "P19,I/O Security Status" "0: The I/O line of the I/O group x is in Secure mode.,1: The I/O line of the I/O group x is in Non-Secure.."
|
|
bitfld.long 0x0 18. "P18,I/O Security Status" "0: The I/O line of the I/O group x is in Secure mode.,1: The I/O line of the I/O group x is in Non-Secure.."
|
|
newline
|
|
bitfld.long 0x0 17. "P17,I/O Security Status" "0: The I/O line of the I/O group x is in Secure mode.,1: The I/O line of the I/O group x is in Non-Secure.."
|
|
bitfld.long 0x0 16. "P16,I/O Security Status" "0: The I/O line of the I/O group x is in Secure mode.,1: The I/O line of the I/O group x is in Non-Secure.."
|
|
newline
|
|
bitfld.long 0x0 15. "P15,I/O Security Status" "0: The I/O line of the I/O group x is in Secure mode.,1: The I/O line of the I/O group x is in Non-Secure.."
|
|
bitfld.long 0x0 14. "P14,I/O Security Status" "0: The I/O line of the I/O group x is in Secure mode.,1: The I/O line of the I/O group x is in Non-Secure.."
|
|
newline
|
|
bitfld.long 0x0 13. "P13,I/O Security Status" "0: The I/O line of the I/O group x is in Secure mode.,1: The I/O line of the I/O group x is in Non-Secure.."
|
|
bitfld.long 0x0 12. "P12,I/O Security Status" "0: The I/O line of the I/O group x is in Secure mode.,1: The I/O line of the I/O group x is in Non-Secure.."
|
|
newline
|
|
bitfld.long 0x0 11. "P11,I/O Security Status" "0: The I/O line of the I/O group x is in Secure mode.,1: The I/O line of the I/O group x is in Non-Secure.."
|
|
bitfld.long 0x0 10. "P10,I/O Security Status" "0: The I/O line of the I/O group x is in Secure mode.,1: The I/O line of the I/O group x is in Non-Secure.."
|
|
newline
|
|
bitfld.long 0x0 9. "P9,I/O Security Status" "0: The I/O line of the I/O group x is in Secure mode.,1: The I/O line of the I/O group x is in Non-Secure.."
|
|
bitfld.long 0x0 8. "P8,I/O Security Status" "0: The I/O line of the I/O group x is in Secure mode.,1: The I/O line of the I/O group x is in Non-Secure.."
|
|
newline
|
|
bitfld.long 0x0 7. "P7,I/O Security Status" "0: The I/O line of the I/O group x is in Secure mode.,1: The I/O line of the I/O group x is in Non-Secure.."
|
|
bitfld.long 0x0 6. "P6,I/O Security Status" "0: The I/O line of the I/O group x is in Secure mode.,1: The I/O line of the I/O group x is in Non-Secure.."
|
|
newline
|
|
bitfld.long 0x0 5. "P5,I/O Security Status" "0: The I/O line of the I/O group x is in Secure mode.,1: The I/O line of the I/O group x is in Non-Secure.."
|
|
bitfld.long 0x0 4. "P4,I/O Security Status" "0: The I/O line of the I/O group x is in Secure mode.,1: The I/O line of the I/O group x is in Non-Secure.."
|
|
newline
|
|
bitfld.long 0x0 3. "P3,I/O Security Status" "0: The I/O line of the I/O group x is in Secure mode.,1: The I/O line of the I/O group x is in Non-Secure.."
|
|
bitfld.long 0x0 2. "P2,I/O Security Status" "0: The I/O line of the I/O group x is in Secure mode.,1: The I/O line of the I/O group x is in Non-Secure.."
|
|
newline
|
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bitfld.long 0x0 1. "P1,I/O Security Status" "0: The I/O line of the I/O group x is in Secure mode.,1: The I/O line of the I/O group x is in Non-Secure.."
|
|
bitfld.long 0x0 0. "P0,I/O Security Status" "0: The I/O line of the I/O group x is in Secure mode.,1: The I/O line of the I/O group x is in Non-Secure.."
|
|
wgroup.long ($2+0x3C)++0x3
|
|
line.long 0x0 "S_PIO_IOFR,Secure PIO I/O Freeze Configuration Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "FRZKEY,Freeze Key"
|
|
bitfld.long 0x0 1. "FINT,Freeze Interrupt Configuration" "0: No effect.,1: Freezes the following configuration fields of.."
|
|
newline
|
|
bitfld.long 0x0 0. "FPHY,Freeze Physical Configuration" "0: No effect.,1: Freezes the following configuration fields of.."
|
|
tree.end
|
|
repeat.end
|
|
base ad:0xE0014000
|
|
group.long 0x1500++0x3
|
|
line.long 0x0 "S_PIO_SCDR,Secure PIO Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "DIV,Slow Clock Divider Selection for Debouncing"
|
|
group.long 0x15E0++0x3
|
|
line.long 0x0 "S_PIO_WPMR,Secure PIO Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on secure..,1: Enables the write protection on secure interrupt.."
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
|
|
rgroup.long 0x15E4++0x3
|
|
line.long 0x0 "S_PIO_WPSR,Secure PIO Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
|
|
tree.end
|
|
tree "PIT64B (64-bit Periodic Interval Timer)"
|
|
base ad:0x0
|
|
tree "PIT64B0"
|
|
base ad:0xE1800000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 8. "SWRST,Software Reset" "0: No effect.,1: Performs a software reset clears the.."
|
|
bitfld.long 0x0 0. "START,Start Timer" "0: No effect.,1: The timer counter is started for 1 or more.."
|
|
group.long 0x4++0xB
|
|
line.long 0x0 "MR,Mode Register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "PRESCALER,Prescaler Period"
|
|
bitfld.long 0x0 4. "SMOD,Start Mode" "0: Writing PIT64B_LSBPR does not start the timer..,1: Writing PIT64B_LSBPR starts the timer period."
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|
newline
|
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bitfld.long 0x0 3. "SGCLK,Generic Clock Selection Enable" "0: The prescaler is triggered at each rising edge..,1: GCLK clock is selected as clock source of the.."
|
|
bitfld.long 0x0 0. "CONT,Continuous Mode" "0: A single period interrupt is generated from a..,1: Continuous periodic interrupts are generated.."
|
|
line.long 0x4 "LSBPR,LSB Period Register"
|
|
hexmask.long 0x4 0.--31. 1. "LSBPERIOD,32 LSB of the Timer Period"
|
|
line.long 0x8 "MSBPR,MSB Period Register"
|
|
hexmask.long 0x8 0.--31. 1. "MSBPERIOD,32 MSB of the Timer Period"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 4. "SECE,Safety and/or Security Report Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PERIOD,Elapsed Timer Period Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 4. "SECE,Safety and/or Security Report Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 1. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "PERIOD,Elapsed Timer Period Interrupt Disable" "0,1"
|
|
rgroup.long 0x18++0xF
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 4. "SECE,Safety and/or Security Report Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 1. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PERIOD,Elapsed Timer Period Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 4. "SECE,Safety/Security Report (cleared on read)" "0: There is no security report in PIT64B_WPSR since..,1: One security flag is set in PIT64B_WPSR since.."
|
|
bitfld.long 0x4 1. "OVRE,Overrun Error (cleared on read)" "0: No multiple rollovers occurred since the last..,1: More than 1 rollover occurred since the last.."
|
|
newline
|
|
bitfld.long 0x4 0. "PERIOD,Elapsed Timer Period Status Flag (cleared on read)" "0: No timer rollover occurred since the last read..,1: A timer rollover occurred since the last read of.."
|
|
line.long 0x8 "TLSBR,Timer LSB Current Value Register"
|
|
hexmask.long 0x8 0.--31. 1. "LSBTIMER,Current 32 LSB of the Timer"
|
|
line.long 0xC "TMSBR,Timer MSB Current Value Register"
|
|
hexmask.long 0xC 0.--31. 1. "MSBTIMER,Current 32 MSB of the Timer"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 4. "FIRSTE,First Error Report Enable" "0: The last write protection violation source is..,1: Only the first write protection violation source.."
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interruption Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
bitfld.long 0x0 31. "ECLASS,Software Error Class (cleared on read)" "0: An abnormal access that does not affect system..,1: A write access is performed into PIT64B_MR.."
|
|
bitfld.long 0x0 24.--25. "SWETYP,Software Error Type (cleared on read)" "0: A write-only register has been read (warning).,1: A write access has been performed on a read-only..,2: Access to an undefined address (warning).,3: A write access is performed into PIT64B_MR.."
|
|
newline
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 3. "SWE,Software Control Error (cleared on read)" "0: No software error has occurred since the last..,1: A software error has occurred since the last.."
|
|
newline
|
|
bitfld.long 0x0 2. "SEQE,Internal Sequencer Error (cleared on read)" "0: No peripheral internal sequencer error has..,1: A peripheral internal sequencer error has.."
|
|
bitfld.long 0x0 1. "CGD,Clock Glitch Detected (cleared on read)" "0: The clock monitoring circuitry has not been..,1: The clock monitoring circuitry has been.."
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status (cleared on read)" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
|
|
tree.end
|
|
tree "PIT64B1"
|
|
base ad:0xE1804000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 8. "SWRST,Software Reset" "0: No effect.,1: Performs a software reset clears the.."
|
|
bitfld.long 0x0 0. "START,Start Timer" "0: No effect.,1: The timer counter is started for 1 or more.."
|
|
group.long 0x4++0xB
|
|
line.long 0x0 "MR,Mode Register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "PRESCALER,Prescaler Period"
|
|
bitfld.long 0x0 4. "SMOD,Start Mode" "0: Writing PIT64B_LSBPR does not start the timer..,1: Writing PIT64B_LSBPR starts the timer period."
|
|
newline
|
|
bitfld.long 0x0 3. "SGCLK,Generic Clock Selection Enable" "0: The prescaler is triggered at each rising edge..,1: GCLK clock is selected as clock source of the.."
|
|
bitfld.long 0x0 0. "CONT,Continuous Mode" "0: A single period interrupt is generated from a..,1: Continuous periodic interrupts are generated.."
|
|
line.long 0x4 "LSBPR,LSB Period Register"
|
|
hexmask.long 0x4 0.--31. 1. "LSBPERIOD,32 LSB of the Timer Period"
|
|
line.long 0x8 "MSBPR,MSB Period Register"
|
|
hexmask.long 0x8 0.--31. 1. "MSBPERIOD,32 MSB of the Timer Period"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 4. "SECE,Safety and/or Security Report Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PERIOD,Elapsed Timer Period Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 4. "SECE,Safety and/or Security Report Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 1. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "PERIOD,Elapsed Timer Period Interrupt Disable" "0,1"
|
|
rgroup.long 0x18++0xF
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 4. "SECE,Safety and/or Security Report Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 1. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PERIOD,Elapsed Timer Period Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 4. "SECE,Safety/Security Report (cleared on read)" "0: There is no security report in PIT64B_WPSR since..,1: One security flag is set in PIT64B_WPSR since.."
|
|
bitfld.long 0x4 1. "OVRE,Overrun Error (cleared on read)" "0: No multiple rollovers occurred since the last..,1: More than 1 rollover occurred since the last.."
|
|
newline
|
|
bitfld.long 0x4 0. "PERIOD,Elapsed Timer Period Status Flag (cleared on read)" "0: No timer rollover occurred since the last read..,1: A timer rollover occurred since the last read of.."
|
|
line.long 0x8 "TLSBR,Timer LSB Current Value Register"
|
|
hexmask.long 0x8 0.--31. 1. "LSBTIMER,Current 32 LSB of the Timer"
|
|
line.long 0xC "TMSBR,Timer MSB Current Value Register"
|
|
hexmask.long 0xC 0.--31. 1. "MSBTIMER,Current 32 MSB of the Timer"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 4. "FIRSTE,First Error Report Enable" "0: The last write protection violation source is..,1: Only the first write protection violation source.."
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interruption Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
bitfld.long 0x0 31. "ECLASS,Software Error Class (cleared on read)" "0: An abnormal access that does not affect system..,1: A write access is performed into PIT64B_MR.."
|
|
bitfld.long 0x0 24.--25. "SWETYP,Software Error Type (cleared on read)" "0: A write-only register has been read (warning).,1: A write access has been performed on a read-only..,2: Access to an undefined address (warning).,3: A write access is performed into PIT64B_MR.."
|
|
newline
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 3. "SWE,Software Control Error (cleared on read)" "0: No software error has occurred since the last..,1: A software error has occurred since the last.."
|
|
newline
|
|
bitfld.long 0x0 2. "SEQE,Internal Sequencer Error (cleared on read)" "0: No peripheral internal sequencer error has..,1: A peripheral internal sequencer error has.."
|
|
bitfld.long 0x0 1. "CGD,Clock Glitch Detected (cleared on read)" "0: The clock monitoring circuitry has not been..,1: The clock monitoring circuitry has been.."
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status (cleared on read)" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
|
|
tree.end
|
|
tree "PIT64B2"
|
|
base ad:0xE1808000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 8. "SWRST,Software Reset" "0: No effect.,1: Performs a software reset clears the.."
|
|
bitfld.long 0x0 0. "START,Start Timer" "0: No effect.,1: The timer counter is started for 1 or more.."
|
|
group.long 0x4++0xB
|
|
line.long 0x0 "MR,Mode Register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "PRESCALER,Prescaler Period"
|
|
bitfld.long 0x0 4. "SMOD,Start Mode" "0: Writing PIT64B_LSBPR does not start the timer..,1: Writing PIT64B_LSBPR starts the timer period."
|
|
newline
|
|
bitfld.long 0x0 3. "SGCLK,Generic Clock Selection Enable" "0: The prescaler is triggered at each rising edge..,1: GCLK clock is selected as clock source of the.."
|
|
bitfld.long 0x0 0. "CONT,Continuous Mode" "0: A single period interrupt is generated from a..,1: Continuous periodic interrupts are generated.."
|
|
line.long 0x4 "LSBPR,LSB Period Register"
|
|
hexmask.long 0x4 0.--31. 1. "LSBPERIOD,32 LSB of the Timer Period"
|
|
line.long 0x8 "MSBPR,MSB Period Register"
|
|
hexmask.long 0x8 0.--31. 1. "MSBPERIOD,32 MSB of the Timer Period"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 4. "SECE,Safety and/or Security Report Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PERIOD,Elapsed Timer Period Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 4. "SECE,Safety and/or Security Report Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 1. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "PERIOD,Elapsed Timer Period Interrupt Disable" "0,1"
|
|
rgroup.long 0x18++0xF
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 4. "SECE,Safety and/or Security Report Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 1. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PERIOD,Elapsed Timer Period Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 4. "SECE,Safety/Security Report (cleared on read)" "0: There is no security report in PIT64B_WPSR since..,1: One security flag is set in PIT64B_WPSR since.."
|
|
bitfld.long 0x4 1. "OVRE,Overrun Error (cleared on read)" "0: No multiple rollovers occurred since the last..,1: More than 1 rollover occurred since the last.."
|
|
newline
|
|
bitfld.long 0x4 0. "PERIOD,Elapsed Timer Period Status Flag (cleared on read)" "0: No timer rollover occurred since the last read..,1: A timer rollover occurred since the last read of.."
|
|
line.long 0x8 "TLSBR,Timer LSB Current Value Register"
|
|
hexmask.long 0x8 0.--31. 1. "LSBTIMER,Current 32 LSB of the Timer"
|
|
line.long 0xC "TMSBR,Timer MSB Current Value Register"
|
|
hexmask.long 0xC 0.--31. 1. "MSBTIMER,Current 32 MSB of the Timer"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 4. "FIRSTE,First Error Report Enable" "0: The last write protection violation source is..,1: Only the first write protection violation source.."
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interruption Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
bitfld.long 0x0 31. "ECLASS,Software Error Class (cleared on read)" "0: An abnormal access that does not affect system..,1: A write access is performed into PIT64B_MR.."
|
|
bitfld.long 0x0 24.--25. "SWETYP,Software Error Type (cleared on read)" "0: A write-only register has been read (warning).,1: A write access has been performed on a read-only..,2: Access to an undefined address (warning).,3: A write access is performed into PIT64B_MR.."
|
|
newline
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 3. "SWE,Software Control Error (cleared on read)" "0: No software error has occurred since the last..,1: A software error has occurred since the last.."
|
|
newline
|
|
bitfld.long 0x0 2. "SEQE,Internal Sequencer Error (cleared on read)" "0: No peripheral internal sequencer error has..,1: A peripheral internal sequencer error has.."
|
|
bitfld.long 0x0 1. "CGD,Clock Glitch Detected (cleared on read)" "0: The clock monitoring circuitry has not been..,1: The clock monitoring circuitry has been.."
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status (cleared on read)" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
|
|
tree.end
|
|
tree "PIT64B3"
|
|
base ad:0xE2004000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 8. "SWRST,Software Reset" "0: No effect.,1: Performs a software reset clears the.."
|
|
bitfld.long 0x0 0. "START,Start Timer" "0: No effect.,1: The timer counter is started for 1 or more.."
|
|
group.long 0x4++0xB
|
|
line.long 0x0 "MR,Mode Register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "PRESCALER,Prescaler Period"
|
|
bitfld.long 0x0 4. "SMOD,Start Mode" "0: Writing PIT64B_LSBPR does not start the timer..,1: Writing PIT64B_LSBPR starts the timer period."
|
|
newline
|
|
bitfld.long 0x0 3. "SGCLK,Generic Clock Selection Enable" "0: The prescaler is triggered at each rising edge..,1: GCLK clock is selected as clock source of the.."
|
|
bitfld.long 0x0 0. "CONT,Continuous Mode" "0: A single period interrupt is generated from a..,1: Continuous periodic interrupts are generated.."
|
|
line.long 0x4 "LSBPR,LSB Period Register"
|
|
hexmask.long 0x4 0.--31. 1. "LSBPERIOD,32 LSB of the Timer Period"
|
|
line.long 0x8 "MSBPR,MSB Period Register"
|
|
hexmask.long 0x8 0.--31. 1. "MSBPERIOD,32 MSB of the Timer Period"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 4. "SECE,Safety and/or Security Report Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PERIOD,Elapsed Timer Period Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 4. "SECE,Safety and/or Security Report Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 1. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "PERIOD,Elapsed Timer Period Interrupt Disable" "0,1"
|
|
rgroup.long 0x18++0xF
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 4. "SECE,Safety and/or Security Report Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 1. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PERIOD,Elapsed Timer Period Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 4. "SECE,Safety/Security Report (cleared on read)" "0: There is no security report in PIT64B_WPSR since..,1: One security flag is set in PIT64B_WPSR since.."
|
|
bitfld.long 0x4 1. "OVRE,Overrun Error (cleared on read)" "0: No multiple rollovers occurred since the last..,1: More than 1 rollover occurred since the last.."
|
|
newline
|
|
bitfld.long 0x4 0. "PERIOD,Elapsed Timer Period Status Flag (cleared on read)" "0: No timer rollover occurred since the last read..,1: A timer rollover occurred since the last read of.."
|
|
line.long 0x8 "TLSBR,Timer LSB Current Value Register"
|
|
hexmask.long 0x8 0.--31. 1. "LSBTIMER,Current 32 LSB of the Timer"
|
|
line.long 0xC "TMSBR,Timer MSB Current Value Register"
|
|
hexmask.long 0xC 0.--31. 1. "MSBTIMER,Current 32 MSB of the Timer"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 4. "FIRSTE,First Error Report Enable" "0: The last write protection violation source is..,1: Only the first write protection violation source.."
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interruption Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
bitfld.long 0x0 31. "ECLASS,Software Error Class (cleared on read)" "0: An abnormal access that does not affect system..,1: A write access is performed into PIT64B_MR.."
|
|
bitfld.long 0x0 24.--25. "SWETYP,Software Error Type (cleared on read)" "0: A write-only register has been read (warning).,1: A write access has been performed on a read-only..,2: Access to an undefined address (warning).,3: A write access is performed into PIT64B_MR.."
|
|
newline
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 3. "SWE,Software Control Error (cleared on read)" "0: No software error has occurred since the last..,1: A software error has occurred since the last.."
|
|
newline
|
|
bitfld.long 0x0 2. "SEQE,Internal Sequencer Error (cleared on read)" "0: No peripheral internal sequencer error has..,1: A peripheral internal sequencer error has.."
|
|
bitfld.long 0x0 1. "CGD,Clock Glitch Detected (cleared on read)" "0: The clock monitoring circuitry has not been..,1: The clock monitoring circuitry has been.."
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status (cleared on read)" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
|
|
tree.end
|
|
tree "PIT64B4"
|
|
base ad:0xE2008000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 8. "SWRST,Software Reset" "0: No effect.,1: Performs a software reset clears the.."
|
|
bitfld.long 0x0 0. "START,Start Timer" "0: No effect.,1: The timer counter is started for 1 or more.."
|
|
group.long 0x4++0xB
|
|
line.long 0x0 "MR,Mode Register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "PRESCALER,Prescaler Period"
|
|
bitfld.long 0x0 4. "SMOD,Start Mode" "0: Writing PIT64B_LSBPR does not start the timer..,1: Writing PIT64B_LSBPR starts the timer period."
|
|
newline
|
|
bitfld.long 0x0 3. "SGCLK,Generic Clock Selection Enable" "0: The prescaler is triggered at each rising edge..,1: GCLK clock is selected as clock source of the.."
|
|
bitfld.long 0x0 0. "CONT,Continuous Mode" "0: A single period interrupt is generated from a..,1: Continuous periodic interrupts are generated.."
|
|
line.long 0x4 "LSBPR,LSB Period Register"
|
|
hexmask.long 0x4 0.--31. 1. "LSBPERIOD,32 LSB of the Timer Period"
|
|
line.long 0x8 "MSBPR,MSB Period Register"
|
|
hexmask.long 0x8 0.--31. 1. "MSBPERIOD,32 MSB of the Timer Period"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 4. "SECE,Safety and/or Security Report Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PERIOD,Elapsed Timer Period Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 4. "SECE,Safety and/or Security Report Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 1. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "PERIOD,Elapsed Timer Period Interrupt Disable" "0,1"
|
|
rgroup.long 0x18++0xF
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 4. "SECE,Safety and/or Security Report Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 1. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PERIOD,Elapsed Timer Period Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 4. "SECE,Safety/Security Report (cleared on read)" "0: There is no security report in PIT64B_WPSR since..,1: One security flag is set in PIT64B_WPSR since.."
|
|
bitfld.long 0x4 1. "OVRE,Overrun Error (cleared on read)" "0: No multiple rollovers occurred since the last..,1: More than 1 rollover occurred since the last.."
|
|
newline
|
|
bitfld.long 0x4 0. "PERIOD,Elapsed Timer Period Status Flag (cleared on read)" "0: No timer rollover occurred since the last read..,1: A timer rollover occurred since the last read of.."
|
|
line.long 0x8 "TLSBR,Timer LSB Current Value Register"
|
|
hexmask.long 0x8 0.--31. 1. "LSBTIMER,Current 32 LSB of the Timer"
|
|
line.long 0xC "TMSBR,Timer MSB Current Value Register"
|
|
hexmask.long 0xC 0.--31. 1. "MSBTIMER,Current 32 MSB of the Timer"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 4. "FIRSTE,First Error Report Enable" "0: The last write protection violation source is..,1: Only the first write protection violation source.."
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interruption Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
bitfld.long 0x0 31. "ECLASS,Software Error Class (cleared on read)" "0: An abnormal access that does not affect system..,1: A write access is performed into PIT64B_MR.."
|
|
bitfld.long 0x0 24.--25. "SWETYP,Software Error Type (cleared on read)" "0: A write-only register has been read (warning).,1: A write access has been performed on a read-only..,2: Access to an undefined address (warning).,3: A write access is performed into PIT64B_MR.."
|
|
newline
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 3. "SWE,Software Control Error (cleared on read)" "0: No software error has occurred since the last..,1: A software error has occurred since the last.."
|
|
newline
|
|
bitfld.long 0x0 2. "SEQE,Internal Sequencer Error (cleared on read)" "0: No peripheral internal sequencer error has..,1: A peripheral internal sequencer error has.."
|
|
bitfld.long 0x0 1. "CGD,Clock Glitch Detected (cleared on read)" "0: The clock monitoring circuitry has not been..,1: The clock monitoring circuitry has been.."
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status (cleared on read)" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
|
|
tree.end
|
|
tree "PIT64B5"
|
|
base ad:0xE2810000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 8. "SWRST,Software Reset" "0: No effect.,1: Performs a software reset clears the.."
|
|
bitfld.long 0x0 0. "START,Start Timer" "0: No effect.,1: The timer counter is started for 1 or more.."
|
|
group.long 0x4++0xB
|
|
line.long 0x0 "MR,Mode Register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "PRESCALER,Prescaler Period"
|
|
bitfld.long 0x0 4. "SMOD,Start Mode" "0: Writing PIT64B_LSBPR does not start the timer..,1: Writing PIT64B_LSBPR starts the timer period."
|
|
newline
|
|
bitfld.long 0x0 3. "SGCLK,Generic Clock Selection Enable" "0: The prescaler is triggered at each rising edge..,1: GCLK clock is selected as clock source of the.."
|
|
bitfld.long 0x0 0. "CONT,Continuous Mode" "0: A single period interrupt is generated from a..,1: Continuous periodic interrupts are generated.."
|
|
line.long 0x4 "LSBPR,LSB Period Register"
|
|
hexmask.long 0x4 0.--31. 1. "LSBPERIOD,32 LSB of the Timer Period"
|
|
line.long 0x8 "MSBPR,MSB Period Register"
|
|
hexmask.long 0x8 0.--31. 1. "MSBPERIOD,32 MSB of the Timer Period"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 4. "SECE,Safety and/or Security Report Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PERIOD,Elapsed Timer Period Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 4. "SECE,Safety and/or Security Report Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 1. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "PERIOD,Elapsed Timer Period Interrupt Disable" "0,1"
|
|
rgroup.long 0x18++0xF
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 4. "SECE,Safety and/or Security Report Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 1. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PERIOD,Elapsed Timer Period Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 4. "SECE,Safety/Security Report (cleared on read)" "0: There is no security report in PIT64B_WPSR since..,1: One security flag is set in PIT64B_WPSR since.."
|
|
bitfld.long 0x4 1. "OVRE,Overrun Error (cleared on read)" "0: No multiple rollovers occurred since the last..,1: More than 1 rollover occurred since the last.."
|
|
newline
|
|
bitfld.long 0x4 0. "PERIOD,Elapsed Timer Period Status Flag (cleared on read)" "0: No timer rollover occurred since the last read..,1: A timer rollover occurred since the last read of.."
|
|
line.long 0x8 "TLSBR,Timer LSB Current Value Register"
|
|
hexmask.long 0x8 0.--31. 1. "LSBTIMER,Current 32 LSB of the Timer"
|
|
line.long 0xC "TMSBR,Timer MSB Current Value Register"
|
|
hexmask.long 0xC 0.--31. 1. "MSBTIMER,Current 32 MSB of the Timer"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 4. "FIRSTE,First Error Report Enable" "0: The last write protection violation source is..,1: Only the first write protection violation source.."
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interruption Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
bitfld.long 0x0 31. "ECLASS,Software Error Class (cleared on read)" "0: An abnormal access that does not affect system..,1: A write access is performed into PIT64B_MR.."
|
|
bitfld.long 0x0 24.--25. "SWETYP,Software Error Type (cleared on read)" "0: A write-only register has been read (warning).,1: A write access has been performed on a read-only..,2: Access to an undefined address (warning).,3: A write access is performed into PIT64B_MR.."
|
|
newline
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 3. "SWE,Software Control Error (cleared on read)" "0: No software error has occurred since the last..,1: A software error has occurred since the last.."
|
|
newline
|
|
bitfld.long 0x0 2. "SEQE,Internal Sequencer Error (cleared on read)" "0: No peripheral internal sequencer error has..,1: A peripheral internal sequencer error has.."
|
|
bitfld.long 0x0 1. "CGD,Clock Glitch Detected (cleared on read)" "0: The clock monitoring circuitry has not been..,1: The clock monitoring circuitry has been.."
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status (cleared on read)" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
|
|
tree.end
|
|
tree.end
|
|
tree "PMC (Power Management Controller)"
|
|
base ad:0xE0018000
|
|
wgroup.long 0x0++0x7
|
|
line.long 0x0 "SCER,System Clock Enable Register"
|
|
bitfld.long 0x0 15. "PCK7,Programmable Clock 7 Output Enable" "0: No effect.,1: Enables the corresponding Programmable Clock.."
|
|
bitfld.long 0x0 14. "PCK6,Programmable Clock 6 Output Enable" "0: No effect.,1: Enables the corresponding Programmable Clock.."
|
|
newline
|
|
bitfld.long 0x0 13. "PCK5,Programmable Clock 5 Output Enable" "0: No effect.,1: Enables the corresponding Programmable Clock.."
|
|
bitfld.long 0x0 12. "PCK4,Programmable Clock 4 Output Enable" "0: No effect.,1: Enables the corresponding Programmable Clock.."
|
|
newline
|
|
bitfld.long 0x0 11. "PCK3,Programmable Clock 3 Output Enable" "0: No effect.,1: Enables the corresponding Programmable Clock.."
|
|
bitfld.long 0x0 10. "PCK2,Programmable Clock 2 Output Enable" "0: No effect.,1: Enables the corresponding Programmable Clock.."
|
|
newline
|
|
bitfld.long 0x0 9. "PCK1,Programmable Clock 1 Output Enable" "0: No effect.,1: Enables the corresponding Programmable Clock.."
|
|
bitfld.long 0x0 8. "PCK0,Programmable Clock 0 Output Enable" "0: No effect.,1: Enables the corresponding Programmable Clock.."
|
|
line.long 0x4 "SCDR,System Clock Disable Register"
|
|
bitfld.long 0x4 15. "PCK7,Programmable Clock 7 Output Disable" "0: No effect.,1: Disables the corresponding Programmable Clock.."
|
|
bitfld.long 0x4 14. "PCK6,Programmable Clock 6 Output Disable" "0: No effect.,1: Disables the corresponding Programmable Clock.."
|
|
newline
|
|
bitfld.long 0x4 13. "PCK5,Programmable Clock 5 Output Disable" "0: No effect.,1: Disables the corresponding Programmable Clock.."
|
|
bitfld.long 0x4 12. "PCK4,Programmable Clock 4 Output Disable" "0: No effect.,1: Disables the corresponding Programmable Clock.."
|
|
newline
|
|
bitfld.long 0x4 11. "PCK3,Programmable Clock 3 Output Disable" "0: No effect.,1: Disables the corresponding Programmable Clock.."
|
|
bitfld.long 0x4 10. "PCK2,Programmable Clock 2 Output Disable" "0: No effect.,1: Disables the corresponding Programmable Clock.."
|
|
newline
|
|
bitfld.long 0x4 9. "PCK1,Programmable Clock 1 Output Disable" "0: No effect.,1: Disables the corresponding Programmable Clock.."
|
|
bitfld.long 0x4 8. "PCK0,Programmable Clock 0 Output Disable" "0: No effect.,1: Disables the corresponding Programmable Clock.."
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "SCSR,System Clock Status Register"
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bitfld.long 0x0 15. "PCK7,Programmable Clock 7 Output Status" "0: The corresponding Programmable Clock output is..,1: The corresponding Programmable Clock output is.."
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bitfld.long 0x0 14. "PCK6,Programmable Clock 6 Output Status" "0: The corresponding Programmable Clock output is..,1: The corresponding Programmable Clock output is.."
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bitfld.long 0x0 13. "PCK5,Programmable Clock 5 Output Status" "0: The corresponding Programmable Clock output is..,1: The corresponding Programmable Clock output is.."
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bitfld.long 0x0 12. "PCK4,Programmable Clock 4 Output Status" "0: The corresponding Programmable Clock output is..,1: The corresponding Programmable Clock output is.."
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bitfld.long 0x0 11. "PCK3,Programmable Clock 3 Output Status" "0: The corresponding Programmable Clock output is..,1: The corresponding Programmable Clock output is.."
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bitfld.long 0x0 10. "PCK2,Programmable Clock 2 Output Status" "0: The corresponding Programmable Clock output is..,1: The corresponding Programmable Clock output is.."
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newline
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bitfld.long 0x0 9. "PCK1,Programmable Clock 1 Output Status" "0: The corresponding Programmable Clock output is..,1: The corresponding Programmable Clock output is.."
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bitfld.long 0x0 8. "PCK0,Programmable Clock 0 Output Status" "0: The corresponding Programmable Clock output is..,1: The corresponding Programmable Clock output is.."
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group.long 0xC++0x2B
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line.long 0x0 "PLL_CTRL0,PLL Control Register 0"
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bitfld.long 0x0 31. "ENLOCK,Enable PLL Lock" "0: The lock signal sent by the PLL is ignored. The..,1: The PLL is considered as locked once the.."
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bitfld.long 0x0 30. "ENIOPLLCK,Enable PLL Clock for IO" "0: The clock generated by the PLL is not send to..,1: The clock generated by the PLL is sent to the IO."
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newline
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bitfld.long 0x0 29. "ENPLLCK,Enable PLL Clock for PMC" "0: The clock generated by the PLL is not send to..,1: The clock generated by the PLL is sent to the.."
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bitfld.long 0x0 28. "ENPLL,Enable PLL" "0: The PLL is off.,1: The PLL is on."
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newline
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hexmask.long.byte 0x0 12.--19. 1. "DIVIO,Divider for PAD"
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hexmask.long.byte 0x0 0.--7. 1. "DIVPMC,Divider for PMC"
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line.long 0x4 "PLL_CTRL1,PLL Control Register 1"
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hexmask.long.byte 0x4 24.--31. 1. "MUL,Multiplier Factor Value"
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hexmask.long.tbyte 0x4 0.--21. 1. "FRACR,Fractional Loop Divider Setting"
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line.long 0x8 "PLL_SSR,PLL Spread Spectrum Register"
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bitfld.long 0x8 28. "ENSPREAD,Spread Spectrum Enable" "0: The spread spectrum is not applied to the PLL.,1: The spread spectrum is applied to the PLL."
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hexmask.long.byte 0x8 16.--23. 1. "NSTEP,Spread Spectrum Number of Steps"
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newline
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hexmask.long.word 0x8 0.--15. 1. "STEP,Spread Spectrum Step Size"
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line.long 0xC "PLL_ACR,PLL Analog Control Register"
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hexmask.long.byte 0xC 24.--29. 1. "LOOP_FILTER,LOOP Filter Selection"
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bitfld.long 0xC 16.--18. "LOCK_THR,PLL Lock Threshold Value Selection" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.word 0xC 0.--11. 1. "CONTROL,PLL CONTROL Value Selection"
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line.long 0x10 "PLL_UPDT,PLL Update Register"
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hexmask.long.byte 0x10 16.--21. 1. "STUPTIM,Start-up Time"
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bitfld.long 0x10 8. "UPDATE,PLL Setting Update (write-only)" "0: No effect.,1: The PLL configuration written in PMC_PLL_CTRL0.."
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newline
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hexmask.long.byte 0x10 0.--3. 1. "ID,PLL ID"
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line.long 0x14 "CKGR_MOR,Main Oscillator Register"
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bitfld.long 0x14 30. "AUTOCPUSW,Automatic Processor Clock Source Switching" "0: A main crystal oscillator failure detection has..,1: If a main crystal oscillator failure is detected.."
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bitfld.long 0x14 29. "AUTOMAINSW,Automatic Main Clock Source Switching" "0: A main crystal oscillator failure detection has..,1: If a main crystal oscillator failure is detected.."
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newline
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bitfld.long 0x14 28. "BMCKIC,Bad MCK0 Clock Interrupt" "0: An MCK0 clock failure has no effect on the..,1: An MCK0 clock failure detection sends an.."
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bitfld.long 0x14 27. "BMCKRST,Bad MCK0 Clock Reset Enable" "0: An MCK0 clock failure detection cannot reset the..,1: An MCK0 clock failure detection can reset the.."
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newline
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bitfld.long 0x14 26. "XT32KFME,32.768 kHz Crystal Oscillator Frequency Monitoring Enable" "0: The 32.768 kHz crystal oscillator frequency..,1: The 32.768 kHz crystal oscillator frequency.."
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bitfld.long 0x14 25. "CFDEN,Clock Failure Detector Enable" "0: The clock failure detector is disabled.,1: The clock failure detector is enabled."
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newline
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bitfld.long 0x14 24. "MOSCSEL,Main Clock Oscillator Selection" "0: The main RC oscillator is selected.,1: The main crystal oscillator is selected."
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hexmask.long.byte 0x14 16.--23. 1. "KEY,Write Access Password"
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newline
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hexmask.long.byte 0x14 8.--15. 1. "MOSCXTST,Main Crystal Oscillator Start-up Time"
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bitfld.long 0x14 7. "ULP2,ULP Mode 2 Command (write-only)" "0: No effect.,1: Enables the device to enter ULP mode 2. ULP mode.."
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newline
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bitfld.long 0x14 3. "MOSCRCEN,Main RC Oscillator Enable" "0: The main RC oscillator is disabled.,1: The main RC oscillator is enabled."
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bitfld.long 0x14 2. "ULP1,ULP Mode 1 Command (write-only)" "0: No effect.,1: Puts the device in ULP mode 1."
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newline
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bitfld.long 0x14 0. "MOSCXTEN,Main Crystal Oscillator Enable" "0: The main crystal oscillator is disabled.,1: The main crystal oscillator is enabled or in.."
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line.long 0x18 "CKGR_MCFR,Main Clock Frequency Register"
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bitfld.long 0x18 24. "CCSS,Counter Clock Source Selection" "0: The measured clock of the MAINF counter is the..,1: The measured clock of the MAINF counter is the.."
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bitfld.long 0x18 20. "RCMEAS,RC Oscillator Frequency Measure (write-only)" "0: No effect.,1: Restarts measuring of the frequency of MAINCK."
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newline
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bitfld.long 0x18 16. "MAINFRDY,Main Clock Frequency Measure Ready" "0: MAINF value is not valid or the measured..,1: The measured oscillator has been enabled.."
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hexmask.long.word 0x18 0.--15. 1. "MAINF,Main Clock Frequency"
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line.long 0x1C "CPU_CKR,CPU Clock Register"
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bitfld.long 0x1C 8.--10. "MDIV,MCK0 Division" "0: MCK0 is FCLK divided by 1.,1: MCK0 is FCLK divided by 2.,2: MCK0 is FCLK divided by 4.,3: MCK0 is FCLK divided by 3.,4: MCK0 is FCLK divided by 5.,?,?,?"
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bitfld.long 0x1C 4.--6. "PRES,Processor Clock Prescaler" "0: Selected clock,1: Selected clock divided by 2,2: Selected clock divided by 4,3: Selected clock divided by 8,4: Selected clock divided by 16,5: Selected clock divided by 32,6: Selected clock divided by 64,7: Selected clock divided by 3"
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newline
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bitfld.long 0x1C 0.--1. "CSS,MCK0 Source Selection" "0: MD_SLCK is selected,1: MAINCK is selected,2: CPUPLLCK is selected,3: SYSPLLCK is selected"
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line.long 0x20 "CPU_RATIO,CPU Clock Ratio Register"
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hexmask.long.byte 0x20 0.--3. 1. "RATIO,CPU Clock Ratio"
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line.long 0x24 "MCR,Master Clock Register"
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bitfld.long 0x24 28. "EN,Master Clock Enable" "0: The corresponding MCKx is disabled.,1: The corresponding MCKx is enabled."
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hexmask.long.byte 0x24 16.--20. 1. "CSS,Clock Source Selection"
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newline
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bitfld.long 0x24 8.--10. "DIV,Divisor Value" "0: Selected clock divided by 1,1: Selected clock divided by 2,2: Selected clock divided by 4,3: Selected clock divided by 8,4: Selected clock divided by 16,5: Selected clock divided by 32,6: Selected clock divided by 64,7: Selected clock divided by 3"
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bitfld.long 0x24 7. "CMD,Command" "0: Read mode.,1: Write mode."
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newline
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hexmask.long.byte 0x24 0.--3. 1. "ID,Master Clock Index"
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line.long 0x28 "XTALF,Main XTAL Frequency Register"
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bitfld.long 0x28 0.--2. "XTALF,Crystal Frequency" "0: The main crystal frequency is 16 MHz.,?,2: The main crystal frequency is 20 MHz.,3: The main crystal frequency is 24 MHz.,?,5: The main crystal frequency is 32 MHz.,?,?"
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repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
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group.long ($2+0x40)++0x3
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line.long 0x0 "PCK[$1],Programmable Clock Register x"
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hexmask.long.byte 0x0 8.--15. 1. "PRES,Programmable Clock Prescaler"
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hexmask.long.byte 0x0 0.--4. 1. "CSS,Programmable Clock Source Selection"
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repeat.end
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wgroup.long 0x60++0x7
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line.long 0x0 "IER,Interrupt Enable Register"
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bitfld.long 0x0 26. "MCKXRDY,Master Clock x [x=1..4] Ready Interrupt Enable" "0,1"
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bitfld.long 0x0 25. "PLL_INT,PLL Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 23. "MCKMON,Master Clock 0 Clock Monitor Interrupt Enable" "0,1"
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bitfld.long 0x0 21. "XT32KERR,32.768 kHz Crystal Oscillator Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 18. "CFDEV,Clock Failure Detector Event Interrupt Enable" "0,1"
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bitfld.long 0x0 17. "MOSCRCS,Main RC Oscillator Status Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 16. "MOSCSELS,Main Clock Source Oscillator Selection Status Interrupt Enable" "0,1"
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bitfld.long 0x0 15. "PCKRDY7,Programmable Clock Ready 7 Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 14. "PCKRDY6,Programmable Clock Ready 6 Interrupt Enable" "0,1"
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bitfld.long 0x0 13. "PCKRDY5,Programmable Clock Ready 5 Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 12. "PCKRDY4,Programmable Clock Ready 4 Interrupt Enable" "0,1"
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bitfld.long 0x0 11. "PCKRDY3,Programmable Clock Ready 3 Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 10. "PCKRDY2,Programmable Clock Ready 2 Interrupt Enable" "0,1"
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bitfld.long 0x0 9. "PCKRDY1,Programmable Clock Ready 1 Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 8. "PCKRDY0,Programmable Clock Ready 0 Interrupt Enable" "0,1"
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bitfld.long 0x0 3. "MCKRDY,Master Clock 0 Ready Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 0. "MOSCXTS,Main Crystal Oscillator Status Interrupt Enable" "0,1"
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line.long 0x4 "IDR,Interrupt Disable Register"
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bitfld.long 0x4 26. "MCKXRDY,Master Clock x [x=1..4] Ready Interrupt Enable" "0,1"
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bitfld.long 0x4 25. "PLL_INT,PLL Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 23. "MCKMON,Master Clock 0 Clock Monitor Interrupt Disable" "0,1"
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bitfld.long 0x4 21. "XT32KERR,32.768 kHz Crystal Oscillator Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 18. "CFDEV,Clock Failure Detector Event Interrupt Disable" "0,1"
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bitfld.long 0x4 17. "MOSCRCS,Main RC Status Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 16. "MOSCSELS,Main Clock Source Oscillator Selection Status Interrupt Disable" "0,1"
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bitfld.long 0x4 15. "PCKRDY7,Programmable Clock Ready 7 Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 14. "PCKRDY6,Programmable Clock Ready 6 Interrupt Disable" "0,1"
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bitfld.long 0x4 13. "PCKRDY5,Programmable Clock Ready 5 Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 12. "PCKRDY4,Programmable Clock Ready 4 Interrupt Disable" "0,1"
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bitfld.long 0x4 11. "PCKRDY3,Programmable Clock Ready 3 Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 10. "PCKRDY2,Programmable Clock Ready 2 Interrupt Disable" "0,1"
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bitfld.long 0x4 9. "PCKRDY1,Programmable Clock Ready 1 Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 8. "PCKRDY0,Programmable Clock Ready 0 Interrupt Disable" "0,1"
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bitfld.long 0x4 3. "MCKRDY,Master Clock 0 Ready Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 0. "MOSCXTS,Main Crystal Oscillator Status Interrupt Disable" "0,1"
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rgroup.long 0x68++0x7
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line.long 0x0 "SR,Status Register"
|
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bitfld.long 0x0 26. "MCKXRDY,Master Clock x [x=1..4] Ready Status" "0: At least one Master Clock is not established.,1: AlL Master Clocks are established."
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bitfld.long 0x0 25. "PLL_INT,PLL Interrupt Status" "0: No PLL interrupt has occurred.,1: A PLL interrupt has occurred. PLL interrupt is.."
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newline
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bitfld.long 0x0 24. "GCLKRDY,GCLK Ready" "0: A GCLK is not ready to use (clock switching in..,1: All GCLKs are switched to their selected source.."
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bitfld.long 0x0 23. "MCKMON,Master Clock 0 Clock Monitor Error" "0: The Master Clock 0 is correct or the CPU clock..,1: The Master Clock 0 is incorrect or has been.."
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newline
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bitfld.long 0x0 21. "XT32KERR,Slow Crystal Oscillator Error" "0: The frequency of the 32.768 kHz crystal..,1: The frequency of the 32.768 kHz crystal.."
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bitfld.long 0x0 20. "FOS,Clock Failure Detector Fault Output Status" "0: The fault output of the clock failure detector..,1: The fault output of the clock failure detector.."
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newline
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bitfld.long 0x0 19. "CFDS,Clock Failure Detector Status" "0: A clock failure of the main crystal oscillator..,1: A clock failure of the main crystal oscillator.."
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bitfld.long 0x0 18. "CFDEV,Clock Failure Detector Event" "0: No clock failure detection of the main crystal..,1: At least one clock failure detection of the main.."
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newline
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bitfld.long 0x0 17. "MOSCRCS,Main RC Oscillator Status" "0: Main RC oscillator is not stabilized.,1: Main RC oscillator is stabilized."
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bitfld.long 0x0 16. "MOSCSELS,Main Clock Source Oscillator Selection Status" "0: Selection is in progress.,1: Selection is done."
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newline
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bitfld.long 0x0 15. "PCKRDY7,Programmable Clock Ready Status" "0: Programmable Clock x is not ready.,1: Programmable Clock x is ready."
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bitfld.long 0x0 14. "PCKRDY6,Programmable Clock Ready Status" "0: Programmable Clock x is not ready.,1: Programmable Clock x is ready."
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newline
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bitfld.long 0x0 13. "PCKRDY5,Programmable Clock Ready Status" "0: Programmable Clock x is not ready.,1: Programmable Clock x is ready."
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bitfld.long 0x0 12. "PCKRDY4,Programmable Clock Ready Status" "0: Programmable Clock x is not ready.,1: Programmable Clock x is ready."
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newline
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bitfld.long 0x0 11. "PCKRDY3,Programmable Clock Ready Status" "0: Programmable Clock x is not ready.,1: Programmable Clock x is ready."
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bitfld.long 0x0 10. "PCKRDY2,Programmable Clock Ready Status" "0: Programmable Clock x is not ready.,1: Programmable Clock x is ready."
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newline
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bitfld.long 0x0 9. "PCKRDY1,Programmable Clock Ready Status" "0: Programmable Clock x is not ready.,1: Programmable Clock x is ready."
|
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bitfld.long 0x0 8. "PCKRDY0,Programmable Clock Ready Status" "0: Programmable Clock x is not ready.,1: Programmable Clock x is ready."
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newline
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bitfld.long 0x0 7. "OSCSELS,Timing Domain Slow Clock Oscillator Selection" "0: Embedded slow RC oscillator is selected.,1: 32.768 kHz crystal oscillator is selected."
|
|
bitfld.long 0x0 3. "MCKRDY,Master Clock 0 Status" "0: Master Clock 0 is not ready.,1: Master Clock 0 is ready."
|
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newline
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bitfld.long 0x0 0. "MOSCXTS,Main Crystal Oscillator Status" "0: Main crystal oscillator is not stabilized.,1: Main crystal oscillator is stabilized."
|
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line.long 0x4 "IMR,Interrupt Mask Register"
|
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bitfld.long 0x4 26. "MCKXRDY,Master Clock x [x=1..4] Ready Interrupt Mask" "0,1"
|
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bitfld.long 0x4 25. "PLL_INT,PLL Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x4 23. "MCKMON,Master Clock 0 Monitor Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 21. "XT32KERR,32.768 kHz Crystal Oscillator Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x4 18. "CFDEV,Clock Failure Detector Event Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 17. "MOSCRCS,Main RC Status Interrupt Mask" "0,1"
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newline
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bitfld.long 0x4 16. "MOSCSELS,Main Clock Source Oscillator Selection Status Interrupt Mask" "0,1"
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bitfld.long 0x4 15. "PCKRDY7,Programmable Clock Ready 7 Interrupt Mask" "0,1"
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newline
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bitfld.long 0x4 14. "PCKRDY6,Programmable Clock Ready 6 Interrupt Mask" "0,1"
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bitfld.long 0x4 13. "PCKRDY5,Programmable Clock Ready 5 Interrupt Mask" "0,1"
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newline
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bitfld.long 0x4 12. "PCKRDY4,Programmable Clock Ready 4 Interrupt Mask" "0,1"
|
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bitfld.long 0x4 11. "PCKRDY3,Programmable Clock Ready 3 Interrupt Mask" "0,1"
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newline
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bitfld.long 0x4 10. "PCKRDY2,Programmable Clock Ready 2 Interrupt Mask" "0,1"
|
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bitfld.long 0x4 9. "PCKRDY1,Programmable Clock Ready 1 Interrupt Mask" "0,1"
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newline
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bitfld.long 0x4 8. "PCKRDY0,Programmable Clock Ready 0 Interrupt Mask" "0,1"
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|
bitfld.long 0x4 3. "MCKRDY,Master Clock 0 Ready Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x4 0. "MOSCXTS,Main Crystal Oscillator Status Interrupt Mask" "0,1"
|
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group.long 0x70++0x7
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line.long 0x0 "FSMR,Fast Startup Mode Register"
|
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bitfld.long 0x0 19. "HSDHC,HSDHC Alarm" "0: The HSDHC alarm has no effect on the PMC.,1: The HSDHC alarm enables a fast restart signal to.."
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bitfld.long 0x0 18. "USBAL,USB Alarm Enable" "0: The USB alarm has no effect on the IP_Acronym.,1: The USB alarm enables a fast restart signal to.."
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newline
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bitfld.long 0x0 17. "RTCAL,RTC Alarm Enable" "0: The RTC alarm has no effect on the IP_Acronym.,1: The RTC alarm enables a fast restart signal to.."
|
|
bitfld.long 0x0 16. "RTTAL,RTT Alarm Enable" "0: The RTT alarm has no effect on the IP_Acronym.,1: The RTT alarm enables a fast restart signal to.."
|
|
line.long 0x4 "WCR,Wakeup Control Register"
|
|
bitfld.long 0x4 24. "CMD,Command" "0: Read mode.,1: Write mode."
|
|
bitfld.long 0x4 17. "WIP,Wakeup Input Polarity" "0,1"
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newline
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bitfld.long 0x4 16. "EN,Wakeup Input Enable" "0: The selected wakeup input has no effect on the..,1: The selected wakeup input enables a fast restart.."
|
|
hexmask.long.byte 0x4 0.--7. 1. "WKPIONB,Wakeup Input Number"
|
|
wgroup.long 0x78++0x3
|
|
line.long 0x0 "FOCR,Fault Output Clear Register"
|
|
bitfld.long 0x0 0. "FOCLR,Fault Output Clear" "0,1"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
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newline
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
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rgroup.long 0x84++0x3
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line.long 0x0 "WPSR,Write Protection Status Register"
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|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
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|
group.long 0x88++0x3
|
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line.long 0x0 "PCR,Peripheral Control Register"
|
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bitfld.long 0x0 31. "CMD,Command" "0: Read mode.,1: Write mode."
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bitfld.long 0x0 29. "GCLKEN,Generic Clock Enable" "0: The selected generic clock is disabled.,1: The selected generic clock is enabled."
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newline
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bitfld.long 0x0 28. "EN,Enable" "0: Selected Peripheral clock is disabled.,1: Selected Peripheral clock is enabled."
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|
hexmask.long.byte 0x0 20.--27. 1. "GCLKDIV,Generic Clock Division Ratio"
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newline
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hexmask.long.byte 0x0 16.--19. 1. "MCKID,Master Clock Index (Read-only)"
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|
hexmask.long.byte 0x0 8.--12. 1. "GCLKCSS,Generic Clock Source Selection"
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newline
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hexmask.long.byte 0x0 0.--6. 1. "PID,Peripheral ID"
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rgroup.long 0x90++0x3
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line.long 0x0 "SLPWK_AIPR,SleepWalking Activity In Progress Register"
|
|
bitfld.long 0x0 0. "AIP,Activity In Progress" "0: There is no activity on peripherals. The..,1: One or more peripherals are currently active."
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|
group.long 0x94++0x3
|
|
line.long 0x0 "SLPWKCR,SleepWalking Control Register"
|
|
bitfld.long 0x0 28. "SLPWKSR,SleepWalking Sleep Register" "0: The asynchronous partial wakeup (SleepWalking)..,1: The asynchronous partial wakeup (SleepWalking).."
|
|
bitfld.long 0x0 16. "ASR,Activity Status Register" "0: The peripheral x is not currently active; the..,1: The peripheral x is currently active; the.."
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newline
|
|
bitfld.long 0x0 12. "CMD,Command" "0: Read mode.,1: Write mode."
|
|
hexmask.long.byte 0x0 0.--6. 1. "PID,Peripheral ID"
|
|
group.long 0x9C++0x3
|
|
line.long 0x0 "MCKLIM,MCK0 Monitor Limits Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "MCK_HIGH_RES,MCK0 Monitoring High Reset Limit"
|
|
hexmask.long.byte 0x0 16.--23. 1. "MCK_LOW_RES,MCK0 Monitoring Low RESET Limit"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "MCK_HIGH_IT,MCK0 Monitoring High IT Limit"
|
|
hexmask.long.byte 0x0 0.--7. 1. "MCK_LOW_IT,MCK0 Monitoring Low IT Limit"
|
|
rgroup.long 0xA0++0xF
|
|
line.long 0x0 "CSR0,Peripheral Clock Status Register 0"
|
|
bitfld.long 0x0 30. "PID30,Peripheral Clock 30 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
bitfld.long 0x0 28. "PID28,Peripheral Clock 28 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
newline
|
|
bitfld.long 0x0 27. "PID27,Peripheral Clock 27 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
bitfld.long 0x0 25. "PID25,Peripheral Clock 25 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
newline
|
|
bitfld.long 0x0 24. "PID24,Peripheral Clock 24 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
bitfld.long 0x0 23. "PID23,Peripheral Clock 23 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
newline
|
|
bitfld.long 0x0 22. "PID22,Peripheral Clock 22 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
bitfld.long 0x0 21. "PID21,Peripheral Clock 21 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
newline
|
|
bitfld.long 0x0 19. "PID19,Peripheral Clock 19 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
bitfld.long 0x0 11. "PID11,Peripheral Clock 11 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
line.long 0x4 "CSR1,Peripheral Clock Status Register 1"
|
|
bitfld.long 0x4 31. "PID63,Peripheral Clock 63 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
bitfld.long 0x4 30. "PID62,Peripheral Clock 62 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
newline
|
|
bitfld.long 0x4 29. "PID61,Peripheral Clock 61 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
bitfld.long 0x4 28. "PID60,Peripheral Clock 60 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
newline
|
|
bitfld.long 0x4 26. "PID58,Peripheral Clock 58 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
bitfld.long 0x4 25. "PID57,Peripheral Clock 57 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
newline
|
|
bitfld.long 0x4 24. "PID56,Peripheral Clock 56 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
bitfld.long 0x4 23. "PID55,Peripheral Clock 55 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
newline
|
|
bitfld.long 0x4 20. "PID52,Peripheral Clock 52 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
bitfld.long 0x4 19. "PID51,Peripheral Clock 51 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
newline
|
|
bitfld.long 0x4 17. "PID49,Peripheral Clock 49 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
bitfld.long 0x4 16. "PID48,Peripheral Clock 48 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
newline
|
|
bitfld.long 0x4 15. "PID47,Peripheral Clock 47 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
bitfld.long 0x4 14. "PID46,Peripheral Clock 46 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
newline
|
|
bitfld.long 0x4 13. "PID45,Peripheral Clock 45 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
bitfld.long 0x4 12. "PID44,Peripheral Clock 44 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
newline
|
|
bitfld.long 0x4 11. "PID43,Peripheral Clock 43 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
bitfld.long 0x4 10. "PID42,Peripheral Clock 42 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
newline
|
|
bitfld.long 0x4 9. "PID41,Peripheral Clock 41 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
bitfld.long 0x4 8. "PID40,Peripheral Clock 40 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
newline
|
|
bitfld.long 0x4 7. "PID39,Peripheral Clock 39 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
bitfld.long 0x4 6. "PID38,Peripheral Clock 38 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
newline
|
|
bitfld.long 0x4 5. "PID37,Peripheral Clock 37 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
bitfld.long 0x4 2. "PID34,Peripheral Clock 34 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
newline
|
|
bitfld.long 0x4 1. "PID33,Peripheral Clock 33 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
bitfld.long 0x4 0. "PID32,Peripheral Clock 32 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
line.long 0x8 "CSR2,Peripheral Clock Status Register 2"
|
|
bitfld.long 0x8 31. "PID95,Peripheral Clock 95 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
bitfld.long 0x8 30. "PID94,Peripheral Clock 94 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
newline
|
|
bitfld.long 0x8 29. "PID93,Peripheral Clock 93 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
bitfld.long 0x8 28. "PID92,Peripheral Clock 92 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
newline
|
|
bitfld.long 0x8 27. "PID91,Peripheral Clock 91 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
bitfld.long 0x8 26. "PID90,Peripheral Clock 90 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
newline
|
|
bitfld.long 0x8 25. "PID89,Peripheral Clock 89 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
bitfld.long 0x8 24. "PID88,Peripheral Clock 88 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
newline
|
|
bitfld.long 0x8 23. "PID87,Peripheral Clock 87 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
bitfld.long 0x8 22. "PID86,Peripheral Clock 86 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
newline
|
|
bitfld.long 0x8 21. "PID85,Peripheral Clock 85 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
bitfld.long 0x8 20. "PID84,Peripheral Clock 84 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
newline
|
|
bitfld.long 0x8 19. "PID83,Peripheral Clock 83 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
bitfld.long 0x8 18. "PID82,Peripheral Clock 82 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
newline
|
|
bitfld.long 0x8 17. "PID81,Peripheral Clock 81 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
bitfld.long 0x8 16. "PID80,Peripheral Clock 80 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
newline
|
|
bitfld.long 0x8 15. "PID79,Peripheral Clock 79 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
bitfld.long 0x8 14. "PID78,Peripheral Clock 78 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
newline
|
|
bitfld.long 0x8 13. "PID77,Peripheral Clock 77 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
bitfld.long 0x8 11. "PID75,Peripheral Clock 75 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
newline
|
|
bitfld.long 0x8 10. "PID74,Peripheral Clock 74 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
bitfld.long 0x8 9. "PID73,Peripheral Clock 73 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
newline
|
|
bitfld.long 0x8 8. "PID72,Peripheral Clock 72 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
bitfld.long 0x8 7. "PID71,Peripheral Clock 71 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
newline
|
|
bitfld.long 0x8 6. "PID70,Peripheral Clock 70 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
bitfld.long 0x8 5. "PID69,Peripheral Clock 69 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
newline
|
|
bitfld.long 0x8 4. "PID68,Peripheral Clock 68 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
bitfld.long 0x8 2. "PID66,Peripheral Clock 66 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
newline
|
|
bitfld.long 0x8 1. "PID65,Peripheral Clock 65 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
bitfld.long 0x8 0. "PID64,Peripheral Clock 64 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
line.long 0xC "CSR3,Peripheral Clock Status Register 3"
|
|
bitfld.long 0xC 10. "PID106,Peripheral Clock 106 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
bitfld.long 0xC 9. "PID105,Peripheral Clock 105 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
newline
|
|
bitfld.long 0xC 8. "PID104,Peripheral Clock 104 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
bitfld.long 0xC 2. "PID98,Peripheral Clock 98 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
newline
|
|
bitfld.long 0xC 1. "PID97,Peripheral Clock 97 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
bitfld.long 0xC 0. "PID96,Peripheral Clock 96 Status" "0: The corresponding peripheral clock is disabled.,1: The corresponding peripheral clock is enabled."
|
|
rgroup.long 0xC0++0xF
|
|
line.long 0x0 "GCSR0,Generic Clock Status Register 0"
|
|
bitfld.long 0x0 30. "GPID30,Generic Clock 30 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
bitfld.long 0x0 29. "GPID29,Generic Clock 29 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
newline
|
|
bitfld.long 0x0 26. "GPID26,Generic Clock 26 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
line.long 0x4 "GCSR1,Generic Clock Status Register 1"
|
|
bitfld.long 0x4 31. "GPID63,Generic Clock 63 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
bitfld.long 0x4 30. "GPID62,Generic Clock 62 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
newline
|
|
bitfld.long 0x4 29. "GPID61,Generic Clock 61 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
bitfld.long 0x4 26. "GPID58,Generic Clock 58 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
newline
|
|
bitfld.long 0x4 25. "GPID57,Generic Clock 57 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
bitfld.long 0x4 22. "GPID54,Generic Clock 54 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
newline
|
|
bitfld.long 0x4 21. "GPID53,Generic Clock 53 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
bitfld.long 0x4 20. "GPID52,Generic Clock 52 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
newline
|
|
bitfld.long 0x4 19. "GPID51,Generic Clock 51 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
bitfld.long 0x4 17. "GPID49,Generic Clock 49 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
newline
|
|
bitfld.long 0x4 16. "GPID48,Generic Clock 48 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
bitfld.long 0x4 15. "GPID47,Generic Clock 47 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
newline
|
|
bitfld.long 0x4 14. "GPID46,Generic Clock 46 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
bitfld.long 0x4 13. "GPID45,Generic Clock 45 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
newline
|
|
bitfld.long 0x4 12. "GPID44,Generic Clock 44 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
bitfld.long 0x4 11. "GPID43,Generic Clock 43 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
newline
|
|
bitfld.long 0x4 10. "GPID42,Generic Clock 42 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
bitfld.long 0x4 9. "GPID41,Generic Clock 41 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
newline
|
|
bitfld.long 0x4 8. "GPID40,Generic Clock 40 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
bitfld.long 0x4 7. "GPID39,Generic Clock 39 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
newline
|
|
bitfld.long 0x4 6. "GPID38,Generic Clock 38 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
bitfld.long 0x4 1. "GPID33,Generic Clock 33 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
line.long 0x8 "GCSR2,Generic Clock Status Register 2"
|
|
bitfld.long 0x8 27. "GPID91,Generic Clock 91 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
bitfld.long 0x8 24. "GPID88,Generic Clock 88 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
newline
|
|
bitfld.long 0x8 21. "GPID85,Generic Clock 85 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
bitfld.long 0x8 20. "GPID84,Generic Clock 84 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
newline
|
|
bitfld.long 0x8 18. "GPID82,Generic Clock 82 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
bitfld.long 0x8 17. "GPID81,Generic Clock 81 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
newline
|
|
bitfld.long 0x8 16. "GPID80,Generic Clock 80 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
bitfld.long 0x8 15. "GPID79,Generic Clock 79 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
newline
|
|
bitfld.long 0x8 14. "GPID78,Generic Clock 78 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
bitfld.long 0x8 11. "GPID75,Generic Clock 75 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
newline
|
|
bitfld.long 0x8 10. "GPID74,Generic Clock 74 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
bitfld.long 0x8 9. "GPID73,Generic Clock 73 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
newline
|
|
bitfld.long 0x8 8. "GPID72,Generic Clock 72 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
bitfld.long 0x8 7. "GPID71,Generic Clock 71 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
newline
|
|
bitfld.long 0x8 6. "GPID70,Generic Clock 70 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
bitfld.long 0x8 5. "GPID69,Generic Clock 69 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
newline
|
|
bitfld.long 0x8 4. "GPID68,Generic Clock 68 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
bitfld.long 0x8 2. "GPID66,Generic Clock 66 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
newline
|
|
bitfld.long 0x8 1. "GPID65,Generic Clock 65 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
bitfld.long 0x8 0. "GPID64,Generic Clock 64 Status" "0: The corresponding Generic clock is disabled.,1: The corresponding Generic clock is enabled."
|
|
line.long 0xC "GCSR3,Generic Clock Status Register 3"
|
|
wgroup.long 0xE0++0x7
|
|
line.long 0x0 "PLL_IER,PLL Interrupt Enable Register"
|
|
bitfld.long 0x0 22. "UNLOCK6,PLL of Index 6 Unlock Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 21. "UNLOCK5,PLL of Index 5 Unlock Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "UNLOCK4,PLL of Index 4 Unlock Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 19. "UNLOCK3,PLL of Index 3 Unlock Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "UNLOCK2,PLL of Index 2 Unlock Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 17. "UNLOCK1,PLL of Index 1 Unlock Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "UNLOCK0,PLL of Index 0 Unlock Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 6. "LOCK6,PLL of Index 6 Lock Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LOCK5,PLL of Index 5 Lock Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "LOCK4,PLL of Index 4 Lock Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "LOCK3,PLL of Index 3 Lock Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "LOCK2,PLL of Index 2 Lock Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LOCK1,PLL of Index 1 Lock Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "LOCK0,PLL of Index 0 Lock Interrupt Enable" "0,1"
|
|
line.long 0x4 "PLL_IDR,PLL Interrupt Disable Register"
|
|
bitfld.long 0x4 22. "UNLOCK6,PLL of Index 6 Unlock Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 21. "UNLOCK5,PLL of Index 5 Unlock Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "UNLOCK4,PLL of Index 4 Unlock Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 19. "UNLOCK3,PLL of Index 3 Unlock Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "UNLOCK2,PLL of Index 2 Unlock Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 17. "UNLOCK1,PLL of Index 1 Unlock Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "UNLOCK0,PLL of Index 0 Unlock Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 6. "LOCK6,PLL of Index 6 Lock Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "LOCK5,PLL of Index 5 Lock Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 4. "LOCK4,PLL of Index 4 Lock Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "LOCK3,PLL of Index 3 Lock Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 2. "LOCK2,PLL of Index 2 Lock Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "LOCK1,PLL of Index 1 Lock Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "LOCK0,PLL of Index 0 Lock Interrupt Disable" "0,1"
|
|
rgroup.long 0xE8++0xB
|
|
line.long 0x0 "PLL_IMR,PLL Interrupt Mask Register"
|
|
bitfld.long 0x0 22. "UNLOCK6,PLL of Index 6 Unlock Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 21. "UNLOCK5,PLL of Index 5 Unlock Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "UNLOCK4,PLL of Index 4 Unlock Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 19. "UNLOCK3,PLL of Index 3 Unlock Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "UNLOCK2,PLL of Index 2 Unlock Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 17. "UNLOCK1,PLL of Index 1 Unlock Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "UNLOCK0,PLL of Index 0 Unlock Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 6. "LOCK6,PLL of Index 6 Lock Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LOCK5,PLL of Index 5 Lock Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 4. "LOCK4,PLL of Index 4 Lock Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "LOCK3,PLL of Index 3 Lock Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "LOCK2,PLL of Index 2 Lock Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LOCK1,PLL of Index 1 Lock Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "LOCK0,PLL of Index 0 Lock Interrupt Mask" "0,1"
|
|
line.long 0x4 "PLL_ISR0,PLL Interrupt Status Register 0"
|
|
bitfld.long 0x4 22. "UNLOCK6,PLL of Index 6 Unlock Interrupt Status" "0: PLL is not unlocked.,1: PLLx is unlocked. To know the unlock type the.."
|
|
bitfld.long 0x4 21. "UNLOCK5,PLL of Index 5 Unlock Interrupt Status" "0: PLL is not unlocked.,1: PLLx is unlocked. To know the unlock type the.."
|
|
newline
|
|
bitfld.long 0x4 20. "UNLOCK4,PLL of Index 4 Unlock Interrupt Status" "0: PLL is not unlocked.,1: PLLx is unlocked. To know the unlock type the.."
|
|
bitfld.long 0x4 19. "UNLOCK3,PLL of Index 3 Unlock Interrupt Status" "0: PLL is not unlocked.,1: PLLx is unlocked. To know the unlock type the.."
|
|
newline
|
|
bitfld.long 0x4 18. "UNLOCK2,PLL of Index 2 Unlock Interrupt Status" "0: PLL is not unlocked.,1: PLLx is unlocked. To know the unlock type the.."
|
|
bitfld.long 0x4 17. "UNLOCK1,PLL of Index 1 Unlock Interrupt Status" "0: PLL is not unlocked.,1: PLLx is unlocked. To know the unlock type the.."
|
|
newline
|
|
bitfld.long 0x4 16. "UNLOCK0,PLL of Index 0 Unlock Interrupt Status" "0: PLL is not unlocked.,1: PLLx is unlocked. To know the unlock type the.."
|
|
bitfld.long 0x4 6. "LOCK6,PLL of Index 6 Lock Interrupt Status" "0: PLLx is not locked.,1: PLLx is locked."
|
|
newline
|
|
bitfld.long 0x4 5. "LOCK5,PLL of Index 5 Lock Interrupt Status" "0: PLLx is not locked.,1: PLLx is locked."
|
|
bitfld.long 0x4 4. "LOCK4,PLL of Index 4 Lock Interrupt Status" "0: PLLx is not locked.,1: PLLx is locked."
|
|
newline
|
|
bitfld.long 0x4 3. "LOCK3,PLL of Index 3 Lock Interrupt Status" "0: PLLx is not locked.,1: PLLx is locked."
|
|
bitfld.long 0x4 2. "LOCK2,PLL of Index 2 Lock Interrupt Status" "0: PLLx is not locked.,1: PLLx is locked."
|
|
newline
|
|
bitfld.long 0x4 1. "LOCK1,PLL of Index 1 Lock Interrupt Status" "0: PLLx is not locked.,1: PLLx is locked."
|
|
bitfld.long 0x4 0. "LOCK0,PLL of Index 0 Lock Interrupt Status" "0: PLLx is not locked.,1: PLLx is locked."
|
|
line.long 0x8 "PLL_ISR1,PLL Interrupt Status Register 1"
|
|
bitfld.long 0x8 22. "OVR6,PLLx Overflow" "0: PLL is not in overflow state.,1: PLL encountered an overflow."
|
|
bitfld.long 0x8 21. "OVR5,PLLx Overflow" "0: PLL is not in overflow state.,1: PLL encountered an overflow."
|
|
newline
|
|
bitfld.long 0x8 20. "OVR4,PLLx Overflow" "0: PLL is not in overflow state.,1: PLL encountered an overflow."
|
|
bitfld.long 0x8 19. "OVR3,PLLx Overflow" "0: PLL is not in overflow state.,1: PLL encountered an overflow."
|
|
newline
|
|
bitfld.long 0x8 18. "OVR2,PLLx Overflow" "0: PLL is not in overflow state.,1: PLL encountered an overflow."
|
|
bitfld.long 0x8 17. "OVR1,PLLx Overflow" "0: PLL is not in overflow state.,1: PLL encountered an overflow."
|
|
newline
|
|
bitfld.long 0x8 16. "OVR0,PLLx Overflow" "0: PLL is not in overflow state.,1: PLL encountered an overflow."
|
|
bitfld.long 0x8 6. "UDR6,PLLx Underflow" "0: PLL is not in underflow state.,1: PLL encountered an underflow."
|
|
newline
|
|
bitfld.long 0x8 5. "UDR5,PLLx Underflow" "0: PLL is not in underflow state.,1: PLL encountered an underflow."
|
|
bitfld.long 0x8 4. "UDR4,PLLx Underflow" "0: PLL is not in underflow state.,1: PLL encountered an underflow."
|
|
newline
|
|
bitfld.long 0x8 3. "UDR3,PLLx Underflow" "0: PLL is not in underflow state.,1: PLL encountered an underflow."
|
|
bitfld.long 0x8 2. "UDR2,PLLx Underflow" "0: PLL is not in underflow state.,1: PLL encountered an underflow."
|
|
newline
|
|
bitfld.long 0x8 1. "UDR1,PLLx Underflow" "0: PLL is not in underflow state.,1: PLL encountered an underflow."
|
|
bitfld.long 0x8 0. "UDR0,PLLx Underflow" "0: PLL is not in underflow state.,1: PLL encountered an underflow."
|
|
tree.end
|
|
tree "PWM (Pulse Width Modulation Controller)"
|
|
base ad:0xE1604000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CLK,PWM Clock Register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "PREB,CLKB Source Clock Selection"
|
|
hexmask.long.byte 0x0 16.--23. 1. "DIVB,CLKB Divide Factor"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "PREA,CLKA Source Clock Selection"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DIVA,CLKA Divide Factor"
|
|
wgroup.long 0x4++0x7
|
|
line.long 0x0 "ENA,PWM Enable Register"
|
|
bitfld.long 0x0 3. "CHID3,Channel ID" "0: No effect.,1: Enable PWM output for channel x."
|
|
bitfld.long 0x0 2. "CHID2,Channel ID" "0: No effect.,1: Enable PWM output for channel x."
|
|
newline
|
|
bitfld.long 0x0 1. "CHID1,Channel ID" "0: No effect.,1: Enable PWM output for channel x."
|
|
bitfld.long 0x0 0. "CHID0,Channel ID" "0: No effect.,1: Enable PWM output for channel x."
|
|
line.long 0x4 "DIS,PWM Disable Register"
|
|
bitfld.long 0x4 3. "CHID3,Channel ID" "0: No effect.,1: Disable PWM output for channel x."
|
|
bitfld.long 0x4 2. "CHID2,Channel ID" "0: No effect.,1: Disable PWM output for channel x."
|
|
newline
|
|
bitfld.long 0x4 1. "CHID1,Channel ID" "0: No effect.,1: Disable PWM output for channel x."
|
|
bitfld.long 0x4 0. "CHID0,Channel ID" "0: No effect.,1: Disable PWM output for channel x."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "SR,PWM Status Register"
|
|
bitfld.long 0x0 3. "CHID3,Channel ID" "0: PWM output for channel x is disabled.,1: PWM output for channel x is enabled."
|
|
bitfld.long 0x0 2. "CHID2,Channel ID" "0: PWM output for channel x is disabled.,1: PWM output for channel x is enabled."
|
|
newline
|
|
bitfld.long 0x0 1. "CHID1,Channel ID" "0: PWM output for channel x is disabled.,1: PWM output for channel x is enabled."
|
|
bitfld.long 0x0 0. "CHID0,Channel ID" "0: PWM output for channel x is disabled.,1: PWM output for channel x is enabled."
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER1,PWM Interrupt Enable Register 1"
|
|
bitfld.long 0x0 19. "FCHID3,Fault Protection Trigger on Channel 3 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 18. "FCHID2,Fault Protection Trigger on Channel 2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "FCHID1,Fault Protection Trigger on Channel 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 16. "FCHID0,Fault Protection Trigger on Channel 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CHID3,Counter Event on Channel 3 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "CHID2,Counter Event on Channel 2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CHID1,Counter Event on Channel 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "CHID0,Counter Event on Channel 0 Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR1,PWM Interrupt Disable Register 1"
|
|
bitfld.long 0x4 19. "FCHID3,Fault Protection Trigger on Channel 3 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 18. "FCHID2,Fault Protection Trigger on Channel 2 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "FCHID1,Fault Protection Trigger on Channel 1 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 16. "FCHID0,Fault Protection Trigger on Channel 0 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CHID3,Counter Event on Channel 3 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 2. "CHID2,Counter Event on Channel 2 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CHID1,Counter Event on Channel 1 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "CHID0,Counter Event on Channel 0 Interrupt Disable" "0,1"
|
|
rgroup.long 0x18++0x7
|
|
line.long 0x0 "IMR1,PWM Interrupt Mask Register 1"
|
|
bitfld.long 0x0 19. "FCHID3,Fault Protection Trigger on Channel 3 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 18. "FCHID2,Fault Protection Trigger on Channel 2 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "FCHID1,Fault Protection Trigger on Channel 1 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 16. "FCHID0,Fault Protection Trigger on Channel 0 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CHID3,Counter Event on Channel 3 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "CHID2,Counter Event on Channel 2 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CHID1,Counter Event on Channel 1 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "CHID0,Counter Event on Channel 0 Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR1,PWM Interrupt Status Register 1"
|
|
bitfld.long 0x4 19. "FCHID3,Fault Protection Trigger on Channel 3" "0: No new trigger of the fault protection since the..,1: At least one trigger of the fault protection.."
|
|
bitfld.long 0x4 18. "FCHID2,Fault Protection Trigger on Channel 2" "0: No new trigger of the fault protection since the..,1: At least one trigger of the fault protection.."
|
|
newline
|
|
bitfld.long 0x4 17. "FCHID1,Fault Protection Trigger on Channel 1" "0: No new trigger of the fault protection since the..,1: At least one trigger of the fault protection.."
|
|
bitfld.long 0x4 16. "FCHID0,Fault Protection Trigger on Channel 0" "0: No new trigger of the fault protection since the..,1: At least one trigger of the fault protection.."
|
|
newline
|
|
bitfld.long 0x4 3. "CHID3,Counter Event on Channel 3" "0: No new counter event has occurred since the last..,1: At least one counter event has occurred since.."
|
|
bitfld.long 0x4 2. "CHID2,Counter Event on Channel 2" "0: No new counter event has occurred since the last..,1: At least one counter event has occurred since.."
|
|
newline
|
|
bitfld.long 0x4 1. "CHID1,Counter Event on Channel 1" "0: No new counter event has occurred since the last..,1: At least one counter event has occurred since.."
|
|
bitfld.long 0x4 0. "CHID0,Counter Event on Channel 0" "0: No new counter event has occurred since the last..,1: At least one counter event has occurred since.."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SCM,PWM Sync Channels Mode Register"
|
|
bitfld.long 0x0 21.--23. "PTRCS,DMA Controller Transfer Request Comparison Selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 20. "PTRM,DMA Controller Transfer Request Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "UPDM,Synchronous Channels Update Mode" "0: Manual write of double buffer registers and..,1: Manual write of double buffer registers and..,2: Automatic write of duty-cycle update registers..,?"
|
|
bitfld.long 0x0 3. "SYNC3,Synchronous Channel 3" "0: Channel x is not a synchronous channel.,1: Channel x is a synchronous channel."
|
|
newline
|
|
bitfld.long 0x0 2. "SYNC2,Synchronous Channel 2" "0: Channel x is not a synchronous channel.,1: Channel x is a synchronous channel."
|
|
bitfld.long 0x0 1. "SYNC1,Synchronous Channel 1" "0: Channel x is not a synchronous channel.,1: Channel x is a synchronous channel."
|
|
newline
|
|
bitfld.long 0x0 0. "SYNC0,Synchronous Channel 0" "0: Channel x is not a synchronous channel.,1: Channel x is a synchronous channel."
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x0 "DMAR,PWM DMA Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "DMADUTY,Duty-Cycle Holding Register for DMA Access"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "SCUC,PWM Sync Channels Update Control Register"
|
|
bitfld.long 0x0 0. "UPDULOCK,Synchronous Channels Update Unlock" "0: No effect,1: If the UPDM field is set to '0' in PWM Sync.."
|
|
line.long 0x4 "SCUP,PWM Sync Channels Update Period Register"
|
|
hexmask.long.byte 0x4 4.--7. 1. "UPRCNT,Update Period Counter"
|
|
hexmask.long.byte 0x4 0.--3. 1. "UPR,Update Period"
|
|
wgroup.long 0x30++0xB
|
|
line.long 0x0 "SCUPUPD,PWM Sync Channels Update Period Update Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "UPRUPD,Update Period Update"
|
|
line.long 0x4 "IER2,PWM Interrupt Enable Register 2"
|
|
bitfld.long 0x4 23. "CMPU7,Comparison 7 Update Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 22. "CMPU6,Comparison 6 Update Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "CMPU5,Comparison 5 Update Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 20. "CMPU4,Comparison 4 Update Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CMPU3,Comparison 3 Update Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 18. "CMPU2,Comparison 2 Update Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "CMPU1,Comparison 1 Update Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 16. "CMPU0,Comparison 0 Update Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CMPM7,Comparison 7 Match Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 14. "CMPM6,Comparison 6 Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "CMPM5,Comparison 5 Match Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 12. "CMPM4,Comparison 4 Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CMPM3,Comparison 3 Match Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 10. "CMPM2,Comparison 2 Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CMPM1,Comparison 1 Match Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 8. "CMPM0,Comparison 0 Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "UNRE,Synchronous Channels Update Underrun Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 0. "WRDY,Write Ready for Synchronous Channels Update Interrupt Enable" "0,1"
|
|
line.long 0x8 "IDR2,PWM Interrupt Disable Register 2"
|
|
bitfld.long 0x8 23. "CMPU7,Comparison 7 Update Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 22. "CMPU6,Comparison 6 Update Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "CMPU5,Comparison 5 Update Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 20. "CMPU4,Comparison 4 Update Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "CMPU3,Comparison 3 Update Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 18. "CMPU2,Comparison 2 Update Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "CMPU1,Comparison 1 Update Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 16. "CMPU0,Comparison 0 Update Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "CMPM7,Comparison 7 Match Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 14. "CMPM6,Comparison 6 Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "CMPM5,Comparison 5 Match Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 12. "CMPM4,Comparison 4 Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "CMPM3,Comparison 3 Match Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 10. "CMPM2,Comparison 2 Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "CMPM1,Comparison 1 Match Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 8. "CMPM0,Comparison 0 Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "UNRE,Synchronous Channels Update Underrun Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 0. "WRDY,Write Ready for Synchronous Channels Update Interrupt Disable" "0,1"
|
|
rgroup.long 0x3C++0x7
|
|
line.long 0x0 "IMR2,PWM Interrupt Mask Register 2"
|
|
bitfld.long 0x0 23. "CMPU7,Comparison 7 Update Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 22. "CMPU6,Comparison 6 Update Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "CMPU5,Comparison 5 Update Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 20. "CMPU4,Comparison 4 Update Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CMPU3,Comparison 3 Update Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 18. "CMPU2,Comparison 2 Update Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "CMPU1,Comparison 1 Update Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 16. "CMPU0,Comparison 0 Update Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CMPM7,Comparison 7 Match Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 14. "CMPM6,Comparison 6 Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "CMPM5,Comparison 5 Match Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 12. "CMPM4,Comparison 4 Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMPM3,Comparison 3 Match Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 10. "CMPM2,Comparison 2 Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CMPM1,Comparison 1 Match Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 8. "CMPM0,Comparison 0 Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "UNRE,Synchronous Channels Update Underrun Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "WRDY,Write Ready for Synchronous Channels Update Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR2,PWM Interrupt Status Register 2"
|
|
bitfld.long 0x4 23. "CMPU7,Comparison 7 Update" "0: The comparison x has not been updated since the..,1: The comparison x has been updated at least one.."
|
|
bitfld.long 0x4 22. "CMPU6,Comparison 6 Update" "0: The comparison x has not been updated since the..,1: The comparison x has been updated at least one.."
|
|
newline
|
|
bitfld.long 0x4 21. "CMPU5,Comparison 5 Update" "0: The comparison x has not been updated since the..,1: The comparison x has been updated at least one.."
|
|
bitfld.long 0x4 20. "CMPU4,Comparison 4 Update" "0: The comparison x has not been updated since the..,1: The comparison x has been updated at least one.."
|
|
newline
|
|
bitfld.long 0x4 19. "CMPU3,Comparison 3 Update" "0: The comparison x has not been updated since the..,1: The comparison x has been updated at least one.."
|
|
bitfld.long 0x4 18. "CMPU2,Comparison 2 Update" "0: The comparison x has not been updated since the..,1: The comparison x has been updated at least one.."
|
|
newline
|
|
bitfld.long 0x4 17. "CMPU1,Comparison 1 Update" "0: The comparison x has not been updated since the..,1: The comparison x has been updated at least one.."
|
|
bitfld.long 0x4 16. "CMPU0,Comparison 0 Update" "0: The comparison x has not been updated since the..,1: The comparison x has been updated at least one.."
|
|
newline
|
|
bitfld.long 0x4 15. "CMPM7,Comparison 7 Match" "0: The comparison x has not matched since the last..,1: The comparison x has matched at least one time.."
|
|
bitfld.long 0x4 14. "CMPM6,Comparison 6 Match" "0: The comparison x has not matched since the last..,1: The comparison x has matched at least one time.."
|
|
newline
|
|
bitfld.long 0x4 13. "CMPM5,Comparison 5 Match" "0: The comparison x has not matched since the last..,1: The comparison x has matched at least one time.."
|
|
bitfld.long 0x4 12. "CMPM4,Comparison 4 Match" "0: The comparison x has not matched since the last..,1: The comparison x has matched at least one time.."
|
|
newline
|
|
bitfld.long 0x4 11. "CMPM3,Comparison 3 Match" "0: The comparison x has not matched since the last..,1: The comparison x has matched at least one time.."
|
|
bitfld.long 0x4 10. "CMPM2,Comparison 2 Match" "0: The comparison x has not matched since the last..,1: The comparison x has matched at least one time.."
|
|
newline
|
|
bitfld.long 0x4 9. "CMPM1,Comparison 1 Match" "0: The comparison x has not matched since the last..,1: The comparison x has matched at least one time.."
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|
bitfld.long 0x4 8. "CMPM0,Comparison 0 Match" "0: The comparison x has not matched since the last..,1: The comparison x has matched at least one time.."
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|
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bitfld.long 0x4 3. "UNRE,Synchronous Channels Update Underrun Error" "0: No Synchronous Channels Update Underrun has..,1: At least one Synchronous Channels Update.."
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|
bitfld.long 0x4 0. "WRDY,Write Ready for Synchronous Channels Update" "0: New duty-cycle and dead-time values for the..,1: New duty-cycle and dead-time values for the.."
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group.long 0x44++0x7
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line.long 0x0 "OOV,PWM Output Override Value Register"
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bitfld.long 0x0 19. "OOVL3,Output Override Value for PWML output of the channel 3" "0: Override value is 0 for PWML output of channel x.,1: Override value is 1 for PWML output of channel x."
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bitfld.long 0x0 18. "OOVL2,Output Override Value for PWML output of the channel 2" "0: Override value is 0 for PWML output of channel x.,1: Override value is 1 for PWML output of channel x."
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bitfld.long 0x0 17. "OOVL1,Output Override Value for PWML output of the channel 1" "0: Override value is 0 for PWML output of channel x.,1: Override value is 1 for PWML output of channel x."
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bitfld.long 0x0 16. "OOVL0,Output Override Value for PWML output of the channel 0" "0: Override value is 0 for PWML output of channel x.,1: Override value is 1 for PWML output of channel x."
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bitfld.long 0x0 3. "OOVH3,Output Override Value for PWMH output of the channel 3" "0: Override value is 0 for PWMH output of channel x.,1: Override value is 1 for PWMH output of channel x."
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bitfld.long 0x0 2. "OOVH2,Output Override Value for PWMH output of the channel 2" "0: Override value is 0 for PWMH output of channel x.,1: Override value is 1 for PWMH output of channel x."
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bitfld.long 0x0 1. "OOVH1,Output Override Value for PWMH output of the channel 1" "0: Override value is 0 for PWMH output of channel x.,1: Override value is 1 for PWMH output of channel x."
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bitfld.long 0x0 0. "OOVH0,Output Override Value for PWMH output of the channel 0" "0: Override value is 0 for PWMH output of channel x.,1: Override value is 1 for PWMH output of channel x."
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line.long 0x4 "OS,PWM Output Selection Register"
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bitfld.long 0x4 19. "OSL3,Output Selection for PWML output of the channel 3" "0: Dead-time generator output DTOLx selected as..,1: Output override value OOVLx selected as PWML.."
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bitfld.long 0x4 18. "OSL2,Output Selection for PWML output of the channel 2" "0: Dead-time generator output DTOLx selected as..,1: Output override value OOVLx selected as PWML.."
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bitfld.long 0x4 17. "OSL1,Output Selection for PWML output of the channel 1" "0: Dead-time generator output DTOLx selected as..,1: Output override value OOVLx selected as PWML.."
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bitfld.long 0x4 16. "OSL0,Output Selection for PWML output of the channel 0" "0: Dead-time generator output DTOLx selected as..,1: Output override value OOVLx selected as PWML.."
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bitfld.long 0x4 3. "OSH3,Output Selection for PWMH output of the channel 3" "0: Dead-time generator output DTOHx selected as..,1: Output override value OOVHx selected as PWMH.."
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bitfld.long 0x4 2. "OSH2,Output Selection for PWMH output of the channel 2" "0: Dead-time generator output DTOHx selected as..,1: Output override value OOVHx selected as PWMH.."
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newline
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bitfld.long 0x4 1. "OSH1,Output Selection for PWMH output of the channel 1" "0: Dead-time generator output DTOHx selected as..,1: Output override value OOVHx selected as PWMH.."
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bitfld.long 0x4 0. "OSH0,Output Selection for PWMH output of the channel 0" "0: Dead-time generator output DTOHx selected as..,1: Output override value OOVHx selected as PWMH.."
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wgroup.long 0x4C++0xF
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line.long 0x0 "OSS,PWM Output Selection Set Register"
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bitfld.long 0x0 19. "OSSL3,Output Selection Set for PWML output of the channel 3" "0: No effect.,1: Output override value OOVLx selected as PWML.."
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bitfld.long 0x0 18. "OSSL2,Output Selection Set for PWML output of the channel 2" "0: No effect.,1: Output override value OOVLx selected as PWML.."
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bitfld.long 0x0 17. "OSSL1,Output Selection Set for PWML output of the channel 1" "0: No effect.,1: Output override value OOVLx selected as PWML.."
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bitfld.long 0x0 16. "OSSL0,Output Selection Set for PWML output of the channel 0" "0: No effect.,1: Output override value OOVLx selected as PWML.."
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bitfld.long 0x0 3. "OSSH3,Output Selection Set for PWMH output of the channel 3" "0: No effect.,1: Output override value OOVHx selected as PWMH.."
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bitfld.long 0x0 2. "OSSH2,Output Selection Set for PWMH output of the channel 2" "0: No effect.,1: Output override value OOVHx selected as PWMH.."
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newline
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bitfld.long 0x0 1. "OSSH1,Output Selection Set for PWMH output of the channel 1" "0: No effect.,1: Output override value OOVHx selected as PWMH.."
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bitfld.long 0x0 0. "OSSH0,Output Selection Set for PWMH output of the channel 0" "0: No effect.,1: Output override value OOVHx selected as PWMH.."
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line.long 0x4 "OSC,PWM Output Selection Clear Register"
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bitfld.long 0x4 19. "OSCL3,Output Selection Clear for PWML output of the channel 3" "0: No effect.,1: Dead-time generator output DTOLx selected as.."
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bitfld.long 0x4 18. "OSCL2,Output Selection Clear for PWML output of the channel 2" "0: No effect.,1: Dead-time generator output DTOLx selected as.."
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bitfld.long 0x4 17. "OSCL1,Output Selection Clear for PWML output of the channel 1" "0: No effect.,1: Dead-time generator output DTOLx selected as.."
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bitfld.long 0x4 16. "OSCL0,Output Selection Clear for PWML output of the channel 0" "0: No effect.,1: Dead-time generator output DTOLx selected as.."
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bitfld.long 0x4 3. "OSCH3,Output Selection Clear for PWMH output of the channel 3" "0: No effect.,1: Dead-time generator output DTOHx selected as.."
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bitfld.long 0x4 2. "OSCH2,Output Selection Clear for PWMH output of the channel 2" "0: No effect.,1: Dead-time generator output DTOHx selected as.."
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newline
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bitfld.long 0x4 1. "OSCH1,Output Selection Clear for PWMH output of the channel 1" "0: No effect.,1: Dead-time generator output DTOHx selected as.."
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bitfld.long 0x4 0. "OSCH0,Output Selection Clear for PWMH output of the channel 0" "0: No effect.,1: Dead-time generator output DTOHx selected as.."
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line.long 0x8 "OSSUPD,PWM Output Selection Set Update Register"
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bitfld.long 0x8 19. "OSSUPL3,Output Selection Set for PWML output of the channel 3" "0: No effect.,1: Output override value OOVLx selected as PWML.."
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bitfld.long 0x8 18. "OSSUPL2,Output Selection Set for PWML output of the channel 2" "0: No effect.,1: Output override value OOVLx selected as PWML.."
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newline
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bitfld.long 0x8 17. "OSSUPL1,Output Selection Set for PWML output of the channel 1" "0: No effect.,1: Output override value OOVLx selected as PWML.."
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bitfld.long 0x8 16. "OSSUPL0,Output Selection Set for PWML output of the channel 0" "0: No effect.,1: Output override value OOVLx selected as PWML.."
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newline
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bitfld.long 0x8 3. "OSSUPH3,Output Selection Set for PWMH output of the channel 3" "0: No effect.,1: Output override value OOVHx selected as PWMH.."
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bitfld.long 0x8 2. "OSSUPH2,Output Selection Set for PWMH output of the channel 2" "0: No effect.,1: Output override value OOVHx selected as PWMH.."
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newline
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bitfld.long 0x8 1. "OSSUPH1,Output Selection Set for PWMH output of the channel 1" "0: No effect.,1: Output override value OOVHx selected as PWMH.."
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bitfld.long 0x8 0. "OSSUPH0,Output Selection Set for PWMH output of the channel 0" "0: No effect.,1: Output override value OOVHx selected as PWMH.."
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line.long 0xC "OSCUPD,PWM Output Selection Clear Update Register"
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bitfld.long 0xC 19. "OSCUPL3,Output Selection Clear for PWML output of the channel 3" "0: No effect.,1: Dead-time generator output DTOLx selected as.."
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bitfld.long 0xC 18. "OSCUPL2,Output Selection Clear for PWML output of the channel 2" "0: No effect.,1: Dead-time generator output DTOLx selected as.."
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bitfld.long 0xC 17. "OSCUPL1,Output Selection Clear for PWML output of the channel 1" "0: No effect.,1: Dead-time generator output DTOLx selected as.."
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bitfld.long 0xC 16. "OSCUPL0,Output Selection Clear for PWML output of the channel 0" "0: No effect.,1: Dead-time generator output DTOLx selected as.."
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newline
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bitfld.long 0xC 3. "OSCUPH3,Output Selection Clear for PWMH output of the channel 3" "0: No effect.,1: Dead-time generator output DTOHx selected as.."
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bitfld.long 0xC 2. "OSCUPH2,Output Selection Clear for PWMH output of the channel 2" "0: No effect.,1: Dead-time generator output DTOHx selected as.."
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newline
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bitfld.long 0xC 1. "OSCUPH1,Output Selection Clear for PWMH output of the channel 1" "0: No effect.,1: Dead-time generator output DTOHx selected as.."
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bitfld.long 0xC 0. "OSCUPH0,Output Selection Clear for PWMH output of the channel 0" "0: No effect.,1: Dead-time generator output DTOHx selected as.."
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group.long 0x5C++0x3
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line.long 0x0 "FMR,PWM Fault Mode Register"
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hexmask.long.byte 0x0 16.--23. 1. "FFIL,Fault Filtering"
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hexmask.long.byte 0x0 8.--15. 1. "FMOD,Fault Activation Mode"
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hexmask.long.byte 0x0 0.--7. 1. "FPOL,Fault Polarity"
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rgroup.long 0x60++0x3
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line.long 0x0 "FSR,PWM Fault Status Register"
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hexmask.long.byte 0x0 8.--15. 1. "FS,Fault Status"
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hexmask.long.byte 0x0 0.--7. 1. "FIV,Fault Input Value"
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wgroup.long 0x64++0x3
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line.long 0x0 "FCR,PWM Fault Clear Register"
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hexmask.long.byte 0x0 0.--7. 1. "FCLR,Fault Clear"
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group.long 0x68++0x7
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line.long 0x0 "FPV1,PWM Fault Protection Value Register 1"
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bitfld.long 0x0 19. "FPVL3,Fault Protection Value for PWML output on channel 3" "0: PWML output of channel x is forced to '0' when..,1: PWML output of channel x is forced to '1' when.."
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bitfld.long 0x0 18. "FPVL2,Fault Protection Value for PWML output on channel 2" "0: PWML output of channel x is forced to '0' when..,1: PWML output of channel x is forced to '1' when.."
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newline
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bitfld.long 0x0 17. "FPVL1,Fault Protection Value for PWML output on channel 1" "0: PWML output of channel x is forced to '0' when..,1: PWML output of channel x is forced to '1' when.."
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bitfld.long 0x0 16. "FPVL0,Fault Protection Value for PWML output on channel 0" "0: PWML output of channel x is forced to '0' when..,1: PWML output of channel x is forced to '1' when.."
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newline
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bitfld.long 0x0 3. "FPVH3,Fault Protection Value for PWMH output on channel 3" "0: PWMH output of channel x is forced to '0' when..,1: PWMH output of channel x is forced to '1' when.."
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bitfld.long 0x0 2. "FPVH2,Fault Protection Value for PWMH output on channel 2" "0: PWMH output of channel x is forced to '0' when..,1: PWMH output of channel x is forced to '1' when.."
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newline
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bitfld.long 0x0 1. "FPVH1,Fault Protection Value for PWMH output on channel 1" "0: PWMH output of channel x is forced to '0' when..,1: PWMH output of channel x is forced to '1' when.."
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bitfld.long 0x0 0. "FPVH0,Fault Protection Value for PWMH output on channel 0" "0: PWMH output of channel x is forced to '0' when..,1: PWMH output of channel x is forced to '1' when.."
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line.long 0x4 "FPE,PWM Fault Protection Enable Register"
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hexmask.long.byte 0x4 24.--31. 1. "FPE3,Fault Protection Enable for channel 3"
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hexmask.long.byte 0x4 16.--23. 1. "FPE2,Fault Protection Enable for channel 2"
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newline
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hexmask.long.byte 0x4 8.--15. 1. "FPE1,Fault Protection Enable for channel 1"
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hexmask.long.byte 0x4 0.--7. 1. "FPE0,Fault Protection Enable for channel 0"
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repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
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group.long ($2+0x7C)++0x3
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line.long 0x0 "ELMR[$1],PWM Event Line x Mode Register"
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bitfld.long 0x0 7. "CSEL7,Comparison y Selection" "0: A pulse is not generated on the event line x..,1: A pulse is generated on the event line x when.."
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bitfld.long 0x0 6. "CSEL6,Comparison y Selection" "0: A pulse is not generated on the event line x..,1: A pulse is generated on the event line x when.."
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newline
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bitfld.long 0x0 5. "CSEL5,Comparison y Selection" "0: A pulse is not generated on the event line x..,1: A pulse is generated on the event line x when.."
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bitfld.long 0x0 4. "CSEL4,Comparison y Selection" "0: A pulse is not generated on the event line x..,1: A pulse is generated on the event line x when.."
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newline
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bitfld.long 0x0 3. "CSEL3,Comparison y Selection" "0: A pulse is not generated on the event line x..,1: A pulse is generated on the event line x when.."
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bitfld.long 0x0 2. "CSEL2,Comparison y Selection" "0: A pulse is not generated on the event line x..,1: A pulse is generated on the event line x when.."
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newline
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bitfld.long 0x0 1. "CSEL1,Comparison y Selection" "0: A pulse is not generated on the event line x..,1: A pulse is generated on the event line x when.."
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bitfld.long 0x0 0. "CSEL0,Comparison y Selection" "0: A pulse is not generated on the event line x..,1: A pulse is generated on the event line x when.."
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repeat.end
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group.long 0xA0++0x3
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line.long 0x0 "SSPR,PWM Spread Spectrum Register"
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bitfld.long 0x0 24. "SPRDM,Spread Spectrum Counter Mode" "0: Triangular mode. The spread spectrum counter..,1: Random mode. The spread spectrum counter is.."
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hexmask.long.tbyte 0x0 0.--23. 1. "SPRD,Spread Spectrum Limit Value"
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wgroup.long 0xA4++0x3
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line.long 0x0 "SSPUP,PWM Spread Spectrum Update Register"
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hexmask.long.tbyte 0x0 0.--23. 1. "SPRDUP,Spread Spectrum Limit Value Update"
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group.long 0xB0++0x3
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line.long 0x0 "SMMR,PWM Stepper Motor Mode Register"
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bitfld.long 0x0 17. "DOWN1,Down Count" "0: Up counter.,1: Down counter."
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bitfld.long 0x0 16. "DOWN0,Down Count" "0: Up counter.,1: Down counter."
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newline
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bitfld.long 0x0 1. "GCEN1,Gray Count Enable" "0: Disable Gray count generation on PWML[2*x]..,1: Enable Gray count generation on PWML[2*x].."
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bitfld.long 0x0 0. "GCEN0,Gray Count Enable" "0: Disable Gray count generation on PWML[2*x]..,1: Enable Gray count generation on PWML[2*x].."
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group.long 0xC0++0x3
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line.long 0x0 "FPV2,PWM Fault Protection Value 2 Register"
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bitfld.long 0x0 19. "FPZL3,Fault Protection to Hi-Z for PWML output on channel 3" "0: When fault occurs PWML output of channel x is..,1: When fault occurs PWML output of channel x is.."
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bitfld.long 0x0 18. "FPZL2,Fault Protection to Hi-Z for PWML output on channel 2" "0: When fault occurs PWML output of channel x is..,1: When fault occurs PWML output of channel x is.."
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newline
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bitfld.long 0x0 17. "FPZL1,Fault Protection to Hi-Z for PWML output on channel 1" "0: When fault occurs PWML output of channel x is..,1: When fault occurs PWML output of channel x is.."
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bitfld.long 0x0 16. "FPZL0,Fault Protection to Hi-Z for PWML output on channel 0" "0: When fault occurs PWML output of channel x is..,1: When fault occurs PWML output of channel x is.."
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newline
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bitfld.long 0x0 3. "FPZH3,Fault Protection to Hi-Z for PWMH output on channel 3" "0: When fault occurs PWMH output of channel x is..,1: When fault occurs PWMH output of channel x is.."
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bitfld.long 0x0 2. "FPZH2,Fault Protection to Hi-Z for PWMH output on channel 2" "0: When fault occurs PWMH output of channel x is..,1: When fault occurs PWMH output of channel x is.."
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newline
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bitfld.long 0x0 1. "FPZH1,Fault Protection to Hi-Z for PWMH output on channel 1" "0: When fault occurs PWMH output of channel x is..,1: When fault occurs PWMH output of channel x is.."
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bitfld.long 0x0 0. "FPZH0,Fault Protection to Hi-Z for PWMH output on channel 0" "0: When fault occurs PWMH output of channel x is..,1: When fault occurs PWMH output of channel x is.."
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wgroup.long 0xE4++0x3
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line.long 0x0 "WPCR,PWM Write Protection Control Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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bitfld.long 0x0 7. "WPRG5,Write Protection Register Group 5" "0: The WPCMD command has no effect on the register..,1: The WPCMD command is applied to the register.."
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newline
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bitfld.long 0x0 6. "WPRG4,Write Protection Register Group 4" "0: The WPCMD command has no effect on the register..,1: The WPCMD command is applied to the register.."
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bitfld.long 0x0 5. "WPRG3,Write Protection Register Group 3" "0: The WPCMD command has no effect on the register..,1: The WPCMD command is applied to the register.."
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newline
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bitfld.long 0x0 4. "WPRG2,Write Protection Register Group 2" "0: The WPCMD command has no effect on the register..,1: The WPCMD command is applied to the register.."
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bitfld.long 0x0 3. "WPRG1,Write Protection Register Group 1" "0: The WPCMD command has no effect on the register..,1: The WPCMD command is applied to the register.."
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newline
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bitfld.long 0x0 2. "WPRG0,Write Protection Register Group 0" "0: The WPCMD command has no effect on the register..,1: The WPCMD command is applied to the register.."
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bitfld.long 0x0 0.--1. "WPCMD,Write Protection Command" "0: Disables the software write protection of the..,1: Enables the software write protection of the..,2: Enables the hardware write protection of the..,?"
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rgroup.long 0xE8++0x3
|
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line.long 0x0 "WPSR,PWM Write Protection Status Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "WPVSRC,Write Protect Violation Source"
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bitfld.long 0x0 13. "WPHWS5,Write Protect HW Status" "0: The HW write protection x of the register group..,1: The HW write protection x of the register group.."
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newline
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bitfld.long 0x0 12. "WPHWS4,Write Protect HW Status" "0: The HW write protection x of the register group..,1: The HW write protection x of the register group.."
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bitfld.long 0x0 11. "WPHWS3,Write Protect HW Status" "0: The HW write protection x of the register group..,1: The HW write protection x of the register group.."
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newline
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bitfld.long 0x0 10. "WPHWS2,Write Protect HW Status" "0: The HW write protection x of the register group..,1: The HW write protection x of the register group.."
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bitfld.long 0x0 9. "WPHWS1,Write Protect HW Status" "0: The HW write protection x of the register group..,1: The HW write protection x of the register group.."
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newline
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bitfld.long 0x0 8. "WPHWS0,Write Protect HW Status" "0: The HW write protection x of the register group..,1: The HW write protection x of the register group.."
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|
bitfld.long 0x0 7. "WPVS,Write Protect Violation Status" "0: No write protection violation has occurred since..,1: At least one write protection violation has.."
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newline
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bitfld.long 0x0 5. "WPSWS5,Write Protect SW Status" "0: The SW write protection x of the register group..,1: The SW write protection x of the register group.."
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|
bitfld.long 0x0 4. "WPSWS4,Write Protect SW Status" "0: The SW write protection x of the register group..,1: The SW write protection x of the register group.."
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newline
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bitfld.long 0x0 3. "WPSWS3,Write Protect SW Status" "0: The SW write protection x of the register group..,1: The SW write protection x of the register group.."
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|
bitfld.long 0x0 2. "WPSWS2,Write Protect SW Status" "0: The SW write protection x of the register group..,1: The SW write protection x of the register group.."
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newline
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bitfld.long 0x0 1. "WPSWS1,Write Protect SW Status" "0: The SW write protection x of the register group..,1: The SW write protection x of the register group.."
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bitfld.long 0x0 0. "WPSWS0,Write Protect SW Status" "0: The SW write protection x of the register group..,1: The SW write protection x of the register group.."
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repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0xE1604130 ad:0xE1604140 ad:0xE1604150 ad:0xE1604160 ad:0xE1604170 ad:0xE1604180 ad:0xE1604190 ad:0xE16041A0)
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|
tree "PWM_CMP[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CMPV,PWM Comparison x Value Register"
|
|
bitfld.long 0x0 24. "CVM,Comparison Value Mode" "0: The comparison x between the counter of the..,1: The comparison x between the counter of the.."
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CV,Comparison Value"
|
|
wgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CMPVUPD,PWM Comparison x Value Update Register"
|
|
bitfld.long 0x0 24. "CVMUPD,Comparison Value Mode Update" "0: The comparison x between the counter of the..,1: The comparison x between the counter of the.."
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CVUPD,Comparison Value Update"
|
|
group.long ($2+0x8)++0x3
|
|
line.long 0x0 "CMPM,PWM Comparison x Mode Register"
|
|
hexmask.long.byte 0x0 20.--23. 1. "CUPRCNT,Comparison Update Period Counter"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CUPR,Comparison Update Period"
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newline
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hexmask.long.byte 0x0 12.--15. 1. "CPRCNT,Comparison Period Counter"
|
|
hexmask.long.byte 0x0 8.--11. 1. "CPR,Comparison Period"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "CTR,Comparison Trigger"
|
|
bitfld.long 0x0 0. "CEN,Comparison Enable" "0: The comparison x is disabled and can not match.,1: The comparison x is enabled and can match."
|
|
wgroup.long ($2+0xC)++0x3
|
|
line.long 0x0 "CMPMUPD,PWM Comparison x Mode Update Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CUPRUPD,Comparison Update Period Update"
|
|
hexmask.long.byte 0x0 8.--11. 1. "CPRUPD,Comparison Period Update"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "CTRUPD,Comparison Trigger Update"
|
|
bitfld.long 0x0 0. "CENUPD,Comparison Enable Update" "0: The comparison x is disabled and can not match.,1: The comparison x is enabled and can match."
|
|
tree.end
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0xE1604200 ad:0xE1604220 ad:0xE1604240 ad:0xE1604260)
|
|
tree "PWM_CH_NUM[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "CMR,PWM Channel Mode Register"
|
|
bitfld.long 0x0 19. "PPM,Push-Pull Mode" "0: The Push-Pull mode is disabled for channel x.,1: The Push-Pull mode is enabled for channel x."
|
|
bitfld.long 0x0 18. "DTLI,Dead-Time PWMLx Output Inverted" "0: The dead-time PWMLx output is not inverted.,1: The dead-time PWMLx output is inverted."
|
|
newline
|
|
bitfld.long 0x0 17. "DTHI,Dead-Time PWMHx Output Inverted" "0: The dead-time PWMHx output is not inverted.,1: The dead-time PWMHx output is inverted."
|
|
bitfld.long 0x0 16. "DTE,Dead-Time Generator Enable" "0: The dead-time generator is disabled.,1: The dead-time generator is enabled."
|
|
newline
|
|
bitfld.long 0x0 13. "TCTS,Timer Counter Trigger Selection" "0: The comparator of the channel x (OCx) is used as..,1: The counter events of the channel x is used as.."
|
|
bitfld.long 0x0 12. "DPOLI,Disabled Polarity Inverted" "0: When the PWM channel x is disabled..,1: When the PWM channel x is disabled.."
|
|
newline
|
|
bitfld.long 0x0 11. "UPDS,Update Selection" "0: The update occurs at the next end of the PWM..,1: The update occurs at the next end of the PWM.."
|
|
bitfld.long 0x0 10. "CES,Counter Event Selection" "0: The channel counter event occurs at the end of..,1: The channel counter event occurs at the end of.."
|
|
newline
|
|
bitfld.long 0x0 9. "CPOL,Channel Polarity" "0: The OCx output waveform (output from the..,1: The OCx output waveform (output from the.."
|
|
bitfld.long 0x0 8. "CALG,Channel Alignment" "0: The period is left-aligned.,1: The period is center-aligned."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "CPRE,Channel Prescaler"
|
|
line.long 0x4 "CDTY,PWM Channel Duty Cycle Register"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "CDTY,Channel Duty-Cycle"
|
|
wgroup.long ($2+0x8)++0x3
|
|
line.long 0x0 "CDTYUPD,PWM Channel Duty Cycle Update Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CDTYUPD,Channel Duty-Cycle Update"
|
|
group.long ($2+0xC)++0x3
|
|
line.long 0x0 "CPRD,PWM Channel Period Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CPRD,Channel Period"
|
|
wgroup.long ($2+0x10)++0x3
|
|
line.long 0x0 "CPRDUPD,PWM Channel Period Update Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CPRDUPD,Channel Period Update"
|
|
rgroup.long ($2+0x14)++0x3
|
|
line.long 0x0 "CCNT,PWM Channel Counter Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CNT,Channel Counter Register"
|
|
group.long ($2+0x18)++0x3
|
|
line.long 0x0 "DT,PWM Channel Dead Time Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "DTL,Dead-Time Value for PWMLx Output"
|
|
hexmask.long.word 0x0 0.--15. 1. "DTH,Dead-Time Value for PWMHx Output"
|
|
wgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "DTUPD,PWM Channel Dead Time Update Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "DTLUPD,Dead-Time Value Update for PWMLx Output"
|
|
hexmask.long.word 0x0 0.--15. 1. "DTHUPD,Dead-Time Value Update for PWMHx Output"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0xE1604000
|
|
wgroup.long 0x400++0x3
|
|
line.long 0x0 "CMUPD0,PWM Channel Mode Update Register (ch_num = 0)"
|
|
bitfld.long 0x0 13. "CPOLINVUP,Channel Polarity Inversion Update" "0: No effect.,1: The OCx output waveform (output from the.."
|
|
bitfld.long 0x0 9. "CPOLUP,Channel Polarity Update" "0: The OCx output waveform (output from the..,1: The OCx output waveform (output from the.."
|
|
wgroup.long 0x420++0x3
|
|
line.long 0x0 "CMUPD1,PWM Channel Mode Update Register (ch_num = 1)"
|
|
bitfld.long 0x0 13. "CPOLINVUP,Channel Polarity Inversion Update" "0: No effect.,1: The OCx output waveform (output from the.."
|
|
bitfld.long 0x0 9. "CPOLUP,Channel Polarity Update" "0: The OCx output waveform (output from the..,1: The OCx output waveform (output from the.."
|
|
group.long 0x42C++0x7
|
|
line.long 0x0 "ETRG1,PWM External Trigger Register 1"
|
|
bitfld.long 0x0 31. "RFEN,Recoverable Fault Enable" "0: The TRGINx signal does not generate a..,1: The TRGINx signal generate a recoverable fault.."
|
|
bitfld.long 0x0 30. "TRGSRC,Trigger Source" "0: The TRGINx signal is driven by the PWMEXTRGx..,1: The TRGINx signal is driven by the Analog.."
|
|
newline
|
|
bitfld.long 0x0 29. "TRGFILT,Filtered input" "0: The external trigger input x is not filtered.,1: The external trigger input x is filtered."
|
|
bitfld.long 0x0 28. "TRGEDGE,Edge Selection" "0: TRGMODE = 1: TRGINx event detection on falling..,1: TRGMODE = 1: TRGINx event detection on rising.."
|
|
newline
|
|
bitfld.long 0x0 24.--25. "TRGMODE,External Trigger Mode" "0: External trigger is not enabled.,1: External PWM Reset Mode,2: External PWM Start Mode,3: Cycle-by-cycle Duty Mode"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "MAXCNT,Maximum Counter value"
|
|
line.long 0x4 "LEBR1,PWM Leading-Edge Blanking Register 1"
|
|
bitfld.long 0x4 19. "PWMHREN,PWMH Rising Edge Enable" "0: Leading-edge blanking is disabled on PWMHx..,1: Leading-edge blanking is enabled on PWMHx output.."
|
|
bitfld.long 0x4 18. "PWMHFEN,PWMH Falling Edge Enable" "0: Leading-edge blanking is disabled on PWMHx..,1: Leading-edge blanking is enabled on PWMHx output.."
|
|
newline
|
|
bitfld.long 0x4 17. "PWMLREN,PWML Rising Edge Enable" "0: Leading-edge blanking is disabled on PWMLx..,1: Leading-edge blanking is enabled on PWMLx output.."
|
|
bitfld.long 0x4 16. "PWMLFEN,PWML Falling Edge Enable" "0: Leading-edge blanking is disabled on PWMLx..,1: Leading-edge blanking is enabled on PWMLx output.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "LEBDELAY,Leading-Edge Blanking Delay for TRGINx"
|
|
wgroup.long 0x440++0x3
|
|
line.long 0x0 "CMUPD2,PWM Channel Mode Update Register (ch_num = 2)"
|
|
bitfld.long 0x0 13. "CPOLINVUP,Channel Polarity Inversion Update" "0: No effect.,1: The OCx output waveform (output from the.."
|
|
bitfld.long 0x0 9. "CPOLUP,Channel Polarity Update" "0: The OCx output waveform (output from the..,1: The OCx output waveform (output from the.."
|
|
group.long 0x44C++0x7
|
|
line.long 0x0 "ETRG2,PWM External Trigger Register 2"
|
|
bitfld.long 0x0 31. "RFEN,Recoverable Fault Enable" "0: The TRGINx signal does not generate a..,1: The TRGINx signal generate a recoverable fault.."
|
|
bitfld.long 0x0 30. "TRGSRC,Trigger Source" "0: The TRGINx signal is driven by the PWMEXTRGx..,1: The TRGINx signal is driven by the Analog.."
|
|
newline
|
|
bitfld.long 0x0 29. "TRGFILT,Filtered input" "0: The external trigger input x is not filtered.,1: The external trigger input x is filtered."
|
|
bitfld.long 0x0 28. "TRGEDGE,Edge Selection" "0: TRGMODE = 1: TRGINx event detection on falling..,1: TRGMODE = 1: TRGINx event detection on rising.."
|
|
newline
|
|
bitfld.long 0x0 24.--25. "TRGMODE,External Trigger Mode" "0: External trigger is not enabled.,1: External PWM Reset Mode,2: External PWM Start Mode,3: Cycle-by-cycle Duty Mode"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "MAXCNT,Maximum Counter value"
|
|
line.long 0x4 "LEBR2,PWM Leading-Edge Blanking Register 2"
|
|
bitfld.long 0x4 19. "PWMHREN,PWMH Rising Edge Enable" "0: Leading-edge blanking is disabled on PWMHx..,1: Leading-edge blanking is enabled on PWMHx output.."
|
|
bitfld.long 0x4 18. "PWMHFEN,PWMH Falling Edge Enable" "0: Leading-edge blanking is disabled on PWMHx..,1: Leading-edge blanking is enabled on PWMHx output.."
|
|
newline
|
|
bitfld.long 0x4 17. "PWMLREN,PWML Rising Edge Enable" "0: Leading-edge blanking is disabled on PWMLx..,1: Leading-edge blanking is enabled on PWMLx output.."
|
|
bitfld.long 0x4 16. "PWMLFEN,PWML Falling Edge Enable" "0: Leading-edge blanking is disabled on PWMLx..,1: Leading-edge blanking is enabled on PWMLx output.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "LEBDELAY,Leading-Edge Blanking Delay for TRGINx"
|
|
wgroup.long 0x460++0x3
|
|
line.long 0x0 "CMUPD3,PWM Channel Mode Update Register (ch_num = 3)"
|
|
bitfld.long 0x0 13. "CPOLINVUP,Channel Polarity Inversion Update" "0: No effect.,1: The OCx output waveform (output from the.."
|
|
bitfld.long 0x0 9. "CPOLUP,Channel Polarity Update" "0: The OCx output waveform (output from the..,1: The OCx output waveform (output from the.."
|
|
tree.end
|
|
tree "QSPI (Quad Serial Peripheral Interface)"
|
|
base ad:0x0
|
|
tree "QSPI0"
|
|
base ad:0xE080C000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0: No effect.,1: The chip select is deasserted after the end of.."
|
|
bitfld.long 0x0 10. "RTOUT,Reset Time-out" "0: No effect.,1: Request a TOUT flag reset."
|
|
newline
|
|
bitfld.long 0x0 9. "STTFR,Start Transfer" "0: No effect.,1: Starts the transfer when TFRTYP = 0 and SMRM = 1.."
|
|
bitfld.long 0x0 8. "UPDCFG,Update Configuration" "0: No effect.,1: Requests an update of the QSPI Controller core.."
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,QSPI Software Reset" "0: No effect.,1: Resets the QSPI. A software-triggered hardware.."
|
|
bitfld.long 0x0 5. "SRFRSH,Start REFRESH" "0: No effect.,1: Starts a refresh sequence. QSPI_ISR.RFRSHD.."
|
|
newline
|
|
bitfld.long 0x0 4. "STPCAL,Start Pad Calibration" "0: No effect.,1: Starts a QSPI pad calibration. QSPI_SR.CALBSY.."
|
|
bitfld.long 0x0 3. "DLLOFF,DLL Off Request" "0: No effect.,1: Disables the DLL. When the DLL is not locked.."
|
|
newline
|
|
bitfld.long 0x0 2. "DLLON,DLL On Request" "0: No effect.,1: Enables the DLL. When the DLL is locked (DLOCK.."
|
|
bitfld.long 0x0 1. "QSPIDIS,QSPI Disable" "0: No effect.,1: Disables the QSPI."
|
|
newline
|
|
bitfld.long 0x0 0. "QSPIEN,QSPI Enable" "0: No effect.,1: Enables the QSPI to transfer and receive data."
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYCS,Minimum Inactive QCS Delay"
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBCT,Delay Between Consecutive Transfers"
|
|
newline
|
|
bitfld.long 0x0 15. "OENSD,Output Enable Shift Disabled" "0: By default the pad output enable signal is held..,1: The pad output enable signal is not held for one.."
|
|
bitfld.long 0x0 13. "QICMEN,QSPI Inter-chip Mode Enable" "0: QSPI_WICR.WROPT and QSPI_RICR.RDOPT define the..,1: No dummy cycles are inserted for write accesses.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "NBBITS,Number Of Bits Per Transfer"
|
|
bitfld.long 0x0 7. "TAMPCLR,Tamper Clear Enable" "0: A tamper detection event has no effect on QSPI..,1: A tamper detection event immediately clears QSPI.."
|
|
newline
|
|
bitfld.long 0x0 4.--5. "CSMODE,Chip Select Mode" "0: The chip select is deasserted if QSPI_TDR.TD has..,1: The chip select is deasserted when the bit..,2: The chip select is deasserted systematically..,?"
|
|
bitfld.long 0x0 3. "DQSDLYEN,DQS Delay Enable" "0: DQS Delay cell is disabled.,1: DQS Delay cell is enabled. The DQS Delay cell.."
|
|
newline
|
|
bitfld.long 0x0 2. "WDRBT,Wait Data Read Before Transfer" "0: No effect. In SPI mode a transfer can be..,1: In SPI mode a transfer can start only if.."
|
|
bitfld.long 0x0 0. "SMM,Serial Memory Mode" "0: The QSPI is in SPI mode.,1: The QSPI is in Serial Memory mode."
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "RDR,Receive Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
|
|
wgroup.long 0xC++0x3
|
|
line.long 0x0 "TDR,Transmit Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x0 17. "TOUT,QSPI Time-out" "0: No QSPI time-out occurred since the last write..,1: At least one QSPI time-out occurred since the.."
|
|
bitfld.long 0x0 16. "RFRSHD,Refresh Done" "0: No refresh done event occurred since the last..,1: One refresh done event has been detected since.."
|
|
newline
|
|
bitfld.long 0x0 15. "CSRA,Chip Select Rise Autoclear" "0: No chip select rise has been detected since..,1: One chip select rise has been detected since the.."
|
|
bitfld.long 0x0 14. "CSFA,Chip Select Fall Autoclear" "0: No chip select fall has been detected since end..,1: One chip select fall has been detected since the.."
|
|
newline
|
|
bitfld.long 0x0 13. "QITR,QSPI Interrupt Rise" "0: No rising of the QSPI memory interrupt line has..,1: At least one QSPI memory interrupt line rising.."
|
|
bitfld.long 0x0 12. "QITF,QSPI Interrupt Fall" "0: No falling of the QSPI memory interrupt line has..,1: At least one QSPI memory interrupt line falling.."
|
|
newline
|
|
bitfld.long 0x0 11. "LWRA,Last Write Access (cleared on read)" "0: Last write access has not been sent since the..,1: At least one last write access has been sent.."
|
|
bitfld.long 0x0 10. "INSTRE,Instruction End Status (cleared on read)" "0: No instruction end has been detected since the..,1: At least one instruction end has been detected.."
|
|
newline
|
|
bitfld.long 0x0 8. "CSR,Chip Select Rise (cleared on read)" "0: No chip select rise has been detected since the..,1: At least one chip select rise has been detected.."
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0: No overrun has been detected since the last read..,1: At least one overrun error has occurred since.."
|
|
newline
|
|
bitfld.long 0x0 2. "TXEMPTY,Transmission Registers Empty (cleared by writing QSPI_TDR)" "0: As soon as data is written in QSPI_TDR.,1: QSPI_TDR and the internal shifter are empty. If.."
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing QSPI_TDR)" "0: Data has been written to QSPI_TDR and not yet..,1: The last data written in the QSPI_TDR has been.."
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading QSPI_RDR)" "0: No data has been received since the last read of..,1: Data has been received and the received data has.."
|
|
wgroup.long 0x14++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 17. "TOUT,QSPI Time-out Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 16. "RFRSHD,Refresh Done Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CSRA,Chip Select Rise Autoclear Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 14. "CSFA,Chip Select Fall Autoclear Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "QITR,QSPI Interrupt Rise Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 12. "QITF,QSPI Interrupt Fall Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "LWRA,Last Write Access Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 10. "INSTRE,Instruction End Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "CSR,Chip Select Rise Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 17. "TOUT,QSPI Time-out Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 16. "RFRSHD,Refresh Done Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CSRA,Chip Select Rise Autoclear Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 14. "CSFA,Chip Select Fall Autoclear Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "QITR,QSPI Interrupt Rise Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 12. "QITF,QSPI Interrupt Fall Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "LWRA,Last Write Access Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 10. "INSTRE,Instruction End Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "CSR,Chip Select Rise Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
|
bitfld.long 0x4 1. "TDRE,Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 17. "TOUT,QSPI Time-out Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 16. "RFRSHD,Refresh Done Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CSRA,Chip Select Rise Autoclear Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 14. "CSFA,Chip Select Fall Autoclear Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "QITR,QSPI Interrupt Rise Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 12. "QITF,QSPI Interrupt Fall Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "LWRA,Last Write Access Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 10. "INSTRE,Instruction End Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "CSR,Chip Select Rise Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "SCR,Serial Clock Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before QSCK"
|
|
bitfld.long 0x0 1. "CPHA,Clock Phase" "0: Data is captured on the leading edge of QSCK and..,1: Data is changed on the leading edge of QSCK and.."
|
|
newline
|
|
bitfld.long 0x0 0. "CPOL,Clock Polarity" "0: The inactive state value of QSCK is logic level..,1: The inactive state value of QSCK is logic level.."
|
|
line.long 0x4 "SR,Status Register"
|
|
bitfld.long 0x4 6. "CALBSY,Pad Calibration Busy" "0: Pad calibration is not ongoing.,1: Pad calibration is ongoing."
|
|
bitfld.long 0x4 5. "DLOCK,DLL Lock" "0: DLL is not locked. The QSPI Controller and..,1: DLL is locked. The QSPI Controller and physical.."
|
|
newline
|
|
bitfld.long 0x4 4. "HIDLE,QSPI Idle" "0: The QSPI is not in Idle state (either..,1: The QSPI is in Idle state (not transmitting and.."
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bitfld.long 0x4 3. "RBUSY,Read Busy" "0: The system bus interface has no activity.,1: The system bus interface is currently processing.."
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bitfld.long 0x4 2. "CSS,Chip Select Status" "0: The chip select is asserted.,1: The chip select is not asserted."
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bitfld.long 0x4 1. "QSPIENS,QSPI Enable Status" "0: The QSPI is disabled.,1: The QSPI is enabled."
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newline
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bitfld.long 0x4 0. "SYNCBSY,Synchronization Busy" "0: No event synchronization between the QSPI..,1: Event synchronization between the QSPI.."
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|
group.long 0x30++0x13
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|
line.long 0x0 "IAR,Instruction Address Register"
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hexmask.long 0x0 0.--31. 1. "ADDR,Address"
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|
line.long 0x4 "WICR,Write Instruction Code Register"
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|
hexmask.long.byte 0x4 16.--23. 1. "WROPT,Write Option Code"
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hexmask.long.word 0x4 0.--15. 1. "WRINST,Write Instruction Code"
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line.long 0x8 "IFR,Instruction Frame Register"
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|
bitfld.long 0x8 28.--29. "PROTTYP,Protocol Type" "0: Standard (Q)SPI Protocol,1: Twin-Quad Protocol,2: OctaFlash Protocol,3: HyperFlash Protocol"
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bitfld.long 0x8 27. "HFWBEN,HyperFlash Write Buffer Enable" "0: No effect.,1: Each write access received on the system bus.."
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|
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bitfld.long 0x8 26. "DDRCMDEN,DDR Mode Command Enable" "0: Transfer of instruction field is performed in..,1: Transfer of instruction field is performed in.."
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|
bitfld.long 0x8 25. "DQSEN,DQS Sampling Enable" "0: Data from the memory are not sampled with DQS..,1: Data from the memory are sampled with DQS signal."
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|
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bitfld.long 0x8 24. "APBTFRTYP,Peripheral BusTransfer Type" "0: Peripheral bus register transfer to the memory..,1: Peripheral bus register transfer to the memory.."
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bitfld.long 0x8 23. "SMRM,Serial Memory Register Mode" "0: Serial Memory registers are written via AHB..,1: Serial Memory registers are written via APB.."
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bitfld.long 0x8 22. "END,Endianness" "0: Data are sent in little-endian format to the..,1: Data are sent in big-endian format to the memory."
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hexmask.long.byte 0x8 16.--20. 1. "NBDUM,Number Of Dummy Cycles"
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newline
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bitfld.long 0x8 15. "DDREN,DDR Mode Enable" "0: Transfers are performed in Single Data Rate mode.,1: Transfers are performed in Double Data Rate mode.."
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bitfld.long 0x8 14. "CRM,Continuous Read Mode" "0: Continuous Read mode is disabled.,1: Continuous Read mode is enabled."
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bitfld.long 0x8 12. "TFRTYP,Data Transfer Type" "0: Read/Write transfer from the serial memory. Read..,1: Read/Write data transfer from the serial memory."
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bitfld.long 0x8 10.--11. "ADDRL,Address Length" "0: 8-bit address size,1: 16-bit address size,2: 24-bit address size,3: 32-bit address size"
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bitfld.long 0x8 8.--9. "OPTL,Option Code Length" "0: The option code is 1 bit long.,1: The option code is 2 bits long.,2: The option code is 4 bits long.,3: The option code is 8 bits long."
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bitfld.long 0x8 7. "DATAEN,Data Enable" "0: No data is sent/received to/from the serial..,1: Data is sent/received to/from the serial Flash.."
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bitfld.long 0x8 6. "OPTEN,Option Enable" "0: The option is not sent to the serial Flash memory.,1: The option is sent to the serial Flash memory."
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bitfld.long 0x8 5. "ADDREN,Address Enable" "0: The transfer address is not sent to the serial..,1: The transfer address is sent to the serial Flash.."
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bitfld.long 0x8 4. "INSTEN,Instruction Enable" "0: The instruction is not sent to the serial Flash..,1: The instruction is sent to the serial Flash.."
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hexmask.long.byte 0x8 0.--3. 1. "WIDTH,Width of Instruction Code Address Option Code and Data"
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line.long 0xC "RICR,Read Instruction Code Register"
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hexmask.long.byte 0xC 16.--23. 1. "RDOPT,Read Option Code"
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hexmask.long.word 0xC 0.--15. 1. "RDINST,Read Instruction Code"
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line.long 0x10 "SMR,Scrambling Mode Register"
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bitfld.long 0x10 2. "SCRKL,Scrambling Key Lock" "0: No action.,1: QSPI_SKR.USRK cannot be written until the next.."
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bitfld.long 0x10 1. "RVDIS,Scrambling/Unscrambling Random Value Disable" "0: The scrambling/unscrambling algorithm includes..,1: The scrambling/unscrambling algorithm includes.."
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newline
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bitfld.long 0x10 0. "SCREN,Scrambling/Unscrambling Enable" "0: The scrambling/unscrambling is disabled.,1: The scrambling/unscrambling is enabled."
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wgroup.long 0x44++0x3
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line.long 0x0 "SKR,Scrambling Key Register"
|
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hexmask.long 0x0 0.--31. 1. "USRK,User Scrambling Key"
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group.long 0x50++0x17
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line.long 0x0 "REFRESH,Refresh Register"
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hexmask.long 0x0 0.--31. 1. "REFRESH,REFRESH Delay Counter"
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line.long 0x4 "WRACNT,Write Access Counter Register"
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hexmask.long 0x4 0.--31. 1. "NBWRA,Number of Write Accesses"
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line.long 0x8 "DLLCFG,DLL Configuration Register"
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bitfld.long 0x8 0. "RANGE,DLL Range" "0: The QSPI Core clock is between 25 MHz and 100 MHz.,1: The QSPI Core clock is between 50 MHz and 208 MHz."
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line.long 0xC "PCALCFG,Pad Calibration Configuration Register"
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hexmask.long.byte 0xC 28.--31. 1. "CALN,Calibration Code for N-channel"
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hexmask.long.byte 0xC 24.--27. 1. "CALP,Calibration Code for P-channel"
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newline
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hexmask.long.word 0xC 8.--16. 1. "CALCNT,Pad Calibration Counter"
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bitfld.long 0xC 4.--6. "CLKDIV,Calibration Clock Division" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0xC 2. "DIFFPM,Differential Pad Mode" "0: Pad differential mode is not enabled.,1: Pad differential mode is enabled."
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bitfld.long 0xC 1. "DAPCAL,Disable Automatic Pad Calibration" "0: Pad calibration is started automatically..,1: Pad calibration is not started automatically."
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newline
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bitfld.long 0xC 0. "AAON,Analog Always On" "0: The analog part of the pad calibration circuitry..,1: The analog part of the pad calibration circuitry.."
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line.long 0x10 "PCALBP,Pad Calibration Bypass Register"
|
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hexmask.long.byte 0x10 16.--19. 1. "CALNBP,Calibration Code Bypass for N-channel"
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hexmask.long.byte 0x10 8.--11. 1. "CALPBP,Calibration Code Bypass for P-channel"
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newline
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bitfld.long 0x10 0. "BPEN,Bypass Enable" "0: Calibration code is not overridden by values of..,1: Calibration code is overridden by values of.."
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line.long 0x14 "TOUT,Timeout Register"
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hexmask.long.word 0x14 0.--15. 1. "TCNTM,Time-out Counter Maximum Value"
|
|
group.long 0xE4++0x3
|
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line.long 0x0 "WPMR,Write Protection Mode Register"
|
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Register Enable" "0: Disables the write protection on the Control..,1: Enables the write protection on the Control.."
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newline
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on Interrupt..,1: Enables the write protection on Interrupt.."
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
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rgroup.long 0xE8++0x3
|
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line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
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tree.end
|
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tree "QSPI1"
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base ad:0xE0810000
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wgroup.long 0x0++0x3
|
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line.long 0x0 "CR,Control Register"
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bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0: No effect.,1: The chip select is deasserted after the end of.."
|
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bitfld.long 0x0 10. "RTOUT,Reset Time-out" "0: No effect.,1: Request a TOUT flag reset."
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newline
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bitfld.long 0x0 9. "STTFR,Start Transfer" "0: No effect.,1: Starts the transfer when TFRTYP = 0 and SMRM = 1.."
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bitfld.long 0x0 8. "UPDCFG,Update Configuration" "0: No effect.,1: Requests an update of the QSPI Controller core.."
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newline
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bitfld.long 0x0 7. "SWRST,QSPI Software Reset" "0: No effect.,1: Resets the QSPI. A software-triggered hardware.."
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bitfld.long 0x0 5. "SRFRSH,Start REFRESH" "0: No effect.,1: Starts a refresh sequence. QSPI_ISR.RFRSHD.."
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newline
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bitfld.long 0x0 4. "STPCAL,Start Pad Calibration" "0: No effect.,1: Starts a QSPI pad calibration. QSPI_SR.CALBSY.."
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bitfld.long 0x0 3. "DLLOFF,DLL Off Request" "0: No effect.,1: Disables the DLL. When the DLL is not locked.."
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newline
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bitfld.long 0x0 2. "DLLON,DLL On Request" "0: No effect.,1: Enables the DLL. When the DLL is locked (DLOCK.."
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bitfld.long 0x0 1. "QSPIDIS,QSPI Disable" "0: No effect.,1: Disables the QSPI."
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newline
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bitfld.long 0x0 0. "QSPIEN,QSPI Enable" "0: No effect.,1: Enables the QSPI to transfer and receive data."
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group.long 0x4++0x3
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line.long 0x0 "MR,Mode Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "DLYCS,Minimum Inactive QCS Delay"
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hexmask.long.byte 0x0 16.--23. 1. "DLYBCT,Delay Between Consecutive Transfers"
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newline
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bitfld.long 0x0 15. "OENSD,Output Enable Shift Disabled" "0: By default the pad output enable signal is held..,1: The pad output enable signal is not held for one.."
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bitfld.long 0x0 13. "QICMEN,QSPI Inter-chip Mode Enable" "0: QSPI_WICR.WROPT and QSPI_RICR.RDOPT define the..,1: No dummy cycles are inserted for write accesses.."
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newline
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hexmask.long.byte 0x0 8.--11. 1. "NBBITS,Number Of Bits Per Transfer"
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bitfld.long 0x0 7. "TAMPCLR,Tamper Clear Enable" "0: A tamper detection event has no effect on QSPI..,1: A tamper detection event immediately clears QSPI.."
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newline
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bitfld.long 0x0 4.--5. "CSMODE,Chip Select Mode" "0: The chip select is deasserted if QSPI_TDR.TD has..,1: The chip select is deasserted when the bit..,2: The chip select is deasserted systematically..,?"
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bitfld.long 0x0 3. "DQSDLYEN,DQS Delay Enable" "0: DQS Delay cell is disabled.,1: DQS Delay cell is enabled. The DQS Delay cell.."
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newline
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bitfld.long 0x0 2. "WDRBT,Wait Data Read Before Transfer" "0: No effect. In SPI mode a transfer can be..,1: In SPI mode a transfer can start only if.."
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bitfld.long 0x0 0. "SMM,Serial Memory Mode" "0: The QSPI is in SPI mode.,1: The QSPI is in Serial Memory mode."
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rgroup.long 0x8++0x3
|
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line.long 0x0 "RDR,Receive Data Register"
|
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hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
|
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wgroup.long 0xC++0x3
|
|
line.long 0x0 "TDR,Transmit Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
|
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rgroup.long 0x10++0x3
|
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line.long 0x0 "ISR,Interrupt Status Register"
|
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bitfld.long 0x0 17. "TOUT,QSPI Time-out" "0: No QSPI time-out occurred since the last write..,1: At least one QSPI time-out occurred since the.."
|
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bitfld.long 0x0 16. "RFRSHD,Refresh Done" "0: No refresh done event occurred since the last..,1: One refresh done event has been detected since.."
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newline
|
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bitfld.long 0x0 15. "CSRA,Chip Select Rise Autoclear" "0: No chip select rise has been detected since..,1: One chip select rise has been detected since the.."
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|
bitfld.long 0x0 14. "CSFA,Chip Select Fall Autoclear" "0: No chip select fall has been detected since end..,1: One chip select fall has been detected since the.."
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newline
|
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bitfld.long 0x0 13. "QITR,QSPI Interrupt Rise" "0: No rising of the QSPI memory interrupt line has..,1: At least one QSPI memory interrupt line rising.."
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bitfld.long 0x0 12. "QITF,QSPI Interrupt Fall" "0: No falling of the QSPI memory interrupt line has..,1: At least one QSPI memory interrupt line falling.."
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newline
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bitfld.long 0x0 11. "LWRA,Last Write Access (cleared on read)" "0: Last write access has not been sent since the..,1: At least one last write access has been sent.."
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bitfld.long 0x0 10. "INSTRE,Instruction End Status (cleared on read)" "0: No instruction end has been detected since the..,1: At least one instruction end has been detected.."
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newline
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bitfld.long 0x0 8. "CSR,Chip Select Rise (cleared on read)" "0: No chip select rise has been detected since the..,1: At least one chip select rise has been detected.."
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|
bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0: No overrun has been detected since the last read..,1: At least one overrun error has occurred since.."
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|
newline
|
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bitfld.long 0x0 2. "TXEMPTY,Transmission Registers Empty (cleared by writing QSPI_TDR)" "0: As soon as data is written in QSPI_TDR.,1: QSPI_TDR and the internal shifter are empty. If.."
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bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing QSPI_TDR)" "0: Data has been written to QSPI_TDR and not yet..,1: The last data written in the QSPI_TDR has been.."
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newline
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading QSPI_RDR)" "0: No data has been received since the last read of..,1: Data has been received and the received data has.."
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wgroup.long 0x14++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 17. "TOUT,QSPI Time-out Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 16. "RFRSHD,Refresh Done Interrupt Enable" "0,1"
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|
newline
|
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bitfld.long 0x0 15. "CSRA,Chip Select Rise Autoclear Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 14. "CSFA,Chip Select Fall Autoclear Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "QITR,QSPI Interrupt Rise Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 12. "QITF,QSPI Interrupt Fall Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 11. "LWRA,Last Write Access Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 10. "INSTRE,Instruction End Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "CSR,Chip Select Rise Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 17. "TOUT,QSPI Time-out Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 16. "RFRSHD,Refresh Done Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 15. "CSRA,Chip Select Rise Autoclear Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 14. "CSFA,Chip Select Fall Autoclear Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "QITR,QSPI Interrupt Rise Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 12. "QITF,QSPI Interrupt Fall Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 11. "LWRA,Last Write Access Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 10. "INSTRE,Instruction End Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "CSR,Chip Select Rise Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
|
bitfld.long 0x4 1. "TDRE,Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 17. "TOUT,QSPI Time-out Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 16. "RFRSHD,Refresh Done Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CSRA,Chip Select Rise Autoclear Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 14. "CSFA,Chip Select Fall Autoclear Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "QITR,QSPI Interrupt Rise Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 12. "QITF,QSPI Interrupt Fall Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "LWRA,Last Write Access Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 10. "INSTRE,Instruction End Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "CSR,Chip Select Rise Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "SCR,Serial Clock Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before QSCK"
|
|
bitfld.long 0x0 1. "CPHA,Clock Phase" "0: Data is captured on the leading edge of QSCK and..,1: Data is changed on the leading edge of QSCK and.."
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|
newline
|
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bitfld.long 0x0 0. "CPOL,Clock Polarity" "0: The inactive state value of QSCK is logic level..,1: The inactive state value of QSCK is logic level.."
|
|
line.long 0x4 "SR,Status Register"
|
|
bitfld.long 0x4 6. "CALBSY,Pad Calibration Busy" "0: Pad calibration is not ongoing.,1: Pad calibration is ongoing."
|
|
bitfld.long 0x4 5. "DLOCK,DLL Lock" "0: DLL is not locked. The QSPI Controller and..,1: DLL is locked. The QSPI Controller and physical.."
|
|
newline
|
|
bitfld.long 0x4 4. "HIDLE,QSPI Idle" "0: The QSPI is not in Idle state (either..,1: The QSPI is in Idle state (not transmitting and.."
|
|
bitfld.long 0x4 3. "RBUSY,Read Busy" "0: The system bus interface has no activity.,1: The system bus interface is currently processing.."
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|
newline
|
|
bitfld.long 0x4 2. "CSS,Chip Select Status" "0: The chip select is asserted.,1: The chip select is not asserted."
|
|
bitfld.long 0x4 1. "QSPIENS,QSPI Enable Status" "0: The QSPI is disabled.,1: The QSPI is enabled."
|
|
newline
|
|
bitfld.long 0x4 0. "SYNCBSY,Synchronization Busy" "0: No event synchronization between the QSPI..,1: Event synchronization between the QSPI.."
|
|
group.long 0x30++0x13
|
|
line.long 0x0 "IAR,Instruction Address Register"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Address"
|
|
line.long 0x4 "WICR,Write Instruction Code Register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "WROPT,Write Option Code"
|
|
hexmask.long.word 0x4 0.--15. 1. "WRINST,Write Instruction Code"
|
|
line.long 0x8 "IFR,Instruction Frame Register"
|
|
bitfld.long 0x8 28.--29. "PROTTYP,Protocol Type" "0: Standard (Q)SPI Protocol,1: Twin-Quad Protocol,2: OctaFlash Protocol,3: HyperFlash Protocol"
|
|
bitfld.long 0x8 27. "HFWBEN,HyperFlash Write Buffer Enable" "0: No effect.,1: Each write access received on the system bus.."
|
|
newline
|
|
bitfld.long 0x8 26. "DDRCMDEN,DDR Mode Command Enable" "0: Transfer of instruction field is performed in..,1: Transfer of instruction field is performed in.."
|
|
bitfld.long 0x8 25. "DQSEN,DQS Sampling Enable" "0: Data from the memory are not sampled with DQS..,1: Data from the memory are sampled with DQS signal."
|
|
newline
|
|
bitfld.long 0x8 24. "APBTFRTYP,Peripheral BusTransfer Type" "0: Peripheral bus register transfer to the memory..,1: Peripheral bus register transfer to the memory.."
|
|
bitfld.long 0x8 23. "SMRM,Serial Memory Register Mode" "0: Serial Memory registers are written via AHB..,1: Serial Memory registers are written via APB.."
|
|
newline
|
|
bitfld.long 0x8 22. "END,Endianness" "0: Data are sent in little-endian format to the..,1: Data are sent in big-endian format to the memory."
|
|
hexmask.long.byte 0x8 16.--20. 1. "NBDUM,Number Of Dummy Cycles"
|
|
newline
|
|
bitfld.long 0x8 15. "DDREN,DDR Mode Enable" "0: Transfers are performed in Single Data Rate mode.,1: Transfers are performed in Double Data Rate mode.."
|
|
bitfld.long 0x8 14. "CRM,Continuous Read Mode" "0: Continuous Read mode is disabled.,1: Continuous Read mode is enabled."
|
|
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|
|
bitfld.long 0x8 12. "TFRTYP,Data Transfer Type" "0: Read/Write transfer from the serial memory. Read..,1: Read/Write data transfer from the serial memory."
|
|
bitfld.long 0x8 10.--11. "ADDRL,Address Length" "0: 8-bit address size,1: 16-bit address size,2: 24-bit address size,3: 32-bit address size"
|
|
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|
|
bitfld.long 0x8 8.--9. "OPTL,Option Code Length" "0: The option code is 1 bit long.,1: The option code is 2 bits long.,2: The option code is 4 bits long.,3: The option code is 8 bits long."
|
|
bitfld.long 0x8 7. "DATAEN,Data Enable" "0: No data is sent/received to/from the serial..,1: Data is sent/received to/from the serial Flash.."
|
|
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|
|
bitfld.long 0x8 6. "OPTEN,Option Enable" "0: The option is not sent to the serial Flash memory.,1: The option is sent to the serial Flash memory."
|
|
bitfld.long 0x8 5. "ADDREN,Address Enable" "0: The transfer address is not sent to the serial..,1: The transfer address is sent to the serial Flash.."
|
|
newline
|
|
bitfld.long 0x8 4. "INSTEN,Instruction Enable" "0: The instruction is not sent to the serial Flash..,1: The instruction is sent to the serial Flash.."
|
|
hexmask.long.byte 0x8 0.--3. 1. "WIDTH,Width of Instruction Code Address Option Code and Data"
|
|
line.long 0xC "RICR,Read Instruction Code Register"
|
|
hexmask.long.byte 0xC 16.--23. 1. "RDOPT,Read Option Code"
|
|
hexmask.long.word 0xC 0.--15. 1. "RDINST,Read Instruction Code"
|
|
line.long 0x10 "SMR,Scrambling Mode Register"
|
|
bitfld.long 0x10 2. "SCRKL,Scrambling Key Lock" "0: No action.,1: QSPI_SKR.USRK cannot be written until the next.."
|
|
bitfld.long 0x10 1. "RVDIS,Scrambling/Unscrambling Random Value Disable" "0: The scrambling/unscrambling algorithm includes..,1: The scrambling/unscrambling algorithm includes.."
|
|
newline
|
|
bitfld.long 0x10 0. "SCREN,Scrambling/Unscrambling Enable" "0: The scrambling/unscrambling is disabled.,1: The scrambling/unscrambling is enabled."
|
|
wgroup.long 0x44++0x3
|
|
line.long 0x0 "SKR,Scrambling Key Register"
|
|
hexmask.long 0x0 0.--31. 1. "USRK,User Scrambling Key"
|
|
group.long 0x50++0x17
|
|
line.long 0x0 "REFRESH,Refresh Register"
|
|
hexmask.long 0x0 0.--31. 1. "REFRESH,REFRESH Delay Counter"
|
|
line.long 0x4 "WRACNT,Write Access Counter Register"
|
|
hexmask.long 0x4 0.--31. 1. "NBWRA,Number of Write Accesses"
|
|
line.long 0x8 "DLLCFG,DLL Configuration Register"
|
|
bitfld.long 0x8 0. "RANGE,DLL Range" "0: The QSPI Core clock is between 25 MHz and 100 MHz.,1: The QSPI Core clock is between 50 MHz and 208 MHz."
|
|
line.long 0xC "PCALCFG,Pad Calibration Configuration Register"
|
|
hexmask.long.byte 0xC 28.--31. 1. "CALN,Calibration Code for N-channel"
|
|
hexmask.long.byte 0xC 24.--27. 1. "CALP,Calibration Code for P-channel"
|
|
newline
|
|
hexmask.long.word 0xC 8.--16. 1. "CALCNT,Pad Calibration Counter"
|
|
bitfld.long 0xC 4.--6. "CLKDIV,Calibration Clock Division" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0xC 2. "DIFFPM,Differential Pad Mode" "0: Pad differential mode is not enabled.,1: Pad differential mode is enabled."
|
|
bitfld.long 0xC 1. "DAPCAL,Disable Automatic Pad Calibration" "0: Pad calibration is started automatically..,1: Pad calibration is not started automatically."
|
|
newline
|
|
bitfld.long 0xC 0. "AAON,Analog Always On" "0: The analog part of the pad calibration circuitry..,1: The analog part of the pad calibration circuitry.."
|
|
line.long 0x10 "PCALBP,Pad Calibration Bypass Register"
|
|
hexmask.long.byte 0x10 16.--19. 1. "CALNBP,Calibration Code Bypass for N-channel"
|
|
hexmask.long.byte 0x10 8.--11. 1. "CALPBP,Calibration Code Bypass for P-channel"
|
|
newline
|
|
bitfld.long 0x10 0. "BPEN,Bypass Enable" "0: Calibration code is not overridden by values of..,1: Calibration code is overridden by values of.."
|
|
line.long 0x14 "TOUT,Timeout Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "TCNTM,Time-out Counter Maximum Value"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Register Enable" "0: Disables the write protection on the Control..,1: Enables the write protection on the Control.."
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on Interrupt..,1: Enables the write protection on Interrupt.."
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
|
|
tree.end
|
|
tree.end
|
|
tree "RSTC (Reset Controller)"
|
|
base ad:0xE001D000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "KEY,System Reset Key"
|
|
bitfld.long 0x0 3. "EXTRST,External Reset" "0: No effect.,1: If KEY = 0xA5 asserts the NRST_OUT pin."
|
|
newline
|
|
bitfld.long 0x0 0. "PROCRST,Processor Reset" "0: No effect.,1: If KEY = 0xA5 resets the processor and all the.."
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 17. "SRCMP,Software Reset Command in Progress" "0: No software command is being performed by the..,1: A Software reset command is being performed by.."
|
|
bitfld.long 0x0 16. "NRSTL,NRST Pin Level" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "RSTTYP,Reset Type"
|
|
bitfld.long 0x0 0. "URSTS,User Reset Status" "0: No high-to-low edge on NRST happened since the..,1: At least one high-to-low transition of NRST has.."
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "KEY,Write Access Password"
|
|
bitfld.long 0x0 20. "ENGCLR,Enable GPBR Clear on Tamper Event" "0: Disables the GPBR immediate clear on tamper..,1: Enables the GPBR immediate clear on tamper.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "ERSTL,External Reset Length"
|
|
bitfld.long 0x0 4. "URSTIEN,User Reset Interrupt Enable" "0: RSTC_SR.USRTS at '1' has no effect on the RSTC..,1: RSTC_SR.USRTS at '1' asserts the RSTC interrupt.."
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|
newline
|
|
bitfld.long 0x0 2. "URSTASYNC,User Reset Asynchronous Control" "0: The NRST input signal is managed synchronously.,1: The NRST input signal is managed asynchronously."
|
|
bitfld.long 0x0 1. "SCKSW,Slow Clock Switching" "0: The detection of a 32.768 kHz crystal failure..,1: The detection of a 32.768 kHz crystal failure.."
|
|
newline
|
|
bitfld.long 0x0 0. "URSTEN,User Reset Enable" "0: The detection of a low level on the NRST pin..,1: The detection of a low level on the NRST pin.."
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "GRSTR,Generic Reset Register"
|
|
bitfld.long 0x0 6. "USB_RST3,USB Reset" "0: POR is disabled.,1: POR is enabled."
|
|
bitfld.long 0x0 5. "USB_RST2,USB Reset" "0: POR is disabled.,1: POR is enabled."
|
|
newline
|
|
bitfld.long 0x0 4. "USB_RST1,USB Reset" "0: POR is disabled.,1: POR is enabled."
|
|
bitfld.long 0x0 2. "DDR_PHY_RST,DDR PHY Reset" "0: DDR PHY reset is asserted.,1: DDR PHY reset is de-asserted."
|
|
newline
|
|
bitfld.long 0x0 0. "DDR_RST,DDR Reset" "0: DDR Controller reset is asserted.,1: DDR Controller reset is de-asserted."
|
|
tree.end
|
|
tree "RTC (Real-time Clock)"
|
|
base ad:0xE001D0A8
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 16.--17. "CALEVSEL,Calendar Event Selection" "0: Week change (every Monday at time 00:00:00),1: Month change (every 01 of each month at time..,2: Year change (every January 1 at time 00:00:00),?"
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|
bitfld.long 0x0 8.--9. "TIMEVSEL,Time Event Selection" "0: Minute change,1: Hour change,2: Every day at midnight,3: Every day at noon"
|
|
newline
|
|
bitfld.long 0x0 1. "UPDCAL,Update Request Calendar Register" "0: No effect or if UPDCAL has been previously..,1: Stops the RTC calendar counting."
|
|
bitfld.long 0x0 0. "UPDTIM,Update Request Time Register" "0: No effect or if UPDTIM has been previously..,1: Stops the RTC time counting."
|
|
line.long 0x4 "MR,Mode Register"
|
|
bitfld.long 0x4 28.--29. "TPERIOD,Period of the Output Pulse" "0: 1 second,1: 500 ms,2: 250 ms,3: 125 ms"
|
|
bitfld.long 0x4 24.--26. "THIGH,High Duration of the Output Pulse" "0: 31.2 ms,1: 15.6 ms,2: 3.91 ms,3: 976 us,4: 488 us,5: 122 us,6: 30.5 us,7: 15.2 us"
|
|
newline
|
|
bitfld.long 0x4 20.--22. "OUT1,RTCOUT1 Output and ADC Last Channel Trigger Event Source Selection" "0: No waveform stuck at '0',1: 1 Hz square wave,2: 32 Hz square wave,3: 64 Hz square wave,4: 512 Hz square wave,5: Output toggles when alarm flag rises,6: Output is a copy of the alarm flag,7: Duty cycle programmable pulse"
|
|
bitfld.long 0x4 16.--18. "OUT0,RTCOUT0 Output and All ADC Channel Trigger Event Source Selection" "0: No waveform stuck at '0',1: 1 Hz square wave,2: 32 Hz square wave,3: 64 Hz square wave,4: 512 Hz square wave,5: Output toggles when alarm flag rises,6: Output is a copy of the alarm flag,7: Duty cycle programmable pulse"
|
|
newline
|
|
bitfld.long 0x4 15. "HIGHPPM,HIGH PPM Correction" "0: Lower range ppm correction with accurate..,1: Higher range ppm correction with accurate.."
|
|
hexmask.long.byte 0x4 8.--14. 1. "CORRECTION,Slow Clock Correction"
|
|
newline
|
|
bitfld.long 0x4 4. "NEGPPM,NEGative PPM Correction" "0: Positive correction (the divider will be..,1: Negative correction (the divider will be.."
|
|
bitfld.long 0x4 2. "UTC,UTC Time Format" "0: Gregorian or Persian calendar.,1: UTC format."
|
|
newline
|
|
bitfld.long 0x4 1. "PERSIAN,PERSIAN Calendar" "0: Gregorian calendar.,1: Persian calendar."
|
|
bitfld.long 0x4 0. "HRMOD,12-/24-hour Mode" "0: 24-hour mode is selected.,1: 12-hour mode is selected."
|
|
line.long 0x8 "TIMR,Time Register"
|
|
bitfld.long 0x8 22. "AMPM,Ante Meridiem Post Meridiem Indicator" "0: AM.,1: PM."
|
|
hexmask.long.byte 0x8 16.--21. 1. "HOUR,Current Hour"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--14. 1. "MIN,Current Minute"
|
|
hexmask.long.byte 0x8 0.--6. 1. "SEC,Current Second"
|
|
group.long 0x8++0xB
|
|
line.long 0x0 "TIMR_UTC_MODE,Time Register"
|
|
hexmask.long 0x0 0.--31. 1. "UTC_TIME,Current UTC Time"
|
|
line.long 0x4 "CALR,Calendar Register"
|
|
hexmask.long.byte 0x4 24.--29. 1. "DATE,Current Day in Current Month"
|
|
bitfld.long 0x4 21.--23. "DAY,Current Day in Current Week" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--20. 1. "MONTH,Current Month"
|
|
hexmask.long.byte 0x4 8.--15. 1. "YEAR,Current Year"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "CENT,Current Century"
|
|
line.long 0x8 "TIMALR,Time Alarm Register"
|
|
bitfld.long 0x8 23. "HOUREN,Hour Alarm Enable" "0: The hour-matching alarm is disabled.,1: The hour-matching alarm is enabled."
|
|
bitfld.long 0x8 22. "AMPM,AM/PM Indicator" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--21. 1. "HOUR,Hour Alarm"
|
|
bitfld.long 0x8 15. "MINEN,Minute Alarm Enable" "0: The minute-matching alarm is disabled.,1: The minute-matching alarm is enabled."
|
|
newline
|
|
hexmask.long.byte 0x8 8.--14. 1. "MIN,Minute Alarm"
|
|
bitfld.long 0x8 7. "SECEN,Second Alarm Enable" "0: The second-matching alarm is disabled.,1: The second-matching alarm is enabled."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--6. 1. "SEC,Second Alarm"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "TIMALR_UTC_MODE,Time Alarm Register"
|
|
hexmask.long 0x0 0.--31. 1. "UTC_TIME,UTC_TIME Alarm"
|
|
line.long 0x4 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x4 31. "DATEEN,Date Alarm Enable" "0: The date-matching alarm is disabled.,1: The date-matching alarm is enabled."
|
|
hexmask.long.byte 0x4 24.--29. 1. "DATE,Date Alarm"
|
|
newline
|
|
bitfld.long 0x4 23. "MTHEN,Month Alarm Enable" "0: The month-matching alarm is disabled.,1: The month-matching alarm is enabled."
|
|
hexmask.long.byte 0x4 16.--20. 1. "MONTH,Month Alarm"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "CALALR_UTC_MODE,Calendar Alarm Register"
|
|
bitfld.long 0x0 0. "UTCEN,UTC Alarm Enable" "0: The UTC-matching alarm is disabled.,1: The UTC-matching alarm is enabled."
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 5. "TDERR,Time and/or Date Free Running Error" "0: The internal free running counters are carrying..,1: The internal free running counters have been.."
|
|
bitfld.long 0x0 4. "CALEV,Calendar Event" "0: No calendar event has occurred since the last..,1: At least one calendar event has occurred since.."
|
|
newline
|
|
bitfld.long 0x0 3. "TIMEV,Time Event" "0: No time event has occurred since the last clear.,1: At least one time event has occurred since the.."
|
|
bitfld.long 0x0 2. "SEC,Second Event" "0: No second event has occurred since the last clear.,1: At least one second event has occurred since the.."
|
|
newline
|
|
bitfld.long 0x0 1. "ALARM,Alarm Flag" "0: No alarm matching condition occurred.,1: An alarm matching condition has occurred."
|
|
bitfld.long 0x0 0. "ACKUPD,Acknowledge for Update" "0: Time and calendar registers cannot be updated.,1: Time and calendar registers can be updated."
|
|
wgroup.long 0x1C++0xB
|
|
line.long 0x0 "SCCR,Status Clear Command Register"
|
|
bitfld.long 0x0 5. "TDERRCLR,Time and/or Date Free Running Error Clear" "0,1"
|
|
bitfld.long 0x0 4. "CALCLR,Calendar Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TIMCLR,Time Clear" "0,1"
|
|
bitfld.long 0x0 2. "SECCLR,Second Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ALRCLR,Alarm Clear" "0,1"
|
|
bitfld.long 0x0 0. "ACKCLR,Acknowledge Clear" "0,1"
|
|
line.long 0x4 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x4 5. "TDERREN,Time and/or Date Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 4. "CALEN,Calendar Event Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "TIMEN,Time Event Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 2. "SECEN,Second Event Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ALREN,Alarm Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 0. "ACKEN,Acknowledge Update Interrupt Enable" "0,1"
|
|
line.long 0x8 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x8 5. "TDERRDIS,Time and/or Date Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 4. "CALDIS,Calendar Event Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "TIMDIS,Time Event Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 2. "SECDIS,Second Event Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "ALRDIS,Alarm Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 0. "ACKDIS,Acknowledge Update Interrupt Disable" "0,1"
|
|
rgroup.long 0x28++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 5. "TDERR,Time and/or Date Error Mask" "0,1"
|
|
bitfld.long 0x0 4. "CAL,Calendar Event Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TIM,Time Event Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "SEC,Second Event Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ALR,Alarm Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "ACK,Acknowledge Update Interrupt Mask" "0,1"
|
|
line.long 0x4 "VER,Valid Entry Register"
|
|
bitfld.long 0x4 3. "NVCALALR,Non-valid Calendar Alarm" "0: No invalid data has been detected in RTC_CALALR..,1: RTC_CALALR has contained invalid data since it.."
|
|
bitfld.long 0x4 2. "NVTIMALR,Non-valid Time Alarm" "0: No invalid data has been detected in RTC_TIMALR..,1: RTC_TIMALR has contained invalid data since it.."
|
|
newline
|
|
bitfld.long 0x4 1. "NVCAL,Non-valid Calendar" "0: No invalid data has been detected in RTC_CALR..,1: RTC_CALR has contained invalid data since it was.."
|
|
bitfld.long 0x4 0. "NVTIM,Non-valid Time" "0: No invalid data has been detected in RTC_TIMR..,1: RTC_TIMR has contained invalid data since it was.."
|
|
rgroup.long 0xB0++0x3
|
|
line.long 0x0 "TSTR0,TimeStamp Time Register 0"
|
|
bitfld.long 0x0 31. "BACKUP,System Mode of the Tamper (cleared by reading RTC_TSSR0)" "0: The state of the system is different from backup..,1: The system is in backup mode when the tamper.."
|
|
hexmask.long.byte 0x0 24.--27. 1. "TEVCNT,Tamper Events Counter (cleared by reading RTC_TSSR0)"
|
|
newline
|
|
bitfld.long 0x0 22. "AMPM,AM/PM Indicator of the Tamper (cleared by reading RTC_TSSR0)" "0,1"
|
|
hexmask.long.byte 0x0 16.--21. 1. "HOUR,Hours of the Tamper (cleared by reading RTC_TSSR0)"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--14. 1. "MIN,Minutes of the Tamper (cleared by reading RTC_TSSR0)"
|
|
hexmask.long.byte 0x0 0.--6. 1. "SEC,Seconds of the Tamper (cleared by reading RTC_TSSR0)"
|
|
rgroup.long 0xB0++0x7
|
|
line.long 0x0 "TSTR0_UTC_MODE,TimeStamp Time Register 0"
|
|
bitfld.long 0x0 31. "BACKUP,System Mode of the Tamper (cleared by reading RTC_TSSR0)" "0: The state of the system is different from Backup..,1: The system is in Backup mode when the tamper.."
|
|
hexmask.long.byte 0x0 24.--27. 1. "TEVCNT,Tamper Events Counter (cleared by reading RTC_TSSR0)"
|
|
line.long 0x4 "TSDR0,TimeStamp Date Register 0"
|
|
hexmask.long.byte 0x4 24.--29. 1. "DATE,Date of the Tamper (cleared by reading RTC_TSSRx)"
|
|
bitfld.long 0x4 21.--23. "DAY,Day of the Tamper (cleared by reading RTC_TSSRx)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--20. 1. "MONTH,Month of the Tamper (cleared by reading RTC_TSSRx)"
|
|
hexmask.long.byte 0x4 8.--15. 1. "YEAR,Year of the Tamper (cleared by reading RTC_TSSRx)"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "CENT,Century of the Tamper (cleared by reading RTC_TSSRx)"
|
|
rgroup.long 0xB4++0xB
|
|
line.long 0x0 "TSDR0_UTC_MODE,TimeStamp Date Register 0"
|
|
hexmask.long 0x0 0.--31. 1. "UTC_TIME,Time of the Tamper (UTC format)"
|
|
line.long 0x4 "TSSR0,TimeStamp Source Register 0"
|
|
bitfld.long 0x4 21. "DET3,PIOBU Intrusion Detector (cleared on read)" "0,1"
|
|
bitfld.long 0x4 20. "DET2,PIOBU Intrusion Detector (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "DET1,PIOBU Intrusion Detector (cleared on read)" "0,1"
|
|
bitfld.long 0x4 18. "DET0,PIOBU Intrusion Detector (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "JTAG,JTAG Pins Monitor (cleared on read)" "0,1"
|
|
bitfld.long 0x4 2. "TST,Test Pin Monitor (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "DWDTSW,Dual WatchDog Timer Event(cleared on read)" "0,1"
|
|
line.long 0x8 "TSTR1,TimeStamp Time Register 1"
|
|
bitfld.long 0x8 31. "BACKUP,System Mode of the Tamper (cleared by reading RTC_TSSR1)" "0: The state of the system is different from Backup..,1: The system is in Backup mode when the tamper.."
|
|
bitfld.long 0x8 22. "AMPM,AM/PM Indicator of the Tamper (cleared by reading RTC_TSSR1)" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--21. 1. "HOUR,Hours of the Tamper (cleared by reading RTC_TSSR1)"
|
|
hexmask.long.byte 0x8 8.--14. 1. "MIN,Minutes of the Tamper (cleared by reading RTC_TSSR1)"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--6. 1. "SEC,Seconds of the Tamper (cleared by reading RTC_TSSR1)"
|
|
rgroup.long 0xBC++0x7
|
|
line.long 0x0 "TSTR1_UTC_MODE,TimeStamp Time Register 1"
|
|
bitfld.long 0x0 31. "BACKUP,System Mode of the Tamper (cleared by reading RTC_TSSR1)" "0: The state of the system is different from Backup..,1: The system is in Backup mode when the tamper.."
|
|
line.long 0x4 "TSDR1,TimeStamp Date Register 1"
|
|
hexmask.long.byte 0x4 24.--29. 1. "DATE,Date of the Tamper (cleared by reading RTC_TSSRx)"
|
|
bitfld.long 0x4 21.--23. "DAY,Day of the Tamper (cleared by reading RTC_TSSRx)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--20. 1. "MONTH,Month of the Tamper (cleared by reading RTC_TSSRx)"
|
|
hexmask.long.byte 0x4 8.--15. 1. "YEAR,Year of the Tamper (cleared by reading RTC_TSSRx)"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "CENT,Century of the Tamper (cleared by reading RTC_TSSRx)"
|
|
rgroup.long 0xC0++0x7
|
|
line.long 0x0 "TSDR1_UTC_MODE,TimeStamp Date Register 1"
|
|
hexmask.long 0x0 0.--31. 1. "UTC_TIME,Time of the Tamper (UTC format)"
|
|
line.long 0x4 "TSSR1,TimeStamp Source Register 1"
|
|
bitfld.long 0x4 21. "DET3,PIOBU Intrusion Detector (cleared on read)" "0,1"
|
|
bitfld.long 0x4 20. "DET2,PIOBU Intrusion Detector (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "DET1,PIOBU Intrusion Detector (cleared on read)" "0,1"
|
|
bitfld.long 0x4 18. "DET0,PIOBU Intrusion Detector (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "JTAG,JTAG Pins Monitor (cleared on read)" "0,1"
|
|
bitfld.long 0x4 2. "TST,Test Pin Monitor (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "DWDTSW,Dual WatchDog Timer Event(cleared on read)" "0,1"
|
|
tree.end
|
|
tree "RTT (Real-time Timer)"
|
|
base ad:0xE001D020
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 24. "RTC1HZ,Real-Time Clock 1Hz Clock Selection" "0: The RTT 32-bit counter is driven by the 16-bit..,1: The RTT 32-bit counter is driven by the 1Hz RTC.."
|
|
bitfld.long 0x0 21. "INC2AEN,RTTINC2 Alarm and Interrupt Enable" "0: The RTTINC2 flag is not a source of the RTT..,1: The RTTINC2 flag is a source of the RTT alarm.."
|
|
newline
|
|
bitfld.long 0x0 20. "RTTDIS,Real-time Timer Disable" "0: The real-time timer is enabled.,1: The real-time timer is disabled (no dynamic.."
|
|
bitfld.long 0x0 18. "RTTRST,Real-time Timer Restart" "0: No effect.,1: Reloads and restarts the clock divider with the.."
|
|
newline
|
|
bitfld.long 0x0 17. "RTTINCIEN,Real-time Timer Increment Interrupt Enable" "0: The bit RTTINC in RTT_SR has no effect on..,1: The bit RTTINC in RTT_SR asserts interrupt."
|
|
bitfld.long 0x0 16. "ALMIEN,Alarm Interrupt Enable" "0: The bit ALMS in RTT_SR has no effect on interrupt.,1: The bit ALMS in RTT_SR asserts interrupt."
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RTPRES,Real-time Timer Prescaler Value"
|
|
line.long 0x4 "AR,Alarm Register"
|
|
hexmask.long 0x4 0.--31. 1. "ALMV,Alarm Value"
|
|
rgroup.long 0x8++0x7
|
|
line.long 0x0 "VR,Value Register"
|
|
hexmask.long 0x0 0.--31. 1. "CRTV,Current Real-time Value"
|
|
line.long 0x4 "SR,Status Register"
|
|
bitfld.long 0x4 2. "RTTINC2,Predefined Number of Prescaler Roll-overs Status (cleared on read)" "0: SELINC2=0 or the number of prescaler roll-overs..,1: The number of prescaler roll-overs programmed.."
|
|
bitfld.long 0x4 1. "RTTINC,Prescaler Roll-over Status (cleared on read)" "0: No prescaler roll-over occurred since the last..,1: Prescaler roll-over occurred since the last read.."
|
|
newline
|
|
bitfld.long 0x4 0. "ALMS,Real-time Alarm Status (cleared on read)" "0: The Real-time Alarm has not occurred since the..,1: The Real-time Alarm occurred since the last read.."
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "MODR,Modulo Selection Register"
|
|
bitfld.long 0x0 0.--2. "SELINC2,Selection of the 32-bit Counter Modulo to generate RTTINC2 Flag" "0: The RTTINC2 flag never rises,1: The RTTINC2 flag is set when CRTV modulo 64..,2: The RTTINC2 flag is set when CRTV modulo 128..,3: The RTTINC2 flag is set when CRTV modulo 256..,4: The RTTINC2 flag is set when CRTV modulo 512..,5: The RTTINC2 flag is set when CRTV modulo 1024..,6: The RTTINC2 flag is set when CRTV modulo 2048..,7: The RTTINC2 flag is set when CRTV modulo 4096.."
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "TSR,TimeStamp Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "TSTAMP,Real-time Timer Value Timestamp"
|
|
tree.end
|
|
tree "SCKC (Slow Clock Controller)"
|
|
base ad:0xE001D050
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR,Slow Clock Controller Configuration Register"
|
|
bitfld.long 0x0 24. "TD_OSCSEL,Timing Domain Slow Clock Selector" "0: Slow clock of the timing domain is driven by the..,1: Slow clock of the timing domain is driven by the.."
|
|
tree.end
|
|
tree "SDMMC (Secure Digital MultiMedia Card Controller)"
|
|
base ad:0x0
|
|
tree "SDMMC0"
|
|
base ad:0xE1204000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "SSAR,SDMA System Address / Argument 2 Register"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,SDMA System Address"
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "SSAR_CMD23_MODE,SDMA System Address / Argument 2 Register"
|
|
hexmask.long 0x0 0.--31. 1. "ARG2,Argument 2"
|
|
group.word 0x4++0x3
|
|
line.word 0x0 "BSR,Block Size Register"
|
|
bitfld.word 0x0 12.--14. "BOUNDARY,SDMA Buffer Boundary" "0: 4-Kbyte boundary,1: 8-Kbyte boundary,2: 16-Kbyte boundary,3: 32-Kbyte boundary,4: 64-Kbyte boundary,5: 128-Kbyte boundary,6: 256-Kbyte boundary,7: 512-Kbyte boundary"
|
|
hexmask.word 0x0 0.--9. 1. "BLKSIZE,Transfer Block Size"
|
|
line.word 0x2 "BCR,Block Count Register"
|
|
hexmask.word 0x2 0.--15. 1. "BLKCNT,Block Count for Current Transfer"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "ARG1R,Argument 1 Register"
|
|
hexmask.long 0x0 0.--31. 1. "ARG1,Argument 1"
|
|
group.word 0xC++0x3
|
|
line.word 0x0 "TMR,Transfer Mode Register"
|
|
bitfld.word 0x0 5. "MSBSEL,Multi/Single Block Selection" "0,1"
|
|
bitfld.word 0x0 4. "DTDSEL,Data Transfer Direction Selection" "0: Writes data from the SDMMC to the device.,1: Reads data from the device to the SDMMC."
|
|
newline
|
|
bitfld.word 0x0 2.--3. "ACMDEN,Auto Command Enable" "0: Auto Command Disabled,1: Auto CMD12 Enabled,2: Auto CMD23 Enabled,?"
|
|
bitfld.word 0x0 1. "BCEN,Block Count Enable" "0: Block count is disabled.,1: Block count is enabled."
|
|
newline
|
|
bitfld.word 0x0 0. "DMAEN,DMA Enable" "0: DMA functionality is disabled.,1: DMA functionality is enabled."
|
|
line.word 0x2 "CR,Command Register"
|
|
hexmask.word.byte 0x2 8.--13. 1. "CMDIDX,Command Index"
|
|
bitfld.word 0x2 6.--7. "CMDTYP,Command Type" "0: Other commands,1: CMD52 to write 'Bus Suspend' in the Card Common..,2: CMD52 to write 'Function Select' in the Card..,3: CMD12 CMD52 to write 'I/O Abort' in the Card.."
|
|
newline
|
|
bitfld.word 0x2 5. "DPSEL,Data Present Select" "0: No data present,1: Data present"
|
|
bitfld.word 0x2 4. "CMDICEN,Command Index Check Enable" "0: The Command Index Check is disabled.,1: The Command Index Check is enabled."
|
|
newline
|
|
bitfld.word 0x2 3. "CMDCCEN,Command CRC Check Enable" "0: The Command CRC Check is disabled.,1: The Command CRC Check is enabled."
|
|
bitfld.word 0x2 0.--1. "RESPTYP,Response Type" "0: No Response,1: Response Length 136,2: Response Length 48,3: Response Length 48 with Busy"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x10)++0x3
|
|
line.long 0x0 "RR[$1],Response Register x"
|
|
hexmask.long 0x0 0.--31. 1. "CMDRESP,Command Response"
|
|
repeat.end
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "BDPR,Buffer Data Port Register"
|
|
hexmask.long 0x0 0.--31. 1. "BUFDATA,Buffer Data"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "PSR,Present State Register"
|
|
bitfld.long 0x0 24. "CMDLL,CMD Line Level" "0,1"
|
|
hexmask.long.byte 0x0 20.--23. 1. "DATLL,DAT[3:0] Line Level"
|
|
newline
|
|
bitfld.long 0x0 19. "WRPPL,Write Protect Pin Level" "0: Write protected (SDMMC_WP = 0),1: Write enabled (SDMMC_WP = 1)"
|
|
bitfld.long 0x0 18. "CARDDPL,Card Detect Pin Level" "0: No card present (SDMMC_CD = 1).,1: Card present (SDMMC_CD = 0)."
|
|
newline
|
|
bitfld.long 0x0 17. "CARDSS,Card State Stable" "0: Reset or debouncing.,1: No card or card inserted."
|
|
bitfld.long 0x0 16. "CARDINS,Card Inserted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "BUFRDEN,Buffer Read Enable" "0,1"
|
|
bitfld.long 0x0 10. "BUFWREN,Buffer Write Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RTACT,Read Transfer Active" "0,1"
|
|
bitfld.long 0x0 8. "WTACT,Write Transfer Active" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DLACT,DAT Line Active" "0: DAT line inactive.,1: DAT line active."
|
|
bitfld.long 0x0 1. "CMDINHD,Command Inhibit (DAT)" "0: Can issue a command which uses the DAT line(s).,1: Cannot issue a command which uses the DAT line(s)."
|
|
newline
|
|
bitfld.long 0x0 0. "CMDINHC,Command Inhibit (CMD)" "0: Can issue a command using only CMD line.,1: Cannot issue a command."
|
|
group.byte 0x28++0x0
|
|
line.byte 0x0 "HC1R_EMMC_MODE,Host Control 1 Register"
|
|
bitfld.byte 0x0 5. "EXTDW,Extended Data Width" "0,1"
|
|
bitfld.byte 0x0 3.--4. "DMASEL,DMA Select" "0: SDMA is selected,?,2: 32-bit Address ADMA2 is selected,?"
|
|
newline
|
|
bitfld.byte 0x0 2. "HSEN,High Speed Enable" "0: Normal Speed mode.,1: High Speed mode."
|
|
bitfld.byte 0x0 1. "DW,Data Width" "0: 1-bit mode.,1: 4-bit mode."
|
|
group.byte 0x28++0x2
|
|
line.byte 0x0 "HC1R_SD_SDIO_MODE,Host Control 1 Register"
|
|
bitfld.byte 0x0 7. "CARDDSEL,Card Detect Signal Selection" "0: The SDMMC_CD pin is selected.,1: The Card Detect Test Level (CARDDTL) is selected.."
|
|
bitfld.byte 0x0 6. "CARDDTL,Card Detect Test Level" "0: No card.,1: Card inserted."
|
|
newline
|
|
bitfld.byte 0x0 3.--4. "DMASEL,DMA Select" "0: SDMA is selected,?,2: 32-bit Address ADMA2 is selected,?"
|
|
bitfld.byte 0x0 2. "HSEN,High Speed Enable" "0: Normal Speed mode.,1: High Speed mode."
|
|
newline
|
|
bitfld.byte 0x0 1. "DW,Data Width" "0: 1-bit mode.,1: 4-bit mode."
|
|
bitfld.byte 0x0 0. "LEDCTRL,LED Control" "0: LED off.,1: LED on."
|
|
line.byte 0x1 "PCR,Power Control Register"
|
|
bitfld.byte 0x1 0. "SDBPWR,SD Bus Power" "0,1"
|
|
line.byte 0x2 "BGCR_EMMC_MODE,Block Gap Control Register"
|
|
bitfld.byte 0x2 1. "CONTR,Continue Request" "0: No effect.,1: Restart."
|
|
bitfld.byte 0x2 0. "STPBGR,Stop At Block Gap Request" "0: Transfer,1: Stop"
|
|
group.byte 0x2A++0x1
|
|
line.byte 0x0 "BGCR_SD_SDIO_MODE,Block Gap Control Register"
|
|
bitfld.byte 0x0 3. "INTBG,Interrupt at Block Gap" "0: Interrupt detection disabled.,1: Interrupt detection enabled."
|
|
bitfld.byte 0x0 2. "RWCTRL,Read Wait Control" "0: Disables Read Wait control.,1: Enables Read Wait control."
|
|
newline
|
|
bitfld.byte 0x0 1. "CONTR,Continue Request" "0: No effect.,1: Restart."
|
|
bitfld.byte 0x0 0. "STPBGR,Stop At Block Gap Request" "0: Transfer,1: Stop"
|
|
line.byte 0x1 "WCR,Wakeup Control Register"
|
|
bitfld.byte 0x1 2. "WKENCREM,Wakeup Event Enable on Card Removal" "0: Wakeup Event disabled.,1: Wakeup Event enabled."
|
|
bitfld.byte 0x1 1. "WKENCINS,Wakeup Event Enable on Card Insertion" "0: Wakeup Event disabled.,1: Wakeup Event enabled."
|
|
newline
|
|
bitfld.byte 0x1 0. "WKENCINT,Wakeup Event Enable on Card Interrupt" "0: Wakeup Event disabled.,1: Wakeup Event enabled."
|
|
group.word 0x2C++0x1
|
|
line.word 0x0 "CCR,Clock Control Register"
|
|
hexmask.word.byte 0x0 8.--15. 1. "SDCLKFSEL,SDCLK Frequency Select"
|
|
bitfld.word 0x0 6.--7. "USDCLKFSEL,Upper Bits of SDCLK Frequency Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 5. "CLKGSEL,Clock Generator Select" "0: Divided Clock mode (BASECLK is used to generate..,1: Programmable Clock mode (MULTCLK is used to.."
|
|
bitfld.word 0x0 2. "SDCLKEN,SD Clock Enable" "0: SD Clock disabled,1: SD Clock enabled"
|
|
newline
|
|
bitfld.word 0x0 1. "INTCLKS,Internal Clock Stable" "0: Internal clock not ready.,1: Internal clock ready."
|
|
bitfld.word 0x0 0. "INTCLKEN,Internal Clock Enable" "0: The internal clock stops.,1: The internal clock oscillates."
|
|
group.byte 0x2E++0x1
|
|
line.byte 0x0 "TCR,Timeout Control Register"
|
|
hexmask.byte 0x0 0.--3. 1. "DTCVAL,Data Timeout Counter Value"
|
|
line.byte 0x1 "SRR,Software Reset Register"
|
|
bitfld.byte 0x1 2. "SWRSTDAT,Software reset for DAT line" "0: Work,1: Reset"
|
|
bitfld.byte 0x1 1. "SWRSTCMD,Software reset for CMD line" "0: Work,1: Reset"
|
|
newline
|
|
bitfld.byte 0x1 0. "SWRSTALL,Software reset for All" "0: Work,1: Reset"
|
|
group.word 0x30++0x1
|
|
line.word 0x0 "NISTR_EMMC_MODE,Normal Interrupt Status Register"
|
|
bitfld.word 0x0 15. "ERRINT,Error Interrupt" "0: No error.,1: Error."
|
|
bitfld.word 0x0 14. "BOOTAR,Boot Acknowledge Received" "0: Boot Acknowledge pattern not received.,1: Boot Acknowledge pattern received."
|
|
newline
|
|
bitfld.word 0x0 5. "BRDRDY,Buffer Read Ready" "0: Not ready to read buffer.,1: Ready to read buffer."
|
|
bitfld.word 0x0 4. "BWRRDY,Buffer Write Ready" "0: Not ready to write buffer.,1: Ready to write buffer."
|
|
newline
|
|
bitfld.word 0x0 3. "DMAINT,DMA Interrupt" "0: No DMA interrupt.,1: DMA interrupt."
|
|
bitfld.word 0x0 2. "BLKGE,Block Gap Event" "0: No block gap event.,1: Transaction stopped at block gap."
|
|
newline
|
|
bitfld.word 0x0 1. "TRFC,Transfer Complete" "0: Command execution is not complete.,1: Command execution is complete."
|
|
bitfld.word 0x0 0. "CMDC,Command Complete" "0: No command complete.,1: Command complete."
|
|
group.word 0x30++0x3
|
|
line.word 0x0 "NISTR_SD_SDIO_MODE,Normal Interrupt Status Register"
|
|
bitfld.word 0x0 15. "ERRINT,Error Interrupt" "0: No error.,1: Error."
|
|
bitfld.word 0x0 8. "CINT,Card Interrupt" "0: No card interrupt.,1: Card interrupt."
|
|
newline
|
|
bitfld.word 0x0 7. "CREM,Card Removal" "0: Card state unstable or card inserted.,1: Card removed."
|
|
bitfld.word 0x0 6. "CINS,Card Insertion" "0: Card state unstable or card removed.,1: Card inserted."
|
|
newline
|
|
bitfld.word 0x0 5. "BRDRDY,Buffer Read Ready" "0: Not ready to read buffer.,1: Ready to read buffer."
|
|
bitfld.word 0x0 4. "BWRRDY,Buffer Write Ready" "0: Not ready to write buffer.,1: Ready to write buffer."
|
|
newline
|
|
bitfld.word 0x0 3. "DMAINT,DMA Interrupt" "0: No DMA Interrupt.,1: DMA Interrupt."
|
|
bitfld.word 0x0 2. "BLKGE,Block Gap Event" "0: No block gap event.,1: Transaction stopped at block gap."
|
|
newline
|
|
bitfld.word 0x0 1. "TRFC,Transfer Complete" "0: Command execution is not complete.,1: Command execution is complete."
|
|
bitfld.word 0x0 0. "CMDC,Command Complete" "0: No command complete.,1: Command complete."
|
|
line.word 0x2 "EISTR_EMMC_MODE,Error Interrupt Status Register"
|
|
bitfld.word 0x2 12. "BOOTAE,Boot Acknowledge Error" "0: No error.,1: Error."
|
|
bitfld.word 0x2 10. "TUNING,Tuning Error" "0: No error.,1: Error."
|
|
newline
|
|
bitfld.word 0x2 9. "ADMA,ADMA Error" "0: No error.,1: Error."
|
|
bitfld.word 0x2 8. "ACMD,Auto CMD Error" "0: No error.,1: Error."
|
|
newline
|
|
bitfld.word 0x2 7. "CURLIM,Current Limit Error" "0: No error.,1: Error."
|
|
bitfld.word 0x2 6. "DATEND,Data End Bit Error" "0: No error.,1: Error."
|
|
newline
|
|
bitfld.word 0x2 5. "DATCRC,Data CRC Error" "0: No error.,1: Error."
|
|
bitfld.word 0x2 4. "DATTEO,Data Timeout error" "0: No error.,1: Error."
|
|
newline
|
|
bitfld.word 0x2 3. "CMDIDX,Command Index Error" "0: No error.,1: Error."
|
|
bitfld.word 0x2 2. "CMDEND,Command End Bit Error" "0: No error.,1: Error."
|
|
newline
|
|
bitfld.word 0x2 1. "CMDCRC,Command CRC Error" "0,1"
|
|
bitfld.word 0x2 0. "CMDTEO,Command Timeout Error" "0,1"
|
|
group.word 0x32++0x3
|
|
line.word 0x0 "EISTR_SD_SDIO_MODE,Error Interrupt Status Register"
|
|
bitfld.word 0x0 10. "TUNING,Tuning Error" "0: No error.,1: Error."
|
|
bitfld.word 0x0 9. "ADMA,ADMA Error" "0: No error.,1: Error."
|
|
newline
|
|
bitfld.word 0x0 8. "ACMD,Auto CMD Error" "0: No error.,1: Error."
|
|
bitfld.word 0x0 7. "CURLIM,Current Limit Error" "0: No error.,1: Error."
|
|
newline
|
|
bitfld.word 0x0 6. "DATEND,Data End Bit Error" "0: No error.,1: Error."
|
|
bitfld.word 0x0 5. "DATCRC,Data CRC error" "0: No error.,1: Error."
|
|
newline
|
|
bitfld.word 0x0 4. "DATTEO,Data Timeout Error" "0: No error.,1: Error."
|
|
bitfld.word 0x0 3. "CMDIDX,Command Index Error" "0: No error.,1: Error."
|
|
newline
|
|
bitfld.word 0x0 2. "CMDEND,Command End Bit Error" "0: No error.,1: Error."
|
|
bitfld.word 0x0 1. "CMDCRC,Command CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "CMDTEO,Command Timeout Error" "0,1"
|
|
line.word 0x2 "NISTER_EMMC_MODE,Normal Interrupt Status Enable Register"
|
|
bitfld.word 0x2 14. "BOOTAR,Boot Acknowledge Received Status Enable" "0: The BOOTAR status flag in SDMMC_NISTR is masked.,1: The BOOTAR status flag in SDMMC_NISTR is enabled."
|
|
bitfld.word 0x2 5. "BRDRDY,Buffer Read Ready Status Enable" "0: The BRDRDY status flag in SDMMC_NISTR is masked.,1: The BRDRDY status flag in SDMMC_NISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 4. "BWRRDY,Buffer Write Ready Status Enable" "0: The BWRRDY status flag in SDMMC_NISTR is masked.,1: The BWRRDY status flag in SDMMC_NISTR is enabled."
|
|
bitfld.word 0x2 3. "DMAINT,DMA Interrupt Status Enable" "0: The DMAINT status flag in SDMMC_NISTR is masked.,1: The DMAINT status flag in SDMMC_NISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 2. "BLKGE,Block Gap Event Status Enable" "0: The BLKGE status flag in SDMMC_NISTR is masked.,1: The BLKGE status flag in SDMMC_NISTR is enabled."
|
|
bitfld.word 0x2 1. "TRFC,Transfer Complete Status Enable" "0: The TRFC status flag in SDMMC_NISTR is masked.,1: The TRFC status flag in SDMMC_NISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 0. "CMDC,Command Complete Status Enable" "0: The CMDC status flag in SDMMC_NISTR is masked.,1: The CMDC status flag in SDMMC_NISTR is enabled."
|
|
group.word 0x34++0x3
|
|
line.word 0x0 "NISTER_SD_SDIO_MODE,Normal Interrupt Status Enable Register"
|
|
bitfld.word 0x0 8. "CINT,Card Interrupt Status Enable" "0: The CINT status flag in SDMMC_NISTR is masked.,1: The CINT status flag in SDMMC_NISTR is enabled."
|
|
bitfld.word 0x0 7. "CREM,Card Removal Status Enable" "0: The CREM status flag in SDMMC_NISTR is masked.,1: The CREM status flag in SDMMC_NISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 6. "CINS,Card Insertion Status Enable" "0: The CINS status flag in SDMMC_NISTR is masked.,1: The CINS status flag in SDMMC_NISTR is enabled."
|
|
bitfld.word 0x0 5. "BRDRDY,Buffer Read Ready Status Enable" "0: The BRDRDY status flag in SDMMC_NISTR is masked.,1: The BRDRDY status flag in SDMMC_NISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 4. "BWRRDY,Buffer Write Ready Status Enable" "0: The BWRRDY status flag in SDMMC_NISTR is masked.,1: The BWRRDY status flag in SDMMC_NISTR is enabled."
|
|
bitfld.word 0x0 3. "DMAINT,DMA Interrupt Status Enable" "0: The DMAINT status flag in SDMMC_NISTR is masked.,1: The DMAINT status flag in SDMMC_NISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 2. "BLKGE,Block Gap Event Status Enable" "0: The BLKGE status flag in SDMMC_NISTR is masked.,1: The BLKGE status flag in SDMMC_NISTR is enabled."
|
|
bitfld.word 0x0 1. "TRFC,Transfer Complete Status Enable" "0: The TRFC status flag in SDMMC_NISTR is masked.,1: The TRFC status flag in SDMMC_NISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 0. "CMDC,Command Complete Status Enable" "0: The CMDC status flag in SDMMC_NISTR is masked.,1: The CMDC status flag in SDMMC_NISTR is enabled."
|
|
line.word 0x2 "EISTER_EMMC_MODE,Error Interrupt Status Enable Register"
|
|
bitfld.word 0x2 12. "BOOTAE,Boot Acknowledge Error Status Enable" "0: The BOOTAE status flag in SDMMC_EISTR is masked.,1: The BOOTAE status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x2 10. "TUNING,Tuning Error Status Enable" "0: The TUNING status flag in SDMMC_EISTR is masked.,1: The TUNING status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 9. "ADMA,ADMA Error Status Enable" "0: The ADMA status flag in SDMMC_EISTR is masked.,1: The ADMA status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x2 8. "ACMD,Auto CMD Error Status Enable" "0: The ACMD status flag in SDMMC_EISTR is masked.,1: The ACMD status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 7. "CURLIM,Current Limit Error Status Enable" "0: The CURLIM status flag in SDMMC_EISTR is masked.,1: The CURLIM status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x2 6. "DATEND,Data End Bit Error Status Enable" "0: The DATEND status flag in SDMMC_EISTR is masked.,1: The DATEND status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 5. "DATCRC,Data CRC Error Status Enable" "0: The DATCRC status flag in SDMMC_EISTR is masked.,1: The DATCRC status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x2 4. "DATTEO,Data Timeout Error Status Enable" "0: The DATTEO status flag in SDMMC_EISTR is masked.,1: The DATTEO status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 3. "CMDIDX,Command Index Error Status Enable" "0: The CMDIDX status flag in SDMMC_EISTR is masked.,1: The CMDIDX status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x2 2. "CMDEND,Command End Bit Error Status Enable" "0: The CMDEND status flag in SDMMC_EISTR is masked.,1: The CMDEND status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 1. "CMDCRC,Command CRC Error Status Enable" "0: The CMDCRC status flag in SDMMC_EISTR is masked.,1: The CMDCRC status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x2 0. "CMDTEO,Command Timeout Error Status Enable" "0: The CMDTEO status flag in SDMMC_EISTR is masked.,1: The CMDTEO status flag in SDMMC_EISTR is enabled."
|
|
group.word 0x36++0x3
|
|
line.word 0x0 "EISTER_SD_SDIO_MODE,Error Interrupt Status Enable Register"
|
|
bitfld.word 0x0 10. "TUNING,Tuning Error Status Enable" "0: The TUNING status flag in SDMMC_EISTR is masked.,1: The TUNING status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x0 9. "ADMA,ADMA Error Status Enable" "0: The ADMA status flag in SDMMC_EISTR is masked.,1: The ADMA status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 8. "ACMD,Auto CMD Error Status Enable" "0: The ACMD status flag in SDMMC_EISTR is masked.,1: The ACMD status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x0 7. "CURLIM,Current Limit Error Status Enable" "0: The CURLIM status flag in SDMMC_EISTR is masked.,1: The CURLIM status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 6. "DATEND,Data End Bit Error Status Enable" "0: The DATEND status flag in SDMMC_EISTR is masked.,1: The DATEND status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x0 5. "DATCRC,Data CRC Error Status Enable" "0: The DATCRC status flag in SDMMC_EISTR is masked.,1: The DATCRC status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 4. "DATTEO,Data Timeout Error Status Enable" "0: The DATTEO status flag in SDMMC_EISTR is masked.,1: The DATTEO status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x0 3. "CMDIDX,Command Index Error Status Enable" "0: The CMDIDX status flag in SDMMC_EISTR is masked.,1: The CMDIDX status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 2. "CMDEND,Command End Bit Error Status Enable" "0: The CMDEND status flag in SDMMC_EISTR is masked.,1: The CMDEND status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x0 1. "CMDCRC,Command CRC Error Status Enable" "0: The CMDCRC status flag in SDMMC_EISTR is masked.,1: The CMDCRC status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 0. "CMDTEO,Command Timeout Error Status Enable" "0: The CMDTEO status flag in SDMMC_EISTR is masked.,1: The CMDTEO status flag in SDMMC_EISTR is enabled."
|
|
line.word 0x2 "NISIER_EMMC_MODE,Normal Interrupt Signal Enable Register"
|
|
bitfld.word 0x2 14. "BOOTAR,Boot Acknowledge Received Signal Enable" "0: No interrupt is generated when the BOOTAR status..,1: An interrupt is generated when the BOOTAR status.."
|
|
bitfld.word 0x2 5. "BRDRDY,Buffer Read Ready Signal Enable" "0: No interrupt is generated when the BRDRDY status..,1: An interrupt is generated when the BRDRDY status.."
|
|
newline
|
|
bitfld.word 0x2 4. "BWRRDY,Buffer Write Ready Signal Enable" "0: No interrupt is generated when the BWRRDY status..,1: An interrupt is generated when the BWRRDY status.."
|
|
bitfld.word 0x2 3. "DMAINT,DMA Interrupt Signal Enable" "0: No interrupt is generated when the DMAINT status..,1: An interrupt is generated when the DMAINT status.."
|
|
newline
|
|
bitfld.word 0x2 2. "BLKGE,Block Gap Event Signal Enable" "0: No interrupt is generated when the BLKGE status..,1: An interrupt is generated when the BLKGE status.."
|
|
bitfld.word 0x2 1. "TRFC,Transfer Complete Signal Enable" "0: No interrupt is generated when the TRFC status..,1: An interrupt is generated when the TRFC status.."
|
|
newline
|
|
bitfld.word 0x2 0. "CMDC,Command Complete Signal Enable" "0: No interrupt is generated when the CMDC status..,1: An interrupt is generated when the CMDC status.."
|
|
group.word 0x38++0x3
|
|
line.word 0x0 "NISIER_SD_SDIO_MODE,Normal Interrupt Signal Enable Register"
|
|
bitfld.word 0x0 8. "CINT,Card Interrupt Signal Enable" "0: No interrupt is generated when the CINT status..,1: An interrupt is generated when the CINT status.."
|
|
bitfld.word 0x0 7. "CREM,Card Removal Signal Enable" "0: No interrupt is generated when the CREM status..,1: An interrupt is generated when the CREM status.."
|
|
newline
|
|
bitfld.word 0x0 6. "CINS,Card Insertion Signal Enable" "0: No interrupt is generated when the CINS status..,1: An interrupt is generated when the CINS status.."
|
|
bitfld.word 0x0 5. "BRDRDY,Buffer Read Ready Signal Enable" "0: No interrupt is generated when the BRDRDY status..,1: An interrupt is generated when the BRDRDY status.."
|
|
newline
|
|
bitfld.word 0x0 4. "BWRRDY,Buffer Write Ready Signal Enable" "0: No interrupt is generated when the BWRRDY status..,1: An interrupt is generated when the BWRRDY status.."
|
|
bitfld.word 0x0 3. "DMAINT,DMA Interrupt Signal Enable" "0: No interrupt is generated when the DMAINT status..,1: An interrupt is generated when the DMAINT status.."
|
|
newline
|
|
bitfld.word 0x0 2. "BLKGE,Block Gap Event Signal Enable" "0: No interrupt is generated when the BLKGE status..,1: An interrupt is generated when the BLKGE status.."
|
|
bitfld.word 0x0 1. "TRFC,Transfer Complete Signal Enable" "0: No interrupt is generated when the TRFC status..,1: An interrupt is generated when the TRFC status.."
|
|
newline
|
|
bitfld.word 0x0 0. "CMDC,Command Complete Signal Enable" "0: No interrupt is generated when the CMDC status..,1: An interrupt is generated when the CMDC status.."
|
|
line.word 0x2 "EISIER_EMMC_MODE,Error Interrupt Signal Enable Register"
|
|
bitfld.word 0x2 12. "BOOTAE,Boot Acknowledge Error Signal Enable" "0: No interrupt is generated when the BOOTAE status..,1: An interrupt is generated when the BOOTAE status.."
|
|
bitfld.word 0x2 10. "TUNING,Tuning Error Signal Enable" "0: No interrupt is generated when the TUNING status..,1: An interrupt is generated when the TUNING status.."
|
|
newline
|
|
bitfld.word 0x2 9. "ADMA,ADMA Error Signal Enable" "0: No interrupt is generated when the ADMA status..,1: An interrupt is generated when the ADMA status.."
|
|
bitfld.word 0x2 8. "ACMD,Auto CMD Error Signal Enable" "0: No interrupt is generated when the ACMD status..,1: An interrupt is generated when the ACMD status.."
|
|
newline
|
|
bitfld.word 0x2 7. "CURLIM,Current Limit Error Signal Enable" "0: No interrupt is generated when the CURLIM status..,1: An interrupt is generated when the CURLIM status.."
|
|
bitfld.word 0x2 6. "DATEND,Data End Bit Error Signal Enable" "0: No interrupt is generated when the DATEND status..,1: An interrupt is generated when the DATEND status.."
|
|
newline
|
|
bitfld.word 0x2 5. "DATCRC,Data CRC Error Signal Enable" "0: No interrupt is generated when the DATCRC status..,1: An interrupt is generated when the DATCRC status.."
|
|
bitfld.word 0x2 4. "DATTEO,Data Timeout Error Signal Enable" "0: No interrupt is generated when the DATTEO status..,1: An interrupt is generated when the DATTEO status.."
|
|
newline
|
|
bitfld.word 0x2 3. "CMDIDX,Command Index Error Signal Enable" "0: No interrupt is generated when the CMDIDX status..,1: An interrupt is generated when the CMDIDX status.."
|
|
bitfld.word 0x2 2. "CMDEND,Command End Bit Error Signal Enable" "0: No interrupt is generated when the CMDEND status..,1: An interrupt is generated when the CMDEND status.."
|
|
newline
|
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bitfld.word 0x2 1. "CMDCRC,Command CRC Error Signal Enable" "0: No interrupt is generated when the CDMCRC status..,1: An interrupt is generated when the CMDCRC status.."
|
|
bitfld.word 0x2 0. "CMDTEO,Command Timeout Error Signal Enable" "0: No interrupt is generated when the CMDTEO status..,1: An interrupt is generated when the CMDTEO status.."
|
|
group.word 0x3A++0x1
|
|
line.word 0x0 "EISIER_SD_SDIO_MODE,Error Interrupt Signal Enable Register"
|
|
bitfld.word 0x0 10. "TUNING,Tuning Error Signal Enable" "0: No interrupt is generated when the TUNING status..,1: An interrupt is generated when the TUNING status.."
|
|
bitfld.word 0x0 9. "ADMA,ADMA Error Signal Enable" "0: No interrupt is generated when the ADMA status..,1: An interrupt is generated when the ADMA status.."
|
|
newline
|
|
bitfld.word 0x0 8. "ACMD,Auto CMD Error Signal Enable" "0: No interrupt is generated when the ACMD status..,1: An interrupt is generated when the ACMD status.."
|
|
bitfld.word 0x0 7. "CURLIM,Current Limit Error Signal Enable" "0: No interrupt is generated when the CURLIM status..,1: An interrupt is generated when the CURLIM status.."
|
|
newline
|
|
bitfld.word 0x0 6. "DATEND,Data End Bit Error Signal Enable" "0: No interrupt is generated when the DATEND status..,1: An interrupt is generated when the DATEND status.."
|
|
bitfld.word 0x0 5. "DATCRC,Data CRC Error Signal Enable" "0: No interrupt is generated when the DATCRC status..,1: An interrupt is generated when the DATCRC status.."
|
|
newline
|
|
bitfld.word 0x0 4. "DATTEO,Data Timeout Error Signal Enable" "0: No interrupt is generated when the DATTEO status..,1: An interrupt is generated when the DATTEO status.."
|
|
bitfld.word 0x0 3. "CMDIDX,Command Index Error Signal Enable" "0: No interrupt is generated when the CMDIDX status..,1: An interrupt is generated when the CMDIDX status.."
|
|
newline
|
|
bitfld.word 0x0 2. "CMDEND,Command End Bit Error Signal Enable" "0: No interrupt is generated when the CMDEND status..,1: An interrupt is generated when the CMDEND status.."
|
|
bitfld.word 0x0 1. "CMDCRC,Command CRC Error Signal Enable" "0: No interrupt is generated when the CDMCRC status..,1: An interrupt is generated when the CMDCRC status.."
|
|
newline
|
|
bitfld.word 0x0 0. "CMDTEO,Command Timeout Error Signal Enable" "0: No interrupt is generated when the CMDTEO status..,1: An interrupt is generated when the CMDTEO status.."
|
|
rgroup.word 0x3C++0x1
|
|
line.word 0x0 "ACESR,Auto CMD Error Status Register"
|
|
bitfld.word 0x0 7. "CMDNI,Command Not Issued by Auto CMD12 Error" "0: No error.,1: Error."
|
|
bitfld.word 0x0 4. "ACMDIDX,Auto CMD Index Error" "0: No error.,1: Error."
|
|
newline
|
|
bitfld.word 0x0 3. "ACMDEND,Auto CMD End Bit Error" "0: No error.,1: Error."
|
|
bitfld.word 0x0 2. "ACMDCRC,Auto CMD CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "ACMDTEO,Auto CMD Timeout Error" "0,1"
|
|
bitfld.word 0x0 0. "ACMD12NE,Auto CMD12 Not Executed" "0: No error.,1: Error."
|
|
group.word 0x3E++0x1
|
|
line.word 0x0 "HC2R_EMMC_MODE,Host Control 2 Register"
|
|
bitfld.word 0x0 15. "PVALEN,Preset Value Enable" "0: SDCLK and Driver strength are controlled by the..,1: Automatic selection by Preset Value is enabled."
|
|
bitfld.word 0x0 7. "SCLKSEL,Sampling Clock Select" "0: The fixed clock is used to sample data.,1: The tuned clock is used to sample data."
|
|
newline
|
|
bitfld.word 0x0 6. "EXTUN,Execute Tuning" "0: Not tuned or tuning completed,1: Execute tuning"
|
|
bitfld.word 0x0 4.--5. "DRVSEL,Driver Strength Select" "0: Driver Type B is selected (Default),1: Driver Type A is selected,2: Driver Type C is selected,3: Driver Type D is selected"
|
|
newline
|
|
hexmask.word.byte 0x0 0.--3. 1. "HS200EN,HS200 Mode Enable"
|
|
group.word 0x3E++0x1
|
|
line.word 0x0 "HC2R_SD_SDIO_MODE,Host Control 2 Register"
|
|
bitfld.word 0x0 15. "PVALEN,Preset Value Enable" "0: SDCLK and Driver strength are controlled by the..,1: Automatic selection by Preset Value is enabled."
|
|
bitfld.word 0x0 14. "ASINTEN,Asynchronous Interrupt Enable" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.word 0x0 7. "SCLKSEL,Sampling Clock Select" "0: The fixed clock is used to sample data.,1: The tuned clock is used to sample data."
|
|
bitfld.word 0x0 6. "EXTUN,Execute Tuning" "0: Not tuned or tuning completed.,1: Execute tuning."
|
|
newline
|
|
bitfld.word 0x0 4.--5. "DRVSEL,Driver Strength Select" "0: Driver Type B is selected (Default),1: Driver Type A is selected,2: Driver Type C is selected,3: Driver Type D is selected"
|
|
bitfld.word 0x0 3. "VS18EN,1.8V Signaling Enable" "0: 3.3V signaling.,1: 1.8V signaling."
|
|
newline
|
|
bitfld.word 0x0 0.--2. "UHSMS,UHS Mode Select" "0: UHS SDR12 Mode,1: UHS SDR25 Mode,2: UHS SDR50 Mode,3: UHS SDR104 Mode,4: UHS DDR50 Mode,?,?,?"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "CA0R,Capabilities 0 Register"
|
|
bitfld.long 0x0 30.--31. "SLTYPE,Slot Type" "0: Removable Card Slot,1: Embedded Slot for One Device,?,?"
|
|
bitfld.long 0x0 29. "ASINTSUP,Asynchronous Interrupt Support" "0: Asynchronous interrupt not supported.,1: Asynchronous interrupt supported."
|
|
newline
|
|
bitfld.long 0x0 28. "SB64SUP,64-Bit System Bus Support" "0: 64-bit address bus not supported.,1: 64-bit address bus supported."
|
|
bitfld.long 0x0 26. "V18VSUP,Voltage Support 1.8V" "0: 1.8V Voltage supply not supported.,1: 1.8V Voltage supply supported."
|
|
newline
|
|
bitfld.long 0x0 25. "V30VSUP,Voltage Support 3.0V" "0: 3.0V Voltage supply not supported.,1: 3.0V Voltage supply supported."
|
|
bitfld.long 0x0 24. "V33VSUP,Voltage Support 3.3V" "0: 3.3V Voltage supply not supported.,1: 3.3V Voltage supply supported."
|
|
newline
|
|
bitfld.long 0x0 23. "SRSUP,Suspend/Resume Support" "0: Suspend/Resume not supported.,1: Suspend/Resume supported."
|
|
bitfld.long 0x0 22. "SDMASUP,SDMA Support" "0: SDMA not supported.,1: SDMA supported."
|
|
newline
|
|
bitfld.long 0x0 21. "HSSUP,High Speed Support" "0: High Speed not supported.,1: High Speed supported."
|
|
bitfld.long 0x0 19. "ADMA2SUP,ADMA2 Support" "0: ADMA2 not supported.,1: ADMA2 supported."
|
|
newline
|
|
bitfld.long 0x0 18. "ED8SUP,8-Bit Support for Embedded Device" "0: 8-bit bus width not supported.,1: 8-bit bus width supported."
|
|
bitfld.long 0x0 16.--17. "MAXBLKL,Max Block Length" "0: 512 bytes,1: 1024 bytes,2: 2048 bytes,?"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "BASECLKF,Base Clock Frequency"
|
|
bitfld.long 0x0 7. "TEOCLKU,Timeout Clock Unit" "0: KHz,1: MHz"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TEOCLKF,Timeout Clock Frequency"
|
|
line.long 0x4 "CA1R,Capabilities 1 Register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "CLKMULT,Clock Multiplier"
|
|
bitfld.long 0x4 14.--15. "RTMOD,Retuning Modes" "0: Timer,1: Timer and Retuning Request,2: Auto Retuning (for transfer) Timer and Retuning..,?"
|
|
newline
|
|
bitfld.long 0x4 13. "TSDR50,Use Tuning for SDR50" "0: SDR50 does not require tuning.,1: SDR50 requires tuning."
|
|
hexmask.long.byte 0x4 8.--11. 1. "TCNTRT,Timer Count For Retuning"
|
|
newline
|
|
bitfld.long 0x4 6. "DRVDSUP,Driver Type D Support" "0: Driver type D is not supported.,1: Driver type D is supported."
|
|
bitfld.long 0x4 5. "DRVCSUP,Driver Type C Support" "0: Driver type C is not supported.,1: Driver type C is supported."
|
|
newline
|
|
bitfld.long 0x4 4. "DRVASUP,Driver Type A Support" "0: Driver type A is not supported.,1: Driver type A is supported."
|
|
bitfld.long 0x4 2. "DDR50SUP,DDR50 Support" "0: DDR50 mode is not supported.,1: DDR50 mode is supported."
|
|
newline
|
|
bitfld.long 0x4 1. "SDR104SUP,SDR104 Support" "0: SDR104 mode is not supported.,1: SDR104 mode is supported."
|
|
bitfld.long 0x4 0. "SDR50SUP,SDR50 Support" "0: SDR50 mode is not supported.,1: SDR50 mode is supported."
|
|
line.long 0x8 "MCCAR,Maximum Current Capabilities Register"
|
|
hexmask.long.byte 0x8 16.--23. 1. "MAXCUR18V,Maximum Current for 1.8V"
|
|
hexmask.long.byte 0x8 8.--15. 1. "MAXCUR30V,Maximum Current for 3.0V"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "MAXCUR33V,Maximum Current for 3.3V"
|
|
wgroup.word 0x50++0x3
|
|
line.word 0x0 "FERACES,Force Event Register for Auto CMD Error Status"
|
|
bitfld.word 0x0 7. "CMDNI,Force Event for Command Not Issued by Auto CMD12 Error" "0,1"
|
|
bitfld.word 0x0 4. "ACMDIDX,Force Event for Auto CMD Index Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "ACMDEND,Force Event for Auto CMD End Bit Error" "0,1"
|
|
bitfld.word 0x0 2. "ACMDCRC,Force Event for Auto CMD CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "ACMDTEO,Force Event for Auto CMD Timeout Error" "0,1"
|
|
bitfld.word 0x0 0. "ACMD12NE,Force Event for Auto CMD12 Not Executed" "0,1"
|
|
line.word 0x2 "FEREIS,Force Event Register for Error Interrupt Status"
|
|
bitfld.word 0x2 12. "BOOTAE,Force Event for Boot Acknowledge Error" "0,1"
|
|
bitfld.word 0x2 9. "ADMA,Force Event for ADMA Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 8. "ACMD,Force Event for Auto CMD Error" "0,1"
|
|
bitfld.word 0x2 7. "CURLIM,Force Event for Current Limit Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 6. "DATEND,Force Event for Data End Bit Error" "0,1"
|
|
bitfld.word 0x2 5. "DATCRC,Force Event for Data CRC error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 4. "DATTEO,Force Event for Data Timeout error" "0,1"
|
|
bitfld.word 0x2 3. "CMDIDX,Force Event for Command Index Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 2. "CMDEND,Force Event for Command End Bit Error" "0,1"
|
|
bitfld.word 0x2 1. "CMDCRC,Force Event for Command CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 0. "CMDTEO,Force Event for Command Timeout Error" "0,1"
|
|
rgroup.byte 0x54++0x0
|
|
line.byte 0x0 "AESR,ADMA Error Status Register"
|
|
bitfld.byte 0x0 2. "LMIS,ADMA Length Mismatch Error" "0: No error.,1: Error."
|
|
bitfld.byte 0x0 0.--1. "ERRST,ADMA Error State" "0: (Stop DMA) SDMMC_ASAR points to the descriptor..,1: (Fetch Descriptor) SDMMC_ASAR points to the..,?,3: (Transfer Data) SDMMC_ASAR points to the.."
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "ASAR0,ADMA System Address Register 0"
|
|
hexmask.long 0x0 0.--31. 1. "ADMASA,ADMA System Address"
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x60)++0x1
|
|
line.word 0x0 "PVR[$1],Preset Value Register x (for initialization)"
|
|
bitfld.word 0x0 14.--15. "DRVSEL,Driver Strength Select" "0,1,2,3"
|
|
bitfld.word 0x0 10. "CLKGSEL,Clock Generator Select" "0,1"
|
|
newline
|
|
hexmask.word 0x0 0.--9. 1. "SDCLKFSEL,SDCLK Frequency Select"
|
|
repeat.end
|
|
rgroup.word 0xFC++0x3
|
|
line.word 0x0 "SISR,Slot Interrupt Status Register"
|
|
bitfld.word 0x0 0.--2. "INTSSL,Interrupt Signal for Each Slot" "0,1,2,3,4,5,6,7"
|
|
line.word 0x2 "HCVR,Host Controller Version Register"
|
|
hexmask.word.byte 0x2 8.--15. 1. "VVER,Vendor Version Number"
|
|
hexmask.word.byte 0x2 0.--7. 1. "SVER,Specification Version Number"
|
|
rgroup.long 0x200++0x3
|
|
line.long 0x0 "APSR,Additional Present State Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "HDATLL,DAT[7:4] High Line Level"
|
|
group.byte 0x204++0x0
|
|
line.byte 0x0 "MC1R,e.MMC Control 1 Register"
|
|
bitfld.byte 0x0 7. "FCD,e.MMC Force Card Detect" "0: E.MMC Forced Card Detect is disabled. The..,1: E.MMC Forced Card Detect is enabled."
|
|
bitfld.byte 0x0 6. "RSTN,e.MMC Reset Signal" "0: Reset signal is inactive.,1: Reset signal is active."
|
|
newline
|
|
bitfld.byte 0x0 5. "BOOTA,e.MMC Boot Acknowledge Enable" "0,1"
|
|
bitfld.byte 0x0 4. "OPD,e.MMC Open Drain Mode" "0: The command line is in push-pull.,1: The command line is in open drain."
|
|
newline
|
|
bitfld.byte 0x0 3. "DDR,e.MMC HSDDR Mode" "0: High Speed DDR is not selected.,1: High Speed DDR is selected."
|
|
bitfld.byte 0x0 0.--1. "CMDTYP,e.MMC Command Type" "0: The command is not an e.MMC specific command.,1: This bit must be set to 1 when the e.MMC is in..,2: This bit must be set to 1 in the case of Stream..,3: Starts a Boot Operation mode at the next write.."
|
|
wgroup.byte 0x205++0x0
|
|
line.byte 0x0 "MC2R,e.MMC Control 2 Register"
|
|
bitfld.byte 0x0 1. "ABOOT,e.MMC Abort Boot" "0,1"
|
|
bitfld.byte 0x0 0. "SRESP,e.MMC Abort Wait IRQ" "0,1"
|
|
group.byte 0x206++0x1
|
|
line.byte 0x0 "MC3R,e.MMC Control 3 Register"
|
|
bitfld.byte 0x0 3.--5. "DQSUPVAL,DQS Delay Update Timer Value" "0: DQS delay update is performed each time a..,?,?,?,?,?,?,?"
|
|
bitfld.byte 0x0 1. "ESMEN,Enhanced Strobe Mode Enable" "0: Enhanced Strobe mode is disabled.,1: Enhanced Strobe mode is enabled."
|
|
newline
|
|
bitfld.byte 0x0 0. "HS400EN,HS400 Mode Enable" "0: HS400 mode is disabled.,1: HS400 mode is enabled."
|
|
line.byte 0x1 "DEBR,Debounce Register"
|
|
bitfld.byte 0x1 0.--1. "CDDVAL,Card Detect Debounce Value" "0,1,2,3"
|
|
group.long 0x208++0x7
|
|
line.long 0x0 "ACR,AHB Control Register"
|
|
hexmask.long.byte 0x0 12.--15. 1. "DFQOS,Descriptor Fetch QOS"
|
|
bitfld.long 0x0 8.--9. "BUFM,AHB Bufferable Mode" "0: All SDMA/ADMA AHB accesses are not bufferable.,1: All SDMA/ADMA AHB accesses are bufferable.,2: All SDMA/ADMA AHB accesses are bufferable except..,3: All SDMA/ADMA AHB accesses are bufferable except.."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "BMAX,AHB Maximum Burst" "0: The maximum burst size is INCR16.,1: The maximum burst size is INCR8.,2: The maximum burst size is INCR4.,3: Only SINGLE transfers are performed."
|
|
line.long 0x4 "CC2R,Clock Control 2 Register"
|
|
bitfld.long 0x4 0. "FSDCLKD,Force SDCLK Disabled" "0: The SDCLK is forced and it cannot be stopped..,1: The SDCLK is not forced and it can be stopped.."
|
|
group.byte 0x210++0x0
|
|
line.byte 0x0 "RTC1R,Retuning Timer Control 1 Register"
|
|
bitfld.byte 0x0 0. "TMREN,Retuning Timer Enable" "0: The retuning timer is disabled.,1: The retuning timer is enabled."
|
|
wgroup.byte 0x211++0x0
|
|
line.byte 0x0 "RTC2R,Retuning Timer Control 2 Register"
|
|
bitfld.byte 0x0 0. "RLD,Retuning Timer Reload" "0,1"
|
|
group.long 0x214++0x3
|
|
line.long 0x0 "RTCVR,Retuning Timer Counter Value Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TCVAL,Retuning Timer Counter Value"
|
|
group.byte 0x218++0x1
|
|
line.byte 0x0 "RTISTER,Retuning Timer Interrupt Status Enable Register"
|
|
bitfld.byte 0x0 0. "TEVT,Retuning Timer Event" "0: The TEVT status flag in SDMMC_RTISTR is masked.,1: The TEVT status flag in SDMMC_RTISTR is enabled."
|
|
line.byte 0x1 "RTISIER,Retuning Timer Interrupt Signal Enable Register"
|
|
bitfld.byte 0x1 0. "TEVT,Retuning Timer Event" "0: No interrupt is generated when the TEVT status..,1: An interrupt is generated when the TEVT status.."
|
|
group.byte 0x21C++0x0
|
|
line.byte 0x0 "RTISTR,Retuning Timer Interrupt Status Register"
|
|
bitfld.byte 0x0 0. "TEVT,Retuning Timer Event" "0: No retuning timer event.,1: Retuning timer event."
|
|
rgroup.byte 0x21D++0x0
|
|
line.byte 0x0 "RTSSR,Retuning Timer Status Slots Register"
|
|
bitfld.byte 0x0 0.--2. "TEVTSLOT,Retuning Timer Event Slots" "0,1,2,3,4,5,6,7"
|
|
group.long 0x220++0x3
|
|
line.long 0x0 "TUNCR,Tuning Control Register"
|
|
bitfld.long 0x0 0. "SMPLPT,Sampling Point" "0: Sampling point is set at 50% of the data window.,1: Sampling point is set at 75% of the data window."
|
|
group.long 0x230++0x7
|
|
line.long 0x0 "CACR,Capabilities Control Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "KEY,Key"
|
|
bitfld.long 0x0 0. "CAPWREN,Capabilities Write Enable" "0: Capabilities registers (SDMMC_CA0R SDMMC_CA1R..,1: Capabilities registers (SDMMC_CA0R SDMMC_CA1R.."
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|
line.long 0x4 "DBGR,Debug Register"
|
|
bitfld.long 0x4 0. "NIDBG,Nonintrusive Debug" "0: Reading the SDMMC_BDPR via debugger increments..,1: Reading the SDMMC_BDPR via debugger does not.."
|
|
group.long 0x240++0x3
|
|
line.long 0x0 "CALCR,Calibration Control Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "CALPBP,Calibration PBypass value"
|
|
hexmask.long.byte 0x0 24.--27. 1. "CALP,Calibration P Status"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "CALNBP,Calibration N Bypass value"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CALN,Calibration N Status"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CNTVAL,Calibration Counter Value"
|
|
bitfld.long 0x0 6. "BPEN,Calibration Bypass Enabled" "0: Calibration bypass is not enabled.,1: Calibration bypass is enabled. CALPBP and CALNBP.."
|
|
newline
|
|
bitfld.long 0x0 5. "TUNDIS,Calibration During Tuning Disabled" "0: Calibration is launched before each tuning.,1: Calibration is not launched at tuning."
|
|
bitfld.long 0x0 4. "ALWYSON,Calibration Analog Always ON" "0: Calibration analog is shut down after each..,1: Calibration analog remains powered after.."
|
|
newline
|
|
bitfld.long 0x0 1.--3. "CLKDIV,Calibration Clock Division" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0. "EN,PADs Calibration Enable" "0: SDMMC I/O calibration disabled.,1: SDMMC I/O calibration enabled."
|
|
group.word 0x244++0x1
|
|
line.word 0x0 "EPVR8,Extended Preset Value Register 8(for HS400)"
|
|
bitfld.word 0x0 14.--15. "DRVSEL,Driver Strength Select" "0,1,2,3"
|
|
bitfld.word 0x0 10. "CLKGSEL,Clock Generator Select" "0,1"
|
|
newline
|
|
hexmask.word 0x0 0.--9. 1. "SDCLKFSEL,SDCLK Frequency Select"
|
|
tree.end
|
|
tree "SDMMC1"
|
|
base ad:0xE1208000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "SSAR,SDMA System Address / Argument 2 Register"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,SDMA System Address"
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "SSAR_CMD23_MODE,SDMA System Address / Argument 2 Register"
|
|
hexmask.long 0x0 0.--31. 1. "ARG2,Argument 2"
|
|
group.word 0x4++0x3
|
|
line.word 0x0 "BSR,Block Size Register"
|
|
bitfld.word 0x0 12.--14. "BOUNDARY,SDMA Buffer Boundary" "0: 4-Kbyte boundary,1: 8-Kbyte boundary,2: 16-Kbyte boundary,3: 32-Kbyte boundary,4: 64-Kbyte boundary,5: 128-Kbyte boundary,6: 256-Kbyte boundary,7: 512-Kbyte boundary"
|
|
hexmask.word 0x0 0.--9. 1. "BLKSIZE,Transfer Block Size"
|
|
line.word 0x2 "BCR,Block Count Register"
|
|
hexmask.word 0x2 0.--15. 1. "BLKCNT,Block Count for Current Transfer"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "ARG1R,Argument 1 Register"
|
|
hexmask.long 0x0 0.--31. 1. "ARG1,Argument 1"
|
|
group.word 0xC++0x3
|
|
line.word 0x0 "TMR,Transfer Mode Register"
|
|
bitfld.word 0x0 5. "MSBSEL,Multi/Single Block Selection" "0,1"
|
|
bitfld.word 0x0 4. "DTDSEL,Data Transfer Direction Selection" "0: Writes data from the SDMMC to the device.,1: Reads data from the device to the SDMMC."
|
|
newline
|
|
bitfld.word 0x0 2.--3. "ACMDEN,Auto Command Enable" "0: Auto Command Disabled,1: Auto CMD12 Enabled,2: Auto CMD23 Enabled,?"
|
|
bitfld.word 0x0 1. "BCEN,Block Count Enable" "0: Block count is disabled.,1: Block count is enabled."
|
|
newline
|
|
bitfld.word 0x0 0. "DMAEN,DMA Enable" "0: DMA functionality is disabled.,1: DMA functionality is enabled."
|
|
line.word 0x2 "CR,Command Register"
|
|
hexmask.word.byte 0x2 8.--13. 1. "CMDIDX,Command Index"
|
|
bitfld.word 0x2 6.--7. "CMDTYP,Command Type" "0: Other commands,1: CMD52 to write 'Bus Suspend' in the Card Common..,2: CMD52 to write 'Function Select' in the Card..,3: CMD12 CMD52 to write 'I/O Abort' in the Card.."
|
|
newline
|
|
bitfld.word 0x2 5. "DPSEL,Data Present Select" "0: No data present,1: Data present"
|
|
bitfld.word 0x2 4. "CMDICEN,Command Index Check Enable" "0: The Command Index Check is disabled.,1: The Command Index Check is enabled."
|
|
newline
|
|
bitfld.word 0x2 3. "CMDCCEN,Command CRC Check Enable" "0: The Command CRC Check is disabled.,1: The Command CRC Check is enabled."
|
|
bitfld.word 0x2 0.--1. "RESPTYP,Response Type" "0: No Response,1: Response Length 136,2: Response Length 48,3: Response Length 48 with Busy"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x10)++0x3
|
|
line.long 0x0 "RR[$1],Response Register x"
|
|
hexmask.long 0x0 0.--31. 1. "CMDRESP,Command Response"
|
|
repeat.end
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "BDPR,Buffer Data Port Register"
|
|
hexmask.long 0x0 0.--31. 1. "BUFDATA,Buffer Data"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "PSR,Present State Register"
|
|
bitfld.long 0x0 24. "CMDLL,CMD Line Level" "0,1"
|
|
hexmask.long.byte 0x0 20.--23. 1. "DATLL,DAT[3:0] Line Level"
|
|
newline
|
|
bitfld.long 0x0 19. "WRPPL,Write Protect Pin Level" "0: Write protected (SDMMC_WP = 0),1: Write enabled (SDMMC_WP = 1)"
|
|
bitfld.long 0x0 18. "CARDDPL,Card Detect Pin Level" "0: No card present (SDMMC_CD = 1).,1: Card present (SDMMC_CD = 0)."
|
|
newline
|
|
bitfld.long 0x0 17. "CARDSS,Card State Stable" "0: Reset or debouncing.,1: No card or card inserted."
|
|
bitfld.long 0x0 16. "CARDINS,Card Inserted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "BUFRDEN,Buffer Read Enable" "0,1"
|
|
bitfld.long 0x0 10. "BUFWREN,Buffer Write Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RTACT,Read Transfer Active" "0,1"
|
|
bitfld.long 0x0 8. "WTACT,Write Transfer Active" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DLACT,DAT Line Active" "0: DAT line inactive.,1: DAT line active."
|
|
bitfld.long 0x0 1. "CMDINHD,Command Inhibit (DAT)" "0: Can issue a command which uses the DAT line(s).,1: Cannot issue a command which uses the DAT line(s)."
|
|
newline
|
|
bitfld.long 0x0 0. "CMDINHC,Command Inhibit (CMD)" "0: Can issue a command using only CMD line.,1: Cannot issue a command."
|
|
group.byte 0x28++0x0
|
|
line.byte 0x0 "HC1R_EMMC_MODE,Host Control 1 Register"
|
|
bitfld.byte 0x0 5. "EXTDW,Extended Data Width" "0,1"
|
|
bitfld.byte 0x0 3.--4. "DMASEL,DMA Select" "0: SDMA is selected,?,2: 32-bit Address ADMA2 is selected,?"
|
|
newline
|
|
bitfld.byte 0x0 2. "HSEN,High Speed Enable" "0: Normal Speed mode.,1: High Speed mode."
|
|
bitfld.byte 0x0 1. "DW,Data Width" "0: 1-bit mode.,1: 4-bit mode."
|
|
group.byte 0x28++0x2
|
|
line.byte 0x0 "HC1R_SD_SDIO_MODE,Host Control 1 Register"
|
|
bitfld.byte 0x0 7. "CARDDSEL,Card Detect Signal Selection" "0: The SDMMC_CD pin is selected.,1: The Card Detect Test Level (CARDDTL) is selected.."
|
|
bitfld.byte 0x0 6. "CARDDTL,Card Detect Test Level" "0: No card.,1: Card inserted."
|
|
newline
|
|
bitfld.byte 0x0 3.--4. "DMASEL,DMA Select" "0: SDMA is selected,?,2: 32-bit Address ADMA2 is selected,?"
|
|
bitfld.byte 0x0 2. "HSEN,High Speed Enable" "0: Normal Speed mode.,1: High Speed mode."
|
|
newline
|
|
bitfld.byte 0x0 1. "DW,Data Width" "0: 1-bit mode.,1: 4-bit mode."
|
|
bitfld.byte 0x0 0. "LEDCTRL,LED Control" "0: LED off.,1: LED on."
|
|
line.byte 0x1 "PCR,Power Control Register"
|
|
bitfld.byte 0x1 0. "SDBPWR,SD Bus Power" "0,1"
|
|
line.byte 0x2 "BGCR_EMMC_MODE,Block Gap Control Register"
|
|
bitfld.byte 0x2 1. "CONTR,Continue Request" "0: No effect.,1: Restart."
|
|
bitfld.byte 0x2 0. "STPBGR,Stop At Block Gap Request" "0: Transfer,1: Stop"
|
|
group.byte 0x2A++0x1
|
|
line.byte 0x0 "BGCR_SD_SDIO_MODE,Block Gap Control Register"
|
|
bitfld.byte 0x0 3. "INTBG,Interrupt at Block Gap" "0: Interrupt detection disabled.,1: Interrupt detection enabled."
|
|
bitfld.byte 0x0 2. "RWCTRL,Read Wait Control" "0: Disables Read Wait control.,1: Enables Read Wait control."
|
|
newline
|
|
bitfld.byte 0x0 1. "CONTR,Continue Request" "0: No effect.,1: Restart."
|
|
bitfld.byte 0x0 0. "STPBGR,Stop At Block Gap Request" "0: Transfer,1: Stop"
|
|
line.byte 0x1 "WCR,Wakeup Control Register"
|
|
bitfld.byte 0x1 2. "WKENCREM,Wakeup Event Enable on Card Removal" "0: Wakeup Event disabled.,1: Wakeup Event enabled."
|
|
bitfld.byte 0x1 1. "WKENCINS,Wakeup Event Enable on Card Insertion" "0: Wakeup Event disabled.,1: Wakeup Event enabled."
|
|
newline
|
|
bitfld.byte 0x1 0. "WKENCINT,Wakeup Event Enable on Card Interrupt" "0: Wakeup Event disabled.,1: Wakeup Event enabled."
|
|
group.word 0x2C++0x1
|
|
line.word 0x0 "CCR,Clock Control Register"
|
|
hexmask.word.byte 0x0 8.--15. 1. "SDCLKFSEL,SDCLK Frequency Select"
|
|
bitfld.word 0x0 6.--7. "USDCLKFSEL,Upper Bits of SDCLK Frequency Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 5. "CLKGSEL,Clock Generator Select" "0: Divided Clock mode (BASECLK is used to generate..,1: Programmable Clock mode (MULTCLK is used to.."
|
|
bitfld.word 0x0 2. "SDCLKEN,SD Clock Enable" "0: SD Clock disabled,1: SD Clock enabled"
|
|
newline
|
|
bitfld.word 0x0 1. "INTCLKS,Internal Clock Stable" "0: Internal clock not ready.,1: Internal clock ready."
|
|
bitfld.word 0x0 0. "INTCLKEN,Internal Clock Enable" "0: The internal clock stops.,1: The internal clock oscillates."
|
|
group.byte 0x2E++0x1
|
|
line.byte 0x0 "TCR,Timeout Control Register"
|
|
hexmask.byte 0x0 0.--3. 1. "DTCVAL,Data Timeout Counter Value"
|
|
line.byte 0x1 "SRR,Software Reset Register"
|
|
bitfld.byte 0x1 2. "SWRSTDAT,Software reset for DAT line" "0: Work,1: Reset"
|
|
bitfld.byte 0x1 1. "SWRSTCMD,Software reset for CMD line" "0: Work,1: Reset"
|
|
newline
|
|
bitfld.byte 0x1 0. "SWRSTALL,Software reset for All" "0: Work,1: Reset"
|
|
group.word 0x30++0x1
|
|
line.word 0x0 "NISTR_EMMC_MODE,Normal Interrupt Status Register"
|
|
bitfld.word 0x0 15. "ERRINT,Error Interrupt" "0: No error.,1: Error."
|
|
bitfld.word 0x0 14. "BOOTAR,Boot Acknowledge Received" "0: Boot Acknowledge pattern not received.,1: Boot Acknowledge pattern received."
|
|
newline
|
|
bitfld.word 0x0 5. "BRDRDY,Buffer Read Ready" "0: Not ready to read buffer.,1: Ready to read buffer."
|
|
bitfld.word 0x0 4. "BWRRDY,Buffer Write Ready" "0: Not ready to write buffer.,1: Ready to write buffer."
|
|
newline
|
|
bitfld.word 0x0 3. "DMAINT,DMA Interrupt" "0: No DMA interrupt.,1: DMA interrupt."
|
|
bitfld.word 0x0 2. "BLKGE,Block Gap Event" "0: No block gap event.,1: Transaction stopped at block gap."
|
|
newline
|
|
bitfld.word 0x0 1. "TRFC,Transfer Complete" "0: Command execution is not complete.,1: Command execution is complete."
|
|
bitfld.word 0x0 0. "CMDC,Command Complete" "0: No command complete.,1: Command complete."
|
|
group.word 0x30++0x3
|
|
line.word 0x0 "NISTR_SD_SDIO_MODE,Normal Interrupt Status Register"
|
|
bitfld.word 0x0 15. "ERRINT,Error Interrupt" "0: No error.,1: Error."
|
|
bitfld.word 0x0 8. "CINT,Card Interrupt" "0: No card interrupt.,1: Card interrupt."
|
|
newline
|
|
bitfld.word 0x0 7. "CREM,Card Removal" "0: Card state unstable or card inserted.,1: Card removed."
|
|
bitfld.word 0x0 6. "CINS,Card Insertion" "0: Card state unstable or card removed.,1: Card inserted."
|
|
newline
|
|
bitfld.word 0x0 5. "BRDRDY,Buffer Read Ready" "0: Not ready to read buffer.,1: Ready to read buffer."
|
|
bitfld.word 0x0 4. "BWRRDY,Buffer Write Ready" "0: Not ready to write buffer.,1: Ready to write buffer."
|
|
newline
|
|
bitfld.word 0x0 3. "DMAINT,DMA Interrupt" "0: No DMA Interrupt.,1: DMA Interrupt."
|
|
bitfld.word 0x0 2. "BLKGE,Block Gap Event" "0: No block gap event.,1: Transaction stopped at block gap."
|
|
newline
|
|
bitfld.word 0x0 1. "TRFC,Transfer Complete" "0: Command execution is not complete.,1: Command execution is complete."
|
|
bitfld.word 0x0 0. "CMDC,Command Complete" "0: No command complete.,1: Command complete."
|
|
line.word 0x2 "EISTR_EMMC_MODE,Error Interrupt Status Register"
|
|
bitfld.word 0x2 12. "BOOTAE,Boot Acknowledge Error" "0: No error.,1: Error."
|
|
bitfld.word 0x2 10. "TUNING,Tuning Error" "0: No error.,1: Error."
|
|
newline
|
|
bitfld.word 0x2 9. "ADMA,ADMA Error" "0: No error.,1: Error."
|
|
bitfld.word 0x2 8. "ACMD,Auto CMD Error" "0: No error.,1: Error."
|
|
newline
|
|
bitfld.word 0x2 7. "CURLIM,Current Limit Error" "0: No error.,1: Error."
|
|
bitfld.word 0x2 6. "DATEND,Data End Bit Error" "0: No error.,1: Error."
|
|
newline
|
|
bitfld.word 0x2 5. "DATCRC,Data CRC Error" "0: No error.,1: Error."
|
|
bitfld.word 0x2 4. "DATTEO,Data Timeout error" "0: No error.,1: Error."
|
|
newline
|
|
bitfld.word 0x2 3. "CMDIDX,Command Index Error" "0: No error.,1: Error."
|
|
bitfld.word 0x2 2. "CMDEND,Command End Bit Error" "0: No error.,1: Error."
|
|
newline
|
|
bitfld.word 0x2 1. "CMDCRC,Command CRC Error" "0,1"
|
|
bitfld.word 0x2 0. "CMDTEO,Command Timeout Error" "0,1"
|
|
group.word 0x32++0x3
|
|
line.word 0x0 "EISTR_SD_SDIO_MODE,Error Interrupt Status Register"
|
|
bitfld.word 0x0 10. "TUNING,Tuning Error" "0: No error.,1: Error."
|
|
bitfld.word 0x0 9. "ADMA,ADMA Error" "0: No error.,1: Error."
|
|
newline
|
|
bitfld.word 0x0 8. "ACMD,Auto CMD Error" "0: No error.,1: Error."
|
|
bitfld.word 0x0 7. "CURLIM,Current Limit Error" "0: No error.,1: Error."
|
|
newline
|
|
bitfld.word 0x0 6. "DATEND,Data End Bit Error" "0: No error.,1: Error."
|
|
bitfld.word 0x0 5. "DATCRC,Data CRC error" "0: No error.,1: Error."
|
|
newline
|
|
bitfld.word 0x0 4. "DATTEO,Data Timeout Error" "0: No error.,1: Error."
|
|
bitfld.word 0x0 3. "CMDIDX,Command Index Error" "0: No error.,1: Error."
|
|
newline
|
|
bitfld.word 0x0 2. "CMDEND,Command End Bit Error" "0: No error.,1: Error."
|
|
bitfld.word 0x0 1. "CMDCRC,Command CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "CMDTEO,Command Timeout Error" "0,1"
|
|
line.word 0x2 "NISTER_EMMC_MODE,Normal Interrupt Status Enable Register"
|
|
bitfld.word 0x2 14. "BOOTAR,Boot Acknowledge Received Status Enable" "0: The BOOTAR status flag in SDMMC_NISTR is masked.,1: The BOOTAR status flag in SDMMC_NISTR is enabled."
|
|
bitfld.word 0x2 5. "BRDRDY,Buffer Read Ready Status Enable" "0: The BRDRDY status flag in SDMMC_NISTR is masked.,1: The BRDRDY status flag in SDMMC_NISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 4. "BWRRDY,Buffer Write Ready Status Enable" "0: The BWRRDY status flag in SDMMC_NISTR is masked.,1: The BWRRDY status flag in SDMMC_NISTR is enabled."
|
|
bitfld.word 0x2 3. "DMAINT,DMA Interrupt Status Enable" "0: The DMAINT status flag in SDMMC_NISTR is masked.,1: The DMAINT status flag in SDMMC_NISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 2. "BLKGE,Block Gap Event Status Enable" "0: The BLKGE status flag in SDMMC_NISTR is masked.,1: The BLKGE status flag in SDMMC_NISTR is enabled."
|
|
bitfld.word 0x2 1. "TRFC,Transfer Complete Status Enable" "0: The TRFC status flag in SDMMC_NISTR is masked.,1: The TRFC status flag in SDMMC_NISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 0. "CMDC,Command Complete Status Enable" "0: The CMDC status flag in SDMMC_NISTR is masked.,1: The CMDC status flag in SDMMC_NISTR is enabled."
|
|
group.word 0x34++0x3
|
|
line.word 0x0 "NISTER_SD_SDIO_MODE,Normal Interrupt Status Enable Register"
|
|
bitfld.word 0x0 8. "CINT,Card Interrupt Status Enable" "0: The CINT status flag in SDMMC_NISTR is masked.,1: The CINT status flag in SDMMC_NISTR is enabled."
|
|
bitfld.word 0x0 7. "CREM,Card Removal Status Enable" "0: The CREM status flag in SDMMC_NISTR is masked.,1: The CREM status flag in SDMMC_NISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 6. "CINS,Card Insertion Status Enable" "0: The CINS status flag in SDMMC_NISTR is masked.,1: The CINS status flag in SDMMC_NISTR is enabled."
|
|
bitfld.word 0x0 5. "BRDRDY,Buffer Read Ready Status Enable" "0: The BRDRDY status flag in SDMMC_NISTR is masked.,1: The BRDRDY status flag in SDMMC_NISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 4. "BWRRDY,Buffer Write Ready Status Enable" "0: The BWRRDY status flag in SDMMC_NISTR is masked.,1: The BWRRDY status flag in SDMMC_NISTR is enabled."
|
|
bitfld.word 0x0 3. "DMAINT,DMA Interrupt Status Enable" "0: The DMAINT status flag in SDMMC_NISTR is masked.,1: The DMAINT status flag in SDMMC_NISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 2. "BLKGE,Block Gap Event Status Enable" "0: The BLKGE status flag in SDMMC_NISTR is masked.,1: The BLKGE status flag in SDMMC_NISTR is enabled."
|
|
bitfld.word 0x0 1. "TRFC,Transfer Complete Status Enable" "0: The TRFC status flag in SDMMC_NISTR is masked.,1: The TRFC status flag in SDMMC_NISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 0. "CMDC,Command Complete Status Enable" "0: The CMDC status flag in SDMMC_NISTR is masked.,1: The CMDC status flag in SDMMC_NISTR is enabled."
|
|
line.word 0x2 "EISTER_EMMC_MODE,Error Interrupt Status Enable Register"
|
|
bitfld.word 0x2 12. "BOOTAE,Boot Acknowledge Error Status Enable" "0: The BOOTAE status flag in SDMMC_EISTR is masked.,1: The BOOTAE status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x2 10. "TUNING,Tuning Error Status Enable" "0: The TUNING status flag in SDMMC_EISTR is masked.,1: The TUNING status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 9. "ADMA,ADMA Error Status Enable" "0: The ADMA status flag in SDMMC_EISTR is masked.,1: The ADMA status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x2 8. "ACMD,Auto CMD Error Status Enable" "0: The ACMD status flag in SDMMC_EISTR is masked.,1: The ACMD status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 7. "CURLIM,Current Limit Error Status Enable" "0: The CURLIM status flag in SDMMC_EISTR is masked.,1: The CURLIM status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x2 6. "DATEND,Data End Bit Error Status Enable" "0: The DATEND status flag in SDMMC_EISTR is masked.,1: The DATEND status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 5. "DATCRC,Data CRC Error Status Enable" "0: The DATCRC status flag in SDMMC_EISTR is masked.,1: The DATCRC status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x2 4. "DATTEO,Data Timeout Error Status Enable" "0: The DATTEO status flag in SDMMC_EISTR is masked.,1: The DATTEO status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 3. "CMDIDX,Command Index Error Status Enable" "0: The CMDIDX status flag in SDMMC_EISTR is masked.,1: The CMDIDX status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x2 2. "CMDEND,Command End Bit Error Status Enable" "0: The CMDEND status flag in SDMMC_EISTR is masked.,1: The CMDEND status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x2 1. "CMDCRC,Command CRC Error Status Enable" "0: The CMDCRC status flag in SDMMC_EISTR is masked.,1: The CMDCRC status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x2 0. "CMDTEO,Command Timeout Error Status Enable" "0: The CMDTEO status flag in SDMMC_EISTR is masked.,1: The CMDTEO status flag in SDMMC_EISTR is enabled."
|
|
group.word 0x36++0x3
|
|
line.word 0x0 "EISTER_SD_SDIO_MODE,Error Interrupt Status Enable Register"
|
|
bitfld.word 0x0 10. "TUNING,Tuning Error Status Enable" "0: The TUNING status flag in SDMMC_EISTR is masked.,1: The TUNING status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x0 9. "ADMA,ADMA Error Status Enable" "0: The ADMA status flag in SDMMC_EISTR is masked.,1: The ADMA status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 8. "ACMD,Auto CMD Error Status Enable" "0: The ACMD status flag in SDMMC_EISTR is masked.,1: The ACMD status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x0 7. "CURLIM,Current Limit Error Status Enable" "0: The CURLIM status flag in SDMMC_EISTR is masked.,1: The CURLIM status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 6. "DATEND,Data End Bit Error Status Enable" "0: The DATEND status flag in SDMMC_EISTR is masked.,1: The DATEND status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x0 5. "DATCRC,Data CRC Error Status Enable" "0: The DATCRC status flag in SDMMC_EISTR is masked.,1: The DATCRC status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 4. "DATTEO,Data Timeout Error Status Enable" "0: The DATTEO status flag in SDMMC_EISTR is masked.,1: The DATTEO status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x0 3. "CMDIDX,Command Index Error Status Enable" "0: The CMDIDX status flag in SDMMC_EISTR is masked.,1: The CMDIDX status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 2. "CMDEND,Command End Bit Error Status Enable" "0: The CMDEND status flag in SDMMC_EISTR is masked.,1: The CMDEND status flag in SDMMC_EISTR is enabled."
|
|
bitfld.word 0x0 1. "CMDCRC,Command CRC Error Status Enable" "0: The CMDCRC status flag in SDMMC_EISTR is masked.,1: The CMDCRC status flag in SDMMC_EISTR is enabled."
|
|
newline
|
|
bitfld.word 0x0 0. "CMDTEO,Command Timeout Error Status Enable" "0: The CMDTEO status flag in SDMMC_EISTR is masked.,1: The CMDTEO status flag in SDMMC_EISTR is enabled."
|
|
line.word 0x2 "NISIER_EMMC_MODE,Normal Interrupt Signal Enable Register"
|
|
bitfld.word 0x2 14. "BOOTAR,Boot Acknowledge Received Signal Enable" "0: No interrupt is generated when the BOOTAR status..,1: An interrupt is generated when the BOOTAR status.."
|
|
bitfld.word 0x2 5. "BRDRDY,Buffer Read Ready Signal Enable" "0: No interrupt is generated when the BRDRDY status..,1: An interrupt is generated when the BRDRDY status.."
|
|
newline
|
|
bitfld.word 0x2 4. "BWRRDY,Buffer Write Ready Signal Enable" "0: No interrupt is generated when the BWRRDY status..,1: An interrupt is generated when the BWRRDY status.."
|
|
bitfld.word 0x2 3. "DMAINT,DMA Interrupt Signal Enable" "0: No interrupt is generated when the DMAINT status..,1: An interrupt is generated when the DMAINT status.."
|
|
newline
|
|
bitfld.word 0x2 2. "BLKGE,Block Gap Event Signal Enable" "0: No interrupt is generated when the BLKGE status..,1: An interrupt is generated when the BLKGE status.."
|
|
bitfld.word 0x2 1. "TRFC,Transfer Complete Signal Enable" "0: No interrupt is generated when the TRFC status..,1: An interrupt is generated when the TRFC status.."
|
|
newline
|
|
bitfld.word 0x2 0. "CMDC,Command Complete Signal Enable" "0: No interrupt is generated when the CMDC status..,1: An interrupt is generated when the CMDC status.."
|
|
group.word 0x38++0x3
|
|
line.word 0x0 "NISIER_SD_SDIO_MODE,Normal Interrupt Signal Enable Register"
|
|
bitfld.word 0x0 8. "CINT,Card Interrupt Signal Enable" "0: No interrupt is generated when the CINT status..,1: An interrupt is generated when the CINT status.."
|
|
bitfld.word 0x0 7. "CREM,Card Removal Signal Enable" "0: No interrupt is generated when the CREM status..,1: An interrupt is generated when the CREM status.."
|
|
newline
|
|
bitfld.word 0x0 6. "CINS,Card Insertion Signal Enable" "0: No interrupt is generated when the CINS status..,1: An interrupt is generated when the CINS status.."
|
|
bitfld.word 0x0 5. "BRDRDY,Buffer Read Ready Signal Enable" "0: No interrupt is generated when the BRDRDY status..,1: An interrupt is generated when the BRDRDY status.."
|
|
newline
|
|
bitfld.word 0x0 4. "BWRRDY,Buffer Write Ready Signal Enable" "0: No interrupt is generated when the BWRRDY status..,1: An interrupt is generated when the BWRRDY status.."
|
|
bitfld.word 0x0 3. "DMAINT,DMA Interrupt Signal Enable" "0: No interrupt is generated when the DMAINT status..,1: An interrupt is generated when the DMAINT status.."
|
|
newline
|
|
bitfld.word 0x0 2. "BLKGE,Block Gap Event Signal Enable" "0: No interrupt is generated when the BLKGE status..,1: An interrupt is generated when the BLKGE status.."
|
|
bitfld.word 0x0 1. "TRFC,Transfer Complete Signal Enable" "0: No interrupt is generated when the TRFC status..,1: An interrupt is generated when the TRFC status.."
|
|
newline
|
|
bitfld.word 0x0 0. "CMDC,Command Complete Signal Enable" "0: No interrupt is generated when the CMDC status..,1: An interrupt is generated when the CMDC status.."
|
|
line.word 0x2 "EISIER_EMMC_MODE,Error Interrupt Signal Enable Register"
|
|
bitfld.word 0x2 12. "BOOTAE,Boot Acknowledge Error Signal Enable" "0: No interrupt is generated when the BOOTAE status..,1: An interrupt is generated when the BOOTAE status.."
|
|
bitfld.word 0x2 10. "TUNING,Tuning Error Signal Enable" "0: No interrupt is generated when the TUNING status..,1: An interrupt is generated when the TUNING status.."
|
|
newline
|
|
bitfld.word 0x2 9. "ADMA,ADMA Error Signal Enable" "0: No interrupt is generated when the ADMA status..,1: An interrupt is generated when the ADMA status.."
|
|
bitfld.word 0x2 8. "ACMD,Auto CMD Error Signal Enable" "0: No interrupt is generated when the ACMD status..,1: An interrupt is generated when the ACMD status.."
|
|
newline
|
|
bitfld.word 0x2 7. "CURLIM,Current Limit Error Signal Enable" "0: No interrupt is generated when the CURLIM status..,1: An interrupt is generated when the CURLIM status.."
|
|
bitfld.word 0x2 6. "DATEND,Data End Bit Error Signal Enable" "0: No interrupt is generated when the DATEND status..,1: An interrupt is generated when the DATEND status.."
|
|
newline
|
|
bitfld.word 0x2 5. "DATCRC,Data CRC Error Signal Enable" "0: No interrupt is generated when the DATCRC status..,1: An interrupt is generated when the DATCRC status.."
|
|
bitfld.word 0x2 4. "DATTEO,Data Timeout Error Signal Enable" "0: No interrupt is generated when the DATTEO status..,1: An interrupt is generated when the DATTEO status.."
|
|
newline
|
|
bitfld.word 0x2 3. "CMDIDX,Command Index Error Signal Enable" "0: No interrupt is generated when the CMDIDX status..,1: An interrupt is generated when the CMDIDX status.."
|
|
bitfld.word 0x2 2. "CMDEND,Command End Bit Error Signal Enable" "0: No interrupt is generated when the CMDEND status..,1: An interrupt is generated when the CMDEND status.."
|
|
newline
|
|
bitfld.word 0x2 1. "CMDCRC,Command CRC Error Signal Enable" "0: No interrupt is generated when the CDMCRC status..,1: An interrupt is generated when the CMDCRC status.."
|
|
bitfld.word 0x2 0. "CMDTEO,Command Timeout Error Signal Enable" "0: No interrupt is generated when the CMDTEO status..,1: An interrupt is generated when the CMDTEO status.."
|
|
group.word 0x3A++0x1
|
|
line.word 0x0 "EISIER_SD_SDIO_MODE,Error Interrupt Signal Enable Register"
|
|
bitfld.word 0x0 10. "TUNING,Tuning Error Signal Enable" "0: No interrupt is generated when the TUNING status..,1: An interrupt is generated when the TUNING status.."
|
|
bitfld.word 0x0 9. "ADMA,ADMA Error Signal Enable" "0: No interrupt is generated when the ADMA status..,1: An interrupt is generated when the ADMA status.."
|
|
newline
|
|
bitfld.word 0x0 8. "ACMD,Auto CMD Error Signal Enable" "0: No interrupt is generated when the ACMD status..,1: An interrupt is generated when the ACMD status.."
|
|
bitfld.word 0x0 7. "CURLIM,Current Limit Error Signal Enable" "0: No interrupt is generated when the CURLIM status..,1: An interrupt is generated when the CURLIM status.."
|
|
newline
|
|
bitfld.word 0x0 6. "DATEND,Data End Bit Error Signal Enable" "0: No interrupt is generated when the DATEND status..,1: An interrupt is generated when the DATEND status.."
|
|
bitfld.word 0x0 5. "DATCRC,Data CRC Error Signal Enable" "0: No interrupt is generated when the DATCRC status..,1: An interrupt is generated when the DATCRC status.."
|
|
newline
|
|
bitfld.word 0x0 4. "DATTEO,Data Timeout Error Signal Enable" "0: No interrupt is generated when the DATTEO status..,1: An interrupt is generated when the DATTEO status.."
|
|
bitfld.word 0x0 3. "CMDIDX,Command Index Error Signal Enable" "0: No interrupt is generated when the CMDIDX status..,1: An interrupt is generated when the CMDIDX status.."
|
|
newline
|
|
bitfld.word 0x0 2. "CMDEND,Command End Bit Error Signal Enable" "0: No interrupt is generated when the CMDEND status..,1: An interrupt is generated when the CMDEND status.."
|
|
bitfld.word 0x0 1. "CMDCRC,Command CRC Error Signal Enable" "0: No interrupt is generated when the CDMCRC status..,1: An interrupt is generated when the CMDCRC status.."
|
|
newline
|
|
bitfld.word 0x0 0. "CMDTEO,Command Timeout Error Signal Enable" "0: No interrupt is generated when the CMDTEO status..,1: An interrupt is generated when the CMDTEO status.."
|
|
rgroup.word 0x3C++0x1
|
|
line.word 0x0 "ACESR,Auto CMD Error Status Register"
|
|
bitfld.word 0x0 7. "CMDNI,Command Not Issued by Auto CMD12 Error" "0: No error.,1: Error."
|
|
bitfld.word 0x0 4. "ACMDIDX,Auto CMD Index Error" "0: No error.,1: Error."
|
|
newline
|
|
bitfld.word 0x0 3. "ACMDEND,Auto CMD End Bit Error" "0: No error.,1: Error."
|
|
bitfld.word 0x0 2. "ACMDCRC,Auto CMD CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "ACMDTEO,Auto CMD Timeout Error" "0,1"
|
|
bitfld.word 0x0 0. "ACMD12NE,Auto CMD12 Not Executed" "0: No error.,1: Error."
|
|
group.word 0x3E++0x1
|
|
line.word 0x0 "HC2R_EMMC_MODE,Host Control 2 Register"
|
|
bitfld.word 0x0 15. "PVALEN,Preset Value Enable" "0: SDCLK and Driver strength are controlled by the..,1: Automatic selection by Preset Value is enabled."
|
|
bitfld.word 0x0 7. "SCLKSEL,Sampling Clock Select" "0: The fixed clock is used to sample data.,1: The tuned clock is used to sample data."
|
|
newline
|
|
bitfld.word 0x0 6. "EXTUN,Execute Tuning" "0: Not tuned or tuning completed,1: Execute tuning"
|
|
bitfld.word 0x0 4.--5. "DRVSEL,Driver Strength Select" "0: Driver Type B is selected (Default),1: Driver Type A is selected,2: Driver Type C is selected,3: Driver Type D is selected"
|
|
newline
|
|
hexmask.word.byte 0x0 0.--3. 1. "HS200EN,HS200 Mode Enable"
|
|
group.word 0x3E++0x1
|
|
line.word 0x0 "HC2R_SD_SDIO_MODE,Host Control 2 Register"
|
|
bitfld.word 0x0 15. "PVALEN,Preset Value Enable" "0: SDCLK and Driver strength are controlled by the..,1: Automatic selection by Preset Value is enabled."
|
|
bitfld.word 0x0 14. "ASINTEN,Asynchronous Interrupt Enable" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.word 0x0 7. "SCLKSEL,Sampling Clock Select" "0: The fixed clock is used to sample data.,1: The tuned clock is used to sample data."
|
|
bitfld.word 0x0 6. "EXTUN,Execute Tuning" "0: Not tuned or tuning completed.,1: Execute tuning."
|
|
newline
|
|
bitfld.word 0x0 4.--5. "DRVSEL,Driver Strength Select" "0: Driver Type B is selected (Default),1: Driver Type A is selected,2: Driver Type C is selected,3: Driver Type D is selected"
|
|
bitfld.word 0x0 3. "VS18EN,1.8V Signaling Enable" "0: 3.3V signaling.,1: 1.8V signaling."
|
|
newline
|
|
bitfld.word 0x0 0.--2. "UHSMS,UHS Mode Select" "0: UHS SDR12 Mode,1: UHS SDR25 Mode,2: UHS SDR50 Mode,3: UHS SDR104 Mode,4: UHS DDR50 Mode,?,?,?"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "CA0R,Capabilities 0 Register"
|
|
bitfld.long 0x0 30.--31. "SLTYPE,Slot Type" "0: Removable Card Slot,1: Embedded Slot for One Device,?,?"
|
|
bitfld.long 0x0 29. "ASINTSUP,Asynchronous Interrupt Support" "0: Asynchronous interrupt not supported.,1: Asynchronous interrupt supported."
|
|
newline
|
|
bitfld.long 0x0 28. "SB64SUP,64-Bit System Bus Support" "0: 64-bit address bus not supported.,1: 64-bit address bus supported."
|
|
bitfld.long 0x0 26. "V18VSUP,Voltage Support 1.8V" "0: 1.8V Voltage supply not supported.,1: 1.8V Voltage supply supported."
|
|
newline
|
|
bitfld.long 0x0 25. "V30VSUP,Voltage Support 3.0V" "0: 3.0V Voltage supply not supported.,1: 3.0V Voltage supply supported."
|
|
bitfld.long 0x0 24. "V33VSUP,Voltage Support 3.3V" "0: 3.3V Voltage supply not supported.,1: 3.3V Voltage supply supported."
|
|
newline
|
|
bitfld.long 0x0 23. "SRSUP,Suspend/Resume Support" "0: Suspend/Resume not supported.,1: Suspend/Resume supported."
|
|
bitfld.long 0x0 22. "SDMASUP,SDMA Support" "0: SDMA not supported.,1: SDMA supported."
|
|
newline
|
|
bitfld.long 0x0 21. "HSSUP,High Speed Support" "0: High Speed not supported.,1: High Speed supported."
|
|
bitfld.long 0x0 19. "ADMA2SUP,ADMA2 Support" "0: ADMA2 not supported.,1: ADMA2 supported."
|
|
newline
|
|
bitfld.long 0x0 18. "ED8SUP,8-Bit Support for Embedded Device" "0: 8-bit bus width not supported.,1: 8-bit bus width supported."
|
|
bitfld.long 0x0 16.--17. "MAXBLKL,Max Block Length" "0: 512 bytes,1: 1024 bytes,2: 2048 bytes,?"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "BASECLKF,Base Clock Frequency"
|
|
bitfld.long 0x0 7. "TEOCLKU,Timeout Clock Unit" "0: KHz,1: MHz"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TEOCLKF,Timeout Clock Frequency"
|
|
line.long 0x4 "CA1R,Capabilities 1 Register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "CLKMULT,Clock Multiplier"
|
|
bitfld.long 0x4 14.--15. "RTMOD,Retuning Modes" "0: Timer,1: Timer and Retuning Request,2: Auto Retuning (for transfer) Timer and Retuning..,?"
|
|
newline
|
|
bitfld.long 0x4 13. "TSDR50,Use Tuning for SDR50" "0: SDR50 does not require tuning.,1: SDR50 requires tuning."
|
|
hexmask.long.byte 0x4 8.--11. 1. "TCNTRT,Timer Count For Retuning"
|
|
newline
|
|
bitfld.long 0x4 6. "DRVDSUP,Driver Type D Support" "0: Driver type D is not supported.,1: Driver type D is supported."
|
|
bitfld.long 0x4 5. "DRVCSUP,Driver Type C Support" "0: Driver type C is not supported.,1: Driver type C is supported."
|
|
newline
|
|
bitfld.long 0x4 4. "DRVASUP,Driver Type A Support" "0: Driver type A is not supported.,1: Driver type A is supported."
|
|
bitfld.long 0x4 2. "DDR50SUP,DDR50 Support" "0: DDR50 mode is not supported.,1: DDR50 mode is supported."
|
|
newline
|
|
bitfld.long 0x4 1. "SDR104SUP,SDR104 Support" "0: SDR104 mode is not supported.,1: SDR104 mode is supported."
|
|
bitfld.long 0x4 0. "SDR50SUP,SDR50 Support" "0: SDR50 mode is not supported.,1: SDR50 mode is supported."
|
|
line.long 0x8 "MCCAR,Maximum Current Capabilities Register"
|
|
hexmask.long.byte 0x8 16.--23. 1. "MAXCUR18V,Maximum Current for 1.8V"
|
|
hexmask.long.byte 0x8 8.--15. 1. "MAXCUR30V,Maximum Current for 3.0V"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "MAXCUR33V,Maximum Current for 3.3V"
|
|
wgroup.word 0x50++0x3
|
|
line.word 0x0 "FERACES,Force Event Register for Auto CMD Error Status"
|
|
bitfld.word 0x0 7. "CMDNI,Force Event for Command Not Issued by Auto CMD12 Error" "0,1"
|
|
bitfld.word 0x0 4. "ACMDIDX,Force Event for Auto CMD Index Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "ACMDEND,Force Event for Auto CMD End Bit Error" "0,1"
|
|
bitfld.word 0x0 2. "ACMDCRC,Force Event for Auto CMD CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "ACMDTEO,Force Event for Auto CMD Timeout Error" "0,1"
|
|
bitfld.word 0x0 0. "ACMD12NE,Force Event for Auto CMD12 Not Executed" "0,1"
|
|
line.word 0x2 "FEREIS,Force Event Register for Error Interrupt Status"
|
|
bitfld.word 0x2 12. "BOOTAE,Force Event for Boot Acknowledge Error" "0,1"
|
|
bitfld.word 0x2 9. "ADMA,Force Event for ADMA Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 8. "ACMD,Force Event for Auto CMD Error" "0,1"
|
|
bitfld.word 0x2 7. "CURLIM,Force Event for Current Limit Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 6. "DATEND,Force Event for Data End Bit Error" "0,1"
|
|
bitfld.word 0x2 5. "DATCRC,Force Event for Data CRC error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 4. "DATTEO,Force Event for Data Timeout error" "0,1"
|
|
bitfld.word 0x2 3. "CMDIDX,Force Event for Command Index Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 2. "CMDEND,Force Event for Command End Bit Error" "0,1"
|
|
bitfld.word 0x2 1. "CMDCRC,Force Event for Command CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 0. "CMDTEO,Force Event for Command Timeout Error" "0,1"
|
|
rgroup.byte 0x54++0x0
|
|
line.byte 0x0 "AESR,ADMA Error Status Register"
|
|
bitfld.byte 0x0 2. "LMIS,ADMA Length Mismatch Error" "0: No error.,1: Error."
|
|
bitfld.byte 0x0 0.--1. "ERRST,ADMA Error State" "0: (Stop DMA) SDMMC_ASAR points to the descriptor..,1: (Fetch Descriptor) SDMMC_ASAR points to the..,?,3: (Transfer Data) SDMMC_ASAR points to the.."
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "ASAR0,ADMA System Address Register 0"
|
|
hexmask.long 0x0 0.--31. 1. "ADMASA,ADMA System Address"
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x60)++0x1
|
|
line.word 0x0 "PVR[$1],Preset Value Register x (for initialization)"
|
|
bitfld.word 0x0 14.--15. "DRVSEL,Driver Strength Select" "0,1,2,3"
|
|
bitfld.word 0x0 10. "CLKGSEL,Clock Generator Select" "0,1"
|
|
newline
|
|
hexmask.word 0x0 0.--9. 1. "SDCLKFSEL,SDCLK Frequency Select"
|
|
repeat.end
|
|
rgroup.word 0xFC++0x3
|
|
line.word 0x0 "SISR,Slot Interrupt Status Register"
|
|
bitfld.word 0x0 0.--2. "INTSSL,Interrupt Signal for Each Slot" "0,1,2,3,4,5,6,7"
|
|
line.word 0x2 "HCVR,Host Controller Version Register"
|
|
hexmask.word.byte 0x2 8.--15. 1. "VVER,Vendor Version Number"
|
|
hexmask.word.byte 0x2 0.--7. 1. "SVER,Specification Version Number"
|
|
rgroup.long 0x200++0x3
|
|
line.long 0x0 "APSR,Additional Present State Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "HDATLL,DAT[7:4] High Line Level"
|
|
group.byte 0x204++0x0
|
|
line.byte 0x0 "MC1R,e.MMC Control 1 Register"
|
|
bitfld.byte 0x0 7. "FCD,e.MMC Force Card Detect" "0: E.MMC Forced Card Detect is disabled. The..,1: E.MMC Forced Card Detect is enabled."
|
|
bitfld.byte 0x0 6. "RSTN,e.MMC Reset Signal" "0: Reset signal is inactive.,1: Reset signal is active."
|
|
newline
|
|
bitfld.byte 0x0 5. "BOOTA,e.MMC Boot Acknowledge Enable" "0,1"
|
|
bitfld.byte 0x0 4. "OPD,e.MMC Open Drain Mode" "0: The command line is in push-pull.,1: The command line is in open drain."
|
|
newline
|
|
bitfld.byte 0x0 3. "DDR,e.MMC HSDDR Mode" "0: High Speed DDR is not selected.,1: High Speed DDR is selected."
|
|
bitfld.byte 0x0 0.--1. "CMDTYP,e.MMC Command Type" "0: The command is not an e.MMC specific command.,1: This bit must be set to 1 when the e.MMC is in..,2: This bit must be set to 1 in the case of Stream..,3: Starts a Boot Operation mode at the next write.."
|
|
wgroup.byte 0x205++0x0
|
|
line.byte 0x0 "MC2R,e.MMC Control 2 Register"
|
|
bitfld.byte 0x0 1. "ABOOT,e.MMC Abort Boot" "0,1"
|
|
bitfld.byte 0x0 0. "SRESP,e.MMC Abort Wait IRQ" "0,1"
|
|
group.byte 0x206++0x1
|
|
line.byte 0x0 "MC3R,e.MMC Control 3 Register"
|
|
bitfld.byte 0x0 3.--5. "DQSUPVAL,DQS Delay Update Timer Value" "0: DQS delay update is performed each time a..,?,?,?,?,?,?,?"
|
|
bitfld.byte 0x0 1. "ESMEN,Enhanced Strobe Mode Enable" "0: Enhanced Strobe mode is disabled.,1: Enhanced Strobe mode is enabled."
|
|
newline
|
|
bitfld.byte 0x0 0. "HS400EN,HS400 Mode Enable" "0: HS400 mode is disabled.,1: HS400 mode is enabled."
|
|
line.byte 0x1 "DEBR,Debounce Register"
|
|
bitfld.byte 0x1 0.--1. "CDDVAL,Card Detect Debounce Value" "0,1,2,3"
|
|
group.long 0x208++0x7
|
|
line.long 0x0 "ACR,AHB Control Register"
|
|
hexmask.long.byte 0x0 12.--15. 1. "DFQOS,Descriptor Fetch QOS"
|
|
bitfld.long 0x0 8.--9. "BUFM,AHB Bufferable Mode" "0: All SDMA/ADMA AHB accesses are not bufferable.,1: All SDMA/ADMA AHB accesses are bufferable.,2: All SDMA/ADMA AHB accesses are bufferable except..,3: All SDMA/ADMA AHB accesses are bufferable except.."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "BMAX,AHB Maximum Burst" "0: The maximum burst size is INCR16.,1: The maximum burst size is INCR8.,2: The maximum burst size is INCR4.,3: Only SINGLE transfers are performed."
|
|
line.long 0x4 "CC2R,Clock Control 2 Register"
|
|
bitfld.long 0x4 0. "FSDCLKD,Force SDCLK Disabled" "0: The SDCLK is forced and it cannot be stopped..,1: The SDCLK is not forced and it can be stopped.."
|
|
group.byte 0x210++0x0
|
|
line.byte 0x0 "RTC1R,Retuning Timer Control 1 Register"
|
|
bitfld.byte 0x0 0. "TMREN,Retuning Timer Enable" "0: The retuning timer is disabled.,1: The retuning timer is enabled."
|
|
wgroup.byte 0x211++0x0
|
|
line.byte 0x0 "RTC2R,Retuning Timer Control 2 Register"
|
|
bitfld.byte 0x0 0. "RLD,Retuning Timer Reload" "0,1"
|
|
group.long 0x214++0x3
|
|
line.long 0x0 "RTCVR,Retuning Timer Counter Value Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TCVAL,Retuning Timer Counter Value"
|
|
group.byte 0x218++0x1
|
|
line.byte 0x0 "RTISTER,Retuning Timer Interrupt Status Enable Register"
|
|
bitfld.byte 0x0 0. "TEVT,Retuning Timer Event" "0: The TEVT status flag in SDMMC_RTISTR is masked.,1: The TEVT status flag in SDMMC_RTISTR is enabled."
|
|
line.byte 0x1 "RTISIER,Retuning Timer Interrupt Signal Enable Register"
|
|
bitfld.byte 0x1 0. "TEVT,Retuning Timer Event" "0: No interrupt is generated when the TEVT status..,1: An interrupt is generated when the TEVT status.."
|
|
group.byte 0x21C++0x0
|
|
line.byte 0x0 "RTISTR,Retuning Timer Interrupt Status Register"
|
|
bitfld.byte 0x0 0. "TEVT,Retuning Timer Event" "0: No retuning timer event.,1: Retuning timer event."
|
|
rgroup.byte 0x21D++0x0
|
|
line.byte 0x0 "RTSSR,Retuning Timer Status Slots Register"
|
|
bitfld.byte 0x0 0.--2. "TEVTSLOT,Retuning Timer Event Slots" "0,1,2,3,4,5,6,7"
|
|
group.long 0x220++0x3
|
|
line.long 0x0 "TUNCR,Tuning Control Register"
|
|
bitfld.long 0x0 0. "SMPLPT,Sampling Point" "0: Sampling point is set at 50% of the data window.,1: Sampling point is set at 75% of the data window."
|
|
group.long 0x230++0x7
|
|
line.long 0x0 "CACR,Capabilities Control Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "KEY,Key"
|
|
bitfld.long 0x0 0. "CAPWREN,Capabilities Write Enable" "0: Capabilities registers (SDMMC_CA0R SDMMC_CA1R..,1: Capabilities registers (SDMMC_CA0R SDMMC_CA1R.."
|
|
line.long 0x4 "DBGR,Debug Register"
|
|
bitfld.long 0x4 0. "NIDBG,Nonintrusive Debug" "0: Reading the SDMMC_BDPR via debugger increments..,1: Reading the SDMMC_BDPR via debugger does not.."
|
|
group.long 0x240++0x3
|
|
line.long 0x0 "CALCR,Calibration Control Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "CALPBP,Calibration PBypass value"
|
|
hexmask.long.byte 0x0 24.--27. 1. "CALP,Calibration P Status"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "CALNBP,Calibration N Bypass value"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CALN,Calibration N Status"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CNTVAL,Calibration Counter Value"
|
|
bitfld.long 0x0 6. "BPEN,Calibration Bypass Enabled" "0: Calibration bypass is not enabled.,1: Calibration bypass is enabled. CALPBP and CALNBP.."
|
|
newline
|
|
bitfld.long 0x0 5. "TUNDIS,Calibration During Tuning Disabled" "0: Calibration is launched before each tuning.,1: Calibration is not launched at tuning."
|
|
bitfld.long 0x0 4. "ALWYSON,Calibration Analog Always ON" "0: Calibration analog is shut down after each..,1: Calibration analog remains powered after.."
|
|
newline
|
|
bitfld.long 0x0 1.--3. "CLKDIV,Calibration Clock Division" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0. "EN,PADs Calibration Enable" "0: SDMMC I/O calibration disabled.,1: SDMMC I/O calibration enabled."
|
|
group.word 0x244++0x1
|
|
line.word 0x0 "EPVR8,Extended Preset Value Register 8(for HS400)"
|
|
bitfld.word 0x0 14.--15. "DRVSEL,Driver Strength Select" "0,1,2,3"
|
|
bitfld.word 0x0 10. "CLKGSEL,Clock Generator Select" "0,1"
|
|
newline
|
|
hexmask.word 0x0 0.--9. 1. "SDCLKFSEL,SDCLK Frequency Select"
|
|
tree.end
|
|
tree "SDMMC2"
|
|
base ad:0xE120C000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "SSAR,SDMA System Address / Argument 2 Register"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,SDMA System Address"
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "SSAR_CMD23_MODE,SDMA System Address / Argument 2 Register"
|
|
hexmask.long 0x0 0.--31. 1. "ARG2,Argument 2"
|
|
group.word 0x4++0x3
|
|
line.word 0x0 "BSR,Block Size Register"
|
|
bitfld.word 0x0 12.--14. "BOUNDARY,SDMA Buffer Boundary" "0: 4-Kbyte boundary,1: 8-Kbyte boundary,2: 16-Kbyte boundary,3: 32-Kbyte boundary,4: 64-Kbyte boundary,5: 128-Kbyte boundary,6: 256-Kbyte boundary,7: 512-Kbyte boundary"
|
|
hexmask.word 0x0 0.--9. 1. "BLKSIZE,Transfer Block Size"
|
|
line.word 0x2 "BCR,Block Count Register"
|
|
hexmask.word 0x2 0.--15. 1. "BLKCNT,Block Count for Current Transfer"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "ARG1R,Argument 1 Register"
|
|
hexmask.long 0x0 0.--31. 1. "ARG1,Argument 1"
|
|
group.word 0xC++0x3
|
|
line.word 0x0 "TMR,Transfer Mode Register"
|
|
bitfld.word 0x0 5. "MSBSEL,Multi/Single Block Selection" "0,1"
|
|
bitfld.word 0x0 4. "DTDSEL,Data Transfer Direction Selection" "0: Writes data from the SDMMC to the device.,1: Reads data from the device to the SDMMC."
|
|
newline
|
|
bitfld.word 0x0 2.--3. "ACMDEN,Auto Command Enable" "0: Auto Command Disabled,1: Auto CMD12 Enabled,2: Auto CMD23 Enabled,?"
|
|
bitfld.word 0x0 1. "BCEN,Block Count Enable" "0: Block count is disabled.,1: Block count is enabled."
|
|
newline
|
|
bitfld.word 0x0 0. "DMAEN,DMA Enable" "0: DMA functionality is disabled.,1: DMA functionality is enabled."
|
|
line.word 0x2 "CR,Command Register"
|
|
hexmask.word.byte 0x2 8.--13. 1. "CMDIDX,Command Index"
|
|
bitfld.word 0x2 6.--7. "CMDTYP,Command Type" "0: Other commands,1: CMD52 to write 'Bus Suspend' in the Card Common..,2: CMD52 to write 'Function Select' in the Card..,3: CMD12 CMD52 to write 'I/O Abort' in the Card.."
|
|
newline
|
|
bitfld.word 0x2 5. "DPSEL,Data Present Select" "0: No data present,1: Data present"
|
|
bitfld.word 0x2 4. "CMDICEN,Command Index Check Enable" "0: The Command Index Check is disabled.,1: The Command Index Check is enabled."
|
|
newline
|
|
bitfld.word 0x2 3. "CMDCCEN,Command CRC Check Enable" "0: The Command CRC Check is disabled.,1: The Command CRC Check is enabled."
|
|
bitfld.word 0x2 0.--1. "RESPTYP,Response Type" "0: No Response,1: Response Length 136,2: Response Length 48,3: Response Length 48 with Busy"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x10)++0x3
|
|
line.long 0x0 "RR[$1],Response Register x"
|
|
hexmask.long 0x0 0.--31. 1. "CMDRESP,Command Response"
|
|
repeat.end
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "BDPR,Buffer Data Port Register"
|
|
hexmask.long 0x0 0.--31. 1. "BUFDATA,Buffer Data"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "PSR,Present State Register"
|
|
bitfld.long 0x0 24. "CMDLL,CMD Line Level" "0,1"
|
|
hexmask.long.byte 0x0 20.--23. 1. "DATLL,DAT[3:0] Line Level"
|
|
newline
|
|
bitfld.long 0x0 19. "WRPPL,Write Protect Pin Level" "0: Write protected (SDMMC_WP = 0),1: Write enabled (SDMMC_WP = 1)"
|
|
bitfld.long 0x0 18. "CARDDPL,Card Detect Pin Level" "0: No card present (SDMMC_CD = 1).,1: Card present (SDMMC_CD = 0)."
|
|
newline
|
|
bitfld.long 0x0 17. "CARDSS,Card State Stable" "0: Reset or debouncing.,1: No card or card inserted."
|
|
bitfld.long 0x0 16. "CARDINS,Card Inserted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "BUFRDEN,Buffer Read Enable" "0,1"
|
|
bitfld.long 0x0 10. "BUFWREN,Buffer Write Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RTACT,Read Transfer Active" "0,1"
|
|
bitfld.long 0x0 8. "WTACT,Write Transfer Active" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DLACT,DAT Line Active" "0: DAT line inactive.,1: DAT line active."
|
|
bitfld.long 0x0 1. "CMDINHD,Command Inhibit (DAT)" "0: Can issue a command which uses the DAT line(s).,1: Cannot issue a command which uses the DAT line(s)."
|
|
newline
|
|
bitfld.long 0x0 0. "CMDINHC,Command Inhibit (CMD)" "0: Can issue a command using only CMD line.,1: Cannot issue a command."
|
|
group.byte 0x28++0x0
|
|
line.byte 0x0 "HC1R_EMMC_MODE,Host Control 1 Register"
|
|
bitfld.byte 0x0 5. "EXTDW,Extended Data Width" "0,1"
|
|
bitfld.byte 0x0 3.--4. "DMASEL,DMA Select" "0: SDMA is selected,?,2: 32-bit Address ADMA2 is selected,?"
|
|
newline
|
|
bitfld.byte 0x0 2. "HSEN,High Speed Enable" "0: Normal Speed mode.,1: High Speed mode."
|
|
bitfld.byte 0x0 1. "DW,Data Width" "0: 1-bit mode.,1: 4-bit mode."
|
|
group.byte 0x28++0x2
|
|
line.byte 0x0 "HC1R_SD_SDIO_MODE,Host Control 1 Register"
|
|
bitfld.byte 0x0 7. "CARDDSEL,Card Detect Signal Selection" "0: The SDMMC_CD pin is selected.,1: The Card Detect Test Level (CARDDTL) is selected.."
|
|
bitfld.byte 0x0 6. "CARDDTL,Card Detect Test Level" "0: No card.,1: Card inserted."
|
|
newline
|
|
bitfld.byte 0x0 3.--4. "DMASEL,DMA Select" "0: SDMA is selected,?,2: 32-bit Address ADMA2 is selected,?"
|
|
bitfld.byte 0x0 2. "HSEN,High Speed Enable" "0: Normal Speed mode.,1: High Speed mode."
|
|
newline
|
|
bitfld.byte 0x0 1. "DW,Data Width" "0: 1-bit mode.,1: 4-bit mode."
|
|
bitfld.byte 0x0 0. "LEDCTRL,LED Control" "0: LED off.,1: LED on."
|
|
line.byte 0x1 "PCR,Power Control Register"
|
|
bitfld.byte 0x1 0. "SDBPWR,SD Bus Power" "0,1"
|
|
line.byte 0x2 "BGCR_EMMC_MODE,Block Gap Control Register"
|
|
bitfld.byte 0x2 1. "CONTR,Continue Request" "0: No effect.,1: Restart."
|
|
bitfld.byte 0x2 0. "STPBGR,Stop At Block Gap Request" "0: Transfer,1: Stop"
|
|
group.byte 0x2A++0x1
|
|
line.byte 0x0 "BGCR_SD_SDIO_MODE,Block Gap Control Register"
|
|
bitfld.byte 0x0 3. "INTBG,Interrupt at Block Gap" "0: Interrupt detection disabled.,1: Interrupt detection enabled."
|
|
bitfld.byte 0x0 2. "RWCTRL,Read Wait Control" "0: Disables Read Wait control.,1: Enables Read Wait control."
|
|
newline
|
|
bitfld.byte 0x0 1. "CONTR,Continue Request" "0: No effect.,1: Restart."
|
|
bitfld.byte 0x0 0. "STPBGR,Stop At Block Gap Request" "0: Transfer,1: Stop"
|
|
line.byte 0x1 "WCR,Wakeup Control Register"
|
|
bitfld.byte 0x1 2. "WKENCREM,Wakeup Event Enable on Card Removal" "0: Wakeup Event disabled.,1: Wakeup Event enabled."
|
|
bitfld.byte 0x1 1. "WKENCINS,Wakeup Event Enable on Card Insertion" "0: Wakeup Event disabled.,1: Wakeup Event enabled."
|
|
newline
|
|
bitfld.byte 0x1 0. "WKENCINT,Wakeup Event Enable on Card Interrupt" "0: Wakeup Event disabled.,1: Wakeup Event enabled."
|
|
group.word 0x2C++0x1
|
|
line.word 0x0 "CCR,Clock Control Register"
|
|
hexmask.word.byte 0x0 8.--15. 1. "SDCLKFSEL,SDCLK Frequency Select"
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bitfld.word 0x0 6.--7. "USDCLKFSEL,Upper Bits of SDCLK Frequency Select" "0,1,2,3"
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newline
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bitfld.word 0x0 5. "CLKGSEL,Clock Generator Select" "0: Divided Clock mode (BASECLK is used to generate..,1: Programmable Clock mode (MULTCLK is used to.."
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bitfld.word 0x0 2. "SDCLKEN,SD Clock Enable" "0: SD Clock disabled,1: SD Clock enabled"
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newline
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bitfld.word 0x0 1. "INTCLKS,Internal Clock Stable" "0: Internal clock not ready.,1: Internal clock ready."
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bitfld.word 0x0 0. "INTCLKEN,Internal Clock Enable" "0: The internal clock stops.,1: The internal clock oscillates."
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group.byte 0x2E++0x1
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line.byte 0x0 "TCR,Timeout Control Register"
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hexmask.byte 0x0 0.--3. 1. "DTCVAL,Data Timeout Counter Value"
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line.byte 0x1 "SRR,Software Reset Register"
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bitfld.byte 0x1 2. "SWRSTDAT,Software reset for DAT line" "0: Work,1: Reset"
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bitfld.byte 0x1 1. "SWRSTCMD,Software reset for CMD line" "0: Work,1: Reset"
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newline
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bitfld.byte 0x1 0. "SWRSTALL,Software reset for All" "0: Work,1: Reset"
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group.word 0x30++0x1
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line.word 0x0 "NISTR_EMMC_MODE,Normal Interrupt Status Register"
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bitfld.word 0x0 15. "ERRINT,Error Interrupt" "0: No error.,1: Error."
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bitfld.word 0x0 14. "BOOTAR,Boot Acknowledge Received" "0: Boot Acknowledge pattern not received.,1: Boot Acknowledge pattern received."
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|
newline
|
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bitfld.word 0x0 5. "BRDRDY,Buffer Read Ready" "0: Not ready to read buffer.,1: Ready to read buffer."
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bitfld.word 0x0 4. "BWRRDY,Buffer Write Ready" "0: Not ready to write buffer.,1: Ready to write buffer."
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|
newline
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bitfld.word 0x0 3. "DMAINT,DMA Interrupt" "0: No DMA interrupt.,1: DMA interrupt."
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bitfld.word 0x0 2. "BLKGE,Block Gap Event" "0: No block gap event.,1: Transaction stopped at block gap."
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newline
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bitfld.word 0x0 1. "TRFC,Transfer Complete" "0: Command execution is not complete.,1: Command execution is complete."
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bitfld.word 0x0 0. "CMDC,Command Complete" "0: No command complete.,1: Command complete."
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group.word 0x30++0x3
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line.word 0x0 "NISTR_SD_SDIO_MODE,Normal Interrupt Status Register"
|
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bitfld.word 0x0 15. "ERRINT,Error Interrupt" "0: No error.,1: Error."
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bitfld.word 0x0 8. "CINT,Card Interrupt" "0: No card interrupt.,1: Card interrupt."
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newline
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bitfld.word 0x0 7. "CREM,Card Removal" "0: Card state unstable or card inserted.,1: Card removed."
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bitfld.word 0x0 6. "CINS,Card Insertion" "0: Card state unstable or card removed.,1: Card inserted."
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newline
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bitfld.word 0x0 5. "BRDRDY,Buffer Read Ready" "0: Not ready to read buffer.,1: Ready to read buffer."
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bitfld.word 0x0 4. "BWRRDY,Buffer Write Ready" "0: Not ready to write buffer.,1: Ready to write buffer."
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|
newline
|
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bitfld.word 0x0 3. "DMAINT,DMA Interrupt" "0: No DMA Interrupt.,1: DMA Interrupt."
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bitfld.word 0x0 2. "BLKGE,Block Gap Event" "0: No block gap event.,1: Transaction stopped at block gap."
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|
newline
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bitfld.word 0x0 1. "TRFC,Transfer Complete" "0: Command execution is not complete.,1: Command execution is complete."
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bitfld.word 0x0 0. "CMDC,Command Complete" "0: No command complete.,1: Command complete."
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line.word 0x2 "EISTR_EMMC_MODE,Error Interrupt Status Register"
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bitfld.word 0x2 12. "BOOTAE,Boot Acknowledge Error" "0: No error.,1: Error."
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|
bitfld.word 0x2 10. "TUNING,Tuning Error" "0: No error.,1: Error."
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|
newline
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bitfld.word 0x2 9. "ADMA,ADMA Error" "0: No error.,1: Error."
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|
bitfld.word 0x2 8. "ACMD,Auto CMD Error" "0: No error.,1: Error."
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|
newline
|
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bitfld.word 0x2 7. "CURLIM,Current Limit Error" "0: No error.,1: Error."
|
|
bitfld.word 0x2 6. "DATEND,Data End Bit Error" "0: No error.,1: Error."
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|
newline
|
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bitfld.word 0x2 5. "DATCRC,Data CRC Error" "0: No error.,1: Error."
|
|
bitfld.word 0x2 4. "DATTEO,Data Timeout error" "0: No error.,1: Error."
|
|
newline
|
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bitfld.word 0x2 3. "CMDIDX,Command Index Error" "0: No error.,1: Error."
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|
bitfld.word 0x2 2. "CMDEND,Command End Bit Error" "0: No error.,1: Error."
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|
newline
|
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bitfld.word 0x2 1. "CMDCRC,Command CRC Error" "0,1"
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|
bitfld.word 0x2 0. "CMDTEO,Command Timeout Error" "0,1"
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group.word 0x32++0x3
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line.word 0x0 "EISTR_SD_SDIO_MODE,Error Interrupt Status Register"
|
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bitfld.word 0x0 10. "TUNING,Tuning Error" "0: No error.,1: Error."
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bitfld.word 0x0 9. "ADMA,ADMA Error" "0: No error.,1: Error."
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|
newline
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bitfld.word 0x0 8. "ACMD,Auto CMD Error" "0: No error.,1: Error."
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|
bitfld.word 0x0 7. "CURLIM,Current Limit Error" "0: No error.,1: Error."
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|
newline
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bitfld.word 0x0 6. "DATEND,Data End Bit Error" "0: No error.,1: Error."
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bitfld.word 0x0 5. "DATCRC,Data CRC error" "0: No error.,1: Error."
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|
newline
|
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bitfld.word 0x0 4. "DATTEO,Data Timeout Error" "0: No error.,1: Error."
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|
bitfld.word 0x0 3. "CMDIDX,Command Index Error" "0: No error.,1: Error."
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newline
|
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bitfld.word 0x0 2. "CMDEND,Command End Bit Error" "0: No error.,1: Error."
|
|
bitfld.word 0x0 1. "CMDCRC,Command CRC Error" "0,1"
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newline
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bitfld.word 0x0 0. "CMDTEO,Command Timeout Error" "0,1"
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line.word 0x2 "NISTER_EMMC_MODE,Normal Interrupt Status Enable Register"
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bitfld.word 0x2 14. "BOOTAR,Boot Acknowledge Received Status Enable" "0: The BOOTAR status flag in SDMMC_NISTR is masked.,1: The BOOTAR status flag in SDMMC_NISTR is enabled."
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bitfld.word 0x2 5. "BRDRDY,Buffer Read Ready Status Enable" "0: The BRDRDY status flag in SDMMC_NISTR is masked.,1: The BRDRDY status flag in SDMMC_NISTR is enabled."
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newline
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bitfld.word 0x2 4. "BWRRDY,Buffer Write Ready Status Enable" "0: The BWRRDY status flag in SDMMC_NISTR is masked.,1: The BWRRDY status flag in SDMMC_NISTR is enabled."
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bitfld.word 0x2 3. "DMAINT,DMA Interrupt Status Enable" "0: The DMAINT status flag in SDMMC_NISTR is masked.,1: The DMAINT status flag in SDMMC_NISTR is enabled."
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newline
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bitfld.word 0x2 2. "BLKGE,Block Gap Event Status Enable" "0: The BLKGE status flag in SDMMC_NISTR is masked.,1: The BLKGE status flag in SDMMC_NISTR is enabled."
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bitfld.word 0x2 1. "TRFC,Transfer Complete Status Enable" "0: The TRFC status flag in SDMMC_NISTR is masked.,1: The TRFC status flag in SDMMC_NISTR is enabled."
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newline
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bitfld.word 0x2 0. "CMDC,Command Complete Status Enable" "0: The CMDC status flag in SDMMC_NISTR is masked.,1: The CMDC status flag in SDMMC_NISTR is enabled."
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group.word 0x34++0x3
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line.word 0x0 "NISTER_SD_SDIO_MODE,Normal Interrupt Status Enable Register"
|
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bitfld.word 0x0 8. "CINT,Card Interrupt Status Enable" "0: The CINT status flag in SDMMC_NISTR is masked.,1: The CINT status flag in SDMMC_NISTR is enabled."
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bitfld.word 0x0 7. "CREM,Card Removal Status Enable" "0: The CREM status flag in SDMMC_NISTR is masked.,1: The CREM status flag in SDMMC_NISTR is enabled."
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newline
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bitfld.word 0x0 6. "CINS,Card Insertion Status Enable" "0: The CINS status flag in SDMMC_NISTR is masked.,1: The CINS status flag in SDMMC_NISTR is enabled."
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bitfld.word 0x0 5. "BRDRDY,Buffer Read Ready Status Enable" "0: The BRDRDY status flag in SDMMC_NISTR is masked.,1: The BRDRDY status flag in SDMMC_NISTR is enabled."
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newline
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bitfld.word 0x0 4. "BWRRDY,Buffer Write Ready Status Enable" "0: The BWRRDY status flag in SDMMC_NISTR is masked.,1: The BWRRDY status flag in SDMMC_NISTR is enabled."
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bitfld.word 0x0 3. "DMAINT,DMA Interrupt Status Enable" "0: The DMAINT status flag in SDMMC_NISTR is masked.,1: The DMAINT status flag in SDMMC_NISTR is enabled."
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newline
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bitfld.word 0x0 2. "BLKGE,Block Gap Event Status Enable" "0: The BLKGE status flag in SDMMC_NISTR is masked.,1: The BLKGE status flag in SDMMC_NISTR is enabled."
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bitfld.word 0x0 1. "TRFC,Transfer Complete Status Enable" "0: The TRFC status flag in SDMMC_NISTR is masked.,1: The TRFC status flag in SDMMC_NISTR is enabled."
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newline
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bitfld.word 0x0 0. "CMDC,Command Complete Status Enable" "0: The CMDC status flag in SDMMC_NISTR is masked.,1: The CMDC status flag in SDMMC_NISTR is enabled."
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line.word 0x2 "EISTER_EMMC_MODE,Error Interrupt Status Enable Register"
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bitfld.word 0x2 12. "BOOTAE,Boot Acknowledge Error Status Enable" "0: The BOOTAE status flag in SDMMC_EISTR is masked.,1: The BOOTAE status flag in SDMMC_EISTR is enabled."
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bitfld.word 0x2 10. "TUNING,Tuning Error Status Enable" "0: The TUNING status flag in SDMMC_EISTR is masked.,1: The TUNING status flag in SDMMC_EISTR is enabled."
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newline
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bitfld.word 0x2 9. "ADMA,ADMA Error Status Enable" "0: The ADMA status flag in SDMMC_EISTR is masked.,1: The ADMA status flag in SDMMC_EISTR is enabled."
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bitfld.word 0x2 8. "ACMD,Auto CMD Error Status Enable" "0: The ACMD status flag in SDMMC_EISTR is masked.,1: The ACMD status flag in SDMMC_EISTR is enabled."
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newline
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bitfld.word 0x2 7. "CURLIM,Current Limit Error Status Enable" "0: The CURLIM status flag in SDMMC_EISTR is masked.,1: The CURLIM status flag in SDMMC_EISTR is enabled."
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bitfld.word 0x2 6. "DATEND,Data End Bit Error Status Enable" "0: The DATEND status flag in SDMMC_EISTR is masked.,1: The DATEND status flag in SDMMC_EISTR is enabled."
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newline
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bitfld.word 0x2 5. "DATCRC,Data CRC Error Status Enable" "0: The DATCRC status flag in SDMMC_EISTR is masked.,1: The DATCRC status flag in SDMMC_EISTR is enabled."
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bitfld.word 0x2 4. "DATTEO,Data Timeout Error Status Enable" "0: The DATTEO status flag in SDMMC_EISTR is masked.,1: The DATTEO status flag in SDMMC_EISTR is enabled."
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newline
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bitfld.word 0x2 3. "CMDIDX,Command Index Error Status Enable" "0: The CMDIDX status flag in SDMMC_EISTR is masked.,1: The CMDIDX status flag in SDMMC_EISTR is enabled."
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bitfld.word 0x2 2. "CMDEND,Command End Bit Error Status Enable" "0: The CMDEND status flag in SDMMC_EISTR is masked.,1: The CMDEND status flag in SDMMC_EISTR is enabled."
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newline
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bitfld.word 0x2 1. "CMDCRC,Command CRC Error Status Enable" "0: The CMDCRC status flag in SDMMC_EISTR is masked.,1: The CMDCRC status flag in SDMMC_EISTR is enabled."
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bitfld.word 0x2 0. "CMDTEO,Command Timeout Error Status Enable" "0: The CMDTEO status flag in SDMMC_EISTR is masked.,1: The CMDTEO status flag in SDMMC_EISTR is enabled."
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group.word 0x36++0x3
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line.word 0x0 "EISTER_SD_SDIO_MODE,Error Interrupt Status Enable Register"
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bitfld.word 0x0 10. "TUNING,Tuning Error Status Enable" "0: The TUNING status flag in SDMMC_EISTR is masked.,1: The TUNING status flag in SDMMC_EISTR is enabled."
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bitfld.word 0x0 9. "ADMA,ADMA Error Status Enable" "0: The ADMA status flag in SDMMC_EISTR is masked.,1: The ADMA status flag in SDMMC_EISTR is enabled."
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newline
|
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bitfld.word 0x0 8. "ACMD,Auto CMD Error Status Enable" "0: The ACMD status flag in SDMMC_EISTR is masked.,1: The ACMD status flag in SDMMC_EISTR is enabled."
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bitfld.word 0x0 7. "CURLIM,Current Limit Error Status Enable" "0: The CURLIM status flag in SDMMC_EISTR is masked.,1: The CURLIM status flag in SDMMC_EISTR is enabled."
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newline
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bitfld.word 0x0 6. "DATEND,Data End Bit Error Status Enable" "0: The DATEND status flag in SDMMC_EISTR is masked.,1: The DATEND status flag in SDMMC_EISTR is enabled."
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bitfld.word 0x0 5. "DATCRC,Data CRC Error Status Enable" "0: The DATCRC status flag in SDMMC_EISTR is masked.,1: The DATCRC status flag in SDMMC_EISTR is enabled."
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newline
|
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bitfld.word 0x0 4. "DATTEO,Data Timeout Error Status Enable" "0: The DATTEO status flag in SDMMC_EISTR is masked.,1: The DATTEO status flag in SDMMC_EISTR is enabled."
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bitfld.word 0x0 3. "CMDIDX,Command Index Error Status Enable" "0: The CMDIDX status flag in SDMMC_EISTR is masked.,1: The CMDIDX status flag in SDMMC_EISTR is enabled."
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newline
|
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bitfld.word 0x0 2. "CMDEND,Command End Bit Error Status Enable" "0: The CMDEND status flag in SDMMC_EISTR is masked.,1: The CMDEND status flag in SDMMC_EISTR is enabled."
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bitfld.word 0x0 1. "CMDCRC,Command CRC Error Status Enable" "0: The CMDCRC status flag in SDMMC_EISTR is masked.,1: The CMDCRC status flag in SDMMC_EISTR is enabled."
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newline
|
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bitfld.word 0x0 0. "CMDTEO,Command Timeout Error Status Enable" "0: The CMDTEO status flag in SDMMC_EISTR is masked.,1: The CMDTEO status flag in SDMMC_EISTR is enabled."
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line.word 0x2 "NISIER_EMMC_MODE,Normal Interrupt Signal Enable Register"
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bitfld.word 0x2 14. "BOOTAR,Boot Acknowledge Received Signal Enable" "0: No interrupt is generated when the BOOTAR status..,1: An interrupt is generated when the BOOTAR status.."
|
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bitfld.word 0x2 5. "BRDRDY,Buffer Read Ready Signal Enable" "0: No interrupt is generated when the BRDRDY status..,1: An interrupt is generated when the BRDRDY status.."
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newline
|
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bitfld.word 0x2 4. "BWRRDY,Buffer Write Ready Signal Enable" "0: No interrupt is generated when the BWRRDY status..,1: An interrupt is generated when the BWRRDY status.."
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bitfld.word 0x2 3. "DMAINT,DMA Interrupt Signal Enable" "0: No interrupt is generated when the DMAINT status..,1: An interrupt is generated when the DMAINT status.."
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newline
|
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bitfld.word 0x2 2. "BLKGE,Block Gap Event Signal Enable" "0: No interrupt is generated when the BLKGE status..,1: An interrupt is generated when the BLKGE status.."
|
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bitfld.word 0x2 1. "TRFC,Transfer Complete Signal Enable" "0: No interrupt is generated when the TRFC status..,1: An interrupt is generated when the TRFC status.."
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newline
|
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bitfld.word 0x2 0. "CMDC,Command Complete Signal Enable" "0: No interrupt is generated when the CMDC status..,1: An interrupt is generated when the CMDC status.."
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group.word 0x38++0x3
|
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line.word 0x0 "NISIER_SD_SDIO_MODE,Normal Interrupt Signal Enable Register"
|
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bitfld.word 0x0 8. "CINT,Card Interrupt Signal Enable" "0: No interrupt is generated when the CINT status..,1: An interrupt is generated when the CINT status.."
|
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bitfld.word 0x0 7. "CREM,Card Removal Signal Enable" "0: No interrupt is generated when the CREM status..,1: An interrupt is generated when the CREM status.."
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newline
|
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bitfld.word 0x0 6. "CINS,Card Insertion Signal Enable" "0: No interrupt is generated when the CINS status..,1: An interrupt is generated when the CINS status.."
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bitfld.word 0x0 5. "BRDRDY,Buffer Read Ready Signal Enable" "0: No interrupt is generated when the BRDRDY status..,1: An interrupt is generated when the BRDRDY status.."
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newline
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bitfld.word 0x0 4. "BWRRDY,Buffer Write Ready Signal Enable" "0: No interrupt is generated when the BWRRDY status..,1: An interrupt is generated when the BWRRDY status.."
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bitfld.word 0x0 3. "DMAINT,DMA Interrupt Signal Enable" "0: No interrupt is generated when the DMAINT status..,1: An interrupt is generated when the DMAINT status.."
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newline
|
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bitfld.word 0x0 2. "BLKGE,Block Gap Event Signal Enable" "0: No interrupt is generated when the BLKGE status..,1: An interrupt is generated when the BLKGE status.."
|
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bitfld.word 0x0 1. "TRFC,Transfer Complete Signal Enable" "0: No interrupt is generated when the TRFC status..,1: An interrupt is generated when the TRFC status.."
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newline
|
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bitfld.word 0x0 0. "CMDC,Command Complete Signal Enable" "0: No interrupt is generated when the CMDC status..,1: An interrupt is generated when the CMDC status.."
|
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line.word 0x2 "EISIER_EMMC_MODE,Error Interrupt Signal Enable Register"
|
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bitfld.word 0x2 12. "BOOTAE,Boot Acknowledge Error Signal Enable" "0: No interrupt is generated when the BOOTAE status..,1: An interrupt is generated when the BOOTAE status.."
|
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bitfld.word 0x2 10. "TUNING,Tuning Error Signal Enable" "0: No interrupt is generated when the TUNING status..,1: An interrupt is generated when the TUNING status.."
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newline
|
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bitfld.word 0x2 9. "ADMA,ADMA Error Signal Enable" "0: No interrupt is generated when the ADMA status..,1: An interrupt is generated when the ADMA status.."
|
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bitfld.word 0x2 8. "ACMD,Auto CMD Error Signal Enable" "0: No interrupt is generated when the ACMD status..,1: An interrupt is generated when the ACMD status.."
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newline
|
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bitfld.word 0x2 7. "CURLIM,Current Limit Error Signal Enable" "0: No interrupt is generated when the CURLIM status..,1: An interrupt is generated when the CURLIM status.."
|
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bitfld.word 0x2 6. "DATEND,Data End Bit Error Signal Enable" "0: No interrupt is generated when the DATEND status..,1: An interrupt is generated when the DATEND status.."
|
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newline
|
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bitfld.word 0x2 5. "DATCRC,Data CRC Error Signal Enable" "0: No interrupt is generated when the DATCRC status..,1: An interrupt is generated when the DATCRC status.."
|
|
bitfld.word 0x2 4. "DATTEO,Data Timeout Error Signal Enable" "0: No interrupt is generated when the DATTEO status..,1: An interrupt is generated when the DATTEO status.."
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newline
|
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bitfld.word 0x2 3. "CMDIDX,Command Index Error Signal Enable" "0: No interrupt is generated when the CMDIDX status..,1: An interrupt is generated when the CMDIDX status.."
|
|
bitfld.word 0x2 2. "CMDEND,Command End Bit Error Signal Enable" "0: No interrupt is generated when the CMDEND status..,1: An interrupt is generated when the CMDEND status.."
|
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newline
|
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bitfld.word 0x2 1. "CMDCRC,Command CRC Error Signal Enable" "0: No interrupt is generated when the CDMCRC status..,1: An interrupt is generated when the CMDCRC status.."
|
|
bitfld.word 0x2 0. "CMDTEO,Command Timeout Error Signal Enable" "0: No interrupt is generated when the CMDTEO status..,1: An interrupt is generated when the CMDTEO status.."
|
|
group.word 0x3A++0x1
|
|
line.word 0x0 "EISIER_SD_SDIO_MODE,Error Interrupt Signal Enable Register"
|
|
bitfld.word 0x0 10. "TUNING,Tuning Error Signal Enable" "0: No interrupt is generated when the TUNING status..,1: An interrupt is generated when the TUNING status.."
|
|
bitfld.word 0x0 9. "ADMA,ADMA Error Signal Enable" "0: No interrupt is generated when the ADMA status..,1: An interrupt is generated when the ADMA status.."
|
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newline
|
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bitfld.word 0x0 8. "ACMD,Auto CMD Error Signal Enable" "0: No interrupt is generated when the ACMD status..,1: An interrupt is generated when the ACMD status.."
|
|
bitfld.word 0x0 7. "CURLIM,Current Limit Error Signal Enable" "0: No interrupt is generated when the CURLIM status..,1: An interrupt is generated when the CURLIM status.."
|
|
newline
|
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bitfld.word 0x0 6. "DATEND,Data End Bit Error Signal Enable" "0: No interrupt is generated when the DATEND status..,1: An interrupt is generated when the DATEND status.."
|
|
bitfld.word 0x0 5. "DATCRC,Data CRC Error Signal Enable" "0: No interrupt is generated when the DATCRC status..,1: An interrupt is generated when the DATCRC status.."
|
|
newline
|
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bitfld.word 0x0 4. "DATTEO,Data Timeout Error Signal Enable" "0: No interrupt is generated when the DATTEO status..,1: An interrupt is generated when the DATTEO status.."
|
|
bitfld.word 0x0 3. "CMDIDX,Command Index Error Signal Enable" "0: No interrupt is generated when the CMDIDX status..,1: An interrupt is generated when the CMDIDX status.."
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newline
|
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bitfld.word 0x0 2. "CMDEND,Command End Bit Error Signal Enable" "0: No interrupt is generated when the CMDEND status..,1: An interrupt is generated when the CMDEND status.."
|
|
bitfld.word 0x0 1. "CMDCRC,Command CRC Error Signal Enable" "0: No interrupt is generated when the CDMCRC status..,1: An interrupt is generated when the CMDCRC status.."
|
|
newline
|
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bitfld.word 0x0 0. "CMDTEO,Command Timeout Error Signal Enable" "0: No interrupt is generated when the CMDTEO status..,1: An interrupt is generated when the CMDTEO status.."
|
|
rgroup.word 0x3C++0x1
|
|
line.word 0x0 "ACESR,Auto CMD Error Status Register"
|
|
bitfld.word 0x0 7. "CMDNI,Command Not Issued by Auto CMD12 Error" "0: No error.,1: Error."
|
|
bitfld.word 0x0 4. "ACMDIDX,Auto CMD Index Error" "0: No error.,1: Error."
|
|
newline
|
|
bitfld.word 0x0 3. "ACMDEND,Auto CMD End Bit Error" "0: No error.,1: Error."
|
|
bitfld.word 0x0 2. "ACMDCRC,Auto CMD CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "ACMDTEO,Auto CMD Timeout Error" "0,1"
|
|
bitfld.word 0x0 0. "ACMD12NE,Auto CMD12 Not Executed" "0: No error.,1: Error."
|
|
group.word 0x3E++0x1
|
|
line.word 0x0 "HC2R_EMMC_MODE,Host Control 2 Register"
|
|
bitfld.word 0x0 15. "PVALEN,Preset Value Enable" "0: SDCLK and Driver strength are controlled by the..,1: Automatic selection by Preset Value is enabled."
|
|
bitfld.word 0x0 7. "SCLKSEL,Sampling Clock Select" "0: The fixed clock is used to sample data.,1: The tuned clock is used to sample data."
|
|
newline
|
|
bitfld.word 0x0 6. "EXTUN,Execute Tuning" "0: Not tuned or tuning completed,1: Execute tuning"
|
|
bitfld.word 0x0 4.--5. "DRVSEL,Driver Strength Select" "0: Driver Type B is selected (Default),1: Driver Type A is selected,2: Driver Type C is selected,3: Driver Type D is selected"
|
|
newline
|
|
hexmask.word.byte 0x0 0.--3. 1. "HS200EN,HS200 Mode Enable"
|
|
group.word 0x3E++0x1
|
|
line.word 0x0 "HC2R_SD_SDIO_MODE,Host Control 2 Register"
|
|
bitfld.word 0x0 15. "PVALEN,Preset Value Enable" "0: SDCLK and Driver strength are controlled by the..,1: Automatic selection by Preset Value is enabled."
|
|
bitfld.word 0x0 14. "ASINTEN,Asynchronous Interrupt Enable" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.word 0x0 7. "SCLKSEL,Sampling Clock Select" "0: The fixed clock is used to sample data.,1: The tuned clock is used to sample data."
|
|
bitfld.word 0x0 6. "EXTUN,Execute Tuning" "0: Not tuned or tuning completed.,1: Execute tuning."
|
|
newline
|
|
bitfld.word 0x0 4.--5. "DRVSEL,Driver Strength Select" "0: Driver Type B is selected (Default),1: Driver Type A is selected,2: Driver Type C is selected,3: Driver Type D is selected"
|
|
bitfld.word 0x0 3. "VS18EN,1.8V Signaling Enable" "0: 3.3V signaling.,1: 1.8V signaling."
|
|
newline
|
|
bitfld.word 0x0 0.--2. "UHSMS,UHS Mode Select" "0: UHS SDR12 Mode,1: UHS SDR25 Mode,2: UHS SDR50 Mode,3: UHS SDR104 Mode,4: UHS DDR50 Mode,?,?,?"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "CA0R,Capabilities 0 Register"
|
|
bitfld.long 0x0 30.--31. "SLTYPE,Slot Type" "0: Removable Card Slot,1: Embedded Slot for One Device,?,?"
|
|
bitfld.long 0x0 29. "ASINTSUP,Asynchronous Interrupt Support" "0: Asynchronous interrupt not supported.,1: Asynchronous interrupt supported."
|
|
newline
|
|
bitfld.long 0x0 28. "SB64SUP,64-Bit System Bus Support" "0: 64-bit address bus not supported.,1: 64-bit address bus supported."
|
|
bitfld.long 0x0 26. "V18VSUP,Voltage Support 1.8V" "0: 1.8V Voltage supply not supported.,1: 1.8V Voltage supply supported."
|
|
newline
|
|
bitfld.long 0x0 25. "V30VSUP,Voltage Support 3.0V" "0: 3.0V Voltage supply not supported.,1: 3.0V Voltage supply supported."
|
|
bitfld.long 0x0 24. "V33VSUP,Voltage Support 3.3V" "0: 3.3V Voltage supply not supported.,1: 3.3V Voltage supply supported."
|
|
newline
|
|
bitfld.long 0x0 23. "SRSUP,Suspend/Resume Support" "0: Suspend/Resume not supported.,1: Suspend/Resume supported."
|
|
bitfld.long 0x0 22. "SDMASUP,SDMA Support" "0: SDMA not supported.,1: SDMA supported."
|
|
newline
|
|
bitfld.long 0x0 21. "HSSUP,High Speed Support" "0: High Speed not supported.,1: High Speed supported."
|
|
bitfld.long 0x0 19. "ADMA2SUP,ADMA2 Support" "0: ADMA2 not supported.,1: ADMA2 supported."
|
|
newline
|
|
bitfld.long 0x0 18. "ED8SUP,8-Bit Support for Embedded Device" "0: 8-bit bus width not supported.,1: 8-bit bus width supported."
|
|
bitfld.long 0x0 16.--17. "MAXBLKL,Max Block Length" "0: 512 bytes,1: 1024 bytes,2: 2048 bytes,?"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "BASECLKF,Base Clock Frequency"
|
|
bitfld.long 0x0 7. "TEOCLKU,Timeout Clock Unit" "0: KHz,1: MHz"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TEOCLKF,Timeout Clock Frequency"
|
|
line.long 0x4 "CA1R,Capabilities 1 Register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "CLKMULT,Clock Multiplier"
|
|
bitfld.long 0x4 14.--15. "RTMOD,Retuning Modes" "0: Timer,1: Timer and Retuning Request,2: Auto Retuning (for transfer) Timer and Retuning..,?"
|
|
newline
|
|
bitfld.long 0x4 13. "TSDR50,Use Tuning for SDR50" "0: SDR50 does not require tuning.,1: SDR50 requires tuning."
|
|
hexmask.long.byte 0x4 8.--11. 1. "TCNTRT,Timer Count For Retuning"
|
|
newline
|
|
bitfld.long 0x4 6. "DRVDSUP,Driver Type D Support" "0: Driver type D is not supported.,1: Driver type D is supported."
|
|
bitfld.long 0x4 5. "DRVCSUP,Driver Type C Support" "0: Driver type C is not supported.,1: Driver type C is supported."
|
|
newline
|
|
bitfld.long 0x4 4. "DRVASUP,Driver Type A Support" "0: Driver type A is not supported.,1: Driver type A is supported."
|
|
bitfld.long 0x4 2. "DDR50SUP,DDR50 Support" "0: DDR50 mode is not supported.,1: DDR50 mode is supported."
|
|
newline
|
|
bitfld.long 0x4 1. "SDR104SUP,SDR104 Support" "0: SDR104 mode is not supported.,1: SDR104 mode is supported."
|
|
bitfld.long 0x4 0. "SDR50SUP,SDR50 Support" "0: SDR50 mode is not supported.,1: SDR50 mode is supported."
|
|
line.long 0x8 "MCCAR,Maximum Current Capabilities Register"
|
|
hexmask.long.byte 0x8 16.--23. 1. "MAXCUR18V,Maximum Current for 1.8V"
|
|
hexmask.long.byte 0x8 8.--15. 1. "MAXCUR30V,Maximum Current for 3.0V"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "MAXCUR33V,Maximum Current for 3.3V"
|
|
wgroup.word 0x50++0x3
|
|
line.word 0x0 "FERACES,Force Event Register for Auto CMD Error Status"
|
|
bitfld.word 0x0 7. "CMDNI,Force Event for Command Not Issued by Auto CMD12 Error" "0,1"
|
|
bitfld.word 0x0 4. "ACMDIDX,Force Event for Auto CMD Index Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "ACMDEND,Force Event for Auto CMD End Bit Error" "0,1"
|
|
bitfld.word 0x0 2. "ACMDCRC,Force Event for Auto CMD CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "ACMDTEO,Force Event for Auto CMD Timeout Error" "0,1"
|
|
bitfld.word 0x0 0. "ACMD12NE,Force Event for Auto CMD12 Not Executed" "0,1"
|
|
line.word 0x2 "FEREIS,Force Event Register for Error Interrupt Status"
|
|
bitfld.word 0x2 12. "BOOTAE,Force Event for Boot Acknowledge Error" "0,1"
|
|
bitfld.word 0x2 9. "ADMA,Force Event for ADMA Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 8. "ACMD,Force Event for Auto CMD Error" "0,1"
|
|
bitfld.word 0x2 7. "CURLIM,Force Event for Current Limit Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 6. "DATEND,Force Event for Data End Bit Error" "0,1"
|
|
bitfld.word 0x2 5. "DATCRC,Force Event for Data CRC error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 4. "DATTEO,Force Event for Data Timeout error" "0,1"
|
|
bitfld.word 0x2 3. "CMDIDX,Force Event for Command Index Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 2. "CMDEND,Force Event for Command End Bit Error" "0,1"
|
|
bitfld.word 0x2 1. "CMDCRC,Force Event for Command CRC Error" "0,1"
|
|
newline
|
|
bitfld.word 0x2 0. "CMDTEO,Force Event for Command Timeout Error" "0,1"
|
|
rgroup.byte 0x54++0x0
|
|
line.byte 0x0 "AESR,ADMA Error Status Register"
|
|
bitfld.byte 0x0 2. "LMIS,ADMA Length Mismatch Error" "0: No error.,1: Error."
|
|
bitfld.byte 0x0 0.--1. "ERRST,ADMA Error State" "0: (Stop DMA) SDMMC_ASAR points to the descriptor..,1: (Fetch Descriptor) SDMMC_ASAR points to the..,?,3: (Transfer Data) SDMMC_ASAR points to the.."
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "ASAR0,ADMA System Address Register 0"
|
|
hexmask.long 0x0 0.--31. 1. "ADMASA,ADMA System Address"
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x60)++0x1
|
|
line.word 0x0 "PVR[$1],Preset Value Register x (for initialization)"
|
|
bitfld.word 0x0 14.--15. "DRVSEL,Driver Strength Select" "0,1,2,3"
|
|
bitfld.word 0x0 10. "CLKGSEL,Clock Generator Select" "0,1"
|
|
newline
|
|
hexmask.word 0x0 0.--9. 1. "SDCLKFSEL,SDCLK Frequency Select"
|
|
repeat.end
|
|
rgroup.word 0xFC++0x3
|
|
line.word 0x0 "SISR,Slot Interrupt Status Register"
|
|
bitfld.word 0x0 0.--2. "INTSSL,Interrupt Signal for Each Slot" "0,1,2,3,4,5,6,7"
|
|
line.word 0x2 "HCVR,Host Controller Version Register"
|
|
hexmask.word.byte 0x2 8.--15. 1. "VVER,Vendor Version Number"
|
|
hexmask.word.byte 0x2 0.--7. 1. "SVER,Specification Version Number"
|
|
rgroup.long 0x200++0x3
|
|
line.long 0x0 "APSR,Additional Present State Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "HDATLL,DAT[7:4] High Line Level"
|
|
group.byte 0x204++0x0
|
|
line.byte 0x0 "MC1R,e.MMC Control 1 Register"
|
|
bitfld.byte 0x0 7. "FCD,e.MMC Force Card Detect" "0: E.MMC Forced Card Detect is disabled. The..,1: E.MMC Forced Card Detect is enabled."
|
|
bitfld.byte 0x0 6. "RSTN,e.MMC Reset Signal" "0: Reset signal is inactive.,1: Reset signal is active."
|
|
newline
|
|
bitfld.byte 0x0 5. "BOOTA,e.MMC Boot Acknowledge Enable" "0,1"
|
|
bitfld.byte 0x0 4. "OPD,e.MMC Open Drain Mode" "0: The command line is in push-pull.,1: The command line is in open drain."
|
|
newline
|
|
bitfld.byte 0x0 3. "DDR,e.MMC HSDDR Mode" "0: High Speed DDR is not selected.,1: High Speed DDR is selected."
|
|
bitfld.byte 0x0 0.--1. "CMDTYP,e.MMC Command Type" "0: The command is not an e.MMC specific command.,1: This bit must be set to 1 when the e.MMC is in..,2: This bit must be set to 1 in the case of Stream..,3: Starts a Boot Operation mode at the next write.."
|
|
wgroup.byte 0x205++0x0
|
|
line.byte 0x0 "MC2R,e.MMC Control 2 Register"
|
|
bitfld.byte 0x0 1. "ABOOT,e.MMC Abort Boot" "0,1"
|
|
bitfld.byte 0x0 0. "SRESP,e.MMC Abort Wait IRQ" "0,1"
|
|
group.byte 0x206++0x1
|
|
line.byte 0x0 "MC3R,e.MMC Control 3 Register"
|
|
bitfld.byte 0x0 3.--5. "DQSUPVAL,DQS Delay Update Timer Value" "0: DQS delay update is performed each time a..,?,?,?,?,?,?,?"
|
|
bitfld.byte 0x0 1. "ESMEN,Enhanced Strobe Mode Enable" "0: Enhanced Strobe mode is disabled.,1: Enhanced Strobe mode is enabled."
|
|
newline
|
|
bitfld.byte 0x0 0. "HS400EN,HS400 Mode Enable" "0: HS400 mode is disabled.,1: HS400 mode is enabled."
|
|
line.byte 0x1 "DEBR,Debounce Register"
|
|
bitfld.byte 0x1 0.--1. "CDDVAL,Card Detect Debounce Value" "0,1,2,3"
|
|
group.long 0x208++0x7
|
|
line.long 0x0 "ACR,AHB Control Register"
|
|
hexmask.long.byte 0x0 12.--15. 1. "DFQOS,Descriptor Fetch QOS"
|
|
bitfld.long 0x0 8.--9. "BUFM,AHB Bufferable Mode" "0: All SDMA/ADMA AHB accesses are not bufferable.,1: All SDMA/ADMA AHB accesses are bufferable.,2: All SDMA/ADMA AHB accesses are bufferable except..,3: All SDMA/ADMA AHB accesses are bufferable except.."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "BMAX,AHB Maximum Burst" "0: The maximum burst size is INCR16.,1: The maximum burst size is INCR8.,2: The maximum burst size is INCR4.,3: Only SINGLE transfers are performed."
|
|
line.long 0x4 "CC2R,Clock Control 2 Register"
|
|
bitfld.long 0x4 0. "FSDCLKD,Force SDCLK Disabled" "0: The SDCLK is forced and it cannot be stopped..,1: The SDCLK is not forced and it can be stopped.."
|
|
group.byte 0x210++0x0
|
|
line.byte 0x0 "RTC1R,Retuning Timer Control 1 Register"
|
|
bitfld.byte 0x0 0. "TMREN,Retuning Timer Enable" "0: The retuning timer is disabled.,1: The retuning timer is enabled."
|
|
wgroup.byte 0x211++0x0
|
|
line.byte 0x0 "RTC2R,Retuning Timer Control 2 Register"
|
|
bitfld.byte 0x0 0. "RLD,Retuning Timer Reload" "0,1"
|
|
group.long 0x214++0x3
|
|
line.long 0x0 "RTCVR,Retuning Timer Counter Value Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TCVAL,Retuning Timer Counter Value"
|
|
group.byte 0x218++0x1
|
|
line.byte 0x0 "RTISTER,Retuning Timer Interrupt Status Enable Register"
|
|
bitfld.byte 0x0 0. "TEVT,Retuning Timer Event" "0: The TEVT status flag in SDMMC_RTISTR is masked.,1: The TEVT status flag in SDMMC_RTISTR is enabled."
|
|
line.byte 0x1 "RTISIER,Retuning Timer Interrupt Signal Enable Register"
|
|
bitfld.byte 0x1 0. "TEVT,Retuning Timer Event" "0: No interrupt is generated when the TEVT status..,1: An interrupt is generated when the TEVT status.."
|
|
group.byte 0x21C++0x0
|
|
line.byte 0x0 "RTISTR,Retuning Timer Interrupt Status Register"
|
|
bitfld.byte 0x0 0. "TEVT,Retuning Timer Event" "0: No retuning timer event.,1: Retuning timer event."
|
|
rgroup.byte 0x21D++0x0
|
|
line.byte 0x0 "RTSSR,Retuning Timer Status Slots Register"
|
|
bitfld.byte 0x0 0.--2. "TEVTSLOT,Retuning Timer Event Slots" "0,1,2,3,4,5,6,7"
|
|
group.long 0x220++0x3
|
|
line.long 0x0 "TUNCR,Tuning Control Register"
|
|
bitfld.long 0x0 0. "SMPLPT,Sampling Point" "0: Sampling point is set at 50% of the data window.,1: Sampling point is set at 75% of the data window."
|
|
group.long 0x230++0x7
|
|
line.long 0x0 "CACR,Capabilities Control Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "KEY,Key"
|
|
bitfld.long 0x0 0. "CAPWREN,Capabilities Write Enable" "0: Capabilities registers (SDMMC_CA0R SDMMC_CA1R..,1: Capabilities registers (SDMMC_CA0R SDMMC_CA1R.."
|
|
line.long 0x4 "DBGR,Debug Register"
|
|
bitfld.long 0x4 0. "NIDBG,Nonintrusive Debug" "0: Reading the SDMMC_BDPR via debugger increments..,1: Reading the SDMMC_BDPR via debugger does not.."
|
|
group.long 0x240++0x3
|
|
line.long 0x0 "CALCR,Calibration Control Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "CALPBP,Calibration PBypass value"
|
|
hexmask.long.byte 0x0 24.--27. 1. "CALP,Calibration P Status"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "CALNBP,Calibration N Bypass value"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CALN,Calibration N Status"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CNTVAL,Calibration Counter Value"
|
|
bitfld.long 0x0 6. "BPEN,Calibration Bypass Enabled" "0: Calibration bypass is not enabled.,1: Calibration bypass is enabled. CALPBP and CALNBP.."
|
|
newline
|
|
bitfld.long 0x0 5. "TUNDIS,Calibration During Tuning Disabled" "0: Calibration is launched before each tuning.,1: Calibration is not launched at tuning."
|
|
bitfld.long 0x0 4. "ALWYSON,Calibration Analog Always ON" "0: Calibration analog is shut down after each..,1: Calibration analog remains powered after.."
|
|
newline
|
|
bitfld.long 0x0 1.--3. "CLKDIV,Calibration Clock Division" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0. "EN,PADs Calibration Enable" "0: SDMMC I/O calibration disabled.,1: SDMMC I/O calibration enabled."
|
|
group.word 0x244++0x1
|
|
line.word 0x0 "EPVR8,Extended Preset Value Register 8(for HS400)"
|
|
bitfld.word 0x0 14.--15. "DRVSEL,Driver Strength Select" "0,1,2,3"
|
|
bitfld.word 0x0 10. "CLKGSEL,Clock Generator Select" "0,1"
|
|
newline
|
|
hexmask.word 0x0 0.--9. 1. "SDCLKFSEL,SDCLK Frequency Select"
|
|
tree.end
|
|
tree.end
|
|
tree "SECUMOD (Security Module)"
|
|
base ad:0xE0004000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "KEY,Password"
|
|
newline
|
|
bitfld.long 0x0 9.--10. "SCRAMB,Memory Scrambling Enable" "?,1: Memories are scrambled (default).,2: Memories are not scrambled.,?"
|
|
newline
|
|
bitfld.long 0x0 5.--6. "AUTOBKP,Automatic Normal to Backup Mode Switching" "?,1: When in Normal mode the powerdown of the core..,2: When in Normal mode the software must switch to..,?"
|
|
newline
|
|
bitfld.long 0x0 3.--4. "NIMP_EN,Non-Imprinting Enable" "0: No effect.,1: The non-imprinting mechanism is authorized to..,2: The non-imprinting mechanism is disabled..,3: The non-imprinting mechanism is authorized to.."
|
|
newline
|
|
bitfld.long 0x0 2. "SWPROT,Software Protection" "0: No effect.,1: Starts the BUSRAM4KB and BUREG256b Clear content."
|
|
newline
|
|
bitfld.long 0x0 1. "NORMAL,Normal Mode" "0: No effect.,1: Switches to Normal mode."
|
|
newline
|
|
bitfld.long 0x0 0. "BACKUP,Backup Mode" "0: No effect.,1: Switches to Backup mode."
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "SYSR,System Status Register"
|
|
bitfld.long 0x0 8. "NIMP_IDLE,'CPU in idle' preliminary condition for non-imprinting (RO)" "0: Idle is not part of preliminary conditions list.,1: Idle is part of preliminary conditions list."
|
|
newline
|
|
bitfld.long 0x0 7. "SCRAMB,Scrambling Enabled (RO)" "0: Disabled.,1: Enabled."
|
|
newline
|
|
bitfld.long 0x0 6. "AUTOBKP,Automatic Backup Mode Enabled (RO)" "0: Disabled.,1: Enabled."
|
|
newline
|
|
bitfld.long 0x0 5. "NIMP_EN,Non-Imprinting Enabled (RO)" "0: Disabled.,1: Enabled."
|
|
newline
|
|
bitfld.long 0x0 3. "SWKUP,SWKUP State (RO)" "0: No SWKUP signal sent since the last clear.,1: SWKUP signal has been sent since the last clear."
|
|
newline
|
|
bitfld.long 0x0 2. "BACKUP,Backup Mode (RO)" "0: Normal mode active.,1: Backup mode active."
|
|
newline
|
|
bitfld.long 0x0 1. "ERASE_ON,Erase Process Ongoing (RO)" "0: Erase automaton is not running.,1: Erase automaton is currently running memories.."
|
|
newline
|
|
bitfld.long 0x0 0. "ERASE_DONE,Erasable Memories State (RW)" "0: Secure memories content has not been erased..,1: Secure memories content has been erased since.."
|
|
rgroup.long 0x8++0x7
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 21. "DET3,PIOBU Intrusion Detector" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "DET2,PIOBU Intrusion Detector" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "DET1,PIOBU Intrusion Detector" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "DET0,PIOBU Intrusion Detector" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "VDDCPUH,High VDDCPU Voltage Monitor" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "VDDCOREH,High VDDCORE Voltage Monitor" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "VDDCPUL,Low VDDCPU Voltage Monitor" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "VDDCOREL,Low VDDCORE Voltage Monitor" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "VBATH,High VBAT Voltage Monitor" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "VBATL,Low VBAT Voltage Monitor" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TPMH,High Temperature Monitor" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TPML,Low Temperature Monitor" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MCKM,Master Clock Monitor" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "REGANA,VDDANA regulator Monitor" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "JTAG,JTAG Pins Monitor" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TST,Test Pin Monitor" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "DBLFM,Double Frequency Monitor" "0,1"
|
|
line.long 0x4 "ASR,Auxiliary Status Register"
|
|
bitfld.long 0x4 9. "PSWHI,VDDIN33 (used as secondary LDO power source through backup powerswitch) low alarm detected is the cause of VBATL flag in SECUMOD_SR." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "BUHI,VBAT high alarm detected is the cause of VBATH flag in SECUMOD_SR." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PSWLO,VDDIN33 (used as secondary LDO power source through backup powerswitch) low alarm detected is the cause of VBATL flag in SECUMOD_SR." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "BULO,VBAT low alarm detected is the cause of VBATL flag in SECUMOD_SR." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "TCK,TCK/TMS activity detected is the cause of JTAG flag in SECUMOD_SR." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "JTAG,JTAGSEL or processor debug acknowledge is the cause of JTAG flag in SECUMOD_SR." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "REGANA_HI,High voltage alarm from VDDANA regulator is the cause of REGANA flag in SECUMOD_SR." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "REGANA_LO,Low voltage alarm from VDDANA regulator is the cause of REGANA flag in SECUMOD_SR." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "MCKM_HI,High frequency limit reached is the cause of MCKM flag in SECUMOD_SR." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "MCKM_LO,Low frequency limit reached is the cause of MCKM flag in SECUMOD_SR." "0,1"
|
|
wgroup.long 0x10++0x3
|
|
line.long 0x0 "SCR,Status Clear Register"
|
|
bitfld.long 0x0 21. "DET3,PIOBU Intrusion Detector" "0,1"
|
|
newline
|
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bitfld.long 0x0 20. "DET2,PIOBU Intrusion Detector" "0,1"
|
|
newline
|
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bitfld.long 0x0 19. "DET1,PIOBU Intrusion Detector" "0,1"
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|
newline
|
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bitfld.long 0x0 18. "DET0,PIOBU Intrusion Detector" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "VDDCPUH,High VDDCPU Voltage Monitor" "0,1"
|
|
newline
|
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bitfld.long 0x0 14. "VDDCOREH,High VDDCORE Voltage Monitor" "0,1"
|
|
newline
|
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bitfld.long 0x0 13. "VDDCPUL,Low VDDCPU Voltage Monitor" "0,1"
|
|
newline
|
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bitfld.long 0x0 12. "VDDCOREL,Low VDDCORE Voltage Monitor" "0,1"
|
|
newline
|
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bitfld.long 0x0 11. "VBATH,High VBAT Voltage Monitor" "0,1"
|
|
newline
|
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bitfld.long 0x0 10. "VBATL,Low VBAT Voltage Monitor" "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "TPMH,High Temperature Monitor" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TPML,Low Temperature Monitor" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MCKM,Master Clock Monitor" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "REGANA,VDDANA regulator Monitor" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "JTAG,JTAG Pins Monitor" "0,1"
|
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newline
|
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bitfld.long 0x0 2. "TST,Test Pin Monitor" "0,1"
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|
newline
|
|
bitfld.long 0x0 1. "DBLFM,Double Frequency Monitor" "0,1"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "RAMRDY,RAM Access Ready Register"
|
|
bitfld.long 0x0 0. "READY,Ready for system access flag" "0,1"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x18)++0x3
|
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line.long 0x0 "PIOBU[$1],PIO Backup Register x"
|
|
bitfld.long 0x0 21. "FILTER3_5,Filter for Dynamic Signatures Input" "0: 3-stage majority vote (default).,1: 5-stage majority vote."
|
|
newline
|
|
bitfld.long 0x0 20. "DYNSTAT,Switch for Static or Dynamic Detection Intrusion" "0: Static detection intrusion (default) mode is..,1: Dynamic detection intrusion mode is selected."
|
|
newline
|
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bitfld.long 0x0 15. "SWITCH,Switch State for Intrusion Detection" "0: Input default state is low level.,1: Input default state is high level."
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newline
|
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bitfld.long 0x0 14. "SCHEDULE,Pullup/Pulldown Scheduled" "0: Pullup/Pulldown is not scheduled.,1: Pullup/Pulldown is scheduled."
|
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newline
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bitfld.long 0x0 12.--13. "PULLUP,Programmable Pullup State" "0,1,2,3"
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newline
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bitfld.long 0x0 10. "PIO_PDS,Level on the Pin in Input Mode (OUTPUT = 0) (Read-only)" "0: The I/O line is at level 0.,1: The I/O line is at level 1."
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newline
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bitfld.long 0x0 9. "PIO_SOD,Set/Clear the I/O Line when configured in Output Mode (OUTPUT =1)" "0: Clears the data to be driven on the I/O line.,1: Sets the data to be driven on the I/O line."
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newline
|
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bitfld.long 0x0 8. "OUTPUT,Configure I/O Line in Input/Output" "0: The I/O line is a pure input.,1: The I/O line is enabled in output."
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newline
|
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hexmask.long.byte 0x0 4.--7. 1. "PIOBU_RFV,PIOBUx Reset Filter Value"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "PIOBU_AFV,PIOBU Alarm Filter Value"
|
|
repeat.end
|
|
group.long 0x58++0x3
|
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line.long 0x0 "VBUFR,VBAT Filter Register"
|
|
bitfld.long 0x0 0.--2. "VBATFV,VBAT Filter Value" "0,1,2,3,4,5,6,7"
|
|
group.long 0x64++0x7
|
|
line.long 0x0 "VCOREFR,VDDCORE Filter Register"
|
|
hexmask.long.word 0x0 0.--12. 1. "VDDCORE_DBTV,VDDCORE Programmable Debouncing Time Value"
|
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line.long 0x4 "VCPUFR,VDDCPU Filter Register"
|
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hexmask.long.word 0x4 0.--12. 1. "VDDCPU_DBTV,VDDCPU Programmable Debouncing Time Value"
|
|
group.long 0x70++0x1B
|
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line.long 0x0 "JTAGCR,JTAG Protection Control Register"
|
|
bitfld.long 0x0 4. "PROC_DEBUG_MON,Debug Acknowledge (DBGACK) Monitoring" "0: The processor's pin DBGACK is not monitored; as..,1: The processor's pin DBGACK is monitored."
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newline
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bitfld.long 0x0 1.--3. "PROC_DEBUG_MODE,Invasive/Non-Invasive Secure/Non-Secure Debug Permissions" "0,1,2,3,4,5,6,7"
|
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newline
|
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bitfld.long 0x0 0. "FNTRST,Force NTRST" "0: The processor's TAP controller access and..,1: NDBGRESET of the processor's TAP controller and.."
|
|
line.long 0x4 "DYSTUNE,Dynamic Signatures Tuning Register"
|
|
hexmask.long.word 0x4 16.--31. 1. "PERIOD,Signature Clock Period"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "RX_OK_CORREL_NUMBER,Error Counter Reset Threshold"
|
|
newline
|
|
bitfld.long 0x4 7. "NOPA,No Periodic Alarm" "0: The alarm is regenerated periodically while..,1: The alarm is not regenerated periodically while.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "RX_ERROR_THRESHOLD,Error Detection Threshold"
|
|
line.long 0x8 "SCRKEY,Scrambling Key Register"
|
|
hexmask.long 0x8 0.--31. 1. "SCRKEY,Scrambling Key Value"
|
|
line.long 0xC "RAMACC,RAM Access Rights Register"
|
|
bitfld.long 0xC 10.--11. "RW5,Access right for RAM region [5 Kbytes; 6 Kbytes] (register bank BUREG256b)" "0,1,2,3"
|
|
newline
|
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bitfld.long 0xC 8.--9. "RW4,Access right for RAM region [4 Kbytes; 5 Kbytes]" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 6.--7. "RW3,Access right for RAM region [3 Kbytes; 4 Kbytes]" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 4.--5. "RW2,Access right for RAM region [2 Kbytes; 3 Kbytes]" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 2.--3. "RW1,Access right for RAM region [1 Kbyte; 2 Kbytes]" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 0.--1. "RW0,Access right for RAM region [0; 1 Kbyte]" "0,1,2,3"
|
|
line.long 0x10 "RAMACCSR,RAM Access Rights Status Register"
|
|
bitfld.long 0x10 10.--11. "RW5,Access right status for RAM region [5 Kbytes; 6 Kbytes] (register bank BUREG256b)" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x10 8.--9. "RW4,Access right status for RAM region [4 Kbytes; 5 Kbytes]" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 6.--7. "RW3,Access right status for RAM region [3 Kbytes; 4 Kbytes]" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 4.--5. "RW2,Access right status for RAM region [2 Kbytes; 3 Kbytes]" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 2.--3. "RW1,Access right status for RAM region [1 Kbytes; 2 Kbytes]" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 0.--1. "RW0,Access right status for RAM region [0; 1 Kbyte]" "0,1,2,3"
|
|
line.long 0x14 "BMPR,Backup Mode Protection Register"
|
|
bitfld.long 0x14 21. "DET3,PIOBU Intrusion Detector Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x14 20. "DET2,PIOBU Intrusion Detector Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x14 19. "DET1,PIOBU Intrusion Detector Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x14 18. "DET0,PIOBU Intrusion Detector Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x14 11. "VBATH,High VBAT Voltage Monitor Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x14 10. "VBATL,Low VBAT Voltage Monitor Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x14 7. "TPMH,High Temperature Monitor Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x14 6. "TPML,Low Temperature Monitor Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x14 3. "JTAG,JTAG Pin Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "TST,Test Pin Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "DBLFM,Double Frequency Monitor Protection" "0,1"
|
|
line.long 0x18 "NMPR,Normal Mode Protection Register"
|
|
bitfld.long 0x18 21. "DET3,PIOBU Intrusion Detector Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x18 20. "DET2,PIOBU Intrusion Detector Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x18 19. "DET1,PIOBU Intrusion Detector Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x18 18. "DET0,PIOBU Intrusion Detector Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x18 15. "VDDCPUH,High VDDCPU Voltage Monitor Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x18 14. "VDDCOREH,High VDDCORE Voltage Monitor Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x18 13. "VDDCPUL,Low VDDCPU Voltage Monitor Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x18 12. "VDDCOREL,Low VDDCORE Voltage Monitor Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x18 11. "VBATH,High VBAT Voltage Monitor Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x18 10. "VBATL,Low VBAT Voltage Monitor Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x18 7. "TPMH,High Temperature Monitor Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x18 6. "TPML,Low Temperature Monitor Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x18 5. "MCKM,Master Clock Monitor Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x18 4. "REGANA,VDDANA regulator voltage monitor Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x18 3. "JTAG,JTAG Pin Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x18 2. "TST,Test Pin Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x18 1. "DBLFM,Double Frequency Monitor Protection" "0,1"
|
|
wgroup.long 0x8C++0x7
|
|
line.long 0x0 "NIEPR,Normal Interrupt Enable Protection Register"
|
|
bitfld.long 0x0 21. "DET3,PIOBU Intrusion Detector Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "DET2,PIOBU Intrusion Detector Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "DET1,PIOBU Intrusion Detector Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "DET0,PIOBU Intrusion Detector Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "VDDCPUH,High VDDCPU Voltage Monitor Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "VDDCOREH,High VDDCORE Voltage Monitor Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "VDDCPUL,Low VDDCPU Voltage Monitor Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "VDDCOREL,Low VDDCORE Voltage Monitor Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "VBATH,High VBAT Voltage Monitor Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "VBATL,Low VBAT Voltage Monitor Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TPMH,High Temperature Monitor Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TPML,Low Temperature Monitor Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MCKM,Master Clock Monitor Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "REGANA,VDDANA regulator voltage monitor Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "JTAG,JTAG Pin Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TST,Test Pin Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "DBLFM,Double Frequency Monitor Protection Interrupt Enable" "0,1"
|
|
line.long 0x4 "NIDPR,Normal Interrupt Disable Protection Register"
|
|
bitfld.long 0x4 21. "DET3,PIOBU Intrusion Detector Protection Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "DET2,PIOBU Intrusion Detector Protection Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "DET1,PIOBU Intrusion Detector Protection Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "DET0,PIOBU Intrusion Detector Protection Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "VDDCPUH,High VDDCPU Voltage Monitor Protection Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "VDDCOREH,High VDDCORE Voltage Monitor Protection Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "VDDCPUL,Low VDDCPU Voltage Monitor Protection Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "VDDCOREL,Low VDDCORE Voltage Monitor Protection Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "VBATH,High VBAT Voltage Monitor Protection Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "VBATL,Low VBAT Voltage Monitor Protection Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "TPMH,High Temperature Monitor Protection Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TPML,Low Temperature Monitor Protection Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "MCKM,Master Clock Monitor Protection Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "REGANA,VDDANA regulator voltage monitor Protection Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "JTAG,JTAG Pin Protection Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TST,Test Pin Protection Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DBLFM,Double Frequency Monitor Protection Interrupt Disable" "0,1"
|
|
rgroup.long 0x94++0x3
|
|
line.long 0x0 "NIMPR,Normal Interrupt Mask Protection Register"
|
|
bitfld.long 0x0 21. "DET3,PIOBU Intrusion Detector Protection Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "DET2,PIOBU Intrusion Detector Protection Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "DET1,PIOBU Intrusion Detector Protection Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "DET0,PIOBU Intrusion Detector Protection Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "VDDCPUH,High VDDCPU Voltage Monitor Protection Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "VDDCOREH,High VDDCORE Voltage Monitor Protection Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "VDDCPUL,Low VDDCPU Voltage Monitor Protection Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "VDDCOREL,Low VDDCORE Voltage Monitor Protection Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "VBATH,High VBAT Voltage Monitor Protection Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "VBATL,Low VBAT Voltage Monitor Protection Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TPMH,High Temperature Monitor Protection Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TPML,Low Temperature Monitor Protection Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MCKM,Master Clock Monitor Protection Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "REGANA,VDDANA regulator voltage monitor Protection Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "JTAG,JTAG Pin Protection Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TST,Test Pin Protection Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "DBLFM,Double Frequency Monitor Protection Interrupt Mask" "0,1"
|
|
group.long 0x98++0x7
|
|
line.long 0x0 "WKPR,Wakeup Protection Register"
|
|
bitfld.long 0x0 21. "DET3,PIOBU Intrusion Detector Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "DET2,PIOBU Intrusion Detector Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "DET1,PIOBU Intrusion Detector Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "DET0,PIOBU Intrusion Detector Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "VBATH,High VBAT Voltage Monitor Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "VBATL,Low VBAT Voltage Monitor Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TPMH,High Temperature Monitor Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TPML,Low Temperature Monitor Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "JTAG,JTAG Pin Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TST,Test Pin Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "DBLFM,Double Frequency Monitor Protection" "0,1"
|
|
line.long 0x4 "GPSBR,General Purpose Security Bits Register"
|
|
hexmask.long.word 0x4 20.--31. 1. "KEY,Safety key must write 0xD5E to enable GPSBR modifications"
|
|
newline
|
|
bitfld.long 0x4 2. "SMCPURANGE," "0: Sets SM VDDCPU thresholds for 600MHz max..,1: Sets SM VDDCPU thresholds for 800MHz max.."
|
|
newline
|
|
bitfld.long 0x4 1. "TSRANGE," "0: Sets Temperature Sensor high threshold to..,1: Sets Temperature Sensor high threshold to.."
|
|
newline
|
|
bitfld.long 0x4 0. "PSWBU,Enables the backup domain power source to automatically switch from VDDIN33 to VBAT supply when security module enters 'backup' mode. Refer to SFRBU specification for details on backup power switch control." "0,1"
|
|
tree.end
|
|
tree "SFR (Special Function Registers)"
|
|
base ad:0xE1624000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "OHCIICR,OHCI Interrupt Configuration Register"
|
|
bitfld.long 0x0 10. "SUSPEND2,USB PORT 2" "0: Suspends controlled by EHCI-OCHI.,1: Forces the suspend for PORTx."
|
|
bitfld.long 0x0 9. "SUSPEND1,USB PORT 1" "0: Suspends controlled by EHCI-OCHI.,1: Forces the suspend for PORTx."
|
|
newline
|
|
bitfld.long 0x0 8. "SUSPEND0,USB PORT 0" "0: Suspends controlled by EHCI-OCHI.,1: Forces the suspend for PORTx."
|
|
bitfld.long 0x0 1. "APPSTART," "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ARIE,OHCI Asynchronous Resume Interrupt Enable" "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "OHCIISR,OHCI Interrupt Status Register"
|
|
bitfld.long 0x0 2. "RIS2,OHCI Resume Interrupt Status Port 2" "0: OHCI port resume not detected.,1: OHCI port resume detected."
|
|
bitfld.long 0x0 1. "RIS1,OHCI Resume Interrupt Status Port 1" "0: OHCI port resume not detected.,1: OHCI port resume detected."
|
|
newline
|
|
bitfld.long 0x0 0. "RIS0,OHCI Resume Interrupt Status Port 0" "0: OHCI port resume not detected.,1: OHCI port resume detected."
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY value..,1: Enables the write protection if WPKEY value.."
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPSRC,Write Protection Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
|
|
group.long 0x200C++0x3
|
|
line.long 0x0 "DEBUG,Debug Register"
|
|
bitfld.long 0x0 0. "PROT,Protection Debug" "0: Protection debug is disabled.,1: Protection debug is enabled."
|
|
group.long 0x2028++0xB
|
|
line.long 0x0 "HSS_AXIQOS,HSS AXI QOS Register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "WRITE,QOS value for write transfer from HSS to the DDR controller"
|
|
hexmask.long.byte 0x0 0.--3. 1. "READ,QOS value for read transfer from HSS to the DDR controller"
|
|
line.long 0x4 "UDDRC,UDDRC Register"
|
|
bitfld.long 0x4 0. "DIS_DECERR,Disable Decode Error" "0: Enables decode error when reading a non-existing..,1: Disables decode error when reading a.."
|
|
line.long 0x8 "CAN_SRAM_SEL,SFR CAN SRAM Selection Register"
|
|
bitfld.long 0x8 5. "UPPER_CAN5,CANx Upper 64K SRAM Selection" "0: CANx accesses the lower 64K SRAM.,1: CANx accesses the upper 64K SRAM."
|
|
bitfld.long 0x8 4. "UPPER_CAN4,CANx Upper 64K SRAM Selection" "0: CANx accesses the lower 64K SRAM.,1: CANx accesses the upper 64K SRAM."
|
|
newline
|
|
bitfld.long 0x8 3. "UPPER_CAN3,CANx Upper 64K SRAM Selection" "0: CANx accesses the lower 64K SRAM.,1: CANx accesses the upper 64K SRAM."
|
|
bitfld.long 0x8 2. "UPPER_CAN2,CANx Upper 64K SRAM Selection" "0: CANx accesses the lower 64K SRAM.,1: CANx accesses the upper 64K SRAM."
|
|
newline
|
|
bitfld.long 0x8 1. "UPPER_CAN1,CANx Upper 64K SRAM Selection" "0: CANx accesses the lower 64K SRAM.,1: CANx accesses the upper 64K SRAM."
|
|
bitfld.long 0x8 0. "UPPER_CAN0,CANx Upper 64K SRAM Selection" "0: CANx accesses the lower 64K SRAM.,1: CANx accesses the upper 64K SRAM."
|
|
tree.end
|
|
tree "SFRBU (Special Function Registers Backup)"
|
|
base ad:0xE0008000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "PSWBU,Power Switch BU Control"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "PSWKEY,Specific Value Mandatory to Allow Writing of Other Register Bits (Write-only)"
|
|
bitfld.long 0x0 2. "STATE,Power Switch BU State (Read-only)" "0: LDO BU Supply source is VBAT.,1: LDO BU Supply source is VDDIN33."
|
|
newline
|
|
bitfld.long 0x0 1. "SOFTSWITCH,Power Switch BU Source Selection" "0: LDO Supply source is VBAT.,1: LDO Supply source is VDDIN33."
|
|
bitfld.long 0x0 0. "CTRL,Power Switch BU Control" "0: Power Switch BU is controlled by hardware..,1: Power Switch BU is controlled by software.."
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "LDO25CR,VDDANAout LDO Pulldown Value"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "LDOANAKEY,Specific value mandatory to allow writing of other register bits"
|
|
bitfld.long 0x0 3. "STATE,LDOANA Switch On/Off Control" "0: Switches LDOANA on.,1: Switches LDOANA off."
|
|
newline
|
|
bitfld.long 0x0 2. "LOWPOWER,LDOANA Low-Power Mode Control" "0: Switches LDOANA Low-power mode off.,1: Switches LDOANA Low-power mode on."
|
|
bitfld.long 0x0 0.--1. "PD_VALUE,LDOANA Pull-down Value" "0: No pull-down plugged on LDO output when off.,1: 500 Ohms pull-down plugged on LDO output when off.,2: 200 Ohms pull-down plugged on LDO output when off.,3: 100 Ohms pull-down plugged on LDO output when off."
|
|
line.long 0x4 "DDRPWR,DDR Power Control"
|
|
bitfld.long 0x4 0. "STATE,DDR Power Mode State" "0: DDR Power mode is on.,1: DDR Power mode is off."
|
|
tree.end
|
|
tree "SHA (Secure Hash Algorithm)"
|
|
base ad:0xE1814000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 24. "UNLOCK,Unlock Processing" "0: No effect.,1: Unlocks the processing in case of abnormal event.."
|
|
bitfld.long 0x0 13. "WUIEHV,Write User Initial or Expected Hash Values" "0: SHA_IDATARx accesses are routed to the data..,1: SHA_IDATARx accesses are routed to the internal.."
|
|
newline
|
|
bitfld.long 0x0 12. "WUIHV,Write User Initial Hash Values" "0: SHA_IDATARx accesses are routed to the data..,1: SHA_IDATARx accesses are routed to the internal.."
|
|
bitfld.long 0x0 8. "SWRST,Software Reset" "0: No effect.,1: Resets the SHA. A software-triggered hardware.."
|
|
newline
|
|
bitfld.long 0x0 4. "FIRST,First Block of a Message" "0: No effect.,1: Indicates that the next block to process is the.."
|
|
bitfld.long 0x0 0. "START,Start Processing" "0: No effect.,1: Starts manual hash algorithm process."
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "CHKCNT,Check Counter"
|
|
bitfld.long 0x0 24.--25. "CHECK,Hash Check" "0: No check is performed,1: Check is performed with expected hash stored in..,2: Check is performed with expected hash provided..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "DUALBUFF,Dual Input Buffer" "0: SHA_IDATARx and SHA_IODATARx cannot be written..,1: SHA_IDATARx and SHA_IODATARx can be written.."
|
|
bitfld.long 0x0 15. "TMPLCK,Tamper Lock Enable" "0: A tamper event has no effect.,1: A tamper event locks the SHA until the tamper.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "ALGO,SHA Algorithm"
|
|
bitfld.long 0x0 7. "BPE,Block Processing End" "0: BPE must be cleared when a DMA transfers data.,1: When processing small messages data transfer by.."
|
|
newline
|
|
bitfld.long 0x0 6. "UIEHV,User Initial or Expected Hash Value Registers" "0: The SHA algorithm is started with the standard..,1: The SHA algorithm is started with the user.."
|
|
bitfld.long 0x0 5. "UIHV,User Initial Hash Value Registers" "0: The SHA algorithm is started with the standard..,1: The SHA algorithm is started with the user.."
|
|
newline
|
|
bitfld.long 0x0 4. "PROCDLY,Processing Delay" "0: SHA processing runtime is the shortest one,1: SHA processing runtime is the longest one.."
|
|
bitfld.long 0x0 3. "AOE,Always ON Enable" "0: The SHA operates in functional operating modes.,1: As soon as a START command is written the SHA.."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SMOD,Start Mode" "0: Manual mode,1: Auto mode,2: SHA_IDATAR0 access only mode (mandatory when DMA..,?"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 24. "SECE,Security and/or Safety Event Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 16. "CHECKF,Check Done Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "URAD,Unspecified Register Access Detection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 24. "SECE,Security and/or Safety Event Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 16. "CHECKF,Check Done Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "URAD,Unspecified Register Access Detection Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "DATRDY,Data Ready Interrupt Disable" "0,1"
|
|
rgroup.long 0x18++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 24. "SECE,Security and/or Safety Event Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 16. "CHECKF,Check Done Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "URAD,Unspecified Register Access Detection Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 24. "SECE,Security and/or Safety Event" "0: There is no report in SHA_WPSR.,1: There is a Security and/or Safety Event reported.."
|
|
hexmask.long.byte 0x4 20.--23. 1. "CHKST,Check Status (cleared by writing START or SWRST bits in SHA_CR or by reading SHA_IODATARx)"
|
|
newline
|
|
bitfld.long 0x4 16. "CHECKF,Check Done Status (cleared by writing START or SWRST bits in SHA_CR or by reading SHA_IODATARx)" "0: Hash check has not been computed.,1: Hash check has been computed status is available.."
|
|
bitfld.long 0x4 12.--14. "URAT,Unspecified Register Access Type (cleared by writing a 1 to SWRST bit in SHA_CR)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 8. "URAD,Unspecified Register Access Detection Status (cleared by writing a 1 to SWRST bit in SHA_CR)" "0: No unspecified register access has been detected..,1: At least one unspecified register access has.."
|
|
bitfld.long 0x4 4. "WRDY,Input Data Register Write Ready" "0: SHA_IDATAR0 cannot be written,1: SHA_IDATAR0 can be written"
|
|
newline
|
|
bitfld.long 0x4 0. "DATRDY,Data Ready (cleared by writing a 1 to bit SWRST or START in SHA_CR or by reading SHA_IODATARx)" "0: Output data is not valid.,1: 512/1024-bit block process is completed."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "MSR,Message Size Register"
|
|
hexmask.long 0x0 0.--31. 1. "MSGSIZE,Message Size"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "BCR,Bytes Count Register"
|
|
hexmask.long 0x0 0.--31. 1. "BYTCNT,Remaining Byte Count Before Auto Padding"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x40)++0x3
|
|
line.long 0x0 "IDATAR[$1],Input Data x Register"
|
|
hexmask.long 0x0 0.--31. 1. "IDATA,Input Data"
|
|
repeat.end
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x80)++0x3
|
|
line.long 0x0 "IODATAR[$1],Input/Output Data x Register"
|
|
hexmask.long 0x0 0.--31. 1. "IODATA,Input/Output Data"
|
|
repeat.end
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 5.--6. "ACTION,Action on Abnormal Event Detection" "0: No action (stop or clear key) is performed when..,1: If a processing is in progress when the..,2: If a processing is in progress when the..,3: If a processing is in progress when the.."
|
|
newline
|
|
bitfld.long 0x0 4. "FIRSTE,First Error Report Enable" "0: The last write protection violation source is..,1: Only the first write protection violation source.."
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interruption Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Configuration Enable" "0: Disables the write protection on configuration..,1: Enables the write protection on configuration.."
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
bitfld.long 0x0 31. "ECLASS,Software Error Class (cleared on read)" "0: An abnormal access that does not affect system..,1: An access is performed into key input data.."
|
|
hexmask.long.byte 0x0 24.--27. 1. "SWETYP,Software Error Type (cleared on read)"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 3. "SWE,Software Control Error (cleared on read)" "0: No software error has occurred since the last..,1: A software error has occurred since the last.."
|
|
newline
|
|
bitfld.long 0x0 2. "SEQE,Internal Sequencer Error (cleared on read)" "0: No peripheral internal sequencer error has..,1: A peripheral internal sequencer error has.."
|
|
bitfld.long 0x0 1. "CGD,Clock Glitch Detected (cleared on read)" "0: The clock monitoring circuitry has not been..,1: The clock monitoring circuitry has been.."
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status (cleared on read)" "0: No write protect violation has occurred since..,1: A write protect violation has occurred since the.."
|
|
tree.end
|
|
tree "SHDWC (Shutdown Controller)"
|
|
base ad:0xE001D010
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "SHDW_CR,Control Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "KEY,Password"
|
|
bitfld.long 0x0 22. "LPMDIS,LPM Pad Disable" "0: No effect.,1: The LPM pad is set low (external regulator is.."
|
|
newline
|
|
bitfld.long 0x0 21. "LPMEN,LPM Pad Enable" "0: No effect.,1: The LPM pad is set high (external regulator is.."
|
|
bitfld.long 0x0 0. "SHDW,Shutdown Command" "0: No effect.,1: If KEY value is correct asserts the SHDN pin."
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "SHDW_MR,Mode Register"
|
|
bitfld.long 0x0 24.--26. "WKUPDBC,Wakeup Inputs Debouncer Period" "0: Immediate no debouncing detected active at least..,1: PIOBUx shall be in its active state for at least..,2: PIOBUx shall be in its active state for at least..,3: PIOBUx shall be in its active state for at least..,4: PIOBUx shall be in its active state for at least..,5: PIOBUx shall be in its active state for at least..,?,?"
|
|
bitfld.long 0x0 20. "AUTOLPM,Automatic LPM Pad Management" "0: The LPM pad is never automatically modified by..,1: The LPM pad is automatically modified by the.."
|
|
newline
|
|
bitfld.long 0x0 17. "RTCWKEN,Real-time Clock Wake-up Enable" "0: The RTC Alarm signal has no effect on the SHDWC.,1: The RTC Alarm signal forces the de-assertion of.."
|
|
bitfld.long 0x0 16. "RTTWKEN,Real-time Timer Wake-up Enable" "0: The RTT Alarm signal has no effect on the SHDWC.,1: The RTT Alarm signal forces the de-assertion of.."
|
|
newline
|
|
bitfld.long 0x0 8.--10. "LPDBC,Low-Power Debouncer Period" "0: Disables the low-power debouncers.,1: WKUP0/1 in active state for at least 2 RTCOUTx..,2: WKUP0/1 in active state for at least 3 RTCOUTx..,3: WKUP0/1 in active state for at least 4 RTCOUTx..,4: WKUP0/1 in active state for at least 5 RTCOUTx..,5: WKUP0/1 in active state for at least 6 RTCOUTx..,6: WKUP0/1 in active state for at least 7 RTCOUTx..,7: WKUP0/1 in active state for at least 8 RTCOUTx.."
|
|
bitfld.long 0x0 1. "LPDBCEN1,Low-Power Debouncer Enable WKUPx" "0: The WKUPx input pin is not connected to the..,1: The WKUPx input pin is connected to the.."
|
|
newline
|
|
bitfld.long 0x0 0. "LPDBCEN0,Low-Power Debouncer Enable WKUPx" "0: The WKUPx input pin is not connected to the..,1: The WKUPx input pin is connected to the.."
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "SHDW_SR,Status Register"
|
|
bitfld.long 0x0 21. "WKUPIS5,Wakeup 0 to 15 Input Status" "0: The corresponding wakeup input is disabled or..,1: The corresponding wakeup input was active at the.."
|
|
bitfld.long 0x0 20. "WKUPIS4,Wakeup 0 to 15 Input Status" "0: The corresponding wakeup input is disabled or..,1: The corresponding wakeup input was active at the.."
|
|
newline
|
|
bitfld.long 0x0 19. "WKUPIS3,Wakeup 0 to 15 Input Status" "0: The corresponding wakeup input is disabled or..,1: The corresponding wakeup input was active at the.."
|
|
bitfld.long 0x0 18. "WKUPIS2,Wakeup 0 to 15 Input Status" "0: The corresponding wakeup input is disabled or..,1: The corresponding wakeup input was active at the.."
|
|
newline
|
|
bitfld.long 0x0 17. "WKUPIS1,Wakeup 0 to 15 Input Status" "0: The corresponding wakeup input is disabled or..,1: The corresponding wakeup input was active at the.."
|
|
bitfld.long 0x0 16. "WKUPIS0,Wakeup 0 to 15 Input Status" "0: The corresponding wakeup input is disabled or..,1: The corresponding wakeup input was active at the.."
|
|
newline
|
|
bitfld.long 0x0 8. "LPM,Low-Power Mode Pad Status" "0: The LPM pad is currently set to 0.,1: The LPM pad is currently set to 1."
|
|
bitfld.long 0x0 5. "RTCWK,Real-time Clock Wake-up" "0: No wake-up alarm from the RTC occurred since the..,1: At least one wake-up alarm from the RTC occurred.."
|
|
newline
|
|
bitfld.long 0x0 4. "RTTWK,Real-time Timer Wake-up" "0: No wake-up alarm from the RTT occurred since the..,1: At least one wake-up alarm from the RTT occurred.."
|
|
bitfld.long 0x0 0. "WKUPS,PIOBU WKUP Wakeup Status" "0: No wakeup due to the assertion of the PIOBU WKUP..,1: At least one wakeup due to the assertion of the.."
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "SHDW_WUIR,Wakeup Inputs Register"
|
|
bitfld.long 0x0 21. "WKUPT5,Wakeup 0 to 15 Input Type" "0: A falling edge followed by a low level on the..,1: A rising edge followed by a high level on the.."
|
|
bitfld.long 0x0 20. "WKUPT4,Wakeup 0 to 15 Input Type" "0: A falling edge followed by a low level on the..,1: A rising edge followed by a high level on the.."
|
|
newline
|
|
bitfld.long 0x0 19. "WKUPT3,Wakeup 0 to 15 Input Type" "0: A falling edge followed by a low level on the..,1: A rising edge followed by a high level on the.."
|
|
bitfld.long 0x0 18. "WKUPT2,Wakeup 0 to 15 Input Type" "0: A falling edge followed by a low level on the..,1: A rising edge followed by a high level on the.."
|
|
newline
|
|
bitfld.long 0x0 17. "WKUPT1,Wakeup 0 to 15 Input Type" "0: A falling edge followed by a low level on the..,1: A rising edge followed by a high level on the.."
|
|
bitfld.long 0x0 16. "WKUPT0,Wakeup 0 to 15 Input Type" "0: A falling edge followed by a low level on the..,1: A rising edge followed by a high level on the.."
|
|
newline
|
|
bitfld.long 0x0 5. "WKUPEN5,Wakeup 0 to 15 Input Enable" "0: The corresponding wakeup input has no wakeup..,1: The corresponding wakeup input forces wakeup of.."
|
|
bitfld.long 0x0 4. "WKUPEN4,Wakeup 0 to 15 Input Enable" "0: The corresponding wakeup input has no wakeup..,1: The corresponding wakeup input forces wakeup of.."
|
|
newline
|
|
bitfld.long 0x0 3. "WKUPEN3,Wakeup 0 to 15 Input Enable" "0: The corresponding wakeup input has no wakeup..,1: The corresponding wakeup input forces wakeup of.."
|
|
bitfld.long 0x0 2. "WKUPEN2,Wakeup 0 to 15 Input Enable" "0: The corresponding wakeup input has no wakeup..,1: The corresponding wakeup input forces wakeup of.."
|
|
newline
|
|
bitfld.long 0x0 1. "WKUPEN1,Wakeup 0 to 15 Input Enable" "0: The corresponding wakeup input has no wakeup..,1: The corresponding wakeup input forces wakeup of.."
|
|
bitfld.long 0x0 0. "WKUPEN0,Wakeup 0 to 15 Input Enable" "0: The corresponding wakeup input has no wakeup..,1: The corresponding wakeup input forces wakeup of.."
|
|
tree.end
|
|
tree "SPDIFRX (Sony/Philips Digital Interface Receiver)"
|
|
base ad:0xE1614000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0: No effect.,1: Resets the SPDIF receiver."
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 24. "AUTORST,Consecutive Preamble Error Threshold Automatic Restart" "0: No action whatever the number of consecutive..,1: If 16 consecutive preamble errors are detected.."
|
|
bitfld.long 0x0 8. "SBMODE,Start of Block Bit Mode" "0: Whatever the preamble code the sample is loaded..,1: The sample is loaded in FIFO only if an Start of.."
|
|
newline
|
|
bitfld.long 0x0 7. "PACK,Packed Data Mode in Receive Holding Register" "0: Each read of SPDIFRX_RHR contains 1 sample and..,1: The 32-bit SPDIFRX_RHR contains only payload.."
|
|
bitfld.long 0x0 4.--5. "DATAWIDTH,Sample Data Width" "0: The complete data field is stored in FIFO.,1: Only the 20 MSB are stored in the FIFO.,2: Only the 16 MSB are stored in the FIFO.,?"
|
|
newline
|
|
bitfld.long 0x0 3. "PBMODE,Parity Bit Mode" "0: Parity check enabled on data payload.,1: There is no parity check on data payload."
|
|
bitfld.long 0x0 2. "ENDIAN,Data Word Endian Mode" "0: Little-endian mode for 24-bit samples.,1: Big-endian mode for 24-bit samples."
|
|
newline
|
|
bitfld.long 0x0 1. "VBMODE,Validity Bit Mode" "0: Whatever the validity bit value is the sample is..,1: The sample is loaded in FIFO only if the.."
|
|
bitfld.long 0x0 0. "RXEN,SPDIF Receive Enable" "0: SPDIF receiver is disabled.,1: SPDIF receiver is enabled."
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 14. "CP_ERR,16 Consecutive Preamble Errors Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 13. "PRE_ERR,Preamble Error (code violation) Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "NRZ_ERR,NRZ Biphase Mark Error in payload data (code violation) Enable" "0,1"
|
|
bitfld.long 0x0 11. "BLOCKST,Start of Block Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SECE,Security Report Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 9. "C2SC,Bit 0 to 31 Channel 2 Status Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "C1SC,Bit 0 to 31 Channel 1 Status Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 7. "RXFULL,Receiver FIFO Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVERRUN,FIFO Overrun Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 5. "PAR_ERR,Parity Bit Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SFE,Sampling Frequency Change Event Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 3. "BLOCKEND,End of Block Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "LOSS,Loss of Signal Activity While Locked Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "LOCKED,Receiver Synchronized Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,Receive Data Ready Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 14. "CP_ERR,16 Consecutive Preamble Errors Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 13. "PRE_ERR,Preamble Error (code violation) Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "NRZ_ERR,NRZ Biphase Mark Error in payload data (code violation) Disable" "0,1"
|
|
bitfld.long 0x4 11. "BLOCKST,Start of Block Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SECE,Security Report Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 9. "C2SC,Bit 0 to 31 Channel 2 Status Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "C1SC,Bit 0 to 31 Channel 1 Status Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 7. "RXFULL,Receiver FIFO Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "OVERRUN,FIFO Overrun Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 5. "PAR_ERR,Parity Bit Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SFE,Sampling Frequency Change Event Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 3. "BLOCKEND,End of Block Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "LOSS,Loss of Signal Activity While Locked Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 1. "LOCKED,Receiver Synchronized Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,Receive Data Ready Interrupt Disable" "0,1"
|
|
rgroup.long 0x18++0xF
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 14. "CP_ERR,16 Consecutive Preamble Errors Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 13. "PRE_ERR,Preamble Error (code violation) Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "NRZ_ERR,NRZ Biphase Mark Error in payload data (code violation) Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 11. "BLOCKST,Start of Block Interrupt Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SECE,Security Report Interrupt Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 9. "C2SC,Bit 0 to 31 Channel 2 Status Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "C1SC,Bit 0 to 31 Channel 1 Status Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 7. "RXFULL,Receiver FIFO Full Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVERRUN,FIFO Overrun Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 5. "PAR_ERR,Parity Bit Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SFE,Sampling Frequency Change Event Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 3. "BLOCKEND,End of Block Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "LOSS,Loss of Signal Activity While Locked Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 1. "LOCKED,Receiver Synchronized Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,Receive Data Ready Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 14. "CP_ERR,16 Consecutive Preamble Errors Interrupt Status (cleared on read)" "0,1"
|
|
bitfld.long 0x4 13. "PRE_ERR,Preamble Error (code violation) Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "NRZ_ERR,NRZ Biphase Mark Error in payload data (code violation) Status (cleared on read)" "0,1"
|
|
bitfld.long 0x4 11. "BLOCKST,Start of Block Interrupt Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SECE,Security Report Interrupt Status (cleared on read)" "0,1"
|
|
bitfld.long 0x4 9. "C2SC,Bit 0 to 31 Channel 2 Status Change (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "C1SC,Bit 0 to 31 Channel 1 Status Change (cleared on read)" "0,1"
|
|
bitfld.long 0x4 7. "RXFULL,Receiver FIFO Full Interrupt Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "OVERRUN,FIFO Overrun Interrupt Status (cleared on read)" "0,1"
|
|
bitfld.long 0x4 5. "PAR_ERR,Parity Bit Error Interrupt Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SFE,Sampling Frequency Change Event Interrupt Status (cleared on read)" "0,1"
|
|
bitfld.long 0x4 3. "BLOCKEND,End of Block Interrupt Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "LOSS,Loss of Signal Activity While Locked Interrupt Status (cleared on read)" "0,1"
|
|
bitfld.long 0x4 1. "LOCKED,Receiver Synchronized Interrupt Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,Receive Data Ready Interrupt Status (cleared when reading SPDIFRX_RHR)" "0,1"
|
|
line.long 0x8 "RSR,Status Register"
|
|
hexmask.long.word 0x8 16.--27. 1. "IFS,Image of Sampling Frequency"
|
|
bitfld.long 0x8 3. "NOSIGNAL,No Signal on Receive Line" "0: The receiver is synchronized or searching for..,1: The receiver is not able to find any activity.."
|
|
newline
|
|
bitfld.long 0x8 2. "LOWF,Low Clock Frequency provided on GCLK Clock" "0: The receiver is synchronized or the receiver is..,1: The receiver is not able to recover the protocol.."
|
|
bitfld.long 0x8 1. "BADF,Bad Format Detected on SPDIF RX Line" "0: The receiver is synchronized or the receiver is..,1: The receiver is not able to detect a SPDIF.."
|
|
newline
|
|
bitfld.long 0x8 0. "ULOCK,Unlocked Receiver" "0: The receiver is synchronized and loads data.,1: The receiver is not locked because it is.."
|
|
line.long 0xC "RHR,Holding Register"
|
|
hexmask.long 0xC 0.--31. 1. "DATA,Channel 1 and 2 Data"
|
|
repeat 2. (list 0x0 0x1)(list ad:0xE1614030 ad:0xE1614060)
|
|
tree "SPDIFRX_CH[$1]"
|
|
base $2
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "CHxSR[$1],Channel X Status Register x"
|
|
hexmask.long 0x0 0.--31. 1. "CHSTATUS,Channel X Status Data"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x18)++0x3
|
|
line.long 0x0 "CHxUD[$1],Channel X User Data Register x"
|
|
hexmask.long 0x0 0.--31. 1. "CHUSERDATA,Channel X User Data"
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
base ad:0xE1614000
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 4. "FIRSTE,First Error Report Enable" "0: The last write protection violation source is..,1: Only the first write protection violation source.."
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Register Enable" "0: Disables the write protection on the Control..,1: Enables the write protection on the Control.."
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on Interrupt..,1: Enables the write protection on Interrupt.."
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection is enabled. All.."
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
bitfld.long 0x0 24.--25. "SWETYP,Software Error Type (cleared on read)" "0: A write-only register has been read (warning).,1: A write access has been performed on a read-only..,2: Access to an undefined address (warning).,?"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPSRC,Write Protection Source"
|
|
newline
|
|
bitfld.long 0x0 3. "SWE,Software Control Error (cleared on read)" "0: No software error has occurred since the last..,1: A software error has occurred since the last.."
|
|
bitfld.long 0x0 2. "SEQE,Internal Sequencer Error (cleared on read)" "0: No peripheral internal sequencer error has..,1: A peripheral internal sequencer error has.."
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status (cleared on read)" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
|
|
rgroup.long 0xFC++0x3
|
|
line.long 0x0 "VERSION,Version Register"
|
|
bitfld.long 0x0 16.--18. "MFN,Metal Fix Number" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 0.--11. 1. "VERSION,Version"
|
|
tree.end
|
|
tree "SPDIFTX (Sony/Philips Digital Interface Transmitter)"
|
|
base ad:0xE1618000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,SPDIF Transmitter Control Register"
|
|
bitfld.long 0x0 1. "FCLR,FIFO clear" "0: No effect.,1: Empties Channel 1 and Channel 2 FIFOs"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0: No effect.,1: Resets the SPDIFTX interface."
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "MR,SPDIF Transmitter Mode Register"
|
|
bitfld.long 0x0 31. "DUDCPY,Disable User Data Copy" "0: Any data written in SPDDIFTX_CH1UDx registers is..,1: SPDDIFTX_CH1UDx and SPDDIFTX_CH2UDx are.."
|
|
bitfld.long 0x0 30. "DCSCPY,Disable Channel Status Copy" "0: Any data written in SPDDIFTX_CH1Sx registers is..,1: SPDDIFTX_CH1Sx and SPDDIFTX_CH2Sx are independant."
|
|
newline
|
|
bitfld.long 0x0 28.--29. "BPS,Bytes Per Sample" "0: SPDIFTX_CDR data holding operating mode is..,1: SPDIFTX_CDR data holding operating mode is..,2: SPDIFTX_CDR data holding operating mode is..,3: SPDIFTX_CDR data holding operating mode is.."
|
|
bitfld.long 0x0 27. "DNFR,Disable Null Frame on underrrun" "0: In case of Underrun (SPDIFTX_ISR.TXEMPTY flag is..,1: In case of Underrun (SPDIFTX_ISR.TXEMPTY flag is.."
|
|
newline
|
|
bitfld.long 0x0 25. "VALID2,Validity Bit Channel 2" "0,1"
|
|
bitfld.long 0x0 24. "VALID1,Validity Bit Channel 1" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "CHUNK,DMA Chunk Size"
|
|
hexmask.long.byte 0x0 8.--13. 1. "VBPS,Valid Bits Per Sample"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "CMODE,Common Audio Register Transfer Mode (if BPS=2)" "0: SPDIFTX_CDR.CDR[25:24] indicates the channel on..,1: The data are stored alternately in the FIFO of..,2: This mode is optimized for 24-bit data compacted..,3: Control bits (preamble validity user data.."
|
|
bitfld.long 0x0 3. "JUSTIFY,Data Justification" "0: Least Significant Bit justification. The valid..,1: Most Significant Bit justification. The valid.."
|
|
newline
|
|
bitfld.long 0x0 2. "ENDIAN,Data Word Endian Mode" "0: Little-endian mode.,1: Big-endian mode."
|
|
bitfld.long 0x0 1. "MULTICH,Multichannel Transfer" "0: One channel is sent on channel 1 to SPDIFTX_TX..,1: Two separate channels are sent to SPDIFTX_TX."
|
|
newline
|
|
bitfld.long 0x0 0. "TXEN,SPDIFTX Transmit Enable" "0: SPDIFTX transmission is disabled.,1: SPDIFTX transmission is enabled."
|
|
line.long 0x4 "EMR,SPDIF Transmitter Extended Mode Register"
|
|
bitfld.long 0x4 4. "VALIDM,Validity Bit Mode" "0: Validity bit is defined by SPDIFTX_MR.VALID1 and..,1: Validity bit is defined by the SPDIFTX_CDR.VALID.."
|
|
bitfld.long 0x4 3. "PARM,Parity Mode" "0: Parity bit is automatically set by the SPDIFTX.,1: Parity bit sent is defined by SPDIFTX_CDR.PAR bit."
|
|
newline
|
|
bitfld.long 0x4 2. "CSM,Channel Status Mode" "0: Channel status is defined by SPDIFTX_CHxCSx..,1: Channel status is defined by SPDIFTX_CDR.CS bit."
|
|
bitfld.long 0x4 1. "UDM,User Data Mode" "0: User data is defined by SPDIFTX_CHxUDx registers.,1: User data is defined by SPDIFTX_CDR.UD bit."
|
|
newline
|
|
bitfld.long 0x4 0. "PCM,Preamble Code Mode" "0: Preamble code is generated automatically by the..,1: Preamble code is defined by SPDIFTX_CDR.PC field."
|
|
wgroup.long 0xC++0x3
|
|
line.long 0x0 "CDR,SPDIF Transmitter Common Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "CDR,Common Data Register"
|
|
wgroup.long 0xC++0x3
|
|
line.long 0x0 "CDR_CONTROL_BITS_MODE,SPDIF Transmitter Common Data Register"
|
|
bitfld.long 0x0 28.--29. "PC,Preamble Code" "0: Preamble 'B' will be sent.,1: Preamble 'M' will be sent.,2: Preamble 'W' will be sent.,?"
|
|
bitfld.long 0x0 27. "PAR,Parity" "0: Correct parity bit will be sent.,1: Wrong parity bit will be sent."
|
|
newline
|
|
bitfld.long 0x0 26. "CS,Channel Status" "0,1"
|
|
bitfld.long 0x0 25. "UD,User Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "VALID,Validity Bit" "0: Sample is valid for analog conversion.,1: Sample is not valid for analog conversion."
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CDR,Common Data Register"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "SR,SPDIF Transmitter Status Register"
|
|
bitfld.long 0x0 0. "ENS,Enable Status" "0: SPDIF core is disabled.,1: SPDIF core is enabled"
|
|
wgroup.long 0x14++0x7
|
|
line.long 0x0 "IER,SPDIF Transmitter Interrupt Enable Register"
|
|
bitfld.long 0x0 13. "BEND,Block End Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 12. "TXUDR2,Channel 2 Transmit Under Flow Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TXUDR1,Channel 1 Transmit Under Flow Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 10. "SECE,Security Report Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXRDYCH2,Transmit Ready Channel 2 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 8. "TXRDYCH1,Transmit Ready Channel 1 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UDRDY,User Data Ready Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 6. "CSRDY,Channel Status Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TXOVR,Transmit Over Flow Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "TXUDR,Transmit Under Flow Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TXCHUNK,Transmit FIFO Chunk Size Empty Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "TXFULL,Transmit FIFO Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXEMPTY,Transmit FIFO Empty Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "TXRDY,Transmit Ready Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,SPDIF Transmitter Interrupt Disable Register"
|
|
bitfld.long 0x4 13. "BEND,Block End Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 12. "TXUDR2,Channel 2 Transmit Under Flow Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "TXUDR1,Channel 1 Transmit Under Flow Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 10. "SECE,Security Report Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXRDYCH2,Transmit Ready Channel 2 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 8. "TXRDYCH1,Transmit Ready Channel 1 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "UDRDY,User Data Ready Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 6. "CSRDY,Channel Status Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "TXOVR,Transmit Over Flow Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 4. "TXUDR,Transmit Under Flow Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "TXCHUNK,Transmit FIFO Chunk Size Empty Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 2. "TXFULL,Transmit FIFO Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXEMPTY,Transmit FIFO Empty Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "TXRDY,Transmit Ready Interrupt Disable" "0,1"
|
|
rgroup.long 0x1C++0xB
|
|
line.long 0x0 "IMR,SPDIF Transmitter Interrupt Mask Register"
|
|
bitfld.long 0x0 13. "BEND,Block End Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 12. "TXUDR2,Channel 2 Transmit Under Flow Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TXUDR1,Channel 1 Transmit Under Flow Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 10. "SECE,Security Report Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXRDYCH2,Transmit Ready Channel 2 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 8. "TXRDYCH1,Transmit Ready Channel 1 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UDRDY,User Data Ready Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 6. "CSRDY,Channel Status Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TXOVR,Transmit Over Flow Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 4. "TXUDR,Transmit Under Flow Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TXCHUNK,Transmit FIFO Chunk Size Empty Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "TXFULL,Transmit FIFO Full Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXEMPTY,Transmit FIFO Empty Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "TXRDY,Transmit Ready Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,SPDIF Transmitter Interrupt Status Register"
|
|
bitfld.long 0x4 13. "BEND,Block End Status (cleared on read)" "0: No Block End event occurred since last..,1: At least one Block End event occurred since last.."
|
|
bitfld.long 0x4 12. "TXUDR2,Channel 2 Transmit Under Flow Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "TXUDR1,Channel 1 Transmit Under Flow Status (cleared on read)" "0,1"
|
|
bitfld.long 0x4 10. "SECE,Security Report Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXRDYCH2,Transmit Ready Status Channel 2 (cleared when channel 2 FIFO is full)" "0,1"
|
|
bitfld.long 0x4 8. "TXRDYCH1,Transmit Ready Status Channel 1 (cleared when channel 1 FIFO is full)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "UDRDY,User Data Ready Status (cleared writing SPDIFTX_CHxUDR0 register)" "0,1"
|
|
bitfld.long 0x4 6. "CSRDY,Channel Status Ready Status (cleared writing SPDIFTX_CHxSR0 register)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "TXOVR,Transmit Over Flow Status (cleared on read)" "0,1"
|
|
bitfld.long 0x4 4. "TXUDR,Transmit Under Flow Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "TXCHUNK,Transmit FIFO Chunk Size Empty Status (cleared by writing CHUNK data in SPDIFTX_CDR)" "0,1"
|
|
bitfld.long 0x4 2. "TXFULL,Transmit FIFO Full Status (cleared when data are sent or writing the SPDIFTX_CR.FCLR bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXEMPTY,Transmit FIFO Empty Status (cleared by writing SPDIFTX_CDR SPDIFTX_AW1 or SPDIFTX_AW2 register)" "0,1"
|
|
bitfld.long 0x4 0. "TXRDY,Transmit Ready Status (cleared when both channel 1 and 2 FIFOs are full)" "0,1"
|
|
line.long 0x8 "SFI,SPDIF Transmitter Subframe Index Register"
|
|
hexmask.long.word 0x8 0.--9. 1. "SFI,Transmit Subframe Index"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x30)++0x3
|
|
line.long 0x0 "AW[$1],SPDIF Transmitter Channel 1 Audio Word"
|
|
hexmask.long 0x0 0.--31. 1. "AW,Audio Word Channel 1"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x50)++0x3
|
|
line.long 0x0 "CH1UD[$1],SPDIF Transmitter User Data 1 Register x"
|
|
hexmask.long 0x0 0.--31. 1. "CHUD,Channel 1 User Data Word"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x68)++0x3
|
|
line.long 0x0 "CH2UD[$1],SPDIF Transmitter User Data 2 Register x"
|
|
hexmask.long 0x0 0.--31. 1. "CHUD,Channel 2 User Data Word"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x80)++0x3
|
|
line.long 0x0 "CH1S[$1],SPDIF Transmitter Channel Status 1 Register x"
|
|
hexmask.long 0x0 0.--31. 1. "CHS,Channel 1 Status Word"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x98)++0x3
|
|
line.long 0x0 "CH2S[$1],SPDIF Transmitter Channel Status 2 Register x"
|
|
hexmask.long 0x0 0.--31. 1. "CHS,Channel 2 Status Word"
|
|
repeat.end
|
|
group.long 0xE0++0x3
|
|
line.long 0x0 "WPMR,SPDIF Transmitter Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 4. "FIRSTE,First Error Report Enable" "0: The last write protection violation source is..,1: Only the first write protection violation source.."
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Register Enable" "0: Disables the write protection on the Control..,1: Enables the write protection on the Control.."
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on Interrupt..,1: Enables the write protection on Interrupt.."
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
|
|
rgroup.long 0xE4++0x3
|
|
line.long 0x0 "WPSR,SPDIF Transmitter Write Protection Status Register"
|
|
bitfld.long 0x0 24.--25. "SWETYP,Software Error Type (cleared on read)" "0: A write-only register has been read (warning).,1: A write access has been performed on a read-only..,2: Access to an undefined address (warning).,?"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 3. "SWE,Software Control Error (cleared on read)" "0: No software error has occurred since the last..,1: A software error has occurred since the last.."
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status (cleared on read)" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
|
|
tree.end
|
|
tree "SSC (Synchronous Serial Controller)"
|
|
base ad:0x0
|
|
tree "SSC0"
|
|
base ad:0xE180C000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 15. "SWRST,Software Reset" "0: No effect.,1: Performs a software reset. Has priority on any.."
|
|
bitfld.long 0x0 9. "TXDIS,Transmit Disable" "0: No effect.,1: Disables Transmit. If a character is currently.."
|
|
newline
|
|
bitfld.long 0x0 8. "TXEN,Transmit Enable" "0: No effect.,1: Enables Transmit if TXDIS is not set."
|
|
bitfld.long 0x0 1. "RXDIS,Receive Disable" "0: No effect.,1: Disables Receive. If a character is currently.."
|
|
newline
|
|
bitfld.long 0x0 0. "RXEN,Receive Enable" "0: No effect.,1: Enables Receive if RXDIS is not set."
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "CMR,Clock Mode Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "DIV,Clock Divider"
|
|
group.long 0x10++0xF
|
|
line.long 0x0 "RCMR,Receive Clock Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PERIOD,Receive Period Divider Selection"
|
|
hexmask.long.byte 0x0 16.--23. 1. "STTDLY,Receive Start Delay"
|
|
newline
|
|
bitfld.long 0x0 12. "STOP,Receive Stop Selection" "0: After completion of a data transfer when..,1: After starting a receive with a Compare 0 the.."
|
|
hexmask.long.byte 0x0 8.--11. 1. "START,Receive Start Selection"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CKG,Receive Clock Gating Selection" "0: None,1: Receive Clock enabled only if RF Low,2: Receive Clock enabled only if RF High,?"
|
|
bitfld.long 0x0 5. "CKI,Receive Clock Inversion" "0: The data inputs (Data and Frame Sync signals)..,1: The data inputs (Data and Frame Sync signals).."
|
|
newline
|
|
bitfld.long 0x0 2.--4. "CKO,Receive Clock Output Mode Selection" "0: None RK pin is an input,1: Continuous Receive Clock RK pin is an output,2: Receive Clock only during data transfers RK pin..,?,?,?,?,?"
|
|
bitfld.long 0x0 0.--1. "CKS,Receive Clock Selection" "0: Divided Clock,1: TK Clock signal,2: RK pin,?"
|
|
line.long 0x4 "RFMR,Receive Frame Mode Register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "FSLEN_EXT,FSLEN Field Extension"
|
|
bitfld.long 0x4 24. "FSEDGE,Frame Sync Edge Detection" "0: Positive Edge Detection,1: Negative Edge Detection"
|
|
newline
|
|
bitfld.long 0x4 20.--22. "FSOS,Receive Frame Sync Output Selection" "0: None RF pin is an input,1: Negative Pulse RF pin is an output,2: Positive Pulse RF pin is an output,3: Driven Low during data transfer RF pin is an..,4: Driven High during data transfer RF pin is an..,5: Toggling at each start of data transfer RF pin..,?,?"
|
|
hexmask.long.byte 0x4 16.--19. 1. "FSLEN,Receive Frame Sync Length"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "DATNB,Data Number per Frame"
|
|
bitfld.long 0x4 7. "MSBF,Most Significant Bit First" "0: The lowest significant bit of the data register..,1: The most significant bit of the data register is.."
|
|
newline
|
|
bitfld.long 0x4 5. "LOOP,Loop Mode" "0: Normal operating mode.,1: RD is driven by TD RF is driven by TF and TK.."
|
|
hexmask.long.byte 0x4 0.--4. 1. "DATLEN,Data Length"
|
|
line.long 0x8 "TCMR,Transmit Clock Mode Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. "PERIOD,Transmit Period Divider Selection"
|
|
hexmask.long.byte 0x8 16.--23. 1. "STTDLY,Transmit Start Delay"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "START,Transmit Start Selection"
|
|
bitfld.long 0x8 6.--7. "CKG,Transmit Clock Gating Selection" "0: None,1: Transmit Clock enabled only if TF Low,2: Transmit Clock enabled only if TF High,?"
|
|
newline
|
|
bitfld.long 0x8 5. "CKI,Transmit Clock Inversion" "0: The data outputs (Data and Frame Sync signals)..,1: The data outputs (Data and Frame Sync signals).."
|
|
bitfld.long 0x8 2.--4. "CKO,Transmit Clock Output Mode Selection" "0: None TK pin is an input,1: Continuous Transmit Clock TK pin is an output,2: Transmit Clock only during data transfers TK pin..,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "CKS,Transmit Clock Selection" "0: Divided Clock,1: RK Clock signal,2: TK pin,?"
|
|
line.long 0xC "TFMR,Transmit Frame Mode Register"
|
|
hexmask.long.byte 0xC 28.--31. 1. "FSLEN_EXT,FSLEN Field Extension"
|
|
bitfld.long 0xC 24. "FSEDGE,Frame Sync Edge Detection" "0: Positive Edge Detection,1: Negative Edge Detection"
|
|
newline
|
|
bitfld.long 0xC 23. "FSDEN,Frame Sync Data Enable" "0: The TD line is driven with the default value..,1: SSC_TSHR value is shifted out during the.."
|
|
bitfld.long 0xC 20.--22. "FSOS,Transmit Frame Sync Output Selection" "0: None TF pin is an input,1: Negative Pulse TF pin is an output,2: Positive Pulse TF pin is an output,3: Driven Low during data transfer,4: Driven High during data transfer,5: Toggling at each start of data transfer,?,?"
|
|
newline
|
|
hexmask.long.byte 0xC 16.--19. 1. "FSLEN,Transmit Frame Sync Length"
|
|
hexmask.long.byte 0xC 8.--11. 1. "DATNB,Data Number per Frame"
|
|
newline
|
|
bitfld.long 0xC 7. "MSBF,Most Significant Bit First" "0: The lowest significant bit of the data register..,1: The most significant bit of the data register is.."
|
|
bitfld.long 0xC 5. "DATDEF,Data Default Value" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--4. 1. "DATLEN,Data Length"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "RHFR,Receive Holding FIFO Register"
|
|
hexmask.long 0x0 0.--31. 1. "RDAT,Receive Data"
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x0 "THFR,Transmit Holding FIFO Register"
|
|
hexmask.long 0x0 0.--31. 1. "TDAT,Transmit Data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "FFMR,FIFO Mode Register"
|
|
bitfld.long 0x0 16. "RXFIFODIS,Receive FIFO Disable" "0: The receive FIFO is enabled.,1: The receive FIFO is disabled. Only a single.."
|
|
hexmask.long.byte 0x0 8.--11. 1. "THRS,Transmit Start Threshold"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFIFODIS,Transmit FIFO Disable" "0: The transmit FIFO is enabled.,1: The transmit FIFO is disabled. Only a single.."
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "RSHR,Receive Sync. Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RSDAT,Receive Synchronization Data"
|
|
group.long 0x34++0xB
|
|
line.long 0x0 "TSHR,Transmit Sync. Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TSDAT,Transmit Synchronization Data"
|
|
line.long 0x4 "RC0R,Receive Compare 0 Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "CP0,Receive Compare Data 0"
|
|
line.long 0x8 "RC1R,Receive Compare 1 Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "CP1,Receive Compare Data 1"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "RXURWCNT,Receive FIFO Unread Word Count"
|
|
hexmask.long.byte 0x0 24.--27. 1. "TXFRECNT,Transmit FIFO Free Entries Count"
|
|
newline
|
|
bitfld.long 0x0 17. "RXEN,Receive Enable" "0: Receive is disabled.,1: Receive is enabled."
|
|
bitfld.long 0x0 16. "TXEN,Transmit Enable" "0: Transmit is disabled.,1: Transmit is enabled."
|
|
newline
|
|
bitfld.long 0x0 11. "RXSYN,Receive Sync" "0: An Rx Sync has not occurred since the last read..,1: An Rx Sync has occurred since the last read of.."
|
|
bitfld.long 0x0 10. "TXSYN,Transmit Sync" "0: A Tx Sync has not occurred since the last read..,1: A Tx Sync has occurred since the last read of.."
|
|
newline
|
|
bitfld.long 0x0 9. "CP1,Compare 1" "0: A compare 1 has not occurred since the last read..,1: A compare 1 has occurred since the last read of.."
|
|
bitfld.long 0x0 8. "CP0,Compare 0" "0: A compare 0 has not occurred since the last read..,1: A compare 0 has occurred since the last read of.."
|
|
newline
|
|
bitfld.long 0x0 5. "OVRUN,Receive Overrun" "0: No data has been loaded in SSC_RHFR while..,1: Data has been loaded in SSC_RHFR while previous.."
|
|
bitfld.long 0x0 4. "RXRDY,Receive Ready" "0: SSC_RHFR is empty.,1: Data has been received and loaded in SSC_RHFR."
|
|
newline
|
|
bitfld.long 0x0 1. "TXEMPTY,Transmit Empty" "0: Data remains in SSC_THFR or is currently..,1: Last data written in SSC_THFR has been loaded in.."
|
|
bitfld.long 0x0 0. "TXRDY,Transmit Ready" "0: Data has been loaded in SSC_THFR and is waiting..,1: SSC_THFR is empty."
|
|
wgroup.long 0x44++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 11. "RXSYN,Rx Sync Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 10. "TXSYN,Tx Sync Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CP1,Compare 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 8. "CP0,Compare 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRUN,Receive Overrun Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "RXRDY,Receive Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXEMPTY,Transmit Empty Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "TXRDY,Transmit Ready Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 11. "RXSYN,Rx Sync Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 10. "TXSYN,Tx Sync Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CP1,Compare 1 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 8. "CP0,Compare 0 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRUN,Receive Overrun Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 4. "RXRDY,Receive Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXEMPTY,Transmit Empty Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "TXRDY,Transmit Ready Interrupt Disable" "0,1"
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 11. "RXSYN,Rx Sync Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 10. "TXSYN,Tx Sync Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CP1,Compare 1 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 8. "CP0,Compare 0 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRUN,Receive Overrun Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 4. "RXRDY,Receive Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXEMPTY,Transmit Empty Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "TXRDY,Transmit Ready Interrupt Mask" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protect Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
|
|
tree.end
|
|
tree "SSC1"
|
|
base ad:0xE200C000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 15. "SWRST,Software Reset" "0: No effect.,1: Performs a software reset. Has priority on any.."
|
|
bitfld.long 0x0 9. "TXDIS,Transmit Disable" "0: No effect.,1: Disables Transmit. If a character is currently.."
|
|
newline
|
|
bitfld.long 0x0 8. "TXEN,Transmit Enable" "0: No effect.,1: Enables Transmit if TXDIS is not set."
|
|
bitfld.long 0x0 1. "RXDIS,Receive Disable" "0: No effect.,1: Disables Receive. If a character is currently.."
|
|
newline
|
|
bitfld.long 0x0 0. "RXEN,Receive Enable" "0: No effect.,1: Enables Receive if RXDIS is not set."
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "CMR,Clock Mode Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "DIV,Clock Divider"
|
|
group.long 0x10++0xF
|
|
line.long 0x0 "RCMR,Receive Clock Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PERIOD,Receive Period Divider Selection"
|
|
hexmask.long.byte 0x0 16.--23. 1. "STTDLY,Receive Start Delay"
|
|
newline
|
|
bitfld.long 0x0 12. "STOP,Receive Stop Selection" "0: After completion of a data transfer when..,1: After starting a receive with a Compare 0 the.."
|
|
hexmask.long.byte 0x0 8.--11. 1. "START,Receive Start Selection"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CKG,Receive Clock Gating Selection" "0: None,1: Receive Clock enabled only if RF Low,2: Receive Clock enabled only if RF High,?"
|
|
bitfld.long 0x0 5. "CKI,Receive Clock Inversion" "0: The data inputs (Data and Frame Sync signals)..,1: The data inputs (Data and Frame Sync signals).."
|
|
newline
|
|
bitfld.long 0x0 2.--4. "CKO,Receive Clock Output Mode Selection" "0: None RK pin is an input,1: Continuous Receive Clock RK pin is an output,2: Receive Clock only during data transfers RK pin..,?,?,?,?,?"
|
|
bitfld.long 0x0 0.--1. "CKS,Receive Clock Selection" "0: Divided Clock,1: TK Clock signal,2: RK pin,?"
|
|
line.long 0x4 "RFMR,Receive Frame Mode Register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "FSLEN_EXT,FSLEN Field Extension"
|
|
bitfld.long 0x4 24. "FSEDGE,Frame Sync Edge Detection" "0: Positive Edge Detection,1: Negative Edge Detection"
|
|
newline
|
|
bitfld.long 0x4 20.--22. "FSOS,Receive Frame Sync Output Selection" "0: None RF pin is an input,1: Negative Pulse RF pin is an output,2: Positive Pulse RF pin is an output,3: Driven Low during data transfer RF pin is an..,4: Driven High during data transfer RF pin is an..,5: Toggling at each start of data transfer RF pin..,?,?"
|
|
hexmask.long.byte 0x4 16.--19. 1. "FSLEN,Receive Frame Sync Length"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "DATNB,Data Number per Frame"
|
|
bitfld.long 0x4 7. "MSBF,Most Significant Bit First" "0: The lowest significant bit of the data register..,1: The most significant bit of the data register is.."
|
|
newline
|
|
bitfld.long 0x4 5. "LOOP,Loop Mode" "0: Normal operating mode.,1: RD is driven by TD RF is driven by TF and TK.."
|
|
hexmask.long.byte 0x4 0.--4. 1. "DATLEN,Data Length"
|
|
line.long 0x8 "TCMR,Transmit Clock Mode Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. "PERIOD,Transmit Period Divider Selection"
|
|
hexmask.long.byte 0x8 16.--23. 1. "STTDLY,Transmit Start Delay"
|
|
newline
|
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hexmask.long.byte 0x8 8.--11. 1. "START,Transmit Start Selection"
|
|
bitfld.long 0x8 6.--7. "CKG,Transmit Clock Gating Selection" "0: None,1: Transmit Clock enabled only if TF Low,2: Transmit Clock enabled only if TF High,?"
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|
newline
|
|
bitfld.long 0x8 5. "CKI,Transmit Clock Inversion" "0: The data outputs (Data and Frame Sync signals)..,1: The data outputs (Data and Frame Sync signals).."
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|
bitfld.long 0x8 2.--4. "CKO,Transmit Clock Output Mode Selection" "0: None TK pin is an input,1: Continuous Transmit Clock TK pin is an output,2: Transmit Clock only during data transfers TK pin..,?,?,?,?,?"
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|
newline
|
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bitfld.long 0x8 0.--1. "CKS,Transmit Clock Selection" "0: Divided Clock,1: RK Clock signal,2: TK pin,?"
|
|
line.long 0xC "TFMR,Transmit Frame Mode Register"
|
|
hexmask.long.byte 0xC 28.--31. 1. "FSLEN_EXT,FSLEN Field Extension"
|
|
bitfld.long 0xC 24. "FSEDGE,Frame Sync Edge Detection" "0: Positive Edge Detection,1: Negative Edge Detection"
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|
newline
|
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bitfld.long 0xC 23. "FSDEN,Frame Sync Data Enable" "0: The TD line is driven with the default value..,1: SSC_TSHR value is shifted out during the.."
|
|
bitfld.long 0xC 20.--22. "FSOS,Transmit Frame Sync Output Selection" "0: None TF pin is an input,1: Negative Pulse TF pin is an output,2: Positive Pulse TF pin is an output,3: Driven Low during data transfer,4: Driven High during data transfer,5: Toggling at each start of data transfer,?,?"
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|
newline
|
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hexmask.long.byte 0xC 16.--19. 1. "FSLEN,Transmit Frame Sync Length"
|
|
hexmask.long.byte 0xC 8.--11. 1. "DATNB,Data Number per Frame"
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|
newline
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bitfld.long 0xC 7. "MSBF,Most Significant Bit First" "0: The lowest significant bit of the data register..,1: The most significant bit of the data register is.."
|
|
bitfld.long 0xC 5. "DATDEF,Data Default Value" "0,1"
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|
newline
|
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hexmask.long.byte 0xC 0.--4. 1. "DATLEN,Data Length"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "RHFR,Receive Holding FIFO Register"
|
|
hexmask.long 0x0 0.--31. 1. "RDAT,Receive Data"
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x0 "THFR,Transmit Holding FIFO Register"
|
|
hexmask.long 0x0 0.--31. 1. "TDAT,Transmit Data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "FFMR,FIFO Mode Register"
|
|
bitfld.long 0x0 16. "RXFIFODIS,Receive FIFO Disable" "0: The receive FIFO is enabled.,1: The receive FIFO is disabled. Only a single.."
|
|
hexmask.long.byte 0x0 8.--11. 1. "THRS,Transmit Start Threshold"
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|
newline
|
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bitfld.long 0x0 0. "TXFIFODIS,Transmit FIFO Disable" "0: The transmit FIFO is enabled.,1: The transmit FIFO is disabled. Only a single.."
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "RSHR,Receive Sync. Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RSDAT,Receive Synchronization Data"
|
|
group.long 0x34++0xB
|
|
line.long 0x0 "TSHR,Transmit Sync. Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TSDAT,Transmit Synchronization Data"
|
|
line.long 0x4 "RC0R,Receive Compare 0 Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "CP0,Receive Compare Data 0"
|
|
line.long 0x8 "RC1R,Receive Compare 1 Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "CP1,Receive Compare Data 1"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "RXURWCNT,Receive FIFO Unread Word Count"
|
|
hexmask.long.byte 0x0 24.--27. 1. "TXFRECNT,Transmit FIFO Free Entries Count"
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|
newline
|
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bitfld.long 0x0 17. "RXEN,Receive Enable" "0: Receive is disabled.,1: Receive is enabled."
|
|
bitfld.long 0x0 16. "TXEN,Transmit Enable" "0: Transmit is disabled.,1: Transmit is enabled."
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|
newline
|
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bitfld.long 0x0 11. "RXSYN,Receive Sync" "0: An Rx Sync has not occurred since the last read..,1: An Rx Sync has occurred since the last read of.."
|
|
bitfld.long 0x0 10. "TXSYN,Transmit Sync" "0: A Tx Sync has not occurred since the last read..,1: A Tx Sync has occurred since the last read of.."
|
|
newline
|
|
bitfld.long 0x0 9. "CP1,Compare 1" "0: A compare 1 has not occurred since the last read..,1: A compare 1 has occurred since the last read of.."
|
|
bitfld.long 0x0 8. "CP0,Compare 0" "0: A compare 0 has not occurred since the last read..,1: A compare 0 has occurred since the last read of.."
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|
newline
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|
bitfld.long 0x0 5. "OVRUN,Receive Overrun" "0: No data has been loaded in SSC_RHFR while..,1: Data has been loaded in SSC_RHFR while previous.."
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|
bitfld.long 0x0 4. "RXRDY,Receive Ready" "0: SSC_RHFR is empty.,1: Data has been received and loaded in SSC_RHFR."
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|
newline
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bitfld.long 0x0 1. "TXEMPTY,Transmit Empty" "0: Data remains in SSC_THFR or is currently..,1: Last data written in SSC_THFR has been loaded in.."
|
|
bitfld.long 0x0 0. "TXRDY,Transmit Ready" "0: Data has been loaded in SSC_THFR and is waiting..,1: SSC_THFR is empty."
|
|
wgroup.long 0x44++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 11. "RXSYN,Rx Sync Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 10. "TXSYN,Tx Sync Interrupt Enable" "0,1"
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|
newline
|
|
bitfld.long 0x0 9. "CP1,Compare 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 8. "CP0,Compare 0 Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "OVRUN,Receive Overrun Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "RXRDY,Receive Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXEMPTY,Transmit Empty Interrupt Enable" "0,1"
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|
bitfld.long 0x0 0. "TXRDY,Transmit Ready Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 11. "RXSYN,Rx Sync Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 10. "TXSYN,Tx Sync Interrupt Enable" "0,1"
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|
newline
|
|
bitfld.long 0x4 9. "CP1,Compare 1 Interrupt Disable" "0,1"
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|
bitfld.long 0x4 8. "CP0,Compare 0 Interrupt Disable" "0,1"
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|
newline
|
|
bitfld.long 0x4 5. "OVRUN,Receive Overrun Interrupt Disable" "0,1"
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|
bitfld.long 0x4 4. "RXRDY,Receive Ready Interrupt Disable" "0,1"
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|
newline
|
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bitfld.long 0x4 1. "TXEMPTY,Transmit Empty Interrupt Disable" "0,1"
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|
bitfld.long 0x4 0. "TXRDY,Transmit Ready Interrupt Disable" "0,1"
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|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 11. "RXSYN,Rx Sync Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 10. "TXSYN,Tx Sync Interrupt Mask" "0,1"
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|
newline
|
|
bitfld.long 0x0 9. "CP1,Compare 1 Interrupt Mask" "0,1"
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|
bitfld.long 0x0 8. "CP0,Compare 0 Interrupt Mask" "0,1"
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|
newline
|
|
bitfld.long 0x0 5. "OVRUN,Receive Overrun Interrupt Mask" "0,1"
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|
bitfld.long 0x0 4. "RXRDY,Receive Ready Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 1. "TXEMPTY,Transmit Empty Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "TXRDY,Transmit Ready Interrupt Mask" "0,1"
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|
group.long 0xE4++0x3
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|
line.long 0x0 "WPMR,Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
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rgroup.long 0xE8++0x3
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line.long 0x0 "WPSR,Write Protection Status Register"
|
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hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protect Violation Source"
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|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
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tree.end
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tree.end
|
|
tree "SYSCWP (System Controller Write Protection)"
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base ad:0xE001D0DC
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group.long 0x0++0x3
|
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line.long 0x0 "SYSC_WPMR,Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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bitfld.long 0x0 1. "WPITEN,Write Protection RTC Interrupt Enable" "0: Disables the write protection of the..,1: Enables the write protection of the.."
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|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection of the..,1: Enables the write protection of the.."
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rgroup.long 0x4++0x3
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line.long 0x0 "SYSC_WPSR,Write Protection Status Register"
|
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hexmask.long.byte 0x0 8.--15. 1. "WVSRC,Write Violation Source"
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bitfld.long 0x0 0. "WPVS,Write Protection Register Violation Status" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
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tree.end
|
|
tree "TC (Timer/Counter)"
|
|
base ad:0x0
|
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tree "TC0"
|
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base ad:0xE2814000
|
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repeat 3. (list 0x0 0x1 0x2)(list ad:0xE2814000 ad:0xE2814040 ad:0xE2814080)
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|
tree "TC_CHANNEL[$1]"
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base $2
|
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wgroup.long ($2)++0x3
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line.long 0x0 "CCR,Channel Control Register"
|
|
bitfld.long 0x0 2. "SWTRG,Software Trigger Command" "0: No effect.,1: A software trigger is performed: the counter is.."
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bitfld.long 0x0 1. "CLKDIS,Counter Clock Disable Command" "0: No effect.,1: Disables the clock."
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newline
|
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bitfld.long 0x0 0. "CLKEN,Counter Clock Enable Command" "0: No effect.,1: Enables the clock if CLKDIS is not 1."
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group.long ($2+0x4)++0x3
|
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line.long 0x0 "CMR_CAPTURE_MODE,Channel Mode Register"
|
|
bitfld.long 0x0 20.--22. "SBSMPLR,Loading Edge Subsampling Ratio" "0: Load a Capture register each selected edge,1: Load a Capture register every 2 selected edges,2: Load a Capture register every 4 selected edges,3: Load a Capture register every 8 selected edges,4: Load a Capture register every 16 selected edges,?,?,?"
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bitfld.long 0x0 18.--19. "LDRB,RB Loading Edge Selection" "0: None,1: Rising edge of TIOAx,2: Falling edge of TIOAx,3: Each edge of TIOAx"
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newline
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bitfld.long 0x0 16.--17. "LDRA,RA Loading Edge Selection" "0: None,1: Rising edge of TIOAx,2: Falling edge of TIOAx,3: Each edge of TIOAx"
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bitfld.long 0x0 15. "WAVE,Waveform Mode" "0: Waveform mode is disabled (Capture mode is..,1: Waveform mode is enabled (Capture mode is.."
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newline
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bitfld.long 0x0 14. "CPCTRG,RC Compare Trigger Enable" "0: RC Compare has no effect on the counter and its..,1: RC Compare resets the counter and starts the.."
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bitfld.long 0x0 10. "ABETRG,TIOAx or TIOBx External Trigger Selection" "0: TIOBx is used as an external trigger.,1: TIOAx is used as an external trigger."
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newline
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bitfld.long 0x0 8.--9. "ETRGEDG,External Trigger Edge Selection" "0: The clock is not gated by an external signal.,1: Rising edge,2: Falling edge,3: Each edge"
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bitfld.long 0x0 7. "LDBDIS,Counter Clock Disable with RB Loading" "0: Counter clock is not disabled when RB loading..,1: Counter clock is disabled when RB loading occurs."
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newline
|
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bitfld.long 0x0 6. "LDBSTOP,Counter Clock Stopped with RB Loading" "0: Counter clock is not stopped when RB loading..,1: Counter clock is stopped when RB loading occurs."
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bitfld.long 0x0 4.--5. "BURST,Burst Signal Selection" "0: The clock is not gated by an external signal.,1: XC0 is ANDed with the selected clock.,2: XC1 is ANDed with the selected clock.,3: XC2 is ANDed with the selected clock."
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newline
|
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bitfld.long 0x0 3. "CLKI,Clock Invert" "0: Counter is incremented on rising edge of the..,1: Counter is incremented on falling edge of the.."
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bitfld.long 0x0 0.--2. "TCCLKS,Clock Selection" "0: Clock selected: internal GCLK [TC_ID] clock..,1: Clock selected: internal MCK/8 clock signal..,2: Clock selected: internal MCK/32 clock signal..,3: Clock selected: internal MCK/128 clock signal..,4: Clock selected: internal TD_SLCK clock signal..,5: Clock selected: XC0,6: Clock selected: XC1,7: Clock selected: XC2"
|
|
group.long ($2+0x4)++0x7
|
|
line.long 0x0 "CMR_WAVEFORM_MODE,Channel Mode Register"
|
|
bitfld.long 0x0 30.--31. "BSWTRG,Software Trigger Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 28.--29. "BEEVT,External Event Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "BCPC,RC Compare Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 24.--25. "BCPB,RB Compare Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "ASWTRG,Software Trigger Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 20.--21. "AEEVT,External Event Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
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bitfld.long 0x0 18.--19. "ACPC,RC Compare Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 16.--17. "ACPA,RA Compare Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 15. "WAVE,Waveform Mode" "0: Waveform mode is disabled (Capture mode is..,1: Waveform mode is enabled (Capture mode is.."
|
|
bitfld.long 0x0 13.--14. "WAVSEL,Waveform Selection" "0: UP mode without automatic trigger on RC Compare,1: UPDOWN mode without automatic trigger on RC..,2: UP mode with automatic trigger on RC Compare,3: UPDOWN mode with automatic trigger on RC Compare"
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|
newline
|
|
bitfld.long 0x0 12. "ENETRG,External Event Trigger Enable" "0: The external event has no effect on the counter..,1: The external event resets the counter and starts.."
|
|
bitfld.long 0x0 10.--11. "EEVT,External Event Selection" "0: TIOB,1: XC0,2: XC1,3: XC2"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "EEVTEDG,External Event Edge Selection" "0: None,1: Rising edge,2: Falling edge,3: Each edge"
|
|
bitfld.long 0x0 7. "CPCDIS,Counter Clock Disable with RC Compare" "0: Counter clock is not disabled when counter..,1: Counter clock is disabled when counter reaches RC."
|
|
newline
|
|
bitfld.long 0x0 6. "CPCSTOP,Counter Clock Stopped with RC Compare" "0: Counter clock is not stopped when counter..,1: Counter clock is stopped when counter reaches RC."
|
|
bitfld.long 0x0 4.--5. "BURST,Burst Signal Selection" "0: The clock is not gated by an external signal.,1: XC0 is ANDed with the selected clock.,2: XC1 is ANDed with the selected clock.,3: XC2 is ANDed with the selected clock."
|
|
newline
|
|
bitfld.long 0x0 3. "CLKI,Clock Invert" "0: Counter is incremented on rising edge of the..,1: Counter is incremented on falling edge of the.."
|
|
bitfld.long 0x0 0.--2. "TCCLKS,Clock Selection" "0: Clock selected: internal GCLK [TC_ID] clock..,1: Clock selected: internal MCK/8 clock signal..,2: Clock selected: internal MCK/32 clock signal..,3: Clock selected: internal MCK/128 clock signal..,4: Clock selected: internal TD_SLCK clock signal..,5: Clock selected: XC0,6: Clock selected: XC1,7: Clock selected: XC2"
|
|
line.long 0x4 "SMMR,Stepper Motor Mode Register"
|
|
bitfld.long 0x4 1. "DOWN,Down Count" "0: Up counter.,1: Down counter."
|
|
bitfld.long 0x4 0. "GCEN,Gray Count Enable" "0: TIOAx [x=0..2] and TIOBx [x=0..2] are driven by..,1: TIOAx [x=0..2] and TIOBx [x=0..2] are driven by.."
|
|
rgroup.long ($2+0xC)++0x7
|
|
line.long 0x0 "RAB,Register AB"
|
|
hexmask.long 0x0 0.--31. 1. "RAB,Register A or Register B"
|
|
line.long 0x4 "CV,Counter Value"
|
|
hexmask.long 0x4 0.--31. 1. "CV,Counter Value"
|
|
group.long ($2+0x14)++0xB
|
|
line.long 0x0 "RA,Register A"
|
|
hexmask.long 0x0 0.--31. 1. "RA,Register A"
|
|
line.long 0x4 "RB,Register B"
|
|
hexmask.long 0x4 0.--31. 1. "RB,Register B"
|
|
line.long 0x8 "RC,Register C"
|
|
hexmask.long 0x8 0.--31. 1. "RC,Register C"
|
|
rgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "SR,Interrupt Status Register"
|
|
bitfld.long 0x0 18. "MTIOB,TIOBx Mirror" "0: TIOBx is low. If TC_CMRx.WAVE = 0 TIOBx pin is..,1: TIOBx is high. If TC_CMRx.WAVE = 0 TIOBx pin is.."
|
|
bitfld.long 0x0 17. "MTIOA,TIOAx Mirror" "0: TIOAx is low. If TC_CMRx.WAVE = 0 TIOAx pin is..,1: TIOAx is high. If TC_CMRx.WAVE = 0 TIOAx pin is.."
|
|
newline
|
|
bitfld.long 0x0 16. "CLKSTA,Clock Enabling Status" "0: Clock is disabled.,1: Clock is enabled."
|
|
bitfld.long 0x0 8. "SECE,Security and/or Safety Event (cleared on read)" "0: No security or safety event occurred.,1: One or more safety or security event occurred.."
|
|
newline
|
|
bitfld.long 0x0 7. "ETRGS,External Trigger Status (cleared on read)" "0: External trigger has not occurred since the last..,1: External trigger has occurred since the last.."
|
|
bitfld.long 0x0 6. "LDRBS,RB Loading Status (cleared on read)" "0: RB Load has not occurred since the last read of..,1: RB Load has occurred since the last read of the.."
|
|
newline
|
|
bitfld.long 0x0 5. "LDRAS,RA Loading Status (cleared on read)" "0: RA Load has not occurred since the last read of..,1: RA Load has occurred since the last read of the.."
|
|
bitfld.long 0x0 4. "CPCS,RC Compare Status (cleared on read)" "0: RC Compare has not occurred since the last read..,1: RC Compare has occurred since the last read of.."
|
|
newline
|
|
bitfld.long 0x0 3. "CPBS,RB Compare Status (cleared on read)" "0: RB Compare has not occurred since the last read..,1: RB Compare has occurred since the last read of.."
|
|
bitfld.long 0x0 2. "CPAS,RA Compare Status (cleared on read)" "0: RA Compare has not occurred since the last read..,1: RA Compare has occurred since the last read of.."
|
|
newline
|
|
bitfld.long 0x0 1. "LOVRS,Load Overrun Status (cleared on read)" "0: Load overrun has not occurred since the last..,1: RA or RB have been loaded at least twice without.."
|
|
bitfld.long 0x0 0. "COVFS,Counter Overflow Status (cleared on read)" "0: No counter overflow has occurred since the last..,1: A counter overflow has occurred since the last.."
|
|
wgroup.long ($2+0x24)++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 10. "SECE,Security and/or Safety Event Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 7. "ETRGS,External Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LDRBS,RB Loading" "0,1"
|
|
bitfld.long 0x0 5. "LDRAS,RA Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CPCS,RC Compare" "0,1"
|
|
bitfld.long 0x0 3. "CPBS,RB Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPAS,RA Compare" "0,1"
|
|
bitfld.long 0x0 1. "LOVRS,Load Overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "COVFS,Counter Overflow" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 10. "SECE,Security and/or Safety Event Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 7. "ETRGS,External Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "LDRBS,RB Loading" "0,1"
|
|
bitfld.long 0x4 5. "LDRAS,RA Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CPCS,RC Compare" "0,1"
|
|
bitfld.long 0x4 3. "CPBS,RB Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "CPAS,RA Compare" "0,1"
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bitfld.long 0x4 1. "LOVRS,Load Overrun" "0,1"
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bitfld.long 0x4 0. "COVFS,Counter Overflow" "0,1"
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rgroup.long ($2+0x2C)++0x3
|
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line.long 0x0 "IMR,Interrupt Mask Register"
|
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bitfld.long 0x0 10. "SECE,Security and/or Safety Event Interrupt Mask" "0,1"
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bitfld.long 0x0 7. "ETRGS,External Trigger" "0,1"
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bitfld.long 0x0 6. "LDRBS,RB Loading" "0,1"
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|
bitfld.long 0x0 5. "LDRAS,RA Loading" "0,1"
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|
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bitfld.long 0x0 4. "CPCS,RC Compare" "0,1"
|
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bitfld.long 0x0 3. "CPBS,RB Compare" "0,1"
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|
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bitfld.long 0x0 2. "CPAS,RA Compare" "0,1"
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|
bitfld.long 0x0 1. "LOVRS,Load Overrun" "0,1"
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|
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bitfld.long 0x0 0. "COVFS,Counter Overflow" "0,1"
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|
group.long ($2+0x30)++0x3
|
|
line.long 0x0 "EMR,Extended Mode Register"
|
|
bitfld.long 0x0 8. "NODIVCLK,No Divided Clock" "0: The selected clock is defined by field TCCLKS in..,1: The selected clock is peripheral clock and.."
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|
bitfld.long 0x0 4.--5. "TRIGSRCB,Trigger Source for Input B" "0: The trigger/capture input B is driven by..,1: For TC0 TC1.TIOB0 TC1.TIOB2: The trigger/capture..,?,?"
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bitfld.long 0x0 0.--1. "TRIGSRCA,Trigger Source for Input A" "0: The trigger/capture input A is driven by..,1: The trigger/capture input A is driven internally..,?,?"
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|
rgroup.long ($2+0x34)++0x7
|
|
line.long 0x0 "CSR,Channel Status Register"
|
|
bitfld.long 0x0 18. "MTIOB,TIOBx Mirror" "0: TIOBx is low. If TC_CMRx.WAVE = 0 TIOBx is low.,1: TIOBx is high. If TC_CMRx.WAVE = 0 TIOBx is.."
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bitfld.long 0x0 17. "MTIOA,TIOAx Mirror" "0: TIOAx is low. If TC_CMRx.WAVE = 0 TIOAx is low.,1: TIOAx is high. If TC_CMRx.WAVE = 0 TIOAx is.."
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bitfld.long 0x0 16. "CLKSTA,Clock Enabling Status" "0: Clock is disabled.,1: Clock is enabled."
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line.long 0x4 "SSR,Safety Status Register"
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|
bitfld.long 0x4 31. "ECLASS,Software Error Class" "0: An abnormal access that does not have any impact.,1: An abnormal access that may have an impact."
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hexmask.long.byte 0x4 24.--27. 1. "SWETYP,Software Error Type (cleared on read)"
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newline
|
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hexmask.long.word 0x4 8.--23. 1. "WPVSRC,Write Protection Violation Source (cleared on read)"
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bitfld.long 0x4 3. "SWE,Software Control Error (cleared on read)" "0: No software error has occurred since the last..,1: A software error has occurred since the last.."
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|
newline
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bitfld.long 0x4 2. "SEQE,Internal Sequencer Error (cleared on read)" "0: No internal counter error has occurred since the..,1: An internal counter error has occurred since the.."
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|
bitfld.long 0x4 1. "CGD,Clock Glitch Detected (cleared on read)" "0: The clock monitoring has not been corrupted..,1: The clock monitoring has been corrupted since.."
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newline
|
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bitfld.long 0x4 0. "WPVS,Write Protection Violation Status (cleared on read)" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
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|
tree.end
|
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repeat.end
|
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base ad:0xE2814000
|
|
wgroup.long 0xC0++0x3
|
|
line.long 0x0 "BCR,Block Control Register"
|
|
bitfld.long 0x0 0. "SYNC,Synchro Command" "0: No effect.,1: Asserts the SYNC signal which generates a.."
|
|
group.long 0xC4++0x3
|
|
line.long 0x0 "BMR,Block Mode Register"
|
|
hexmask.long.byte 0x0 26.--29. 1. "MAXCMP,Maximum Consecutive Missing Pulses"
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hexmask.long.byte 0x0 20.--25. 1. "MAXFILT,Maximum Filter"
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bitfld.long 0x0 18. "AUTOC,AutoCorrection of missing pulses" "0: The detection and autocorrection function is..,1: The detection and autocorrection function is.."
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bitfld.long 0x0 17. "IDXPHB,Index Pin is PHB Pin" "0: IDX pin of the rotary sensor must drive TIOA1.,1: IDX pin of the rotary sensor must drive TIOB0."
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newline
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bitfld.long 0x0 16. "SWAP,Swap PHA and PHB" "0: No swap between PHA and PHB.,1: Swap PHA and PHB internally prior to driving the.."
|
|
bitfld.long 0x0 15. "INVIDX,Inverted Index" "0: IDX (TIOA1) is directly driving the QDEC.,1: IDX is inverted before driving the QDEC."
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newline
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bitfld.long 0x0 14. "INVB,Inverted PHB" "0: PHB (TIOB0) is directly driving the QDEC.,1: PHB is inverted before driving the QDEC."
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bitfld.long 0x0 13. "INVA,Inverted PHA" "0: PHA (TIOA0) is directly driving the QDEC.,1: PHA is inverted before driving the QDEC."
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newline
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bitfld.long 0x0 12. "EDGPHA,Edge on PHA Count Mode" "0: Edges are detected on PHA only.,1: Edges are detected on both PHA and PHB."
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|
bitfld.long 0x0 11. "QDTRANS,Quadrature Decoding Transparent" "0: Full quadrature decoding logic is active..,1: Quadrature decoding logic is inactive (direction.."
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newline
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bitfld.long 0x0 10. "SPEEDEN,Speed Enabled" "0: Disabled.,1: Enables the speed measure on channel 0 the time.."
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|
bitfld.long 0x0 9. "POSEN,Position Enabled" "0: Disable position.,1: Enables the position measure on channel 0 and 1."
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|
newline
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bitfld.long 0x0 8. "QDEN,Quadrature Decoder Enabled" "0: Disabled.,1: Enables the QDEC (filter edge detection and.."
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|
bitfld.long 0x0 4.--5. "TC2XC2S,External Clock Signal 2 Selection" "0: Signal connected to XC2: TCLK2,?,2: Signal connected to XC2: TIOA0,3: Signal connected to XC2: TIOA1"
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|
newline
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bitfld.long 0x0 2.--3. "TC1XC1S,External Clock Signal 1 Selection" "0: Signal connected to XC1: TCLK1,?,2: Signal connected to XC1: TIOA0,3: Signal connected to XC1: TIOA2"
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|
bitfld.long 0x0 0.--1. "TC0XC0S,External Clock Signal 0 Selection" "0: Signal connected to XC0: TCLK0,?,2: Signal connected to XC0: TIOA1,3: Signal connected to XC0: TIOA2"
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|
wgroup.long 0xC8++0x7
|
|
line.long 0x0 "QIER,QDEC Interrupt Enable Register"
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|
bitfld.long 0x0 7. "FMP,Filtered Missing Pulse" "0: No effect.,1: Enables the interrupt when phase A or phase B.."
|
|
bitfld.long 0x0 6. "FIDX,Filtered Index Line" "0: No effect.,1: Enables the interrupt when index line has a.."
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|
newline
|
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bitfld.long 0x0 5. "FPHB,Filtered Phase B Line" "0: No effect.,1: Enables the interrupt when phase B line has a.."
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|
bitfld.long 0x0 4. "FPHA,Filtered Phase A Line" "0: No effect.,1: Enables the interrupt when phase A line has a.."
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|
newline
|
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bitfld.long 0x0 3. "MPE,Consecutive Missing Pulse Error" "0: No effect.,1: Enables the interrupt when an occurrence of.."
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|
bitfld.long 0x0 2. "QERR,Quadrature Error" "0: No effect.,1: Enables the interrupt when a quadrature error.."
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newline
|
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bitfld.long 0x0 1. "DIRCHG,Direction Change" "0: No effect.,1: Enables the interrupt when a change on rotation.."
|
|
bitfld.long 0x0 0. "IDX,Index" "0: No effect.,1: Enables the interrupt when a rising edge occurs.."
|
|
line.long 0x4 "QIDR,QDEC Interrupt Disable Register"
|
|
bitfld.long 0x4 7. "FMP,Filtered Missing Pulse" "0: No effect.,1: Disables the interrupt when phase A or phase B.."
|
|
bitfld.long 0x4 6. "FIDX,Filtered Index Line" "0: No effect.,1: Disables the interrupt when index line has a.."
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|
newline
|
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bitfld.long 0x4 5. "FPHB,Filtered Phase B Line" "0: No effect.,1: Disables the interrupt when phase B line has a.."
|
|
bitfld.long 0x4 4. "FPHA,Filtered Phase A Line" "0: No effect.,1: Disables the interrupt when phase A line has a.."
|
|
newline
|
|
bitfld.long 0x4 3. "MPE,Consecutive Missing Pulse Error" "0: No effect.,1: Disables the interrupt when an occurrence of.."
|
|
bitfld.long 0x4 2. "QERR,Quadrature Error" "0: No effect.,1: Disables the interrupt when a quadrature error.."
|
|
newline
|
|
bitfld.long 0x4 1. "DIRCHG,Direction Change" "0: No effect.,1: Disables the interrupt when a change on rotation.."
|
|
bitfld.long 0x4 0. "IDX,Index" "0: No effect.,1: Disables the interrupt when a rising edge occurs.."
|
|
rgroup.long 0xD0++0x7
|
|
line.long 0x0 "QIMR,QDEC Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "FMP,Filtered Missing Pulse" "0: The interrupt on auto-corrected missing pulse is..,1: The interrupt on auto-corrected missing pulse is.."
|
|
bitfld.long 0x0 6. "FIDX,Filtered Index Line" "0: The interrupt on index line filtered..,1: The interrupt on index line filtered.."
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|
newline
|
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bitfld.long 0x0 5. "FPHB,Filtered Phase B Line" "0: The interrupt on phase B line filtered..,1: The interrupt on phase B line filtered.."
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|
bitfld.long 0x0 4. "FPHA,Filtered Phase A Line" "0: The interrupt on phase A line filtered..,1: The interrupt on phase A line filtered.."
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|
newline
|
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bitfld.long 0x0 3. "MPE,Consecutive Missing Pulse Error" "0: The interrupt on the maximum number of..,1: The interrupt on the maximum number of.."
|
|
bitfld.long 0x0 2. "QERR,Quadrature Error" "0: The interrupt on quadrature error is disabled.,1: The interrupt on quadrature error is enabled."
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|
newline
|
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bitfld.long 0x0 1. "DIRCHG,Direction Change" "0: The interrupt on rotation direction change is..,1: The interrupt on rotation direction change is.."
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|
bitfld.long 0x0 0. "IDX,Index" "0: The interrupt on IDX input is disabled.,1: The interrupt on IDX input is enabled."
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|
line.long 0x4 "QISR,QDEC Interrupt Status Register"
|
|
bitfld.long 0x4 8. "DIR,Direction" "0,1"
|
|
bitfld.long 0x4 7. "FMP,Filtered Missing Pulse" "0: No correction of missing pulse on phase A or B..,1: A correction of missing pulse on phase A or B.."
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|
newline
|
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bitfld.long 0x4 6. "FIDX,Filtered Index Line" "0: No filtered contamination on index line since..,1: A contamination has been successfully on index.."
|
|
bitfld.long 0x4 5. "FPHB,Filtered Phase B Line" "0: No filtered contamination on phase B line since..,1: A contamination has been successfully on phase B.."
|
|
newline
|
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bitfld.long 0x4 4. "FPHA,Filtered Phase A Line" "0: No filtered contamination on phase A line since..,1: A contamination has been successfully on phase A.."
|
|
bitfld.long 0x4 3. "MPE,Consecutive Missing Pulse Error" "0: The number of consecutive missing pulses has not..,1: An occurrence of MAXCMP consecutive missing.."
|
|
newline
|
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bitfld.long 0x4 2. "QERR,Quadrature Error" "0: No quadrature error since the last read of..,1: A quadrature error occurred since the last read.."
|
|
bitfld.long 0x4 1. "DIRCHG,Direction Change" "0: No change on rotation direction since the last..,1: The rotation direction changed since the last.."
|
|
newline
|
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bitfld.long 0x4 0. "IDX,Index" "0: No Index input change since the last read of..,1: The IDX input has changed since the last read of.."
|
|
group.long 0xD8++0x3
|
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line.long 0x0 "FMR,Fault Mode Register"
|
|
bitfld.long 0x0 1. "ENCF1,Enable Compare Fault Channel 1" "0: Disables the FAULT output source (CPCS flag)..,1: Enables the FAULT output source (CPCS flag) from.."
|
|
bitfld.long 0x0 0. "ENCF0,Enable Compare Fault Channel 0" "0: Disables the FAULT output source (CPCS flag)..,1: Enables the FAULT output source (CPCS flag) from.."
|
|
rgroup.long 0xDC++0x3
|
|
line.long 0x0 "QSR,QDEC Status Register"
|
|
bitfld.long 0x0 8. "DIR,Direction" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 4. "FIRSTE,First Error Report Enable" "0: The last write protection violation source is..,1: Only the first write protection violation source.."
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|
newline
|
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
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|
newline
|
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
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tree.end
|
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tree "TC1"
|
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base ad:0xE0800000
|
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repeat 3. (list 0x0 0x1 0x2)(list ad:0xE0800000 ad:0xE0800040 ad:0xE0800080)
|
|
tree "TC_CHANNEL[$1]"
|
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base $2
|
|
wgroup.long ($2)++0x3
|
|
line.long 0x0 "CCR,Channel Control Register"
|
|
bitfld.long 0x0 2. "SWTRG,Software Trigger Command" "0: No effect.,1: A software trigger is performed: the counter is.."
|
|
bitfld.long 0x0 1. "CLKDIS,Counter Clock Disable Command" "0: No effect.,1: Disables the clock."
|
|
newline
|
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bitfld.long 0x0 0. "CLKEN,Counter Clock Enable Command" "0: No effect.,1: Enables the clock if CLKDIS is not 1."
|
|
group.long ($2+0x4)++0x3
|
|
line.long 0x0 "CMR_CAPTURE_MODE,Channel Mode Register"
|
|
bitfld.long 0x0 20.--22. "SBSMPLR,Loading Edge Subsampling Ratio" "0: Load a Capture register each selected edge,1: Load a Capture register every 2 selected edges,2: Load a Capture register every 4 selected edges,3: Load a Capture register every 8 selected edges,4: Load a Capture register every 16 selected edges,?,?,?"
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|
bitfld.long 0x0 18.--19. "LDRB,RB Loading Edge Selection" "0: None,1: Rising edge of TIOAx,2: Falling edge of TIOAx,3: Each edge of TIOAx"
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newline
|
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bitfld.long 0x0 16.--17. "LDRA,RA Loading Edge Selection" "0: None,1: Rising edge of TIOAx,2: Falling edge of TIOAx,3: Each edge of TIOAx"
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bitfld.long 0x0 15. "WAVE,Waveform Mode" "0: Waveform mode is disabled (Capture mode is..,1: Waveform mode is enabled (Capture mode is.."
|
|
newline
|
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bitfld.long 0x0 14. "CPCTRG,RC Compare Trigger Enable" "0: RC Compare has no effect on the counter and its..,1: RC Compare resets the counter and starts the.."
|
|
bitfld.long 0x0 10. "ABETRG,TIOAx or TIOBx External Trigger Selection" "0: TIOBx is used as an external trigger.,1: TIOAx is used as an external trigger."
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newline
|
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bitfld.long 0x0 8.--9. "ETRGEDG,External Trigger Edge Selection" "0: The clock is not gated by an external signal.,1: Rising edge,2: Falling edge,3: Each edge"
|
|
bitfld.long 0x0 7. "LDBDIS,Counter Clock Disable with RB Loading" "0: Counter clock is not disabled when RB loading..,1: Counter clock is disabled when RB loading occurs."
|
|
newline
|
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bitfld.long 0x0 6. "LDBSTOP,Counter Clock Stopped with RB Loading" "0: Counter clock is not stopped when RB loading..,1: Counter clock is stopped when RB loading occurs."
|
|
bitfld.long 0x0 4.--5. "BURST,Burst Signal Selection" "0: The clock is not gated by an external signal.,1: XC0 is ANDed with the selected clock.,2: XC1 is ANDed with the selected clock.,3: XC2 is ANDed with the selected clock."
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newline
|
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bitfld.long 0x0 3. "CLKI,Clock Invert" "0: Counter is incremented on rising edge of the..,1: Counter is incremented on falling edge of the.."
|
|
bitfld.long 0x0 0.--2. "TCCLKS,Clock Selection" "0: Clock selected: internal GCLK [TC_ID] clock..,1: Clock selected: internal MCK/8 clock signal..,2: Clock selected: internal MCK/32 clock signal..,3: Clock selected: internal MCK/128 clock signal..,4: Clock selected: internal TD_SLCK clock signal..,5: Clock selected: XC0,6: Clock selected: XC1,7: Clock selected: XC2"
|
|
group.long ($2+0x4)++0x7
|
|
line.long 0x0 "CMR_WAVEFORM_MODE,Channel Mode Register"
|
|
bitfld.long 0x0 30.--31. "BSWTRG,Software Trigger Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 28.--29. "BEEVT,External Event Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
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bitfld.long 0x0 26.--27. "BCPC,RC Compare Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 24.--25. "BCPB,RB Compare Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
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|
newline
|
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bitfld.long 0x0 22.--23. "ASWTRG,Software Trigger Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 20.--21. "AEEVT,External Event Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "ACPC,RC Compare Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 16.--17. "ACPA,RA Compare Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
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bitfld.long 0x0 15. "WAVE,Waveform Mode" "0: Waveform mode is disabled (Capture mode is..,1: Waveform mode is enabled (Capture mode is.."
|
|
bitfld.long 0x0 13.--14. "WAVSEL,Waveform Selection" "0: UP mode without automatic trigger on RC Compare,1: UPDOWN mode without automatic trigger on RC..,2: UP mode with automatic trigger on RC Compare,3: UPDOWN mode with automatic trigger on RC Compare"
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|
newline
|
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bitfld.long 0x0 12. "ENETRG,External Event Trigger Enable" "0: The external event has no effect on the counter..,1: The external event resets the counter and starts.."
|
|
bitfld.long 0x0 10.--11. "EEVT,External Event Selection" "0: TIOB,1: XC0,2: XC1,3: XC2"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "EEVTEDG,External Event Edge Selection" "0: None,1: Rising edge,2: Falling edge,3: Each edge"
|
|
bitfld.long 0x0 7. "CPCDIS,Counter Clock Disable with RC Compare" "0: Counter clock is not disabled when counter..,1: Counter clock is disabled when counter reaches RC."
|
|
newline
|
|
bitfld.long 0x0 6. "CPCSTOP,Counter Clock Stopped with RC Compare" "0: Counter clock is not stopped when counter..,1: Counter clock is stopped when counter reaches RC."
|
|
bitfld.long 0x0 4.--5. "BURST,Burst Signal Selection" "0: The clock is not gated by an external signal.,1: XC0 is ANDed with the selected clock.,2: XC1 is ANDed with the selected clock.,3: XC2 is ANDed with the selected clock."
|
|
newline
|
|
bitfld.long 0x0 3. "CLKI,Clock Invert" "0: Counter is incremented on rising edge of the..,1: Counter is incremented on falling edge of the.."
|
|
bitfld.long 0x0 0.--2. "TCCLKS,Clock Selection" "0: Clock selected: internal GCLK [TC_ID] clock..,1: Clock selected: internal MCK/8 clock signal..,2: Clock selected: internal MCK/32 clock signal..,3: Clock selected: internal MCK/128 clock signal..,4: Clock selected: internal TD_SLCK clock signal..,5: Clock selected: XC0,6: Clock selected: XC1,7: Clock selected: XC2"
|
|
line.long 0x4 "SMMR,Stepper Motor Mode Register"
|
|
bitfld.long 0x4 1. "DOWN,Down Count" "0: Up counter.,1: Down counter."
|
|
bitfld.long 0x4 0. "GCEN,Gray Count Enable" "0: TIOAx [x=0..2] and TIOBx [x=0..2] are driven by..,1: TIOAx [x=0..2] and TIOBx [x=0..2] are driven by.."
|
|
rgroup.long ($2+0xC)++0x7
|
|
line.long 0x0 "RAB,Register AB"
|
|
hexmask.long 0x0 0.--31. 1. "RAB,Register A or Register B"
|
|
line.long 0x4 "CV,Counter Value"
|
|
hexmask.long 0x4 0.--31. 1. "CV,Counter Value"
|
|
group.long ($2+0x14)++0xB
|
|
line.long 0x0 "RA,Register A"
|
|
hexmask.long 0x0 0.--31. 1. "RA,Register A"
|
|
line.long 0x4 "RB,Register B"
|
|
hexmask.long 0x4 0.--31. 1. "RB,Register B"
|
|
line.long 0x8 "RC,Register C"
|
|
hexmask.long 0x8 0.--31. 1. "RC,Register C"
|
|
rgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "SR,Interrupt Status Register"
|
|
bitfld.long 0x0 18. "MTIOB,TIOBx Mirror" "0: TIOBx is low. If TC_CMRx.WAVE = 0 TIOBx pin is..,1: TIOBx is high. If TC_CMRx.WAVE = 0 TIOBx pin is.."
|
|
bitfld.long 0x0 17. "MTIOA,TIOAx Mirror" "0: TIOAx is low. If TC_CMRx.WAVE = 0 TIOAx pin is..,1: TIOAx is high. If TC_CMRx.WAVE = 0 TIOAx pin is.."
|
|
newline
|
|
bitfld.long 0x0 16. "CLKSTA,Clock Enabling Status" "0: Clock is disabled.,1: Clock is enabled."
|
|
bitfld.long 0x0 8. "SECE,Security and/or Safety Event (cleared on read)" "0: No security or safety event occurred.,1: One or more safety or security event occurred.."
|
|
newline
|
|
bitfld.long 0x0 7. "ETRGS,External Trigger Status (cleared on read)" "0: External trigger has not occurred since the last..,1: External trigger has occurred since the last.."
|
|
bitfld.long 0x0 6. "LDRBS,RB Loading Status (cleared on read)" "0: RB Load has not occurred since the last read of..,1: RB Load has occurred since the last read of the.."
|
|
newline
|
|
bitfld.long 0x0 5. "LDRAS,RA Loading Status (cleared on read)" "0: RA Load has not occurred since the last read of..,1: RA Load has occurred since the last read of the.."
|
|
bitfld.long 0x0 4. "CPCS,RC Compare Status (cleared on read)" "0: RC Compare has not occurred since the last read..,1: RC Compare has occurred since the last read of.."
|
|
newline
|
|
bitfld.long 0x0 3. "CPBS,RB Compare Status (cleared on read)" "0: RB Compare has not occurred since the last read..,1: RB Compare has occurred since the last read of.."
|
|
bitfld.long 0x0 2. "CPAS,RA Compare Status (cleared on read)" "0: RA Compare has not occurred since the last read..,1: RA Compare has occurred since the last read of.."
|
|
newline
|
|
bitfld.long 0x0 1. "LOVRS,Load Overrun Status (cleared on read)" "0: Load overrun has not occurred since the last..,1: RA or RB have been loaded at least twice without.."
|
|
bitfld.long 0x0 0. "COVFS,Counter Overflow Status (cleared on read)" "0: No counter overflow has occurred since the last..,1: A counter overflow has occurred since the last.."
|
|
wgroup.long ($2+0x24)++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 10. "SECE,Security and/or Safety Event Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 7. "ETRGS,External Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LDRBS,RB Loading" "0,1"
|
|
bitfld.long 0x0 5. "LDRAS,RA Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CPCS,RC Compare" "0,1"
|
|
bitfld.long 0x0 3. "CPBS,RB Compare" "0,1"
|
|
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|
|
bitfld.long 0x0 2. "CPAS,RA Compare" "0,1"
|
|
bitfld.long 0x0 1. "LOVRS,Load Overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "COVFS,Counter Overflow" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 10. "SECE,Security and/or Safety Event Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 7. "ETRGS,External Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "LDRBS,RB Loading" "0,1"
|
|
bitfld.long 0x4 5. "LDRAS,RA Loading" "0,1"
|
|
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|
|
bitfld.long 0x4 4. "CPCS,RC Compare" "0,1"
|
|
bitfld.long 0x4 3. "CPBS,RB Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "CPAS,RA Compare" "0,1"
|
|
bitfld.long 0x4 1. "LOVRS,Load Overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "COVFS,Counter Overflow" "0,1"
|
|
rgroup.long ($2+0x2C)++0x3
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 10. "SECE,Security and/or Safety Event Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 7. "ETRGS,External Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LDRBS,RB Loading" "0,1"
|
|
bitfld.long 0x0 5. "LDRAS,RA Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CPCS,RC Compare" "0,1"
|
|
bitfld.long 0x0 3. "CPBS,RB Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPAS,RA Compare" "0,1"
|
|
bitfld.long 0x0 1. "LOVRS,Load Overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "COVFS,Counter Overflow" "0,1"
|
|
group.long ($2+0x30)++0x3
|
|
line.long 0x0 "EMR,Extended Mode Register"
|
|
bitfld.long 0x0 8. "NODIVCLK,No Divided Clock" "0: The selected clock is defined by field TCCLKS in..,1: The selected clock is peripheral clock and.."
|
|
bitfld.long 0x0 4.--5. "TRIGSRCB,Trigger Source for Input B" "0: The trigger/capture input B is driven by..,1: For TC0 TC1.TIOB0 TC1.TIOB2: The trigger/capture..,?,?"
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|
newline
|
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bitfld.long 0x0 0.--1. "TRIGSRCA,Trigger Source for Input A" "0: The trigger/capture input A is driven by..,1: The trigger/capture input A is driven internally..,?,?"
|
|
rgroup.long ($2+0x34)++0x7
|
|
line.long 0x0 "CSR,Channel Status Register"
|
|
bitfld.long 0x0 18. "MTIOB,TIOBx Mirror" "0: TIOBx is low. If TC_CMRx.WAVE = 0 TIOBx is low.,1: TIOBx is high. If TC_CMRx.WAVE = 0 TIOBx is.."
|
|
bitfld.long 0x0 17. "MTIOA,TIOAx Mirror" "0: TIOAx is low. If TC_CMRx.WAVE = 0 TIOAx is low.,1: TIOAx is high. If TC_CMRx.WAVE = 0 TIOAx is.."
|
|
newline
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bitfld.long 0x0 16. "CLKSTA,Clock Enabling Status" "0: Clock is disabled.,1: Clock is enabled."
|
|
line.long 0x4 "SSR,Safety Status Register"
|
|
bitfld.long 0x4 31. "ECLASS,Software Error Class" "0: An abnormal access that does not have any impact.,1: An abnormal access that may have an impact."
|
|
hexmask.long.byte 0x4 24.--27. 1. "SWETYP,Software Error Type (cleared on read)"
|
|
newline
|
|
hexmask.long.word 0x4 8.--23. 1. "WPVSRC,Write Protection Violation Source (cleared on read)"
|
|
bitfld.long 0x4 3. "SWE,Software Control Error (cleared on read)" "0: No software error has occurred since the last..,1: A software error has occurred since the last.."
|
|
newline
|
|
bitfld.long 0x4 2. "SEQE,Internal Sequencer Error (cleared on read)" "0: No internal counter error has occurred since the..,1: An internal counter error has occurred since the.."
|
|
bitfld.long 0x4 1. "CGD,Clock Glitch Detected (cleared on read)" "0: The clock monitoring has not been corrupted..,1: The clock monitoring has been corrupted since.."
|
|
newline
|
|
bitfld.long 0x4 0. "WPVS,Write Protection Violation Status (cleared on read)" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
|
|
tree.end
|
|
repeat.end
|
|
base ad:0xE0800000
|
|
wgroup.long 0xC0++0x3
|
|
line.long 0x0 "BCR,Block Control Register"
|
|
bitfld.long 0x0 0. "SYNC,Synchro Command" "0: No effect.,1: Asserts the SYNC signal which generates a.."
|
|
group.long 0xC4++0x3
|
|
line.long 0x0 "BMR,Block Mode Register"
|
|
hexmask.long.byte 0x0 26.--29. 1. "MAXCMP,Maximum Consecutive Missing Pulses"
|
|
hexmask.long.byte 0x0 20.--25. 1. "MAXFILT,Maximum Filter"
|
|
newline
|
|
bitfld.long 0x0 18. "AUTOC,AutoCorrection of missing pulses" "0: The detection and autocorrection function is..,1: The detection and autocorrection function is.."
|
|
bitfld.long 0x0 17. "IDXPHB,Index Pin is PHB Pin" "0: IDX pin of the rotary sensor must drive TIOA1.,1: IDX pin of the rotary sensor must drive TIOB0."
|
|
newline
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bitfld.long 0x0 16. "SWAP,Swap PHA and PHB" "0: No swap between PHA and PHB.,1: Swap PHA and PHB internally prior to driving the.."
|
|
bitfld.long 0x0 15. "INVIDX,Inverted Index" "0: IDX (TIOA1) is directly driving the QDEC.,1: IDX is inverted before driving the QDEC."
|
|
newline
|
|
bitfld.long 0x0 14. "INVB,Inverted PHB" "0: PHB (TIOB0) is directly driving the QDEC.,1: PHB is inverted before driving the QDEC."
|
|
bitfld.long 0x0 13. "INVA,Inverted PHA" "0: PHA (TIOA0) is directly driving the QDEC.,1: PHA is inverted before driving the QDEC."
|
|
newline
|
|
bitfld.long 0x0 12. "EDGPHA,Edge on PHA Count Mode" "0: Edges are detected on PHA only.,1: Edges are detected on both PHA and PHB."
|
|
bitfld.long 0x0 11. "QDTRANS,Quadrature Decoding Transparent" "0: Full quadrature decoding logic is active..,1: Quadrature decoding logic is inactive (direction.."
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|
newline
|
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bitfld.long 0x0 10. "SPEEDEN,Speed Enabled" "0: Disabled.,1: Enables the speed measure on channel 0 the time.."
|
|
bitfld.long 0x0 9. "POSEN,Position Enabled" "0: Disable position.,1: Enables the position measure on channel 0 and 1."
|
|
newline
|
|
bitfld.long 0x0 8. "QDEN,Quadrature Decoder Enabled" "0: Disabled.,1: Enables the QDEC (filter edge detection and.."
|
|
bitfld.long 0x0 4.--5. "TC2XC2S,External Clock Signal 2 Selection" "0: Signal connected to XC2: TCLK2,?,2: Signal connected to XC2: TIOA0,3: Signal connected to XC2: TIOA1"
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|
newline
|
|
bitfld.long 0x0 2.--3. "TC1XC1S,External Clock Signal 1 Selection" "0: Signal connected to XC1: TCLK1,?,2: Signal connected to XC1: TIOA0,3: Signal connected to XC1: TIOA2"
|
|
bitfld.long 0x0 0.--1. "TC0XC0S,External Clock Signal 0 Selection" "0: Signal connected to XC0: TCLK0,?,2: Signal connected to XC0: TIOA1,3: Signal connected to XC0: TIOA2"
|
|
wgroup.long 0xC8++0x7
|
|
line.long 0x0 "QIER,QDEC Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "FMP,Filtered Missing Pulse" "0: No effect.,1: Enables the interrupt when phase A or phase B.."
|
|
bitfld.long 0x0 6. "FIDX,Filtered Index Line" "0: No effect.,1: Enables the interrupt when index line has a.."
|
|
newline
|
|
bitfld.long 0x0 5. "FPHB,Filtered Phase B Line" "0: No effect.,1: Enables the interrupt when phase B line has a.."
|
|
bitfld.long 0x0 4. "FPHA,Filtered Phase A Line" "0: No effect.,1: Enables the interrupt when phase A line has a.."
|
|
newline
|
|
bitfld.long 0x0 3. "MPE,Consecutive Missing Pulse Error" "0: No effect.,1: Enables the interrupt when an occurrence of.."
|
|
bitfld.long 0x0 2. "QERR,Quadrature Error" "0: No effect.,1: Enables the interrupt when a quadrature error.."
|
|
newline
|
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bitfld.long 0x0 1. "DIRCHG,Direction Change" "0: No effect.,1: Enables the interrupt when a change on rotation.."
|
|
bitfld.long 0x0 0. "IDX,Index" "0: No effect.,1: Enables the interrupt when a rising edge occurs.."
|
|
line.long 0x4 "QIDR,QDEC Interrupt Disable Register"
|
|
bitfld.long 0x4 7. "FMP,Filtered Missing Pulse" "0: No effect.,1: Disables the interrupt when phase A or phase B.."
|
|
bitfld.long 0x4 6. "FIDX,Filtered Index Line" "0: No effect.,1: Disables the interrupt when index line has a.."
|
|
newline
|
|
bitfld.long 0x4 5. "FPHB,Filtered Phase B Line" "0: No effect.,1: Disables the interrupt when phase B line has a.."
|
|
bitfld.long 0x4 4. "FPHA,Filtered Phase A Line" "0: No effect.,1: Disables the interrupt when phase A line has a.."
|
|
newline
|
|
bitfld.long 0x4 3. "MPE,Consecutive Missing Pulse Error" "0: No effect.,1: Disables the interrupt when an occurrence of.."
|
|
bitfld.long 0x4 2. "QERR,Quadrature Error" "0: No effect.,1: Disables the interrupt when a quadrature error.."
|
|
newline
|
|
bitfld.long 0x4 1. "DIRCHG,Direction Change" "0: No effect.,1: Disables the interrupt when a change on rotation.."
|
|
bitfld.long 0x4 0. "IDX,Index" "0: No effect.,1: Disables the interrupt when a rising edge occurs.."
|
|
rgroup.long 0xD0++0x7
|
|
line.long 0x0 "QIMR,QDEC Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "FMP,Filtered Missing Pulse" "0: The interrupt on auto-corrected missing pulse is..,1: The interrupt on auto-corrected missing pulse is.."
|
|
bitfld.long 0x0 6. "FIDX,Filtered Index Line" "0: The interrupt on index line filtered..,1: The interrupt on index line filtered.."
|
|
newline
|
|
bitfld.long 0x0 5. "FPHB,Filtered Phase B Line" "0: The interrupt on phase B line filtered..,1: The interrupt on phase B line filtered.."
|
|
bitfld.long 0x0 4. "FPHA,Filtered Phase A Line" "0: The interrupt on phase A line filtered..,1: The interrupt on phase A line filtered.."
|
|
newline
|
|
bitfld.long 0x0 3. "MPE,Consecutive Missing Pulse Error" "0: The interrupt on the maximum number of..,1: The interrupt on the maximum number of.."
|
|
bitfld.long 0x0 2. "QERR,Quadrature Error" "0: The interrupt on quadrature error is disabled.,1: The interrupt on quadrature error is enabled."
|
|
newline
|
|
bitfld.long 0x0 1. "DIRCHG,Direction Change" "0: The interrupt on rotation direction change is..,1: The interrupt on rotation direction change is.."
|
|
bitfld.long 0x0 0. "IDX,Index" "0: The interrupt on IDX input is disabled.,1: The interrupt on IDX input is enabled."
|
|
line.long 0x4 "QISR,QDEC Interrupt Status Register"
|
|
bitfld.long 0x4 8. "DIR,Direction" "0,1"
|
|
bitfld.long 0x4 7. "FMP,Filtered Missing Pulse" "0: No correction of missing pulse on phase A or B..,1: A correction of missing pulse on phase A or B.."
|
|
newline
|
|
bitfld.long 0x4 6. "FIDX,Filtered Index Line" "0: No filtered contamination on index line since..,1: A contamination has been successfully on index.."
|
|
bitfld.long 0x4 5. "FPHB,Filtered Phase B Line" "0: No filtered contamination on phase B line since..,1: A contamination has been successfully on phase B.."
|
|
newline
|
|
bitfld.long 0x4 4. "FPHA,Filtered Phase A Line" "0: No filtered contamination on phase A line since..,1: A contamination has been successfully on phase A.."
|
|
bitfld.long 0x4 3. "MPE,Consecutive Missing Pulse Error" "0: The number of consecutive missing pulses has not..,1: An occurrence of MAXCMP consecutive missing.."
|
|
newline
|
|
bitfld.long 0x4 2. "QERR,Quadrature Error" "0: No quadrature error since the last read of..,1: A quadrature error occurred since the last read.."
|
|
bitfld.long 0x4 1. "DIRCHG,Direction Change" "0: No change on rotation direction since the last..,1: The rotation direction changed since the last.."
|
|
newline
|
|
bitfld.long 0x4 0. "IDX,Index" "0: No Index input change since the last read of..,1: The IDX input has changed since the last read of.."
|
|
group.long 0xD8++0x3
|
|
line.long 0x0 "FMR,Fault Mode Register"
|
|
bitfld.long 0x0 1. "ENCF1,Enable Compare Fault Channel 1" "0: Disables the FAULT output source (CPCS flag)..,1: Enables the FAULT output source (CPCS flag) from.."
|
|
bitfld.long 0x0 0. "ENCF0,Enable Compare Fault Channel 0" "0: Disables the FAULT output source (CPCS flag)..,1: Enables the FAULT output source (CPCS flag) from.."
|
|
rgroup.long 0xDC++0x3
|
|
line.long 0x0 "QSR,QDEC Status Register"
|
|
bitfld.long 0x0 8. "DIR,Direction" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 4. "FIRSTE,First Error Report Enable" "0: The last write protection violation source is..,1: Only the first write protection violation source.."
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
|
|
tree.end
|
|
tree.end
|
|
tree "TCPC (USB Type-C Port Controller)"
|
|
base ad:0x0
|
|
tree "TCPCA"
|
|
base ad:0xE0840000
|
|
rgroup.word 0x0++0xB
|
|
line.word 0x0 "VID,Vendor ID Register"
|
|
hexmask.word 0x0 0.--15. 1. "VID,Vendor ID"
|
|
line.word 0x2 "PID,Product ID Register"
|
|
hexmask.word 0x2 0.--15. 1. "PID,Product ID"
|
|
line.word 0x4 "DID,Device ID Register"
|
|
hexmask.word 0x4 0.--15. 1. "DID,Device ID"
|
|
line.word 0x6 "UTCR,USB Type-C Rev Register"
|
|
hexmask.word 0x6 0.--15. 1. "UTCR,USB Type-C Revision"
|
|
line.word 0x8 "UPDR,USB PD Rev Ver Register"
|
|
hexmask.word 0x8 0.--15. 1. "UPDR,USB-PD Specification Revision and Version"
|
|
line.word 0xA "PDIR,PD Interface Rev Register"
|
|
hexmask.word 0xA 0.--15. 1. "PDIR,USB-Port Controller Interface Specification Revision"
|
|
group.word 0x10++0x3
|
|
line.word 0x0 "AL,Alert Register"
|
|
bitfld.word 0x0 15. "VDA,Vendor Defined Alert" "0: No vendor defined alert has been detected.,1: A vendor defined alert has been detected."
|
|
bitfld.word 0x0 11. "VBUSSNKDS,VBUS Sink Disconnect Detected" "0: No VBUS sink disconnect threshold crossing has..,1: A VBUS sink disconnect threshold crossing has.."
|
|
newline
|
|
bitfld.word 0x0 9. "FLT,Fault" "0: No fault has occurred.,1: A fault has occurred. Read TCPC_FS."
|
|
bitfld.word 0x0 8. "VBUSLO,VBUS Voltage Alarm Low" "0: A low-voltage alarm has not occurred.,1: A low-voltage alarm has occurred."
|
|
newline
|
|
bitfld.word 0x0 7. "VBUSHI,VBUS Voltage Alarm High" "0: A high-voltage alarm has not occurred.,1: A high-voltage alarm has occurred."
|
|
bitfld.word 0x0 1. "PWRS,Power Status" "0: Power status not changed.,1: Power status changed."
|
|
newline
|
|
bitfld.word 0x0 0. "CCS,CC Status" "0: CC status not changed.,1: CC status changed."
|
|
line.word 0x2 "ALM,Alert Mask Register"
|
|
bitfld.word 0x2 15. "VDA,Vendor Defined Alert Interrupt Mask" "0,1"
|
|
bitfld.word 0x2 11. "VBUSSNKDS,VBUS Sink Disconnect Detected Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.word 0x2 9. "FLT,Fault Interrupt Mask" "0,1"
|
|
bitfld.word 0x2 8. "VBUSLO,VBUS Voltage Alarm Low Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.word 0x2 7. "VBUSHI,VBUS Voltage Alarm High Interrupt Mask" "0,1"
|
|
bitfld.word 0x2 1. "PWRS,Power Status Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.word 0x2 0. "CCS,CC Status Interrupt Mask" "0,1"
|
|
group.byte 0x14++0x1
|
|
line.byte 0x0 "PSM,Power Status Mask Register"
|
|
bitfld.byte 0x0 6. "INIT,TCPC Initialization Interrupt Mask" "0,1"
|
|
bitfld.byte 0x0 4. "SRCVBUS,Sourcing VBUS Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "VBUSDETE,VBUS Present Detection Interrupt Mask" "0,1"
|
|
bitfld.byte 0x0 2. "VBUS,VBUS Present Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "SNKVBUS,Sinking VBUS Interrupt Mask" "0,1"
|
|
line.byte 0x1 "FSM,Fault Status Mask Register"
|
|
bitfld.byte 0x1 7. "ALLREGRES,All Registers Reset To Default Interrupt Mask" "0,1"
|
|
bitfld.byte 0x1 6. "FRCOFVBUS,Force Off VBUS Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 5. "AUTDCHF,Auto Discharge Failed Interrupt Mask" "0,1"
|
|
bitfld.byte 0x1 4. "FRCDCHF,Force Discharge Failed Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 3. "VBUSOCPF,Internal or External OCP VBUS Over Current Protection Fault Interrupt Mask" "0,1"
|
|
bitfld.byte 0x1 2. "VBUSOVPF,Internal or External OVP VBUS Over Voltage Protection Fault Interrupt Mask" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "CSO,Config Standard Output Register"
|
|
bitfld.byte 0x0 1. "CNX,Connection Present" "0: No connection (default).,1: Connection."
|
|
bitfld.byte 0x0 0. "COR,Connector Orientation" "0: Normal (CC1=A5 CC2=B5 TX1=A2/A3 RX1=B10/B11)..,1: Flipped (CC2=A5 CC1=B5 TX1=B2/B3 RX1=A10/A11)."
|
|
group.byte 0x1A++0x1
|
|
line.byte 0x0 "RCTL,Role Control Register"
|
|
bitfld.byte 0x0 6. "DRP,Dual Role Play" "0: No DRP. CC1 CC2 fields determine Rp/Rd/Ra or..,1: DRP."
|
|
bitfld.byte 0x0 4.--5. "RP,Resistor for Power Advertising" "0: Rp default,1: Rp 1.5A,2: Rp 3.0A,?"
|
|
newline
|
|
bitfld.byte 0x0 2.--3. "CC2,Configuration Channel 2" "0: Ra,1: Rp defined as in RP field,2: Rd,3: Open (Disconnect or don't care)"
|
|
bitfld.byte 0x0 0.--1. "CC1,Configuration Channel 1" "0: Ra,1: Rp defined as in RP field,2: Rd,3: Open (Disconnect or don't care)"
|
|
line.byte 0x1 "FCTL,Fault Control Register"
|
|
bitfld.byte 0x1 4. "FRCOFVBUS,Force Off VBUS (Source or Sink)" "0: Allows standard input signal Force Off VBUS..,1: Blocks standard input signal Force Off VBUS.."
|
|
bitfld.byte 0x1 2. "VBUSOCPF,Internal or External OCP VBUS Over Current Protection Fault" "0: Internal and external OCP circuit enabled.,1: Internal and external OCP circuit disabled."
|
|
newline
|
|
bitfld.byte 0x1 1. "VBUSOVPF,Internal or External OVP VBUS Over Voltage Protection Fault" "0: Internal and external OVP circuit enabled.,1: Internal and external OVP circuit disabled."
|
|
rgroup.byte 0x1D++0x1
|
|
line.byte 0x0 "CCS,CC Status Register"
|
|
bitfld.byte 0x0 5. "LK4CNX,Looking4Connection" "0: TCPC is not actively looking for a connection. A..,1: TCPC is looking for a connection (toggling as a.."
|
|
bitfld.byte 0x0 4. "CONRES,Connect Result" "0: TCPC is presenting Rp.,1: TCPC is presenting Rd."
|
|
newline
|
|
bitfld.byte 0x0 2.--3. "CC2,CC2 State" "0: SRC.Open (Open Rp),1: SRC.Ra (below maximum VRa),2: SRC.Rd (within the VRd range),3: SNK.Power3.0 (Above minimum VRd-Connect) Detects.."
|
|
bitfld.byte 0x0 0.--1. "CC1,CC1 State" "0: SRC.Open (Open Rp),1: SRC.Ra (below maximum VRa),2: SRC.Rd (within the VRd range),3: SNK.Power3.0 (Above minimum VRd-Connect) Detects.."
|
|
line.byte 0x1 "PS,Power Status Register"
|
|
bitfld.byte 0x1 7. "DBG,Debug Accessory Connected" "0: No debug accessory connected (default).,?"
|
|
bitfld.byte 0x1 6. "INIT,TCPC Initialization" "0: TCPC has completed initialization and all..,1: TCPC is still performing internal initialization.."
|
|
newline
|
|
bitfld.byte 0x1 5. "SRCHIV,Sourcing High Voltage" "0: VSafe5V.,?"
|
|
bitfld.byte 0x1 4. "SRCVBUS,Sourcing VBUS" "0: Sourcing VBUS is disabled.,1: Sourcing VBUS is enabled."
|
|
newline
|
|
bitfld.byte 0x1 3. "VBUSDETE,VBUS Present Detection Enabled" "0: VBUS present detection disabled.,1: VBUS present detection enabled (default)."
|
|
bitfld.byte 0x1 2. "VBUS,VBUS Present" "0: VBUS disconnected.,1: VBUS connected."
|
|
newline
|
|
bitfld.byte 0x1 1. "VCONN,VCONN Present" "0: VCONN is not present.,?"
|
|
bitfld.byte 0x1 0. "SNKVBUS,Sinking VBUS" "0: Sink is disconnected. (Default and if not..,1: TCPC is sinking VBUS to the system load."
|
|
group.byte 0x1F++0x0
|
|
line.byte 0x0 "FS,Fault Status Register"
|
|
bitfld.byte 0x0 7. "ALLREGRES,All Registers Reset To Default" "0: The registers have not been reset since the last..,1: The TCPC has reset all registers to their.."
|
|
bitfld.byte 0x0 6. "FRCOFVBUS,Force Off VBUS" "0: No fault detected no action (default and not..,1: VBUS source/sink has been forced off due to.."
|
|
newline
|
|
bitfld.byte 0x0 3. "VBUSOCPF,Internal or External OCP VBUS Over-Current Protection Fault" "0: Not in an over-current protection state.,1: Over-current fault latched."
|
|
bitfld.byte 0x0 2. "VBUSOVPF,Internal or External OVP VBUS Over-Voltage Protection Fault" "0: Not in an over-voltage protection state.,1: Over-voltage fault latched."
|
|
group.byte 0x23++0x0
|
|
line.byte 0x0 "CMD,Command Register"
|
|
hexmask.byte 0x0 0.--7. 1. "COMMAND,Command"
|
|
group.word 0x24++0x3
|
|
line.word 0x0 "DCP1,Device Capabilities 1 Register"
|
|
bitfld.word 0x0 14. "VBUSOCPR,VBUS OCP Reporting" "0: VBUS OCP is not reported by the TCPC.,1: VBUS OCP is reported by the TCPC."
|
|
bitfld.word 0x0 13. "VBUSOVPR,VBUS OVP Reporting" "0: VBUS OVP is not reported by the TCPC.,1: VBUS OVP is reported by the TCPC."
|
|
newline
|
|
bitfld.word 0x0 12. "BLDDCH,Bleed Discharge" "0: No bleed discharge implemented in TCPC.,1: Bleed discharge is implemented in the TCPC."
|
|
bitfld.word 0x0 11. "FRCDCH,Force Discharge" "0: No force discharge implemented in TCPC.,1: Force discharge is implemented in the TCPC."
|
|
newline
|
|
bitfld.word 0x0 10. "VBUSMSRAL,VBUS Measurement and Alarm Capable" "0: No VBUS voltage measurement nor VBUS alarms.,1: VBUS voltage measurement and VBUS alarms."
|
|
bitfld.word 0x0 8.--9. "SRCRES,Source Resistor Supported" "0: Rp default only,1: Rp 1.5A and default,2: Rp 3.0A 1.5A and default,?"
|
|
newline
|
|
bitfld.word 0x0 5.--7. "ROLES,Roles Supported" "0: USB Type-C Port Manager can configure the Port..,1: Source only,2: Sink only,3: Sink with accessory support,4: DRP only,5: Source Sink DRP Adapter/Cable all supported,6: Source Sink DRP,7: Not valid"
|
|
bitfld.word 0x0 4. "SOPDBG,SOP'_DBG/SOP''_DBG Support" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "SRCVCN,Source VCONN" "0: TCPC is not capable of switching VCONN.,1: TCPC is capable of switching VCONN."
|
|
bitfld.word 0x0 2. "SNKVBUS,Sink VBUS" "0: TCPC is not capable controlling the sink path to..,1: TCPC is capable of controlling the sink path to.."
|
|
newline
|
|
bitfld.word 0x0 1. "SRCHVBUS,Source High Voltage VBUS" "0: TCPC is not capable of controlling the source..,1: TCPC is capable of controlling the source high.."
|
|
bitfld.word 0x0 0. "SRCVBUS,Source VBUS" "0: TCPC is not capable of controlling the source..,1: TCPC is capable of controlling the source path.."
|
|
line.word 0x2 "DCP2,Device Capabilities 2 Register"
|
|
bitfld.word 0x2 8. "WDTMR,Watchdog Timer" "0: Enable Watchdog Timer not implemented.,1: Enable Watchdog Timer implemented."
|
|
bitfld.word 0x2 7. "SKDSCDET,Sink Disconnect Detection" "0: VBUS_SINK_DISCONNECT_THRESHOLD not implemented..,1: VBUS_SINK_DISCONNECT_THRESHOLD implemented."
|
|
newline
|
|
bitfld.word 0x2 6. "STPDSCHTH,Stop Discharge Threshold" "0,1"
|
|
bitfld.word 0x2 4.--5. "VBUSVALSB,VBUS Voltage Alarm LSB" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x2 1.--3. "VCPSP,VCONN Power Supported" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 0. "VCOFC,VCONN Overcurrent Fault Capable" "0,1"
|
|
group.byte 0x28++0x1
|
|
line.byte 0x0 "SIC,Standard Input Capabilities Register"
|
|
bitfld.byte 0x0 2. "VBUSEOVF,VBUS External Over-Voltage Fault" "0: Not present in TCPC.,1: Present in TCPC."
|
|
bitfld.byte 0x0 1. "VBUSEOCF,VBUS External Over-Current Fault" "0: Not present in TCPC.,1: Present in TCPC."
|
|
newline
|
|
bitfld.byte 0x0 0. "FOFVBUS,Force Off VBUS (Source or Sink)" "0: Not present in TCPC.,1: Present in TCPC."
|
|
line.byte 0x1 "SOC,Standard Output Capabilities Register"
|
|
bitfld.byte 0x1 6. "DBGAI,Debug Accessory Indicator" "0: Not present in TCPC.,1: Present in TCPC."
|
|
bitfld.byte 0x1 5. "VBUSPM,VBUS Present Monitor" "0: Not present in TCPC.,1: Present in TCPC."
|
|
newline
|
|
bitfld.byte 0x1 4. "AAAI,Audio Adapter Accessory Indicator" "0: Not present in TCPC.,1: Present in TCPC."
|
|
bitfld.byte 0x1 3. "ACI,Active Cable Indicator" "0: Not present in TCPC.,1: Present in TCPC."
|
|
newline
|
|
bitfld.byte 0x1 2. "MXCFGCTL,MUX Configuration Control" "0: Not present in TCPC.,1: Present in TCPC."
|
|
bitfld.byte 0x1 1. "CNXPR,Connection Present" "0: No connection.,1: Connection."
|
|
newline
|
|
bitfld.byte 0x1 0. "CNROR,Connector Orientation" "0: Not present in TCPC.,1: Present in TCPC."
|
|
wgroup.long 0x80++0xF
|
|
line.long 0x0 "CR,Control Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WAKEY,Register Write Access Key"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0: No effect.,1: Resets the TCPC. A software-triggered hardware.."
|
|
line.long 0x4 "SSR,Set Status Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. "FAULT_STATUS,Fault Status Register Set"
|
|
hexmask.long.byte 0x4 16.--23. 1. "POWER_STATUS,Power Status Register Set"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "CC_STATUS,CC Status Register Set"
|
|
line.long 0x8 "CSR,Clear Status Register"
|
|
hexmask.long.byte 0x8 16.--23. 1. "POWER_STATUS,Power Status Register Clear"
|
|
hexmask.long.byte 0x8 8.--15. 1. "CC_STATUS,CC Status Register Clear"
|
|
line.long 0xC "SAR,Set Alert Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ALERT,Alert Register Set"
|
|
group.long 0xA0++0x3
|
|
line.long 0x0 "UPC,USB Phy Control Register"
|
|
bitfld.long 0x0 29. "BCDETE,Battery Charging Detection Enable" "0: Battery charging detection is disabled.,1: Battery charging detection is enabled."
|
|
bitfld.long 0x0 28. "BCVSRCE,Battery Charging Voltage Source Enable" "0: Battery charging VDP_SRC and VDM_SRC voltage..,1: Battery charging voltage source enable:"
|
|
newline
|
|
bitfld.long 0x0 27. "BCDETSEL,Battery Charging Detection Selection" "0: Battery charging primary detection is selected.,1: Battery charging secondary detection is selected."
|
|
bitfld.long 0x0 26. "BCIDPSRCE,Battery Charging IDP Source Enable" "0: Battery charging IDP current source is disabled.,1: Battery charging IDP current source is enabled.."
|
|
newline
|
|
bitfld.long 0x0 25. "DMPDFE,DM Pull Down Force Enable" "0: DM pull down is not forced to the active state..,1: DM pull down is forced to the active state by.."
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|
bitfld.long 0x0 24. "DMPDFD,DM Pull Down Force Disable" "0: DM pull down is not forced to the inactive state..,1: DM pull down is forced to the inactive state by.."
|
|
newline
|
|
bitfld.long 0x0 12.--13. "RDIPSEL,Type-C Rd or Ip Pull up Current Selection" "0: Type-C pull up current source Ip is off Rd pull..,1: Type-C pull up current source Ip is advertising..,?,?"
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|
bitfld.long 0x0 8.--10. "TCIDCTSEL,Type-C or ID Comparator Threshold Selection" "0: Type-C cell power down,?,2: Type-C VRa Threshold,?,4: Type-C VRd-USB Threshold,?,6: Type-C VRd-1.5 Threshold Type-C VRd Threshold,?"
|
|
rgroup.long 0xA4++0x3
|
|
line.long 0x0 "UPS,USB Phy Status Register"
|
|
bitfld.long 0x0 4. "CC2RDT,Type-C CC2 Comparator or Rd Trim comparator" "0: CC2 or Rd Trim comparator output is low. Voltage..,1: CC2 or Rd Trim comparator output is high."
|
|
bitfld.long 0x0 3. "CC1ID,Type-C CC1 Comparator or ID comparator" "0: CC1 or ID comparator output is low. Voltage is..,1: CC1 or ID comparator output is high. Voltage is.."
|
|
newline
|
|
bitfld.long 0x0 2. "CHGDCP,Charging Port Detection Dedicated Charging Port Detection" "0: No charging port detected,1: Charging port detected"
|
|
bitfld.long 0x0 1. "DM,USB Differential line Minus" "0: DM is low.,1: DM is high."
|
|
newline
|
|
bitfld.long 0x0 0. "DP,USB Differential line Plus" "0: DP is low.,1: DP is high."
|
|
tree.end
|
|
tree "TCPCB"
|
|
base ad:0xE0844000
|
|
rgroup.word 0x0++0xB
|
|
line.word 0x0 "VID,Vendor ID Register"
|
|
hexmask.word 0x0 0.--15. 1. "VID,Vendor ID"
|
|
line.word 0x2 "PID,Product ID Register"
|
|
hexmask.word 0x2 0.--15. 1. "PID,Product ID"
|
|
line.word 0x4 "DID,Device ID Register"
|
|
hexmask.word 0x4 0.--15. 1. "DID,Device ID"
|
|
line.word 0x6 "UTCR,USB Type-C Rev Register"
|
|
hexmask.word 0x6 0.--15. 1. "UTCR,USB Type-C Revision"
|
|
line.word 0x8 "UPDR,USB PD Rev Ver Register"
|
|
hexmask.word 0x8 0.--15. 1. "UPDR,USB-PD Specification Revision and Version"
|
|
line.word 0xA "PDIR,PD Interface Rev Register"
|
|
hexmask.word 0xA 0.--15. 1. "PDIR,USB-Port Controller Interface Specification Revision"
|
|
group.word 0x10++0x3
|
|
line.word 0x0 "AL,Alert Register"
|
|
bitfld.word 0x0 15. "VDA,Vendor Defined Alert" "0: No vendor defined alert has been detected.,1: A vendor defined alert has been detected."
|
|
bitfld.word 0x0 11. "VBUSSNKDS,VBUS Sink Disconnect Detected" "0: No VBUS sink disconnect threshold crossing has..,1: A VBUS sink disconnect threshold crossing has.."
|
|
newline
|
|
bitfld.word 0x0 9. "FLT,Fault" "0: No fault has occurred.,1: A fault has occurred. Read TCPC_FS."
|
|
bitfld.word 0x0 8. "VBUSLO,VBUS Voltage Alarm Low" "0: A low-voltage alarm has not occurred.,1: A low-voltage alarm has occurred."
|
|
newline
|
|
bitfld.word 0x0 7. "VBUSHI,VBUS Voltage Alarm High" "0: A high-voltage alarm has not occurred.,1: A high-voltage alarm has occurred."
|
|
bitfld.word 0x0 1. "PWRS,Power Status" "0: Power status not changed.,1: Power status changed."
|
|
newline
|
|
bitfld.word 0x0 0. "CCS,CC Status" "0: CC status not changed.,1: CC status changed."
|
|
line.word 0x2 "ALM,Alert Mask Register"
|
|
bitfld.word 0x2 15. "VDA,Vendor Defined Alert Interrupt Mask" "0,1"
|
|
bitfld.word 0x2 11. "VBUSSNKDS,VBUS Sink Disconnect Detected Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.word 0x2 9. "FLT,Fault Interrupt Mask" "0,1"
|
|
bitfld.word 0x2 8. "VBUSLO,VBUS Voltage Alarm Low Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.word 0x2 7. "VBUSHI,VBUS Voltage Alarm High Interrupt Mask" "0,1"
|
|
bitfld.word 0x2 1. "PWRS,Power Status Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.word 0x2 0. "CCS,CC Status Interrupt Mask" "0,1"
|
|
group.byte 0x14++0x1
|
|
line.byte 0x0 "PSM,Power Status Mask Register"
|
|
bitfld.byte 0x0 6. "INIT,TCPC Initialization Interrupt Mask" "0,1"
|
|
bitfld.byte 0x0 4. "SRCVBUS,Sourcing VBUS Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "VBUSDETE,VBUS Present Detection Interrupt Mask" "0,1"
|
|
bitfld.byte 0x0 2. "VBUS,VBUS Present Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "SNKVBUS,Sinking VBUS Interrupt Mask" "0,1"
|
|
line.byte 0x1 "FSM,Fault Status Mask Register"
|
|
bitfld.byte 0x1 7. "ALLREGRES,All Registers Reset To Default Interrupt Mask" "0,1"
|
|
bitfld.byte 0x1 6. "FRCOFVBUS,Force Off VBUS Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 5. "AUTDCHF,Auto Discharge Failed Interrupt Mask" "0,1"
|
|
bitfld.byte 0x1 4. "FRCDCHF,Force Discharge Failed Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 3. "VBUSOCPF,Internal or External OCP VBUS Over Current Protection Fault Interrupt Mask" "0,1"
|
|
bitfld.byte 0x1 2. "VBUSOVPF,Internal or External OVP VBUS Over Voltage Protection Fault Interrupt Mask" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "CSO,Config Standard Output Register"
|
|
bitfld.byte 0x0 1. "CNX,Connection Present" "0: No connection (default).,1: Connection."
|
|
bitfld.byte 0x0 0. "COR,Connector Orientation" "0: Normal (CC1=A5 CC2=B5 TX1=A2/A3 RX1=B10/B11)..,1: Flipped (CC2=A5 CC1=B5 TX1=B2/B3 RX1=A10/A11)."
|
|
group.byte 0x1A++0x1
|
|
line.byte 0x0 "RCTL,Role Control Register"
|
|
bitfld.byte 0x0 6. "DRP,Dual Role Play" "0: No DRP. CC1 CC2 fields determine Rp/Rd/Ra or..,1: DRP."
|
|
bitfld.byte 0x0 4.--5. "RP,Resistor for Power Advertising" "0: Rp default,1: Rp 1.5A,2: Rp 3.0A,?"
|
|
newline
|
|
bitfld.byte 0x0 2.--3. "CC2,Configuration Channel 2" "0: Ra,1: Rp defined as in RP field,2: Rd,3: Open (Disconnect or don't care)"
|
|
bitfld.byte 0x0 0.--1. "CC1,Configuration Channel 1" "0: Ra,1: Rp defined as in RP field,2: Rd,3: Open (Disconnect or don't care)"
|
|
line.byte 0x1 "FCTL,Fault Control Register"
|
|
bitfld.byte 0x1 4. "FRCOFVBUS,Force Off VBUS (Source or Sink)" "0: Allows standard input signal Force Off VBUS..,1: Blocks standard input signal Force Off VBUS.."
|
|
bitfld.byte 0x1 2. "VBUSOCPF,Internal or External OCP VBUS Over Current Protection Fault" "0: Internal and external OCP circuit enabled.,1: Internal and external OCP circuit disabled."
|
|
newline
|
|
bitfld.byte 0x1 1. "VBUSOVPF,Internal or External OVP VBUS Over Voltage Protection Fault" "0: Internal and external OVP circuit enabled.,1: Internal and external OVP circuit disabled."
|
|
rgroup.byte 0x1D++0x1
|
|
line.byte 0x0 "CCS,CC Status Register"
|
|
bitfld.byte 0x0 5. "LK4CNX,Looking4Connection" "0: TCPC is not actively looking for a connection. A..,1: TCPC is looking for a connection (toggling as a.."
|
|
bitfld.byte 0x0 4. "CONRES,Connect Result" "0: TCPC is presenting Rp.,1: TCPC is presenting Rd."
|
|
newline
|
|
bitfld.byte 0x0 2.--3. "CC2,CC2 State" "0: SRC.Open (Open Rp),1: SRC.Ra (below maximum VRa),2: SRC.Rd (within the VRd range),3: SNK.Power3.0 (Above minimum VRd-Connect) Detects.."
|
|
bitfld.byte 0x0 0.--1. "CC1,CC1 State" "0: SRC.Open (Open Rp),1: SRC.Ra (below maximum VRa),2: SRC.Rd (within the VRd range),3: SNK.Power3.0 (Above minimum VRd-Connect) Detects.."
|
|
line.byte 0x1 "PS,Power Status Register"
|
|
bitfld.byte 0x1 7. "DBG,Debug Accessory Connected" "0: No debug accessory connected (default).,?"
|
|
bitfld.byte 0x1 6. "INIT,TCPC Initialization" "0: TCPC has completed initialization and all..,1: TCPC is still performing internal initialization.."
|
|
newline
|
|
bitfld.byte 0x1 5. "SRCHIV,Sourcing High Voltage" "0: VSafe5V.,?"
|
|
bitfld.byte 0x1 4. "SRCVBUS,Sourcing VBUS" "0: Sourcing VBUS is disabled.,1: Sourcing VBUS is enabled."
|
|
newline
|
|
bitfld.byte 0x1 3. "VBUSDETE,VBUS Present Detection Enabled" "0: VBUS present detection disabled.,1: VBUS present detection enabled (default)."
|
|
bitfld.byte 0x1 2. "VBUS,VBUS Present" "0: VBUS disconnected.,1: VBUS connected."
|
|
newline
|
|
bitfld.byte 0x1 1. "VCONN,VCONN Present" "0: VCONN is not present.,?"
|
|
bitfld.byte 0x1 0. "SNKVBUS,Sinking VBUS" "0: Sink is disconnected. (Default and if not..,1: TCPC is sinking VBUS to the system load."
|
|
group.byte 0x1F++0x0
|
|
line.byte 0x0 "FS,Fault Status Register"
|
|
bitfld.byte 0x0 7. "ALLREGRES,All Registers Reset To Default" "0: The registers have not been reset since the last..,1: The TCPC has reset all registers to their.."
|
|
bitfld.byte 0x0 6. "FRCOFVBUS,Force Off VBUS" "0: No fault detected no action (default and not..,1: VBUS source/sink has been forced off due to.."
|
|
newline
|
|
bitfld.byte 0x0 3. "VBUSOCPF,Internal or External OCP VBUS Over-Current Protection Fault" "0: Not in an over-current protection state.,1: Over-current fault latched."
|
|
bitfld.byte 0x0 2. "VBUSOVPF,Internal or External OVP VBUS Over-Voltage Protection Fault" "0: Not in an over-voltage protection state.,1: Over-voltage fault latched."
|
|
group.byte 0x23++0x0
|
|
line.byte 0x0 "CMD,Command Register"
|
|
hexmask.byte 0x0 0.--7. 1. "COMMAND,Command"
|
|
group.word 0x24++0x3
|
|
line.word 0x0 "DCP1,Device Capabilities 1 Register"
|
|
bitfld.word 0x0 14. "VBUSOCPR,VBUS OCP Reporting" "0: VBUS OCP is not reported by the TCPC.,1: VBUS OCP is reported by the TCPC."
|
|
bitfld.word 0x0 13. "VBUSOVPR,VBUS OVP Reporting" "0: VBUS OVP is not reported by the TCPC.,1: VBUS OVP is reported by the TCPC."
|
|
newline
|
|
bitfld.word 0x0 12. "BLDDCH,Bleed Discharge" "0: No bleed discharge implemented in TCPC.,1: Bleed discharge is implemented in the TCPC."
|
|
bitfld.word 0x0 11. "FRCDCH,Force Discharge" "0: No force discharge implemented in TCPC.,1: Force discharge is implemented in the TCPC."
|
|
newline
|
|
bitfld.word 0x0 10. "VBUSMSRAL,VBUS Measurement and Alarm Capable" "0: No VBUS voltage measurement nor VBUS alarms.,1: VBUS voltage measurement and VBUS alarms."
|
|
bitfld.word 0x0 8.--9. "SRCRES,Source Resistor Supported" "0: Rp default only,1: Rp 1.5A and default,2: Rp 3.0A 1.5A and default,?"
|
|
newline
|
|
bitfld.word 0x0 5.--7. "ROLES,Roles Supported" "0: USB Type-C Port Manager can configure the Port..,1: Source only,2: Sink only,3: Sink with accessory support,4: DRP only,5: Source Sink DRP Adapter/Cable all supported,6: Source Sink DRP,7: Not valid"
|
|
bitfld.word 0x0 4. "SOPDBG,SOP'_DBG/SOP''_DBG Support" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "SRCVCN,Source VCONN" "0: TCPC is not capable of switching VCONN.,1: TCPC is capable of switching VCONN."
|
|
bitfld.word 0x0 2. "SNKVBUS,Sink VBUS" "0: TCPC is not capable controlling the sink path to..,1: TCPC is capable of controlling the sink path to.."
|
|
newline
|
|
bitfld.word 0x0 1. "SRCHVBUS,Source High Voltage VBUS" "0: TCPC is not capable of controlling the source..,1: TCPC is capable of controlling the source high.."
|
|
bitfld.word 0x0 0. "SRCVBUS,Source VBUS" "0: TCPC is not capable of controlling the source..,1: TCPC is capable of controlling the source path.."
|
|
line.word 0x2 "DCP2,Device Capabilities 2 Register"
|
|
bitfld.word 0x2 8. "WDTMR,Watchdog Timer" "0: Enable Watchdog Timer not implemented.,1: Enable Watchdog Timer implemented."
|
|
bitfld.word 0x2 7. "SKDSCDET,Sink Disconnect Detection" "0: VBUS_SINK_DISCONNECT_THRESHOLD not implemented..,1: VBUS_SINK_DISCONNECT_THRESHOLD implemented."
|
|
newline
|
|
bitfld.word 0x2 6. "STPDSCHTH,Stop Discharge Threshold" "0,1"
|
|
bitfld.word 0x2 4.--5. "VBUSVALSB,VBUS Voltage Alarm LSB" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x2 1.--3. "VCPSP,VCONN Power Supported" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x2 0. "VCOFC,VCONN Overcurrent Fault Capable" "0,1"
|
|
group.byte 0x28++0x1
|
|
line.byte 0x0 "SIC,Standard Input Capabilities Register"
|
|
bitfld.byte 0x0 2. "VBUSEOVF,VBUS External Over-Voltage Fault" "0: Not present in TCPC.,1: Present in TCPC."
|
|
bitfld.byte 0x0 1. "VBUSEOCF,VBUS External Over-Current Fault" "0: Not present in TCPC.,1: Present in TCPC."
|
|
newline
|
|
bitfld.byte 0x0 0. "FOFVBUS,Force Off VBUS (Source or Sink)" "0: Not present in TCPC.,1: Present in TCPC."
|
|
line.byte 0x1 "SOC,Standard Output Capabilities Register"
|
|
bitfld.byte 0x1 6. "DBGAI,Debug Accessory Indicator" "0: Not present in TCPC.,1: Present in TCPC."
|
|
bitfld.byte 0x1 5. "VBUSPM,VBUS Present Monitor" "0: Not present in TCPC.,1: Present in TCPC."
|
|
newline
|
|
bitfld.byte 0x1 4. "AAAI,Audio Adapter Accessory Indicator" "0: Not present in TCPC.,1: Present in TCPC."
|
|
bitfld.byte 0x1 3. "ACI,Active Cable Indicator" "0: Not present in TCPC.,1: Present in TCPC."
|
|
newline
|
|
bitfld.byte 0x1 2. "MXCFGCTL,MUX Configuration Control" "0: Not present in TCPC.,1: Present in TCPC."
|
|
bitfld.byte 0x1 1. "CNXPR,Connection Present" "0: No connection.,1: Connection."
|
|
newline
|
|
bitfld.byte 0x1 0. "CNROR,Connector Orientation" "0: Not present in TCPC.,1: Present in TCPC."
|
|
wgroup.long 0x80++0xF
|
|
line.long 0x0 "CR,Control Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WAKEY,Register Write Access Key"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0: No effect.,1: Resets the TCPC. A software-triggered hardware.."
|
|
line.long 0x4 "SSR,Set Status Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. "FAULT_STATUS,Fault Status Register Set"
|
|
hexmask.long.byte 0x4 16.--23. 1. "POWER_STATUS,Power Status Register Set"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "CC_STATUS,CC Status Register Set"
|
|
line.long 0x8 "CSR,Clear Status Register"
|
|
hexmask.long.byte 0x8 16.--23. 1. "POWER_STATUS,Power Status Register Clear"
|
|
hexmask.long.byte 0x8 8.--15. 1. "CC_STATUS,CC Status Register Clear"
|
|
line.long 0xC "SAR,Set Alert Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ALERT,Alert Register Set"
|
|
group.long 0xA0++0x3
|
|
line.long 0x0 "UPC,USB Phy Control Register"
|
|
bitfld.long 0x0 29. "BCDETE,Battery Charging Detection Enable" "0: Battery charging detection is disabled.,1: Battery charging detection is enabled."
|
|
bitfld.long 0x0 28. "BCVSRCE,Battery Charging Voltage Source Enable" "0: Battery charging VDP_SRC and VDM_SRC voltage..,1: Battery charging voltage source enable:"
|
|
newline
|
|
bitfld.long 0x0 27. "BCDETSEL,Battery Charging Detection Selection" "0: Battery charging primary detection is selected.,1: Battery charging secondary detection is selected."
|
|
bitfld.long 0x0 26. "BCIDPSRCE,Battery Charging IDP Source Enable" "0: Battery charging IDP current source is disabled.,1: Battery charging IDP current source is enabled.."
|
|
newline
|
|
bitfld.long 0x0 25. "DMPDFE,DM Pull Down Force Enable" "0: DM pull down is not forced to the active state..,1: DM pull down is forced to the active state by.."
|
|
bitfld.long 0x0 24. "DMPDFD,DM Pull Down Force Disable" "0: DM pull down is not forced to the inactive state..,1: DM pull down is forced to the inactive state by.."
|
|
newline
|
|
bitfld.long 0x0 12.--13. "RDIPSEL,Type-C Rd or Ip Pull up Current Selection" "0: Type-C pull up current source Ip is off Rd pull..,1: Type-C pull up current source Ip is advertising..,?,?"
|
|
bitfld.long 0x0 8.--10. "TCIDCTSEL,Type-C or ID Comparator Threshold Selection" "0: Type-C cell power down,?,2: Type-C VRa Threshold,?,4: Type-C VRd-USB Threshold,?,6: Type-C VRd-1.5 Threshold Type-C VRd Threshold,?"
|
|
rgroup.long 0xA4++0x3
|
|
line.long 0x0 "UPS,USB Phy Status Register"
|
|
bitfld.long 0x0 4. "CC2RDT,Type-C CC2 Comparator or Rd Trim comparator" "0: CC2 or Rd Trim comparator output is low. Voltage..,1: CC2 or Rd Trim comparator output is high."
|
|
bitfld.long 0x0 3. "CC1ID,Type-C CC1 Comparator or ID comparator" "0: CC1 or ID comparator output is low. Voltage is..,1: CC1 or ID comparator output is high. Voltage is.."
|
|
newline
|
|
bitfld.long 0x0 2. "CHGDCP,Charging Port Detection Dedicated Charging Port Detection" "0: No charging port detected,1: Charging port detected"
|
|
bitfld.long 0x0 1. "DM,USB Differential line Minus" "0: DM is low.,1: DM is high."
|
|
newline
|
|
bitfld.long 0x0 0. "DP,USB Differential line Plus" "0: DP is low.,1: DP is high."
|
|
tree.end
|
|
tree.end
|
|
tree "TDES (Triple Data Encryption Standard)"
|
|
base ad:0xE2014000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 24. "UNLOCK,Unlock Processing" "0: No effect.,1: Unlocks the processing in case of abnormal event.."
|
|
bitfld.long 0x0 8. "SWRST,Software Reset" "0: No effect,1: Resets the TDES. A software-triggered reset of.."
|
|
newline
|
|
bitfld.long 0x0 0. "START,Start Processing" "0: No effect,1: Starts Manual encryption/decryption process."
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 31. "TAMPCLR,Tamper Pin Clear Key Enable" "0: A tamper detection event has no effect on..,1: A tamper detection event immediately clears.."
|
|
bitfld.long 0x0 16.--17. "CFBS,Cipher Feedback Data Size" "0: 64-bit,1: 32-bit,2: 16-bit,3: 8-bit"
|
|
newline
|
|
bitfld.long 0x0 15. "LOD,Last Output Data Mode" "0: No effect.,1: The DATRDY flag is cleared when at least one of.."
|
|
bitfld.long 0x0 12.--13. "OPMOD,Operating Mode" "0: Electronic Code Book mode,1: Cipher Block Chaining mode,2: Output Feedback mode,3: Cipher Feedback mode"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "SMOD,Start Mode" "0: Manual Mode,1: Auto Mode,2: TDES_IDATAR0 accesses only Auto mode,?"
|
|
bitfld.long 0x0 7. "PKRS,Private Key Internal Register Select" "0: The keys used by the TDES are in the..,1: The keys used by the TDES are the in the Private.."
|
|
newline
|
|
bitfld.long 0x0 6. "PKWO,Private Key Write Once" "0: The Private Key internal registers can be..,1: The Private Key internal registers can be.."
|
|
bitfld.long 0x0 4. "KEYMOD,Key Mode" "0: Three-key algorithm is selected.,1: Two-key algorithm is selected. There is no need.."
|
|
newline
|
|
bitfld.long 0x0 1.--2. "TDESMOD,ALGORITHM Mode" "0: Single DES processing using TDES_KEY1WRy.,1: Triple DES processing using TDES_KEY1WRy..,2: XTEA processing using TDES_KEY1WRy and..,?"
|
|
bitfld.long 0x0 0. "CIPHER,Processing Mode" "0: Decrypts data.,1: Encrypts data."
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 16. "SECE,Security and/or Safety Event Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 8. "URAD,Unspecified Register Access Detection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 16. "SECE,Security and/or Safety Event Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 8. "URAD,Unspecified Register Access Detection Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "DATRDY,Data Ready Interrupt Disable" "0,1"
|
|
rgroup.long 0x18++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 16. "SECE,Security and/or Safety Event Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 8. "URAD,Unspecified Register Access Detection Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 16. "SECE,Security and/or Safety Event Interrupt Mask" "0: There is no security report in TDES_WPSR.,1: One security flag is set in TDES_WPSR."
|
|
bitfld.long 0x4 12.--13. "URAT,Unspecified Register Access (cleared by setting TDES_CR.SWRST)" "0: TDES_IDATAR written during data processing when..,1: TDES_ODATAR read during data processing.,2: TDES_MR written during data processing.,3: Write-only register read access."
|
|
newline
|
|
bitfld.long 0x4 8. "URAD,Unspecified Register Access Detection Status (cleared by setting TDES_CR.SWRST)" "0: No unspecified register access has been detected..,1: At least one unspecified register access has.."
|
|
bitfld.long 0x4 0. "DATRDY,Data Ready (cleared by setting TDES_CR.START or TDES_CR.SWRST or by reading TDES_ODATARx)" "0: Output data is not valid.,1: Encryption or decryption process is completed."
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "KEY1WR[$1],Key 1 Word Register x"
|
|
hexmask.long 0x0 0.--31. 1. "KEY1W,Key 1 Word"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x28)++0x3
|
|
line.long 0x0 "KEY2WR[$1],Key 2 Word Register x"
|
|
hexmask.long 0x0 0.--31. 1. "KEY2W,Key 2 Word"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x30)++0x3
|
|
line.long 0x0 "KEY3WR[$1],Key 3 Word Register x"
|
|
hexmask.long 0x0 0.--31. 1. "KEY3W,Key 3 Word"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x40)++0x3
|
|
line.long 0x0 "IDATAR[$1],Input Data Register x"
|
|
hexmask.long 0x0 0.--31. 1. "IDATA,Input Data"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x50)++0x3
|
|
line.long 0x0 "ODATAR[$1],Output Data Register x"
|
|
hexmask.long 0x0 0.--31. 1. "ODATA,Output Data"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x60)++0x3
|
|
line.long 0x0 "IVR[$1],Initialization Vector Register x"
|
|
hexmask.long 0x0 0.--31. 1. "IV,Initialization Vector"
|
|
repeat.end
|
|
group.long 0x70++0x3
|
|
line.long 0x0 "XTEA_RNDR,XTEA Rounds Register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "XTEA_RNDS,Number of Rounds"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 5.--7. "ACTION,Action on Abnormal Event Detection" "0: No action (stop or clear key) is performed when..,1: If a processing is in progress when the..,2: If a processing is in progress when the..,3: If a processing is in progress when the..,4: If a processing is in progress when the..,5: If a processing is in progress when the..,6: If a processing is in progress when the..,?"
|
|
newline
|
|
bitfld.long 0x0 4. "FIRSTE,First Error Report Enable" "0: The last write protection violation source is..,1: Only the first write protection violation source.."
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
bitfld.long 0x0 31. "ECLASS,Software Error Class (cleared on read)" "0: An abnormal access that does not affect system..,1: An access is performed into key input data.."
|
|
hexmask.long.byte 0x0 24.--27. 1. "SWETYP,Software Error Type (cleared on read)"
|
|
newline
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source (cleared on read)"
|
|
bitfld.long 0x0 4. "PKRPVS,Private Key Register Protection Violation Status (cleared on read)" "0: No Private Key internal register access..,1: A Private Key internal register access violation.."
|
|
newline
|
|
bitfld.long 0x0 3. "SWE,Software Control Error (cleared on read)" "0: No software error has occurred since the last..,1: A software error has occurred since the last.."
|
|
bitfld.long 0x0 2. "SEQE,Internal Sequencer Error (cleared on read)" "0: No peripheral internal sequencer error has..,1: A peripheral internal sequencer error has.."
|
|
newline
|
|
bitfld.long 0x0 1. "CGD,Clock Glitch Detected (cleared on read)" "0: The clock monitoring circuitry has not been..,1: The clock monitoring circuitry has been.."
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status (cleared on read)" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
|
|
tree.end
|
|
tree "TRNG (True Random Number Generator)"
|
|
base ad:0xE2010000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WAKEY,Register Write Access Key"
|
|
bitfld.long 0x0 0. "ENABLE,Enable TRNG to Provide Random Values" "0: Disables the TRNG if 0x524E47 ('RNG' in ASCII)..,1: Enables the TRNG if 0x524E47 ('RNG' in ASCII) is.."
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 0. "HALFR,Half Rate Enable" "0: Maximum stream rate provided.,1: Half maximum stream rate provided if the.."
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x0 "PKBCR,Private Key Bus Control Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "WAKEY,Register Write Access Key"
|
|
hexmask.long.byte 0x0 8.--15. 1. "KLENGTH,Key Length"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "KSLAVE,Key Bus Slave" "0: TDES,1: AES,2: TZAESB,3: OTPC"
|
|
bitfld.long 0x0 0. "KID,Key ID" "0: TrustZone Secure Key access.,1: TrustZone Not Secure Key access."
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 2. "EOTPKB,End Of Transfer on Private Key Bus Interrupt Enable" "0: No effect.,1: Enables the corresponding interrupt."
|
|
bitfld.long 0x0 1. "SECE,Security and/or Safety Event Interrupt Enable" "0: No effect.,1: Enables the corresponding interrupt."
|
|
newline
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready Interrupt Enable" "0: No effect.,1: Enables the corresponding interrupt."
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 2. "EOTPKB,End Of Transfer on Private Key Bus Interrupt Disable" "0: No effect.,1: Disables the corresponding interrupt."
|
|
bitfld.long 0x4 1. "SECE,Security and/or Safety Event Interrupt Disable" "0: No effect.,1: Disables the corresponding interrupt."
|
|
newline
|
|
bitfld.long 0x4 0. "DATRDY,Data Ready Interrupt Disable" "0: No effect.,1: Disables the corresponding interrupt."
|
|
rgroup.long 0x18++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 2. "EOTPKB,End Of Transfer on Private Key Bus Interrupt Mask" "0: The corresponding interrupt is not enabled.,1: The corresponding interrupt is enabled."
|
|
bitfld.long 0x0 1. "SECE,Security and/or Safety Event Interrupt Mask" "0: The corresponding interrupt is not enabled.,1: The corresponding interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready Interrupt Mask" "0: The corresponding interrupt is not enabled.,1: The corresponding interrupt is enabled."
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 2. "EOTPKB,End Of Transfer on Private Key Bus (cleared on read)" "0: No private key bus transfer has ended since the..,1: The private key bus transfer has ended."
|
|
bitfld.long 0x4 1. "SECE,Security and/or Safety Event (cleared on read)" "0: No security or safety event occurred.,1: One or more safety or security event occurred.."
|
|
newline
|
|
bitfld.long 0x4 0. "DATRDY,Data Ready (cleared on read)" "0: Output data is not valid or TRNG is disabled.,1: New random value is completed since the last.."
|
|
rgroup.long 0x50++0x3
|
|
line.long 0x0 "ODATA,Output Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "ODATA,Output Data"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 4. "FIRSTE,First Error Report Enable" "0: The last write protection violation source is..,1: Only the first write protection violation source.."
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0: Disables the write protection on control..,1: Enables the write protection on control register.."
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0: Disables the write protection on interrupt..,1: Enables the write protection on interrupt.."
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0: Disables the write protection if WPKEY..,1: Enables the write protection if WPKEY.."
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
bitfld.long 0x0 31. "ECLASS,Software Error Class (cleared on read)" "0: An abnormal access that does not affect system..,1: Reading TRNG_ODATA when TRNG was disabled or.."
|
|
hexmask.long.byte 0x0 24.--27. 1. "SWETYP,Software Error Type (cleared on read)"
|
|
newline
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source (cleared on read)"
|
|
bitfld.long 0x0 3. "SWE,Software Control Error (cleared on read)" "0: No software error has occurred since the last..,1: A software error has occurred since the last.."
|
|
newline
|
|
bitfld.long 0x0 2. "SEQE,Internal Sequencer Error (cleared on read)" "0: No peripheral internal sequencer error has..,1: A peripheral internal sequencer error has.."
|
|
bitfld.long 0x0 1. "CGD,Clock Glitch Detected (cleared on read)" "0: The clock monitoring circuitry has not been..,1: The clock monitoring circuitry has been.."
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status (cleared on read)" "0: No write protection violation has occurred since..,1: A write protection violation has occurred since.."
|
|
tree.end
|
|
AUTOINDENT.OFF
|