29470 lines
2.0 MiB
29470 lines
2.0 MiB
; --------------------------------------------------------------------------------
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; @Title: AT91SAM3AX4C/4E/8C/8E On-Chip Peripherals
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; @Props: Released
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; @Author: EMK
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; @Changelog: 2012-07-13 EMK
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; @Manufacturer: ATMEL - Atmel Corporation
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; @Doc: doc11057.pdf (2012-05-28)
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; @Core: Cortex-M3
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; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perat91sam3x.per 17736 2024-04-08 09:26:07Z kwisniewski $
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width 0x0b
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tree.close "Core Registers (Cortex-M3)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 11.
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group 0x10--0x1b
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,Clock Source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "Not SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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;group 0x14++0x03
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line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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;group 0x18++0x03
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line.long 0x08 "SYST_CVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Current Value"
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rgroup 0x1c++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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textline " "
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rgroup 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
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bitfld.long 0x00 20.--23. " VARIANT ,Implementation Defined Variant Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. " CONSTANT ,Constant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Number of Processor"
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bitfld.long 0x00 0.--3. " REVISION ,Implementation Defined Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group 0xd04--0xd17
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Not set,Set"
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bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not set,Set"
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bitfld.long 0x00 27. " PENDSVCLR ,Clear Pending pendSV Bit" "Not cleared,Cleared"
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textline " "
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bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not set,Set"
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bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "Not cleared,Cleared"
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bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,Interrupt Pending Flag" "Not pending,Pending"
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hexmask.long.word 0x00 12.--21. 1. " VECTPENDING ,Pending ISR Number Field"
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bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
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textline " "
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,Active ISR Number Field"
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;group 0xd08++0x03
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line.long 0x04 "VTOR,Vector Table Offset Register"
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bitfld.long 0x04 29. " TBLBASE ,Table Base" "Code,RAM"
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hexmask.long.tbyte 0x04 7.--28. 1. " TBLOFF ,Vector Table Base Offset Field"
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;group 0xd0c++0x03
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
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rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "Not cleared,Cleared all"
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bitfld.long 0x08 0. " VECTRESET ,System Reset" "No reset,Reset"
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;group 0xd10++0x03
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line.long 0x0c "SCR,System Control Register"
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bitfld.long 0x0c 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0c 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
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bitfld.long 0x0c 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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;group 0xd14++0x03
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line.long 0x10 "CCR,Configuration Control Register"
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bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte,8-byte"
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bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI, Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
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bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 1. " USERSETMPEND ,Enable User Access to the Software Trigger Exception Register" "Disabled,Enabled"
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bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
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group 0xd18--0xd23
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line.long 0x00 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x00 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x00 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x00 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x00 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x04 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x04 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x04 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x04 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x04 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x08 "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x08 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x08 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x08 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x08 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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group 0xd24++0x3
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line.long 0x00 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x00 18. " USGFAULTENA ,USGFAULTENA" "Disabled,Enabled"
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bitfld.long 0x00 17. " BUSFAULTENA ,BUSFAULTENA" "Disabled,Enabled"
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bitfld.long 0x00 16. " MEMFAULTENA ,MEMFAULTENA" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 15. " SVCALLPENDED ,SVCall is Pended Started" "Not replaced,Replaced"
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bitfld.long 0x00 14. " BUSFAULTPENDED ,BusFault is Pended Started" "Not replaced,Replaced"
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bitfld.long 0x00 13. " MEMFAULTPENDED ,MemManage is Pended Started" "Not replaced,Replaced"
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textline " "
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bitfld.long 0x00 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
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bitfld.long 0x00 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
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bitfld.long 0x00 8. " MONITORACT ,Monitor is Active" "Not active,Active"
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textline " "
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bitfld.long 0x00 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
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bitfld.long 0x00 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
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bitfld.long 0x00 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
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textline " "
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bitfld.long 0x00 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
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group 0xd28--0xd3b
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line.byte 0x0 "MMFSR,Memory Manage Fault Status Register"
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bitfld.byte 0x0 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x0 4. " MSTKERR ,Stacking Access Violations" "No error,Error"
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bitfld.byte 0x0 3. " MUNSTKERR ,Unstack Access Violations" "No error,Error"
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textline " "
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bitfld.byte 0x0 1. " DACCVIOL ,Data Access Violation" "No error,Error"
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bitfld.byte 0x0 0. " IACCVIOL ,Instruction Access Violation" "No error,Error"
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;group 0xd29++0x00
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid" "Not valid,Valid"
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bitfld.byte 0x01 4. " STKERR ,Stacking from Exception has Caused Bus Faults" "No error,Error"
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bitfld.byte 0x01 3. " UNSTKERR ,Unstack from Exception Return has Caused Bus Faults" "No error,Error"
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textline " "
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise Data Bus Error" "No error,Error"
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bitfld.byte 0x01 1. " PRECISERR ,Precise Data Bus Error Return" "No error,Error"
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bitfld.byte 0x01 0. " IBUSERR ,Instruction Bus Error Flag" "No error,Error"
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;group 0xd2a++0x01
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line.word 0x02 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x02 9. " DIVBYZERO ,Illegal PC Load" "No error,Error"
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bitfld.word 0x02 8. " UNALIGNED ,Illegal Unaligned Access" "No error,Error"
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bitfld.word 0x02 3. " NOCP ,Attempt to use a coprocessor instruction" "No error,Error"
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textline " "
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bitfld.word 0x02 2. " INVPC ,Attempt to Load EXC_RETURN into PC Illegally" "No error,Error"
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bitfld.word 0x02 1. " INVSTATE , Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x02 0. " UNDEFINSTR ,Illegal Processor State" "No error,Error"
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;group 0xd2c++0x03
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line.long 0x04 "HFSR,Hard Fault Status Register"
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bitfld.long 0x04 31. " DEBUGEVT ,This Bit is Set if There is a Fault Related to Debug" "No error,Error"
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bitfld.long 0x04 30. " FORCED ,Hard Fault Activated" "No error,Error"
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bitfld.long 0x04 1. " VECTTBL ,Bus Fault" "No error,Error"
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;group 0xd30++0x03
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line.long 0x08 "DFSR,Debug Fault Status Register"
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bitfld.long 0x08 4. " EXTERNAL ,External Debug Request Flag" "Not asserted,Asserted"
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bitfld.long 0x08 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
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bitfld.long 0x08 2. " DWTTRAP ,Data Watchpoint and Trace (DWT) Flag" "Not matched,Matched"
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textline " "
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bitfld.long 0x08 1. " BKPT ,BKPT Flag" "Not executed,Executed"
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bitfld.long 0x08 0. " HALTED ,Halt Request Flag" "Not requested,Requested"
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;group 0xd34++0x03
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line.long 0xc "MMFAR,Memory Manage Fault Address Register"
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;group 0xd38++0x03
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line.long 0x10 "BFAR,Bus Fault Address Register"
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wgroup 0xf00++0x03
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line.long 0x00 "STIR,Software Trigger Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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tree "Feature Registers"
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width 10.
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rgroup.long 0xD40++0x0B
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
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bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
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line.long 0x04 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
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line.long 0x08 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
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hgroup.long 0xD4C++0x03
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hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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rgroup.long 0xD50++0x03
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
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bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
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textline " "
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bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
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bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
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hgroup.long 0xD54++0x03
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hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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rgroup.long 0xD58++0x03
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
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rgroup.long 0xD60++0x13
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line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
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bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
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bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
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bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
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line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
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bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
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bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
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bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
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textline " "
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bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
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line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
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bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
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bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
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bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
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textline " "
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bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
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bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
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bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
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textline " "
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bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
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line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
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bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
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bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
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bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
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textline " "
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bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
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bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
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textline " "
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bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
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line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
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bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
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bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
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textline " "
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bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
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bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
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bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
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tree.end
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tree "CoreSight Identification Registers"
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width 6.
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rgroup.long 0xFE0++0x0F
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line.long 0x00 "PID0,Peripheral ID0"
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hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
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line.long 0x04 "PID1,Peripheral ID1"
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hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
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hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
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line.long 0x08 "PID2,Peripheral ID2"
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hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
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bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
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hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
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line.long 0x0c "PID3,Peripheral ID3"
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hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
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hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
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rgroup.long 0xFD0++0x03
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line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x20000)
|
|
group 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x20001)
|
|
group 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 5. " C_SNAPSTALL ,Halting debug to gain control of the core" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " C_STEP ,Core Step" "No step,Step"
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x0)
|
|
group 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x00001)
|
|
group 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 2. " C_STEP ,Core Step" "No step,Step"
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
wgroup 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,R13,R14,R15,xPSR/ Flags,MSP,PSP,RAZ/WI,CONTROL/FAULTMASK/BASEPRI/PRIMASK,?..."
|
|
group 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group 0x00--0x27
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 8.--11. " NUM_LIT ,Number of Literal Slots Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE ,Number of Code Slots Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
;group 0x04++0x03
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
hexmask.long.tbyte 0x04 5.--28. 1. " REMAP ,Remap Base Address Field"
|
|
;group 0x08++0x03
|
|
line.long 0x8 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x8 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x8 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x8 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0xC "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0xC 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0xC 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0xC 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x10 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x10 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x10 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x10 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x14 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x14 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x14 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x14 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x18 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x18 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x18 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x18 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x1C "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x1C 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x1C 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x1C 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x20 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x20 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x20 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x20 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x24 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x24 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x24 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x24 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
tree "Coresight Management Registers"
|
|
rgroup 0xfd0--0xfff
|
|
line.long 0x00 "PID4,Peripheral ID4"
|
|
line.long 0x04 "PID5,Peripheral ID5"
|
|
line.long 0x08 "PID6,Peripheral ID6"
|
|
line.long 0x0c "PID7,Peripheral ID7"
|
|
line.long 0x10 "PID0,Peripheral ID0"
|
|
line.long 0x14 "PID1,Peripheral ID1"
|
|
line.long 0x18 "PID2,Peripheral ID2"
|
|
line.long 0x1c "PID3,Peripheral ID3"
|
|
line.long 0x20 "CID0,Component ID0"
|
|
line.long 0x24 "CID1,Component ID1"
|
|
line.long 0x28 "CID2,Component ID2"
|
|
line.long 0x2c "CID3,Component ID3"
|
|
tree.end
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group 0x00--0x1B
|
|
line.long 0x00 "DWT_CTRL,DWT Control Register"
|
|
bitfld.long 0x00 28.--31. " NUMCOMP ,Number of Comparators Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables Cycle Count Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables Folded Instruction Count Event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables LSU Count Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables Sleep Count Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables Interrupt Overhead Event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables CPI Count Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables Interrupt Event Tracing" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables PC Sampling Event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Feed Synchronization Pulse to the ITM SYNCEN Control" "Disabled,24,26,28"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects a Tap on the DWT_CYCCNT Register" "Bit 6,Bit 10"
|
|
bitfld.long 0x00 5.--8. " POSTCNT ,Post-Scalar Counter for CYCTAP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload Value for POSTCNT Post-Scalar Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enable the DWT_CYCCNT Counter" "Disabled,Enabled"
|
|
;group 0x04++0x03
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count register"
|
|
;group 0x08++0x03
|
|
line.long 0x08 "DWT_CPICNT,DWT CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
;group 0x0c++0x03
|
|
line.long 0x0c "DWT_EXCCNT,DWT Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
;group 0x10++0x03
|
|
line.long 0x10 "DWT_SLEEPCNT,DWT Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
;group 0x14++0x03
|
|
line.long 0x14 "DWT_LSUCNT,DWT LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
;group 0x18++0x03
|
|
line.long 0x18 "DWT_FOLDCNT,DWT Fold Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x20)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
endif
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x38))&0x20)==0x00)
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
endif
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x48))&0x20)==0x00)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
else
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
endif
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x58))&0x20)==0x00)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
endif
|
|
tree "Coresight Management Registers"
|
|
rgroup 0xfd0--0xfff
|
|
line.long 0x00 "PID4,Peripheral ID4"
|
|
line.long 0x04 "PID5,Peripheral ID5"
|
|
line.long 0x08 "PID6,Peripheral ID6"
|
|
line.long 0x0c "PID7,Peripheral ID7"
|
|
line.long 0x10 "PID0,Peripheral ID1"
|
|
line.long 0x14 "PID1,Peripheral ID2"
|
|
line.long 0x18 "PID2,Peripheral ID3"
|
|
line.long 0x1c "PID3,Peripheral ID4"
|
|
line.long 0x20 "CID0,Component ID0"
|
|
line.long 0x24 "CID1,Component ID1"
|
|
line.long 0x28 "CID2,Component ID2"
|
|
line.long 0x2c "CID3,Component ID3"
|
|
tree.end
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
config 16. 8.
|
|
tree "RSTC (Reset Controller)"
|
|
base ad:0x400E1A00
|
|
width 9.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "RSTC_CR,Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password"
|
|
sif !cpuis("ATSAMA5D2?")
|
|
bitfld.long 0x00 3. " EXTRST ,External Reset" "No effect,NRST asserted"
|
|
endif
|
|
sif (cpuis("ATSAMV7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2*"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " PROCRST ,Processor Reset" "No effect,Processor reset"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 2. " PERRST ,Peripheral Reset" "No effect,Peripherals reset"
|
|
bitfld.long 0x00 0. " PROCRST ,Processor Reset" "No effect,Processor reset"
|
|
endif
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "RSTC_SR,Status Register"
|
|
in
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RSTC_MR,Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password"
|
|
sif (!cpuis("ATSAMA5D41")&&!cpuis("ATSAMA5D42")&&!cpuis("ATSAMA5D43")&&!cpuis("ATSAMA5D44")&&!cpuis("ATSAMA5D2?"))
|
|
bitfld.long 0x00 8.--11. " ERSTL ,External Reset Length" "2 slow clock cycles (60 us),4 slow clock cycles (120 us),8 slow clock cycles (240 us),16 slow clock cycles (480 us),32 slow clock cycles (960 us),64 slow clock cycles (1.92 ms),128 slow clock cycles (3.84 ms),256 slow clock cycles (7.68 ms),512 slow clock cycles (15.36 ms),1024 slow clock cycles (30.72 ms),2048 slow clock cycles (61.44 ms),4096 slow clock cycles (122.88 ms),8192 slow clock cycles (245.76 ms),16384 slow clock cycles (491.52 ms),32768 slow clock cycles (0.98304 s),65536 slow clock cycles (1.96608 s)"
|
|
endif
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAMA5D36"))
|
|
textline " "
|
|
bitfld.long 0x00 4. " URSTIEN ,User Reset Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " URSTEN ,User Reset Enable" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "RTT (Real-time Timer)"
|
|
base ad:0x400E1A30
|
|
width 4.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "MR,Real-Time Timer Mode Register"
|
|
sif (cpuis("ATSAM4E*")||cpuis("ATSAM4N*")||cpuis("ATSAM4S*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*"))
|
|
bitfld.long 0x00 24. " RTC1HZ ,Real-time clock 1Hz clock selection" "16-bit prescaler,RTC 1 Hz clock"
|
|
bitfld.long 0x00 20. " RTTDIS ,Real-time timer disable" "No,Yes"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 18. " RTTRST ,Real-time timer restart" "No restart,Restart"
|
|
bitfld.long 0x00 17. " RTTINCIEN ,Real-time timer increment interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ALMIEN ,Alarm interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--15. 1. " RTPRES ,Real-time timer prescaler value"
|
|
line.long 0x04 "AR,Real-Time Timer Alarm Register"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "VR,Real-Time Timer Value Register"
|
|
newline
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "SR,Real-Time Timer Status Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
tree "RTC (Real-time Clock)"
|
|
base ad:0x400E1A60
|
|
width 12.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "RTC_CR,Control Register"
|
|
bitfld.long 0x00 16.--17. " CALEVSEL ,Calendar Event Selection" "Week change,Month change,Year change,Year change"
|
|
bitfld.long 0x00 8.--9. " TIMEVSEL ,Time Event Selection" "Minute change,Hour change,Every day at midnight,Every day at noon"
|
|
textline " "
|
|
bitfld.long 0x00 1. " UPDCAL ,Update Request Calendar Register" "No effect,Stopped"
|
|
bitfld.long 0x00 0. " UPDTIM ,Update Request Time Register" "No effect,Stopped"
|
|
line.long 0x04 "RTC_MR,RTC Mode Register"
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
sif !cpuis("ATSAM4N*")
|
|
bitfld.long 0x04 28.--29. " TPERIO ,Period of the Output Pulse" "1 s,500 ms,250 ms,125 ms"
|
|
bitfld.long 0x04 24.--26. " THIGH ,High Duration of the Output Pulse" "31.2 ms,15.6 ms,3.91 ms,967 u_s,488 u_s,122 u_s,30.5 u_s,15.2 u_s"
|
|
textline " "
|
|
bitfld.long 0x04 20.--22. " OUT1 ,RTCOUT1 Output Source Selection" "No waveform,1 Hz square wave,32 Hz square wave,64 Hz square wave,512 Hz square wave,Output toggles when alarm flag rises,Output is a copy of the alarm flag,Duty cycle programmable pulse"
|
|
textline " "
|
|
bitfld.long 0x04 16.--18. " OUT0 ,RTCOUT0 Output Source Selection" "No waveform,1 Hz square wave,32 Hz square wave,64 Hz square wave,512 Hz square wave,Output toggles when alarm flag rises,Output is a copy of the alarm flag,Duty cycle programmable pulse"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 15. " HIGHPPM ,HIGH PPM Correction" "Lower,Higher"
|
|
hexmask.long.byte 0x04 8.--14. 1. " CORRECTION ,Correction"
|
|
textline " "
|
|
bitfld.long 0x04 4. " NEGPPM ,NEGative PPM Correction" "Positive,Negative"
|
|
bitfld.long 0x04 1. " PERSIAN ,PERSIAN Calendar" "Gregorian,Persian"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 0. " HRMOD ,12/24 Hour Mode" "24,12"
|
|
if ((data.long(ad:0x400E1A60+0x04)&0x1)==0x1)
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "RTC_TIMR,Time Register"
|
|
bitfld.long 0x00 22. " AMPM ,Ante Meridiem Post Meridiem Indicator" "AM,PM"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RTC_TIMR,Time Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
endif
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "RTC_CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current Date" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 21.--23. " DAY ,Current Day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MONTH ,Current Month" ",1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 12.--15. " YEAR ,Current Year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CENT ,Current Century" "0,1,2,3,-,?..."
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
if ((d.l(ad:0x400E1A60+0x04)&0x00000001)==0x00000001)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RTC_TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " AMPM ,AM/PM Indicator" "AM,PM"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " MINEN ,Minute Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SECEN ,Second Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RTC_TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current Hour" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " MINEN ,Minute Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Current Minute" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SECEN ,Second Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current Second" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
endif
|
|
width 12.
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date Alarm" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " MTHEN ,Month Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month Alarm" "0,1"
|
|
bitfld.long 0x00 16.--19. "," "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
width 12.
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "RTC_SR,Status Register"
|
|
sif (cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 5. " TDERR ,Time and/or Date Free Running Error" "Not occurred,Occurred"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " CALEV ,Calendar Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " TIMEV ,Time Event" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEC ,Second Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " ALARM ,Alarm Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ACKUPD ,Acknowledge for Update" "No,Yes"
|
|
wgroup.long 0x1C++0x0B
|
|
line.long 0x00 "RTC_SCCR,Status Clear Register"
|
|
sif (cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 5. " TDERRCLR ,Time and/or Date Free Running Error Clear" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " CALCLR ,Calendar Event Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x00 3. " TIMCLR ,Time Event Interrupt Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SECCLR ,Second Event Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " ALRCLR ,Alarm Flag Interrupt Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ACKCLR ,Acknowledge for Update Interrupt Clear" "No effect,Clear"
|
|
line.long 0x04 "RTC_IER,Interrupt Enable Register"
|
|
sif (cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x04 5. " TDERREN ,Time and/or Date Free Running Error Interrupt Enable" "No effect,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 4. " CALEN ,Calendar Event Interrupt Enable" "No effect,Enabled"
|
|
bitfld.long 0x04 3. " TIMEN ,Time Event Interrupt Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " SECEN ,Second Event Interrupt Enable" "No effect,Enabled"
|
|
bitfld.long 0x04 1. " ALREN ,Alarm Flag Interrupt Enable" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ACKEN ,Acknowledge for Update Interrupt Enable" "No effect,Enabled"
|
|
line.long 0x08 "RTC_IDR,Interrupt Disable Register"
|
|
sif (cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x08 5. " TDERRDIS ,Time and/or Date Free Running Error Interrupt Disable" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 4. " CALDIS ,Calendar Event Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x08 3. " TIMDIS ,Time Event Interrupt Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SECDIS ,Second Event Interrupt Disable" "No,Yes"
|
|
bitfld.long 0x08 1. " ALRDIS ,Alarm Flag Interrupt Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x08 0. " ACKDIS ,Acknowledge for Update Interrupt Disable" "No,Yes"
|
|
rgroup.long 0x28++0x7
|
|
line.long 0x00 "RTC_IMR,Interrupt Mask Register"
|
|
bitfld.long 0x00 4. " CAL ,Calendar Event Interrupt Mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TIM ,Time Event Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEC ,Second Event Interrupt Mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ALR ,Alarm Flag Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ACK ,Acknowledge for Update Interrupt Mask" "Disabled,Enabled"
|
|
line.long 0x04 "RTC_VER,Valid Entry Register"
|
|
bitfld.long 0x04 3. " NVCAL ,Non-Valid Calendar Alarm" "Not detected,Detected"
|
|
bitfld.long 0x04 2. " NVTAL ,Non-Valid Time Alarm" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 1. " NVC ,Non-Valid Calendar" "Not detected,Detected"
|
|
bitfld.long 0x04 0. " NVT ,Non-Valid Time" "Not detected,Detected"
|
|
sif (cpuis("AT91SAM3N*")||cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "RTC_WPMR,RTC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect access key"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "WDT (Watchdog Timer)"
|
|
base ad:0x400E1A50
|
|
width 4.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password"
|
|
bitfld.long 0x00 0. " WDRSTT ,Watchdog restart" "No effect,Restart"
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D4*")||cpuis("ATSAMA5D2*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 29. " WDIDLEHLT ,Watchdog idle halt" "Not halted,Halted"
|
|
bitfld.long 0x00 28. " WDDBGHLT ,Watchdog debug halt" "Not halted,Halted"
|
|
hexmask.long.word 0x00 16.--27. 1. " WDD ,Watchdog delta value"
|
|
bitfld.long 0x00 15. " WDDIS ,Watchdog disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13. " WDRSTEN ,Watchdog reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WDFIEN ,Watchdog fault interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--11. 1. " WDV ,Watchdog counter value"
|
|
else
|
|
if ((per.l(ad:0x400E1A50+0x04)&0x2000)==0x2000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 29. " WDIDLEHLT ,Watchdog idle halt" "Running,Stopped"
|
|
bitfld.long 0x00 28. " WDDBGHLT ,Watchdog debug halt" "Running,Stopped"
|
|
hexmask.long.word 0x00 16.--27. 1. " WDD ,Watchdog delta value"
|
|
bitfld.long 0x00 15. " WDDIS ,Watchdog disable" "No,Yes"
|
|
bitfld.long 0x00 14. " WDRPROC ,Watchdog reset processor" "All resets,Processor reset"
|
|
newline
|
|
bitfld.long 0x00 13. " WDRSTEN ,Watchdog reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WDFIEN ,Watchdog fault interrupt enable" "No effect,Interrupt"
|
|
hexmask.long.word 0x00 0.--11. 1. " WDV ,Watchdog counter value"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 29. " WDIDLEHLT ,Watchdog idle halt" "Running,Stopped"
|
|
bitfld.long 0x00 28. " WDDBGHLT ,Watchdog debug halt" "Running,Stopped"
|
|
hexmask.long.word 0x00 16.--27. 1. " WDD ,Watchdog delta value"
|
|
bitfld.long 0x00 15. " WDDIS ,Watchdog disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13. " WDRSTEN ,Watchdog reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WDFIEN ,Watchdog fault interrupt enable" "No effect,Interrupt"
|
|
hexmask.long.word 0x00 0.--11. 1. " WDV ,Watchdog counter value"
|
|
endif
|
|
endif
|
|
newline
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "SR,Status Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
tree "SUPC (Supply Controller)"
|
|
base ad:0x400E1A10
|
|
width 12.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SUPC_CR,Supply Controller Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password Key"
|
|
bitfld.long 0x00 3. " XTALSEL , Crystal Oscillator Select " "No effect,Oscillator output"
|
|
textline " "
|
|
bitfld.long 0x00 2. " VROFF , Voltage Regulator Off" "No effect,Off"
|
|
group.long 0x04++0x0f
|
|
line.long 0x00 "SUPC_SMMR,Supply Controller Supply Monitor Mode Register"
|
|
bitfld.long 0x00 13. " SMIEN , Supply Monitor Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SMRSTEN , Supply Monitor Reset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " SMSMPL , Supply Monitor Sampling Period" "Disabled,Continuous,Every 32 SLCK,Every 256 SLCK,Every 2048 SLCK,?..."
|
|
textline " "
|
|
sif cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 0.--3. " SMTH ,Supply Monitor Threshold" "1.6 V,1.72 V,1.84 V,1.96 V,2.08 V,2.2 V,2.32 V,2.44 V,2.56 V,2.68 V,2.8 V,2.92 V,3.04 V,3.16 V,3.28 V,3.4 V"
|
|
else
|
|
bitfld.long 0x00 0.--3. " SMTH ,Supply Monitor Threshold" "1.9 V,2.0 V,2.1 V,2.2 V,2.3 V,2.4 V,2.5 V,2.6 V,2.7 V,2.8 V,2.9 V,3.0 V,3.1 V,3.2 V,3.3 V,3.4 V"
|
|
endif
|
|
line.long 0x04 "SUPC_MR,Supply Controller Mode Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " KEY ,Password Key"
|
|
bitfld.long 0x04 20. " OSCBYPASS , Oscillator Bypass" "No effect,Bypass"
|
|
textline " "
|
|
sif (cpuis("AT91SAM3N*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x04 14. " ONREG ,Voltage Regulator Enabled" "Not used,Used"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 14. " VDDIORDY ,VDDIO Ready" "Removed,Present"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 13. " BODDIS , Brownout Detector Disable" "No,Yes"
|
|
bitfld.long 0x04 12. " BODRSTEN , Brownout Detector Reset Enable" "Disabled,Enabled"
|
|
line.long 0x08 "SUPC_WUMR,Supply Controller Wake Up Mode Register"
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x08 16.--18. " LPDBC ,Low Power DeBounCer Period" "Disabled,2_RTCOUT0,3_RTCOUT0,4_RTCOUT0,5_RTCOUT0,6_RTCOUT0,7_RTCOUT0,8_RTCOUT0"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 12.--14. " WKUPDBC , Wake Up Inputs Debouncer" "1 SLCK,3 SLCK,32 SLCK,512 SLCK,4096 SLCK,32768 SLCK,?..."
|
|
textline " "
|
|
sif (cpuis("AT91SAM3U*")||cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x08 8.--10. " FWUPDBC , Force Wake Up Debouncer" "1 SLCK,3 SLCK,32 SLCK,512 SLCK,4096 SLCK,32768 SLCK,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x08 7. " LPDBCCLR ,Low power Debouncer Clear" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " LPDBCEN1 ,Low power Debouncer ENable WKUP1" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " LPDBCEN0 ,Low power Debouncer ENable WKUP0" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 3. " RTCEN , Real Time Clock Wake Up Enable " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " RTTEN , Real Time Timer Wake Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " SMEN , Supply Monitor Wake Up Enable" "Disabled,Enabled"
|
|
sif (cpuis("AT91SAM3U*")||cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x08 0. " FWUPEN , Force Wake Up Enable" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x0c "SUPC_WUIR,System Controller Wake Up Inputs Register"
|
|
sif (cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x0c 31. " WKUPT15 , Wake Up Input Transition" "Low,High"
|
|
bitfld.long 0x0c 30. " WKUPT14 , Wake Up Input Transition" "Low,High"
|
|
bitfld.long 0x0c 29. " WKUPT13 , Wake Up Input Transition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0c 28. " WKUPT12 , Wake Up Input Transition" "Low,High"
|
|
bitfld.long 0x0c 27. " WKUPT11 , Wake Up Input Transition" "Low,High"
|
|
bitfld.long 0x0c 26. " WKUPT10 , Wake Up Input Transition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " WKUPT9 , Wake Up Input Transition" "Low,High"
|
|
bitfld.long 0x0c 24. " WKUPT8 , Wake Up Input Transition" "Low,High"
|
|
bitfld.long 0x0c 23. " WKUPT7 , Wake Up Input Transition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0c 22. " WKUPT6 , Wake Up Input Transition" "Low,High"
|
|
bitfld.long 0x0c 21. " WKUPT5 , Wake Up Input Transition" "Low,High"
|
|
bitfld.long 0x0c 20. " WKUPT4 , Wake Up Input Transition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " WKUPT3 , Wake Up Input Transition" "Low,High"
|
|
bitfld.long 0x0c 18. " WKUPT2 , Wake Up Input Transition" "Low,High"
|
|
bitfld.long 0x0c 17. " WKUPT1 , Wake Up Input Transition" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0c 16. " WKUPT0 , Wake Up Input Transition" "Low,High"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0c 31. " WKUPT15 , Wake Up Input Transition" "High to low,Low to high"
|
|
bitfld.long 0x0c 30. " WKUPT14 , Wake Up Input Transition" "High to low,Low to high"
|
|
bitfld.long 0x0c 29. " WKUPT13 , Wake Up Input Transition" "High to low,Low to high"
|
|
textline " "
|
|
bitfld.long 0x0c 28. " WKUPT12 , Wake Up Input Transition" "High to low,Low to high"
|
|
bitfld.long 0x0c 27. " WKUPT11 , Wake Up Input Transition" "High to low,Low to high"
|
|
bitfld.long 0x0c 26. " WKUPT10 , Wake Up Input Transition" "High to low,Low to high"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " WKUPT9 , Wake Up Input Transition" "High to low,Low to high"
|
|
bitfld.long 0x0c 24. " WKUPT8 , Wake Up Input Transition" "High to low,Low to high"
|
|
bitfld.long 0x0c 23. " WKUPT7 , Wake Up Input Transition" "High to low,Low to high"
|
|
textline " "
|
|
bitfld.long 0x0c 22. " WKUPT6 , Wake Up Input Transition" "High to low,Low to high"
|
|
bitfld.long 0x0c 21. " WKUPT5 , Wake Up Input Transition" "High to low,Low to high"
|
|
bitfld.long 0x0c 20. " WKUPT4 , Wake Up Input Transition" "High to low,Low to high"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " WKUPT3 , Wake Up Input Transition" "High to low,Low to high"
|
|
bitfld.long 0x0c 18. " WKUPT2 , Wake Up Input Transition" "High to low,Low to high"
|
|
bitfld.long 0x0c 17. " WKUPT1 , Wake Up Input Transition" "High to low,Low to high"
|
|
textline " "
|
|
bitfld.long 0x0c 16. " WKUPT0 , Wake Up Input Transition" "High to low,Low to high"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0c 15. " WKUPEN15 , Wake Up Input Transition" "Disabled,Enabled"
|
|
bitfld.long 0x0c 14. " WKUPEN14 , Wake Up Input Transition" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " WKUPEN13 , Wake Up Input Transition" "Disabled,Enabled"
|
|
bitfld.long 0x0c 12. " WKUPEN12 , Wake Up Input Transition" "Disabled,Enabled"
|
|
bitfld.long 0x0c 11. " WKUPEN11 , Wake Up Input Transition" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 10. " WKUPEN10 , Wake Up Input Transition" "Disabled,Enabled"
|
|
bitfld.long 0x0c 9. " WKUPEN9 , Wake Up Input Transition" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8. " WKUPEN8 , Wake Up Input Transition" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " WKUPEN7 , Wake Up Input Transition" "Disabled,Enabled"
|
|
bitfld.long 0x0c 6. " WKUPEN6 , Wake Up Input Transition" "Disabled,Enabled"
|
|
bitfld.long 0x0c 5. " WKUPEN5 , Wake Up Input Transition" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 4. " WKUPEN4 , Wake Up Input Transition" "Disabled,Enabled"
|
|
bitfld.long 0x0c 3. " WKUPEN3 , Wake Up Input Transition" "Disabled,Enabled"
|
|
bitfld.long 0x0c 2. " WKUPEN2 , Wake Up Input Transition" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " WKUPEN1 , Wake Up Input Transition" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0. " WKUPEN0 , Wake Up Input Transition" "Disabled,Enabled"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "SUPC_SR,Supply Controller Status Register"
|
|
in
|
|
width 0xb
|
|
tree.end
|
|
tree "GPBR (General Purpose Backup Registers)"
|
|
base ad:0x400E1A90
|
|
width 8.
|
|
sif (cpuis("AT91SAM3S8*")||cpuis("AT91SAM3N*")||cpuis("ATSAM4N*")||cpuis("ATSAM4S*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMG5*"))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "GPBR0,General Purpose Backup Register 0"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "GPBR1,General Purpose Backup Register 1"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "GPBR2,General Purpose Backup Register 2"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "GPBR3,General Purpose Backup Register 3"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "GPBR4,General Purpose Backup Register 4"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPBR5,General Purpose Backup Register 5"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "GPBR6,General Purpose Backup Register 6"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPBR7,General Purpose Backup Register 7"
|
|
elif (cpuis("ATSAM4E*"))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "GPBR0,General Purpose Backup Register 0"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "GPBR1,General Purpose Backup Register 1"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "GPBR2,General Purpose Backup Register 2"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "GPBR3,General Purpose Backup Register 3"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "GPBR4,General Purpose Backup Register 4"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPBR5,General Purpose Backup Register 5"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "GPBR6,General Purpose Backup Register 6"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPBR7,General Purpose Backup Register 7"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "GPBR8,General Purpose Backup Register 8"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "GPBR9,General Purpose Backup Register 9"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "GPBR10,General Purpose Backup Register 10"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "GPBR11,General Purpose Backup Register 11"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "GPBR12,General Purpose Backup Register 12"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "GPBR13,General Purpose Backup Register 13"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "GPBR14,General Purpose Backup Register 14"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "GPBR15,General Purpose Backup Register 15"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "GPBR16,General Purpose Backup Register 16"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "GPBR17,General Purpose Backup Register 17"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "GPBR18,General Purpose Backup Register 18"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "GPBR19,General Purpose Backup Register 19"
|
|
else
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "GPBR0,General Purpose Backup Register 0"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "GPBR1,General Purpose Backup Register 1"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "GPBR2,General Purpose Backup Register 2"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "GPBR3,General Purpose Backup Register 3"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "EEFC (Enhanced Embedded Flash Controller)"
|
|
tree "EFC 0"
|
|
base ad:0x400E0A00
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "EEFC_FMR,EEFC Flash Mode Register"
|
|
sif (cpuis("ATSAM4S*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 26. " CLOE ,Code Loops Optimization Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24. " FAM , Flash Access Mode" "128-bit,64-bit"
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4S*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
textline " "
|
|
bitfld.long 0x00 16. " SCOD ,Sequential Code Optimization Disable" "No,Yes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " FWS ,Flash Wait State" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FRDY ,Flash Ready Interrupt Enable" "Disabled,Enabled"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "EEFC_FCR,EEFC Flash Command Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " FKEY , Flash Writing Protection Key"
|
|
textline " "
|
|
hexmask.long.word 0x00 8.--23. 1. " FARG ,Flash Command Argument"
|
|
textline " "
|
|
sif (cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0.--4. " FCMD ,Flash Command" "GETD,WP,WPL,EWP,EWPL,EA,,EPA,SLB,CLB,GLB,SGPB,CGPB,GGPB,STUI,SPUI,GCALB,ES,WUS,EUS,STUS,SPUS,?..."
|
|
else
|
|
hexmask.long.byte 0x00 0.--7. 1. " FCMD ,Flash Command"
|
|
endif
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "EEFC_FSR,EEFC Flash Status Register"
|
|
in
|
|
rgroup.long 0x0c++0x03
|
|
line.long 0x00 "EEFC_FRR,EEFC Flash Result Register"
|
|
hexmask.long 0x00 0.--31. 1. " FVALUE , Flash Result Value"
|
|
width 0xb
|
|
tree.end
|
|
tree "EFC 1"
|
|
base ad:0x400E0C00
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "EEFC_FMR,EEFC Flash Mode Register"
|
|
sif (cpuis("ATSAM4S*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 26. " CLOE ,Code Loops Optimization Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24. " FAM , Flash Access Mode" "128-bit,64-bit"
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4S*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
textline " "
|
|
bitfld.long 0x00 16. " SCOD ,Sequential Code Optimization Disable" "No,Yes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " FWS ,Flash Wait State" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FRDY ,Flash Ready Interrupt Enable" "Disabled,Enabled"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "EEFC_FCR,EEFC Flash Command Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " FKEY , Flash Writing Protection Key"
|
|
textline " "
|
|
hexmask.long.word 0x00 8.--23. 1. " FARG ,Flash Command Argument"
|
|
textline " "
|
|
sif (cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0.--4. " FCMD ,Flash Command" "GETD,WP,WPL,EWP,EWPL,EA,,EPA,SLB,CLB,GLB,SGPB,CGPB,GGPB,STUI,SPUI,GCALB,ES,WUS,EUS,STUS,SPUS,?..."
|
|
else
|
|
hexmask.long.byte 0x00 0.--7. 1. " FCMD ,Flash Command"
|
|
endif
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "EEFC_FSR,EEFC Flash Status Register"
|
|
in
|
|
rgroup.long 0x0c++0x03
|
|
line.long 0x00 "EEFC_FRR,EEFC Flash Result Register"
|
|
hexmask.long 0x00 0.--31. 1. " FVALUE , Flash Result Value"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "MATRIX (Bus Matrix)"
|
|
base ad:0x400E0400
|
|
width 14.
|
|
group.long 0x00++0x23
|
|
line.long 0x0 "MATRIX_MCFG0,Bus Matrix Master Configuration Register 0"
|
|
bitfld.long 0x0 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,?..."
|
|
line.long 0x4 "MATRIX_MCFG1,Bus Matrix Master Configuration Register 1"
|
|
bitfld.long 0x4 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,?..."
|
|
line.long 0x8 "MATRIX_MCFG2,Bus Matrix Master Configuration Register 2"
|
|
bitfld.long 0x8 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,?..."
|
|
line.long 0xC "MATRIX_MCFG3,Bus Matrix Master Configuration Register 3"
|
|
bitfld.long 0xC 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,?..."
|
|
line.long 0x10 "MATRIX_MCFG4,Bus Matrix Master Configuration Register 4"
|
|
bitfld.long 0x10 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,?..."
|
|
line.long 0x14 "MATRIX_MCFG5,Bus Matrix Master Configuration Register 5"
|
|
bitfld.long 0x14 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite,Single,4-beat,8-beat,16-beat,?..."
|
|
if ((d.l(ad:0x400E0400+0x40)&0x30000)==0x20000)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "MATRIX_SCFG0,Bus Matrix Slave Configuration Register 0"
|
|
bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
sif (cpuis("ATSAM4S*")||cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "MATRIX_SCFG0,Bus Matrix Slave Configuration Register 0"
|
|
bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
endif
|
|
if ((d.l(ad:0x400E0400+0x44)&0x30000)==0x20000)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "MATRIX_SCFG1,Bus Matrix Slave Configuration Register 1"
|
|
bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
sif (cpuis("ATSAM4S*")||cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
else
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "MATRIX_SCFG1,Bus Matrix Slave Configuration Register 1"
|
|
bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
endif
|
|
if ((d.l(ad:0x400E0400+0x48)&0x30000)==0x20000)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "MATRIX_SCFG2,Bus Matrix Slave Configuration Register 2"
|
|
bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
sif (cpuis("ATSAM4S*")||cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
else
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "MATRIX_SCFG2,Bus Matrix Slave Configuration Register 2"
|
|
bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
endif
|
|
if ((d.l(ad:0x400E0400+0x4C)&0x30000)==0x20000)
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "MATRIX_SCFG3,Bus Matrix Slave Configuration Register 3"
|
|
bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
sif (cpuis("ATSAM4S*")||cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
else
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "MATRIX_SCFG3,Bus Matrix Slave Configuration Register 3"
|
|
bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
endif
|
|
if ((d.l(ad:0x400E0400+0x50)&0x30000)==0x20000)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "MATRIX_SCFG4,Bus Matrix Slave Configuration Register 4"
|
|
bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
sif (cpuis("ATSAM4S*")||cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
else
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "MATRIX_SCFG4,Bus Matrix Slave Configuration Register 4"
|
|
bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
endif
|
|
if ((d.l(ad:0x400E0400+0x54)&0x30000)==0x20000)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "MATRIX_SCFG5,Bus Matrix Slave Configuration Register 5"
|
|
bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
sif (cpuis("ATSAM4S*")||cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "MATRIX_SCFG5,Bus Matrix Slave Configuration Register 5"
|
|
bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
endif
|
|
if ((d.l(ad:0x400E0400+0x58)&0x30000)==0x20000)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MATRIX_SCFG6,Bus Matrix Slave Configuration Register 6"
|
|
bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
sif (cpuis("ATSAM4S*")||cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MATRIX_SCFG6,Bus Matrix Slave Configuration Register 6"
|
|
bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
endif
|
|
if ((d.l(ad:0x400E0400+0x5C)&0x30000)==0x20000)
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "MATRIX_SCFG7,Bus Matrix Slave Configuration Register 7"
|
|
bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
sif (cpuis("ATSAM4S*")||cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
else
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "MATRIX_SCFG7,Bus Matrix Slave Configuration Register 7"
|
|
bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
endif
|
|
if ((d.l(ad:0x400E0400+0x60)&0x30000)==0x20000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "MATRIX_SCFG8,Bus Matrix Slave Configuration Register 8"
|
|
bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
sif (cpuis("ATSAM4S*")||cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 18.--20. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default Master Fixed Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "MATRIX_SCFG8,Bus Matrix Slave Configuration Register 8"
|
|
bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " DEFMASTR_TYPE ,Default Master Type" "No master,Last,Fixed,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Burst Allowed Cycles Maximum Number"
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "MATRIX_PRAS0,Bus Matrix Priority Register A for Slave 0 Register"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Lowest,1,2,Highest"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "MATRIX_PRAS1,Bus Matrix Priority Register A for Slave 1 Register"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Lowest,1,2,Highest"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "MATRIX_PRAS2,Bus Matrix Priority Register A for Slave 2 Register"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Lowest,1,2,Highest"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "MATRIX_PRAS3,Bus Matrix Priority Register A for Slave 3 Register"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Lowest,1,2,Highest"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "MATRIX_PRAS4,Bus Matrix Priority Register A for Slave 4 Register"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Lowest,1,2,Highest"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "MATRIX_PRAS5,Bus Matrix Priority Register A for Slave 5 Register"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Lowest,1,2,Highest"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "MATRIX_PRAS6,Bus Matrix Priority Register A for Slave 6 Register"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Lowest,1,2,Highest"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "MATRIX_PRAS7,Bus Matrix Priority Register A for Slave 7 Register"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Lowest,1,2,Highest"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "MATRIX_PRAS8,Bus Matrix Priority Register A for Slave 8 Register"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "Lowest,1,2,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "Lowest,1,2,Highest"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "MATRIX_MRCR,Master Remap Control Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 6. " RCB6 ,Remap Command Bit for AHB Master 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RCB5 ,Remap Command Bit for AHB Master 5" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " RCB4 ,Remap Command Bit for AHB Master 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RCB3 ,Remap Command Bit for AHB Master 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCB2 ,Remap Command Bit for AHB Master 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCB1 ,Remap Command Bit for AHB Master 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCB0 ,Remap Command Bit for AHB Master 0" "Disabled,Enabled"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "CCFG_SYSIO,System I/O Configuration Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 12. " SYSIO12 ,PC0 or ERASE Assignment" "PC0,ERASE"
|
|
else
|
|
bitfld.long 0x00 12. " SYSIO12 ,PB12 or ERASE Assignment" "ERASE,PB12"
|
|
endif
|
|
sif (!cpuis("AT91SAM3A4C")&&!cpuis("AT91SAM3A8C")&&!cpuis("AT91SAM3X4C")&&!cpuis("AT91SAM3X4E")&&!cpuis("AT91SAM3X8C")&&!cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 11. " SYSIO11 ,PB11 or DDP Assignment" "DDP,PB11"
|
|
bitfld.long 0x00 10. " SYSIO10 ,PB10 or DDM Assignment" "DDM,PB10"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SYSIO7 ,PB7 or TCK/SWCLK Assignment" "TCK/SWCLK,PB7"
|
|
bitfld.long 0x00 6. " SYSIO6 ,PB6 or TMS/SWDIO Assignment" "TMS/SWDIO,PB6"
|
|
bitfld.long 0x00 5. " SYSIO5 ,PB5 or TDO/TRACESWO Assignment" "TDO/TRACESWO,PB5"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SYSIO4 ,PB4 or TDI Assignment" "TDI,PB4"
|
|
group.long 0x11C++0x3
|
|
line.long 0x00 "CCFG_SMCNFCS,SMC NAND Flash Chip select Configuration Register"
|
|
bitfld.long 0x00 3. " SMC_NFCS3 ,SMC NAND Flash Chip Select 3 Assignment" "Not assigned,Assigned"
|
|
bitfld.long 0x00 2. " SMC_NFCS2 ,SMC NAND Flash Chip Select 2 Assignment" "Not assigned,Assigned"
|
|
bitfld.long 0x00 1. " SMC_NFCS1 ,SMC NAND Flash Chip Select 1 Assignment" "Not assigned,Assigned"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SMC_NFCS0 ,SMC NAND Flash Chip Select 0 Assignment" "Not assigned,Assigned"
|
|
endif
|
|
endif
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "MATRIX_WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
rgroup.long 0x1E8++0x03
|
|
line.long 0x00 "MATRIX_WPSR,Write Protect Status Register"
|
|
hexmask.long.word 0x00 8.--23. 1. " WPVSRC ,Write Protect Violation Source"
|
|
bitfld.long 0x00 0. " WPVS ,Write Protect" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMAC (Direct Memory Access Controller)"
|
|
base ad:0x400C4000
|
|
width 13.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "DMAC_GCFG,DMAC Global Configuration Register"
|
|
bitfld.long 0x00 4. " ARB_CFG ,Arbiter configuration" "Fixed,Round robin"
|
|
line.long 0x04 "DMAC_EN,DMAC Enable Register"
|
|
bitfld.long 0x04 0. " ENABLE ,DMA Controller Enable" "Disabled,Enabled"
|
|
line.long 0x08 "DMAC_SREQ,Software Single Request Register"
|
|
sif (cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x08 11. " DSREQ5 ,Request a destination single transfer on channel 5" "Not requested,Requested"
|
|
bitfld.long 0x08 10. " SSREQ5 ,Request a source single transfer on channel 5" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 9. " DSREQ4 ,Request a destination single transfer on channel 4" "Not requested,Requested"
|
|
bitfld.long 0x08 8. " SSREQ4 ,Request a source single transfer on channel 4" "Not requested,Requested"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 7. " DSREQ3 ,Request a destination single transfer on channel 3" "Not requested,Requested"
|
|
bitfld.long 0x08 6. " SSREQ3 ,Request a source single transfer on channel 3" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 5. " DSREQ2 ,Request a destination single transfer on channel 2" "Not requested,Requested"
|
|
bitfld.long 0x08 4. " SSREQ2 ,Request a source single transfer on channel 2" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DSREQ1 ,Request a destination single transfer on channel 1" "Not requested,Requested"
|
|
bitfld.long 0x08 2. " SSREQ1 ,Request a source single transfer on channel 1" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 1. " DSREQ0 ,Request a destination single transfer on channel 0" "Not requested,Requested"
|
|
bitfld.long 0x08 0. " SSREQ0 ,Request a source single transfer on channel 0" "Not requested,Requested"
|
|
line.long 0x0C "DMAC_CREQ,Software Chunk Transfer Request Register"
|
|
sif (cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x0C 11. " DCREQ5 ,Request a destination chunk transfer on channel 5" "Not requested,Requested"
|
|
bitfld.long 0x0C 10. " SCREQ5 ,Request a source chunk transfer on channel 5" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " DCREQ4 ,Request a destination chunk transfer on channel 4" "Not requested,Requested"
|
|
bitfld.long 0x0C 8. " SCREQ4 ,Request a source chunk transfer on channel 4" "Not requested,Requested"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 7. " DCREQ3 ,Request a destination chunk transfer on channel 3" "Not requested,Requested"
|
|
bitfld.long 0x0C 6. " SCREQ3 ,Request a source chunk transfer on channel 3" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " DCREQ2 ,Request a destination chunk transfer on channel 2" "Not requested,Requested"
|
|
bitfld.long 0x0C 4. " SCREQ2 ,Request a source chunk transfer on channel 2" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " DCREQ1 ,Request a destination chunk transfer on channel 1" "Not requested,Requested"
|
|
bitfld.long 0x0C 2. " SCREQ1 ,Request a source chunk transfer on channel 1" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " DCREQ0 ,Request a destination chunk transfer on channel 0" "Not requested,Requested"
|
|
bitfld.long 0x0C 0. " SCREQ0 ,Request a source chunk transfer on channel 0" "Not requested,Requested"
|
|
line.long 0x10 "DMAC_LAST,Software Last Transfer Flag Register"
|
|
sif (cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x10 11. " DLAST5 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 10. " SLAST5 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
textline " "
|
|
bitfld.long 0x10 9. " DLAST4 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 8. " SLAST4 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 7. " DLAST3 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 6. " SLAST3 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
textline " "
|
|
bitfld.long 0x10 5. " DLAST2 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 4. " SLAST2 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
textline " "
|
|
bitfld.long 0x10 3. " DLAST1 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 2. " SLAST1 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
textline " "
|
|
bitfld.long 0x10 1. " DLAST0 ,Destination request is the last transfer of the buffer" "Not last,Last"
|
|
bitfld.long 0x10 0. " SLAST0 ,Source request is the last transfer of the buffer" "Not last,Last"
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "DMAC_EBCIMR, DMAC Error Buffer Transfer and Chained Buffer Transfer Mask Register"
|
|
sif (cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " ERR5_set/clr ,Access Error Interrupt Enable Register" "Masked,Not masked"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " ERR4_set/clr ,Access Error Interrupt Enable Register" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " ERR3_set/clr ,Access Error Interrupt Enable Register" "Masked,Not masked"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " ERR2_set/clr ,Access Error Interrupt Enable Register" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " ERR1_set/clr ,Access Error Interrupt Enable Register" "Masked,Not masked"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " ERR0_set/clr ,Access Error Interrupt Enable Register" "Masked,Not masked"
|
|
textline " "
|
|
sif (cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " CBTC5_set/clr ,Chained Buffer Transfer Completed " "Masked,Not masked"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " CBTC4_set/clr ,Chained Buffer Transfer Completed " "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " CBTC3_set/clr , Chained Buffer Transfer Completed " "Masked,Not masked"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " CBTC2_set/clr , Chained Buffer Transfer Completed " "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " CBTC1_set/clr , Chained Buffer Transfer Completed " "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " CBTC0_set/clr , Chained Buffer Transfer Completed " "Masked,Not masked"
|
|
textline " "
|
|
sif (cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " BTC5_set/clr ,Buffer Transfer Completed" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " BTC4_set/clr ,Buffer Transfer Completed" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " BTC3_set/clr ,Buffer Transfer Completed" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " BTC2_set/clr ,Buffer Transfer Completed" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " BTC1_set/clr ,Buffer Transfer Completed" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BTC0_set/clr ,Buffer Transfer Completed" "Masked,Not masked"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x00 "DMAC_EBCISR, DMAC Error Buffer Transfer and Chained Buffer Transfer Status Register"
|
|
sif (cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 21. " ERR5 , Access Error Interrupt Enable Register" "No error,Error"
|
|
bitfld.long 0x00 20. " ERR4 , Access Error Interrupt Enable Register" "No error,Error"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " ERR3 , Access Error Interrupt Enable Register" "No error,Error"
|
|
bitfld.long 0x00 18. " ERR2 , Access Error Interrupt Enable Register" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ERR1 , Access Error Interrupt Enable Register" "No error,Error"
|
|
bitfld.long 0x00 16. " ERR0 , Access Error Interrupt Enable Register" "No error,Error"
|
|
textline " "
|
|
sif (cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 13. " CBTC5 ,Channel 5 Chained buffer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 12. " CBTC4 , Channel 4 Chained buffer has terminated" "Not terminated,Terminated"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 11. " CBTC3 ,Channel 3 Chained buffer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 10. " CBTC2 ,Channel 2 Chained buffer has terminated" "Not terminated,Terminated"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CBTC1 ,Channel 1 Chained buffer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 8. " CBTC0 ,Channel 0 Chained buffer has terminated" "Not terminated,Terminated"
|
|
textline " "
|
|
sif (cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 5. " BTC5 , Channel 5 buffer transfer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 4. " BTC4 , Channel 4 buffer transfer has terminated" "Not terminated,Terminated"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " BTC3 ,Channel 3 buffer transfer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 2. " BTC2 ,Channel 2 buffer transfer has terminated" "Not terminated,Terminated"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BTC1 ,Channel 1 buffer transfer has terminated" "Not terminated,Terminated"
|
|
bitfld.long 0x00 0. " BTC0 ,Channel 0 buffer transfer has terminated" "Not terminated,Terminated"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x00 "DMAC_CHER, DMAC Channel Handler Enable Register"
|
|
sif (cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 29. " KEEP5 ,Resume the current channel from an automatic stall state" "Not resumed,Resumed"
|
|
bitfld.long 0x00 28. " KEEP4 ,Resume the current channel from an automatic stall state" "Not resumed,Resumed"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 27. " KEEP3 ,Resume the current channel from an automatic stall state" "Not resumed,Resumed"
|
|
bitfld.long 0x00 26. " KEEP2 ,Resume the current channel from an automatic stall state" "Not resumed,Resumed"
|
|
textline " "
|
|
bitfld.long 0x00 25. " KEEP1 ,Resume the current channel from an automatic stall state" "Not resumed,Resumed"
|
|
bitfld.long 0x00 24. " KEEP0 ,Resume the current channel from an automatic stall state" "Not resumed,Resumed"
|
|
sif (cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8E"))
|
|
textline " "
|
|
bitfld.long 0x00 13. " SUSP5 ,Freez the relevant channel and its current context" "Not resumed,Resumed"
|
|
bitfld.long 0x00 12. " SUSP4 ,Freez the relevant channel and its current context" "Not resumed,Resumed"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SUSP3 ,Freez the relevant channel and its current context" "Not resumed,Resumed"
|
|
bitfld.long 0x00 10. " SUSP2 ,Freez the relevant channel and its current context" "Not resumed,Resumed"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SUSP1 ,Freez the relevant channel and its current context" "Not resumed,Resumed"
|
|
bitfld.long 0x00 8. " SUSP0 ,Freez the relevant channel and its current context" "Not resumed,Resumed"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ENA5 ,Enable the relevant channel" "Not resumed,Resumed"
|
|
bitfld.long 0x00 4. " ENA4 ,Enable the relevant channel" "Not resumed,Resumed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENA3 ,Enable the relevant channel" "Not resumed,Resumed"
|
|
bitfld.long 0x00 2. " ENA2 ,Enable the relevant channel" "Not resumed,Resumed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENA1 ,Enable the relevant channel" "Not resumed,Resumed"
|
|
bitfld.long 0x00 0. " ENA0 ,Enable the relevant channel" "Not resumed,Resumed"
|
|
endif
|
|
group.long 0x030++0x3
|
|
line.long 0x00 "DMAC_CHSR, DMAC Channel Handler Status Register"
|
|
sif (cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 29. " STAL5 , Relevant channel enabled" "Not stalled,Stalled"
|
|
bitfld.long 0x00 28. " STAL4 , Relevant channel enabled" "Not stalled,Stalled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 27. " STAL3 , Relevant channel enabled" "Not stalled,Stalled"
|
|
bitfld.long 0x00 26. " STAL2 , Relevant channel enabled" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " STAL1 , Relevant channel enabled" "Not stalled,Stalled"
|
|
bitfld.long 0x00 24. " STAL0 ,Relevant channel enabled" "Not stalled,Stalled"
|
|
textline " "
|
|
sif (cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 21. " EMPT5 ,Relevant channel is empty" "Not Empty,Empty"
|
|
bitfld.long 0x00 20. " EMPT4 ,Relevant channel is empty" "Not Empty,Empty"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " EMPT3 ,Relevant channel is empty" "Not Empty,Empty"
|
|
bitfld.long 0x00 18. " EMPT2 ,Relevant channel is empty" "Not Empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EMPT1 ,Relevant channel is empty" "Not Empty,Empty"
|
|
bitfld.long 0x00 16. " EMPT0 ,Relevant channel is empty" "Not Empty,Empty"
|
|
textline " "
|
|
sif (cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " SUSP5_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " SUSP4_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " SUSP3_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " SUSP2_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " SUSP1_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " SUSP0_set/clr , Channel transfer is suspended" "Resume,Suspended"
|
|
textline " "
|
|
sif (cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " ENA5_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENA4_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " ENA3_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " ENA2_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " ENA1_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " ENA0_set/clr , Relevant channel enabled" "Disabled,Enabled"
|
|
sif (cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8E"))
|
|
tree "Channel 0"
|
|
group.long 0x3C++0x17
|
|
line.long 0x00 "DMAC_SADDR0,DMAC Channel 0 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR0, DMAC Channel 0 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR0,DMAC Channel 0 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " DSCR0 , Buffer Transfer descriptor address"
|
|
line.long 0x0c "DMAC_CTRLA0,DMAC Channel 0 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "In progress,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB0,DMAC Channel 0 Control B Register"
|
|
bitfld.long 0x10 30. " IEN , BTC[0] flag enable" "Enabled,Disabled"
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,,Fixed,?..."
|
|
textline " "
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,,Fixed,?..."
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
line.long 0x14 "DMAC_CFG0,DMAC Channel 0 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
textline " "
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 0 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 0 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 0 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Channel 1"
|
|
group.long 0x64++0x17
|
|
line.long 0x00 "DMAC_SADDR1,DMAC Channel 1 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR1, DMAC Channel 1 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR1,DMAC Channel 1 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " DSCR1 , Buffer Transfer descriptor address"
|
|
line.long 0x0c "DMAC_CTRLA1,DMAC Channel 1 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "In progress,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB1,DMAC Channel 1 Control B Register"
|
|
bitfld.long 0x10 30. " IEN , BTC[1] flag enable" "Enabled,Disabled"
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,,Fixed,?..."
|
|
textline " "
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,,Fixed,?..."
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
line.long 0x14 "DMAC_CFG1,DMAC Channel 1 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
textline " "
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 1 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 1 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 1 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Channel 2"
|
|
group.long 0x8C++0x17
|
|
line.long 0x00 "DMAC_SADDR2,DMAC Channel 2 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR2, DMAC Channel 2 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR2,DMAC Channel 2 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " DSCR2 , Buffer Transfer descriptor address"
|
|
line.long 0x0c "DMAC_CTRLA2,DMAC Channel 2 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "In progress,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB2,DMAC Channel 2 Control B Register"
|
|
bitfld.long 0x10 30. " IEN , BTC[2] flag enable" "Enabled,Disabled"
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,,Fixed,?..."
|
|
textline " "
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,,Fixed,?..."
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
line.long 0x14 "DMAC_CFG2,DMAC Channel 2 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
textline " "
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 2 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 2 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 2 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Channel 3"
|
|
group.long 0xB4++0x17
|
|
line.long 0x00 "DMAC_SADDR3,DMAC Channel 3 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR3, DMAC Channel 3 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR3,DMAC Channel 3 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " DSCR3 , Buffer Transfer descriptor address"
|
|
line.long 0x0c "DMAC_CTRLA3,DMAC Channel 3 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "In progress,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB3,DMAC Channel 3 Control B Register"
|
|
bitfld.long 0x10 30. " IEN , BTC[3] flag enable" "Enabled,Disabled"
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,,Fixed,?..."
|
|
textline " "
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,,Fixed,?..."
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
line.long 0x14 "DMAC_CFG3,DMAC Channel 3 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
textline " "
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 3 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 3 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 3 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Channel 4"
|
|
group.long 0xDC++0x17
|
|
line.long 0x00 "DMAC_SADDR4,DMAC Channel 4 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR4, DMAC Channel 4 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR4,DMAC Channel 4 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " DSCR4 , Buffer Transfer descriptor address"
|
|
line.long 0x0c "DMAC_CTRLA4,DMAC Channel 4 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "In progress,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB4,DMAC Channel 4 Control B Register"
|
|
bitfld.long 0x10 30. " IEN , BTC[4] flag enable" "Enabled,Disabled"
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,,Fixed,?..."
|
|
textline " "
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,,Fixed,?..."
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
line.long 0x14 "DMAC_CFG4,DMAC Channel 4 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
textline " "
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 4 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 4 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 4 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Channel 5"
|
|
group.long 0x104++0x17
|
|
line.long 0x00 "DMAC_SADDR5,DMAC Channel 5 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR5, DMAC Channel 5 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR5,DMAC Channel 5 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " DSCR5 , Buffer Transfer descriptor address"
|
|
line.long 0x0c "DMAC_CTRLA5,DMAC Channel 5 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "In progress,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
line.long 0x10 "DMAC_CTRLB5,DMAC Channel 5 Control B Register"
|
|
bitfld.long 0x10 30. " IEN , BTC[5] flag enable" "Enabled,Disabled"
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,,Fixed,?..."
|
|
textline " "
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,,Fixed,?..."
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
line.long 0x14 "DMAC_CFG5,DMAC Channel 5 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
textline " "
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 5 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 5 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 5 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
else
|
|
tree "Channel 0"
|
|
group.long 0x3C++0x17
|
|
line.long 0x00 "DMAC_SADDR0,DMAC Channel 0 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR0, DMAC Channel 0 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR0,DMAC Channel 0 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " DSCR0 , Buffer Transfer descriptor address"
|
|
line.long 0x0c "DMAC_CTRLA0,DMAC Channel 0 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "In progress,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X8C"))
|
|
textline " "
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
elif (cpuis("ATSAM4E*"))
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x0c 20. " DCSIZE , Destination Chunk Transfer size" "1,4"
|
|
textline " "
|
|
bitfld.long 0x0c 16. " SCSIZE , Source Chunk Transfer Size" "1,4"
|
|
hexmask.long.word 0x0c 0.--11. 1. " BTSIZE ,Buffer Transfer Size"
|
|
endif
|
|
line.long 0x10 "DMAC_CTRLB0,DMAC Channel 0 Control B Register"
|
|
bitfld.long 0x10 30. " IEN , BTC[0] flag enable" "Enabled,Disabled"
|
|
sif (cpuis("ATSAM4E*"))
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
textline " "
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
bitfld.long 0x10 21.--22. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA"
|
|
else
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,,Fixed,?..."
|
|
textline " "
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,,Fixed,?..."
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
line.long 0x14 "DMAC_CFG0,DMAC Channel 0 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
textline " "
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 0 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 0 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 0 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Channel 1"
|
|
group.long 0x64++0x17
|
|
line.long 0x00 "DMAC_SADDR1,DMAC Channel 1 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR1, DMAC Channel 1 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR1,DMAC Channel 1 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " DSCR1 , Buffer Transfer descriptor address"
|
|
line.long 0x0c "DMAC_CTRLA1,DMAC Channel 1 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "In progress,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X8C"))
|
|
textline " "
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
elif (cpuis("ATSAM4E*"))
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x0c 20. " DCSIZE , Destination Chunk Transfer size" "1,4"
|
|
textline " "
|
|
bitfld.long 0x0c 16. " SCSIZE , Source Chunk Transfer Size" "1,4"
|
|
hexmask.long.word 0x0c 0.--11. 1. " BTSIZE ,Buffer Transfer Size"
|
|
endif
|
|
line.long 0x10 "DMAC_CTRLB1,DMAC Channel 1 Control B Register"
|
|
bitfld.long 0x10 30. " IEN , BTC[1] flag enable" "Enabled,Disabled"
|
|
sif (cpuis("ATSAM4E*"))
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
textline " "
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
bitfld.long 0x10 21.--22. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA"
|
|
else
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,,Fixed,?..."
|
|
textline " "
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,,Fixed,?..."
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
line.long 0x14 "DMAC_CFG1,DMAC Channel 1 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
textline " "
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 1 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 1 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 1 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Channel 2"
|
|
group.long 0x8C++0x17
|
|
line.long 0x00 "DMAC_SADDR2,DMAC Channel 2 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR2, DMAC Channel 2 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR2,DMAC Channel 2 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " DSCR2 , Buffer Transfer descriptor address"
|
|
line.long 0x0c "DMAC_CTRLA2,DMAC Channel 2 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "In progress,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X8C"))
|
|
textline " "
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
elif (cpuis("ATSAM4E*"))
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x0c 20. " DCSIZE , Destination Chunk Transfer size" "1,4"
|
|
textline " "
|
|
bitfld.long 0x0c 16. " SCSIZE , Source Chunk Transfer Size" "1,4"
|
|
hexmask.long.word 0x0c 0.--11. 1. " BTSIZE ,Buffer Transfer Size"
|
|
endif
|
|
line.long 0x10 "DMAC_CTRLB2,DMAC Channel 2 Control B Register"
|
|
bitfld.long 0x10 30. " IEN , BTC[2] flag enable" "Enabled,Disabled"
|
|
sif (cpuis("ATSAM4E*"))
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
textline " "
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
bitfld.long 0x10 21.--22. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA"
|
|
else
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,,Fixed,?..."
|
|
textline " "
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,,Fixed,?..."
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
line.long 0x14 "DMAC_CFG2,DMAC Channel 2 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
textline " "
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 2 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 2 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 2 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Channel 3"
|
|
group.long 0xB4++0x17
|
|
line.long 0x00 "DMAC_SADDR3,DMAC Channel 3 Source Address Register"
|
|
line.long 0x04 "DMAC_DADDR3, DMAC Channel 3 Destination Address Register"
|
|
line.long 0x08 "DMAC_DSCR3,DMAC Channel 3 Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " DSCR3 , Buffer Transfer descriptor address"
|
|
line.long 0x0c "DMAC_CTRLA3,DMAC Channel 3 Control A Register"
|
|
bitfld.long 0x0c 31. " DONE , Buffer Transfer descriptor fetched" "In progress,Done"
|
|
bitfld.long 0x0c 28.--29. " DST_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--25. " SRC_WIDTH , Buffer Transfer descriptor fetched" "Byte,Half-word,Word,Word"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X8C"))
|
|
textline " "
|
|
bitfld.long 0x0c 20.--22. " DCSIZE , Destination Chunk Transfer size" "1,4,8,16,32,64,128,256"
|
|
bitfld.long 0x0c 16.--18. " SCSIZE , Source Chunk Transfer Size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
elif (cpuis("ATSAM4E*"))
|
|
hexmask.long.word 0x0c 0.--15. 1. " BTSIZE ,Buffer Transfer Size"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x0c 20. " DCSIZE , Destination Chunk Transfer size" "1,4"
|
|
textline " "
|
|
bitfld.long 0x0c 16. " SCSIZE , Source Chunk Transfer Size" "1,4"
|
|
hexmask.long.word 0x0c 0.--11. 1. " BTSIZE ,Buffer Transfer Size"
|
|
endif
|
|
line.long 0x10 "DMAC_CTRLB3,DMAC Channel 3 Control B Register"
|
|
bitfld.long 0x10 30. " IEN , BTC[3] flag enable" "Enabled,Disabled"
|
|
sif (cpuis("ATSAM4E*"))
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
textline " "
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,Decrementing,Fixed,?..."
|
|
bitfld.long 0x10 21.--22. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA"
|
|
else
|
|
bitfld.long 0x10 28.--29. " DST_INCR , Addressing mode" "Incrementing,,Fixed,?..."
|
|
textline " "
|
|
bitfld.long 0x10 24.--25. " SRC_INCR , Addressing mode" "Incrementing,,Fixed,?..."
|
|
bitfld.long 0x10 21.--23. " FC , Defines which device controls the size of the buffer transfer" "Mem2Mem | DMA,Mem2Per | DMA,Per2Mem | DMA,Per2Per | DMA,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 20. " DST_DSCR , Destination descriptor" "Address updated,Disabled"
|
|
bitfld.long 0x10 16. " SRC_DSCR , Source descriptor" "Address updated,Disabled"
|
|
line.long 0x14 "DMAC_CFG3,DMAC Channel 3 Configuration Register"
|
|
bitfld.long 0x14 28.--29. " FIFOCFG ,FIFO request" "Largest AHB burst,Half FIFO size available,Space for single AHB access,?..."
|
|
textline " "
|
|
bitfld.long 0x14 26. " AHB_PROT2 ,AHB Protection - Data access" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0x14 25. " AHB_PROT1 ,AHB Protection - Data access" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x14 24. " AHB_PROT0 ,AHB Protection - Data access" "User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x14 22. " LOCK_IF_L ,Master Interface Arbiter is locked by the channel 3 for a chunk/buffer transfer" "Chunk,Buffer"
|
|
textline " "
|
|
bitfld.long 0x14 21. " LOCK_B ,AHB Bus Locking capability" "Disabled,Empty"
|
|
textline " "
|
|
bitfld.long 0x14 20. " LOCK_IF ,Interface Lock capability" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16. " SOD ,STOP ON DONE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " DST_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
textline " "
|
|
bitfld.long 0x14 9. " SRC_H2SEL ,Transfer request trigger" "Software handshaking,Hardware handshaking"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " DST_PER ,Channel 3 Destination Request associated with peripheral identifier coded DST_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 0.--3. " SRC_PER ,Channel 3 Source Request associated with peripheral identifier coded SRC_PER handshaking interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4E*"))
|
|
sif (cpuis("ATSAM4E*"))
|
|
group.long 0x1E4++0x3
|
|
else
|
|
group.long 0xE4++0x3
|
|
endif
|
|
line.long 0x00 "DMAC_WPMR,DMAC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
sif (cpuis("ATSAM4E*"))
|
|
hgroup.long 0x1E8++0x3
|
|
else
|
|
hgroup.long 0xE8++0x3
|
|
endif
|
|
hide.long 0x00 "DMAC_WPSR,DMAC Write Protect Status Register"
|
|
in
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "SDRAMC (AHB SDRAM Controller)"
|
|
base ad:0x400E0200
|
|
width 13.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "SDRAMC_MR,SDRAMC Mode Register"
|
|
bitfld.long 0x00 0.--2. " MODE ,SDRAMC Command Mode" "Normal,NOP,ALLBANKS_PRECHARGE,LOAD_MODEREG,AUTO_REFRESH,EXT_LOAD_MODEREG,DEEP_POWERDOWN,?..."
|
|
line.long 0x04 "SDRAMC_TR,SDRAMC Refresh Timer Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " COUNT ,SDRAMC Refresh Timer Count"
|
|
line.long 0x08 "SDRAMC_CR,SDRAMC Configuration Register"
|
|
bitfld.long 0x08 28.--31. " TXSR ,Exit Self Refresh to Active Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 24.--27. " TRAS ,Active to Precharge Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 20.--23. " TRCD ,Row to Column Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 16.--19. " TRP ,Row Precharge Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 12.--15. " TRC_TRFC ,Row Cycle Delay and Row Refresh Cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 8.--11. " TWR ,Write Recovery Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 7. " DBW ,Data Bus Width" "0,1"
|
|
bitfld.long 0x08 5.--6. " CAS ,CAS Latency" ",1 cycle,2 cycle,3 cycle"
|
|
textline " "
|
|
bitfld.long 0x08 4. " NB ,Number of Banks" "2 banks,4 banks"
|
|
bitfld.long 0x08 2.--3. " NR ,Number of Row Bits" "11 row,12 row,13 row,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " NC ,Number of Column Bits" "8 column,9 column,10 column,11 column"
|
|
line.long 0x10 "SDRAMC_LPR,SDRAMC Low Power Register"
|
|
bitfld.long 0x10 12.--13. " TIMEOUT ,Time to define when low-power mode is enable" "Enable immediately,64 clock cycles,?..."
|
|
bitfld.long 0x10 10.--11. " DS ,Drive Strength" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x10 8.--9. " TCSR ,TCSR: Temperature Compensated Self-Refresh" "0,1,2,3"
|
|
bitfld.long 0x10 4.--6. " PASR ,Partial Array Self-refresh" "0,1,2,3,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " LPCB ,Low-power Configuration Bits" "Disabled,Self-refresh,Power-down,Deep power-down"
|
|
wgroup.long 0x14++0x7
|
|
line.long 0x00 "SDRAMC_IER,SDRAMC Interrupt Enable Register"
|
|
bitfld.long 0x00 0. " RES ,Refresh Error Status" "No effect,Enabled"
|
|
line.long 0x04 "SDRAMC_IDR,SDRAMC Interrupt Disable Register"
|
|
bitfld.long 0x04 0. " RES ,Refresh Error Status" "No effect,Disabled"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x00 "SDRAMC_IMR,SDRAMC Interrupt Mask Register"
|
|
bitfld.long 0x00 0. " RES ,Refresh Error Status" "Disabled,Enabled"
|
|
hgroup.long 0x20++0x3
|
|
hide.long 0x00 "SDRAMC_ISR,SDRAMC Interrupt Status Register"
|
|
in
|
|
group.long 0x24++0xB
|
|
line.long 0x00 "SDRAMC_MDR,SDRAMC Memory Device Register"
|
|
bitfld.long 0x00 0.--1. " MD ,Memory Device Type" "SDRAM,Low-power,?..."
|
|
line.long 0x04 "SDRAMC_CR1,SDRAMC Configuration 1 Register"
|
|
bitfld.long 0x04 0.--3. " TMRD ,Load Mode Register Command to Active or Refresh Command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "SDRAMC_OCMS,SDRAMC OCMS Register"
|
|
bitfld.long 0x08 0. " SDR_SE ,SDRAM Memory Controller Scrambling Enable" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree.open "SMC (Static Memory Controller)"
|
|
tree "NFC (NAND Flash Controller Operations)"
|
|
base ad:0x68000000
|
|
width 16.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "NFCADDR_CMD,NFC Address Command"
|
|
bitfld.long 0x00 27. " NFCCMD ,NFC Command Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NFCWR ,NFC Write Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " NFCEN ,NFC Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--24. " CSID ,Chip Select Identifier" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 19.--21. " ACYCLE ,Number of Address required for the current command" "0,1,2,3,4,5,?..."
|
|
bitfld.long 0x00 18. " VCMD2 ,Valid Cycle 2 Command" "Not valid,Valid"
|
|
textline " "
|
|
hexmask.long.byte 0x00 10.--17. 1. " CMD2 ,Command Register Value for Cycle 2"
|
|
hexmask.long.byte 0x00 2.--9. 1. " CMD1 ,Command Register Value for Cycle 1"
|
|
wgroup.long 0x04++0x3
|
|
line.long 0x00 "NFCDATA_ADDT,NFC Data Address"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ADDR_CYCLE4 ,NAND Flash Array Address Cycle 4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ADDR_CYCLE3 ,NAND Flash Array Address Cycle 3"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ADDR_CYCLE2 ,NAND Flash Array Address Cycle 2"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " ADDR_CYCLE1 ,NAND Flash Array Address Cycle 1"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x00 "NFCDATA_STATUS,NFC DATA Status"
|
|
bitfld.long 0x00 27. " NFCBUSY ,NFC Command Enable" "Idle,Busy"
|
|
bitfld.long 0x00 26. " NFCWR ,NFC Write Enable" "Read mode,Write mode"
|
|
bitfld.long 0x00 25. " NFCEN ,NFC Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--24. " CSID ,Chip Select Identifier" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 19.--21. " ACYCLE ,Number of Address required for the current command" ",1,2,3,4,5,?..."
|
|
bitfld.long 0x00 18. " VCMD2 ,Valid Cycle 2 Command" "Not valid,Valid"
|
|
textline " "
|
|
hexmask.long.byte 0x00 10.--17. 1. " CMD2 ,Command Register Value for Cycle 2"
|
|
hexmask.long.byte 0x00 2.--9. 1. " CMD1 ,Command Register Value for Cycle 1"
|
|
width 0xb
|
|
tree.end
|
|
base ad:0x400E0000
|
|
width 0xC
|
|
tree "Common Registers"
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "SMC_CFG,SMC NFC Configuration Register"
|
|
bitfld.long 0x00 20.--22. " DTOMUL ,Data Timeout Multiplier" "1,16,128,256,1024,4096,65536,1048576"
|
|
bitfld.long 0x00 16.--19. " DTOCYC ,Data Timeout Cycle Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RBEDGE ,Ready/Busy Signal Edge Detection" "Level,Transition"
|
|
bitfld.long 0x00 12. " EDGECTRL ,Rising/Falling Edge Detection Control" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RSPARE ,Read Spare Area" "Not read,Read"
|
|
bitfld.long 0x00 8. " WSPARE ,Write Spare Area" "Not written,Written"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PAGESIZE ,Page size of the NAND Flash device (Main Area + Spare Area/Spare Area)" "528 Bytes/16 byte,1056 Bytes/32 bytes,2112 Bytes/64 bytes,4224 Bytes/128 bytes"
|
|
wgroup.long 0x04++0x3
|
|
line.long 0x00 "SMC_CTRL,SMC NFC Control Register"
|
|
bitfld.long 0x00 1. " NFCDIS ,NAND Flash Controller Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " NFCEN ,NAND Flash Controller Enable" "Disabled,Enabled"
|
|
hgroup.long 0x08++0x3
|
|
hide.long 0x00 "SMC_SR,SMC NFC Status Register"
|
|
in
|
|
wgroup.long 0x0c++0x7
|
|
line.long 0x00 "SMC_IER,SMC NFC Interrupt Enable Register"
|
|
bitfld.long 0x00 24. " RB_EDGE0 ,Ready/Busy Line x Interrupt Enable" "No effect,Enable"
|
|
bitfld.long 0x00 23. " NFCASE ,NFC Access Size Error Interrupt Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 22. " AWB ,Accessing While Busy Interrupt Enable" "No effect,Enable"
|
|
bitfld.long 0x00 21. " UNDEF ,Undefined Area Access Interrupt Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 20. " DTOE ,Data Timeout Error Interrupt Enable" "No effect,Enable"
|
|
bitfld.long 0x00 17. " CMDDONE ,Command Done Interrupt Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 16. " XFRDONE ,Transfer Done Interrupt Enable" "No effect,Enable"
|
|
bitfld.long 0x00 5. " RB_FALL ,Ready Busy Falling Edge Detection Interrupt Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RB_RISE ,Ready Busy Rising Edge Detection Interrupt Enable" "No effect,Enable"
|
|
line.long 0x04 "SMC_IDR,SMC NFC Interrupt Disable Register"
|
|
bitfld.long 0x04 24. " RB_EDGE0 ,Ready/Busy Line x Interrupt Enable" "No effect,Disable"
|
|
bitfld.long 0x04 23. " NFCASE ,NFC Access Size Error Interrupt Enable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x04 22. " AWB ,Accessing While Busy Interrupt Enable" "No effect,Disable"
|
|
bitfld.long 0x04 21. " UNDEF ,Undefined Area Access Interrupt Enable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x04 20. " DTOE ,Data Timeout Error Interrupt Enable" "No effect,Disable"
|
|
bitfld.long 0x04 17. " CMDDONE ,Command Done Interrupt Enable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x04 16. " XFRDONE ,Transfer Done Interrupt Enable" "No effect,Disable"
|
|
bitfld.long 0x04 5. " RB_FALL ,Ready Busy Falling Edge Detection Interrupt Enable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x04 4. " RB_RISE ,Ready Busy Rising Edge Detection Interrupt Enable" "No effect,Disable"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "SMC_IMR,SMC NFC Interrupt Mask Register"
|
|
bitfld.long 0x00 24. " RB_EDGE0 ,Ready/Busy Line x Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " NFCASE ,NFC Access Size Error Interrupt Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " AWB ,Accessing While Busy Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " UNDEF ,Undefined Area Access Interrupt Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 20. " DTOE ,Data Timeout Error Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " CMDDONE ,Command Done Interrupt Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " XFRDONE ,Transfer Done Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " RB_FALL ,Ready Busy Falling Edge Detection Interrupt Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RB_RISE ,Ready Busy Rising Edge Detection Interrupt Mask" "Not masked,Masked"
|
|
group.long 0x18++0x7
|
|
line.long 0x00 "SMC_ADDR,SMC NFC Address Cycle Zero Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ADDR_CYCLE0 ,NAND Flash Array Address cycle 0"
|
|
line.long 0x04 "SMC_BANK,SMC NFC Bank Register"
|
|
bitfld.long 0x04 0.--2. " BANK ,Bank Identifier" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x00 "SMC_ECC_CTRL,SMC ECC Control Register"
|
|
bitfld.long 0x00 1. " SWRST ,Software Reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " RST ,Reset ECC" "No reset,Reset"
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "SMC_ECC_MD,SMC ECC MODE Register"
|
|
bitfld.long 0x00 4.--5. " TYPCORREC ,Type of correction" "Page,256 bytes,512 bytes,?..."
|
|
bitfld.long 0x00 0.--1. " ECC_PAGESIZE ,Page size of the NAND Flash device" "528 Bytes,1056 Bytes,2112 Bytes,4224 Bytes"
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "SMC_ECC_SR1,SMC ECC Status Register 1"
|
|
bitfld.long 0x00 30. " ECCERR7 ,Multiple Error in the page (1792-2047 byte or 3584-4095 byte)" "No error,Error"
|
|
bitfld.long 0x00 29. " ECCERR7 ,ECC Error in the page (1792-2047 byte or 3584-4095 byte)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RECERR7 ,Recoverable Error in the page (1792-2047 byte or 3584-4095 byte)" "No error,Error"
|
|
bitfld.long 0x00 26. " ECCERR6 ,Multiple Error in the page (1536-1791 byte or 3072-3583 byte)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ECCERR6 ,ECC Error in the page (1536-1791 byte or 3072-3583 byte)" "No error,Error"
|
|
bitfld.long 0x00 24. " RECERR6 ,Recoverable Error in the page (1280-1535 byte or 2560-3071 byte)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ECCERR5 ,Multiple Error in the page (1280-1535 byte or 2560-3071 byte)" "No error,Error"
|
|
bitfld.long 0x00 21. " ECCERR5 ,ECC Error in the page (1280-1535 byte or 2560-3071 byte)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 20. " RECERR5 ,Recoverable Error in the page (1280-1535 byte or 2560-3071 byte)" "No error,Error"
|
|
bitfld.long 0x00 18. " ECCERR4 ,Multiple Error in the page (1024-1279 byte or 2048-2559 byte)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ECCERR4 ,ECC Error in the page (1024-1279 byte or 2048-2559 byte)" "No error,Error"
|
|
bitfld.long 0x00 16. " RECERR4 ,Recoverable Error in the page (1024-1279 byte or 2048-2559 byte)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 14. " MULERR3 ,Multiple Error in the page (768-1023 byte or 1536-2047 byte)" "No error,Error"
|
|
bitfld.long 0x00 13. " ECCERR3 ,ECC Error in the page (768-1023 byte or 1536-2047 byte)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RECERR3 ,Recoverable Error in the page (768-1023 byte or 1536-2047 byte)" "No error,Error"
|
|
bitfld.long 0x00 10. " MULERR2 ,Multiple Error in the page(512-767 byte or 1024-1535 byte)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ECCERR2 ,ECC Error in the page (512-767 byte or 1024-1535 byte)" "No error,Error"
|
|
bitfld.long 0x00 8. " RECERR2 ,Recoverable Error in the page (512-767 byte or 1024-1535 byte)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 6. " MULERR1 ,Multiple Error in the page (256-511 byte or 512-1023 byte)" "No error,Error"
|
|
bitfld.long 0x00 5. " ECCERR1 ,ECC Error in the page (256-511 byte or 512-1023 byte)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RECERR1 ,Recoverable Error in the page (256-511 byte or 512-1023 byte)" "No error,Error"
|
|
bitfld.long 0x00 2. " ECCERR0 ,Multiple Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ECCERR0 ,ECC Error" "No error,Error"
|
|
bitfld.long 0x00 0. " RECERR0 ,Recoverable Error" "No error,Error"
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "SMC_ECC_SR2,SMC ECC Status Register 2"
|
|
bitfld.long 0x00 30. " ECCERR15 ,Multiple Error in the page (3840-4095 byte)" "No error,Error"
|
|
bitfld.long 0x00 29. " ECCERR15 ,ECC Error in the page (3840-4095 byte)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RECERR15 ,Recoverable Error in the page (3840-4095 byte)" "No error,Error"
|
|
bitfld.long 0x00 26. " ECCERR14 ,Multiple Error in the page (3584-3839 byte)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ECCERR14 ,ECC Error in the page (3584-3839 byte)" "No error,Error"
|
|
bitfld.long 0x00 24. " RECERR14 ,Recoverable Error in the page (3584-3839 byte)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ECCERR13 ,Multiple Error in the page (3328-3583 byte)" "No error,Error"
|
|
bitfld.long 0x00 21. " ECCERR13 ,ECC Error in the page (3328-3583 byte)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 20. " RECERR13 ,Recoverable Error in the page (3328-3583 byte)" "No error,Error"
|
|
bitfld.long 0x00 18. " ECCERR12 ,Multiple Error in the page (3072-3327 byte)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ECCERR12 ,ECC Error in the page (3072-3327 byte)" "No error,Error"
|
|
bitfld.long 0x00 16. " RECERR12 ,Recoverable Error in the page (3072-3327 byte)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 14. " MULERR11 ,Multiple Error in the page (2816-3071 byte)" "No error,Error"
|
|
bitfld.long 0x00 13. " ECCERR11 ,ECC Error in the page (2816-3071 byte)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RECERR11 ,Recoverable Error in the page (2816-3071 byte)" "No error,Error"
|
|
bitfld.long 0x00 10. " MULERR10 ,Multiple Error in the page (2560-2559 byte)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ECCERR10 ,ECC Error in the page (2560-2559 byte)" "No error,Error"
|
|
bitfld.long 0x00 8. " RECERR10 ,Recoverable Error in the page (2560-2559 byte)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 6. " MULERR9 ,Multiple Error in the page (2304-2559 byte)" "No error,Error"
|
|
bitfld.long 0x00 5. " ECCERR9 ,ECC Error in the page (2304-2559 byte)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RECERR9 ,Recoverable Error in the page (2304-2559 byte)" "No error,Error"
|
|
bitfld.long 0x00 2. " ECCERR8 ,Multiple Error in the page (2048-2303 byte)" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ECCERR8 ,ECC Error in the page (2048-2303 byte)" "No error,Error"
|
|
bitfld.long 0x00 0. " RECERR8 ,Recoverable Error in the page (2048-2303 byte)" "No error,Error"
|
|
if ((d.l((ad:0x400E0000+0x24))&0x30)==0x0)
|
|
rgroup.long 0x2C++0x7
|
|
line.long 0x00 "SMC_ECC_PR0,SMC ECC Parity Register 0"
|
|
hexmask.long.word 0x00 4.--15. 0x10 " WORDADDR ,Word Address"
|
|
bitfld.long 0x00 0.--3. " BITADDR ,Bit Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "SMC_ECC_PR1,SMC_ECC Parity Register 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " NPARITY ,Parity N"
|
|
elif ((d.l((ad:0x400E0000+0x24))&0x30)==0x20)
|
|
rgroup.long 0x2c++0x1f
|
|
line.long 0x0 "SMC_ECC_PR0 ,SMC ECC Parity Register 0 "
|
|
hexmask.long.word 0x0 12.--23. 1. " NPARITY0 ,Parity N"
|
|
hexmask.long.word 0x0 3.--11. 0x8 " WORDADDR0 ,Corrupted Word Address in the page (0-511 byte)"
|
|
textline " "
|
|
bitfld.long 0x0 0.--2. " BITADDR0 ,Corrupted Bit Address in the page (0-511 byte)" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "SMC_ECC_PR1 ,SMC ECC Parity Register 1 "
|
|
hexmask.long.word 0x4 12.--23. 1. " NPARITY1 ,Parity N"
|
|
hexmask.long.word 0x4 3.--11. 0x8 " WORDADDR1 ,Corrupted Word Address in the page (512-1023 byte)"
|
|
textline " "
|
|
bitfld.long 0x4 0.--2. " BITADDR1 ,Corrupted Bit Address in the page (512-1023 byte)" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "SMC_ECC_PR2 ,SMC ECC Parity Register 2 "
|
|
hexmask.long.word 0x8 12.--23. 1. " NPARITY2 ,Parity N"
|
|
hexmask.long.word 0x8 3.--11. 0x8 " WORDADDR2 ,Corrupted Word Address in the page (1024-1535 byte)"
|
|
textline " "
|
|
bitfld.long 0x8 0.--2. " BITADDR2 ,Corrupted Bit Address in the page (1024-1535 byte)" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "SMC_ECC_PR3 ,SMC ECC Parity Register 3 "
|
|
hexmask.long.word 0xC 12.--23. 1. " NPARITY3 ,Parity N"
|
|
hexmask.long.word 0xC 3.--11. 0x8 " WORDADDR3 ,Corrupted Word Address in the page (1536-2047 byte)"
|
|
textline " "
|
|
bitfld.long 0xC 0.--2. " BITADDR3 ,Corrupted Bit Address in the page (1536-2047 byte)" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "SMC_ECC_PR4 ,SMC ECC Parity Register 4 "
|
|
hexmask.long.word 0x10 12.--23. 1. " NPARITY4 ,Parity N"
|
|
hexmask.long.word 0x10 3.--11. 0x8 " WORDADDR4 ,Corrupted Word Address in the page (2048-2559 byte)"
|
|
textline " "
|
|
bitfld.long 0x10 0.--2. " BITADDR4 ,Corrupted Bit Address in the page (2048-2559 byte)" "0,1,2,3,4,5,6,7"
|
|
line.long 0x14 "SMC_ECC_PR5 ,SMC ECC Parity Register 5 "
|
|
hexmask.long.word 0x14 12.--23. 1. " NPARITY5 ,Parity N"
|
|
hexmask.long.word 0x14 3.--11. 0x8 " WORDADDR5 ,Corrupted Word Address in the page (2560-3071 byte)"
|
|
textline " "
|
|
bitfld.long 0x14 0.--2. " BITADDR5 ,Corrupted Bit Address in the page (2560-3071 byte)" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "SMC_ECC_PR6 ,SMC ECC Parity Register 6 "
|
|
hexmask.long.word 0x18 12.--23. 1. " NPARITY6 ,Parity N"
|
|
hexmask.long.word 0x18 3.--11. 0x8 " WORDADDR6 ,Corrupted Word Address in the page (3072-3583 byte)"
|
|
textline " "
|
|
bitfld.long 0x18 0.--2. " BITADDR6 ,Corrupted Bit Address in the page (3072-3583 byte)" "0,1,2,3,4,5,6,7"
|
|
line.long 0x1C "SMC_ECC_PR7 ,SMC ECC Parity Register 7 "
|
|
hexmask.long.word 0x1C 12.--23. 1. " NPARITY7 ,Parity N"
|
|
hexmask.long.word 0x1C 3.--11. 0x8 " WORDADDR7 ,Corrupted Word Address in the page (3584-4095 byte)"
|
|
textline " "
|
|
bitfld.long 0x1C 0.--2. " BITADDR7 ,Corrupted Bit Address in the page (3584-4095 byte)" "0,1,2,3,4,5,6,7"
|
|
else
|
|
rgroup.long 0x2c++0x3f
|
|
line.long 0x0 "SMC_ECC_PR0 ,SMC ECC Parity Register 0 "
|
|
hexmask.long.word 0x0 12.--22. 1. " NPARITY0 ,Parity N"
|
|
hexmask.long.word 0x0 3.--10. 0x8 " WORDADDR0 ,Corrupted Word Address in the page (0-255 byte)"
|
|
textline " "
|
|
bitfld.long 0x0 0.--2. " BITADDR0 ,Corrupted Bit Address in the page (0-255 byte)" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "SMC_ECC_PR1 ,SMC ECC Parity Register 1 "
|
|
hexmask.long.word 0x4 12.--22. 1. " NPARITY1 ,Parity N"
|
|
hexmask.long.word 0x4 3.--10. 0x8 " WORDADDR1 ,Corrupted Word Address in the page (256-511 byte)"
|
|
textline " "
|
|
bitfld.long 0x4 0.--2. " BITADDR1 ,Corrupted Bit Address in the page (256-511 byte)" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "SMC_ECC_PR2 ,SMC ECC Parity Register 2 "
|
|
hexmask.long.word 0x8 12.--22. 1. " NPARITY2 ,Parity N"
|
|
hexmask.long.word 0x8 3.--10. 0x8 " WORDADDR2 ,Corrupted Word Address in the page (512-767 byte)"
|
|
textline " "
|
|
bitfld.long 0x8 0.--2. " BITADDR2 ,Corrupted Bit Address in the page (512-767 byte)" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "SMC_ECC_PR3 ,SMC ECC Parity Register 3 "
|
|
hexmask.long.word 0xC 12.--22. 1. " NPARITY3 ,Parity N"
|
|
hexmask.long.word 0xC 3.--10. 0x8 " WORDADDR3 ,Corrupted Word Address in the page (768-1023 byte)"
|
|
textline " "
|
|
bitfld.long 0xC 0.--2. " BITADDR3 ,Corrupted Bit Address in the page (768-1023 byte)" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "SMC_ECC_PR4 ,SMC ECC Parity Register 4 "
|
|
hexmask.long.word 0x10 12.--22. 1. " NPARITY4 ,Parity N"
|
|
hexmask.long.word 0x10 3.--10. 0x8 " WORDADDR4 ,Corrupted Word Address in the page (1024-1279 byte)"
|
|
textline " "
|
|
bitfld.long 0x10 0.--2. " BITADDR4 ,Corrupted Bit Address in the page (1024-1279 byte)" "0,1,2,3,4,5,6,7"
|
|
line.long 0x14 "SMC_ECC_PR5 ,SMC ECC Parity Register 5 "
|
|
hexmask.long.word 0x14 12.--22. 1. " NPARITY5 ,Parity N"
|
|
hexmask.long.word 0x14 3.--10. 0x8 " WORDADDR5 ,Corrupted Word Address in the page (1280-1535 byte)"
|
|
textline " "
|
|
bitfld.long 0x14 0.--2. " BITADDR5 ,Corrupted Bit Address in the page (1280-1535 byte)" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "SMC_ECC_PR6 ,SMC ECC Parity Register 6 "
|
|
hexmask.long.word 0x18 12.--22. 1. " NPARITY6 ,Parity N"
|
|
hexmask.long.word 0x18 3.--10. 0x8 " WORDADDR6 ,Corrupted Word Address in the page (1536-1791 byte)"
|
|
textline " "
|
|
bitfld.long 0x18 0.--2. " BITADDR6 ,Corrupted Bit Address in the page (1536-1791 byte)" "0,1,2,3,4,5,6,7"
|
|
line.long 0x1C "SMC_ECC_PR7 ,SMC ECC Parity Register 7 "
|
|
hexmask.long.word 0x1C 12.--22. 1. " NPARITY7 ,Parity N"
|
|
hexmask.long.word 0x1C 3.--10. 0x8 " WORDADDR7 ,Corrupted Word Address in the page (1792-2047 byte)"
|
|
textline " "
|
|
bitfld.long 0x1C 0.--2. " BITADDR7 ,Corrupted Bit Address in the page (1792-2047 byte)" "0,1,2,3,4,5,6,7"
|
|
line.long 0x20 "SMC_ECC_PR8 ,SMC ECC Parity Register 8 "
|
|
hexmask.long.word 0x20 12.--22. 1. " NPARITY8 ,Parity N"
|
|
hexmask.long.word 0x20 3.--10. 0x8 " WORDADDR8 ,Corrupted Word Address in the page (2048-2303 byte)"
|
|
textline " "
|
|
bitfld.long 0x20 0.--2. " BITADDR8 ,Corrupted Bit Address in the page (2048-2303 byte)" "0,1,2,3,4,5,6,7"
|
|
line.long 0x24 "SMC_ECC_PR9 ,SMC ECC Parity Register 9 "
|
|
hexmask.long.word 0x24 12.--22. 1. " NPARITY9 ,Parity N"
|
|
hexmask.long.word 0x24 3.--10. 0x8 " WORDADDR9 ,Corrupted Word Address in the page (2304-2559 byte)"
|
|
textline " "
|
|
bitfld.long 0x24 0.--2. " BITADDR9 ,Corrupted Bit Address in the page (2304-2559 byte)" "0,1,2,3,4,5,6,7"
|
|
line.long 0x28 "SMC_ECC_PR10,SMC ECC Parity Register 10"
|
|
hexmask.long.word 0x28 12.--22. 1. " NPARITY10 ,Parity N"
|
|
hexmask.long.word 0x28 3.--10. 0x8 " WORDADDR10 ,Corrupted Word Address in the page (2560-2815 byte)"
|
|
textline " "
|
|
bitfld.long 0x28 0.--2. " BITADDR10 ,Corrupted Bit Address in the page (2560-2815 byte)" "0,1,2,3,4,5,6,7"
|
|
line.long 0x2C "SMC_ECC_PR11,SMC ECC Parity Register 11"
|
|
hexmask.long.word 0x2C 12.--22. 1. " NPARITY11 ,Parity N"
|
|
hexmask.long.word 0x2C 3.--10. 0x8 " WORDADDR11 ,Corrupted Word Address in the page (2816-3071 byte)"
|
|
textline " "
|
|
bitfld.long 0x2C 0.--2. " BITADDR11 ,Corrupted Bit Address in the page (2816-3071 byte)" "0,1,2,3,4,5,6,7"
|
|
line.long 0x30 "SMC_ECC_PR12,SMC ECC Parity Register 12"
|
|
hexmask.long.word 0x30 12.--22. 1. " NPARITY12 ,Parity N"
|
|
hexmask.long.word 0x30 3.--10. 0x8 " WORDADDR12 ,Corrupted Word Address in the page (3072-3327 byte)"
|
|
textline " "
|
|
bitfld.long 0x30 0.--2. " BITADDR12 ,Corrupted Bit Address in the page (3072-3327 byte)" "0,1,2,3,4,5,6,7"
|
|
line.long 0x34 "SMC_ECC_PR13,SMC ECC Parity Register 13"
|
|
hexmask.long.word 0x34 12.--22. 1. " NPARITY13 ,Parity N"
|
|
hexmask.long.word 0x34 3.--10. 0x8 " WORDADDR13 ,Corrupted Word Address in the page (3328-3583 byte)"
|
|
textline " "
|
|
bitfld.long 0x34 0.--2. " BITADDR13 ,Corrupted Bit Address in the page (3328-3583 byte)" "0,1,2,3,4,5,6,7"
|
|
line.long 0x38 "SMC_ECC_PR14,SMC ECC Parity Register 14"
|
|
hexmask.long.word 0x38 12.--22. 1. " NPARITY14 ,Parity N"
|
|
hexmask.long.word 0x38 3.--10. 0x8 " WORDADDR14 ,Corrupted Word Address in the page (3584-3839 byte)"
|
|
textline " "
|
|
bitfld.long 0x38 0.--2. " BITADDR14 ,Corrupted Bit Address in the page (3584-3839 byte)" "0,1,2,3,4,5,6,7"
|
|
line.long 0x3C "SMC_ECC_PR15,SMC ECC Parity Register 15"
|
|
hexmask.long.word 0x3C 12.--22. 1. " NPARITY15 ,Parity N"
|
|
hexmask.long.word 0x3C 3.--10. 0x8 " WORDADDR15 ,Corrupted Word Address in the page (3840-4095 byte)"
|
|
textline " "
|
|
bitfld.long 0x3C 0.--2. " BITADDR15 ,Corrupted Bit Address in the page (3840-4095 byte)" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
tree.end
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
tree "CS0"
|
|
group.long 0x70++0xf
|
|
line.long 0x00 "SMC_SETUP0,SMC Setup Register 0"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x04 "SMC_PULSE0,SMC Pulse Register 0"
|
|
hexmask.long.byte 0x4 24.--29. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--21. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
textline " "
|
|
hexmask.long.byte 0x4 8.--13. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
hexmask.long.byte 0x4 0.--5. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x08 "SMC_CYCLE0,SMC Cycle Register 0"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
line.long 0x0c "SMC_TIMINGS0,SMC Timings Register"
|
|
bitfld.long 0x0c 31. " NFSEL ,NAND Flash Selection" "Disabled,Enabled"
|
|
bitfld.long 0x0c 28.--30. " RBNSEL ,Ready/Busy Line Selection" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--27. " TWB ,WEN High to REN to Busy" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0c 16.--19. " TRR ,Ready to REN Low Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " OCMS ,Off Chip Memory Scrambling Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8.--11. " TAR ,ALE to REN Low Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0c 4.--7. " TADL ,ALE to Data Start" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0c 0.--3. " TCLR ,CLE to REN Low Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((d.l((ad:0x400E0000+0x70+0x10)))&0x1000)==0x1000)
|
|
group.long (0x70+0x10)++0x3
|
|
line.long 0x00 "SMC_MODE0,SMC Mode Register 0"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DBW ,Data Bus Width" "8-bit,16-bit"
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x70+0x10)++0x3
|
|
line.long 0x00 "SMC_MODE0,SMC Mode Register 0"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DBW ,Data Bus Width" "8-bit,16-bit"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS1"
|
|
group.long 0x84++0xf
|
|
line.long 0x00 "SMC_SETUP1,SMC Setup Register 1"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x04 "SMC_PULSE1,SMC Pulse Register 1"
|
|
hexmask.long.byte 0x4 24.--29. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--21. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
textline " "
|
|
hexmask.long.byte 0x4 8.--13. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
hexmask.long.byte 0x4 0.--5. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x08 "SMC_CYCLE1,SMC Cycle Register 1"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
line.long 0x0c "SMC_TIMINGS1,SMC Timings Register"
|
|
bitfld.long 0x0c 31. " NFSEL ,NAND Flash Selection" "Disabled,Enabled"
|
|
bitfld.long 0x0c 28.--30. " RBNSEL ,Ready/Busy Line Selection" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--27. " TWB ,WEN High to REN to Busy" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0c 16.--19. " TRR ,Ready to REN Low Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " OCMS ,Off Chip Memory Scrambling Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8.--11. " TAR ,ALE to REN Low Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0c 4.--7. " TADL ,ALE to Data Start" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0c 0.--3. " TCLR ,CLE to REN Low Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((d.l((ad:0x400E0000+0x84+0x10)))&0x1000)==0x1000)
|
|
group.long (0x84+0x10)++0x3
|
|
line.long 0x00 "SMC_MODE1,SMC Mode Register 1"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DBW ,Data Bus Width" "8-bit,16-bit"
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x84+0x10)++0x3
|
|
line.long 0x00 "SMC_MODE1,SMC Mode Register 1"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DBW ,Data Bus Width" "8-bit,16-bit"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS2"
|
|
group.long 0x98++0xf
|
|
line.long 0x00 "SMC_SETUP2,SMC Setup Register 2"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x04 "SMC_PULSE2,SMC Pulse Register 2"
|
|
hexmask.long.byte 0x4 24.--29. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--21. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
textline " "
|
|
hexmask.long.byte 0x4 8.--13. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
hexmask.long.byte 0x4 0.--5. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x08 "SMC_CYCLE2,SMC Cycle Register 2"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
line.long 0x0c "SMC_TIMINGS2,SMC Timings Register"
|
|
bitfld.long 0x0c 31. " NFSEL ,NAND Flash Selection" "Disabled,Enabled"
|
|
bitfld.long 0x0c 28.--30. " RBNSEL ,Ready/Busy Line Selection" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--27. " TWB ,WEN High to REN to Busy" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0c 16.--19. " TRR ,Ready to REN Low Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " OCMS ,Off Chip Memory Scrambling Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8.--11. " TAR ,ALE to REN Low Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0c 4.--7. " TADL ,ALE to Data Start" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0c 0.--3. " TCLR ,CLE to REN Low Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((d.l((ad:0x400E0000+0x98+0x10)))&0x1000)==0x1000)
|
|
group.long (0x98+0x10)++0x3
|
|
line.long 0x00 "SMC_MODE2,SMC Mode Register 2"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DBW ,Data Bus Width" "8-bit,16-bit"
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x98+0x10)++0x3
|
|
line.long 0x00 "SMC_MODE2,SMC Mode Register 2"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DBW ,Data Bus Width" "8-bit,16-bit"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS3"
|
|
group.long 0xAC++0xf
|
|
line.long 0x00 "SMC_SETUP3,SMC Setup Register 3"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x04 "SMC_PULSE3,SMC Pulse Register 3"
|
|
hexmask.long.byte 0x4 24.--29. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--21. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
textline " "
|
|
hexmask.long.byte 0x4 8.--13. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
hexmask.long.byte 0x4 0.--5. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x08 "SMC_CYCLE3,SMC Cycle Register 3"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
line.long 0x0c "SMC_TIMINGS3,SMC Timings Register"
|
|
bitfld.long 0x0c 31. " NFSEL ,NAND Flash Selection" "Disabled,Enabled"
|
|
bitfld.long 0x0c 28.--30. " RBNSEL ,Ready/Busy Line Selection" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--27. " TWB ,WEN High to REN to Busy" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0c 16.--19. " TRR ,Ready to REN Low Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " OCMS ,Off Chip Memory Scrambling Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8.--11. " TAR ,ALE to REN Low Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0c 4.--7. " TADL ,ALE to Data Start" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0c 0.--3. " TCLR ,CLE to REN Low Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((d.l((ad:0x400E0000+0xAC+0x10)))&0x1000)==0x1000)
|
|
group.long (0xAC+0x10)++0x3
|
|
line.long 0x00 "SMC_MODE3,SMC Mode Register 3"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DBW ,Data Bus Width" "8-bit,16-bit"
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0xAC+0x10)++0x3
|
|
line.long 0x00 "SMC_MODE3,SMC Mode Register 3"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DBW ,Data Bus Width" "8-bit,16-bit"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS4"
|
|
group.long 0xC0++0xf
|
|
line.long 0x00 "SMC_SETUP4,SMC Setup Register 4"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x04 "SMC_PULSE4,SMC Pulse Register 4"
|
|
hexmask.long.byte 0x4 24.--29. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--21. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
textline " "
|
|
hexmask.long.byte 0x4 8.--13. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
hexmask.long.byte 0x4 0.--5. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x08 "SMC_CYCLE4,SMC Cycle Register 4"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
line.long 0x0c "SMC_TIMINGS4,SMC Timings Register"
|
|
bitfld.long 0x0c 31. " NFSEL ,NAND Flash Selection" "Disabled,Enabled"
|
|
bitfld.long 0x0c 28.--30. " RBNSEL ,Ready/Busy Line Selection" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--27. " TWB ,WEN High to REN to Busy" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0c 16.--19. " TRR ,Ready to REN Low Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " OCMS ,Off Chip Memory Scrambling Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8.--11. " TAR ,ALE to REN Low Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0c 4.--7. " TADL ,ALE to Data Start" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0c 0.--3. " TCLR ,CLE to REN Low Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((d.l((ad:0x400E0000+0xC0+0x10)))&0x1000)==0x1000)
|
|
group.long (0xC0+0x10)++0x3
|
|
line.long 0x00 "SMC_MODE4,SMC Mode Register 4"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DBW ,Data Bus Width" "8-bit,16-bit"
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0xC0+0x10)++0x3
|
|
line.long 0x00 "SMC_MODE4,SMC Mode Register 4"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DBW ,Data Bus Width" "8-bit,16-bit"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS5"
|
|
group.long 0xD4++0xf
|
|
line.long 0x00 "SMC_SETUP5,SMC Setup Register 5"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x04 "SMC_PULSE5,SMC Pulse Register 5"
|
|
hexmask.long.byte 0x4 24.--29. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--21. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
textline " "
|
|
hexmask.long.byte 0x4 8.--13. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
hexmask.long.byte 0x4 0.--5. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x08 "SMC_CYCLE5,SMC Cycle Register 5"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
line.long 0x0c "SMC_TIMINGS5,SMC Timings Register"
|
|
bitfld.long 0x0c 31. " NFSEL ,NAND Flash Selection" "Disabled,Enabled"
|
|
bitfld.long 0x0c 28.--30. " RBNSEL ,Ready/Busy Line Selection" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--27. " TWB ,WEN High to REN to Busy" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0c 16.--19. " TRR ,Ready to REN Low Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " OCMS ,Off Chip Memory Scrambling Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8.--11. " TAR ,ALE to REN Low Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0c 4.--7. " TADL ,ALE to Data Start" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0c 0.--3. " TCLR ,CLE to REN Low Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((d.l((ad:0x400E0000+0xD4+0x10)))&0x1000)==0x1000)
|
|
group.long (0xD4+0x10)++0x3
|
|
line.long 0x00 "SMC_MODE5,SMC Mode Register 5"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DBW ,Data Bus Width" "8-bit,16-bit"
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0xD4+0x10)++0x3
|
|
line.long 0x00 "SMC_MODE5,SMC Mode Register 5"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DBW ,Data Bus Width" "8-bit,16-bit"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS6"
|
|
group.long 0xE8++0xf
|
|
line.long 0x00 "SMC_SETUP6,SMC Setup Register 6"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x04 "SMC_PULSE6,SMC Pulse Register 6"
|
|
hexmask.long.byte 0x4 24.--29. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--21. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
textline " "
|
|
hexmask.long.byte 0x4 8.--13. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
hexmask.long.byte 0x4 0.--5. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x08 "SMC_CYCLE6,SMC Cycle Register 6"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
line.long 0x0c "SMC_TIMINGS6,SMC Timings Register"
|
|
bitfld.long 0x0c 31. " NFSEL ,NAND Flash Selection" "Disabled,Enabled"
|
|
bitfld.long 0x0c 28.--30. " RBNSEL ,Ready/Busy Line Selection" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--27. " TWB ,WEN High to REN to Busy" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0c 16.--19. " TRR ,Ready to REN Low Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " OCMS ,Off Chip Memory Scrambling Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8.--11. " TAR ,ALE to REN Low Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0c 4.--7. " TADL ,ALE to Data Start" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0c 0.--3. " TCLR ,CLE to REN Low Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((d.l((ad:0x400E0000+0xE8+0x10)))&0x1000)==0x1000)
|
|
group.long (0xE8+0x10)++0x3
|
|
line.long 0x00 "SMC_MODE6,SMC Mode Register 6"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DBW ,Data Bus Width" "8-bit,16-bit"
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0xE8+0x10)++0x3
|
|
line.long 0x00 "SMC_MODE6,SMC Mode Register 6"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DBW ,Data Bus Width" "8-bit,16-bit"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS7"
|
|
group.long 0xFC++0xf
|
|
line.long 0x00 "SMC_SETUP7,SMC Setup Register 7"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x04 "SMC_PULSE7,SMC Pulse Register 7"
|
|
hexmask.long.byte 0x4 24.--29. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--21. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
textline " "
|
|
hexmask.long.byte 0x4 8.--13. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
hexmask.long.byte 0x4 0.--5. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x08 "SMC_CYCLE7,SMC Cycle Register 7"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
line.long 0x0c "SMC_TIMINGS7,SMC Timings Register"
|
|
bitfld.long 0x0c 31. " NFSEL ,NAND Flash Selection" "Disabled,Enabled"
|
|
bitfld.long 0x0c 28.--30. " RBNSEL ,Ready/Busy Line Selection" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--27. " TWB ,WEN High to REN to Busy" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0c 16.--19. " TRR ,Ready to REN Low Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " OCMS ,Off Chip Memory Scrambling Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8.--11. " TAR ,ALE to REN Low Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0c 4.--7. " TADL ,ALE to Data Start" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0c 0.--3. " TCLR ,CLE to REN Low Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((d.l((ad:0x400E0000+0xFC+0x10)))&0x1000)==0x1000)
|
|
group.long (0xFC+0x10)++0x3
|
|
line.long 0x00 "SMC_MODE7,SMC Mode Register 7"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DBW ,Data Bus Width" "8-bit,16-bit"
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0xFC+0x10)++0x3
|
|
line.long 0x00 "SMC_MODE7,SMC Mode Register 7"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DBW ,Data Bus Width" "8-bit,16-bit"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
else
|
|
tree "CS0"
|
|
group.long 0x70++0xf
|
|
line.long 0x00 "SMC_SETUP0,SMC Setup Register 0"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x04 "SMC_PULSE0,SMC Pulse Register 0"
|
|
hexmask.long.byte 0x4 24.--29. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--21. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
textline " "
|
|
hexmask.long.byte 0x4 8.--13. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
hexmask.long.byte 0x4 0.--5. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x08 "SMC_CYCLE0,SMC Cycle Register 0"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
line.long 0x0c "SMC_TIMINGS0,SMC Timings Register"
|
|
bitfld.long 0x0c 31. " NFSEL ,NAND Flash Selection" "Disabled,Enabled"
|
|
bitfld.long 0x0c 28.--30. " RBNSEL ,Ready/Busy Line Selection" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--27. " TWB ,WEN High to REN to Busy" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0c 16.--19. " TRR ,Ready to REN Low Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " OCMS ,Off Chip Memory Scrambling Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8.--11. " TAR ,ALE to REN Low Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0c 4.--7. " TADL ,ALE to Data Start" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0c 0.--3. " TCLR ,CLE to REN Low Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((d.l((ad:0x400E0000+0x70+0x10)))&0x1000)==0x1000)
|
|
group.long (0x70+0x10)++0x3
|
|
line.long 0x00 "SMC_MODE0,SMC Mode Register 0"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DBW ,Data Bus Width" "8-bit,16-bit"
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x70+0x10)++0x3
|
|
line.long 0x00 "SMC_MODE0,SMC Mode Register 0"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DBW ,Data Bus Width" "8-bit,16-bit"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS1"
|
|
group.long 0x84++0xf
|
|
line.long 0x00 "SMC_SETUP1,SMC Setup Register 1"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x04 "SMC_PULSE1,SMC Pulse Register 1"
|
|
hexmask.long.byte 0x4 24.--29. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--21. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
textline " "
|
|
hexmask.long.byte 0x4 8.--13. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
hexmask.long.byte 0x4 0.--5. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x08 "SMC_CYCLE1,SMC Cycle Register 1"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
line.long 0x0c "SMC_TIMINGS1,SMC Timings Register"
|
|
bitfld.long 0x0c 31. " NFSEL ,NAND Flash Selection" "Disabled,Enabled"
|
|
bitfld.long 0x0c 28.--30. " RBNSEL ,Ready/Busy Line Selection" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--27. " TWB ,WEN High to REN to Busy" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0c 16.--19. " TRR ,Ready to REN Low Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " OCMS ,Off Chip Memory Scrambling Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8.--11. " TAR ,ALE to REN Low Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0c 4.--7. " TADL ,ALE to Data Start" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0c 0.--3. " TCLR ,CLE to REN Low Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((d.l((ad:0x400E0000+0x84+0x10)))&0x1000)==0x1000)
|
|
group.long (0x84+0x10)++0x3
|
|
line.long 0x00 "SMC_MODE1,SMC Mode Register 1"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DBW ,Data Bus Width" "8-bit,16-bit"
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x84+0x10)++0x3
|
|
line.long 0x00 "SMC_MODE1,SMC Mode Register 1"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DBW ,Data Bus Width" "8-bit,16-bit"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS2"
|
|
group.long 0x98++0xf
|
|
line.long 0x00 "SMC_SETUP2,SMC Setup Register 2"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x04 "SMC_PULSE2,SMC Pulse Register 2"
|
|
hexmask.long.byte 0x4 24.--29. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--21. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
textline " "
|
|
hexmask.long.byte 0x4 8.--13. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
hexmask.long.byte 0x4 0.--5. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x08 "SMC_CYCLE2,SMC Cycle Register 2"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
line.long 0x0c "SMC_TIMINGS2,SMC Timings Register"
|
|
bitfld.long 0x0c 31. " NFSEL ,NAND Flash Selection" "Disabled,Enabled"
|
|
bitfld.long 0x0c 28.--30. " RBNSEL ,Ready/Busy Line Selection" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--27. " TWB ,WEN High to REN to Busy" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0c 16.--19. " TRR ,Ready to REN Low Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " OCMS ,Off Chip Memory Scrambling Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8.--11. " TAR ,ALE to REN Low Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0c 4.--7. " TADL ,ALE to Data Start" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0c 0.--3. " TCLR ,CLE to REN Low Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((d.l((ad:0x400E0000+0x98+0x10)))&0x1000)==0x1000)
|
|
group.long (0x98+0x10)++0x3
|
|
line.long 0x00 "SMC_MODE2,SMC Mode Register 2"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DBW ,Data Bus Width" "8-bit,16-bit"
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0x98+0x10)++0x3
|
|
line.long 0x00 "SMC_MODE2,SMC Mode Register 2"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DBW ,Data Bus Width" "8-bit,16-bit"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
tree "CS3"
|
|
group.long 0xAC++0xf
|
|
line.long 0x00 "SMC_SETUP3,SMC Setup Register 3"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access"
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length"
|
|
line.long 0x04 "SMC_PULSE3,SMC Pulse Register 3"
|
|
hexmask.long.byte 0x4 24.--29. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access"
|
|
hexmask.long.byte 0x4 16.--21. 1. " NRD_PULSE ,NRD Pulse Length"
|
|
textline " "
|
|
hexmask.long.byte 0x4 8.--13. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access"
|
|
hexmask.long.byte 0x4 0.--5. 1. " NWE_PULSE ,NWE Pulse Length"
|
|
line.long 0x08 "SMC_CYCLE3,SMC Cycle Register 3"
|
|
hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length"
|
|
line.long 0x0c "SMC_TIMINGS3,SMC Timings Register"
|
|
bitfld.long 0x0c 31. " NFSEL ,NAND Flash Selection" "Disabled,Enabled"
|
|
bitfld.long 0x0c 28.--30. " RBNSEL ,Ready/Busy Line Selection" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--27. " TWB ,WEN High to REN to Busy" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0c 16.--19. " TRR ,Ready to REN Low Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " OCMS ,Off Chip Memory Scrambling Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8.--11. " TAR ,ALE to REN Low Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0c 4.--7. " TADL ,ALE to Data Start" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0c 0.--3. " TCLR ,CLE to REN Low Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((d.l((ad:0x400E0000+0xAC+0x10)))&0x1000)==0x1000)
|
|
group.long (0xAC+0x10)++0x3
|
|
line.long 0x00 "SMC_MODE3,SMC Mode Register 3"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DBW ,Data Bus Width" "8-bit,16-bit"
|
|
bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
else
|
|
group.long (0xAC+0x10)++0x3
|
|
line.long 0x00 "SMC_MODE3,SMC Mode Register 3"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DBW ,Data Bus Width" "8-bit,16-bit"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,,Frozen,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD"
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "OCMS and Write Protection registers"
|
|
group.long 0x110++0x3
|
|
line.long 0x00 "SMC_OCMS,SMC OCMS Register"
|
|
bitfld.long 0x00 1. " SRSE ,SRAM Scrambling Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SMSE ,Static Memory Controller Scrambling Enable" "Disabled,Enabled"
|
|
wgroup.long 0x114++0x7
|
|
line.long 0x00 "SMC_KEY1,SMC OCMS Key1 Register"
|
|
line.long 0x04 "SMC_KEY2,SMC OCMS Key2 Register"
|
|
wgroup.long 0x1e4++0x3
|
|
line.long 0x00 "SMC_WPCR,SMC Write Protection Control"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WP_KEY ,Write Protection KEY password"
|
|
bitfld.long 0x00 0. " WP_PEN ,Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0x1e8++0x3
|
|
hide.long 0x00 "SMC_WPSR,SMC Write Protection Status"
|
|
in
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree "PMC (Power Management Controller)"
|
|
base ad:0x400E0600
|
|
width 12.
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "PMC_SCSR,PMC System Clock Status Register"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " PCK2_set/clr ,Programmable Clock 2 Output Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " PCK1_set/clr ,Programmable Clock 1 Output Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " PCK0_set/clr ,Programmable Clock 0 Output Status" "Disabled,Enabled"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " UOTGCLK_set/clr ,USB OTG Clock" "Disabled,Enabled"
|
|
elif (cpuis("ATSAM4E*"))
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " UDP_set/clr ,USB Device Port Clock" "Disabled,Enabled"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " UOTGCLK_set/clr ,USB OTG Clock" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PMC_PCSR,PMC Peripheral Clock Status Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " TC4_set/clr ,Timer Counter 4 (Peripheral ID 31) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " TC3_set/clr ,Timer Counter 3 (Peripheral ID 30)Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " TC2_set/clr ,Timer Counter 2 (Peripheral ID 29) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " TC1_set/clr ,Timer Counter 1 (Peripheral ID 28)Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " TC0_set/clr ,Timer Counter 0 (Peripheral ID 27) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " SSC_set/clr ,Synchronous Serial Controller (Peripheral ID 26) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " SPI1_set/clr ,Serial Peripheral Interface (Peripheral ID 25) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " SPI0_set/clr ,Serial Peripheral Interface (Peripheral ID 24) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 23. " TWI1_set/clr ,Two-Wire Interface 1 (Peripheral ID 24) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " TWI0_set/clr ,Two-Wire Interface 0 (Peripheral ID 22) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " HSMCI_set/clr ,High Speed Multimedia Card Interface (Peripheral ID 21) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " USART3_set/clr ,USART 3 (Peripheral ID 20) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " USART2_set/clr ,USART 2 (Peripheral ID 19) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " USART1_set/clr ,USART 1 (Peripheral ID 18) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " USART0_set/clr ,USART 0 (Peripheral ID 17) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " PIOF_set/clr ,Parallel I/O Controller F (Peripheral ID 16) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " PIOE_set/clr ,Parallel I/O Controller E (Peripheral ID 15) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " PIOD_set/clr ,Parallel I/O Controller D (Peripheral ID 14) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " PIOC_set/clr ,Parallel I/O Controller C (Peripheral ID 13) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " PIOB_set/clr ,Parallel I/O Controller B (Peripheral ID 12) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " PIOA_set/clr ,Parallel I/O Controller A (Peripheral ID 11) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " SMC_SDRAMC_set/clr ,Static Memory Controller/Synchronous Dynamic RAM Controller (Peripheral ID 9) Clock Status" "Disabled,Enabled"
|
|
elif (cpuis("ATSAM4E*"))
|
|
setclrfld.long 0x0 31. -0x8 31. -0x4 31. " AFEC1_set/clr ,Analog Front End 1 (Peripheral ID 31) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " AFEC0_set/clr ,Analog Front End 0 (Peripheral ID 30) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " TC8_set/clr ,Timer/Counter 8 (Peripheral ID 29)Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " TC7_set/clr ,Timer Counter 7 Controller (Peripheral ID 28) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " TC6_set/clr ,Timer Counter 6 Controller (Peripheral ID 27) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " TC5_set/clr ,Timer Counter 5 Controller (Peripheral ID 26) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " TC4_set/clr ,Timer Counter 4 (Peripheral ID 25) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " TC3_set/clr ,Timer Counter 3 (Peripheral ID 24) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " TC2_set/clr ,Timer Counter 2 (Peripheral ID 23) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " TC1_set/clr ,Timer Counter 1 (Peripheral ID 22) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " TC0_set/clr ,Timer Counter 0 (Peripheral ID 21) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " DMAC_set/clr ,DMAC (Peripheral ID 20) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " SPI_set/clr ,Serial Peripheral Interface (Peripheral ID 19) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " TWI1_set/clr ,Two-wire Interface 1 (Peripheral ID 18) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " TWI0_set/clr ,Two-wire Interface 0 Peripheral ID 15) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " HSMCI_set/clr ,Multimedia Card Interface (Peripheral ID 14) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " USART1_set/clr ,USART 1 (Peripheral ID 15) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " USART0_set/clr ,USART 0 (Peripheral ID 14) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="ATSAM4E16C"&&cpu()!="ATSAM4E8C")
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " PIOE_set/clr ,Parallel I/O Controller E (Peripheral ID 13) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " PIOD_set/clr ,Parallel I/O Controller D (Peripheral ID 12) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " PIOC_set/clr ,Parallel I/O Controller C (Peripheral ID 11) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " PIOB_set/clr ,Parallel I/O Controller B (Peripheral ID 10) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " PIOA_set/clr ,Parallel I/O Controller A (Peripheral ID 9) Clock Status" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " UDPHS_set/clr ,USB Device High Speed (Peripheral ID 29) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " DMAC_set/clr ,DMA Controller (Peripheral ID 28)Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " ADC_set/clr ,10-bit ADC Controller (Peripheral ID 27) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " ADC12B_set/clr ,12-bit ADC Controller (Peripheral ID 26) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " PWM_set/clr ,Pulse Width Modulation Controller (Peripheral ID 25) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " TC2_set/clr ,Timer Counter 2 (Peripheral ID 24) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 23. " TC1_set/clr ,Timer Counter 1 (Peripheral ID 24) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " TC0_set/clr ,Timer Counter 0 (Peripheral ID 22) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " SSC_set/clr ,Synchronous Serial Controller (Peripheral ID 21) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " SPI_set/clr ,Serial Peripheral Interface (Peripheral ID 20) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " TWI1_set/clr ,Two-Wire Interface 1 (Peripheral ID 19) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " TWI0_set/clr ,Two-Wire Interface 0 (Peripheral ID 18) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " HSMCI_set/clr ,High Speed Multimedia Card Interface (Peripheral ID 17) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " USART3_set/clr ,USART 3 (Peripheral ID 16) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " USART2_set/clr ,USART 2 (Peripheral ID 15) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " USART1_set/clr ,USART 1 (Peripheral ID 14) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " USART0_set/clr ,USART 0 (Peripheral ID 13) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " PIOC_set/clr ,Parallel I/O Controller C (Peripheral ID 12) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " PIOB_set/clr ,Parallel I/O Controller B (Peripheral ID 11) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " PIOA_set/clr ,Parallel I/O Controller A (Peripheral ID 10) Clock Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " SMC_set/clr ,Static Memory Controller (Peripheral ID 9) Clock Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " UART_set/clr ,Universal Asynchronous Receiver Transmitter (Peripheral ID 8) Clock Status" "Disabled,Enabled"
|
|
endif
|
|
sif (!cpuis("ATSAM4E*"))
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "CKGR_UCKR,PMC UTMI Clock Configuration Register"
|
|
bitfld.long 0x00 20.--23. " UPLLCOUNT , UTMI PLL Start-up Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " UPLLEN , UTMI PLL Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "CKGR_MOR,PMC Clock Generator Main Oscillator Register"
|
|
bitfld.long 0x00 25. " CFDEN ,Clock Failure Detector Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " MOSCSEL ,Main Oscillator Selection" "Main On-Chip RC,Main Crystal"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " KEY ,Password"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MOSCXTST ,Main Crystal Oscillator Start-up Time"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " MOSCRCF ,Main On-Chip RC Oscillator Frequency Selection" "4 MHz,8 MHz,12 MHz,?..."
|
|
bitfld.long 0x00 3. " MOSCRCEN ,Main On-Chip RC Oscillator Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("AT91SAM3A*")&&!cpuis("AT91SAM3X4C")&&!cpuis("AT91SAM3X4E")&&!cpuis("AT91SAM3X8C")&&!cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 2. " WAITMODE ,Wait Mode Command" "No effect,Wait"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " MOSCXTBY ,Main Crystal Oscillator Bypass" "No effect,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MOSCXTEN ,Main Crystal Oscillator Enable" "Disabled,Enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CKGR_MCFR,PMC Clock Generator Main Clock Frequency Register"
|
|
sif (cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 20. " RCMEAS ,RC Oscillator Frequency Measure" "No effect,Restart"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16. " MAINRDY ,Main Clock Ready" "Not ready,Ready"
|
|
hexmask.long.word 0x00 0.--15. 1. " MAINF ,Main Clock Frequency"
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "CKGR_PLLAR,PMC Clock Generator PLL A Register"
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 29. " ONE ,Must Be Set to 1" "0,1"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x00 16.--26. 1. " MULA ,PLL A Multiplier"
|
|
textline " "
|
|
sif (!cpuis("AT91SAM3A*")&&!cpuis("AT91SAM3X4C")&&!cpuis("AT91SAM3X4E")&&!cpuis("AT91SAM3X8C")&&!cpuis("AT91SAM3X8E")&&!cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 14.--15. " STMODE ,Start Mode" "Fast Startup,,Normal Startup,?..."
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x00 8.--13. 1. " PLLACOUNT ,PLL A Counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIVA ,Divider A"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "PMC_MCKR,PMC Master Clock Register"
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x0 12. " PLLADIV2 ,PLLA Divisor by 2" "Clock,Clock/2"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0 4.--6. " PRES ,Processor Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,Clock/3"
|
|
bitfld.long 0x0 0.--1. " CSS ,Master Clock Source Selection" "Slow,Main,PLL A,UPLL"
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4E*"))
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "PMC_USB,PMC USB Clock Register"
|
|
bitfld.long 0x00 8.--11. " USBDIV ,Divider for USB Clock" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
sif (!cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0. " USBS ,USB Input Clock Selection" "PLLA,PLLB"
|
|
endif
|
|
endif
|
|
sif (cpuis("ATSAM4E*"))
|
|
group.long 0x40++0xF
|
|
line.long 0x0 "PMC_PCK0,PMC Programmable Clock 0 Register"
|
|
bitfld.long 0x0 4.--6. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
bitfld.long 0x0 0.--2. " CSS ,Master Clock Selection" "Slow,Main,PLL A,,Master,?..."
|
|
line.long 0x4 "PMC_PCK1,PMC Programmable Clock 1 Register"
|
|
bitfld.long 0x4 4.--6. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
bitfld.long 0x4 0.--2. " CSS ,Master Clock Selection" "Slow,Main,PLL A,,Master,?..."
|
|
line.long 0x8 "PMC_PCK2,PMC Programmable Clock 2 Register"
|
|
bitfld.long 0x8 4.--6. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
bitfld.long 0x8 0.--2. " CSS ,Master Clock Selection" "Slow,Main,PLL A,,Master,?..."
|
|
line.long 0xC "PMC_PCK3,PMC Programmable Clock 3 Register"
|
|
bitfld.long 0xC 4.--6. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
bitfld.long 0xC 0.--2. " CSS ,Master Clock Selection" "Slow,Main,PLL A,,Master,?..."
|
|
else
|
|
group.long 0x40++0xF
|
|
line.long 0x0 "PMC_PCK0,PMC Programmable Clock 0 Register"
|
|
bitfld.long 0x0 4.--6. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
bitfld.long 0x0 0.--2. " CSS ,Master Clock Selection" "Slow,Main,PLL A,UPLL,Master,Master,Master,Master"
|
|
line.long 0x4 "PMC_PCK1,PMC Programmable Clock 1 Register"
|
|
bitfld.long 0x4 4.--6. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
bitfld.long 0x4 0.--2. " CSS ,Master Clock Selection" "Slow,Main,PLL A,UPLL,Master,Master,Master,Master"
|
|
line.long 0x8 "PMC_PCK2,PMC Programmable Clock 2 Register"
|
|
bitfld.long 0x8 4.--6. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
bitfld.long 0x8 0.--2. " CSS ,Master Clock Selection" "Slow,Main,PLL A,UPLL,Master,Master,Master,Master"
|
|
line.long 0xC "PMC_PCK3,PMC Programmable Clock 3 Register"
|
|
bitfld.long 0xC 4.--6. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..."
|
|
bitfld.long 0xC 0.--2. " CSS ,Master Clock Selection" "Slow,Main,PLL A,UPLL,Master,Master,Master,Master"
|
|
endif
|
|
group.long 0x6c++3
|
|
line.long 0x00 "PMC_IMR,Interrupt Enable\Mask Register"
|
|
setclrfld.long 0x00 18. -0xc 18. -0x8 18. " CFDEV_set/clr ,Clock Failure Detector Event" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0xc 17. -0x8 17. " MOSCRCS_set/clr ,Main On-Chip RC Oscillator Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0xc 16. -0x8 16. " MOSCSELS_set/clr ,Main Oscillator Selection Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0xc 10. -0x8 10. " PCKRDY2_set/clr ,Programmable Clock Ready 2 Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0xc 9. -0x8 9. " PCKRDY1_set/clr ,Programmable Clock Ready 1 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0xc 8. -0x8 8. " PCKRDY0_set/clr ,Programmable Clock Ready 0 Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("AT91SAM3A*")&&!cpuis("AT91SAM3X4C")&&!cpuis("AT91SAM3X4E")&&!cpuis("AT91SAM3X8C")&&!cpuis("AT91SAM3X8E")&&!cpuis("ATSAM4E*"))
|
|
setclrfld.long 0x00 7. -0xc 7. -0x8 7. " OSCSELS_set/clr ,Slow Clock Oscillator Selection" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("ATSAM4E*"))
|
|
setclrfld.long 0x00 6. -0xc 6. -0x8 6. " LOCKU_set/clr ,UTMI PLL Lock Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 3. -0xc 3. -0x8 3. " MCKRDY_set/clr ,Master Clock Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0xc 1. -0x8 1. " LOCKA_set/clr ,PLL A Lock Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0xc 0. -0x8 0. " MOSCXTS_set/clr ,Main Oscillator Status Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x68++0x3
|
|
hide.long 0x00 "PMC_SR,PMC Status Register"
|
|
in
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "PMC_FSMR,PMC Fast Startup Mode Register"
|
|
sif (cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 21.--22. " FLPM ,Flash Low Power Mode" "FLASH_STANDBY,FLASH_DEEP_POWERDOWN,FLASH_IDLE,?..."
|
|
bitfld.long 0x00 20. " LPM ,Low Power Mode" "Idle,Wait"
|
|
else
|
|
bitfld.long 0x00 20. " LPM ,Low Power Mode" "Idle,Wait"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18. " USBAL ,USB Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RTCAL ,RTC Alarm Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " RTTAL ,RTT Alarm Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " FSTT15 ,Fast Startup Input Enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " FSTT14 ,Fast Startup Input Enable 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FSTT13 ,Fast Startup Input Enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " FSTT12 ,Fast Startup Input Enable 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " FSTT11 ,Fast Startup Input Enable 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSTT10 ,Fast Startup Input Enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " FSTT9 ,Fast Startup Input Enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FSTT8 ,Fast Startup Input Enable 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FSTT7 ,Fast Startup Input Enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FSTT6 ,Fast Startup Input Enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " FSTT5 ,Fast Startup Input Enable 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " FSTT4 ,Fast Startup Input Enable 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FSTT3 ,Fast Startup Input Enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FSTT2 ,Fast Startup Input Enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FSTT1 ,Fast Startup Input Enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FSTT0 ,Fast Startup Input Enable 0" "Disabled,Enabled"
|
|
group.long 0x74++0x3
|
|
line.long 0x00 "PMC_FSPR,PMC Fast Startup Polarity Register"
|
|
bitfld.long 0x00 15. " FSTP15 ,Fast Startup Input Polarity 15" "Low,High"
|
|
bitfld.long 0x00 14. " FSTP14 ,Fast Startup Input Polarity 14" "Low,High"
|
|
bitfld.long 0x00 13. " FSTP13 ,Fast Startup Input Polarity 13" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSTP12 ,Fast Startup Input Polarity 12" "Low,High"
|
|
bitfld.long 0x00 11. " FSTP11 ,Fast Startup Input Polarity 11" "Low,High"
|
|
bitfld.long 0x00 10. " FSTP10 ,Fast Startup Input Polarity 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FSTP9 ,Fast Startup Input Polarity 9" "Low,High"
|
|
bitfld.long 0x00 8. " FSTP8 ,Fast Startup Input Polarity 8" "Low,High"
|
|
bitfld.long 0x00 7. " FSTP7 ,Fast Startup Input Polarity 7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FSTP6 ,Fast Startup Input Polarity 6" "Low,High"
|
|
bitfld.long 0x00 5. " FSTP5 ,Fast Startup Input Polarity 5" "Low,High"
|
|
bitfld.long 0x00 4. " FSTP4 ,Fast Startup Input Polarity 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FSTP3 ,Fast Startup Input Polarity 3" "Low,High"
|
|
bitfld.long 0x00 2. " FSTP2 ,Fast Startup Input Polarity 2" "Low,High"
|
|
bitfld.long 0x00 1. " FSTP1 ,Fast Startup Input Polarity 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FSTP0 ,Fast Startup Input Polarity 0" "Low,High"
|
|
wgroup.long 0x78++0x3
|
|
line.long 0x00 "PMC_FOCR,PMC Fault Output Clear Register"
|
|
bitfld.long 0x00 0. " FOCLR ,Fault Output Clear" "No effect,Clear"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "PMC_WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PMC_WPSR,Write Protect Status Register"
|
|
in
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4E*"))
|
|
group.long 0x108++0x3
|
|
line.long 0x00 "PMC_PCSR1,PMC Peripheral Clock Status Register 1"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " CAN1_set/clr ,CAN Controller 1(Peripheral 44)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " CAN0_set/clr ,CAN Controller 0(Peripheral 43)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " EMAC_set/clr ,Ethernet MAC(Peripheral 42)" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TRNG_set/clr ,True Random Number Generator(Peripheral 41)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " UOTGHS_set/clr ,USB OTG High Speed(Peripheral 40)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " DMAC_set/clr ,DMA Controller(Peripheral 39)" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " DACC_set/clr ,DAC Controller(Peripheral 38)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " ADC_set/clr ,ADC Controller(Peripheral 37)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " PWM_set/clr ,Pulse Width Modulation Controller(Peripheral 36)" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " TC8_set/clr ,Timer Counter 8 (Peripheral 35)" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " TC7_set/clr ,Timer Counter 7 (Peripheral 34)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TC6_set/clr ,Timer Counter 6 (Peripheral 33)" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " TC5_set/clr ,Timer Counter 5 (Peripheral 32)" "Disabled,Enabled"
|
|
elif (cpuis("ATSAM4E*"))
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " UART1_set/clr ,UART1 (Peripheral 45)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " EMAC_set/clr ,EMAC(Peripheral 44)" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " AES_set/clr ,AES(Peripheral 39)" "Disabled,Enabled"
|
|
sif (cpu()=="ATSAM4E8E"||cpu()=="ATSAM4E16E")
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " CAN1_set/clr ,CAN1(Peripheral 38)" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " CAN0_set/clr ,CAN0(Peripheral 37)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " PWM_set/clr ,Pulse Width Modulation Controller(Peripheral 36)" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " UDP_set/clr ,USB DEVICE (Peripheral 35)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " ARM_set/clr ,FPU signals: FPIXC FPOFC FPUFC FPIOC FPDZC FPIDC FPIXC (Peripheral 34)" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " ACC_set/clr ,Analog Comparator (Peripheral 33)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DACC_set/clr ,Digital to Analog Converter (Peripheral 32)" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " UDP_set/clr ,USB Device Port (Peripheral 34)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " ACC_set/clr ,Analog Comparator (Peripheral 33)" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " CRCCU_set/clr ,CRC Calculation Unit (Peripheral 32)" "Disabled,Enabled"
|
|
endif
|
|
sif (!cpuis("ATSAM4E*"))
|
|
group.long 0x10C++0x3
|
|
line.long 0x00 "PMC_PCR,PMC Peripheral Control Register"
|
|
bitfld.long 0x00 28. " EN ,Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " DIV ,Divisor Value" "MCK,MCK/2,MCK/4,?..."
|
|
bitfld.long 0x00 12. " CMD ,Command" "Read mode,Write mode"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " PID ,Peripheral ID"
|
|
endif
|
|
endif
|
|
sif (cpuis("ATSAM4E*"))
|
|
group.long 0x110++0x3
|
|
line.long 0x00 "PMC_OCR,PMC Oscillator Calibration Register"
|
|
bitfld.long 0x00 23. " SEL12 ,Selection of RC Oscillator Calibration bits for 12 Mhz" "Flash memory,Written in CAL12"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CAL12 ,RC Oscillator Calibration bits for 12 Mhz"
|
|
bitfld.long 0x00 15. " SEL8 ,Selection of RC Oscillator Calibration bits for 8 Mhz" "Flash memory,Written in CAL8"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " CAL8 ,RC Oscillator Calibration bits for 8 Mhz"
|
|
bitfld.long 0x00 7. " SEL4 ,Selection of RC Oscillator Calibration bits for 4 Mhz" "Flash memory,Written in CAL4"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CAL4 ,RC Oscillator Calibration bits for 4 Mhz"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "CHIPID (Chip Identifier)"
|
|
base ad:0x400E0940
|
|
width 13.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "CHIPID_CIDR,Chip ID Register"
|
|
bitfld.long 0x00 31. " EXT ,Extension flag" "Not implemented,Implemented"
|
|
bitfld.long 0x00 28.--30. " NVPTYP ,Nonvolatile program memory type" "ROM,Romless/flash,Embedded flash,ROM & embedded flash,SRAM emulating ROM,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 20.--27. 1. " ARCH ,Architecture identifier"
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 16.--19. " SRAMSIZ ,Internal SRAM size" "48-KB,1-KB,2-KB,6-KB,24-KB,4-KB,80-KB,160-KB,8-KB,16-KB,32-KB,64-KB,128-KB,256-KB,96-KB,512-KB"
|
|
elif ((cpuis("ATSAM4S*"))||(cpuis("ATSAMV7*"))||(cpuis("ATSAME70*")))
|
|
bitfld.long 0x00 16.--19. " SRAMSIZ ,Internal SRAM size" "48-KB,192-KB,384-KB,6-KB,24-KB,4-KB,80-KB,160-KB,8-KB,16-KB,32-KB,64-KB,128-KB,256-KB,96-KB,512-KB"
|
|
else
|
|
bitfld.long 0x00 16.--19. " SRAMSIZ ,Internal SRAM size" "48-KB,1-KB,2-KB,6-KB,112-KB,4-KB,80-KB,160-KB,8-KB,16-KB,32-KB,64-KB,128-KB,256-KB,96-KB,512-KB"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " NVPSIZ2 ,Second nonvolatile program memory size" "Disabled,8-KB,16-KB,32-KB,,64-KB,,128-KB,,256-KB,512-KB,,1-MB,,2-MB,?..."
|
|
sif ((cpuis("ATSAM4S*"))||(cpuis("ATSAMV7*"))||(cpuis("ATSAME70*")))
|
|
bitfld.long 0x00 8.--11. " NVPSIZ ,Nonvolatile program memory size" "Disabled,8-KB,16-KB,32-KB,,64-KB,,128-KB,160-KB,256-KB,512-KB,,1-MB,,2-MB,?..."
|
|
else
|
|
bitfld.long 0x00 8.--11. " NVPSIZ ,Nonvolatile program memory size" "Disabled,8-KB,16-KB,32-KB,,64-KB,,128-KB,,256-KB,512-KB,,1-MB,,2-MB,?..."
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
bitfld.long 0x00 5.--7. " EPROC ,Embedded processor" "ARM946ES,ARM7TDMI,Cortex-m3,ARM920T,ARM926EJS,Cortex-a5,Cortex-a5,?..."
|
|
hexmask.long.byte 0x00 0.--4. 1. " VERSION ,Device version"
|
|
elif (cpuis("AT91SAM3S*"))
|
|
bitfld.long 0x00 5.--7. " EPROC ,Embedded processor" "ARM946ES,ARM7TDMI,Cortex-m3,ARM920T,ARM926EJS,?..."
|
|
hexmask.long.byte 0x00 0.--4. 1. " VERSION ,Device version"
|
|
elif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3N*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 5.--7. " EPROC ,Embedded processor" ",ARM946ES,ARM7TDMI,Cortex-m3,ARM920T,ARM926EJS,Cortex-a5,?..."
|
|
hexmask.long.byte 0x00 0.--4. 1. " VERSION ,Device version"
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 5.--7. " EPROC ,Embedded processor" ",ARM946ES,ARM7TDMI,Cortex-m3,ARM920T,ARM926EJS,Cortex-a5,Cortex-m4"
|
|
hexmask.long.byte 0x00 0.--4. 1. " VERSION ,Device version"
|
|
elif ((cpuis("ATSAM4S*"))||(cpuis("ATSAMV70*"))||(cpuis("ATSAME70*")))
|
|
bitfld.long 0x00 5.--7. " EPROC ,Embedded processor" "Cortex-m7,ARM946ES,ARM7TDMI,Cortex-m3,ARM920T,ARM926EJS,Cortex-a5,Cortex-m4"
|
|
hexmask.long.byte 0x00 0.--4. 1. " VERSION ,Device version"
|
|
elif (cpuis("ATSAMV71*"))
|
|
bitfld.long 0x00 5.--7. " EPROC ,Embedded processor" "Cortex-m7,ARM946ES,ARM7TDMI,Cortex-m3,ARM920T,ARM926EJS,Cortex-a5,Cortex-m4"
|
|
bitfld.long 0x00 0.--4. " VERSION ,Device version" "MRLA,MRLB,Version 2,Version 3,Version 4,Version 5,Version 6,Version 7,Version 8,Version 9,Version 10,Version 11,Version 12,Version 13,Version 14,Version 15,Version 16,Version 17,Version 18,Version 19,Version 20,Version 21,Version 22,Version 23,Version 24,Version 25,Version 26,Version 27,Version 28,Version 29,Version 30,Version 31"
|
|
else
|
|
bitfld.long 0x00 5.--7. " EPROC ,Embedded processor" ",ARM946E-S,ARM7TDMI,Cortex-m3,ARM920T,ARM926EJ-S,?..."
|
|
bitfld.long 0x00 0.--4. " VERSION ,Device version" "Version 0,Version 1,Version 2,Version 3,Version 4,Version 5,Version 6,Version 7,Version 8,Version 9,Version 10,Version 11,Version 12,Version 13,Version 14,Version 15,Version 16,Version 17,Version 18,Version 19,Version 20,Version 21,Version 22,Version 23,Version 24,Version 25,Version 26,Version 27,Version 28,Version 29,Version 30,Version 31"
|
|
endif
|
|
sif (cpuis("ATSAM4LS*")||cpuis("ATSAM4LC*"))
|
|
line.long 0x04 "EXID,Extension Register"
|
|
bitfld.long 0x04 24.--26. " PACKAGE ,Package type" "24-pin,32-pin,48-pin,64-pin,100-pin,144-pin,?..."
|
|
bitfld.long 0x04 3. " LCD ,LCD option" "Not implemented,Implemented"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*"))
|
|
bitfld.long 0x04 2. " USBFULL ,USB configuration" "Device-only,Device and host"
|
|
elif (cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x04 2. " USBFULL ,USB configuration" "Device-only,?..."
|
|
endif
|
|
bitfld.long 0x04 1. " USB ,USB option" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x04 0. " AES ,AES option" "Not implemented,Implemented"
|
|
else
|
|
line.long 0x04 "CHIPID_EXID,Chip ID Extension Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "SSC (Synchronous Serial Controller)"
|
|
base ad:0x40004000
|
|
width 13.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,SSC Control Register"
|
|
bitfld.long 0x00 15. " SWRST ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 9. " TXDIS ,Transmit disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXEN ,Transmit enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXDIS ,Receive disable" "No effect,Disabled"
|
|
newline
|
|
bitfld.long 0x00 0. " RXEN ,Receive enable" "No effect,Enabled"
|
|
sif cpuis("ATSAM4S*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")
|
|
if ((per.l(ad:0+0xE4)&0x01)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CMR,SSC Clock Mode Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DIV ,Clock divider"
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "RCMR,SSC Receive Clock Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PERIOD ,Receive period divider selection"
|
|
hexmask.long.byte 0x00 16.--23. 1. " STTDLY ,Receive start delay"
|
|
bitfld.long 0x00 12. " STOP ,Receive stop selection" "Completed,Compare 1"
|
|
bitfld.long 0x00 8.--11. " START ,Receive start selection" "Continuous,Transmit start,Low,High,Falling,Rising,Level change,Any edge,Compare 0,?..."
|
|
newline
|
|
bitfld.long 0x00 6.--7. " CKG ,Receive clock gating selection" "No gating,Low,High,?..."
|
|
bitfld.long 0x00 5. " CKI ,Receive clock inversion (data inputs/frame sync)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 2.--4. " CKO ,Receive clock output mode selection" "No clock,Continuous,During transfers,?..."
|
|
bitfld.long 0x00 0.--1. " CKS ,Receive clock selection" "Divided,TK,RK,?..."
|
|
line.long 0x04 "RFMR,SSC Receive Frame Mode Register"
|
|
bitfld.long 0x04 28.--31. " FSLEN_EXT ,FSLEN field extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 24. " FSEDGE ,Frame sync edge detection" "Positive,Negative"
|
|
bitfld.long 0x04 20.--22. " FSOS ,Receive frame sync output selection" "No signal,Negative,Positive,Low,High,Toggled,?..."
|
|
bitfld.long 0x04 16.--19. " FSLEN ,Receive frame sync length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 8.--11. " DATNB ,Data number per frame" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
bitfld.long 0x04 7. " MSBF ,Most significant bit first" "LSB,MSB"
|
|
bitfld.long 0x04 5. " LOOP ,Loop mode" "Normal,Loop"
|
|
bitfld.long 0x04 0.--4. " DATLEN ,Data length" ",2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
line.long 0x08 "TCMR,SSC Transmit Clock Mode Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " PERIOD ,Transmit period divider selection"
|
|
hexmask.long.byte 0x08 16.--23. 1. " STTDLY ,Transmit start delay"
|
|
bitfld.long 0x08 8.--11. " START ,Transmit start selection" "Continuous,Receive start,Low,High,Falling,Rising,Level change,Any edge,?..."
|
|
bitfld.long 0x08 6.--7. " CKG ,Transmit clock gating selection" "No gating,Low,High,?..."
|
|
newline
|
|
bitfld.long 0x08 5. " CKI ,Transmit clock inversion (shifted out/sampled)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x08 2.--4. " CKO ,Transmit clock output mode selection" "No clock,Continuous,During transfers,?..."
|
|
bitfld.long 0x08 0.--1. " CKS ,Transmit clock selection" "Divided,RK,TK,?..."
|
|
line.long 0x0C "TFMR,SSC Transmit Frame Mode Register"
|
|
bitfld.long 0x0C 28.--31. " FSLEN_EXT ,FSLEN field extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 24. " FSEDGE ,Frame sync edge detection" "Positive,Negative"
|
|
bitfld.long 0x0C 23. " FSDEN ,Frame sync data enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20.--22. " FSOS ,Transmit frame sync output selection" "No signal,Negative,Positive,Low,High,Toggled,?..."
|
|
newline
|
|
bitfld.long 0x0C 16.--19. " FSLEN ,Transmit frame sync length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 8.--11. " DATNB ,Data number per frame" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
bitfld.long 0x0C 7. " MSBF ,Most significant bit first" "LSB,MSB"
|
|
bitfld.long 0x0C 5. " DATDEF ,Data default value" "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 0.--4. " DATLEN ,Data length" ",2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "CMR,SSC Clock Mode Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DIV ,Clock divider"
|
|
rgroup.long 0x10++0x0F
|
|
line.long 0x00 "RCMR,SSC Receive Clock Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PERIOD ,Receive period divider selection"
|
|
hexmask.long.byte 0x00 16.--23. 1. " STTDLY ,Receive start delay"
|
|
bitfld.long 0x00 12. " STOP ,Receive stop selection" "Completed,Compare 1"
|
|
bitfld.long 0x00 8.--11. " START ,Receive start selection" "Continuous,Transmit start,Low,High,Falling,Rising,Level change,Any edge,Compare 0,?..."
|
|
newline
|
|
bitfld.long 0x00 6.--7. " CKG ,Receive clock gating selection" "No gating,Low,High,?..."
|
|
bitfld.long 0x00 5. " CKI ,Receive clock inversion (data inputs/frame sync)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 2.--4. " CKO ,Receive clock output mode selection" "No clock,Continuous,During transfers,?..."
|
|
bitfld.long 0x00 0.--1. " CKS ,Receive clock selection" "Divided,TK,RK,?..."
|
|
line.long 0x04 "RFMR,SSC Receive Frame Mode Register"
|
|
bitfld.long 0x04 28.--31. " FSLEN_EXT ,FSLEN field extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 24. " FSEDGE ,Frame sync edge detection" "Positive,Negative"
|
|
bitfld.long 0x04 20.--22. " FSOS ,Receive frame sync output selection" "No signal,Negative,Positive,Low,High,Toggled,?..."
|
|
bitfld.long 0x04 16.--19. " FSLEN ,Receive frame sync length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 8.--11. " DATNB ,Data number per frame" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
bitfld.long 0x04 7. " MSBF ,Most significant bit first" "LSB,MSB"
|
|
bitfld.long 0x04 5. " LOOP ,Loop mode" "Normal,Loop"
|
|
bitfld.long 0x04 0.--4. " DATLEN ,Data length" ",2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
line.long 0x08 "TCMR,SSC Transmit Clock Mode Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " PERIOD ,Transmit period divider selection"
|
|
hexmask.long.byte 0x08 16.--23. 1. " STTDLY ,Transmit start delay"
|
|
bitfld.long 0x08 8.--11. " START ,Transmit start selection" "Continuous,Receive start,Low,High,Falling,Rising,Level change,Any edge,?..."
|
|
bitfld.long 0x08 6.--7. " CKG ,Transmit clock gating selection" "No gating,Low,High,?..."
|
|
newline
|
|
bitfld.long 0x08 5. " CKI ,Transmit clock inversion (shifted out/sampled)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x08 2.--4. " CKO ,Transmit clock output mode selection" "No clock,Continuous,During transfers,?..."
|
|
bitfld.long 0x08 0.--1. " CKS ,Transmit clock selection" "Divided,RK,TK,?..."
|
|
line.long 0x0C "TFMR,SSC Transmit Frame Mode Register"
|
|
bitfld.long 0x0C 28.--31. " FSLEN_EXT ,FSLEN field extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 24. " FSEDGE ,Frame sync edge detection" "Positive,Negative"
|
|
bitfld.long 0x0C 23. " FSDEN ,Frame sync data enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20.--22. " FSOS ,Transmit frame sync output selection" "No signal,Negative,Positive,Low,High,Toggled,?..."
|
|
newline
|
|
bitfld.long 0x0C 16.--19. " FSLEN ,Transmit frame sync length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 8.--11. " DATNB ,Data number per frame" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
bitfld.long 0x0C 7. " MSBF ,Most significant bit first" "LSB,MSB"
|
|
bitfld.long 0x0C 5. " DATDEF ,Data default value" "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 0.--4. " DATLEN ,Data length" ",2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CMR,SSC Clock Mode Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DIV ,Clock divider"
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "RCMR,SSC Receive Clock Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PERIOD ,Receive period divider selection"
|
|
hexmask.long.byte 0x00 16.--23. 1. " STTDLY ,Receive start delay"
|
|
bitfld.long 0x00 12. " STOP ,Receive stop selection" "Completed,Compare 1"
|
|
bitfld.long 0x00 8.--11. " START ,Receive start selection" "Continuous,Transmit start,Low,High,Falling,Rising,Level change,Any edge,Compare 0,?..."
|
|
newline
|
|
bitfld.long 0x00 6.--7. " CKG ,Receive clock gating selection" "No gating,RF Low,RF High,?..."
|
|
bitfld.long 0x00 5. " CKI ,Receive clock inversion (data inputs/frame sync)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 2.--4. " CKO ,Receive clock output mode selection" "No clock,Continuous,During transfers,?..."
|
|
bitfld.long 0x00 0.--1. " CKS ,Receive clock selection" "Divided,TK,RK,?..."
|
|
line.long 0x04 "RFMR,SSC Receive Frame Mode Register"
|
|
bitfld.long 0x04 28.--31. " FSLEN_EXT ,FSLEN field extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 24. " FSEDGE ,Frame sync edge detection" "Positive,Negative"
|
|
bitfld.long 0x04 20.--22. " FSOS ,Receive frame sync output selection" "No signal,Negative,Positive,Low,High,Toggled,?..."
|
|
bitfld.long 0x04 16.--19. " FSLEN ,Receive frame sync length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 8.--11. " DATNB ,Data number per frame" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
bitfld.long 0x04 7. " MSBF ,Most significant bit first" "LSB,MSB"
|
|
bitfld.long 0x04 5. " LOOP ,Loop mode" "Normal,Loop"
|
|
bitfld.long 0x04 0.--4. " DATLEN ,Data length" ",2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
line.long 0x08 "TCMR,SSC Transmit Clock Mode Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " PERIOD ,Transmit period divider selection"
|
|
hexmask.long.byte 0x08 16.--23. 1. " STTDLY ,Transmit start delay"
|
|
bitfld.long 0x08 8.--11. " START ,Transmit start selection" "Continuous,Receive start,Low,High,Falling,Rising,Level change,Any edge,?..."
|
|
bitfld.long 0x08 6.--7. " CKG ,Transmit clock gating selection" "No gating,Low,High,?..."
|
|
newline
|
|
bitfld.long 0x08 5. " CKI ,Transmit clock inversion (shifted out/sampled)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x08 2.--4. " CKO ,Transmit clock output mode selection" "No clock,Continuous,During transfers,?..."
|
|
bitfld.long 0x08 0.--1. " CKS ,Transmit clock selection" "Divided,RK,TK,?..."
|
|
line.long 0x0C "TFMR,SSC Transmit Frame Mode Register"
|
|
bitfld.long 0x0C 28.--31. " FSLEN_EXT ,FSLEN field extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 24. " FSEDGE ,Frame sync edge detection" "Positive,Negative"
|
|
bitfld.long 0x0C 23. " FSDEN ,Frame sync data enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20.--22. " FSOS ,Transmit frame sync output selection" "No signal,Negative,Positive,Low,High,Toggled,?..."
|
|
newline
|
|
bitfld.long 0x0C 16.--19. " FSLEN ,Transmit frame sync length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 8.--11. " DATNB ,Data number per frame" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
bitfld.long 0x0C 7. " MSBF ,Most significant bit first" "LSB,MSB"
|
|
bitfld.long 0x0C 5. " DATDEF ,Data default value" "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 0.--4. " DATLEN ,Data length" ",2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
endif
|
|
newline
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "RHR,SSC Receive Holding Register"
|
|
in
|
|
newline
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "THR,SSC Transmit Holding Register"
|
|
newline
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "RSHR,SSC Receive Synchronization Holding Register"
|
|
in
|
|
newline
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TSHR,SSC Transmit Synchronization Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TSDAT ,Transmit synchronization data"
|
|
sif cpuis("ATSAM4S*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")
|
|
if ((per.l(ad:0+0xE4)&0x01)==0x00)
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "RC0R,SSC Receive Compare 0 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CP0 ,Receive compare data 0"
|
|
line.long 0x04 "RC1R,SSC Receive Compare 1 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CP1 ,Receive compare data 1"
|
|
else
|
|
rgroup.long 0x38++0x07
|
|
line.long 0x00 "RC0R,SSC Receive Compare 0 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CP0 ,Receive compare data 0"
|
|
line.long 0x04 "RC1R,SSC Receive Compare 1 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CP1 ,Receive compare data 1"
|
|
endif
|
|
else
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "RC0R,SSC Receive Compare 0 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CP0 ,Receive compare data 0"
|
|
line.long 0x04 "RC1R,SSC Receive Compare 1 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CP1 ,Receive compare data 1"
|
|
endif
|
|
newline
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "SR,SSC Status Register"
|
|
in
|
|
newline
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "IMR_SET/CLR,SSC Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " RXSYN ,Rx sync interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TXSYN ,Tx sync interrupt" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " CP1 ,Compare 1 interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " CP0 ,Compare 0 interrupt" "Masked,Unmasked"
|
|
newline
|
|
sif !cpuis("AT91SAM3A*")&&!cpuis("AT91SAM3X4C")&&!cpuis("AT91SAM3X4E")&&!cpuis("AT91SAM3X8C")&&!cpuis("AT91SAM3X8E")&&!cpuis("ATSAMV7*")&&!cpuis("ATSAMS7*")&&!cpuis("ATSAME70*")
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " RXBUFF ,Receive buffer full interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ENDRX ,Reception end interrupt" "Masked,Unmasked"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRUN ,Receive overrun interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RXRDY ,Receive ready interrupt" "Masked,Unmasked"
|
|
newline
|
|
sif !cpuis("AT91SAM3A*")&&!cpuis("AT91SAM3X4C")&&!cpuis("AT91SAM3X4E")&&!cpuis("AT91SAM3X8C")&&!cpuis("AT91SAM3X8E")&&!cpuis("ATSAMV7*")&&!cpuis("ATSAMS7*")&&!cpuis("ATSAME70*")
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " TXBUFE ,Transmit buffer empty interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " ENDTX ,Transmission end interrupt" "Masked,Unmasked"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXEMPTY ,Transmit empty interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " TXRDY ,Transmit ready interrupt" "Masked,Unmasked"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,SSC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write protect enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,SSC Write Protect Status Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "PIO (Parallel Input/Output)"
|
|
tree "Port A"
|
|
base ad:0x400E0E00
|
|
width 13.
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PIO_PSRA,PIO Controller PIO Status Register A"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,PIO29 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,PIO28 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,PIO27 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,PIO26 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,PIO25 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,PIO24 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,PIO23 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,PIO22 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,PIO21 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,PIO20 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,PIO19 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,PIO18 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,PIO17 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,PIO16 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,PIO15 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,PIO14 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,PIO13 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO12 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,PIO11 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,PIO10 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,PIO9 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,PIO8 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,PIO7 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,PIO6 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO5 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO4 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO3 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO2 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO1 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO0 Status" "Peripheral,PIO"
|
|
else
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,PIO29 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,PIO28 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,PIO27 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,PIO26 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,PIO25 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,PIO24 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,PIO23 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,PIO22 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,PIO21 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,PIO20 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,PIO19 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,PIO18 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,PIO17 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,PIO16 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,PIO15 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,PIO14 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,PIO13 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO12 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,PIO11 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,PIO10 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,PIO9 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,PIO8 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,PIO7 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,PIO6 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO5 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO4 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO3 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO2 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO1 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO0 Status" "Peripheral,PIO"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PIO_OSRA,PIO Controller Output Status Register A"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,PIO29 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,PIO28 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,PIO27 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,PIO26 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,PIO25 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,PIO24 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,PIO23 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,PIO22 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,PIO21 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,PIO20 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,PIO19 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,PIO18 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,PIO17 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,PIO16 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,PIO15 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,PIO14 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,PIO13 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO12 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,PIO11 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,PIO10 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,PIO9 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,PIO8 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,PIO7 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,PIO6 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO5 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO4 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO3 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO2 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO1 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO0 Status" "Peripheral,PIO"
|
|
else
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,PIO29 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,PIO28 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,PIO27 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,PIO26 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,PIO25 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,PIO24 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,PIO23 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,PIO22 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,PIO21 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,PIO20 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,PIO19 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,PIO18 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,PIO17 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,PIO16 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,PIO15 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,PIO14 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,PIO13 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO12 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,PIO11 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,PIO10 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,PIO9 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,PIO8 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,PIO7 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,PIO6 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO5 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO4 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO3 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO2 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO1 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO0 Status" "Peripheral,PIO"
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PIO_IFSRA,PIO Controller Input Filter Status Register A"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,PIO29 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,PIO28 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,PIO27 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,PIO26 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,PIO25 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,PIO24 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,PIO23 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,PIO22 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,PIO21 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,PIO20 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,PIO19 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,PIO18 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,PIO17 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,PIO16 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,PIO15 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,PIO14 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,PIO13 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO12 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,PIO11 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,PIO10 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,PIO9 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,PIO8 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,PIO7 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,PIO6 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO5 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO4 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO3 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO2 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO1 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO0 Status" "Peripheral,PIO"
|
|
else
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,PIO29 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,PIO28 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,PIO27 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,PIO26 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,PIO25 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,PIO24 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,PIO23 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,PIO22 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,PIO21 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,PIO20 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,PIO19 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,PIO18 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,PIO17 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,PIO16 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,PIO15 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,PIO14 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,PIO13 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO12 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,PIO11 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,PIO10 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,PIO9 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,PIO8 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,PIO7 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,PIO6 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO5 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO4 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO3 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO2 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO1 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO0 Status" "Peripheral,PIO"
|
|
endif
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PIO_ODSRA,PIO Controller Output Data Status Register A"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Data Status 29" "Low,High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Data Status 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Data Status 25" "Low,High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Data Status 23" "Low,High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Data Status 21" "Low,High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Data Status 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Data Status 17" "Low,High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Data Status 15" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
else
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Data Status 29" "Low,High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Data Status 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Data Status 25" "Low,High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Data Status 23" "Low,High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Data Status 21" "Low,High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Data Status 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Data Status 17" "Low,High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Data Status 15" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
endif
|
|
rgroup.long 0x3c++0x03
|
|
line.long 0x00 "PIO_PDSRA,PIO Controller Pin Data Status Register A"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 29. " P29 ,Output Data Status 29" "Low,High"
|
|
bitfld.long 0x00 28. " P28 ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Output Data Status 27" "Low,High"
|
|
bitfld.long 0x00 26. " P26 ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Output Data Status 25" "Low,High"
|
|
bitfld.long 0x00 24. " P24 ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Output Data Status 23" "Low,High"
|
|
bitfld.long 0x00 22. " P22 ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Output Data Status 21" "Low,High"
|
|
bitfld.long 0x00 20. " P20 ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Output Data Status 19" "Low,High"
|
|
bitfld.long 0x00 18. " P18 ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Output Data Status 17" "Low,High"
|
|
bitfld.long 0x00 16. " P16 ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Output Data Status 15" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Data Status 13" "Low,High"
|
|
bitfld.long 0x00 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x00 10. " P10 ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x00 8. " P8 ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Data Status 7" "Low,High"
|
|
bitfld.long 0x00 6. " P6 ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x00 4. " P4 ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x00 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Data Status 1" "Low,High"
|
|
bitfld.long 0x00 0. " P0 ,Output Data Status 0" "Low,High"
|
|
else
|
|
bitfld.long 0x00 29. " P29 ,Output Data Status 29" "Low,High"
|
|
bitfld.long 0x00 28. " P28 ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Output Data Status 27" "Low,High"
|
|
bitfld.long 0x00 26. " P26 ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Output Data Status 25" "Low,High"
|
|
bitfld.long 0x00 24. " P24 ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Output Data Status 23" "Low,High"
|
|
bitfld.long 0x00 22. " P22 ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Output Data Status 21" "Low,High"
|
|
bitfld.long 0x00 20. " P20 ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Output Data Status 19" "Low,High"
|
|
bitfld.long 0x00 18. " P18 ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Output Data Status 17" "Low,High"
|
|
bitfld.long 0x00 16. " P16 ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Output Data Status 15" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Data Status 13" "Low,High"
|
|
bitfld.long 0x00 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x00 10. " P10 ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x00 8. " P8 ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Data Status 7" "Low,High"
|
|
bitfld.long 0x00 6. " P6 ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x00 4. " P4 ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x00 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Data Status 1" "Low,High"
|
|
bitfld.long 0x00 0. " P0 ,Output Data Status 0" "Low,High"
|
|
endif
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PIO_IMRA,PIO Controller Interrupt Mask Register A"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Input Change Interrupt Data Status 29" "Low,High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Input Change Interrupt Data Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Input Change Interrupt Data Status 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Input Change Interrupt Data Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Input Change Interrupt Data Status 25" "Low,High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Input Change Interrupt Data Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Input Change Interrupt Data Status 23" "Low,High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Input Change Interrupt Data Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Input Change Interrupt Data Status 21" "Low,High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Input Change Interrupt Data Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Input Change Interrupt Data Status 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Input Change Interrupt Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Input Change Interrupt Data Status 17" "Low,High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Input Change Interrupt Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Input Change Interrupt Data Status 15" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Input Change Interrupt Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Input Change Interrupt Data Status 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Change Interrupt Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Change Interrupt Data Status 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Change Interrupt Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Change Interrupt Data Status 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Change Interrupt Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Change Interrupt Data Status 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Change Interrupt Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Change Interrupt Data Status 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Change Interrupt Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Change Interrupt Data Status 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Change Interrupt Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Change Interrupt Data Status 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Change Interrupt Data Status 0" "Low,High"
|
|
else
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Input Change Interrupt Data Status 29" "Low,High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Input Change Interrupt Data Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Input Change Interrupt Data Status 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Input Change Interrupt Data Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Input Change Interrupt Data Status 25" "Low,High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Input Change Interrupt Data Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Input Change Interrupt Data Status 23" "Low,High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Input Change Interrupt Data Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Input Change Interrupt Data Status 21" "Low,High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Input Change Interrupt Data Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Input Change Interrupt Data Status 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Input Change Interrupt Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Input Change Interrupt Data Status 17" "Low,High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Input Change Interrupt Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Input Change Interrupt Data Status 15" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Input Change Interrupt Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Input Change Interrupt Data Status 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Change Interrupt Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Change Interrupt Data Status 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Change Interrupt Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Change Interrupt Data Status 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Change Interrupt Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Change Interrupt Data Status 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Change Interrupt Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Change Interrupt Data Status 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Change Interrupt Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Change Interrupt Data Status 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Change Interrupt Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Change Interrupt Data Status 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Change Interrupt Data Status 0" "Low,High"
|
|
endif
|
|
hgroup.long 0x4c++0x03
|
|
hide.long 0x00 "PIO_ISRA,PIO Controller Interrupt Status Register A"
|
|
in
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "PIO_MDSRA,PIO Multi-Driver Status Register A"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,The Multi Drive Status 29" "Low,High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,The Multi Drive Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,The Multi Drive Status 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,The Multi Drive Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,The Multi Drive Status 25" "Low,High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,The Multi Drive Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,The Multi Drive Status 23" "Low,High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,The Multi Drive Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,The Multi Drive Status 21" "Low,High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,The Multi Drive Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,The Multi Drive Status 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,The Multi Drive Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,The Multi Drive Status 17" "Low,High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,The Multi Drive Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,The Multi Drive Status 15" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,The Multi Drive Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,The Multi Drive Status 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,The Multi Drive Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,The Multi Drive Status 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,The Multi Drive Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,The Multi Drive Status 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,The Multi Drive Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,The Multi Drive Status 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,The Multi Drive Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,The Multi Drive Status 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,The Multi Drive Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,The Multi Drive Status 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,The Multi Drive Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,The Multi Drive Status 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,The Multi Drive Status 0" "Low,High"
|
|
else
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,The Multi Drive Status 29" "Low,High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,The Multi Drive Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,The Multi Drive Status 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,The Multi Drive Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,The Multi Drive Status 25" "Low,High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,The Multi Drive Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,The Multi Drive Status 23" "Low,High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,The Multi Drive Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,The Multi Drive Status 21" "Low,High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,The Multi Drive Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,The Multi Drive Status 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,The Multi Drive Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,The Multi Drive Status 17" "Low,High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,The Multi Drive Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,The Multi Drive Status 15" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,The Multi Drive Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,The Multi Drive Status 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,The Multi Drive Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,The Multi Drive Status 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,The Multi Drive Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,The Multi Drive Status 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,The Multi Drive Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,The Multi Drive Status 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,The Multi Drive Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,The Multi Drive Status 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,The Multi Drive Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,The Multi Drive Status 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,The Multi Drive Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,The Multi Drive Status 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,The Multi Drive Status 0" "Low,High"
|
|
endif
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PIO_PUSRA,PIO Pull Up Status Register A"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Pull Up resistor Status 29" "Low,High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Pull Up resistor Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Pull Up resistor Status 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Pull Up resistor Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Pull Up resistor Status 25" "Low,High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Pull Up resistor Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Pull Up resistor Status 23" "Low,High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Pull Up resistor Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Pull Up resistor Status 21" "Low,High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Pull Up resistor Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Pull Up resistor Status 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Pull Up resistor Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Pull Up resistor Status 17" "Low,High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Pull Up resistor Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Pull Up resistor Status 15" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Pull Up resistor Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Pull Up resistor Status 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Pull Up resistor Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Pull Up resistor Status 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Pull Up resistor Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Pull Up resistor Status 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Pull Up resistor Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Pull Up resistor Status 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Pull Up resistor Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Pull Up resistor Status 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Pull Up resistor Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Pull Up resistor Status 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Pull Up resistor Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Pull Up resistor Status 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Pull Up resistor Status 0" "Low,High"
|
|
else
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Pull Up resistor Status 29" "Low,High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Pull Up resistor Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Pull Up resistor Status 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Pull Up resistor Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Pull Up resistor Status 25" "Low,High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Pull Up resistor Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Pull Up resistor Status 23" "Low,High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Pull Up resistor Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Pull Up resistor Status 21" "Low,High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Pull Up resistor Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Pull Up resistor Status 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Pull Up resistor Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Pull Up resistor Status 17" "Low,High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Pull Up resistor Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Pull Up resistor Status 15" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Pull Up resistor Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Pull Up resistor Status 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Pull Up resistor Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Pull Up resistor Status 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Pull Up resistor Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Pull Up resistor Status 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Pull Up resistor Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Pull Up resistor Status 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Pull Up resistor Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Pull Up resistor Status 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Pull Up resistor Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Pull Up resistor Status 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Pull Up resistor Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Pull Up resistor Status 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Pull Up resistor Status 0" "Low,High"
|
|
endif
|
|
group.long 0x70++0x7
|
|
line.long 0x00 "PIO_ABCDSR1,PIO Peripheral ABCD Select Register 1"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 29. " P29 ,Assigns the I/O line Status 29" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 28. " P28 ,Assigns the I/O line Status 28" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Assigns the I/O line Status 27" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 26. " P26 ,Assigns the I/O line Status 26" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Assigns the I/O line Status 25" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 24. " P24 ,Assigns the I/O line Status 24" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Assigns the I/O line Status 23" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 22. " P22 ,Assigns the I/O line Status 22" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Assigns the I/O line Status 21" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 20. " P20 ,Assigns the I/O line Status 20" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Assigns the I/O line Status 19" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 18. " P18 ,Assigns the I/O line Status 18" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Assigns the I/O line Status 17" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 16. " P16 ,Assigns the I/O line Status 16" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Assigns the I/O line Status 15" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Assigns the I/O line Status 14" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Assigns the I/O line Status 13" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 12. " P12 ,Assigns the I/O line Status 12" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Assigns the I/O line Status 11" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 10. " P10 ,Assigns the I/O line Status 10" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Assigns the I/O line Status 9" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 8. " P8 ,Assigns the I/O line Status 8" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Assigns the I/O line Status 7" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 6. " P6 ,Assigns the I/O line Status 6" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Assigns the I/O line Status 5" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 4. " P4 ,Assigns the I/O line Status 4" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Assigns the I/O line Status 3" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 2. " P2 ,Assigns the I/O line Status 2" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Assigns the I/O line Status 1" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 0. " P0 ,Assigns the I/O line Status 0" "Peripheral A/C,Peripheral B/D"
|
|
else
|
|
bitfld.long 0x00 29. " P29 ,Assigns the I/O line Status 29" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 28. " P28 ,Assigns the I/O line Status 28" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Assigns the I/O line Status 27" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 26. " P26 ,Assigns the I/O line Status 26" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Assigns the I/O line Status 25" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 24. " P24 ,Assigns the I/O line Status 24" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Assigns the I/O line Status 23" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 22. " P22 ,Assigns the I/O line Status 22" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Assigns the I/O line Status 21" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 20. " P20 ,Assigns the I/O line Status 20" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Assigns the I/O line Status 19" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 18. " P18 ,Assigns the I/O line Status 18" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Assigns the I/O line Status 17" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 16. " P16 ,Assigns the I/O line Status 16" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Assigns the I/O line Status 15" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Assigns the I/O line Status 14" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Assigns the I/O line Status 13" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 12. " P12 ,Assigns the I/O line Status 12" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Assigns the I/O line Status 11" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 10. " P10 ,Assigns the I/O line Status 10" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Assigns the I/O line Status 9" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 8. " P8 ,Assigns the I/O line Status 8" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Assigns the I/O line Status 7" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 6. " P6 ,Assigns the I/O line Status 6" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Assigns the I/O line Status 5" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 4. " P4 ,Assigns the I/O line Status 4" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Assigns the I/O line Status 3" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 2. " P2 ,Assigns the I/O line Status 2" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Assigns the I/O line Status 1" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 0. " P0 ,Assigns the I/O line Status 0" "Peripheral A/C,Peripheral B/D"
|
|
endif
|
|
line.long 0x04 "PIO_ABCDSR2,PIO Peripheral ABCD Select Register 2"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x04 29. " P29 ,Assigns the I/O line Status 29" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 28. " P28 ,Assigns the I/O line Status 28" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 27. " P27 ,Assigns the I/O line Status 27" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 26. " P26 ,Assigns the I/O line Status 26" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 25. " P25 ,Assigns the I/O line Status 25" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 24. " P24 ,Assigns the I/O line Status 24" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 23. " P23 ,Assigns the I/O line Status 23" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 22. " P22 ,Assigns the I/O line Status 22" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 21. " P21 ,Assigns the I/O line Status 21" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 20. " P20 ,Assigns the I/O line Status 20" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 19. " P19 ,Assigns the I/O line Status 19" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 18. " P18 ,Assigns the I/O line Status 18" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 17. " P17 ,Assigns the I/O line Status 17" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 16. " P16 ,Assigns the I/O line Status 16" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 15. " P15 ,Assigns the I/O line Status 15" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 14. " P14 ,Assigns the I/O line Status 14" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 13. " P13 ,Assigns the I/O line Status 13" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 12. " P12 ,Assigns the I/O line Status 12" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 11. " P11 ,Assigns the I/O line Status 11" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 10. " P10 ,Assigns the I/O line Status 10" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 9. " P9 ,Assigns the I/O line Status 9" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 8. " P8 ,Assigns the I/O line Status 8" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 7. " P7 ,Assigns the I/O line Status 7" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 6. " P6 ,Assigns the I/O line Status 6" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 5. " P5 ,Assigns the I/O line Status 5" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 4. " P4 ,Assigns the I/O line Status 4" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 3. " P3 ,Assigns the I/O line Status 3" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 2. " P2 ,Assigns the I/O line Status 2" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 1. " P1 ,Assigns the I/O line Status 1" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 0. " P0 ,Assigns the I/O line Status 0" "Peripheral A/B,Peripheral C/D"
|
|
else
|
|
bitfld.long 0x04 29. " P29 ,Assigns the I/O line Status 29" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 28. " P28 ,Assigns the I/O line Status 28" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 27. " P27 ,Assigns the I/O line Status 27" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 26. " P26 ,Assigns the I/O line Status 26" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 25. " P25 ,Assigns the I/O line Status 25" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 24. " P24 ,Assigns the I/O line Status 24" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 23. " P23 ,Assigns the I/O line Status 23" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 22. " P22 ,Assigns the I/O line Status 22" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 21. " P21 ,Assigns the I/O line Status 21" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 20. " P20 ,Assigns the I/O line Status 20" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 19. " P19 ,Assigns the I/O line Status 19" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 18. " P18 ,Assigns the I/O line Status 18" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 17. " P17 ,Assigns the I/O line Status 17" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 16. " P16 ,Assigns the I/O line Status 16" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 15. " P15 ,Assigns the I/O line Status 15" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 14. " P14 ,Assigns the I/O line Status 14" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 13. " P13 ,Assigns the I/O line Status 13" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 12. " P12 ,Assigns the I/O line Status 12" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 11. " P11 ,Assigns the I/O line Status 11" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 10. " P10 ,Assigns the I/O line Status 10" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 9. " P9 ,Assigns the I/O line Status 9" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 8. " P8 ,Assigns the I/O line Status 8" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 7. " P7 ,Assigns the I/O line Status 7" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 6. " P6 ,Assigns the I/O line Status 6" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 5. " P5 ,Assigns the I/O line Status 5" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 4. " P4 ,Assigns the I/O line Status 4" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 3. " P3 ,Assigns the I/O line Status 3" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 2. " P2 ,Assigns the I/O line Status 2" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 1. " P1 ,Assigns the I/O line Status 1" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 0. " P0 ,Assigns the I/O line Status 0" "Peripheral A/B,Peripheral C/D"
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")&&!cpuis("AT91SAM3X*"))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "PIO_ABSRA,PIO Peripheral A B Status Register A"
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P31_set/clr ,Peripheral 31 A B Status" "RF,TIOB2"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " P30_set/clr ,Peripheral 30 A B Status" "TF,TIOA2"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " P29_set/clr ,Peripheral 29 A B Status" "RK,PWMH1"
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " P28_set/clr ,Peripheral 28 A B Status" "TK,PWMH0"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " P27_set/clr ,Peripheral 27 A B Status" "RD,PCK0"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " P26_set/clr ,Peripheral 26 A B Status" "TD,TCLK2"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " P25_set/clr ,Peripheral 25 A B Status" "TWCK1,SCK2"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " P24_set/clr ,Peripheral 24 A B Status" "TWD1,SCK1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23_set/clr ,Peripheral 23 A B Status" "RXD2,CTS1"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22_set/clr ,Peripheral 22 A B Status" "TXD2,RTS1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21_set/clr ,Peripheral 21 A B Status" "RXD1,PCK0"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20_set/clr ,Peripheral 20 A B Status" "TXD1,PWMH3"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19_set/clr ,Peripheral 19 A B Status" "RXD0,NPCS3"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18_set/clr ,Peripheral 18 A B Status" "TXD0,PWMFI2"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17_set/clr ,Peripheral 17 A B Status" "SCK0,ADTRG"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16_set/clr ,Peripheral 16 A B Status" "NPCS0,NCS1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_set/clr ,Peripheral 15 A B Status" "SPCK,PWMH2"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Peripheral 14 A B Status" "MOSI,?..."
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Peripheral 13 A B Status" "MISO,?..."
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Peripheral 12 A B Status" "UTXD,PWMFI1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Peripheral 11 A B Status" "URXD,PWMFI0"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Peripheral 10 A B Status" "TWCK0,PWML3"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Peripheral 9 A B Status" "TWD0,PWML2"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Peripheral 8 A B Status" "MCDA3,PWML1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Peripheral 7 A B Status" "MCDA2,PWML0"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Peripheral 6 A B Status" "MCDA1,PWMH2"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Peripheral 5 A B Status" "MCDA0,PWMH1"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Peripheral 4 A B Status" "MCCDA,PWMH0"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Peripheral 3 A B Status" "MCCK,PCK1"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Peripheral 2 A B Status" "TCLK0,AD12BTRG"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr ,Peripheral 1 A B Status" "TIOA0,NPCS2"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Peripheral 0 A B Status" "TIOB0,NPCS1"
|
|
endif
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "PIO_IFDGSR,PIO Glitch or Debouncing Input Filter Selection Status Register"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " P29_set/clr ,Glitch or Debouncing Filter Selection Status 29" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " P28_set/clr ,Glitch or Debouncing Filter Selection Status 28" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " P27_set/clr ,Glitch or Debouncing Filter Selection Status 27" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " P26_set/clr ,Glitch or Debouncing Filter Selection Status 26" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " P25_set/clr ,Glitch or Debouncing Filter Selection Status 25" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " P24_set/clr ,Glitch or Debouncing Filter Selection Status 24" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23_set/clr ,Glitch or Debouncing Filter Selection Status 23" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22_set/clr ,Glitch or Debouncing Filter Selection Status 22" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21_set/clr ,Glitch or Debouncing Filter Selection Status 21" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20_set/clr ,Glitch or Debouncing Filter Selection Status 20" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19_set/clr ,Glitch or Debouncing Filter Selection Status 19" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18_set/clr ,Glitch or Debouncing Filter Selection Status 18" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17_set/clr ,Glitch or Debouncing Filter Selection Status 17" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16_set/clr ,Glitch or Debouncing Filter Selection Status 16" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_set/clr ,Glitch or Debouncing Filter Selection Status 15" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Glitch or Debouncing Filter Selection Status 14" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Glitch or Debouncing Filter Selection Status 13" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Glitch or Debouncing Filter Selection Status 12" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Glitch or Debouncing Filter Selection Status 11" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Glitch or Debouncing Filter Selection Status 10" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Glitch or Debouncing Filter Selection Status 9" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Glitch or Debouncing Filter Selection Status 8" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Glitch or Debouncing Filter Selection Status 7" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Glitch or Debouncing Filter Selection Status 6" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Glitch or Debouncing Filter Selection Status 5" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Glitch or Debouncing Filter Selection Status 4" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Glitch or Debouncing Filter Selection Status 3" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Glitch or Debouncing Filter Selection Status 2" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr1 ,Glitch or Debouncing Filter Selection Status 1" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Glitch or Debouncing Filter Selection Status 0" "Glitch,Debouncing"
|
|
else
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " P29_set/clr ,Glitch or Debouncing Filter Selection Status 29" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " P28_set/clr ,Glitch or Debouncing Filter Selection Status 28" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " P27_set/clr ,Glitch or Debouncing Filter Selection Status 27" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " P26_set/clr ,Glitch or Debouncing Filter Selection Status 26" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " P25_set/clr ,Glitch or Debouncing Filter Selection Status 25" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " P24_set/clr ,Glitch or Debouncing Filter Selection Status 24" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23_set/clr ,Glitch or Debouncing Filter Selection Status 23" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22_set/clr ,Glitch or Debouncing Filter Selection Status 22" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21_set/clr ,Glitch or Debouncing Filter Selection Status 21" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20_set/clr ,Glitch or Debouncing Filter Selection Status 20" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19_set/clr ,Glitch or Debouncing Filter Selection Status 19" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18_set/clr ,Glitch or Debouncing Filter Selection Status 18" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17_set/clr ,Glitch or Debouncing Filter Selection Status 17" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16_set/clr ,Glitch or Debouncing Filter Selection Status 16" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_set/clr ,Glitch or Debouncing Filter Selection Status 15" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Glitch or Debouncing Filter Selection Status 14" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Glitch or Debouncing Filter Selection Status 13" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Glitch or Debouncing Filter Selection Status 12" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Glitch or Debouncing Filter Selection Status 11" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Glitch or Debouncing Filter Selection Status 10" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Glitch or Debouncing Filter Selection Status 9" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Glitch or Debouncing Filter Selection Status 8" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Glitch or Debouncing Filter Selection Status 7" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Glitch or Debouncing Filter Selection Status 6" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Glitch or Debouncing Filter Selection Status 5" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Glitch or Debouncing Filter Selection Status 4" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Glitch or Debouncing Filter Selection Status 3" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Glitch or Debouncing Filter Selection Status 2" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr1 ,Glitch or Debouncing Filter Selection Status 1" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Glitch or Debouncing Filter Selection Status 0" "Glitch,Debouncing"
|
|
endif
|
|
group.long 0x8c++0x3
|
|
line.long 0x00 "PIO_SCDR,PIO Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow Clock Divider Selection for Debouncing"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "PIO_OWSRA,PIO Output Write Status Register A"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Write Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Write Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Write Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Write Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Write Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Write Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Write Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Write Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Write Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Write Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Write Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Write Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Write Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Write Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Write Status 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Write Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Write Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Write Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Write Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Write Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Write Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Write Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Write Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Write Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Write Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Write Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Write Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Write Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Output Write Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Write Status 0" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Write Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Write Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Write Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Write Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Write Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Write Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Write Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Write Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Write Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Write Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Write Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Write Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Write Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Write Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Write Status 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Write Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Write Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Write Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Write Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Write Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Write Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Write Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Write Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Write Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Write Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Write Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Write Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Write Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Output Write Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Write Status 0" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xB8++0x3
|
|
line.long 0x00 "PIO_AIMMR,Additional Interrupt Modes Mask Register"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Peripheral CD Status 29" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Peripheral CD Status 28" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Peripheral CD Status 27" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Peripheral CD Status 26" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Peripheral CD Status 25" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Peripheral CD Status 24" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Peripheral CD Status 23" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Peripheral CD Status 22" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Peripheral CD Status 21" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Peripheral CD Status 20" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Peripheral CD Status 19" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Peripheral CD Status 18" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Peripheral CD Status 17" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Peripheral CD Status 16" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Peripheral CD Status 15" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Peripheral CD Status 14" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Peripheral CD Status 13" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Peripheral CD Status 12" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Peripheral CD Status 11" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Peripheral CD Status 10" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Peripheral CD Status 9" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Peripheral CD Status 8" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Peripheral CD Status 7" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Peripheral CD Status 6" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Peripheral CD Status 5" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Peripheral CD Status 4" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Peripheral CD Status 3" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Peripheral CD Status 2" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Peripheral CD Status 1" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Peripheral CD Status 0" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
else
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Peripheral CD Status 29" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Peripheral CD Status 28" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Peripheral CD Status 27" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Peripheral CD Status 26" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Peripheral CD Status 25" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Peripheral CD Status 24" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Peripheral CD Status 23" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Peripheral CD Status 22" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Peripheral CD Status 21" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Peripheral CD Status 20" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Peripheral CD Status 19" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Peripheral CD Status 18" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Peripheral CD Status 17" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Peripheral CD Status 16" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Peripheral CD Status 15" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Peripheral CD Status 14" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Peripheral CD Status 13" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Peripheral CD Status 12" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Peripheral CD Status 11" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Peripheral CD Status 10" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Peripheral CD Status 9" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Peripheral CD Status 8" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Peripheral CD Status 7" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Peripheral CD Status 6" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Peripheral CD Status 5" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Peripheral CD Status 4" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Peripheral CD Status 3" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Peripheral CD Status 2" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Peripheral CD Status 1" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Peripheral CD Status 0" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
endif
|
|
group.long 0xC8++0x3
|
|
line.long 0x00 "PIO_ELSR,Edge/Level Status Register"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Edge/Level Interrupt source selection 29" "Edge,Level"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Edge/Level Interrupt source selection 28" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Edge/Level Interrupt source selection 27" "Edge,Level"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Edge/Level Interrupt source selection 26" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Edge/Level Interrupt source selection 25" "Edge,Level"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Edge/Level Interrupt source selection 24" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Edge/Level Interrupt source selection 23" "Edge,Level"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Edge/Level Interrupt source selection 22" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Edge/Level Interrupt source selection 21" "Edge,Level"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Edge/Level Interrupt source selection 20" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Edge/Level Interrupt source selection 19" "Edge,Level"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Edge/Level Interrupt source selection 18" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Edge/Level Interrupt source selection 17" "Edge,Level"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Edge/Level Interrupt source selection 16" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Edge/Level Interrupt source selection 15" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Edge/Level Interrupt source selection 14" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Edge/Level Interrupt source selection 13" "Edge,Level"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Edge/Level Interrupt source selection 12" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Edge/Level Interrupt source selection 11" "Edge,Level"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Edge/Level Interrupt source selection 10" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Edge/Level Interrupt source selection 9" "Edge,Level"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Edge/Level Interrupt source selection 8" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Edge/Level Interrupt source selection 7" "Edge,Level"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Edge/Level Interrupt source selection 6" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Edge/Level Interrupt source selection 5" "Edge,Level"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Edge/Level Interrupt source selection 4" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Edge/Level Interrupt source selection 3" "Edge,Level"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Edge/Level Interrupt source selection 2" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Edge/Level Interrupt source selection 1" "Edge,Level"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection 0" "Edge,Level"
|
|
else
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Edge/Level Interrupt source selection 29" "Edge,Level"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Edge/Level Interrupt source selection 28" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Edge/Level Interrupt source selection 27" "Edge,Level"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Edge/Level Interrupt source selection 26" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Edge/Level Interrupt source selection 25" "Edge,Level"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Edge/Level Interrupt source selection 24" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Edge/Level Interrupt source selection 23" "Edge,Level"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Edge/Level Interrupt source selection 22" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Edge/Level Interrupt source selection 21" "Edge,Level"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Edge/Level Interrupt source selection 20" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Edge/Level Interrupt source selection 19" "Edge,Level"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Edge/Level Interrupt source selection 18" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Edge/Level Interrupt source selection 17" "Edge,Level"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Edge/Level Interrupt source selection 16" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Edge/Level Interrupt source selection 15" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Edge/Level Interrupt source selection 14" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Edge/Level Interrupt source selection 13" "Edge,Level"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Edge/Level Interrupt source selection 12" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Edge/Level Interrupt source selection 11" "Edge,Level"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Edge/Level Interrupt source selection 10" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Edge/Level Interrupt source selection 9" "Edge,Level"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Edge/Level Interrupt source selection 8" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Edge/Level Interrupt source selection 7" "Edge,Level"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Edge/Level Interrupt source selection 6" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Edge/Level Interrupt source selection 5" "Edge,Level"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Edge/Level Interrupt source selection 4" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Edge/Level Interrupt source selection 3" "Edge,Level"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Edge/Level Interrupt source selection 2" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Edge/Level Interrupt source selection 1" "Edge,Level"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection 0" "Edge,Level"
|
|
endif
|
|
group.long 0xd8++0x3
|
|
line.long 0x00 "PIO_FRLHSR,Fall/Rise - Low/High Status Register"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Edge/Level Interrupt source selection 29 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Edge/Level Interrupt source selection 28 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Edge/Level Interrupt source selection 27 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Edge/Level Interrupt source selection 26 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Edge/Level Interrupt source selection 25 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Edge/Level Interrupt source selection 24 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Edge/Level Interrupt source selection 23 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Edge/Level Interrupt source selection 22 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Edge/Level Interrupt source selection 21 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Edge/Level Interrupt source selection 20 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Edge/Level Interrupt source selection 19 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Edge/Level Interrupt source selection 18 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Edge/Level Interrupt source selection 17 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Edge/Level Interrupt source selection 16 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Edge/Level Interrupt source selection 15 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Edge/Level Interrupt source selection 14 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Edge/Level Interrupt source selection 13 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Edge/Level Interrupt source selection 12 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Edge/Level Interrupt source selection 11 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Edge/Level Interrupt source selection 10 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Edge/Level Interrupt source selection 9 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Edge/Level Interrupt source selection 8 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Edge/Level Interrupt source selection 7 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Edge/Level Interrupt source selection 6 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Edge/Level Interrupt source selection 5 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Edge/Level Interrupt source selection 4 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Edge/Level Interrupt source selection 3 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Edge/Level Interrupt source selection 2 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Edge/Level Interrupt source selection 1 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection 0 (Edge/Level)" "Falling/Low,Rising/High"
|
|
else
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Edge/Level Interrupt source selection 29 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Edge/Level Interrupt source selection 28 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Edge/Level Interrupt source selection 27 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Edge/Level Interrupt source selection 26 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Edge/Level Interrupt source selection 25 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Edge/Level Interrupt source selection 24 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Edge/Level Interrupt source selection 23 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Edge/Level Interrupt source selection 22 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Edge/Level Interrupt source selection 21 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Edge/Level Interrupt source selection 20 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Edge/Level Interrupt source selection 19 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Edge/Level Interrupt source selection 18 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Edge/Level Interrupt source selection 17 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Edge/Level Interrupt source selection 16 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Edge/Level Interrupt source selection 15 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Edge/Level Interrupt source selection 14 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Edge/Level Interrupt source selection 13 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Edge/Level Interrupt source selection 12 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Edge/Level Interrupt source selection 11 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Edge/Level Interrupt source selection 10 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Edge/Level Interrupt source selection 9 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Edge/Level Interrupt source selection 8 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Edge/Level Interrupt source selection 7 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Edge/Level Interrupt source selection 6 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Edge/Level Interrupt source selection 5 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Edge/Level Interrupt source selection 4 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Edge/Level Interrupt source selection 3 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Edge/Level Interrupt source selection 2 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Edge/Level Interrupt source selection 1 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection 0 (Edge/Level)" "Falling/Low,Rising/High"
|
|
endif
|
|
rgroup.long 0xe0++0x3
|
|
line.long 0x00 "PIO_LOCKSR,Lock Status Register"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 29. " P29 ,I/O line 29 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 28. " P28 ,I/O line 28 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,I/O line 27 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " P26 ,I/O line 26 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,I/O line 25 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 24. " P24 ,I/O line 24 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,I/O line 23 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 22. " P22 ,I/O line 22 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,I/O line 21 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 20. " P20 ,I/O line 20 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,I/O line 19 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 18. " P18 ,I/O line 18 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,I/O line 17 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 16. " P16 ,I/O line 16 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,I/O line 15 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,I/O line 14 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,I/O line 13 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " P12 ,I/O line 12 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,I/O line 11 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " P10 ,I/O line 10 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,I/O line 9 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " P8 ,I/O line 8 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,I/O line 7 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " P6 ,I/O line 6 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,I/O line 5 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " P4 ,I/O line 4 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,I/O line 3 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " P2 ,I/O line 2 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,I/O line 1 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " P0 ,I/O line 0 Lock Status" "Not locked,Locked"
|
|
else
|
|
bitfld.long 0x00 29. " P29 ,I/O line 29 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 28. " P28 ,I/O line 28 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,I/O line 27 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " P26 ,I/O line 26 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,I/O line 25 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 24. " P24 ,I/O line 24 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,I/O line 23 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 22. " P22 ,I/O line 22 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,I/O line 21 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 20. " P20 ,I/O line 20 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,I/O line 19 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 18. " P18 ,I/O line 18 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,I/O line 17 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 16. " P16 ,I/O line 16 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,I/O line 15 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,I/O line 14 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,I/O line 13 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " P12 ,I/O line 12 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,I/O line 11 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " P10 ,I/O line 10 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,I/O line 9 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " P8 ,I/O line 8 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,I/O line 7 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " P6 ,I/O line 6 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,I/O line 5 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " P4 ,I/O line 4 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,I/O line 3 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " P2 ,I/O line 2 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,I/O line 1 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " P0 ,I/O line 0 Lock Status" "Not locked,Locked"
|
|
endif
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect Enable"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PIO_WPSR,Write Protect Violation Status"
|
|
in
|
|
width 13.
|
|
sif (!cpuis("AT91SAM3A*")&&!cpuis("AT91SAM3X4C")&&!cpuis("AT91SAM3X4E")&&!cpuis("AT91SAM3X8C")&&!cpuis("AT91SAM3X8E"))
|
|
group.long 0xF50++0x3
|
|
line.long 0x00 "PIO_PCMR,PIO Parallel Capture Mode Register"
|
|
bitfld.long 0x00 11. " FRSTS ,Parallel Capture Mode First Sample" "Even index,Odd index"
|
|
bitfld.long 0x00 10. " HALFS ,Parallel Capture Mode Half Sampling" "All data,One time out of two"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ALWYS ,Parallel Capture Mode Always Sampling" "No,Yes"
|
|
bitfld.long 0x00 4.--5. " DSIZE ,Parallel Capture Mode Data Size" "8 bit,16 bit,32 bit,32 bit"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PCEN ,Parallel Capture Mode Enable" "Disabled,Enabled"
|
|
rgroup.long 0xF5C++0x3
|
|
line.long 0x00 "PIO_PCIMR,PIO Parallel Capture Interrupt Mask Register"
|
|
bitfld.long 0x00 3. " RXBUFF ,Reception Buffer Full Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " ENDRX ,End of Reception Transfer Interrupt Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OVRE ,Parallel Capture Mode Overrun Error Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " DRDY ,Parallel Capture Mode Data Ready Interrupt Mask" "Not masked,Masked"
|
|
group.long 0xF60++0x3
|
|
line.long 0x00 "PIO_PCISR,PIO Parallel Capture Interrupt Status Register"
|
|
setclrfld.long 0x00 3. -0x0C 3. -0x08 3. " RXBUFF_set/clr ,Reception Buffer Full Interrupt Status" "Inactive,Active"
|
|
setclrfld.long 0x00 2. -0x0C 2. -0x08 2. " ENDRX_set/clr ,End of Reception Transfer Interrupt Status" "Inactive,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x0C 1. -0x08 1. " OVRE_set/clr ,Parallel Capture Mode Overrun Error Interrupt Status" "No error,Error"
|
|
setclrfld.long 0x00 0. -0x0C 0. -0x08 0. " DRDY_set/clr ,Parallel Capture Mode Data Ready Interrupt Status" "Not ready,Ready"
|
|
if ((d.l(ad:0x0+0xf50)&0x30)==0x00)
|
|
rgroup.long 0xF64++0x3
|
|
line.long 0x00 "PIO_PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
hexmask.long.byte 0x00 0.--8. 1. " RDATA ,Parallel Capture Mode Reception Data"
|
|
elif ((d.l(ad:0x0+0xf50)&0x30)==0x10)
|
|
rgroup.long 0xF64++0x3
|
|
line.long 0x00 "PIO_PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
hexmask.long.word 0x00 0.--16. 1. " RDATA ,Parallel Capture Mode Reception Data"
|
|
else
|
|
rgroup.long 0xF64++0x3
|
|
line.long 0x00 "PIO_PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
endif
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "Port B"
|
|
base ad:0x400E1000
|
|
width 13.
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PIO_PSRB,PIO Controller PIO Status Register B"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,PIO31 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,PIO30 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,PIO29 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,PIO28 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,PIO27 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,PIO26 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,PIO25 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,PIO24 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,PIO23 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,PIO22 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,PIO21 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,PIO20 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,PIO19 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,PIO18 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,PIO17 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,PIO16 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,PIO15 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,PIO14 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,PIO13 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO12 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,PIO11 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,PIO10 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,PIO9 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,PIO8 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,PIO7 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,PIO6 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO5 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO4 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO3 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO2 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO1 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO0 Status" "Peripheral,PIO"
|
|
else
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,PIO31 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,PIO30 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,PIO29 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,PIO28 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,PIO27 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,PIO26 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,PIO25 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,PIO24 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,PIO23 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,PIO22 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,PIO21 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,PIO20 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,PIO19 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,PIO18 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,PIO17 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,PIO16 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,PIO15 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,PIO14 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,PIO13 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO12 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,PIO11 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,PIO10 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,PIO9 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,PIO8 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,PIO7 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,PIO6 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO5 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO4 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO3 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO2 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO1 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO0 Status" "Peripheral,PIO"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PIO_OSRB,PIO Controller Output Status Register B"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,PIO31 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,PIO30 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,PIO29 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,PIO28 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,PIO27 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,PIO26 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,PIO25 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,PIO24 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,PIO23 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,PIO22 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,PIO21 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,PIO20 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,PIO19 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,PIO18 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,PIO17 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,PIO16 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,PIO15 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,PIO14 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,PIO13 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO12 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,PIO11 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,PIO10 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,PIO9 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,PIO8 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,PIO7 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,PIO6 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO5 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO4 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO3 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO2 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO1 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO0 Status" "Peripheral,PIO"
|
|
else
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,PIO31 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,PIO30 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,PIO29 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,PIO28 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,PIO27 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,PIO26 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,PIO25 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,PIO24 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,PIO23 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,PIO22 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,PIO21 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,PIO20 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,PIO19 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,PIO18 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,PIO17 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,PIO16 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,PIO15 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,PIO14 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,PIO13 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO12 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,PIO11 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,PIO10 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,PIO9 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,PIO8 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,PIO7 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,PIO6 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO5 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO4 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO3 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO2 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO1 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO0 Status" "Peripheral,PIO"
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PIO_IFSRB,PIO Controller Input Filter Status Register B"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,PIO31 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,PIO30 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,PIO29 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,PIO28 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,PIO27 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,PIO26 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,PIO25 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,PIO24 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,PIO23 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,PIO22 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,PIO21 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,PIO20 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,PIO19 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,PIO18 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,PIO17 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,PIO16 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,PIO15 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,PIO14 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,PIO13 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO12 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,PIO11 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,PIO10 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,PIO9 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,PIO8 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,PIO7 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,PIO6 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO5 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO4 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO3 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO2 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO1 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO0 Status" "Peripheral,PIO"
|
|
else
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,PIO31 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,PIO30 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,PIO29 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,PIO28 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,PIO27 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,PIO26 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,PIO25 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,PIO24 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,PIO23 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,PIO22 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,PIO21 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,PIO20 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,PIO19 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,PIO18 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,PIO17 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,PIO16 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,PIO15 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,PIO14 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,PIO13 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO12 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,PIO11 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,PIO10 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,PIO9 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,PIO8 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,PIO7 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,PIO6 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO5 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO4 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO3 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO2 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO1 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO0 Status" "Peripheral,PIO"
|
|
endif
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PIO_ODSRB,PIO Controller Output Data Status Register B"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Output Data Status 31" "Low,High"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Output Data Status 30" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Data Status 29" "Low,High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Data Status 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Data Status 25" "Low,High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Data Status 23" "Low,High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Data Status 21" "Low,High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Data Status 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Data Status 17" "Low,High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Data Status 15" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
else
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Output Data Status 31" "Low,High"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Output Data Status 30" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Data Status 29" "Low,High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Data Status 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Data Status 25" "Low,High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Data Status 23" "Low,High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Data Status 21" "Low,High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Data Status 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Data Status 17" "Low,High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Data Status 15" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
endif
|
|
rgroup.long 0x3c++0x03
|
|
line.long 0x00 "PIO_PDSRB,PIO Controller Pin Data Status Register B"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 31. " P31 ,Output Data Status 31" "Low,High"
|
|
bitfld.long 0x00 30. " P30 ,Output Data Status 30" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Output Data Status 29" "Low,High"
|
|
bitfld.long 0x00 28. " P28 ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Output Data Status 27" "Low,High"
|
|
bitfld.long 0x00 26. " P26 ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Output Data Status 25" "Low,High"
|
|
bitfld.long 0x00 24. " P24 ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Output Data Status 23" "Low,High"
|
|
bitfld.long 0x00 22. " P22 ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Output Data Status 21" "Low,High"
|
|
bitfld.long 0x00 20. " P20 ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Output Data Status 19" "Low,High"
|
|
bitfld.long 0x00 18. " P18 ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Output Data Status 17" "Low,High"
|
|
bitfld.long 0x00 16. " P16 ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Output Data Status 15" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Data Status 13" "Low,High"
|
|
bitfld.long 0x00 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x00 10. " P10 ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x00 8. " P8 ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Data Status 7" "Low,High"
|
|
bitfld.long 0x00 6. " P6 ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x00 4. " P4 ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x00 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Data Status 1" "Low,High"
|
|
bitfld.long 0x00 0. " P0 ,Output Data Status 0" "Low,High"
|
|
else
|
|
bitfld.long 0x00 31. " P31 ,Output Data Status 31" "Low,High"
|
|
bitfld.long 0x00 30. " P30 ,Output Data Status 30" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Output Data Status 29" "Low,High"
|
|
bitfld.long 0x00 28. " P28 ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Output Data Status 27" "Low,High"
|
|
bitfld.long 0x00 26. " P26 ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Output Data Status 25" "Low,High"
|
|
bitfld.long 0x00 24. " P24 ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Output Data Status 23" "Low,High"
|
|
bitfld.long 0x00 22. " P22 ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Output Data Status 21" "Low,High"
|
|
bitfld.long 0x00 20. " P20 ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Output Data Status 19" "Low,High"
|
|
bitfld.long 0x00 18. " P18 ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Output Data Status 17" "Low,High"
|
|
bitfld.long 0x00 16. " P16 ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Output Data Status 15" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Data Status 13" "Low,High"
|
|
bitfld.long 0x00 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x00 10. " P10 ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x00 8. " P8 ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Data Status 7" "Low,High"
|
|
bitfld.long 0x00 6. " P6 ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x00 4. " P4 ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x00 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Data Status 1" "Low,High"
|
|
bitfld.long 0x00 0. " P0 ,Output Data Status 0" "Low,High"
|
|
endif
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PIO_IMRB,PIO Controller Interrupt Mask Register B"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Input Change Interrupt Data Status 31" "Low,High"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Input Change Interrupt Data Status 30" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Input Change Interrupt Data Status 29" "Low,High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Input Change Interrupt Data Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Input Change Interrupt Data Status 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Input Change Interrupt Data Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Input Change Interrupt Data Status 25" "Low,High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Input Change Interrupt Data Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Input Change Interrupt Data Status 23" "Low,High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Input Change Interrupt Data Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Input Change Interrupt Data Status 21" "Low,High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Input Change Interrupt Data Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Input Change Interrupt Data Status 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Input Change Interrupt Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Input Change Interrupt Data Status 17" "Low,High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Input Change Interrupt Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Input Change Interrupt Data Status 15" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Input Change Interrupt Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Input Change Interrupt Data Status 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Change Interrupt Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Change Interrupt Data Status 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Change Interrupt Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Change Interrupt Data Status 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Change Interrupt Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Change Interrupt Data Status 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Change Interrupt Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Change Interrupt Data Status 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Change Interrupt Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Change Interrupt Data Status 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Change Interrupt Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Change Interrupt Data Status 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Change Interrupt Data Status 0" "Low,High"
|
|
else
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Input Change Interrupt Data Status 31" "Low,High"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Input Change Interrupt Data Status 30" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Input Change Interrupt Data Status 29" "Low,High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Input Change Interrupt Data Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Input Change Interrupt Data Status 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Input Change Interrupt Data Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Input Change Interrupt Data Status 25" "Low,High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Input Change Interrupt Data Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Input Change Interrupt Data Status 23" "Low,High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Input Change Interrupt Data Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Input Change Interrupt Data Status 21" "Low,High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Input Change Interrupt Data Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Input Change Interrupt Data Status 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Input Change Interrupt Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Input Change Interrupt Data Status 17" "Low,High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Input Change Interrupt Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Input Change Interrupt Data Status 15" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Input Change Interrupt Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Input Change Interrupt Data Status 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Change Interrupt Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Change Interrupt Data Status 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Change Interrupt Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Change Interrupt Data Status 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Change Interrupt Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Change Interrupt Data Status 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Change Interrupt Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Change Interrupt Data Status 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Change Interrupt Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Change Interrupt Data Status 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Change Interrupt Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Change Interrupt Data Status 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Change Interrupt Data Status 0" "Low,High"
|
|
endif
|
|
hgroup.long 0x4c++0x03
|
|
hide.long 0x00 "PIO_ISRB,PIO Controller Interrupt Status Register B"
|
|
in
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "PIO_MDSRB,PIO Multi-Driver Status Register B"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,The Multi Drive Status 31" "Low,High"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,The Multi Drive Status 30" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,The Multi Drive Status 29" "Low,High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,The Multi Drive Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,The Multi Drive Status 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,The Multi Drive Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,The Multi Drive Status 25" "Low,High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,The Multi Drive Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,The Multi Drive Status 23" "Low,High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,The Multi Drive Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,The Multi Drive Status 21" "Low,High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,The Multi Drive Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,The Multi Drive Status 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,The Multi Drive Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,The Multi Drive Status 17" "Low,High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,The Multi Drive Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,The Multi Drive Status 15" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,The Multi Drive Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,The Multi Drive Status 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,The Multi Drive Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,The Multi Drive Status 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,The Multi Drive Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,The Multi Drive Status 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,The Multi Drive Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,The Multi Drive Status 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,The Multi Drive Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,The Multi Drive Status 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,The Multi Drive Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,The Multi Drive Status 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,The Multi Drive Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,The Multi Drive Status 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,The Multi Drive Status 0" "Low,High"
|
|
else
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,The Multi Drive Status 31" "Low,High"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,The Multi Drive Status 30" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,The Multi Drive Status 29" "Low,High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,The Multi Drive Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,The Multi Drive Status 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,The Multi Drive Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,The Multi Drive Status 25" "Low,High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,The Multi Drive Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,The Multi Drive Status 23" "Low,High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,The Multi Drive Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,The Multi Drive Status 21" "Low,High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,The Multi Drive Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,The Multi Drive Status 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,The Multi Drive Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,The Multi Drive Status 17" "Low,High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,The Multi Drive Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,The Multi Drive Status 15" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,The Multi Drive Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,The Multi Drive Status 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,The Multi Drive Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,The Multi Drive Status 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,The Multi Drive Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,The Multi Drive Status 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,The Multi Drive Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,The Multi Drive Status 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,The Multi Drive Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,The Multi Drive Status 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,The Multi Drive Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,The Multi Drive Status 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,The Multi Drive Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,The Multi Drive Status 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,The Multi Drive Status 0" "Low,High"
|
|
endif
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PIO_PUSRB,PIO Pull Up Status Register B"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Pull Up resistor Status 31" "Low,High"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Pull Up resistor Status 30" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Pull Up resistor Status 29" "Low,High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Pull Up resistor Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Pull Up resistor Status 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Pull Up resistor Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Pull Up resistor Status 25" "Low,High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Pull Up resistor Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Pull Up resistor Status 23" "Low,High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Pull Up resistor Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Pull Up resistor Status 21" "Low,High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Pull Up resistor Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Pull Up resistor Status 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Pull Up resistor Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Pull Up resistor Status 17" "Low,High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Pull Up resistor Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Pull Up resistor Status 15" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Pull Up resistor Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Pull Up resistor Status 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Pull Up resistor Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Pull Up resistor Status 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Pull Up resistor Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Pull Up resistor Status 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Pull Up resistor Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Pull Up resistor Status 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Pull Up resistor Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Pull Up resistor Status 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Pull Up resistor Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Pull Up resistor Status 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Pull Up resistor Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Pull Up resistor Status 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Pull Up resistor Status 0" "Low,High"
|
|
else
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Pull Up resistor Status 31" "Low,High"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Pull Up resistor Status 30" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Pull Up resistor Status 29" "Low,High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Pull Up resistor Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Pull Up resistor Status 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Pull Up resistor Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Pull Up resistor Status 25" "Low,High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Pull Up resistor Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Pull Up resistor Status 23" "Low,High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Pull Up resistor Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Pull Up resistor Status 21" "Low,High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Pull Up resistor Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Pull Up resistor Status 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Pull Up resistor Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Pull Up resistor Status 17" "Low,High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Pull Up resistor Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Pull Up resistor Status 15" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Pull Up resistor Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Pull Up resistor Status 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Pull Up resistor Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Pull Up resistor Status 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Pull Up resistor Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Pull Up resistor Status 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Pull Up resistor Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Pull Up resistor Status 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Pull Up resistor Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Pull Up resistor Status 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Pull Up resistor Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Pull Up resistor Status 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Pull Up resistor Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Pull Up resistor Status 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Pull Up resistor Status 0" "Low,High"
|
|
endif
|
|
group.long 0x70++0x7
|
|
line.long 0x00 "PIO_ABCDSR1,PIO Peripheral ABCD Select Register 1"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 31. " P31 ,Assigns the I/O line Status 31" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 30. " P30 ,Assigns the I/O line Status 30" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Assigns the I/O line Status 29" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 28. " P28 ,Assigns the I/O line Status 28" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Assigns the I/O line Status 27" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 26. " P26 ,Assigns the I/O line Status 26" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Assigns the I/O line Status 25" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 24. " P24 ,Assigns the I/O line Status 24" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Assigns the I/O line Status 23" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 22. " P22 ,Assigns the I/O line Status 22" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Assigns the I/O line Status 21" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 20. " P20 ,Assigns the I/O line Status 20" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Assigns the I/O line Status 19" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 18. " P18 ,Assigns the I/O line Status 18" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Assigns the I/O line Status 17" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 16. " P16 ,Assigns the I/O line Status 16" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Assigns the I/O line Status 15" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Assigns the I/O line Status 14" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Assigns the I/O line Status 13" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 12. " P12 ,Assigns the I/O line Status 12" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Assigns the I/O line Status 11" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 10. " P10 ,Assigns the I/O line Status 10" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Assigns the I/O line Status 9" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 8. " P8 ,Assigns the I/O line Status 8" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Assigns the I/O line Status 7" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 6. " P6 ,Assigns the I/O line Status 6" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Assigns the I/O line Status 5" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 4. " P4 ,Assigns the I/O line Status 4" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Assigns the I/O line Status 3" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 2. " P2 ,Assigns the I/O line Status 2" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Assigns the I/O line Status 1" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 0. " P0 ,Assigns the I/O line Status 0" "Peripheral A/C,Peripheral B/D"
|
|
else
|
|
bitfld.long 0x00 31. " P31 ,Assigns the I/O line Status 31" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 30. " P30 ,Assigns the I/O line Status 30" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Assigns the I/O line Status 29" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 28. " P28 ,Assigns the I/O line Status 28" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Assigns the I/O line Status 27" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 26. " P26 ,Assigns the I/O line Status 26" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Assigns the I/O line Status 25" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 24. " P24 ,Assigns the I/O line Status 24" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Assigns the I/O line Status 23" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 22. " P22 ,Assigns the I/O line Status 22" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Assigns the I/O line Status 21" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 20. " P20 ,Assigns the I/O line Status 20" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Assigns the I/O line Status 19" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 18. " P18 ,Assigns the I/O line Status 18" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Assigns the I/O line Status 17" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 16. " P16 ,Assigns the I/O line Status 16" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Assigns the I/O line Status 15" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Assigns the I/O line Status 14" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Assigns the I/O line Status 13" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 12. " P12 ,Assigns the I/O line Status 12" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Assigns the I/O line Status 11" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 10. " P10 ,Assigns the I/O line Status 10" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Assigns the I/O line Status 9" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 8. " P8 ,Assigns the I/O line Status 8" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Assigns the I/O line Status 7" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 6. " P6 ,Assigns the I/O line Status 6" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Assigns the I/O line Status 5" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 4. " P4 ,Assigns the I/O line Status 4" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Assigns the I/O line Status 3" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 2. " P2 ,Assigns the I/O line Status 2" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Assigns the I/O line Status 1" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 0. " P0 ,Assigns the I/O line Status 0" "Peripheral A/C,Peripheral B/D"
|
|
endif
|
|
line.long 0x04 "PIO_ABCDSR2,PIO Peripheral ABCD Select Register 2"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x04 31. " P31 ,Assigns the I/O line Status 31" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 30. " P30 ,Assigns the I/O line Status 30" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 29. " P29 ,Assigns the I/O line Status 29" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 28. " P28 ,Assigns the I/O line Status 28" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 27. " P27 ,Assigns the I/O line Status 27" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 26. " P26 ,Assigns the I/O line Status 26" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 25. " P25 ,Assigns the I/O line Status 25" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 24. " P24 ,Assigns the I/O line Status 24" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 23. " P23 ,Assigns the I/O line Status 23" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 22. " P22 ,Assigns the I/O line Status 22" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 21. " P21 ,Assigns the I/O line Status 21" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 20. " P20 ,Assigns the I/O line Status 20" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 19. " P19 ,Assigns the I/O line Status 19" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 18. " P18 ,Assigns the I/O line Status 18" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 17. " P17 ,Assigns the I/O line Status 17" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 16. " P16 ,Assigns the I/O line Status 16" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 15. " P15 ,Assigns the I/O line Status 15" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 14. " P14 ,Assigns the I/O line Status 14" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 13. " P13 ,Assigns the I/O line Status 13" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 12. " P12 ,Assigns the I/O line Status 12" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 11. " P11 ,Assigns the I/O line Status 11" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 10. " P10 ,Assigns the I/O line Status 10" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 9. " P9 ,Assigns the I/O line Status 9" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 8. " P8 ,Assigns the I/O line Status 8" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 7. " P7 ,Assigns the I/O line Status 7" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 6. " P6 ,Assigns the I/O line Status 6" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 5. " P5 ,Assigns the I/O line Status 5" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 4. " P4 ,Assigns the I/O line Status 4" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 3. " P3 ,Assigns the I/O line Status 3" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 2. " P2 ,Assigns the I/O line Status 2" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 1. " P1 ,Assigns the I/O line Status 1" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 0. " P0 ,Assigns the I/O line Status 0" "Peripheral A/B,Peripheral C/D"
|
|
else
|
|
bitfld.long 0x04 31. " P31 ,Assigns the I/O line Status 31" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 30. " P30 ,Assigns the I/O line Status 30" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 29. " P29 ,Assigns the I/O line Status 29" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 28. " P28 ,Assigns the I/O line Status 28" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 27. " P27 ,Assigns the I/O line Status 27" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 26. " P26 ,Assigns the I/O line Status 26" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 25. " P25 ,Assigns the I/O line Status 25" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 24. " P24 ,Assigns the I/O line Status 24" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 23. " P23 ,Assigns the I/O line Status 23" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 22. " P22 ,Assigns the I/O line Status 22" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 21. " P21 ,Assigns the I/O line Status 21" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 20. " P20 ,Assigns the I/O line Status 20" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 19. " P19 ,Assigns the I/O line Status 19" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 18. " P18 ,Assigns the I/O line Status 18" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 17. " P17 ,Assigns the I/O line Status 17" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 16. " P16 ,Assigns the I/O line Status 16" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 15. " P15 ,Assigns the I/O line Status 15" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 14. " P14 ,Assigns the I/O line Status 14" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 13. " P13 ,Assigns the I/O line Status 13" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 12. " P12 ,Assigns the I/O line Status 12" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 11. " P11 ,Assigns the I/O line Status 11" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 10. " P10 ,Assigns the I/O line Status 10" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 9. " P9 ,Assigns the I/O line Status 9" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 8. " P8 ,Assigns the I/O line Status 8" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 7. " P7 ,Assigns the I/O line Status 7" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 6. " P6 ,Assigns the I/O line Status 6" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 5. " P5 ,Assigns the I/O line Status 5" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 4. " P4 ,Assigns the I/O line Status 4" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 3. " P3 ,Assigns the I/O line Status 3" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 2. " P2 ,Assigns the I/O line Status 2" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 1. " P1 ,Assigns the I/O line Status 1" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 0. " P0 ,Assigns the I/O line Status 0" "Peripheral A/B,Peripheral C/D"
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")&&!cpuis("AT91SAM3X*"))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "PIO_ABSRB,PIO Peripheral A B Status Register B"
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P31_set/clr ,Peripheral 31 A B Status" "D14,?..."
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " P30_set/clr ,Peripheral 30 A B Status" "D13,?..."
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " P29_set/clr ,Peripheral 29 A B Status" "D12,?..."
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " P28_set/clr ,Peripheral 28 A B Status" "D11,PWML3"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " P27_set/clr ,Peripheral 27 A B Status" "D10,PWML2"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " P26_set/clr ,Peripheral 26 A B Status" "D9,PWML1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " P25_set/clr ,Peripheral 25 A B Status" "D8,PWML0"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " P24_set/clr ,Peripheral 24 A B Status" "NANDRDY,PCK1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23_set/clr ,Peripheral 23 A B Status" "NWR0/NWE,PCK2"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22_set/clr ,Peripheral 22 A B Status" "A22/NANDCLE,CTS2"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21_set/clr ,Peripheral 21 A B Status" "A21/NANDALE,RTS2"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20_set/clr ,Peripheral 20 A B Status" "NCS0,PWML3"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19_set/clr ,Peripheral 19 A B Status" "NRD,PWML2"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18_set/clr ,Peripheral 18 A B Status" "NANDWE,PWML1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17_set/clr ,Peripheral 17 A B Status" "NANDOE,PWML0"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16_set/clr ,Peripheral 16 A B Status" "D7,PWMH3"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_set/clr ,Peripheral 15 A B Status" "D6,PWMH2"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Peripheral 14 A B Status" "D5,PWMH1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Peripheral 13 A B Status" "D4,PWMH0"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Peripheral 12 A B Status" "D3,RI0"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Peripheral 11 A B Status" "D2,DCD0"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Peripheral 10 A B Status" "D1,DSR0"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Peripheral 9 A B Status" "D0,DTR0"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Peripheral 8 A B Status" "CTS0,A1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Peripheral 7 A B Status" "RTS0,A0/NBS0"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Peripheral 6 A B Status" "TIOB1,D15"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Peripheral 5 A B Status" "TIOA1,A7"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Peripheral 4 A B Status" "TCLK1,A6"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Peripheral 3 A B Status" "PWMH3,A5"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Peripheral 2 A B Status" "PWMH2,A4"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr ,Peripheral 1 A B Status" "PWMH1,A3"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Peripheral 0 A B Status" "PWMH0,A2"
|
|
endif
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "PIO_IFDGSR,PIO Glitch or Debouncing Input Filter Selection Status Register"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P31_set/clr ,Glitch or Debouncing Filter Selection Status 31" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " P30_set/clr ,Glitch or Debouncing Filter Selection Status 30" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " P29_set/clr ,Glitch or Debouncing Filter Selection Status 29" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " P28_set/clr ,Glitch or Debouncing Filter Selection Status 28" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " P27_set/clr ,Glitch or Debouncing Filter Selection Status 27" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " P26_set/clr ,Glitch or Debouncing Filter Selection Status 26" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " P25_set/clr ,Glitch or Debouncing Filter Selection Status 25" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " P24_set/clr ,Glitch or Debouncing Filter Selection Status 24" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23_set/clr ,Glitch or Debouncing Filter Selection Status 23" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22_set/clr ,Glitch or Debouncing Filter Selection Status 22" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21_set/clr ,Glitch or Debouncing Filter Selection Status 21" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20_set/clr ,Glitch or Debouncing Filter Selection Status 20" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19_set/clr ,Glitch or Debouncing Filter Selection Status 19" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18_set/clr ,Glitch or Debouncing Filter Selection Status 18" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17_set/clr ,Glitch or Debouncing Filter Selection Status 17" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16_set/clr ,Glitch or Debouncing Filter Selection Status 16" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_set/clr ,Glitch or Debouncing Filter Selection Status 15" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Glitch or Debouncing Filter Selection Status 14" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Glitch or Debouncing Filter Selection Status 13" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Glitch or Debouncing Filter Selection Status 12" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Glitch or Debouncing Filter Selection Status 11" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Glitch or Debouncing Filter Selection Status 10" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Glitch or Debouncing Filter Selection Status 9" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Glitch or Debouncing Filter Selection Status 8" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Glitch or Debouncing Filter Selection Status 7" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Glitch or Debouncing Filter Selection Status 6" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Glitch or Debouncing Filter Selection Status 5" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Glitch or Debouncing Filter Selection Status 4" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Glitch or Debouncing Filter Selection Status 3" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Glitch or Debouncing Filter Selection Status 2" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr1 ,Glitch or Debouncing Filter Selection Status 1" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Glitch or Debouncing Filter Selection Status 0" "Glitch,Debouncing"
|
|
else
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P31_set/clr ,Glitch or Debouncing Filter Selection Status 31" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " P30_set/clr ,Glitch or Debouncing Filter Selection Status 30" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " P29_set/clr ,Glitch or Debouncing Filter Selection Status 29" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " P28_set/clr ,Glitch or Debouncing Filter Selection Status 28" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " P27_set/clr ,Glitch or Debouncing Filter Selection Status 27" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " P26_set/clr ,Glitch or Debouncing Filter Selection Status 26" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " P25_set/clr ,Glitch or Debouncing Filter Selection Status 25" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " P24_set/clr ,Glitch or Debouncing Filter Selection Status 24" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23_set/clr ,Glitch or Debouncing Filter Selection Status 23" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22_set/clr ,Glitch or Debouncing Filter Selection Status 22" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21_set/clr ,Glitch or Debouncing Filter Selection Status 21" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20_set/clr ,Glitch or Debouncing Filter Selection Status 20" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19_set/clr ,Glitch or Debouncing Filter Selection Status 19" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18_set/clr ,Glitch or Debouncing Filter Selection Status 18" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17_set/clr ,Glitch or Debouncing Filter Selection Status 17" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16_set/clr ,Glitch or Debouncing Filter Selection Status 16" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_set/clr ,Glitch or Debouncing Filter Selection Status 15" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Glitch or Debouncing Filter Selection Status 14" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Glitch or Debouncing Filter Selection Status 13" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Glitch or Debouncing Filter Selection Status 12" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Glitch or Debouncing Filter Selection Status 11" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Glitch or Debouncing Filter Selection Status 10" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Glitch or Debouncing Filter Selection Status 9" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Glitch or Debouncing Filter Selection Status 8" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Glitch or Debouncing Filter Selection Status 7" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Glitch or Debouncing Filter Selection Status 6" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Glitch or Debouncing Filter Selection Status 5" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Glitch or Debouncing Filter Selection Status 4" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Glitch or Debouncing Filter Selection Status 3" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Glitch or Debouncing Filter Selection Status 2" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr1 ,Glitch or Debouncing Filter Selection Status 1" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Glitch or Debouncing Filter Selection Status 0" "Glitch,Debouncing"
|
|
endif
|
|
group.long 0x8c++0x3
|
|
line.long 0x00 "PIO_SCDR,PIO Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow Clock Divider Selection for Debouncing"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "PIO_OWSRB,PIO Output Write Status Register B"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Output Write Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Output Write Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Write Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Write Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Write Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Write Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Write Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Write Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Write Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Write Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Write Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Write Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Write Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Write Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Write Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Write Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Write Status 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Write Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Write Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Write Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Write Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Write Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Write Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Write Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Write Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Write Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Write Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Write Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Write Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Write Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Output Write Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Write Status 0" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Output Write Status 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Output Write Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Write Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Write Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Write Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Write Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Write Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Write Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Write Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Write Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Write Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Write Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Write Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Write Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Write Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Write Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Write Status 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Write Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Write Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Write Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Write Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Write Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Write Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Write Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Write Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Write Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Write Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Write Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Write Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Write Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Output Write Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Write Status 0" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xB8++0x3
|
|
line.long 0x00 "PIO_AIMMR,Additional Interrupt Modes Mask Register"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Peripheral CD Status 31" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Peripheral CD Status 30" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Peripheral CD Status 29" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Peripheral CD Status 28" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Peripheral CD Status 27" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Peripheral CD Status 26" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Peripheral CD Status 25" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Peripheral CD Status 24" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Peripheral CD Status 23" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Peripheral CD Status 22" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Peripheral CD Status 21" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Peripheral CD Status 20" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Peripheral CD Status 19" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Peripheral CD Status 18" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Peripheral CD Status 17" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Peripheral CD Status 16" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Peripheral CD Status 15" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Peripheral CD Status 14" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Peripheral CD Status 13" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Peripheral CD Status 12" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Peripheral CD Status 11" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Peripheral CD Status 10" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Peripheral CD Status 9" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Peripheral CD Status 8" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Peripheral CD Status 7" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Peripheral CD Status 6" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Peripheral CD Status 5" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Peripheral CD Status 4" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Peripheral CD Status 3" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Peripheral CD Status 2" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Peripheral CD Status 1" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Peripheral CD Status 0" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
else
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Peripheral CD Status 31" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Peripheral CD Status 30" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Peripheral CD Status 29" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Peripheral CD Status 28" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Peripheral CD Status 27" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Peripheral CD Status 26" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Peripheral CD Status 25" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Peripheral CD Status 24" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Peripheral CD Status 23" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Peripheral CD Status 22" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Peripheral CD Status 21" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Peripheral CD Status 20" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Peripheral CD Status 19" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Peripheral CD Status 18" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Peripheral CD Status 17" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Peripheral CD Status 16" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Peripheral CD Status 15" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Peripheral CD Status 14" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Peripheral CD Status 13" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Peripheral CD Status 12" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Peripheral CD Status 11" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Peripheral CD Status 10" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Peripheral CD Status 9" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Peripheral CD Status 8" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Peripheral CD Status 7" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Peripheral CD Status 6" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Peripheral CD Status 5" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Peripheral CD Status 4" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Peripheral CD Status 3" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Peripheral CD Status 2" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Peripheral CD Status 1" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Peripheral CD Status 0" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
endif
|
|
group.long 0xC8++0x3
|
|
line.long 0x00 "PIO_ELSR,Edge/Level Status Register"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Edge/Level Interrupt source selection 31" "Edge,Level"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Edge/Level Interrupt source selection 30" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Edge/Level Interrupt source selection 29" "Edge,Level"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Edge/Level Interrupt source selection 28" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Edge/Level Interrupt source selection 27" "Edge,Level"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Edge/Level Interrupt source selection 26" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Edge/Level Interrupt source selection 25" "Edge,Level"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Edge/Level Interrupt source selection 24" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Edge/Level Interrupt source selection 23" "Edge,Level"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Edge/Level Interrupt source selection 22" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Edge/Level Interrupt source selection 21" "Edge,Level"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Edge/Level Interrupt source selection 20" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Edge/Level Interrupt source selection 19" "Edge,Level"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Edge/Level Interrupt source selection 18" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Edge/Level Interrupt source selection 17" "Edge,Level"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Edge/Level Interrupt source selection 16" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Edge/Level Interrupt source selection 15" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Edge/Level Interrupt source selection 14" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Edge/Level Interrupt source selection 13" "Edge,Level"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Edge/Level Interrupt source selection 12" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Edge/Level Interrupt source selection 11" "Edge,Level"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Edge/Level Interrupt source selection 10" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Edge/Level Interrupt source selection 9" "Edge,Level"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Edge/Level Interrupt source selection 8" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Edge/Level Interrupt source selection 7" "Edge,Level"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Edge/Level Interrupt source selection 6" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Edge/Level Interrupt source selection 5" "Edge,Level"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Edge/Level Interrupt source selection 4" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Edge/Level Interrupt source selection 3" "Edge,Level"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Edge/Level Interrupt source selection 2" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Edge/Level Interrupt source selection 1" "Edge,Level"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection 0" "Edge,Level"
|
|
else
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Edge/Level Interrupt source selection 31" "Edge,Level"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Edge/Level Interrupt source selection 30" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Edge/Level Interrupt source selection 29" "Edge,Level"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Edge/Level Interrupt source selection 28" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Edge/Level Interrupt source selection 27" "Edge,Level"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Edge/Level Interrupt source selection 26" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Edge/Level Interrupt source selection 25" "Edge,Level"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Edge/Level Interrupt source selection 24" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Edge/Level Interrupt source selection 23" "Edge,Level"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Edge/Level Interrupt source selection 22" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Edge/Level Interrupt source selection 21" "Edge,Level"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Edge/Level Interrupt source selection 20" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Edge/Level Interrupt source selection 19" "Edge,Level"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Edge/Level Interrupt source selection 18" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Edge/Level Interrupt source selection 17" "Edge,Level"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Edge/Level Interrupt source selection 16" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Edge/Level Interrupt source selection 15" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Edge/Level Interrupt source selection 14" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Edge/Level Interrupt source selection 13" "Edge,Level"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Edge/Level Interrupt source selection 12" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Edge/Level Interrupt source selection 11" "Edge,Level"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Edge/Level Interrupt source selection 10" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Edge/Level Interrupt source selection 9" "Edge,Level"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Edge/Level Interrupt source selection 8" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Edge/Level Interrupt source selection 7" "Edge,Level"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Edge/Level Interrupt source selection 6" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Edge/Level Interrupt source selection 5" "Edge,Level"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Edge/Level Interrupt source selection 4" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Edge/Level Interrupt source selection 3" "Edge,Level"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Edge/Level Interrupt source selection 2" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Edge/Level Interrupt source selection 1" "Edge,Level"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection 0" "Edge,Level"
|
|
endif
|
|
group.long 0xd8++0x3
|
|
line.long 0x00 "PIO_FRLHSR,Fall/Rise - Low/High Status Register"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Edge/Level Interrupt source selection 31 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Edge/Level Interrupt source selection 30 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Edge/Level Interrupt source selection 29 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Edge/Level Interrupt source selection 28 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Edge/Level Interrupt source selection 27 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Edge/Level Interrupt source selection 26 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Edge/Level Interrupt source selection 25 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Edge/Level Interrupt source selection 24 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Edge/Level Interrupt source selection 23 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Edge/Level Interrupt source selection 22 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Edge/Level Interrupt source selection 21 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Edge/Level Interrupt source selection 20 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Edge/Level Interrupt source selection 19 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Edge/Level Interrupt source selection 18 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Edge/Level Interrupt source selection 17 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Edge/Level Interrupt source selection 16 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Edge/Level Interrupt source selection 15 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Edge/Level Interrupt source selection 14 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Edge/Level Interrupt source selection 13 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Edge/Level Interrupt source selection 12 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Edge/Level Interrupt source selection 11 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Edge/Level Interrupt source selection 10 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Edge/Level Interrupt source selection 9 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Edge/Level Interrupt source selection 8 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Edge/Level Interrupt source selection 7 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Edge/Level Interrupt source selection 6 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Edge/Level Interrupt source selection 5 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Edge/Level Interrupt source selection 4 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Edge/Level Interrupt source selection 3 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Edge/Level Interrupt source selection 2 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Edge/Level Interrupt source selection 1 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection 0 (Edge/Level)" "Falling/Low,Rising/High"
|
|
else
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Edge/Level Interrupt source selection 31 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Edge/Level Interrupt source selection 30 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Edge/Level Interrupt source selection 29 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Edge/Level Interrupt source selection 28 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Edge/Level Interrupt source selection 27 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Edge/Level Interrupt source selection 26 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Edge/Level Interrupt source selection 25 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Edge/Level Interrupt source selection 24 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Edge/Level Interrupt source selection 23 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Edge/Level Interrupt source selection 22 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Edge/Level Interrupt source selection 21 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Edge/Level Interrupt source selection 20 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Edge/Level Interrupt source selection 19 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Edge/Level Interrupt source selection 18 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Edge/Level Interrupt source selection 17 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Edge/Level Interrupt source selection 16 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Edge/Level Interrupt source selection 15 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Edge/Level Interrupt source selection 14 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Edge/Level Interrupt source selection 13 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Edge/Level Interrupt source selection 12 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Edge/Level Interrupt source selection 11 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Edge/Level Interrupt source selection 10 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Edge/Level Interrupt source selection 9 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Edge/Level Interrupt source selection 8 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Edge/Level Interrupt source selection 7 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Edge/Level Interrupt source selection 6 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Edge/Level Interrupt source selection 5 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Edge/Level Interrupt source selection 4 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Edge/Level Interrupt source selection 3 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Edge/Level Interrupt source selection 2 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Edge/Level Interrupt source selection 1 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection 0 (Edge/Level)" "Falling/Low,Rising/High"
|
|
endif
|
|
rgroup.long 0xe0++0x3
|
|
line.long 0x00 "PIO_LOCKSR,Lock Status Register"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 31. " P31 ,I/O line 31 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 30. " P30 ,I/O line 30 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,I/O line 29 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 28. " P28 ,I/O line 28 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,I/O line 27 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " P26 ,I/O line 26 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,I/O line 25 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 24. " P24 ,I/O line 24 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,I/O line 23 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 22. " P22 ,I/O line 22 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,I/O line 21 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 20. " P20 ,I/O line 20 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,I/O line 19 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 18. " P18 ,I/O line 18 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,I/O line 17 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 16. " P16 ,I/O line 16 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,I/O line 15 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,I/O line 14 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,I/O line 13 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " P12 ,I/O line 12 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,I/O line 11 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " P10 ,I/O line 10 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,I/O line 9 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " P8 ,I/O line 8 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,I/O line 7 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " P6 ,I/O line 6 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,I/O line 5 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " P4 ,I/O line 4 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,I/O line 3 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " P2 ,I/O line 2 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,I/O line 1 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " P0 ,I/O line 0 Lock Status" "Not locked,Locked"
|
|
else
|
|
bitfld.long 0x00 31. " P31 ,I/O line 31 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 30. " P30 ,I/O line 30 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,I/O line 29 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 28. " P28 ,I/O line 28 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,I/O line 27 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " P26 ,I/O line 26 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,I/O line 25 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 24. " P24 ,I/O line 24 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,I/O line 23 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 22. " P22 ,I/O line 22 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,I/O line 21 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 20. " P20 ,I/O line 20 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,I/O line 19 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 18. " P18 ,I/O line 18 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,I/O line 17 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 16. " P16 ,I/O line 16 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,I/O line 15 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,I/O line 14 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,I/O line 13 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " P12 ,I/O line 12 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,I/O line 11 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " P10 ,I/O line 10 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,I/O line 9 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " P8 ,I/O line 8 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,I/O line 7 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " P6 ,I/O line 6 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,I/O line 5 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " P4 ,I/O line 4 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,I/O line 3 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " P2 ,I/O line 2 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,I/O line 1 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " P0 ,I/O line 0 Lock Status" "Not locked,Locked"
|
|
endif
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect Enable"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PIO_WPSR,Write Protect Violation Status"
|
|
in
|
|
width 13.
|
|
sif (!cpuis("AT91SAM3A*")&&!cpuis("AT91SAM3X4C")&&!cpuis("AT91SAM3X4E")&&!cpuis("AT91SAM3X8C")&&!cpuis("AT91SAM3X8E"))
|
|
group.long 0xF50++0x3
|
|
line.long 0x00 "PIO_PCMR,PIO Parallel Capture Mode Register"
|
|
bitfld.long 0x00 11. " FRSTS ,Parallel Capture Mode First Sample" "Even index,Odd index"
|
|
bitfld.long 0x00 10. " HALFS ,Parallel Capture Mode Half Sampling" "All data,One time out of two"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ALWYS ,Parallel Capture Mode Always Sampling" "No,Yes"
|
|
bitfld.long 0x00 4.--5. " DSIZE ,Parallel Capture Mode Data Size" "8 bit,16 bit,32 bit,32 bit"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PCEN ,Parallel Capture Mode Enable" "Disabled,Enabled"
|
|
rgroup.long 0xF5C++0x3
|
|
line.long 0x00 "PIO_PCIMR,PIO Parallel Capture Interrupt Mask Register"
|
|
bitfld.long 0x00 3. " RXBUFF ,Reception Buffer Full Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " ENDRX ,End of Reception Transfer Interrupt Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OVRE ,Parallel Capture Mode Overrun Error Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " DRDY ,Parallel Capture Mode Data Ready Interrupt Mask" "Not masked,Masked"
|
|
group.long 0xF60++0x3
|
|
line.long 0x00 "PIO_PCISR,PIO Parallel Capture Interrupt Status Register"
|
|
setclrfld.long 0x00 3. -0x0C 3. -0x08 3. " RXBUFF_set/clr ,Reception Buffer Full Interrupt Status" "Inactive,Active"
|
|
setclrfld.long 0x00 2. -0x0C 2. -0x08 2. " ENDRX_set/clr ,End of Reception Transfer Interrupt Status" "Inactive,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x0C 1. -0x08 1. " OVRE_set/clr ,Parallel Capture Mode Overrun Error Interrupt Status" "No error,Error"
|
|
setclrfld.long 0x00 0. -0x0C 0. -0x08 0. " DRDY_set/clr ,Parallel Capture Mode Data Ready Interrupt Status" "Not ready,Ready"
|
|
if ((d.l(ad:0x0+0xf50)&0x30)==0x00)
|
|
rgroup.long 0xF64++0x3
|
|
line.long 0x00 "PIO_PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
hexmask.long.byte 0x00 0.--8. 1. " RDATA ,Parallel Capture Mode Reception Data"
|
|
elif ((d.l(ad:0x0+0xf50)&0x30)==0x10)
|
|
rgroup.long 0xF64++0x3
|
|
line.long 0x00 "PIO_PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
hexmask.long.word 0x00 0.--16. 1. " RDATA ,Parallel Capture Mode Reception Data"
|
|
else
|
|
rgroup.long 0xF64++0x3
|
|
line.long 0x00 "PIO_PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
endif
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "Port C"
|
|
base ad:0x400E2000
|
|
width 13.
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PIO_PSRC,PIO Controller PIO Status Register C"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,PIO30 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,PIO29 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,PIO28 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,PIO27 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,PIO26 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,PIO25 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,PIO24 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,PIO23 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,PIO22 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,PIO21 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,PIO20 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,PIO19 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,PIO18 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,PIO17 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,PIO16 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,PIO15 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,PIO14 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,PIO13 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO12 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,PIO11 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,PIO10 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,PIO9 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,PIO8 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,PIO7 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,PIO6 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO5 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO4 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO3 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO2 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO1 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO0 Status" "Peripheral,PIO"
|
|
else
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO0 Status" "Peripheral,PIO"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PIO_OSRC,PIO Controller Output Status Register C"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,PIO30 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,PIO29 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,PIO28 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,PIO27 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,PIO26 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,PIO25 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,PIO24 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,PIO23 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,PIO22 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,PIO21 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,PIO20 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,PIO19 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,PIO18 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,PIO17 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,PIO16 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,PIO15 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,PIO14 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,PIO13 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO12 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,PIO11 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,PIO10 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,PIO9 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,PIO8 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,PIO7 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,PIO6 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO5 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO4 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO3 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO2 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO1 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO0 Status" "Peripheral,PIO"
|
|
else
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO0 Status" "Peripheral,PIO"
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PIO_IFSRC,PIO Controller Input Filter Status Register C"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,PIO30 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,PIO29 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,PIO28 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,PIO27 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,PIO26 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,PIO25 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,PIO24 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,PIO23 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,PIO22 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,PIO21 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,PIO20 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,PIO19 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,PIO18 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,PIO17 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,PIO16 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,PIO15 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,PIO14 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,PIO13 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO12 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,PIO11 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,PIO10 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,PIO9 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,PIO8 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,PIO7 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,PIO6 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO5 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO4 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO3 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO2 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO1 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO0 Status" "Peripheral,PIO"
|
|
else
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO0 Status" "Peripheral,PIO"
|
|
endif
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PIO_ODSRC,PIO Controller Output Data Status Register C"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Output Data Status 30" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Data Status 29" "Low,High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Data Status 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Data Status 25" "Low,High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Data Status 23" "Low,High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Data Status 21" "Low,High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Data Status 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Data Status 17" "Low,High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Data Status 15" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
else
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
endif
|
|
rgroup.long 0x3c++0x03
|
|
line.long 0x00 "PIO_PDSRC,PIO Controller Pin Data Status Register C"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 30. " P30 ,Output Data Status 30" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Output Data Status 29" "Low,High"
|
|
bitfld.long 0x00 28. " P28 ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Output Data Status 27" "Low,High"
|
|
bitfld.long 0x00 26. " P26 ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Output Data Status 25" "Low,High"
|
|
bitfld.long 0x00 24. " P24 ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Output Data Status 23" "Low,High"
|
|
bitfld.long 0x00 22. " P22 ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Output Data Status 21" "Low,High"
|
|
bitfld.long 0x00 20. " P20 ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Output Data Status 19" "Low,High"
|
|
bitfld.long 0x00 18. " P18 ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Output Data Status 17" "Low,High"
|
|
bitfld.long 0x00 16. " P16 ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Output Data Status 15" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Data Status 13" "Low,High"
|
|
bitfld.long 0x00 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x00 10. " P10 ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x00 8. " P8 ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Data Status 7" "Low,High"
|
|
bitfld.long 0x00 6. " P6 ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x00 4. " P4 ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x00 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Data Status 1" "Low,High"
|
|
bitfld.long 0x00 0. " P0 ,Output Data Status 0" "Low,High"
|
|
else
|
|
bitfld.long 0x00 0. " P0 ,Output Data Status 0" "Low,High"
|
|
endif
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PIO_IMRC,PIO Controller Interrupt Mask Register C"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Input Change Interrupt Data Status 30" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Input Change Interrupt Data Status 29" "Low,High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Input Change Interrupt Data Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Input Change Interrupt Data Status 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Input Change Interrupt Data Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Input Change Interrupt Data Status 25" "Low,High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Input Change Interrupt Data Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Input Change Interrupt Data Status 23" "Low,High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Input Change Interrupt Data Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Input Change Interrupt Data Status 21" "Low,High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Input Change Interrupt Data Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Input Change Interrupt Data Status 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Input Change Interrupt Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Input Change Interrupt Data Status 17" "Low,High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Input Change Interrupt Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Input Change Interrupt Data Status 15" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Input Change Interrupt Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Input Change Interrupt Data Status 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Change Interrupt Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Change Interrupt Data Status 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Change Interrupt Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Change Interrupt Data Status 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Change Interrupt Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Change Interrupt Data Status 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Change Interrupt Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Change Interrupt Data Status 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Change Interrupt Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Change Interrupt Data Status 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Change Interrupt Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Change Interrupt Data Status 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Change Interrupt Data Status 0" "Low,High"
|
|
else
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Change Interrupt Data Status 0" "Low,High"
|
|
endif
|
|
hgroup.long 0x4c++0x03
|
|
hide.long 0x00 "PIO_ISRC,PIO Controller Interrupt Status Register C"
|
|
in
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "PIO_MDSRC,PIO Multi-Driver Status Register C"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,The Multi Drive Status 30" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,The Multi Drive Status 29" "Low,High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,The Multi Drive Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,The Multi Drive Status 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,The Multi Drive Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,The Multi Drive Status 25" "Low,High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,The Multi Drive Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,The Multi Drive Status 23" "Low,High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,The Multi Drive Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,The Multi Drive Status 21" "Low,High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,The Multi Drive Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,The Multi Drive Status 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,The Multi Drive Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,The Multi Drive Status 17" "Low,High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,The Multi Drive Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,The Multi Drive Status 15" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,The Multi Drive Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,The Multi Drive Status 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,The Multi Drive Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,The Multi Drive Status 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,The Multi Drive Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,The Multi Drive Status 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,The Multi Drive Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,The Multi Drive Status 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,The Multi Drive Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,The Multi Drive Status 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,The Multi Drive Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,The Multi Drive Status 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,The Multi Drive Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,The Multi Drive Status 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,The Multi Drive Status 0" "Low,High"
|
|
else
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,The Multi Drive Status 0" "Low,High"
|
|
endif
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PIO_PUSRC,PIO Pull Up Status Register C"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Pull Up resistor Status 30" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Pull Up resistor Status 29" "Low,High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Pull Up resistor Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Pull Up resistor Status 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Pull Up resistor Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Pull Up resistor Status 25" "Low,High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Pull Up resistor Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Pull Up resistor Status 23" "Low,High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Pull Up resistor Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Pull Up resistor Status 21" "Low,High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Pull Up resistor Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Pull Up resistor Status 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Pull Up resistor Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Pull Up resistor Status 17" "Low,High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Pull Up resistor Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Pull Up resistor Status 15" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Pull Up resistor Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Pull Up resistor Status 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Pull Up resistor Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Pull Up resistor Status 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Pull Up resistor Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Pull Up resistor Status 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Pull Up resistor Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Pull Up resistor Status 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Pull Up resistor Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Pull Up resistor Status 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Pull Up resistor Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Pull Up resistor Status 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Pull Up resistor Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Pull Up resistor Status 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Pull Up resistor Status 0" "Low,High"
|
|
else
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Pull Up resistor Status 0" "Low,High"
|
|
endif
|
|
group.long 0x70++0x7
|
|
line.long 0x00 "PIO_ABCDSR1,PIO Peripheral ABCD Select Register 1"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 30. " P30 ,Assigns the I/O line Status 30" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,Assigns the I/O line Status 29" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 28. " P28 ,Assigns the I/O line Status 28" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Assigns the I/O line Status 27" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 26. " P26 ,Assigns the I/O line Status 26" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Assigns the I/O line Status 25" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 24. " P24 ,Assigns the I/O line Status 24" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Assigns the I/O line Status 23" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 22. " P22 ,Assigns the I/O line Status 22" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Assigns the I/O line Status 21" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 20. " P20 ,Assigns the I/O line Status 20" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Assigns the I/O line Status 19" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 18. " P18 ,Assigns the I/O line Status 18" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Assigns the I/O line Status 17" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 16. " P16 ,Assigns the I/O line Status 16" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Assigns the I/O line Status 15" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Assigns the I/O line Status 14" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Assigns the I/O line Status 13" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 12. " P12 ,Assigns the I/O line Status 12" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Assigns the I/O line Status 11" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 10. " P10 ,Assigns the I/O line Status 10" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Assigns the I/O line Status 9" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 8. " P8 ,Assigns the I/O line Status 8" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Assigns the I/O line Status 7" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 6. " P6 ,Assigns the I/O line Status 6" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Assigns the I/O line Status 5" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 4. " P4 ,Assigns the I/O line Status 4" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Assigns the I/O line Status 3" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 2. " P2 ,Assigns the I/O line Status 2" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Assigns the I/O line Status 1" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 0. " P0 ,Assigns the I/O line Status 0" "Peripheral A/C,Peripheral B/D"
|
|
else
|
|
bitfld.long 0x00 0. " P0 ,Assigns the I/O line Status 0" "Peripheral A/C,Peripheral B/D"
|
|
endif
|
|
line.long 0x04 "PIO_ABCDSR2,PIO Peripheral ABCD Select Register 2"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x04 30. " P30 ,Assigns the I/O line Status 30" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 29. " P29 ,Assigns the I/O line Status 29" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 28. " P28 ,Assigns the I/O line Status 28" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 27. " P27 ,Assigns the I/O line Status 27" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 26. " P26 ,Assigns the I/O line Status 26" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 25. " P25 ,Assigns the I/O line Status 25" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 24. " P24 ,Assigns the I/O line Status 24" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 23. " P23 ,Assigns the I/O line Status 23" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 22. " P22 ,Assigns the I/O line Status 22" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 21. " P21 ,Assigns the I/O line Status 21" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 20. " P20 ,Assigns the I/O line Status 20" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 19. " P19 ,Assigns the I/O line Status 19" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 18. " P18 ,Assigns the I/O line Status 18" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 17. " P17 ,Assigns the I/O line Status 17" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 16. " P16 ,Assigns the I/O line Status 16" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 15. " P15 ,Assigns the I/O line Status 15" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 14. " P14 ,Assigns the I/O line Status 14" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 13. " P13 ,Assigns the I/O line Status 13" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 12. " P12 ,Assigns the I/O line Status 12" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 11. " P11 ,Assigns the I/O line Status 11" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 10. " P10 ,Assigns the I/O line Status 10" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 9. " P9 ,Assigns the I/O line Status 9" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 8. " P8 ,Assigns the I/O line Status 8" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 7. " P7 ,Assigns the I/O line Status 7" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 6. " P6 ,Assigns the I/O line Status 6" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 5. " P5 ,Assigns the I/O line Status 5" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 4. " P4 ,Assigns the I/O line Status 4" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 3. " P3 ,Assigns the I/O line Status 3" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 2. " P2 ,Assigns the I/O line Status 2" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 1. " P1 ,Assigns the I/O line Status 1" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 0. " P0 ,Assigns the I/O line Status 0" "Peripheral A/B,Peripheral C/D"
|
|
else
|
|
bitfld.long 0x04 0. " P0 ,Assigns the I/O line Status 0" "Peripheral A/B,Peripheral C/D"
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")&&!cpuis("AT91SAM3X*"))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "PIO_ABSRC,PIO Peripheral A B Status Register C"
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P31_set/clr ,Peripheral 31 A B Status" "PWML2,MCDA7"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " P30_set/clr ,Peripheral 30 A B Status" "PWML1,MCDA6"
|
|
textline " "
|
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setclrfld.long 0x00 29. -0x04 29. -0x08 29. " P29_set/clr ,Peripheral 29 A B Status" "PWML0,MCDA5"
|
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setclrfld.long 0x00 28. -0x04 28. -0x08 28. " P28_set/clr ,Peripheral 28 A B Status" ",MCDA4"
|
|
textline " "
|
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setclrfld.long 0x00 27. -0x04 27. -0x08 27. " P27_set/clr ,Peripheral 27 A B Status" "A23,PWMH3"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " P26_set/clr ,Peripheral 26 A B Status" "A20,PWMH2"
|
|
textline " "
|
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setclrfld.long 0x00 25. -0x04 25. -0x08 25. " P25_set/clr ,Peripheral 25 A B Status" "A19,PWMH1"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " P24_set/clr ,Peripheral 24 A B Status" "A18,PWMH0"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23_set/clr ,Peripheral 23 A B Status" "A17,?..."
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22_set/clr ,Peripheral 22 A B Status" "A16,?..."
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21_set/clr ,Peripheral 21 A B Status" "A15,?..."
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20_set/clr ,Peripheral 20 A B Status" "A14,?..."
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19_set/clr ,Peripheral 19 A B Status" "SCK3,NPCS1"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18_set/clr ,Peripheral 18 A B Status" "NWAIT,?..."
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17_set/clr ,Peripheral 17 A B Status" "NCS3,?..."
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16_set/clr ,Peripheral 16 A B Status" "NCS2,PWML3"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_set/clr ,Peripheral 15 A B Status" "NWR1/NBS1,?..."
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Peripheral 14 A B Status" "A3,NPCS2"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Peripheral 13 A B Status" "A2,RXD3"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Peripheral 12 A B Status" "NCS1,TXD3"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Peripheral 11 A B Status" "A13,RTS3"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Peripheral 10 A B Status" "A12,CTS3"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Peripheral 9 A B Status" "A11,PWML3"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Peripheral 8 A B Status" "A10,PWML2"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Peripheral 7 A B Status" "A9,PWML1"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Peripheral 6 A B Status" "A8,PWML0"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Peripheral 5 A B Status" "A7,NPCS3"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Peripheral 4 A B Status" "A6,NPCS2"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Peripheral 3 A B Status" "A5,NPCS1"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Peripheral 2 A B Status" "A4,?..."
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr ,Peripheral 1 A B Status" "A3,?..."
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Peripheral 0 A B Status" "A2,?..."
|
|
endif
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "PIO_IFDGSR,PIO Glitch or Debouncing Input Filter Selection Status Register"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " P30_set/clr ,Glitch or Debouncing Filter Selection Status 30" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " P29_set/clr ,Glitch or Debouncing Filter Selection Status 29" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " P28_set/clr ,Glitch or Debouncing Filter Selection Status 28" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " P27_set/clr ,Glitch or Debouncing Filter Selection Status 27" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " P26_set/clr ,Glitch or Debouncing Filter Selection Status 26" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " P25_set/clr ,Glitch or Debouncing Filter Selection Status 25" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " P24_set/clr ,Glitch or Debouncing Filter Selection Status 24" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23_set/clr ,Glitch or Debouncing Filter Selection Status 23" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22_set/clr ,Glitch or Debouncing Filter Selection Status 22" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21_set/clr ,Glitch or Debouncing Filter Selection Status 21" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20_set/clr ,Glitch or Debouncing Filter Selection Status 20" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19_set/clr ,Glitch or Debouncing Filter Selection Status 19" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18_set/clr ,Glitch or Debouncing Filter Selection Status 18" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17_set/clr ,Glitch or Debouncing Filter Selection Status 17" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16_set/clr ,Glitch or Debouncing Filter Selection Status 16" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_set/clr ,Glitch or Debouncing Filter Selection Status 15" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Glitch or Debouncing Filter Selection Status 14" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Glitch or Debouncing Filter Selection Status 13" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Glitch or Debouncing Filter Selection Status 12" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Glitch or Debouncing Filter Selection Status 11" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Glitch or Debouncing Filter Selection Status 10" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Glitch or Debouncing Filter Selection Status 9" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Glitch or Debouncing Filter Selection Status 8" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Glitch or Debouncing Filter Selection Status 7" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Glitch or Debouncing Filter Selection Status 6" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Glitch or Debouncing Filter Selection Status 5" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Glitch or Debouncing Filter Selection Status 4" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Glitch or Debouncing Filter Selection Status 3" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Glitch or Debouncing Filter Selection Status 2" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr1 ,Glitch or Debouncing Filter Selection Status 1" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Glitch or Debouncing Filter Selection Status 0" "Glitch,Debouncing"
|
|
else
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Glitch or Debouncing Filter Selection Status 0" "Glitch,Debouncing"
|
|
endif
|
|
group.long 0x8c++0x3
|
|
line.long 0x00 "PIO_SCDR,PIO Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow Clock Divider Selection for Debouncing"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "PIO_OWSRC,PIO Output Write Status Register C"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Output Write Status 30" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Write Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Write Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Write Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Write Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Write Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Write Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Write Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Write Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Write Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Write Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Write Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Write Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Write Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Write Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Write Status 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Write Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Write Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Write Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Write Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Write Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Write Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Write Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Write Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Write Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Write Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Write Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Write Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Write Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Output Write Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Write Status 0" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Write Status 0" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xB8++0x3
|
|
line.long 0x00 "PIO_AIMMR,Additional Interrupt Modes Mask Register"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Peripheral CD Status 30" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Peripheral CD Status 29" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Peripheral CD Status 28" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Peripheral CD Status 27" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Peripheral CD Status 26" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Peripheral CD Status 25" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Peripheral CD Status 24" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Peripheral CD Status 23" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Peripheral CD Status 22" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Peripheral CD Status 21" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Peripheral CD Status 20" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Peripheral CD Status 19" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Peripheral CD Status 18" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Peripheral CD Status 17" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Peripheral CD Status 16" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Peripheral CD Status 15" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Peripheral CD Status 14" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Peripheral CD Status 13" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Peripheral CD Status 12" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Peripheral CD Status 11" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Peripheral CD Status 10" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Peripheral CD Status 9" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Peripheral CD Status 8" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Peripheral CD Status 7" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Peripheral CD Status 6" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Peripheral CD Status 5" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Peripheral CD Status 4" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Peripheral CD Status 3" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Peripheral CD Status 2" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Peripheral CD Status 1" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Peripheral CD Status 0" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
else
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Peripheral CD Status 0" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
endif
|
|
group.long 0xC8++0x3
|
|
line.long 0x00 "PIO_ELSR,Edge/Level Status Register"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Edge/Level Interrupt source selection 30" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Edge/Level Interrupt source selection 29" "Edge,Level"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Edge/Level Interrupt source selection 28" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Edge/Level Interrupt source selection 27" "Edge,Level"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Edge/Level Interrupt source selection 26" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Edge/Level Interrupt source selection 25" "Edge,Level"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Edge/Level Interrupt source selection 24" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Edge/Level Interrupt source selection 23" "Edge,Level"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Edge/Level Interrupt source selection 22" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Edge/Level Interrupt source selection 21" "Edge,Level"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Edge/Level Interrupt source selection 20" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Edge/Level Interrupt source selection 19" "Edge,Level"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Edge/Level Interrupt source selection 18" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Edge/Level Interrupt source selection 17" "Edge,Level"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Edge/Level Interrupt source selection 16" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Edge/Level Interrupt source selection 15" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Edge/Level Interrupt source selection 14" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Edge/Level Interrupt source selection 13" "Edge,Level"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Edge/Level Interrupt source selection 12" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Edge/Level Interrupt source selection 11" "Edge,Level"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Edge/Level Interrupt source selection 10" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Edge/Level Interrupt source selection 9" "Edge,Level"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Edge/Level Interrupt source selection 8" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Edge/Level Interrupt source selection 7" "Edge,Level"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Edge/Level Interrupt source selection 6" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Edge/Level Interrupt source selection 5" "Edge,Level"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Edge/Level Interrupt source selection 4" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Edge/Level Interrupt source selection 3" "Edge,Level"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Edge/Level Interrupt source selection 2" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Edge/Level Interrupt source selection 1" "Edge,Level"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection 0" "Edge,Level"
|
|
else
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection 0" "Edge,Level"
|
|
endif
|
|
group.long 0xd8++0x3
|
|
line.long 0x00 "PIO_FRLHSR,Fall/Rise - Low/High Status Register"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Edge/Level Interrupt source selection 30 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Edge/Level Interrupt source selection 29 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Edge/Level Interrupt source selection 28 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Edge/Level Interrupt source selection 27 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Edge/Level Interrupt source selection 26 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Edge/Level Interrupt source selection 25 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Edge/Level Interrupt source selection 24 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Edge/Level Interrupt source selection 23 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Edge/Level Interrupt source selection 22 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Edge/Level Interrupt source selection 21 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Edge/Level Interrupt source selection 20 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Edge/Level Interrupt source selection 19 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Edge/Level Interrupt source selection 18 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Edge/Level Interrupt source selection 17 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Edge/Level Interrupt source selection 16 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Edge/Level Interrupt source selection 15 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Edge/Level Interrupt source selection 14 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Edge/Level Interrupt source selection 13 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Edge/Level Interrupt source selection 12 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Edge/Level Interrupt source selection 11 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Edge/Level Interrupt source selection 10 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Edge/Level Interrupt source selection 9 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Edge/Level Interrupt source selection 8 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Edge/Level Interrupt source selection 7 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Edge/Level Interrupt source selection 6 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Edge/Level Interrupt source selection 5 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Edge/Level Interrupt source selection 4 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Edge/Level Interrupt source selection 3 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Edge/Level Interrupt source selection 2 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Edge/Level Interrupt source selection 1 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection 0 (Edge/Level)" "Falling/Low,Rising/High"
|
|
else
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection 0 (Edge/Level)" "Falling/Low,Rising/High"
|
|
endif
|
|
rgroup.long 0xe0++0x3
|
|
line.long 0x00 "PIO_LOCKSR,Lock Status Register"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 30. " P30 ,I/O line 30 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 29. " P29 ,I/O line 29 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 28. " P28 ,I/O line 28 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,I/O line 27 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " P26 ,I/O line 26 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,I/O line 25 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 24. " P24 ,I/O line 24 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,I/O line 23 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 22. " P22 ,I/O line 22 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,I/O line 21 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 20. " P20 ,I/O line 20 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,I/O line 19 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 18. " P18 ,I/O line 18 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,I/O line 17 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 16. " P16 ,I/O line 16 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,I/O line 15 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,I/O line 14 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,I/O line 13 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " P12 ,I/O line 12 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,I/O line 11 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " P10 ,I/O line 10 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,I/O line 9 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " P8 ,I/O line 8 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,I/O line 7 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " P6 ,I/O line 6 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,I/O line 5 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " P4 ,I/O line 4 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,I/O line 3 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " P2 ,I/O line 2 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,I/O line 1 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " P0 ,I/O line 0 Lock Status" "Not locked,Locked"
|
|
else
|
|
bitfld.long 0x00 0. " P0 ,I/O line 0 Lock Status" "Not locked,Locked"
|
|
endif
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect Enable"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PIO_WPSR,Write Protect Violation Status"
|
|
in
|
|
width 13.
|
|
sif (!cpuis("AT91SAM3A*")&&!cpuis("AT91SAM3X4C")&&!cpuis("AT91SAM3X4E")&&!cpuis("AT91SAM3X8C")&&!cpuis("AT91SAM3X8E"))
|
|
group.long 0xF50++0x3
|
|
line.long 0x00 "PIO_PCMR,PIO Parallel Capture Mode Register"
|
|
bitfld.long 0x00 11. " FRSTS ,Parallel Capture Mode First Sample" "Even index,Odd index"
|
|
bitfld.long 0x00 10. " HALFS ,Parallel Capture Mode Half Sampling" "All data,One time out of two"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ALWYS ,Parallel Capture Mode Always Sampling" "No,Yes"
|
|
bitfld.long 0x00 4.--5. " DSIZE ,Parallel Capture Mode Data Size" "8 bit,16 bit,32 bit,32 bit"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PCEN ,Parallel Capture Mode Enable" "Disabled,Enabled"
|
|
rgroup.long 0xF5C++0x3
|
|
line.long 0x00 "PIO_PCIMR,PIO Parallel Capture Interrupt Mask Register"
|
|
bitfld.long 0x00 3. " RXBUFF ,Reception Buffer Full Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " ENDRX ,End of Reception Transfer Interrupt Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OVRE ,Parallel Capture Mode Overrun Error Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " DRDY ,Parallel Capture Mode Data Ready Interrupt Mask" "Not masked,Masked"
|
|
group.long 0xF60++0x3
|
|
line.long 0x00 "PIO_PCISR,PIO Parallel Capture Interrupt Status Register"
|
|
setclrfld.long 0x00 3. -0x0C 3. -0x08 3. " RXBUFF_set/clr ,Reception Buffer Full Interrupt Status" "Inactive,Active"
|
|
setclrfld.long 0x00 2. -0x0C 2. -0x08 2. " ENDRX_set/clr ,End of Reception Transfer Interrupt Status" "Inactive,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x0C 1. -0x08 1. " OVRE_set/clr ,Parallel Capture Mode Overrun Error Interrupt Status" "No error,Error"
|
|
setclrfld.long 0x00 0. -0x0C 0. -0x08 0. " DRDY_set/clr ,Parallel Capture Mode Data Ready Interrupt Status" "Not ready,Ready"
|
|
if ((d.l(ad:0x0+0xf50)&0x30)==0x00)
|
|
rgroup.long 0xF64++0x3
|
|
line.long 0x00 "PIO_PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
hexmask.long.byte 0x00 0.--8. 1. " RDATA ,Parallel Capture Mode Reception Data"
|
|
elif ((d.l(ad:0x0+0xf50)&0x30)==0x10)
|
|
rgroup.long 0xF64++0x3
|
|
line.long 0x00 "PIO_PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
hexmask.long.word 0x00 0.--16. 1. " RDATA ,Parallel Capture Mode Reception Data"
|
|
else
|
|
rgroup.long 0xF64++0x3
|
|
line.long 0x00 "PIO_PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
endif
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
sif (cpuis("AT91SAM3X8E")||cpuis("AT91SAM3X4E"))
|
|
tree "Port D"
|
|
base ad:0x400E1400
|
|
width 13.
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PIO_PSRD,PIO Controller PIO Status Register D"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,PIO29 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,PIO28 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,PIO27 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,PIO26 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,PIO25 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,PIO24 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,PIO23 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,PIO22 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,PIO21 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,PIO20 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,PIO19 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,PIO18 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,PIO17 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,PIO16 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,PIO15 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,PIO14 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,PIO13 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO12 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,PIO11 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,PIO10 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,PIO9 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,PIO8 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,PIO7 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,PIO6 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO5 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO4 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO3 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO2 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO1 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO0 Status" "Peripheral,PIO"
|
|
else
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,PIO29 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,PIO28 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,PIO27 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,PIO26 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,PIO25 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,PIO24 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,PIO23 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,PIO22 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,PIO21 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,PIO20 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,PIO19 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,PIO18 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,PIO17 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,PIO16 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,PIO15 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,PIO14 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,PIO13 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO12 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,PIO11 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,PIO10 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,PIO9 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,PIO8 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,PIO7 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,PIO6 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO5 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO4 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO3 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO2 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO1 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO0 Status" "Peripheral,PIO"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PIO_OSRD,PIO Controller Output Status Register D"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,PIO29 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,PIO28 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,PIO27 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,PIO26 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,PIO25 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,PIO24 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,PIO23 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,PIO22 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,PIO21 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,PIO20 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,PIO19 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,PIO18 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,PIO17 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,PIO16 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,PIO15 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,PIO14 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,PIO13 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO12 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,PIO11 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,PIO10 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,PIO9 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,PIO8 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,PIO7 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,PIO6 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO5 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO4 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO3 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO2 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO1 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO0 Status" "Peripheral,PIO"
|
|
else
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,PIO29 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,PIO28 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,PIO27 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,PIO26 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,PIO25 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,PIO24 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,PIO23 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,PIO22 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,PIO21 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,PIO20 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,PIO19 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,PIO18 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,PIO17 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,PIO16 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,PIO15 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,PIO14 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,PIO13 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO12 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,PIO11 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,PIO10 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,PIO9 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,PIO8 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,PIO7 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,PIO6 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO5 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO4 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO3 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO2 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO1 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO0 Status" "Peripheral,PIO"
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PIO_IFSRD,PIO Controller Input Filter Status Register D"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,PIO29 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,PIO28 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,PIO27 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,PIO26 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,PIO25 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,PIO24 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,PIO23 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,PIO22 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,PIO21 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,PIO20 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,PIO19 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,PIO18 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,PIO17 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,PIO16 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,PIO15 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,PIO14 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,PIO13 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO12 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,PIO11 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,PIO10 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,PIO9 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,PIO8 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,PIO7 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,PIO6 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO5 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO4 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO3 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO2 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO1 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO0 Status" "Peripheral,PIO"
|
|
else
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,PIO29 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,PIO28 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,PIO27 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,PIO26 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,PIO25 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,PIO24 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,PIO23 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,PIO22 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,PIO21 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,PIO20 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,PIO19 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,PIO18 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,PIO17 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,PIO16 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,PIO15 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,PIO14 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,PIO13 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO12 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,PIO11 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,PIO10 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,PIO9 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,PIO8 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,PIO7 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,PIO6 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO5 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO4 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO3 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO2 Status" "Peripheral,PIO"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO1 Status" "Peripheral,PIO"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO0 Status" "Peripheral,PIO"
|
|
endif
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PIO_ODSRD,PIO Controller Output Data Status Register D"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Data Status 29" "Low,High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Data Status 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Data Status 25" "Low,High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Data Status 23" "Low,High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Data Status 21" "Low,High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Data Status 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Data Status 17" "Low,High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Data Status 15" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
else
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Data Status 29" "Low,High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Data Status 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Data Status 25" "Low,High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Data Status 23" "Low,High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Data Status 21" "Low,High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Data Status 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Data Status 17" "Low,High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Data Status 15" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Data Status 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Data Status 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Data Status 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Data Status 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Data Status 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Data Status 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Data Status 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Data Status 0" "Low,High"
|
|
endif
|
|
rgroup.long 0x3c++0x03
|
|
line.long 0x00 "PIO_PDSRD,PIO Controller Pin Data Status Register D"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 29. " P29 ,Output Data Status 29" "Low,High"
|
|
bitfld.long 0x00 28. " P28 ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Output Data Status 27" "Low,High"
|
|
bitfld.long 0x00 26. " P26 ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Output Data Status 25" "Low,High"
|
|
bitfld.long 0x00 24. " P24 ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Output Data Status 23" "Low,High"
|
|
bitfld.long 0x00 22. " P22 ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Output Data Status 21" "Low,High"
|
|
bitfld.long 0x00 20. " P20 ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Output Data Status 19" "Low,High"
|
|
bitfld.long 0x00 18. " P18 ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Output Data Status 17" "Low,High"
|
|
bitfld.long 0x00 16. " P16 ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Output Data Status 15" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Data Status 13" "Low,High"
|
|
bitfld.long 0x00 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x00 10. " P10 ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x00 8. " P8 ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Data Status 7" "Low,High"
|
|
bitfld.long 0x00 6. " P6 ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x00 4. " P4 ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x00 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Data Status 1" "Low,High"
|
|
bitfld.long 0x00 0. " P0 ,Output Data Status 0" "Low,High"
|
|
else
|
|
bitfld.long 0x00 29. " P29 ,Output Data Status 29" "Low,High"
|
|
bitfld.long 0x00 28. " P28 ,Output Data Status 28" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Output Data Status 27" "Low,High"
|
|
bitfld.long 0x00 26. " P26 ,Output Data Status 26" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Output Data Status 25" "Low,High"
|
|
bitfld.long 0x00 24. " P24 ,Output Data Status 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Output Data Status 23" "Low,High"
|
|
bitfld.long 0x00 22. " P22 ,Output Data Status 22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Output Data Status 21" "Low,High"
|
|
bitfld.long 0x00 20. " P20 ,Output Data Status 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Output Data Status 19" "Low,High"
|
|
bitfld.long 0x00 18. " P18 ,Output Data Status 18" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Output Data Status 17" "Low,High"
|
|
bitfld.long 0x00 16. " P16 ,Output Data Status 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Output Data Status 15" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Output Data Status 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Output Data Status 13" "Low,High"
|
|
bitfld.long 0x00 12. " P12 ,Output Data Status 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Output Data Status 11" "Low,High"
|
|
bitfld.long 0x00 10. " P10 ,Output Data Status 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Output Data Status 9" "Low,High"
|
|
bitfld.long 0x00 8. " P8 ,Output Data Status 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Output Data Status 7" "Low,High"
|
|
bitfld.long 0x00 6. " P6 ,Output Data Status 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Output Data Status 5" "Low,High"
|
|
bitfld.long 0x00 4. " P4 ,Output Data Status 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Output Data Status 3" "Low,High"
|
|
bitfld.long 0x00 2. " P2 ,Output Data Status 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Output Data Status 1" "Low,High"
|
|
bitfld.long 0x00 0. " P0 ,Output Data Status 0" "Low,High"
|
|
endif
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PIO_IMRD,PIO Controller Interrupt Mask Register D"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Input Change Interrupt Data Status 29" "Low,High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Input Change Interrupt Data Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Input Change Interrupt Data Status 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Input Change Interrupt Data Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Input Change Interrupt Data Status 25" "Low,High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Input Change Interrupt Data Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Input Change Interrupt Data Status 23" "Low,High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Input Change Interrupt Data Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Input Change Interrupt Data Status 21" "Low,High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Input Change Interrupt Data Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Input Change Interrupt Data Status 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Input Change Interrupt Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Input Change Interrupt Data Status 17" "Low,High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Input Change Interrupt Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Input Change Interrupt Data Status 15" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Input Change Interrupt Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Input Change Interrupt Data Status 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Change Interrupt Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Change Interrupt Data Status 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Change Interrupt Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Change Interrupt Data Status 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Change Interrupt Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Change Interrupt Data Status 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Change Interrupt Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Change Interrupt Data Status 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Change Interrupt Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Change Interrupt Data Status 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Change Interrupt Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Change Interrupt Data Status 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Change Interrupt Data Status 0" "Low,High"
|
|
else
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Input Change Interrupt Data Status 29" "Low,High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Input Change Interrupt Data Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Input Change Interrupt Data Status 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Input Change Interrupt Data Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Input Change Interrupt Data Status 25" "Low,High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Input Change Interrupt Data Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Input Change Interrupt Data Status 23" "Low,High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Input Change Interrupt Data Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Input Change Interrupt Data Status 21" "Low,High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Input Change Interrupt Data Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Input Change Interrupt Data Status 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Input Change Interrupt Data Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Input Change Interrupt Data Status 17" "Low,High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Input Change Interrupt Data Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Input Change Interrupt Data Status 15" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Input Change Interrupt Data Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Input Change Interrupt Data Status 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Change Interrupt Data Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Change Interrupt Data Status 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Change Interrupt Data Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Change Interrupt Data Status 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Change Interrupt Data Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Change Interrupt Data Status 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Change Interrupt Data Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Change Interrupt Data Status 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Change Interrupt Data Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Change Interrupt Data Status 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Change Interrupt Data Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Change Interrupt Data Status 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Change Interrupt Data Status 0" "Low,High"
|
|
endif
|
|
hgroup.long 0x4c++0x03
|
|
hide.long 0x00 "PIO_ISRD,PIO Controller Interrupt Status Register D"
|
|
in
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "PIO_MDSRD,PIO Multi-Driver Status Register D"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,The Multi Drive Status 29" "Low,High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,The Multi Drive Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,The Multi Drive Status 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,The Multi Drive Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,The Multi Drive Status 25" "Low,High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,The Multi Drive Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,The Multi Drive Status 23" "Low,High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,The Multi Drive Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,The Multi Drive Status 21" "Low,High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,The Multi Drive Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,The Multi Drive Status 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,The Multi Drive Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,The Multi Drive Status 17" "Low,High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,The Multi Drive Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,The Multi Drive Status 15" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,The Multi Drive Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,The Multi Drive Status 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,The Multi Drive Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,The Multi Drive Status 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,The Multi Drive Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,The Multi Drive Status 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,The Multi Drive Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,The Multi Drive Status 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,The Multi Drive Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,The Multi Drive Status 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,The Multi Drive Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,The Multi Drive Status 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,The Multi Drive Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,The Multi Drive Status 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,The Multi Drive Status 0" "Low,High"
|
|
else
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,The Multi Drive Status 29" "Low,High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,The Multi Drive Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,The Multi Drive Status 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,The Multi Drive Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,The Multi Drive Status 25" "Low,High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,The Multi Drive Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,The Multi Drive Status 23" "Low,High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,The Multi Drive Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,The Multi Drive Status 21" "Low,High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,The Multi Drive Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,The Multi Drive Status 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,The Multi Drive Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,The Multi Drive Status 17" "Low,High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,The Multi Drive Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,The Multi Drive Status 15" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,The Multi Drive Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,The Multi Drive Status 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,The Multi Drive Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,The Multi Drive Status 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,The Multi Drive Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,The Multi Drive Status 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,The Multi Drive Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,The Multi Drive Status 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,The Multi Drive Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,The Multi Drive Status 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,The Multi Drive Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,The Multi Drive Status 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,The Multi Drive Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,The Multi Drive Status 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,The Multi Drive Status 0" "Low,High"
|
|
endif
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PIO_PUSRD,PIO Pull Up Status Register D"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Pull Up resistor Status 29" "Low,High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Pull Up resistor Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Pull Up resistor Status 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Pull Up resistor Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Pull Up resistor Status 25" "Low,High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Pull Up resistor Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Pull Up resistor Status 23" "Low,High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Pull Up resistor Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Pull Up resistor Status 21" "Low,High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Pull Up resistor Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Pull Up resistor Status 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Pull Up resistor Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Pull Up resistor Status 17" "Low,High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Pull Up resistor Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Pull Up resistor Status 15" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Pull Up resistor Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Pull Up resistor Status 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Pull Up resistor Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Pull Up resistor Status 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Pull Up resistor Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Pull Up resistor Status 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Pull Up resistor Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Pull Up resistor Status 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Pull Up resistor Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Pull Up resistor Status 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Pull Up resistor Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Pull Up resistor Status 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Pull Up resistor Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Pull Up resistor Status 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Pull Up resistor Status 0" "Low,High"
|
|
else
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Pull Up resistor Status 29" "Low,High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Pull Up resistor Status 28" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Pull Up resistor Status 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Pull Up resistor Status 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Pull Up resistor Status 25" "Low,High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Pull Up resistor Status 24" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Pull Up resistor Status 23" "Low,High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Pull Up resistor Status 22" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Pull Up resistor Status 21" "Low,High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Pull Up resistor Status 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Pull Up resistor Status 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Pull Up resistor Status 18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Pull Up resistor Status 17" "Low,High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Pull Up resistor Status 16" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Pull Up resistor Status 15" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Pull Up resistor Status 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Pull Up resistor Status 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Pull Up resistor Status 12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Pull Up resistor Status 11" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Pull Up resistor Status 10" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Pull Up resistor Status 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Pull Up resistor Status 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Pull Up resistor Status 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Pull Up resistor Status 6" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Pull Up resistor Status 5" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Pull Up resistor Status 4" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Pull Up resistor Status 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Pull Up resistor Status 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Pull Up resistor Status 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Pull Up resistor Status 0" "Low,High"
|
|
endif
|
|
group.long 0x70++0x7
|
|
line.long 0x00 "PIO_ABCDSR1,PIO Peripheral ABCD Select Register 1"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 29. " P29 ,Assigns the I/O line Status 29" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 28. " P28 ,Assigns the I/O line Status 28" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Assigns the I/O line Status 27" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 26. " P26 ,Assigns the I/O line Status 26" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Assigns the I/O line Status 25" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 24. " P24 ,Assigns the I/O line Status 24" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Assigns the I/O line Status 23" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 22. " P22 ,Assigns the I/O line Status 22" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Assigns the I/O line Status 21" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 20. " P20 ,Assigns the I/O line Status 20" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Assigns the I/O line Status 19" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 18. " P18 ,Assigns the I/O line Status 18" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Assigns the I/O line Status 17" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 16. " P16 ,Assigns the I/O line Status 16" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Assigns the I/O line Status 15" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Assigns the I/O line Status 14" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Assigns the I/O line Status 13" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 12. " P12 ,Assigns the I/O line Status 12" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Assigns the I/O line Status 11" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 10. " P10 ,Assigns the I/O line Status 10" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Assigns the I/O line Status 9" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 8. " P8 ,Assigns the I/O line Status 8" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Assigns the I/O line Status 7" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 6. " P6 ,Assigns the I/O line Status 6" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Assigns the I/O line Status 5" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 4. " P4 ,Assigns the I/O line Status 4" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Assigns the I/O line Status 3" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 2. " P2 ,Assigns the I/O line Status 2" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Assigns the I/O line Status 1" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 0. " P0 ,Assigns the I/O line Status 0" "Peripheral A/C,Peripheral B/D"
|
|
else
|
|
bitfld.long 0x00 29. " P29 ,Assigns the I/O line Status 29" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 28. " P28 ,Assigns the I/O line Status 28" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Assigns the I/O line Status 27" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 26. " P26 ,Assigns the I/O line Status 26" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,Assigns the I/O line Status 25" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 24. " P24 ,Assigns the I/O line Status 24" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Assigns the I/O line Status 23" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 22. " P22 ,Assigns the I/O line Status 22" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,Assigns the I/O line Status 21" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 20. " P20 ,Assigns the I/O line Status 20" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Assigns the I/O line Status 19" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 18. " P18 ,Assigns the I/O line Status 18" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,Assigns the I/O line Status 17" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 16. " P16 ,Assigns the I/O line Status 16" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Assigns the I/O line Status 15" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,Assigns the I/O line Status 14" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,Assigns the I/O line Status 13" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 12. " P12 ,Assigns the I/O line Status 12" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Assigns the I/O line Status 11" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 10. " P10 ,Assigns the I/O line Status 10" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,Assigns the I/O line Status 9" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 8. " P8 ,Assigns the I/O line Status 8" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Assigns the I/O line Status 7" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 6. " P6 ,Assigns the I/O line Status 6" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,Assigns the I/O line Status 5" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 4. " P4 ,Assigns the I/O line Status 4" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Assigns the I/O line Status 3" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 2. " P2 ,Assigns the I/O line Status 2" "Peripheral A/C,Peripheral B/D"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,Assigns the I/O line Status 1" "Peripheral A/C,Peripheral B/D"
|
|
bitfld.long 0x00 0. " P0 ,Assigns the I/O line Status 0" "Peripheral A/C,Peripheral B/D"
|
|
endif
|
|
line.long 0x04 "PIO_ABCDSR2,PIO Peripheral ABCD Select Register 2"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x04 29. " P29 ,Assigns the I/O line Status 29" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 28. " P28 ,Assigns the I/O line Status 28" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 27. " P27 ,Assigns the I/O line Status 27" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 26. " P26 ,Assigns the I/O line Status 26" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 25. " P25 ,Assigns the I/O line Status 25" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 24. " P24 ,Assigns the I/O line Status 24" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 23. " P23 ,Assigns the I/O line Status 23" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 22. " P22 ,Assigns the I/O line Status 22" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 21. " P21 ,Assigns the I/O line Status 21" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 20. " P20 ,Assigns the I/O line Status 20" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 19. " P19 ,Assigns the I/O line Status 19" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 18. " P18 ,Assigns the I/O line Status 18" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 17. " P17 ,Assigns the I/O line Status 17" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 16. " P16 ,Assigns the I/O line Status 16" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 15. " P15 ,Assigns the I/O line Status 15" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 14. " P14 ,Assigns the I/O line Status 14" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 13. " P13 ,Assigns the I/O line Status 13" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 12. " P12 ,Assigns the I/O line Status 12" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 11. " P11 ,Assigns the I/O line Status 11" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 10. " P10 ,Assigns the I/O line Status 10" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 9. " P9 ,Assigns the I/O line Status 9" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 8. " P8 ,Assigns the I/O line Status 8" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 7. " P7 ,Assigns the I/O line Status 7" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 6. " P6 ,Assigns the I/O line Status 6" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 5. " P5 ,Assigns the I/O line Status 5" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 4. " P4 ,Assigns the I/O line Status 4" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 3. " P3 ,Assigns the I/O line Status 3" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 2. " P2 ,Assigns the I/O line Status 2" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 1. " P1 ,Assigns the I/O line Status 1" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 0. " P0 ,Assigns the I/O line Status 0" "Peripheral A/B,Peripheral C/D"
|
|
else
|
|
bitfld.long 0x04 29. " P29 ,Assigns the I/O line Status 29" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 28. " P28 ,Assigns the I/O line Status 28" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 27. " P27 ,Assigns the I/O line Status 27" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 26. " P26 ,Assigns the I/O line Status 26" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 25. " P25 ,Assigns the I/O line Status 25" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 24. " P24 ,Assigns the I/O line Status 24" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 23. " P23 ,Assigns the I/O line Status 23" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 22. " P22 ,Assigns the I/O line Status 22" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 21. " P21 ,Assigns the I/O line Status 21" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 20. " P20 ,Assigns the I/O line Status 20" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 19. " P19 ,Assigns the I/O line Status 19" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 18. " P18 ,Assigns the I/O line Status 18" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 17. " P17 ,Assigns the I/O line Status 17" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 16. " P16 ,Assigns the I/O line Status 16" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 15. " P15 ,Assigns the I/O line Status 15" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 14. " P14 ,Assigns the I/O line Status 14" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 13. " P13 ,Assigns the I/O line Status 13" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 12. " P12 ,Assigns the I/O line Status 12" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 11. " P11 ,Assigns the I/O line Status 11" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 10. " P10 ,Assigns the I/O line Status 10" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 9. " P9 ,Assigns the I/O line Status 9" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 8. " P8 ,Assigns the I/O line Status 8" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 7. " P7 ,Assigns the I/O line Status 7" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 6. " P6 ,Assigns the I/O line Status 6" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 5. " P5 ,Assigns the I/O line Status 5" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 4. " P4 ,Assigns the I/O line Status 4" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 3. " P3 ,Assigns the I/O line Status 3" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 2. " P2 ,Assigns the I/O line Status 2" "Peripheral A/B,Peripheral C/D"
|
|
textline " "
|
|
bitfld.long 0x04 1. " P1 ,Assigns the I/O line Status 1" "Peripheral A/B,Peripheral C/D"
|
|
bitfld.long 0x04 0. " P0 ,Assigns the I/O line Status 0" "Peripheral A/B,Peripheral C/D"
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")&&!cpuis("AT91SAM3X*"))
|
|
endif
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "PIO_IFDGSR,PIO Glitch or Debouncing Input Filter Selection Status Register"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " P29_set/clr ,Glitch or Debouncing Filter Selection Status 29" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " P28_set/clr ,Glitch or Debouncing Filter Selection Status 28" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " P27_set/clr ,Glitch or Debouncing Filter Selection Status 27" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " P26_set/clr ,Glitch or Debouncing Filter Selection Status 26" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " P25_set/clr ,Glitch or Debouncing Filter Selection Status 25" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " P24_set/clr ,Glitch or Debouncing Filter Selection Status 24" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23_set/clr ,Glitch or Debouncing Filter Selection Status 23" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22_set/clr ,Glitch or Debouncing Filter Selection Status 22" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21_set/clr ,Glitch or Debouncing Filter Selection Status 21" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20_set/clr ,Glitch or Debouncing Filter Selection Status 20" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19_set/clr ,Glitch or Debouncing Filter Selection Status 19" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18_set/clr ,Glitch or Debouncing Filter Selection Status 18" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17_set/clr ,Glitch or Debouncing Filter Selection Status 17" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16_set/clr ,Glitch or Debouncing Filter Selection Status 16" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_set/clr ,Glitch or Debouncing Filter Selection Status 15" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Glitch or Debouncing Filter Selection Status 14" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Glitch or Debouncing Filter Selection Status 13" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Glitch or Debouncing Filter Selection Status 12" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Glitch or Debouncing Filter Selection Status 11" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Glitch or Debouncing Filter Selection Status 10" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Glitch or Debouncing Filter Selection Status 9" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Glitch or Debouncing Filter Selection Status 8" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Glitch or Debouncing Filter Selection Status 7" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Glitch or Debouncing Filter Selection Status 6" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Glitch or Debouncing Filter Selection Status 5" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Glitch or Debouncing Filter Selection Status 4" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Glitch or Debouncing Filter Selection Status 3" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Glitch or Debouncing Filter Selection Status 2" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr1 ,Glitch or Debouncing Filter Selection Status 1" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Glitch or Debouncing Filter Selection Status 0" "Glitch,Debouncing"
|
|
else
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " P29_set/clr ,Glitch or Debouncing Filter Selection Status 29" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " P28_set/clr ,Glitch or Debouncing Filter Selection Status 28" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " P27_set/clr ,Glitch or Debouncing Filter Selection Status 27" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " P26_set/clr ,Glitch or Debouncing Filter Selection Status 26" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " P25_set/clr ,Glitch or Debouncing Filter Selection Status 25" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " P24_set/clr ,Glitch or Debouncing Filter Selection Status 24" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23_set/clr ,Glitch or Debouncing Filter Selection Status 23" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22_set/clr ,Glitch or Debouncing Filter Selection Status 22" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21_set/clr ,Glitch or Debouncing Filter Selection Status 21" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20_set/clr ,Glitch or Debouncing Filter Selection Status 20" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19_set/clr ,Glitch or Debouncing Filter Selection Status 19" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18_set/clr ,Glitch or Debouncing Filter Selection Status 18" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17_set/clr ,Glitch or Debouncing Filter Selection Status 17" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16_set/clr ,Glitch or Debouncing Filter Selection Status 16" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_set/clr ,Glitch or Debouncing Filter Selection Status 15" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Glitch or Debouncing Filter Selection Status 14" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Glitch or Debouncing Filter Selection Status 13" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Glitch or Debouncing Filter Selection Status 12" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Glitch or Debouncing Filter Selection Status 11" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Glitch or Debouncing Filter Selection Status 10" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Glitch or Debouncing Filter Selection Status 9" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Glitch or Debouncing Filter Selection Status 8" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Glitch or Debouncing Filter Selection Status 7" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Glitch or Debouncing Filter Selection Status 6" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Glitch or Debouncing Filter Selection Status 5" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Glitch or Debouncing Filter Selection Status 4" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Glitch or Debouncing Filter Selection Status 3" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Glitch or Debouncing Filter Selection Status 2" "Glitch,Debouncing"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr1 ,Glitch or Debouncing Filter Selection Status 1" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Glitch or Debouncing Filter Selection Status 0" "Glitch,Debouncing"
|
|
endif
|
|
group.long 0x8c++0x3
|
|
line.long 0x00 "PIO_SCDR,PIO Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow Clock Divider Selection for Debouncing"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "PIO_OWSRD,PIO Output Write Status Register D"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Write Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Write Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Write Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Write Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Write Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Write Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Write Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Write Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Write Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Write Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Write Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Write Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Write Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Write Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Write Status 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Write Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Write Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Write Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Write Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Write Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Write Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Write Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Write Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Write Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Write Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Write Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Write Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Write Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Output Write Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Write Status 0" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Write Status 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Write Status 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Write Status 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Write Status 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Write Status 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Write Status 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Write Status 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Write Status 22" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Write Status 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Write Status 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Write Status 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Write Status 18" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Write Status 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Write Status 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Write Status 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Write Status 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Write Status 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Write Status 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Write Status 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Write Status 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Write Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Write Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Write Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Write Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Write Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Write Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Write Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Write Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Output Write Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Write Status 0" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xB8++0x3
|
|
line.long 0x00 "PIO_AIMMR,Additional Interrupt Modes Mask Register"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Peripheral CD Status 29" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Peripheral CD Status 28" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Peripheral CD Status 27" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Peripheral CD Status 26" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Peripheral CD Status 25" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Peripheral CD Status 24" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Peripheral CD Status 23" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Peripheral CD Status 22" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Peripheral CD Status 21" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Peripheral CD Status 20" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Peripheral CD Status 19" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Peripheral CD Status 18" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Peripheral CD Status 17" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Peripheral CD Status 16" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Peripheral CD Status 15" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Peripheral CD Status 14" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Peripheral CD Status 13" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Peripheral CD Status 12" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Peripheral CD Status 11" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Peripheral CD Status 10" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Peripheral CD Status 9" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Peripheral CD Status 8" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Peripheral CD Status 7" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Peripheral CD Status 6" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Peripheral CD Status 5" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Peripheral CD Status 4" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Peripheral CD Status 3" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Peripheral CD Status 2" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Peripheral CD Status 1" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Peripheral CD Status 0" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
else
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Peripheral CD Status 29" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Peripheral CD Status 28" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Peripheral CD Status 27" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Peripheral CD Status 26" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Peripheral CD Status 25" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Peripheral CD Status 24" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Peripheral CD Status 23" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Peripheral CD Status 22" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Peripheral CD Status 21" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Peripheral CD Status 20" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Peripheral CD Status 19" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Peripheral CD Status 18" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Peripheral CD Status 17" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Peripheral CD Status 16" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Peripheral CD Status 15" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Peripheral CD Status 14" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Peripheral CD Status 13" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Peripheral CD Status 12" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Peripheral CD Status 11" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Peripheral CD Status 10" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Peripheral CD Status 9" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Peripheral CD Status 8" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Peripheral CD Status 7" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Peripheral CD Status 6" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Peripheral CD Status 5" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Peripheral CD Status 4" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Peripheral CD Status 3" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Peripheral CD Status 2" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Peripheral CD Status 1" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Peripheral CD Status 0" "Both edge detection,PIO_ELSR and PIO_FRLHSR"
|
|
endif
|
|
group.long 0xC8++0x3
|
|
line.long 0x00 "PIO_ELSR,Edge/Level Status Register"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Edge/Level Interrupt source selection 29" "Edge,Level"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Edge/Level Interrupt source selection 28" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Edge/Level Interrupt source selection 27" "Edge,Level"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Edge/Level Interrupt source selection 26" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Edge/Level Interrupt source selection 25" "Edge,Level"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Edge/Level Interrupt source selection 24" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Edge/Level Interrupt source selection 23" "Edge,Level"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Edge/Level Interrupt source selection 22" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Edge/Level Interrupt source selection 21" "Edge,Level"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Edge/Level Interrupt source selection 20" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Edge/Level Interrupt source selection 19" "Edge,Level"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Edge/Level Interrupt source selection 18" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Edge/Level Interrupt source selection 17" "Edge,Level"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Edge/Level Interrupt source selection 16" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Edge/Level Interrupt source selection 15" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Edge/Level Interrupt source selection 14" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Edge/Level Interrupt source selection 13" "Edge,Level"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Edge/Level Interrupt source selection 12" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Edge/Level Interrupt source selection 11" "Edge,Level"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Edge/Level Interrupt source selection 10" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Edge/Level Interrupt source selection 9" "Edge,Level"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Edge/Level Interrupt source selection 8" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Edge/Level Interrupt source selection 7" "Edge,Level"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Edge/Level Interrupt source selection 6" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Edge/Level Interrupt source selection 5" "Edge,Level"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Edge/Level Interrupt source selection 4" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Edge/Level Interrupt source selection 3" "Edge,Level"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Edge/Level Interrupt source selection 2" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Edge/Level Interrupt source selection 1" "Edge,Level"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection 0" "Edge,Level"
|
|
else
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Edge/Level Interrupt source selection 29" "Edge,Level"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Edge/Level Interrupt source selection 28" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Edge/Level Interrupt source selection 27" "Edge,Level"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Edge/Level Interrupt source selection 26" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Edge/Level Interrupt source selection 25" "Edge,Level"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Edge/Level Interrupt source selection 24" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Edge/Level Interrupt source selection 23" "Edge,Level"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Edge/Level Interrupt source selection 22" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Edge/Level Interrupt source selection 21" "Edge,Level"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Edge/Level Interrupt source selection 20" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Edge/Level Interrupt source selection 19" "Edge,Level"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Edge/Level Interrupt source selection 18" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Edge/Level Interrupt source selection 17" "Edge,Level"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Edge/Level Interrupt source selection 16" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Edge/Level Interrupt source selection 15" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Edge/Level Interrupt source selection 14" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Edge/Level Interrupt source selection 13" "Edge,Level"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Edge/Level Interrupt source selection 12" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Edge/Level Interrupt source selection 11" "Edge,Level"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Edge/Level Interrupt source selection 10" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Edge/Level Interrupt source selection 9" "Edge,Level"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Edge/Level Interrupt source selection 8" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Edge/Level Interrupt source selection 7" "Edge,Level"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Edge/Level Interrupt source selection 6" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Edge/Level Interrupt source selection 5" "Edge,Level"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Edge/Level Interrupt source selection 4" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Edge/Level Interrupt source selection 3" "Edge,Level"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Edge/Level Interrupt source selection 2" "Edge,Level"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Edge/Level Interrupt source selection 1" "Edge,Level"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection 0" "Edge,Level"
|
|
endif
|
|
group.long 0xd8++0x3
|
|
line.long 0x00 "PIO_FRLHSR,Fall/Rise - Low/High Status Register"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Edge/Level Interrupt source selection 29 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Edge/Level Interrupt source selection 28 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Edge/Level Interrupt source selection 27 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Edge/Level Interrupt source selection 26 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Edge/Level Interrupt source selection 25 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Edge/Level Interrupt source selection 24 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Edge/Level Interrupt source selection 23 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Edge/Level Interrupt source selection 22 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Edge/Level Interrupt source selection 21 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Edge/Level Interrupt source selection 20 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Edge/Level Interrupt source selection 19 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Edge/Level Interrupt source selection 18 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Edge/Level Interrupt source selection 17 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Edge/Level Interrupt source selection 16 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Edge/Level Interrupt source selection 15 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Edge/Level Interrupt source selection 14 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Edge/Level Interrupt source selection 13 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Edge/Level Interrupt source selection 12 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Edge/Level Interrupt source selection 11 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Edge/Level Interrupt source selection 10 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Edge/Level Interrupt source selection 9 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Edge/Level Interrupt source selection 8 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Edge/Level Interrupt source selection 7 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Edge/Level Interrupt source selection 6 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Edge/Level Interrupt source selection 5 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Edge/Level Interrupt source selection 4 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Edge/Level Interrupt source selection 3 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Edge/Level Interrupt source selection 2 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Edge/Level Interrupt source selection 1 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection 0 (Edge/Level)" "Falling/Low,Rising/High"
|
|
else
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Edge/Level Interrupt source selection 29 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Edge/Level Interrupt source selection 28 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Edge/Level Interrupt source selection 27 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Edge/Level Interrupt source selection 26 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Edge/Level Interrupt source selection 25 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Edge/Level Interrupt source selection 24 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Edge/Level Interrupt source selection 23 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Edge/Level Interrupt source selection 22 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Edge/Level Interrupt source selection 21 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Edge/Level Interrupt source selection 20 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Edge/Level Interrupt source selection 19 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Edge/Level Interrupt source selection 18 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Edge/Level Interrupt source selection 17 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Edge/Level Interrupt source selection 16 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Edge/Level Interrupt source selection 15 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Edge/Level Interrupt source selection 14 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Edge/Level Interrupt source selection 13 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Edge/Level Interrupt source selection 12 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Edge/Level Interrupt source selection 11 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Edge/Level Interrupt source selection 10 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Edge/Level Interrupt source selection 9 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Edge/Level Interrupt source selection 8 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Edge/Level Interrupt source selection 7 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Edge/Level Interrupt source selection 6 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Edge/Level Interrupt source selection 5 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Edge/Level Interrupt source selection 4 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Edge/Level Interrupt source selection 3 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Edge/Level Interrupt source selection 2 (Edge/Level)" "Falling/Low,Rising/High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr1 ,Edge/Level Interrupt source selection 1 (Edge/Level)" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Edge/Level Interrupt source selection 0 (Edge/Level)" "Falling/Low,Rising/High"
|
|
endif
|
|
rgroup.long 0xe0++0x3
|
|
line.long 0x00 "PIO_LOCKSR,Lock Status Register"
|
|
sif (cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 29. " P29 ,I/O line 29 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 28. " P28 ,I/O line 28 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,I/O line 27 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " P26 ,I/O line 26 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,I/O line 25 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 24. " P24 ,I/O line 24 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,I/O line 23 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 22. " P22 ,I/O line 22 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,I/O line 21 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 20. " P20 ,I/O line 20 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,I/O line 19 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 18. " P18 ,I/O line 18 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,I/O line 17 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 16. " P16 ,I/O line 16 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,I/O line 15 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,I/O line 14 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,I/O line 13 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " P12 ,I/O line 12 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,I/O line 11 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " P10 ,I/O line 10 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,I/O line 9 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " P8 ,I/O line 8 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,I/O line 7 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " P6 ,I/O line 6 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,I/O line 5 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " P4 ,I/O line 4 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,I/O line 3 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " P2 ,I/O line 2 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,I/O line 1 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " P0 ,I/O line 0 Lock Status" "Not locked,Locked"
|
|
else
|
|
bitfld.long 0x00 29. " P29 ,I/O line 29 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 28. " P28 ,I/O line 28 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,I/O line 27 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " P26 ,I/O line 26 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " P25 ,I/O line 25 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 24. " P24 ,I/O line 24 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,I/O line 23 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 22. " P22 ,I/O line 22 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P21 ,I/O line 21 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 20. " P20 ,I/O line 20 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,I/O line 19 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 18. " P18 ,I/O line 18 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P17 ,I/O line 17 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 16. " P16 ,I/O line 16 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,I/O line 15 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 14. " P14 ,I/O line 14 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P13 ,I/O line 13 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " P12 ,I/O line 12 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,I/O line 11 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " P10 ,I/O line 10 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P9 ,I/O line 9 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " P8 ,I/O line 8 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,I/O line 7 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " P6 ,I/O line 6 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5 ,I/O line 5 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " P4 ,I/O line 4 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,I/O line 3 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " P2 ,I/O line 2 Lock Status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1 ,I/O line 1 Lock Status" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " P0 ,I/O line 0 Lock Status" "Not locked,Locked"
|
|
endif
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "PIO_WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect Enable"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PIO_WPSR,Write Protect Violation Status"
|
|
in
|
|
width 13.
|
|
sif (!cpuis("AT91SAM3A*")&&!cpuis("AT91SAM3X4C")&&!cpuis("AT91SAM3X4E")&&!cpuis("AT91SAM3X8C")&&!cpuis("AT91SAM3X8E"))
|
|
group.long 0xF50++0x3
|
|
line.long 0x00 "PIO_PCMR,PIO Parallel Capture Mode Register"
|
|
bitfld.long 0x00 11. " FRSTS ,Parallel Capture Mode First Sample" "Even index,Odd index"
|
|
bitfld.long 0x00 10. " HALFS ,Parallel Capture Mode Half Sampling" "All data,One time out of two"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ALWYS ,Parallel Capture Mode Always Sampling" "No,Yes"
|
|
bitfld.long 0x00 4.--5. " DSIZE ,Parallel Capture Mode Data Size" "8 bit,16 bit,32 bit,32 bit"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PCEN ,Parallel Capture Mode Enable" "Disabled,Enabled"
|
|
rgroup.long 0xF5C++0x3
|
|
line.long 0x00 "PIO_PCIMR,PIO Parallel Capture Interrupt Mask Register"
|
|
bitfld.long 0x00 3. " RXBUFF ,Reception Buffer Full Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " ENDRX ,End of Reception Transfer Interrupt Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OVRE ,Parallel Capture Mode Overrun Error Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " DRDY ,Parallel Capture Mode Data Ready Interrupt Mask" "Not masked,Masked"
|
|
group.long 0xF60++0x3
|
|
line.long 0x00 "PIO_PCISR,PIO Parallel Capture Interrupt Status Register"
|
|
setclrfld.long 0x00 3. -0x0C 3. -0x08 3. " RXBUFF_set/clr ,Reception Buffer Full Interrupt Status" "Inactive,Active"
|
|
setclrfld.long 0x00 2. -0x0C 2. -0x08 2. " ENDRX_set/clr ,End of Reception Transfer Interrupt Status" "Inactive,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x0C 1. -0x08 1. " OVRE_set/clr ,Parallel Capture Mode Overrun Error Interrupt Status" "No error,Error"
|
|
setclrfld.long 0x00 0. -0x0C 0. -0x08 0. " DRDY_set/clr ,Parallel Capture Mode Data Ready Interrupt Status" "Not ready,Ready"
|
|
if ((d.l(ad:0x0+0xf50)&0x30)==0x00)
|
|
rgroup.long 0xF64++0x3
|
|
line.long 0x00 "PIO_PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
hexmask.long.byte 0x00 0.--8. 1. " RDATA ,Parallel Capture Mode Reception Data"
|
|
elif ((d.l(ad:0x0+0xf50)&0x30)==0x10)
|
|
rgroup.long 0xF64++0x3
|
|
line.long 0x00 "PIO_PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
hexmask.long.word 0x00 0.--16. 1. " RDATA ,Parallel Capture Mode Reception Data"
|
|
else
|
|
rgroup.long 0xF64++0x3
|
|
line.long 0x00 "PIO_PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
endif
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree.open "SPI (Serial Peripheral Interface)"
|
|
tree "SPI0"
|
|
base ad:0x40008000
|
|
width 13.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,SPI Control Register"
|
|
sif cpuis("ATSAME70*")
|
|
bitfld.long 0x00 31. "FIFODIS,FIFO disable" "No effect,Disabled"
|
|
bitfld.long 0x00 30. "FIFOEN,FIFO enable" "No effect,Enabled"
|
|
endif
|
|
bitfld.long 0x00 24. " LASTXFER ,Last transfer" "No effect,Deasserted"
|
|
sif cpuis("ATSAME70*")
|
|
bitfld.long 0x00 17. "RXFCLR,Receive FIFO clear" "Di,Enabled"
|
|
bitfld.long 0x00 16. "TXFCLR,Transmit FIFO clear" "No effect,Transmitted"
|
|
endif
|
|
bitfld.long 0x00 7. " SWRST ,SPI software reset" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI disable" "No effect,Yes"
|
|
bitfld.long 0x00 0. " SPIEN ,SPI enable" "No effect,Enabled"
|
|
sif cpuis("ATSAM4S*")||cpuis("ATSAMV7*")||cpuis("ATSAME70*")
|
|
if ((per.l(ad:0x40008000+0xE4)&0x01)==0x00)
|
|
if (((per.l((ad:0x40008000+0x04)))&0x07)==0x01)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x07)==0x05)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x07)==(0x03||0x07))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x07)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x07)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects belay"
|
|
newline
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
endif
|
|
else
|
|
if (((per.l((ad:0x40008000+0x04)))&0x07)==0x01)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x07)==0x05)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x07)==(0x03||0x07))
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x07)==0x00)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x07)==0x04)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l((ad:0x40008000+0x04)))&0x07)==0x01)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x07)==0x05)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x07)==(0x03||0x07))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x07)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x07)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
endif
|
|
endif
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "RDR,SPI Receive Data Register"
|
|
in
|
|
if (((per.l((ad:0x40008000+0x04)))&0x06)==0x02)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last transfer" "No effect,Deasserted"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit data"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x06)==0x06)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last transfer" "No effect,Deasserted"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit data"
|
|
else
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "TDR,SPI Transmit Data Register"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit data"
|
|
endif
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SR,SPI Status Register"
|
|
in
|
|
sif cpuis("AT91SAM3S*")||cpuis("AT91SAM3N*")||cpuis("ATSAM4E*")||cpuis("ATSAM4S*")||cpuis("ATSAMG51")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "IMR_SET/CLR,SPI Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNDES ,Underrun error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY ,Transmission registers empty mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NSSR ,NSS rising interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " TXBUFE ,Transmit buffer empty interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " RXBUFF ,Receive buffer full interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " ENDTX ,End of transmit buffer interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDRX ,End of receive buffer interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " OVRES ,Overrun error interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " MODF ,Mode fault error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TDRE ,SPI transmit data register empty interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RDRF ,Receive data register full interrupt mask" "Masked,Unmasked"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "IMR_SET/CLR,SPI Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNDES ,Underrun error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY ,Transmission registers empty mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NSSR ,NSS rising interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " OVRES ,Overrun error interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " MODF ,Mode fault error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TDRE ,SPI transmit data register empty interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RDRF ,Receive data register full interrupt mask" "Masked,Unmasked"
|
|
endif
|
|
sif cpuis("ATSAM4S*")||cpuis("ATSAMV7*")||cpuis("ATSAME70*")
|
|
if ((per.l(ad:0x40008000+0xE4)&0x01)==0x00)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock bit rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
endif
|
|
if ((per.l(ad:0x40008000+0xE4)&0x01)==0x00)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock bit rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
else
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
endif
|
|
if ((per.l(ad:0x40008000+0xE4)&0x01)==0x00)
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CSR2,SPI Chip Select Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock bit rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
else
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "CSR2,SPI Chip Select Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
endif
|
|
if ((per.l(ad:0x40008000+0xE4)&0x01)==0x00)
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CSR3,SPI Chip Select Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock bit rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
else
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "CSR3,SPI Chip Select Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
endif
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CSR2,SPI Chip Select Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CSR3,SPI Chip Select Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,SPI write protection key password"
|
|
bitfld.long 0x00 0. " WPEN ,SPI write protection enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,SPI Write Protection Status Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
tree "SPI1"
|
|
base ad:0x4000C000
|
|
width 13.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,SPI Control Register"
|
|
sif cpuis("ATSAME70*")
|
|
bitfld.long 0x00 31. "FIFODIS,FIFO disable" "No effect,Disabled"
|
|
bitfld.long 0x00 30. "FIFOEN,FIFO enable" "No effect,Enabled"
|
|
endif
|
|
bitfld.long 0x00 24. " LASTXFER ,Last transfer" "No effect,Deasserted"
|
|
sif cpuis("ATSAME70*")
|
|
bitfld.long 0x00 17. "RXFCLR,Receive FIFO clear" "Di,Enabled"
|
|
bitfld.long 0x00 16. "TXFCLR,Transmit FIFO clear" "No effect,Transmitted"
|
|
endif
|
|
bitfld.long 0x00 7. " SWRST ,SPI software reset" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI disable" "No effect,Yes"
|
|
bitfld.long 0x00 0. " SPIEN ,SPI enable" "No effect,Enabled"
|
|
sif cpuis("ATSAM4S*")||cpuis("ATSAMV7*")||cpuis("ATSAME70*")
|
|
if ((per.l(ad:0x4000C000+0xE4)&0x01)==0x00)
|
|
if (((per.l((ad:0x4000C000+0x04)))&0x07)==0x01)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x4000C000+0x04)))&0x07)==0x05)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x4000C000+0x04)))&0x07)==(0x03||0x07))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x4000C000+0x04)))&0x07)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x4000C000+0x04)))&0x07)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects belay"
|
|
newline
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
endif
|
|
else
|
|
if (((per.l((ad:0x4000C000+0x04)))&0x07)==0x01)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x4000C000+0x04)))&0x07)==0x05)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x4000C000+0x04)))&0x07)==(0x03||0x07))
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x4000C000+0x04)))&0x07)==0x00)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x4000C000+0x04)))&0x07)==0x04)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l((ad:0x4000C000+0x04)))&0x07)==0x01)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x4000C000+0x04)))&0x07)==0x05)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x4000C000+0x04)))&0x07)==(0x03||0x07))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x4000C000+0x04)))&0x07)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x4000C000+0x04)))&0x07)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
endif
|
|
endif
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "RDR,SPI Receive Data Register"
|
|
in
|
|
if (((per.l((ad:0x4000C000+0x04)))&0x06)==0x02)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last transfer" "No effect,Deasserted"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit data"
|
|
elif (((per.l((ad:0x4000C000+0x04)))&0x06)==0x06)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last transfer" "No effect,Deasserted"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit data"
|
|
else
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "TDR,SPI Transmit Data Register"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit data"
|
|
endif
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SR,SPI Status Register"
|
|
in
|
|
sif cpuis("AT91SAM3S*")||cpuis("AT91SAM3N*")||cpuis("ATSAM4E*")||cpuis("ATSAM4S*")||cpuis("ATSAMG51")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "IMR_SET/CLR,SPI Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNDES ,Underrun error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY ,Transmission registers empty mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NSSR ,NSS rising interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " TXBUFE ,Transmit buffer empty interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " RXBUFF ,Receive buffer full interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " ENDTX ,End of transmit buffer interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDRX ,End of receive buffer interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " OVRES ,Overrun error interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " MODF ,Mode fault error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TDRE ,SPI transmit data register empty interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RDRF ,Receive data register full interrupt mask" "Masked,Unmasked"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "IMR_SET/CLR,SPI Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNDES ,Underrun error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY ,Transmission registers empty mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NSSR ,NSS rising interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " OVRES ,Overrun error interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " MODF ,Mode fault error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TDRE ,SPI transmit data register empty interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RDRF ,Receive data register full interrupt mask" "Masked,Unmasked"
|
|
endif
|
|
sif cpuis("ATSAM4S*")||cpuis("ATSAMV7*")||cpuis("ATSAME70*")
|
|
if ((per.l(ad:0x4000C000+0xE4)&0x01)==0x00)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock bit rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
endif
|
|
if ((per.l(ad:0x4000C000+0xE4)&0x01)==0x00)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock bit rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
else
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
endif
|
|
if ((per.l(ad:0x4000C000+0xE4)&0x01)==0x00)
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CSR2,SPI Chip Select Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock bit rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
else
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "CSR2,SPI Chip Select Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
endif
|
|
if ((per.l(ad:0x4000C000+0xE4)&0x01)==0x00)
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CSR3,SPI Chip Select Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock bit rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
else
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "CSR3,SPI Chip Select Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
endif
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CSR2,SPI Chip Select Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CSR3,SPI Chip Select Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
newline
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Low,High"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,SPI write protection key password"
|
|
bitfld.long 0x00 0. " WPEN ,SPI write protection enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,SPI Write Protection Status Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "TWI (Two-wire Interface)"
|
|
tree "TWI 0"
|
|
base ad:0x4008C000
|
|
width 16.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TWI_CR,TWI Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 6. " QUICK ,SMBUS Quick Command" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SVDIS ,TWI Slave Mode Disabled" "No effect,Disable"
|
|
bitfld.long 0x00 4. " SVEN ,TWI Slave Mode Enabled" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSDIS ,TWI Master Transfer Disabled" "No effect,Disable"
|
|
bitfld.long 0x00 2. " MSEN ,TWI Master Transfer Enabled" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STOP ,Send a STOP Condition" "No effect,Stop"
|
|
bitfld.long 0x00 0. " START ,Send a START Condition" "No effect,Start"
|
|
sif ((cpu()!="ATSAMG5*")||cpuis("ATSAM4S*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TWI_MMR,TWI Master Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " DADR ,Device Address"
|
|
bitfld.long 0x00 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal Device Address Size" "No address,One-byte,Two-byte,Three-byte"
|
|
endif
|
|
sif (cpuis("ATSAM4S*"))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,TWI Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " SADR ,Slave Address"
|
|
endif
|
|
if (((d.l((ad:0x4008C000+0x04)))&0x300)==0x300)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " IADR ,Internal Address"
|
|
elif (((d.l((ad:0x4008C000+0x04)))&0x300)==0x200)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " IADR ,Internal Address"
|
|
elif (((d.l((ad:0x4008C000+0x04)))&0x300)==0x100)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IADR ,Internal Address"
|
|
else
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
endif
|
|
sif cpuis("ATSAM4S*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
sif cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 24.--28. " HOLD ,TWD Hold Time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16.--18. " CKDIV ,Clock Divider" "1,2,4,8,16,32,64,128"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHDIV ,Clock High Divider"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLDIV ,Clock Low Divider"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TWI_SR,TWI Status Register"
|
|
in
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TWI_IMR,TWI Interrupt Mask Register"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " EOSACC_set/clr ,End Of Slave Access Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " SCL_WS_set/clr ,Clock Wait State Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " ARBLST_set/clr ,Arbitration Lost Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NACK_set/clr ,Not Acknowledge" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " OVRE_set/clr ,Overrun Error" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " GACC_set/clr ,General Call Access Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " SVACC_set/clr ,Slave Access Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " TXRDY_set/clr ,Transmit Holding Register Ready" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " RXRDY_set/clr ,Receive Holding Register Ready" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " TXCOMP_set/clr ,Transmission Completed" "Disabled,Enabled"
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "TWI_RHR,TWI Receive Holding Register"
|
|
in
|
|
sif cpuis("ATSAM4S*")
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Master or Slave Transmit Holding Data"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Master or Slave Transmit Holding Data"
|
|
endif
|
|
sif cpuis("ATSAM4E*")
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TWI_WPROT_MODE,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " SECURITY_CODE ,Write protection mode security code"
|
|
bitfld.long 0x00 0. " WPROT ,Write protection bit" "Disabled,Enabled"
|
|
sif (cpu()=="ATSAMG5*")
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "TWI_WPROT_STATUS,TWI Write Protection Status Register"
|
|
in
|
|
endif
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree "PDC (Peripheral DMA Controller)"
|
|
base ad:0x4008C000
|
|
width 11.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "TWI0_RPR,Receive Pointer Register"
|
|
line.long 0x04 "TWI0_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "TWI0_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "TWI0_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "TWI0_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "TWI0_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "TWI0_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "TWI0_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "TWI0_PTCR,PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enable"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "TWI0_PTSR,PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "TWI 1"
|
|
base ad:0x40090000
|
|
width 16.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "TWI_CR,TWI Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 6. " QUICK ,SMBUS Quick Command" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SVDIS ,TWI Slave Mode Disabled" "No effect,Disable"
|
|
bitfld.long 0x00 4. " SVEN ,TWI Slave Mode Enabled" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MSDIS ,TWI Master Transfer Disabled" "No effect,Disable"
|
|
bitfld.long 0x00 2. " MSEN ,TWI Master Transfer Enabled" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STOP ,Send a STOP Condition" "No effect,Stop"
|
|
bitfld.long 0x00 0. " START ,Send a START Condition" "No effect,Start"
|
|
sif ((cpu()!="ATSAMG5*")||cpuis("ATSAM4S*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TWI_MMR,TWI Master Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " DADR ,Device Address"
|
|
bitfld.long 0x00 12. " MREAD ,Master Read Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal Device Address Size" "No address,One-byte,Two-byte,Three-byte"
|
|
endif
|
|
sif (cpuis("ATSAM4S*"))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TWI_SMR,TWI Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " SADR ,Slave Address"
|
|
endif
|
|
if (((d.l((ad:0x40090000+0x04)))&0x300)==0x300)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " IADR ,Internal Address"
|
|
elif (((d.l((ad:0x40090000+0x04)))&0x300)==0x200)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " IADR ,Internal Address"
|
|
elif (((d.l((ad:0x40090000+0x04)))&0x300)==0x100)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IADR ,Internal Address"
|
|
else
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "TWI_IADR,TWI Internal Address Register"
|
|
endif
|
|
sif cpuis("ATSAM4S*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
sif cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 24.--28. " HOLD ,TWD Hold Time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16.--18. " CKDIV ,Clock Divider" "1,2,4,8,16,32,64,128"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHDIV ,Clock High Divider"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLDIV ,Clock Low Divider"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "TWI_SR,TWI Status Register"
|
|
in
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TWI_IMR,TWI Interrupt Mask Register"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " EOSACC_set/clr ,End Of Slave Access Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " SCL_WS_set/clr ,Clock Wait State Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " ARBLST_set/clr ,Arbitration Lost Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NACK_set/clr ,Not Acknowledge" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " OVRE_set/clr ,Overrun Error" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " GACC_set/clr ,General Call Access Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " SVACC_set/clr ,Slave Access Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " TXRDY_set/clr ,Transmit Holding Register Ready" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " RXRDY_set/clr ,Receive Holding Register Ready" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " TXCOMP_set/clr ,Transmission Completed" "Disabled,Enabled"
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "TWI_RHR,TWI Receive Holding Register"
|
|
in
|
|
sif cpuis("ATSAM4S*")
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Master or Slave Transmit Holding Data"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Master or Slave Transmit Holding Data"
|
|
endif
|
|
sif cpuis("ATSAM4E*")
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TWI_WPROT_MODE,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " SECURITY_CODE ,Write protection mode security code"
|
|
bitfld.long 0x00 0. " WPROT ,Write protection bit" "Disabled,Enabled"
|
|
sif (cpu()=="ATSAMG5*")
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "TWI_WPROT_STATUS,TWI Write Protection Status Register"
|
|
in
|
|
endif
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree "PDC (Peripheral DMA Controller)"
|
|
base ad:0x40090000
|
|
width 11.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "TWI1_RPR,Receive Pointer Register"
|
|
line.long 0x04 "TWI1_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "TWI1_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "TWI1_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "TWI1_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "TWI1_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "TWI1_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "TWI1_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "TWI1_PTCR,PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enable"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "TWI1_PTSR,PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
tree "UART (Universal Asynchronous Receiver Transmitter)"
|
|
tree "UART0"
|
|
base ad:0x400E0800
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,UART Control Register"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,UART Mode Register"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal Mode,Automatic Echo,Local Loopback,Remote Loopback"
|
|
sif (cpuis("ATSAMA5D31")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*")||cpuis("ATSAM4S*"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Space,Mark,No,?..."
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Space,Mark,No,No,No,No"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IMR,UART Interrupt Mask Register"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAMA5D36"))
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RXBUFF_set/clr ,RXBUFF Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TXBUFE_set/clr ,TXBUFE Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAMA5D36"))
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Masked,Not masked"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "SR,UART Status Register"
|
|
in
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "RHR,UART Receiver Holding Register"
|
|
in
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "THR,Transmitter Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "BRGR,UART Baud Rate Generator Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
width 0x0B
|
|
tree "PDC (Peripheral DMA Controller)"
|
|
base ad:0x400E0800
|
|
width 11.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "UART_RPR,Receive Pointer Register"
|
|
line.long 0x04 "UART_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "UART_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "UART_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "UART_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "UART_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "UART_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "UART_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "UART_PTCR,PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enable"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "UART_PTSR,PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
tree.open "USART (Universal Synchronous Asynchronous Receiver Transmitter)"
|
|
tree "USART 0"
|
|
base ad:0x40098000
|
|
width 10.
|
|
if ((d.l((ad:0x40098000)+0x4)&0xF)==(0xE||0xF))
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
sif (!cpuis("AT91SAM3N*")&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select" "No effect,Slave Select Line NSS = 0"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("AT91SAM3N*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
if ((d.l((ad:0x40098000+0x04))&0x0f)==(0x0e||0x0f))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*")&&!cpuis("ATSAMA5D36"))
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
hexmask.long.byte 0x00 24.--26. 1. " MAX_ITERATION ,Maximum Number of Iterations"
|
|
bitfld.long 0x00 23. " INVDATA ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 20. " WRDBT ,Wait Read Data Before Transfer" "No,Yes"
|
|
else
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Inactive-Low,Inactive-High"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))||(cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
elif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/Captured,Captured/Changed"
|
|
sif cpuis("ATSAM4E*")||cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" ",,,8 bits"
|
|
else
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "CLK_USART,CLK_USART/8,,CLK"
|
|
else
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK / 8,,SCK"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
elif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" ",,,,,,,,,,,,,,SPI Master,SPI Slave"
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
elif ((d.l((ad:0x40098000+0x04))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
hexmask.long.byte 0x00 24.--26. 1. " MAX_ITERATION ,Maximum Number of Iterations"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Not inverted,Inverted"
|
|
textline " "
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
textline " "
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "CLK_USART,CLK_USART/8,,CLK"
|
|
else
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK / 8,,SCK"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
hexmask.long.byte 0x00 24.--26. 1. " MAX_ITERATION ,Maximum Number of Iterations"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Not inverted,Inverted"
|
|
textline " "
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,1.5,2,?..."
|
|
textline " "
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "CLK_USART,CLK_USART/8,,CLK"
|
|
else
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK / 8,,SCK"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
endif
|
|
if (((d.l((ad:0x40098000+0x4))&0x1f)==0xE)||(d.l((ad:0x40098000+0x4))&0x1f)==0xF)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Enable/Mask Register"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
sif (cpuis("AT91SAM3N*"))
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 31. -0x8 31. -0x4 31. " LINHTE_set/clr ,LIN Header Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x8 30. -0x4 30. " LINSTE_set/clr ,LIN Sync Tolerance Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Sync Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bit Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANEA_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x8 20. -0x4 20. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*"))
|
|
sif !cpuis("ATSAM4N*")
|
|
setclrfld.long 0x00 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("ATSAM4E*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Max number of Repetitions Reached/SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
elif (cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " UNRE_set/clr ,SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*"))
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Enable/Mask Register"
|
|
sif (cpuis("AT91SAM3N*")||cpuis("ATSAM4N*"))
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 31. -0x8 31. -0x4 31. " LINHTE_set/clr ,LIN Header Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x8 30. -0x4 30. " LINSTE_set/clr ,LIN Sync Tolerance Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Sync Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bit Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANEA_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x8 20. -0x4 20. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAMA5D3*"))
|
|
setclrfld.long 0x00 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Max number of Repetitions Reached/SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
elif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITER_set/clr ,Max number of Repetitions Reached Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*")&&!cpuis("ATSAMA5D3*"))
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x0 "US_CSR,Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "US_RHR,Receiver Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US_THR,Transmitter Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20--0x2b
|
|
line.long 0x00 "US_BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1 x 1/8,2 x 1/8,3 x 1/8,4 x 1/8,5 x 1/8,6 x 1/8,7 x 1/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US_RTOR,Receiver Time-out Register"
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " TO ,Time-out Value"
|
|
else
|
|
hexmask.long.tbyte 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
endif
|
|
line.long 0x08 "US_TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US_FIDI,FI DI Ratio Register"
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
else
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("ATSAM4N*"))
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US_NER,Number of Errors Register"
|
|
in
|
|
else
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "US_NER,Number of Errors Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " NB_ERRORS ,Number of Errors"
|
|
endif
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US_IF,USART IrDA FILTER Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
width 10.
|
|
sif (!cpuis("AT91SAM3N*")&&!cpuis("ATSAM4N*"))
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT , Drift Compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ONE ,Must be set to 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RX_MPOL , Receiver Manchester Polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 24.--25. " RX_PP , Receiver Preamble Pattern Detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " RX_PL , Receiver Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
bitfld.long 0x00 12. " TX_MPOL , Transmitter Manchester Polarity" "0-to-1,1-to-0"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TX_PP , Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 0.--3. " TX_PL , Transmitter Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long 0x54++0x7
|
|
line.long 0x00 "US_LINMR,USART LIN Mode Register"
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 17. " SYNCDIS ,Synchronization Disable" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16. " PDCM ,PDC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC ,Data Length Control"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "2.0,1.3"
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "Field DLC,4 and 5 bits Identifier"
|
|
else
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "Field DLC,5 and 6 bits Identifier"
|
|
endif
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "Enhanced,Classic"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "PUBLISH,SUBSCRIBE,IGNORE,?..."
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
line.long 0x04 "US_LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " IDCHR ,Identifier Character"
|
|
endif
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
if ((d.l(ad:0x40098000+0x58)&0x0A)==0x0A)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "LINIR,LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
else
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "LINIR,LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
endif
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "LINBRR,LIN Baud Rate Register"
|
|
bitfld.long 0x00 16.--18. " LINFP ,LIN Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--15. 1. " LINCD ,LIN Clock Divider after Synchronization"
|
|
endif
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "US_WPMR,USART Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "US_WPSR,USART Write Protect Status Register"
|
|
in
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*")&&!cpuis("AT91SAM3N*")&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
hgroup.long 0xec++0x3
|
|
hide.long 0x00 "US_VERSION,USART Version Register"
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "VERSION,Version Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " VERSION ,Version number"
|
|
endif
|
|
width 0xb
|
|
tree "PDC (Peripheral DMA Controller)"
|
|
base ad:0x40098000
|
|
width 13.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "USART0_RPR,Receive Pointer Register"
|
|
line.long 0x04 "USART0_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "USART0_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "USART0_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "USART0_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "USART0_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "USART0_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "USART0_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "USART0_PTCR,PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enable"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "USART0_PTSR,PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "USART 1"
|
|
base ad:0x4009C000
|
|
width 10.
|
|
if ((d.l((ad:0x4009C000)+0x4)&0xF)==(0xE||0xF))
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
sif (!cpuis("AT91SAM3N*")&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select" "No effect,Slave Select Line NSS = 0"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("AT91SAM3N*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
if ((d.l((ad:0x4009C000+0x04))&0x0f)==(0x0e||0x0f))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*")&&!cpuis("ATSAMA5D36"))
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
hexmask.long.byte 0x00 24.--26. 1. " MAX_ITERATION ,Maximum Number of Iterations"
|
|
bitfld.long 0x00 23. " INVDATA ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 20. " WRDBT ,Wait Read Data Before Transfer" "No,Yes"
|
|
else
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Inactive-Low,Inactive-High"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))||(cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
elif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/Captured,Captured/Changed"
|
|
sif cpuis("ATSAM4E*")||cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" ",,,8 bits"
|
|
else
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "CLK_USART,CLK_USART/8,,CLK"
|
|
else
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK / 8,,SCK"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
elif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" ",,,,,,,,,,,,,,SPI Master,SPI Slave"
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
elif ((d.l((ad:0x4009C000+0x04))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
hexmask.long.byte 0x00 24.--26. 1. " MAX_ITERATION ,Maximum Number of Iterations"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Not inverted,Inverted"
|
|
textline " "
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
textline " "
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "CLK_USART,CLK_USART/8,,CLK"
|
|
else
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK / 8,,SCK"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
hexmask.long.byte 0x00 24.--26. 1. " MAX_ITERATION ,Maximum Number of Iterations"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Not inverted,Inverted"
|
|
textline " "
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,1.5,2,?..."
|
|
textline " "
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "CLK_USART,CLK_USART/8,,CLK"
|
|
else
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK / 8,,SCK"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
endif
|
|
if (((d.l((ad:0x4009C000+0x4))&0x1f)==0xE)||(d.l((ad:0x4009C000+0x4))&0x1f)==0xF)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Enable/Mask Register"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
sif (cpuis("AT91SAM3N*"))
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 31. -0x8 31. -0x4 31. " LINHTE_set/clr ,LIN Header Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x8 30. -0x4 30. " LINSTE_set/clr ,LIN Sync Tolerance Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Sync Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bit Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANEA_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x8 20. -0x4 20. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*"))
|
|
sif !cpuis("ATSAM4N*")
|
|
setclrfld.long 0x00 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("ATSAM4E*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Max number of Repetitions Reached/SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
elif (cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " UNRE_set/clr ,SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*"))
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Enable/Mask Register"
|
|
sif (cpuis("AT91SAM3N*")||cpuis("ATSAM4N*"))
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 31. -0x8 31. -0x4 31. " LINHTE_set/clr ,LIN Header Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x8 30. -0x4 30. " LINSTE_set/clr ,LIN Sync Tolerance Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Sync Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bit Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANEA_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x8 20. -0x4 20. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAMA5D3*"))
|
|
setclrfld.long 0x00 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Max number of Repetitions Reached/SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
elif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITER_set/clr ,Max number of Repetitions Reached Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*")&&!cpuis("ATSAMA5D3*"))
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x0 "US_CSR,Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "US_RHR,Receiver Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US_THR,Transmitter Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20--0x2b
|
|
line.long 0x00 "US_BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1 x 1/8,2 x 1/8,3 x 1/8,4 x 1/8,5 x 1/8,6 x 1/8,7 x 1/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US_RTOR,Receiver Time-out Register"
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " TO ,Time-out Value"
|
|
else
|
|
hexmask.long.tbyte 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
endif
|
|
line.long 0x08 "US_TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US_FIDI,FI DI Ratio Register"
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
else
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("ATSAM4N*"))
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US_NER,Number of Errors Register"
|
|
in
|
|
else
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "US_NER,Number of Errors Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " NB_ERRORS ,Number of Errors"
|
|
endif
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US_IF,USART IrDA FILTER Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
width 10.
|
|
sif (!cpuis("AT91SAM3N*")&&!cpuis("ATSAM4N*"))
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT , Drift Compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ONE ,Must be set to 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RX_MPOL , Receiver Manchester Polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 24.--25. " RX_PP , Receiver Preamble Pattern Detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " RX_PL , Receiver Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
bitfld.long 0x00 12. " TX_MPOL , Transmitter Manchester Polarity" "0-to-1,1-to-0"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TX_PP , Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 0.--3. " TX_PL , Transmitter Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long 0x54++0x7
|
|
line.long 0x00 "US_LINMR,USART LIN Mode Register"
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 17. " SYNCDIS ,Synchronization Disable" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16. " PDCM ,PDC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC ,Data Length Control"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "2.0,1.3"
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "Field DLC,4 and 5 bits Identifier"
|
|
else
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "Field DLC,5 and 6 bits Identifier"
|
|
endif
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "Enhanced,Classic"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "PUBLISH,SUBSCRIBE,IGNORE,?..."
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
line.long 0x04 "US_LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " IDCHR ,Identifier Character"
|
|
endif
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
if ((d.l(ad:0x4009C000+0x58)&0x0A)==0x0A)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "LINIR,LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
else
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "LINIR,LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
endif
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "LINBRR,LIN Baud Rate Register"
|
|
bitfld.long 0x00 16.--18. " LINFP ,LIN Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--15. 1. " LINCD ,LIN Clock Divider after Synchronization"
|
|
endif
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "US_WPMR,USART Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "US_WPSR,USART Write Protect Status Register"
|
|
in
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*")&&!cpuis("AT91SAM3N*")&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
hgroup.long 0xec++0x3
|
|
hide.long 0x00 "US_VERSION,USART Version Register"
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "VERSION,Version Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " VERSION ,Version number"
|
|
endif
|
|
width 0xb
|
|
tree "PDC (Peripheral DMA Controller)"
|
|
base ad:0x4009C000
|
|
width 13.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "USART1_RPR,Receive Pointer Register"
|
|
line.long 0x04 "USART1_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "USART1_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "USART1_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "USART1_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "USART1_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "USART1_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "USART1_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "USART1_PTCR,PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enable"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "USART1_PTSR,PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "USART 2"
|
|
base ad:0x400A0000
|
|
width 10.
|
|
if ((d.l((ad:0x400A0000)+0x4)&0xF)==(0xE||0xF))
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
sif (!cpuis("AT91SAM3N*")&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select" "No effect,Slave Select Line NSS = 0"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("AT91SAM3N*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
if ((d.l((ad:0x400A0000+0x04))&0x0f)==(0x0e||0x0f))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*")&&!cpuis("ATSAMA5D36"))
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
hexmask.long.byte 0x00 24.--26. 1. " MAX_ITERATION ,Maximum Number of Iterations"
|
|
bitfld.long 0x00 23. " INVDATA ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 20. " WRDBT ,Wait Read Data Before Transfer" "No,Yes"
|
|
else
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Inactive-Low,Inactive-High"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))||(cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
elif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/Captured,Captured/Changed"
|
|
sif cpuis("ATSAM4E*")||cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" ",,,8 bits"
|
|
else
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "CLK_USART,CLK_USART/8,,CLK"
|
|
else
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK / 8,,SCK"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
elif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" ",,,,,,,,,,,,,,SPI Master,SPI Slave"
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
elif ((d.l((ad:0x400A0000+0x04))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
hexmask.long.byte 0x00 24.--26. 1. " MAX_ITERATION ,Maximum Number of Iterations"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Not inverted,Inverted"
|
|
textline " "
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
textline " "
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "CLK_USART,CLK_USART/8,,CLK"
|
|
else
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK / 8,,SCK"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
hexmask.long.byte 0x00 24.--26. 1. " MAX_ITERATION ,Maximum Number of Iterations"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Not inverted,Inverted"
|
|
textline " "
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,1.5,2,?..."
|
|
textline " "
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "CLK_USART,CLK_USART/8,,CLK"
|
|
else
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK / 8,,SCK"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
endif
|
|
if (((d.l((ad:0x400A0000+0x4))&0x1f)==0xE)||(d.l((ad:0x400A0000+0x4))&0x1f)==0xF)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Enable/Mask Register"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
sif (cpuis("AT91SAM3N*"))
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 31. -0x8 31. -0x4 31. " LINHTE_set/clr ,LIN Header Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x8 30. -0x4 30. " LINSTE_set/clr ,LIN Sync Tolerance Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Sync Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bit Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANEA_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x8 20. -0x4 20. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*"))
|
|
sif !cpuis("ATSAM4N*")
|
|
setclrfld.long 0x00 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("ATSAM4E*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Max number of Repetitions Reached/SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
elif (cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " UNRE_set/clr ,SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*"))
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Enable/Mask Register"
|
|
sif (cpuis("AT91SAM3N*")||cpuis("ATSAM4N*"))
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 31. -0x8 31. -0x4 31. " LINHTE_set/clr ,LIN Header Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x8 30. -0x4 30. " LINSTE_set/clr ,LIN Sync Tolerance Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Sync Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bit Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANEA_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x8 20. -0x4 20. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAMA5D3*"))
|
|
setclrfld.long 0x00 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Max number of Repetitions Reached/SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
elif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITER_set/clr ,Max number of Repetitions Reached Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*")&&!cpuis("ATSAMA5D3*"))
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x0 "US_CSR,Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "US_RHR,Receiver Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US_THR,Transmitter Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20--0x2b
|
|
line.long 0x00 "US_BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1 x 1/8,2 x 1/8,3 x 1/8,4 x 1/8,5 x 1/8,6 x 1/8,7 x 1/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US_RTOR,Receiver Time-out Register"
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " TO ,Time-out Value"
|
|
else
|
|
hexmask.long.tbyte 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
endif
|
|
line.long 0x08 "US_TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US_FIDI,FI DI Ratio Register"
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
else
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("ATSAM4N*"))
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US_NER,Number of Errors Register"
|
|
in
|
|
else
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "US_NER,Number of Errors Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " NB_ERRORS ,Number of Errors"
|
|
endif
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US_IF,USART IrDA FILTER Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
width 10.
|
|
sif (!cpuis("AT91SAM3N*")&&!cpuis("ATSAM4N*"))
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT , Drift Compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ONE ,Must be set to 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RX_MPOL , Receiver Manchester Polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 24.--25. " RX_PP , Receiver Preamble Pattern Detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " RX_PL , Receiver Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
bitfld.long 0x00 12. " TX_MPOL , Transmitter Manchester Polarity" "0-to-1,1-to-0"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TX_PP , Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 0.--3. " TX_PL , Transmitter Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long 0x54++0x7
|
|
line.long 0x00 "US_LINMR,USART LIN Mode Register"
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 17. " SYNCDIS ,Synchronization Disable" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16. " PDCM ,PDC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC ,Data Length Control"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "2.0,1.3"
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "Field DLC,4 and 5 bits Identifier"
|
|
else
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "Field DLC,5 and 6 bits Identifier"
|
|
endif
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "Enhanced,Classic"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "PUBLISH,SUBSCRIBE,IGNORE,?..."
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
line.long 0x04 "US_LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " IDCHR ,Identifier Character"
|
|
endif
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
if ((d.l(ad:0x400A0000+0x58)&0x0A)==0x0A)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "LINIR,LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
else
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "LINIR,LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
endif
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "LINBRR,LIN Baud Rate Register"
|
|
bitfld.long 0x00 16.--18. " LINFP ,LIN Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--15. 1. " LINCD ,LIN Clock Divider after Synchronization"
|
|
endif
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "US_WPMR,USART Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "US_WPSR,USART Write Protect Status Register"
|
|
in
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*")&&!cpuis("AT91SAM3N*")&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
hgroup.long 0xec++0x3
|
|
hide.long 0x00 "US_VERSION,USART Version Register"
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "VERSION,Version Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " VERSION ,Version number"
|
|
endif
|
|
width 0xb
|
|
tree "PDC (Peripheral DMA Controller)"
|
|
base ad:0x400A0000
|
|
width 13.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "USART2_RPR,Receive Pointer Register"
|
|
line.long 0x04 "USART2_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "USART2_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "USART2_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "USART2_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "USART2_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "USART2_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "USART2_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "USART2_PTCR,PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enable"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "USART2_PTSR,PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
sif (cpuis("AT91SAM3X8E")||cpuis("AT91SAM3X4E"))
|
|
tree "USART 3"
|
|
base ad:0x400A4000
|
|
width 10.
|
|
if ((d.l((ad:0x400A4000)+0x4)&0xF)==(0xE||0xF))
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
sif (!cpuis("AT91SAM3N*")&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " RCS ,Release SPI Chip Select" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI Chip Select" "No effect,Slave Select Line NSS = 0"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "US_CR,Control Register"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("AT91SAM3N*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN Wakeup Signal" "No effect,Sent"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN Transmission" "No effect,Abort"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,RTS=1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,RTS=0"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " RETTO ,Rearm Time-out" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset Non Acknowledge" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIT ,Reset Iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send Address" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STTTO ,Start Time-out" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop Break" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STTBRK ,Start Break" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset Status Bits" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Yes"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Yes"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset"
|
|
endif
|
|
if ((d.l((ad:0x400A4000+0x04))&0x0f)==(0x0e||0x0f))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*")&&!cpuis("ATSAMA5D36"))
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
hexmask.long.byte 0x00 24.--26. 1. " MAX_ITERATION ,Maximum Number of Iterations"
|
|
bitfld.long 0x00 23. " INVDATA ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 20. " WRDBT ,Wait Read Data Before Transfer" "No,Yes"
|
|
else
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16. " CPOL ,SPI Clock Polarity" "Inactive-Low,Inactive-High"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))||(cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
elif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPHA ,SPI Clock Phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/Captured,Captured/Changed"
|
|
sif cpuis("ATSAM4E*")||cpuis("ATSAM4N*")
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" ",,,8 bits"
|
|
else
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "CLK_USART,CLK_USART/8,,CLK"
|
|
else
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK / 8,,SCK"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
elif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" ",,,,,,,,,,,,,,SPI Master,SPI Slave"
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
elif ((d.l((ad:0x400A4000+0x04))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
hexmask.long.byte 0x00 24.--26. 1. " MAX_ITERATION ,Maximum Number of Iterations"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Not inverted,Inverted"
|
|
textline " "
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,,2,?..."
|
|
textline " "
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "CLK_USART,CLK_USART/8,,CLK"
|
|
else
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK / 8,,SCK"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "US_MR,Mode Register"
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 31. " ONEBIT , Start Frame Delimiter Selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "0 to 1,1 to 0"
|
|
textline " "
|
|
endif
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered"
|
|
textline " "
|
|
hexmask.long.byte 0x00 24.--26. 1. " MAX_ITERATION ,Maximum Number of Iterations"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted Data" "Not inverted,Inverted"
|
|
textline " "
|
|
sif (!(cpuis("AT91SAM3N*"))&&!cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync" "User defined,US_THR register"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSNACK ,Disable Successive NACK" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "NACK,No NACK"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CKLO ,Clock Output Select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit Character Length" "Def by CHRL,9-bit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic Echo,Local Loopback,Remote Loopback"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of Stop Bits" "1,1.5,2,?..."
|
|
textline " "
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
else
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Forced to 0,Forced to 1,No parity,No parity,Multidrop,Multidrop"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous Mode Select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5 bits,6 bits,7 bits,8 bits"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "CLK_USART,CLK_USART/8,,CLK"
|
|
else
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK / 8,,SCK"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN Master,LIN Slave,,,SPI Master,SPI Slave"
|
|
else
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware Handshaking,,IS07816 T = 0,,IS07816 T = 1,,IrDA,,,,,,SPI Master,SPI Slave"
|
|
endif
|
|
endif
|
|
if (((d.l((ad:0x400A4000+0x4))&0x1f)==0xE)||(d.l((ad:0x400A4000+0x4))&0x1f)==0xF)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Enable/Mask Register"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
sif (cpuis("AT91SAM3N*"))
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 31. -0x8 31. -0x4 31. " LINHTE_set/clr ,LIN Header Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x8 30. -0x4 30. " LINSTE_set/clr ,LIN Sync Tolerance Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Sync Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bit Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANEA_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x8 20. -0x4 20. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*"))
|
|
sif !cpuis("ATSAM4N*")
|
|
setclrfld.long 0x00 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("ATSAM4E*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Max number of Repetitions Reached/SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
elif (cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " UNRE_set/clr ,SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
textline " "
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*"))
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "US_IMR,Interrupt Enable/Mask Register"
|
|
sif (cpuis("AT91SAM3N*")||cpuis("ATSAM4N*"))
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C"))
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Synch Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bus Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("AT91SAM3S16C")||cpuis("AT91SAM3S8B")||cpuis("AT91SAM3S8C")||cpuis("AT91SAM3SD8B")||cpuis("AT91SAM3SD8C")||cpuis("ATSAM4E*"))
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 31. -0x8 31. -0x4 31. " LINHTE_set/clr ,LIN Header Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x8 30. -0x4 30. " LINSTE_set/clr ,LIN Sync Tolerance Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 29. -0x8 29. -0x4 29. " LINSNRE_set/clr ,LIN Slave Not Responding Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x8 28. -0x4 28. " LINCE_set/clr ,LIN Checksum Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. -0x8 27. -0x4 27. " LINIPE_set/clr ,LIN Identifier Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x8 26. -0x4 26. " LINISFE_set/clr ,LIN Inconsistent Sync Field Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x8 25. -0x4 25. " LINBE_set/clr ,LIN Bit Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANEA_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 20. -0x8 20. -0x4 20. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " DSRIC_set/clr ,Data Set Ready Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " RIIC_set/clr ,Ring Indicator Input Change Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " LINTC_set/clr ,LIN Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " LINID_set/clr ,LIN Identifier Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x00 24. -0x8 24. -0x4 24. " MANE_set/clr , Manchester Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 13. -0x8 13. -0x4 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAMA5D3*"))
|
|
setclrfld.long 0x00 12. -0x8 12. -0x4 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 11. -0x8 11. -0x4 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITER/UNRE_set/clr ,Max number of Repetitions Reached/SPI Underrun Error Interrupt Mask" "Disabled,Enabled"
|
|
elif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4E*")||cpuis("ATSAM4N*"))
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITER_set/clr ,Max number of Repetitions Reached Interrupt Mask" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " TIMEOUT_set/clr ,Time-out Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*")&&!cpuis("ATSAMA5D3*"))
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x0 "US_CSR,Channel Status Register"
|
|
in
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "US_RHR,Receiver Holding Register"
|
|
in
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "US_THR,Transmitter Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync Field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be Transmitted"
|
|
group.long 0x20--0x2b
|
|
line.long 0x00 "US_BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1 x 1/8,2 x 1/8,3 x 1/8,4 x 1/8,5 x 1/8,6 x 1/8,7 x 1/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider"
|
|
line.long 0x04 "US_RTOR,Receiver Time-out Register"
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " TO ,Time-out Value"
|
|
else
|
|
hexmask.long.tbyte 0x04 0.--15. 1. " TO ,Time-out Value"
|
|
endif
|
|
line.long 0x08 "US_TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "US_FIDI,FI DI Ratio Register"
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("ATSAM4N*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
else
|
|
hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value"
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("ATSAM4N*"))
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "US_NER,Number of Errors Register"
|
|
in
|
|
else
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "US_NER,Number of Errors Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " NB_ERRORS ,Number of Errors"
|
|
endif
|
|
group.long 0x4c++0x03
|
|
line.long 0x00 "US_IF,USART IrDA FILTER Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA Filter"
|
|
width 10.
|
|
sif (!cpuis("AT91SAM3N*")&&!cpuis("ATSAM4N*"))
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 30. " DRIFT , Drift Compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ONE ,Must be set to 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RX_MPOL , Receiver Manchester Polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 24.--25. " RX_PP , Receiver Preamble Pattern Detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " RX_PL , Receiver Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
bitfld.long 0x00 12. " TX_MPOL , Transmitter Manchester Polarity" "0-to-1,1-to-0"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TX_PP , Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 0.--3. " TX_PL , Transmitter Preamble Length" "Disabled,1 Bit,2 Bit,3 Bit,4 Bit,5 Bit,6 Bit,7 Bit,8 Bit,9 Bit,10 Bit,11 Bit,12 Bit,13 Bit,14 Bit,15 Bit"
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*")||cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long 0x54++0x7
|
|
line.long 0x00 "US_LINMR,USART LIN Mode Register"
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 17. " SYNCDIS ,Synchronization Disable" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16. " PDCM ,PDC Mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC ,Data Length Control"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup Signal Type" "2.0,1.3"
|
|
bitfld.long 0x00 6. " FSDIS ,Frame Slot Mode Disable" "No,Yes"
|
|
textline " "
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "Field DLC,4 and 5 bits Identifier"
|
|
else
|
|
bitfld.long 0x00 5. " DLM ,Data Length Mode" "Field DLC,5 and 6 bits Identifier"
|
|
endif
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum Type" "Enhanced,Classic"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum Disable" "No,Yes"
|
|
bitfld.long 0x00 2. " PARDIS ,Parity Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN Node Action" "PUBLISH,SUBSCRIBE,IGNORE,?..."
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*"))
|
|
line.long 0x04 "US_LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " IDCHR ,Identifier Character"
|
|
endif
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
if ((d.l(ad:0x400A4000+0x58)&0x0A)==0x0A)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "LINIR,LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
else
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "LINIR,LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier Character"
|
|
endif
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "LINBRR,LIN Baud Rate Register"
|
|
bitfld.long 0x00 16.--18. " LINFP ,LIN Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--15. 1. " LINCD ,LIN Clock Divider after Synchronization"
|
|
endif
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "US_WPMR,USART Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "US_WPSR,USART Write Protect Status Register"
|
|
in
|
|
sif (!cpuis("ATSAM4LC*")&&!cpuis("ATSAM4LS*")&&!cpuis("AT91SAM3N*")&&!cpuis("ATSAMA5D3*")&&!cpuis("ATSAM4E*")&&!cpuis("ATSAM4N*"))
|
|
hgroup.long 0xec++0x3
|
|
hide.long 0x00 "US_VERSION,USART Version Register"
|
|
endif
|
|
sif (cpuis("ATSAM4LC*")||cpuis("ATSAM4LS*"))
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "VERSION,Version Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " VERSION ,Version number"
|
|
endif
|
|
width 0xb
|
|
tree "PDC (Peripheral DMA Controller)"
|
|
base ad:0x400A4000
|
|
width 13.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "USART3_RPR,Receive Pointer Register"
|
|
line.long 0x04 "USART3_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "USART3_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "USART3_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "USART3_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "USART3_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "USART3_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "USART3_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "USART3_PTCR,PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enable"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "USART3_PTSR,PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree.open "TC (Timer Counter)"
|
|
tree "TC0"
|
|
base ad:0x40080000
|
|
width 8.
|
|
tree "Block Registers"
|
|
wgroup.long 0xc0++0x03
|
|
line.long 0x00 "TC_BCR,TC Block Control Register"
|
|
bitfld.long 0x00 4.--5. " TC_BCR ,TC Block Control Register" "TIOA0->TIOA1,TIOA1->TIOA2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " SYNC , Synchro Command" "No effect,Asserted"
|
|
group.long 0xc4++0x03
|
|
line.long 0x00 "TC_BMR,TC Block Mode Register"
|
|
bitfld.long 0x00 20.--25. " MAXFILT ,Maximum Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 19. " FILTER ,IDX,PHA ,IDX,PHA, PHB input pins filter" "Disable,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " IDXPHB ,Index pin is PHB pin" "TIOA1,TIOB0"
|
|
bitfld.long 0x00 16. " SWAP ,SWAP PHA and PHB" "No swap,Swap"
|
|
textline " "
|
|
bitfld.long 0x00 15. " INVIDX ,Inverted Index" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " INVB ,Inverted PHB" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INVA ,Inverted PHA" "Not inverted,Inverted"
|
|
bitfld.long 0x00 12. " EDGPHA ,Edge on PHA count mode" "PHA and PHB,PHA only"
|
|
textline " "
|
|
bitfld.long 0x00 11. " QDTRANS ,Quadrature Decoding Transparent" "Full,Transparent"
|
|
bitfld.long 0x00 10. " SPEEDEN ,Speed Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " POSEN ,Position Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " QDEN ,Quadrature Decoder Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External Clock Signal 2 Selection" "TCLK2,No signal,TIOA0,TIOA1"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External Clock Signal 1 Selection" "TCLK1,No signal,TIOA0,TIOA2"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External Clock Signal 0 Selection" "TCLK0,No signal,TIOA1,TIOA2"
|
|
group.long 0xd0++0x3
|
|
line.long 0x00 "TC_QIMR,TC QDEC Interrupt Mask Register"
|
|
sif cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " QERR_set/clr ,Quadrature Error" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " DIRCHG_set/clr ,Direction Change" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " IDX_set/clr ,Index" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " IDX_set/clr ,Index" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " DIRCHG_set/clr ,Direction Change" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " QERR_set/clr ,Quadrature Error" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long 0xd4++0x3
|
|
hide.long 0x00 "TC_QISR,TC QDEC Interrupt Status Register"
|
|
in
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long 0xD8++0x3
|
|
line.long 0x00 "TC_FMR,TC Fault Mode Register"
|
|
bitfld.long 0x00 1. " ENCF1 ,ENable Compare Fault Channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENCF0 ,ENable Compare Fault Channel 0" "Disabled,Enabled"
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "TC_WPMR,TC Write Protect Mode Register"
|
|
hexmask.long 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
endif
|
|
tree.end
|
|
width 9.
|
|
sif cpuis("AT91SAMX8C")||cpuis("AT91SAMX4C")
|
|
tree "TC Channel 0"
|
|
wgroup.long (0x0+0x00)++0x03
|
|
line.long 0x00 "TC0_CCR,TC0 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40080000+0x0+0x4)))&0x8000)==0x8000)
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
sif (cpuis("AT01SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x0+0x8)++0xB
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x0+0x10)++0x03
|
|
line.long 0x00 "TC0_CV,TC0 Counter Value Register"
|
|
hexmask.long 0x00 0.--31. 1. " CV ,Counter Value"
|
|
else
|
|
rgroup.long (0x0+0x10)++0x03
|
|
line.long 0x00 "TC0_CV,TC0 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40080000+0x0+0x4)))&0x8000)==0x8000)
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x0+0x14)++0x7
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x0+0x14)++0x07
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
rgroup.long (0x0+0x14)++0x07
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x0+0x1C)++0x3
|
|
line.long 0x00 "TC0_RC,TC0 Register C"
|
|
hexmask.long 0x00 0.--31. 1. " RC ,Register C Value"
|
|
else
|
|
group.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "TC0_RC,TC0 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0x0+0x20)++0x03
|
|
hide.long 0x00 "TC0_SR,TC0 Status Register"
|
|
in
|
|
group.long (0x0+0x2C)++0x03
|
|
line.long 0x00 "TC0_IMR,TC0 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
tree "TC Channel 1"
|
|
wgroup.long (0x40+0x00)++0x03
|
|
line.long 0x00 "TC1_CCR,TC1 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40080000+0x40+0x4)))&0x8000)==0x8000)
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
sif (cpuis("AT01SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x40+0x8)++0xB
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x40+0x10)++0x03
|
|
line.long 0x00 "TC1_CV,TC1 Counter Value Register"
|
|
hexmask.long 0x00 0.--31. 1. " CV ,Counter Value"
|
|
else
|
|
rgroup.long (0x40+0x10)++0x03
|
|
line.long 0x00 "TC1_CV,TC1 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40080000+0x40+0x4)))&0x8000)==0x8000)
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x40+0x14)++0x7
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x40+0x14)++0x07
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
rgroup.long (0x40+0x14)++0x07
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x40+0x1C)++0x3
|
|
line.long 0x00 "TC1_RC,TC1 Register C"
|
|
hexmask.long 0x00 0.--31. 1. " RC ,Register C Value"
|
|
else
|
|
group.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "TC1_RC,TC1 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0x40+0x20)++0x03
|
|
hide.long 0x00 "TC1_SR,TC1 Status Register"
|
|
in
|
|
group.long (0x40+0x2C)++0x03
|
|
line.long 0x00 "TC1_IMR,TC1 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
tree "TC Channel 2"
|
|
wgroup.long (0x80+0x00)++0x03
|
|
line.long 0x00 "TC2_CCR,TC2 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40080000+0x80+0x4)))&0x8000)==0x8000)
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "TC2_CMR,TC2 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "TC2_CMR,TC2 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
sif (cpuis("AT01SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x80+0x8)++0xB
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x80+0x10)++0x03
|
|
line.long 0x00 "TC2_CV,TC2 Counter Value Register"
|
|
hexmask.long 0x00 0.--31. 1. " CV ,Counter Value"
|
|
else
|
|
rgroup.long (0x80+0x10)++0x03
|
|
line.long 0x00 "TC2_CV,TC2 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40080000+0x80+0x4)))&0x8000)==0x8000)
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x80+0x14)++0x7
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x80+0x14)++0x07
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
rgroup.long (0x80+0x14)++0x07
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x80+0x1C)++0x3
|
|
line.long 0x00 "TC2_RC,TC2 Register C"
|
|
hexmask.long 0x00 0.--31. 1. " RC ,Register C Value"
|
|
else
|
|
group.long (0x80+0x1C)++0x03
|
|
line.long 0x00 "TC2_RC,TC2 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0x80+0x20)++0x03
|
|
hide.long 0x00 "TC2_SR,TC2 Status Register"
|
|
in
|
|
group.long (0x80+0x2C)++0x03
|
|
line.long 0x00 "TC2_IMR,TC2 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
tree "TC Channel 3"
|
|
wgroup.long (0xC0+0x00)++0x03
|
|
line.long 0x00 "TC3_CCR,TC3 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40080000+0xC0+0x4)))&0x8000)==0x8000)
|
|
group.long (0xC0+0x04)++0x03
|
|
line.long 0x00 "TC3_CMR,TC3 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0xC0+0x04)++0x03
|
|
line.long 0x00 "TC3_CMR,TC3 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
sif (cpuis("AT01SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0xC0+0x8)++0xB
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0xC0+0x10)++0x03
|
|
line.long 0x00 "TC3_CV,TC3 Counter Value Register"
|
|
hexmask.long 0x00 0.--31. 1. " CV ,Counter Value"
|
|
else
|
|
rgroup.long (0xC0+0x10)++0x03
|
|
line.long 0x00 "TC3_CV,TC3 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40080000+0xC0+0x4)))&0x8000)==0x8000)
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0xC0+0x14)++0x7
|
|
line.long 0x00 "TC3_RA,TC3 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC3_RB,TC3 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
line.long 0x00 "TC3_RA,TC3 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC3_RB,TC3 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0xC0+0x14)++0x07
|
|
line.long 0x00 "TC3_RA,TC3 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC3_RB,TC3 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
rgroup.long (0xC0+0x14)++0x07
|
|
line.long 0x00 "TC3_RA,TC3 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC3_RB,TC3 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0xC0+0x1C)++0x3
|
|
line.long 0x00 "TC3_RC,TC3 Register C"
|
|
hexmask.long 0x00 0.--31. 1. " RC ,Register C Value"
|
|
else
|
|
group.long (0xC0+0x1C)++0x03
|
|
line.long 0x00 "TC3_RC,TC3 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0xC0+0x20)++0x03
|
|
hide.long 0x00 "TC3_SR,TC3 Status Register"
|
|
in
|
|
group.long (0xC0+0x2C)++0x03
|
|
line.long 0x00 "TC3_IMR,TC3 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
tree "TC Channel 4"
|
|
wgroup.long (0x100+0x00)++0x03
|
|
line.long 0x00 "TC4_CCR,TC4 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40080000+0x100+0x4)))&0x8000)==0x8000)
|
|
group.long (0x100+0x04)++0x03
|
|
line.long 0x00 "TC4_CMR,TC4 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x100+0x04)++0x03
|
|
line.long 0x00 "TC4_CMR,TC4 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
sif (cpuis("AT01SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x100+0x8)++0xB
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x100+0x10)++0x03
|
|
line.long 0x00 "TC4_CV,TC4 Counter Value Register"
|
|
hexmask.long 0x00 0.--31. 1. " CV ,Counter Value"
|
|
else
|
|
rgroup.long (0x100+0x10)++0x03
|
|
line.long 0x00 "TC4_CV,TC4 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40080000+0x100+0x4)))&0x8000)==0x8000)
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x100+0x14)++0x7
|
|
line.long 0x00 "TC4_RA,TC4 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC4_RB,TC4 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
line.long 0x00 "TC4_RA,TC4 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC4_RB,TC4 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x100+0x14)++0x07
|
|
line.long 0x00 "TC4_RA,TC4 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC4_RB,TC4 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
rgroup.long (0x100+0x14)++0x07
|
|
line.long 0x00 "TC4_RA,TC4 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC4_RB,TC4 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x100+0x1C)++0x3
|
|
line.long 0x00 "TC4_RC,TC4 Register C"
|
|
hexmask.long 0x00 0.--31. 1. " RC ,Register C Value"
|
|
else
|
|
group.long (0x100+0x1C)++0x03
|
|
line.long 0x00 "TC4_RC,TC4 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0x100+0x20)++0x03
|
|
hide.long 0x00 "TC4_SR,TC4 Status Register"
|
|
in
|
|
group.long (0x100+0x2C)++0x03
|
|
line.long 0x00 "TC4_IMR,TC4 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
tree "TC Channel 5"
|
|
wgroup.long (0x140+0x00)++0x03
|
|
line.long 0x00 "TC5_CCR,TC5 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40080000+0x140+0x4)))&0x8000)==0x8000)
|
|
group.long (0x140+0x04)++0x03
|
|
line.long 0x00 "TC5_CMR,TC5 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x140+0x04)++0x03
|
|
line.long 0x00 "TC5_CMR,TC5 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
sif (cpuis("AT01SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x140+0x8)++0xB
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x140+0x10)++0x03
|
|
line.long 0x00 "TC5_CV,TC5 Counter Value Register"
|
|
hexmask.long 0x00 0.--31. 1. " CV ,Counter Value"
|
|
else
|
|
rgroup.long (0x140+0x10)++0x03
|
|
line.long 0x00 "TC5_CV,TC5 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40080000+0x140+0x4)))&0x8000)==0x8000)
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x140+0x14)++0x7
|
|
line.long 0x00 "TC5_RA,TC5 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC5_RB,TC5 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
line.long 0x00 "TC5_RA,TC5 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC5_RB,TC5 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x140+0x14)++0x07
|
|
line.long 0x00 "TC5_RA,TC5 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC5_RB,TC5 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
rgroup.long (0x140+0x14)++0x07
|
|
line.long 0x00 "TC5_RA,TC5 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC5_RB,TC5 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x140+0x1C)++0x3
|
|
line.long 0x00 "TC5_RC,TC5 Register C"
|
|
hexmask.long 0x00 0.--31. 1. " RC ,Register C Value"
|
|
else
|
|
group.long (0x140+0x1C)++0x03
|
|
line.long 0x00 "TC5_RC,TC5 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0x140+0x20)++0x03
|
|
hide.long 0x00 "TC5_SR,TC5 Status Register"
|
|
in
|
|
group.long (0x140+0x2C)++0x03
|
|
line.long 0x00 "TC5_IMR,TC5 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
else
|
|
tree "TC Channel 0"
|
|
wgroup.long (0x0+0x00)++0x03
|
|
line.long 0x00 "TC0_CCR,TC0 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40080000+0x0+0x4)))&0x8000)==0x8000)
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
sif (cpuis("AT01SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x0+0x8)++0xB
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x0+0x10)++0x03
|
|
line.long 0x00 "TC0_CV,TC0 Counter Value Register"
|
|
hexmask.long 0x00 0.--31. 1. " CV ,Counter Value"
|
|
else
|
|
rgroup.long (0x0+0x10)++0x03
|
|
line.long 0x00 "TC0_CV,TC0 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40080000+0x0+0x4)))&0x8000)==0x8000)
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x0+0x14)++0x7
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
group.long (0x0+0x14)++0x7
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x0+0x14)++0x07
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
rgroup.long (0x0+0x14)++0x07
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x0+0x1C)++0x3
|
|
line.long 0x00 "TC0_RC,TC0 Register C"
|
|
hexmask.long 0x00 0.--31. 1. " RC ,Register C Value"
|
|
else
|
|
group.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "TC0_RC,TC0 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0x0+0x20)++0x03
|
|
hide.long 0x00 "TC0_SR,TC0 Status Register"
|
|
in
|
|
group.long (0x0+0x2C)++0x03
|
|
line.long 0x00 "TC0_IMR,TC0 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
tree "TC Channel 1"
|
|
wgroup.long (0x40+0x00)++0x03
|
|
line.long 0x00 "TC1_CCR,TC1 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40080000+0x40+0x4)))&0x8000)==0x8000)
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
sif (cpuis("AT01SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x40+0x8)++0xB
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x40+0x10)++0x03
|
|
line.long 0x00 "TC1_CV,TC1 Counter Value Register"
|
|
hexmask.long 0x00 0.--31. 1. " CV ,Counter Value"
|
|
else
|
|
rgroup.long (0x40+0x10)++0x03
|
|
line.long 0x00 "TC1_CV,TC1 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40080000+0x40+0x4)))&0x8000)==0x8000)
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x40+0x14)++0x7
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
group.long (0x40+0x14)++0x7
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x40+0x14)++0x07
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
rgroup.long (0x40+0x14)++0x07
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x40+0x1C)++0x3
|
|
line.long 0x00 "TC1_RC,TC1 Register C"
|
|
hexmask.long 0x00 0.--31. 1. " RC ,Register C Value"
|
|
else
|
|
group.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "TC1_RC,TC1 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0x40+0x20)++0x03
|
|
hide.long 0x00 "TC1_SR,TC1 Status Register"
|
|
in
|
|
group.long (0x40+0x2C)++0x03
|
|
line.long 0x00 "TC1_IMR,TC1 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
tree "TC Channel 2"
|
|
wgroup.long (0x80+0x00)++0x03
|
|
line.long 0x00 "TC2_CCR,TC2 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40080000+0x80+0x4)))&0x8000)==0x8000)
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "TC2_CMR,TC2 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "TC2_CMR,TC2 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
sif (cpuis("AT01SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x80+0x8)++0xB
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x80+0x10)++0x03
|
|
line.long 0x00 "TC2_CV,TC2 Counter Value Register"
|
|
hexmask.long 0x00 0.--31. 1. " CV ,Counter Value"
|
|
else
|
|
rgroup.long (0x80+0x10)++0x03
|
|
line.long 0x00 "TC2_CV,TC2 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40080000+0x80+0x4)))&0x8000)==0x8000)
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x80+0x14)++0x7
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
group.long (0x80+0x14)++0x7
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x80+0x14)++0x07
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
rgroup.long (0x80+0x14)++0x07
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x80+0x1C)++0x3
|
|
line.long 0x00 "TC2_RC,TC2 Register C"
|
|
hexmask.long 0x00 0.--31. 1. " RC ,Register C Value"
|
|
else
|
|
group.long (0x80+0x1C)++0x03
|
|
line.long 0x00 "TC2_RC,TC2 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0x80+0x20)++0x03
|
|
hide.long 0x00 "TC2_SR,TC2 Status Register"
|
|
in
|
|
group.long (0x80+0x2C)++0x03
|
|
line.long 0x00 "TC2_IMR,TC2 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "TC1"
|
|
base ad:0x40084000
|
|
width 8.
|
|
tree "Block Registers"
|
|
wgroup.long 0xc0++0x03
|
|
line.long 0x00 "TC_BCR,TC Block Control Register"
|
|
bitfld.long 0x00 4.--5. " TC_BCR ,TC Block Control Register" "TIOA0->TIOA1,TIOA1->TIOA2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " SYNC , Synchro Command" "No effect,Asserted"
|
|
group.long 0xc4++0x03
|
|
line.long 0x00 "TC_BMR,TC Block Mode Register"
|
|
bitfld.long 0x00 20.--25. " MAXFILT ,Maximum Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 19. " FILTER ,IDX,PHA ,IDX,PHA, PHB input pins filter" "Disable,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " IDXPHB ,Index pin is PHB pin" "TIOA1,TIOB0"
|
|
bitfld.long 0x00 16. " SWAP ,SWAP PHA and PHB" "No swap,Swap"
|
|
textline " "
|
|
bitfld.long 0x00 15. " INVIDX ,Inverted Index" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " INVB ,Inverted PHB" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INVA ,Inverted PHA" "Not inverted,Inverted"
|
|
bitfld.long 0x00 12. " EDGPHA ,Edge on PHA count mode" "PHA and PHB,PHA only"
|
|
textline " "
|
|
bitfld.long 0x00 11. " QDTRANS ,Quadrature Decoding Transparent" "Full,Transparent"
|
|
bitfld.long 0x00 10. " SPEEDEN ,Speed Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " POSEN ,Position Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " QDEN ,Quadrature Decoder Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External Clock Signal 2 Selection" "TCLK2,No signal,TIOA0,TIOA1"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External Clock Signal 1 Selection" "TCLK1,No signal,TIOA0,TIOA2"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External Clock Signal 0 Selection" "TCLK0,No signal,TIOA1,TIOA2"
|
|
group.long 0xd0++0x3
|
|
line.long 0x00 "TC_QIMR,TC QDEC Interrupt Mask Register"
|
|
sif cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " QERR_set/clr ,Quadrature Error" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " DIRCHG_set/clr ,Direction Change" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " IDX_set/clr ,Index" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " IDX_set/clr ,Index" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " DIRCHG_set/clr ,Direction Change" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " QERR_set/clr ,Quadrature Error" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long 0xd4++0x3
|
|
hide.long 0x00 "TC_QISR,TC QDEC Interrupt Status Register"
|
|
in
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long 0xD8++0x3
|
|
line.long 0x00 "TC_FMR,TC Fault Mode Register"
|
|
bitfld.long 0x00 1. " ENCF1 ,ENable Compare Fault Channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENCF0 ,ENable Compare Fault Channel 0" "Disabled,Enabled"
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "TC_WPMR,TC Write Protect Mode Register"
|
|
hexmask.long 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
endif
|
|
tree.end
|
|
width 9.
|
|
sif cpuis("AT91SAMX8C")||cpuis("AT91SAMX4C")
|
|
tree "TC Channel 0"
|
|
wgroup.long (0x0+0x00)++0x03
|
|
line.long 0x00 "TC0_CCR,TC0 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40080000+0x0+0x4)))&0x8000)==0x8000)
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
sif (cpuis("AT01SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x0+0x8)++0xB
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x0+0x10)++0x03
|
|
line.long 0x00 "TC0_CV,TC0 Counter Value Register"
|
|
hexmask.long 0x00 0.--31. 1. " CV ,Counter Value"
|
|
else
|
|
rgroup.long (0x0+0x10)++0x03
|
|
line.long 0x00 "TC0_CV,TC0 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40080000+0x0+0x4)))&0x8000)==0x8000)
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x0+0x14)++0x7
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x0+0x14)++0x07
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
rgroup.long (0x0+0x14)++0x07
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x0+0x1C)++0x3
|
|
line.long 0x00 "TC0_RC,TC0 Register C"
|
|
hexmask.long 0x00 0.--31. 1. " RC ,Register C Value"
|
|
else
|
|
group.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "TC0_RC,TC0 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0x0+0x20)++0x03
|
|
hide.long 0x00 "TC0_SR,TC0 Status Register"
|
|
in
|
|
group.long (0x0+0x2C)++0x03
|
|
line.long 0x00 "TC0_IMR,TC0 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
tree "TC Channel 1"
|
|
wgroup.long (0x40+0x00)++0x03
|
|
line.long 0x00 "TC1_CCR,TC1 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40080000+0x40+0x4)))&0x8000)==0x8000)
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
sif (cpuis("AT01SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x40+0x8)++0xB
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x40+0x10)++0x03
|
|
line.long 0x00 "TC1_CV,TC1 Counter Value Register"
|
|
hexmask.long 0x00 0.--31. 1. " CV ,Counter Value"
|
|
else
|
|
rgroup.long (0x40+0x10)++0x03
|
|
line.long 0x00 "TC1_CV,TC1 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40080000+0x40+0x4)))&0x8000)==0x8000)
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x40+0x14)++0x7
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x40+0x14)++0x07
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
rgroup.long (0x40+0x14)++0x07
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x40+0x1C)++0x3
|
|
line.long 0x00 "TC1_RC,TC1 Register C"
|
|
hexmask.long 0x00 0.--31. 1. " RC ,Register C Value"
|
|
else
|
|
group.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "TC1_RC,TC1 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0x40+0x20)++0x03
|
|
hide.long 0x00 "TC1_SR,TC1 Status Register"
|
|
in
|
|
group.long (0x40+0x2C)++0x03
|
|
line.long 0x00 "TC1_IMR,TC1 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
tree "TC Channel 2"
|
|
wgroup.long (0x80+0x00)++0x03
|
|
line.long 0x00 "TC2_CCR,TC2 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40080000+0x80+0x4)))&0x8000)==0x8000)
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "TC2_CMR,TC2 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "TC2_CMR,TC2 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
sif (cpuis("AT01SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x80+0x8)++0xB
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x80+0x10)++0x03
|
|
line.long 0x00 "TC2_CV,TC2 Counter Value Register"
|
|
hexmask.long 0x00 0.--31. 1. " CV ,Counter Value"
|
|
else
|
|
rgroup.long (0x80+0x10)++0x03
|
|
line.long 0x00 "TC2_CV,TC2 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40080000+0x80+0x4)))&0x8000)==0x8000)
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x80+0x14)++0x7
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x80+0x14)++0x07
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
rgroup.long (0x80+0x14)++0x07
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x80+0x1C)++0x3
|
|
line.long 0x00 "TC2_RC,TC2 Register C"
|
|
hexmask.long 0x00 0.--31. 1. " RC ,Register C Value"
|
|
else
|
|
group.long (0x80+0x1C)++0x03
|
|
line.long 0x00 "TC2_RC,TC2 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0x80+0x20)++0x03
|
|
hide.long 0x00 "TC2_SR,TC2 Status Register"
|
|
in
|
|
group.long (0x80+0x2C)++0x03
|
|
line.long 0x00 "TC2_IMR,TC2 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
tree "TC Channel 3"
|
|
wgroup.long (0xC0+0x00)++0x03
|
|
line.long 0x00 "TC3_CCR,TC3 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40080000+0xC0+0x4)))&0x8000)==0x8000)
|
|
group.long (0xC0+0x04)++0x03
|
|
line.long 0x00 "TC3_CMR,TC3 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0xC0+0x04)++0x03
|
|
line.long 0x00 "TC3_CMR,TC3 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
sif (cpuis("AT01SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0xC0+0x8)++0xB
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0xC0+0x10)++0x03
|
|
line.long 0x00 "TC3_CV,TC3 Counter Value Register"
|
|
hexmask.long 0x00 0.--31. 1. " CV ,Counter Value"
|
|
else
|
|
rgroup.long (0xC0+0x10)++0x03
|
|
line.long 0x00 "TC3_CV,TC3 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40080000+0xC0+0x4)))&0x8000)==0x8000)
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0xC0+0x14)++0x7
|
|
line.long 0x00 "TC3_RA,TC3 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC3_RB,TC3 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
line.long 0x00 "TC3_RA,TC3 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC3_RB,TC3 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0xC0+0x14)++0x07
|
|
line.long 0x00 "TC3_RA,TC3 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC3_RB,TC3 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
rgroup.long (0xC0+0x14)++0x07
|
|
line.long 0x00 "TC3_RA,TC3 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC3_RB,TC3 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0xC0+0x1C)++0x3
|
|
line.long 0x00 "TC3_RC,TC3 Register C"
|
|
hexmask.long 0x00 0.--31. 1. " RC ,Register C Value"
|
|
else
|
|
group.long (0xC0+0x1C)++0x03
|
|
line.long 0x00 "TC3_RC,TC3 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0xC0+0x20)++0x03
|
|
hide.long 0x00 "TC3_SR,TC3 Status Register"
|
|
in
|
|
group.long (0xC0+0x2C)++0x03
|
|
line.long 0x00 "TC3_IMR,TC3 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
tree "TC Channel 4"
|
|
wgroup.long (0x100+0x00)++0x03
|
|
line.long 0x00 "TC4_CCR,TC4 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40080000+0x100+0x4)))&0x8000)==0x8000)
|
|
group.long (0x100+0x04)++0x03
|
|
line.long 0x00 "TC4_CMR,TC4 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x100+0x04)++0x03
|
|
line.long 0x00 "TC4_CMR,TC4 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
sif (cpuis("AT01SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x100+0x8)++0xB
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x100+0x10)++0x03
|
|
line.long 0x00 "TC4_CV,TC4 Counter Value Register"
|
|
hexmask.long 0x00 0.--31. 1. " CV ,Counter Value"
|
|
else
|
|
rgroup.long (0x100+0x10)++0x03
|
|
line.long 0x00 "TC4_CV,TC4 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40080000+0x100+0x4)))&0x8000)==0x8000)
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x100+0x14)++0x7
|
|
line.long 0x00 "TC4_RA,TC4 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC4_RB,TC4 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
line.long 0x00 "TC4_RA,TC4 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC4_RB,TC4 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x100+0x14)++0x07
|
|
line.long 0x00 "TC4_RA,TC4 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC4_RB,TC4 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
rgroup.long (0x100+0x14)++0x07
|
|
line.long 0x00 "TC4_RA,TC4 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC4_RB,TC4 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x100+0x1C)++0x3
|
|
line.long 0x00 "TC4_RC,TC4 Register C"
|
|
hexmask.long 0x00 0.--31. 1. " RC ,Register C Value"
|
|
else
|
|
group.long (0x100+0x1C)++0x03
|
|
line.long 0x00 "TC4_RC,TC4 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0x100+0x20)++0x03
|
|
hide.long 0x00 "TC4_SR,TC4 Status Register"
|
|
in
|
|
group.long (0x100+0x2C)++0x03
|
|
line.long 0x00 "TC4_IMR,TC4 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
tree "TC Channel 5"
|
|
wgroup.long (0x140+0x00)++0x03
|
|
line.long 0x00 "TC5_CCR,TC5 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40080000+0x140+0x4)))&0x8000)==0x8000)
|
|
group.long (0x140+0x04)++0x03
|
|
line.long 0x00 "TC5_CMR,TC5 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x140+0x04)++0x03
|
|
line.long 0x00 "TC5_CMR,TC5 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
sif (cpuis("AT01SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x140+0x8)++0xB
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x140+0x10)++0x03
|
|
line.long 0x00 "TC5_CV,TC5 Counter Value Register"
|
|
hexmask.long 0x00 0.--31. 1. " CV ,Counter Value"
|
|
else
|
|
rgroup.long (0x140+0x10)++0x03
|
|
line.long 0x00 "TC5_CV,TC5 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40080000+0x140+0x4)))&0x8000)==0x8000)
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x140+0x14)++0x7
|
|
line.long 0x00 "TC5_RA,TC5 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC5_RB,TC5 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
line.long 0x00 "TC5_RA,TC5 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC5_RB,TC5 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x140+0x14)++0x07
|
|
line.long 0x00 "TC5_RA,TC5 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC5_RB,TC5 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
rgroup.long (0x140+0x14)++0x07
|
|
line.long 0x00 "TC5_RA,TC5 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC5_RB,TC5 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x140+0x1C)++0x3
|
|
line.long 0x00 "TC5_RC,TC5 Register C"
|
|
hexmask.long 0x00 0.--31. 1. " RC ,Register C Value"
|
|
else
|
|
group.long (0x140+0x1C)++0x03
|
|
line.long 0x00 "TC5_RC,TC5 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0x140+0x20)++0x03
|
|
hide.long 0x00 "TC5_SR,TC5 Status Register"
|
|
in
|
|
group.long (0x140+0x2C)++0x03
|
|
line.long 0x00 "TC5_IMR,TC5 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
else
|
|
tree "TC Channel 0"
|
|
wgroup.long (0x0+0x00)++0x03
|
|
line.long 0x00 "TC0_CCR,TC0 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40080000+0x0+0x4)))&0x8000)==0x8000)
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
sif (cpuis("AT01SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x0+0x8)++0xB
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x0+0x10)++0x03
|
|
line.long 0x00 "TC0_CV,TC0 Counter Value Register"
|
|
hexmask.long 0x00 0.--31. 1. " CV ,Counter Value"
|
|
else
|
|
rgroup.long (0x0+0x10)++0x03
|
|
line.long 0x00 "TC0_CV,TC0 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40080000+0x0+0x4)))&0x8000)==0x8000)
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x0+0x14)++0x7
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
group.long (0x0+0x14)++0x7
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x0+0x14)++0x07
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
rgroup.long (0x0+0x14)++0x07
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x0+0x1C)++0x3
|
|
line.long 0x00 "TC0_RC,TC0 Register C"
|
|
hexmask.long 0x00 0.--31. 1. " RC ,Register C Value"
|
|
else
|
|
group.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "TC0_RC,TC0 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0x0+0x20)++0x03
|
|
hide.long 0x00 "TC0_SR,TC0 Status Register"
|
|
in
|
|
group.long (0x0+0x2C)++0x03
|
|
line.long 0x00 "TC0_IMR,TC0 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
tree "TC Channel 1"
|
|
wgroup.long (0x40+0x00)++0x03
|
|
line.long 0x00 "TC1_CCR,TC1 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40080000+0x40+0x4)))&0x8000)==0x8000)
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
sif (cpuis("AT01SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x40+0x8)++0xB
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x40+0x10)++0x03
|
|
line.long 0x00 "TC1_CV,TC1 Counter Value Register"
|
|
hexmask.long 0x00 0.--31. 1. " CV ,Counter Value"
|
|
else
|
|
rgroup.long (0x40+0x10)++0x03
|
|
line.long 0x00 "TC1_CV,TC1 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40080000+0x40+0x4)))&0x8000)==0x8000)
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x40+0x14)++0x7
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
group.long (0x40+0x14)++0x7
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x40+0x14)++0x07
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
rgroup.long (0x40+0x14)++0x07
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x40+0x1C)++0x3
|
|
line.long 0x00 "TC1_RC,TC1 Register C"
|
|
hexmask.long 0x00 0.--31. 1. " RC ,Register C Value"
|
|
else
|
|
group.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "TC1_RC,TC1 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0x40+0x20)++0x03
|
|
hide.long 0x00 "TC1_SR,TC1 Status Register"
|
|
in
|
|
group.long (0x40+0x2C)++0x03
|
|
line.long 0x00 "TC1_IMR,TC1 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
tree "TC Channel 2"
|
|
wgroup.long (0x80+0x00)++0x03
|
|
line.long 0x00 "TC2_CCR,TC2 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40080000+0x80+0x4)))&0x8000)==0x8000)
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "TC2_CMR,TC2 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "TC2_CMR,TC2 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
sif (cpuis("AT01SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x80+0x8)++0xB
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x80+0x10)++0x03
|
|
line.long 0x00 "TC2_CV,TC2 Counter Value Register"
|
|
hexmask.long 0x00 0.--31. 1. " CV ,Counter Value"
|
|
else
|
|
rgroup.long (0x80+0x10)++0x03
|
|
line.long 0x00 "TC2_CV,TC2 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40080000+0x80+0x4)))&0x8000)==0x8000)
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x80+0x14)++0x7
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
group.long (0x80+0x14)++0x7
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x80+0x14)++0x07
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
rgroup.long (0x80+0x14)++0x07
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x80+0x1C)++0x3
|
|
line.long 0x00 "TC2_RC,TC2 Register C"
|
|
hexmask.long 0x00 0.--31. 1. " RC ,Register C Value"
|
|
else
|
|
group.long (0x80+0x1C)++0x03
|
|
line.long 0x00 "TC2_RC,TC2 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0x80+0x20)++0x03
|
|
hide.long 0x00 "TC2_SR,TC2 Status Register"
|
|
in
|
|
group.long (0x80+0x2C)++0x03
|
|
line.long 0x00 "TC2_IMR,TC2 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "TC2"
|
|
base ad:0x40088000
|
|
width 8.
|
|
tree "Block Registers"
|
|
wgroup.long 0xc0++0x03
|
|
line.long 0x00 "TC_BCR,TC Block Control Register"
|
|
bitfld.long 0x00 4.--5. " TC_BCR ,TC Block Control Register" "TIOA0->TIOA1,TIOA1->TIOA2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " SYNC , Synchro Command" "No effect,Asserted"
|
|
group.long 0xc4++0x03
|
|
line.long 0x00 "TC_BMR,TC Block Mode Register"
|
|
bitfld.long 0x00 20.--25. " MAXFILT ,Maximum Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 19. " FILTER ,IDX,PHA ,IDX,PHA, PHB input pins filter" "Disable,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " IDXPHB ,Index pin is PHB pin" "TIOA1,TIOB0"
|
|
bitfld.long 0x00 16. " SWAP ,SWAP PHA and PHB" "No swap,Swap"
|
|
textline " "
|
|
bitfld.long 0x00 15. " INVIDX ,Inverted Index" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " INVB ,Inverted PHB" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INVA ,Inverted PHA" "Not inverted,Inverted"
|
|
bitfld.long 0x00 12. " EDGPHA ,Edge on PHA count mode" "PHA and PHB,PHA only"
|
|
textline " "
|
|
bitfld.long 0x00 11. " QDTRANS ,Quadrature Decoding Transparent" "Full,Transparent"
|
|
bitfld.long 0x00 10. " SPEEDEN ,Speed Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " POSEN ,Position Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " QDEN ,Quadrature Decoder Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External Clock Signal 2 Selection" "TCLK2,No signal,TIOA0,TIOA1"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External Clock Signal 1 Selection" "TCLK1,No signal,TIOA0,TIOA2"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External Clock Signal 0 Selection" "TCLK0,No signal,TIOA1,TIOA2"
|
|
group.long 0xd0++0x3
|
|
line.long 0x00 "TC_QIMR,TC QDEC Interrupt Mask Register"
|
|
sif cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " QERR_set/clr ,Quadrature Error" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " DIRCHG_set/clr ,Direction Change" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " IDX_set/clr ,Index" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " IDX_set/clr ,Index" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " DIRCHG_set/clr ,Direction Change" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " QERR_set/clr ,Quadrature Error" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long 0xd4++0x3
|
|
hide.long 0x00 "TC_QISR,TC QDEC Interrupt Status Register"
|
|
in
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long 0xD8++0x3
|
|
line.long 0x00 "TC_FMR,TC Fault Mode Register"
|
|
bitfld.long 0x00 1. " ENCF1 ,ENable Compare Fault Channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENCF0 ,ENable Compare Fault Channel 0" "Disabled,Enabled"
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "TC_WPMR,TC Write Protect Mode Register"
|
|
hexmask.long 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
endif
|
|
tree.end
|
|
width 9.
|
|
sif cpuis("AT91SAMX8C")||cpuis("AT91SAMX4C")
|
|
tree "TC Channel 0"
|
|
wgroup.long (0x0+0x00)++0x03
|
|
line.long 0x00 "TC0_CCR,TC0 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40080000+0x0+0x4)))&0x8000)==0x8000)
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
sif (cpuis("AT01SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x0+0x8)++0xB
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x0+0x10)++0x03
|
|
line.long 0x00 "TC0_CV,TC0 Counter Value Register"
|
|
hexmask.long 0x00 0.--31. 1. " CV ,Counter Value"
|
|
else
|
|
rgroup.long (0x0+0x10)++0x03
|
|
line.long 0x00 "TC0_CV,TC0 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40080000+0x0+0x4)))&0x8000)==0x8000)
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x0+0x14)++0x7
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x0+0x14)++0x07
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
rgroup.long (0x0+0x14)++0x07
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x0+0x1C)++0x3
|
|
line.long 0x00 "TC0_RC,TC0 Register C"
|
|
hexmask.long 0x00 0.--31. 1. " RC ,Register C Value"
|
|
else
|
|
group.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "TC0_RC,TC0 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0x0+0x20)++0x03
|
|
hide.long 0x00 "TC0_SR,TC0 Status Register"
|
|
in
|
|
group.long (0x0+0x2C)++0x03
|
|
line.long 0x00 "TC0_IMR,TC0 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
tree "TC Channel 1"
|
|
wgroup.long (0x40+0x00)++0x03
|
|
line.long 0x00 "TC1_CCR,TC1 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40080000+0x40+0x4)))&0x8000)==0x8000)
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
sif (cpuis("AT01SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x40+0x8)++0xB
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x40+0x10)++0x03
|
|
line.long 0x00 "TC1_CV,TC1 Counter Value Register"
|
|
hexmask.long 0x00 0.--31. 1. " CV ,Counter Value"
|
|
else
|
|
rgroup.long (0x40+0x10)++0x03
|
|
line.long 0x00 "TC1_CV,TC1 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40080000+0x40+0x4)))&0x8000)==0x8000)
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x40+0x14)++0x7
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x40+0x14)++0x07
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
rgroup.long (0x40+0x14)++0x07
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x40+0x1C)++0x3
|
|
line.long 0x00 "TC1_RC,TC1 Register C"
|
|
hexmask.long 0x00 0.--31. 1. " RC ,Register C Value"
|
|
else
|
|
group.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "TC1_RC,TC1 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0x40+0x20)++0x03
|
|
hide.long 0x00 "TC1_SR,TC1 Status Register"
|
|
in
|
|
group.long (0x40+0x2C)++0x03
|
|
line.long 0x00 "TC1_IMR,TC1 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
tree "TC Channel 2"
|
|
wgroup.long (0x80+0x00)++0x03
|
|
line.long 0x00 "TC2_CCR,TC2 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40080000+0x80+0x4)))&0x8000)==0x8000)
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "TC2_CMR,TC2 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "TC2_CMR,TC2 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
sif (cpuis("AT01SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x80+0x8)++0xB
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x80+0x10)++0x03
|
|
line.long 0x00 "TC2_CV,TC2 Counter Value Register"
|
|
hexmask.long 0x00 0.--31. 1. " CV ,Counter Value"
|
|
else
|
|
rgroup.long (0x80+0x10)++0x03
|
|
line.long 0x00 "TC2_CV,TC2 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40080000+0x80+0x4)))&0x8000)==0x8000)
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x80+0x14)++0x7
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x80+0x14)++0x07
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
rgroup.long (0x80+0x14)++0x07
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x80+0x1C)++0x3
|
|
line.long 0x00 "TC2_RC,TC2 Register C"
|
|
hexmask.long 0x00 0.--31. 1. " RC ,Register C Value"
|
|
else
|
|
group.long (0x80+0x1C)++0x03
|
|
line.long 0x00 "TC2_RC,TC2 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0x80+0x20)++0x03
|
|
hide.long 0x00 "TC2_SR,TC2 Status Register"
|
|
in
|
|
group.long (0x80+0x2C)++0x03
|
|
line.long 0x00 "TC2_IMR,TC2 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
tree "TC Channel 3"
|
|
wgroup.long (0xC0+0x00)++0x03
|
|
line.long 0x00 "TC3_CCR,TC3 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40080000+0xC0+0x4)))&0x8000)==0x8000)
|
|
group.long (0xC0+0x04)++0x03
|
|
line.long 0x00 "TC3_CMR,TC3 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0xC0+0x04)++0x03
|
|
line.long 0x00 "TC3_CMR,TC3 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
sif (cpuis("AT01SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0xC0+0x8)++0xB
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0xC0+0x10)++0x03
|
|
line.long 0x00 "TC3_CV,TC3 Counter Value Register"
|
|
hexmask.long 0x00 0.--31. 1. " CV ,Counter Value"
|
|
else
|
|
rgroup.long (0xC0+0x10)++0x03
|
|
line.long 0x00 "TC3_CV,TC3 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40080000+0xC0+0x4)))&0x8000)==0x8000)
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0xC0+0x14)++0x7
|
|
line.long 0x00 "TC3_RA,TC3 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC3_RB,TC3 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
line.long 0x00 "TC3_RA,TC3 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC3_RB,TC3 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0xC0+0x14)++0x07
|
|
line.long 0x00 "TC3_RA,TC3 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC3_RB,TC3 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
rgroup.long (0xC0+0x14)++0x07
|
|
line.long 0x00 "TC3_RA,TC3 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC3_RB,TC3 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0xC0+0x1C)++0x3
|
|
line.long 0x00 "TC3_RC,TC3 Register C"
|
|
hexmask.long 0x00 0.--31. 1. " RC ,Register C Value"
|
|
else
|
|
group.long (0xC0+0x1C)++0x03
|
|
line.long 0x00 "TC3_RC,TC3 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0xC0+0x20)++0x03
|
|
hide.long 0x00 "TC3_SR,TC3 Status Register"
|
|
in
|
|
group.long (0xC0+0x2C)++0x03
|
|
line.long 0x00 "TC3_IMR,TC3 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
tree "TC Channel 4"
|
|
wgroup.long (0x100+0x00)++0x03
|
|
line.long 0x00 "TC4_CCR,TC4 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40080000+0x100+0x4)))&0x8000)==0x8000)
|
|
group.long (0x100+0x04)++0x03
|
|
line.long 0x00 "TC4_CMR,TC4 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x100+0x04)++0x03
|
|
line.long 0x00 "TC4_CMR,TC4 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
sif (cpuis("AT01SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x100+0x8)++0xB
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x100+0x10)++0x03
|
|
line.long 0x00 "TC4_CV,TC4 Counter Value Register"
|
|
hexmask.long 0x00 0.--31. 1. " CV ,Counter Value"
|
|
else
|
|
rgroup.long (0x100+0x10)++0x03
|
|
line.long 0x00 "TC4_CV,TC4 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40080000+0x100+0x4)))&0x8000)==0x8000)
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x100+0x14)++0x7
|
|
line.long 0x00 "TC4_RA,TC4 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC4_RB,TC4 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
line.long 0x00 "TC4_RA,TC4 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC4_RB,TC4 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x100+0x14)++0x07
|
|
line.long 0x00 "TC4_RA,TC4 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC4_RB,TC4 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
rgroup.long (0x100+0x14)++0x07
|
|
line.long 0x00 "TC4_RA,TC4 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC4_RB,TC4 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x100+0x1C)++0x3
|
|
line.long 0x00 "TC4_RC,TC4 Register C"
|
|
hexmask.long 0x00 0.--31. 1. " RC ,Register C Value"
|
|
else
|
|
group.long (0x100+0x1C)++0x03
|
|
line.long 0x00 "TC4_RC,TC4 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0x100+0x20)++0x03
|
|
hide.long 0x00 "TC4_SR,TC4 Status Register"
|
|
in
|
|
group.long (0x100+0x2C)++0x03
|
|
line.long 0x00 "TC4_IMR,TC4 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
tree "TC Channel 5"
|
|
wgroup.long (0x140+0x00)++0x03
|
|
line.long 0x00 "TC5_CCR,TC5 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40080000+0x140+0x4)))&0x8000)==0x8000)
|
|
group.long (0x140+0x04)++0x03
|
|
line.long 0x00 "TC5_CMR,TC5 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x140+0x04)++0x03
|
|
line.long 0x00 "TC5_CMR,TC5 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
sif (cpuis("AT01SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x140+0x8)++0xB
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x140+0x10)++0x03
|
|
line.long 0x00 "TC5_CV,TC5 Counter Value Register"
|
|
hexmask.long 0x00 0.--31. 1. " CV ,Counter Value"
|
|
else
|
|
rgroup.long (0x140+0x10)++0x03
|
|
line.long 0x00 "TC5_CV,TC5 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40080000+0x140+0x4)))&0x8000)==0x8000)
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x140+0x14)++0x7
|
|
line.long 0x00 "TC5_RA,TC5 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC5_RB,TC5 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
line.long 0x00 "TC5_RA,TC5 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC5_RB,TC5 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x140+0x14)++0x07
|
|
line.long 0x00 "TC5_RA,TC5 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC5_RB,TC5 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
rgroup.long (0x140+0x14)++0x07
|
|
line.long 0x00 "TC5_RA,TC5 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC5_RB,TC5 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x140+0x1C)++0x3
|
|
line.long 0x00 "TC5_RC,TC5 Register C"
|
|
hexmask.long 0x00 0.--31. 1. " RC ,Register C Value"
|
|
else
|
|
group.long (0x140+0x1C)++0x03
|
|
line.long 0x00 "TC5_RC,TC5 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0x140+0x20)++0x03
|
|
hide.long 0x00 "TC5_SR,TC5 Status Register"
|
|
in
|
|
group.long (0x140+0x2C)++0x03
|
|
line.long 0x00 "TC5_IMR,TC5 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
else
|
|
tree "TC Channel 0"
|
|
wgroup.long (0x0+0x00)++0x03
|
|
line.long 0x00 "TC0_CCR,TC0 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40080000+0x0+0x4)))&0x8000)==0x8000)
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "TC0_CMR,TC0 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
sif (cpuis("AT01SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x0+0x8)++0xB
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x0+0x10)++0x03
|
|
line.long 0x00 "TC0_CV,TC0 Counter Value Register"
|
|
hexmask.long 0x00 0.--31. 1. " CV ,Counter Value"
|
|
else
|
|
rgroup.long (0x0+0x10)++0x03
|
|
line.long 0x00 "TC0_CV,TC0 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40080000+0x0+0x4)))&0x8000)==0x8000)
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x0+0x14)++0x7
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
group.long (0x0+0x14)++0x7
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x0+0x14)++0x07
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
rgroup.long (0x0+0x14)++0x07
|
|
line.long 0x00 "TC0_RA,TC0 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC0_RB,TC0 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x0+0x1C)++0x3
|
|
line.long 0x00 "TC0_RC,TC0 Register C"
|
|
hexmask.long 0x00 0.--31. 1. " RC ,Register C Value"
|
|
else
|
|
group.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "TC0_RC,TC0 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0x0+0x20)++0x03
|
|
hide.long 0x00 "TC0_SR,TC0 Status Register"
|
|
in
|
|
group.long (0x0+0x2C)++0x03
|
|
line.long 0x00 "TC0_IMR,TC0 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
tree "TC Channel 1"
|
|
wgroup.long (0x40+0x00)++0x03
|
|
line.long 0x00 "TC1_CCR,TC1 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40080000+0x40+0x4)))&0x8000)==0x8000)
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "TC1_CMR,TC1 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
sif (cpuis("AT01SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x40+0x8)++0xB
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x40+0x10)++0x03
|
|
line.long 0x00 "TC1_CV,TC1 Counter Value Register"
|
|
hexmask.long 0x00 0.--31. 1. " CV ,Counter Value"
|
|
else
|
|
rgroup.long (0x40+0x10)++0x03
|
|
line.long 0x00 "TC1_CV,TC1 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40080000+0x40+0x4)))&0x8000)==0x8000)
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x40+0x14)++0x7
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
group.long (0x40+0x14)++0x7
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x40+0x14)++0x07
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
rgroup.long (0x40+0x14)++0x07
|
|
line.long 0x00 "TC1_RA,TC1 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC1_RB,TC1 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x40+0x1C)++0x3
|
|
line.long 0x00 "TC1_RC,TC1 Register C"
|
|
hexmask.long 0x00 0.--31. 1. " RC ,Register C Value"
|
|
else
|
|
group.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "TC1_RC,TC1 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0x40+0x20)++0x03
|
|
hide.long 0x00 "TC1_SR,TC1 Status Register"
|
|
in
|
|
group.long (0x40+0x2C)++0x03
|
|
line.long 0x00 "TC1_IMR,TC1 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
tree "TC Channel 2"
|
|
wgroup.long (0x80+0x00)++0x03
|
|
line.long 0x00 "TC2_CCR,TC2 Channel Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled"
|
|
if (((data.long((ad:0x40080000+0x80+0x4)))&0x8000)==0x8000)
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "TC2_CMR,TC2 Channel Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Clear,Toggle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "TC2_CMR,TC2 Channel Mode Register"
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA"
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
sif (cpuis("AT01SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x80+0x8)++0xB
|
|
line.long 0x00 "TC_SMMR0,TC Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray Count Enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x80+0x10)++0x03
|
|
line.long 0x00 "TC2_CV,TC2 Counter Value Register"
|
|
hexmask.long 0x00 0.--31. 1. " CV ,Counter Value"
|
|
else
|
|
rgroup.long (0x80+0x10)++0x03
|
|
line.long 0x00 "TC2_CV,TC2 Counter Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value"
|
|
endif
|
|
if (((data.long((ad:0x40080000+0x80+0x4)))&0x8000)==0x8000)
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x80+0x14)++0x7
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
group.long (0x80+0x14)++0x7
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
else
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long (0x80+0x14)++0x07
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
hexmask.long 0x00 0.--31. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
hexmask.long 0x04 0.--31. 1. " RB ,Register B Value"
|
|
else
|
|
rgroup.long (0x80+0x14)++0x07
|
|
line.long 0x00 "TC2_RA,TC2 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value"
|
|
line.long 0x04 "TC2_RB,TC2 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value"
|
|
endif
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long (0x80+0x1C)++0x3
|
|
line.long 0x00 "TC2_RC,TC2 Register C"
|
|
hexmask.long 0x00 0.--31. 1. " RC ,Register C Value"
|
|
else
|
|
group.long (0x80+0x1C)++0x03
|
|
line.long 0x00 "TC2_RC,TC2 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value"
|
|
endif
|
|
hgroup.long (0x80+0x20)++0x03
|
|
hide.long 0x00 "TC2_SR,TC2 Status Register"
|
|
in
|
|
group.long (0x80+0x2C)++0x03
|
|
line.long 0x00 "TC2_IMR,TC2 Interrupt Mask Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree "HSMCI (High Speed MultiMedia Card Interface)"
|
|
base ad:0x40000000
|
|
width 0xd
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "HSMCI_CR,MCI Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No effect,Reset"
|
|
bitfld.long 0x00 3. " PWSDIS ,Power Save Mode Disable" "No effect,Disables"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PWSEN ,Power Save Mode Enable" "No effect,Enables"
|
|
bitfld.long 0x00 1. " HSMCIDIS ,Multi-Media Interface Disable" "No effect,Disables"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MCIEN ,Multi-Media Interface Enable" "No effect,Enables"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "HSMCI_MR,MCI Mode Register"
|
|
sif (cpuis("ATSAM4E*"))
|
|
bitfld.long 0x00 16. " CLKODD ,Clock divider is odd" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PDCMODE ,PDC-oriented Mode" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("ATSAM4S*"))
|
|
bitfld.long 0x00 15. " PDCMODE ,PDC-oriented Mode" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
hexmask.long.word 0x00 16.--31. 1. " BLKLEN ,Data Block Length"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14. " PADV ,Padding Value" "0x00,0xFF"
|
|
bitfld.long 0x00 13. " FBYTE ,Force Byte Transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " WRPROOF ,Write Proof Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RDPROOF ,Read Proof Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " PWSDIV ,Power Saving Divider" "Clock/2,Clock/3,Clock/5,Clock/9,Clock/17,Clock/33,Clock/65,Clock/129"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLKDIV ,Clock Divider"
|
|
group.long 0x08++0xb
|
|
line.long 0x0 "HSMCI_DTOR,MCI Data Timeout Register"
|
|
bitfld.long 0x0 4.--6. " DTOMUL ,Data Timeout Multiplier" "1,16,128,256,1024,4096,65536,1048576"
|
|
bitfld.long 0x0 0.--3. " DTOCYC ,Data Timeout Cycle Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "HSMCI_SDCR,MCI SDCard Register"
|
|
bitfld.long 0x04 6.--7. " SDCBUS ,SDCard Bus Width" "1-bit,,4-bit,8-bit"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x04 0.--1. " SDCSEL ,SDCard Slot" "A,B,?..."
|
|
else
|
|
bitfld.long 0x04 0.--1. " SDCSEL ,SDCard Slot" "A,?..."
|
|
endif
|
|
line.long 0x08 "HSMCI_ARGR,MCI Argument Register"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "HSMCI_CMDR,MCI Command Register"
|
|
bitfld.long 0x00 27. " BOOT_ACK ,Boot Operation Acknowledge" "Not expected,Expect"
|
|
textline " "
|
|
bitfld.long 0x00 26. " ATACS ,ATA with Command Completion Signal" "Normal,With completion"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " IOSPCMD ,SDIO Special Command" "No SDIO Special,SDIO Suspend,SDIO Resume,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " TRTYP ,Transfer Type" "Single Block,Multiple Block,Stream,,SDIO Byte,SDIO Block,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18. " TRDIR ,Transfer Direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " TRCMD ,Transfer Command" "No transferred,Start,Stop,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12. " MAXLAT ,Max Latency for Command to Response" "5-cycle,64-cycle"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OPDCMD ,Open Drain Command" "Push pull,Open drain"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " SPCMD ,Special Command" "Not special,Initialization,Synchronize,CE-ATA Completion Signal disable,Interrupt command,Interrupt response,Boot Operation Request,End Boot Operation"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " RSPTYP ,Response Type" "No response,48-bit,136-bit,R1b"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " CMDNB ,Command Number"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "HSMCI_BLKR,Block Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BLKLEN ,Data Block Length"
|
|
hexmask.long.word 0x00 0.--15. 1. " BCNT ,MMC/SDIO Block Count - SDIO Byte Count"
|
|
line.long 0x04 "HSMCI_CSTOR,HSMCI Completion Signal Timeout Register"
|
|
bitfld.long 0x04 4.--6. " CSTOMUL ,Completion Signal Timeout Multiplier" "1,16,128,256,1024,4096,65536,1048576"
|
|
bitfld.long 0x04 0.--3. " CSTOCYC ,Completion Signal Timeout Cycle Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x20++0xF
|
|
line.long 0x00 "HSMCI_RSPR0,MCI Response Register 0"
|
|
line.long 0x04 "HSMCI_RSPR1,MCI Response Register 1"
|
|
line.long 0x08 "HSMCI_RSPR2,MCI Response Register 2"
|
|
line.long 0x0c "HSMCI_RSPR3,MCI Response Register 3"
|
|
hgroup.long 0x30++0x3
|
|
hide.long 0x0 "HSMCI_RDR,MCI Receive Data Register"
|
|
in
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "HSMCI_TDR,MCI Transmit Data Register"
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "HSMCI_SR,MCI Status Register"
|
|
in
|
|
group.long 0x4c++0x3
|
|
line.long 0x0 "HSMCI_IMR,MCI Interrupt Mask Register"
|
|
setclrfld.long 0x0 31. -0x08 31. -0x4 31. " UNRE_set/clr ,UnderRun Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. -0x08 30. -0x4 30. " OVRE_set/clr ,Overrun Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 29. -0x08 29. -0x4 29. " ACKRCVE_set/clr ,Boot Operation Acknowledge Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 28. -0x08 28. -0x4 28. " ACKRCV_set/clr ,Boot Operation Acknowledge Received Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x08 27. -0x4 27. " XFRDONE_set/clr ,Transfer Done Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 26. -0x08 26. -0x4 26. " FIFOEMPTY_set/clr ,FIFO Empty Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("ATSAM4S*")&&!cpuis("ATSAM4E*"))
|
|
setclrfld.long 0x0 25. -0x08 25. -0x4 25. " DMADONE_set/clr ,DMA Transfer Completed Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 24. -0x08 24. -0x4 24. " BLKOVRE_set/clr ,DMA Block Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 23. -0x08 23. -0x4 23. " CSTOE_set/clr ,Completion Signal Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 22. -0x08 22. -0x4 22. " DTOE_set/clr ,Data Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 21. -0x08 21. -0x4 21. " DCRCE_set/clr ,Data CRC Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 20. -0x08 20. -0x4 20. " RTOE_set/clr ,Response Time-out Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 19. -0x08 19. -0x4 19. " RENDE_set/clr ,Response End Bit Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 18. -0x08 18. -0x4 18. " RCRCE_set/clr ,Response CRC Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x08 17. -0x4 17. " RDIRE_set/clr ,Response Direction Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 16. -0x08 16. -0x4 16. " RINDE_set/clr ,Response Index Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ATSAM4S*")||cpuis("ATSAM4E*"))
|
|
setclrfld.long 0x0 15. -0x08 15. -0x4 15. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x08 14. -0x4 14. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 13. -0x08 13. -0x4 13. " CSRCV_set/clr ,Completion Signal Received Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x08 12. -0x4 12. " SDIOWAIT_set/clr ,SDIO Read Wait Operation Status Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x08 8. -0x4 8. " SDIOIRQA_set/clr ,SDIOIRQA Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ATSAM4S*")||cpuis("ATSAM4E*"))
|
|
setclrfld.long 0x0 7. -0x08 7. -0x4 7. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x08 6. -0x4 6. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x0 5. -0x08 5. -0x4 5. " NOTBUSY_set/clr ,Data Not Busy Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x08 4. -0x4 4. " DTIP_set/clr ,Data Transfer In Progress Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x08 3. -0x4 3. " BLKE_set/clr ,Data Block Ended Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x08 2. -0x4 2. " TXRDY_set/clr ,Transmit Ready Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x08 1. -0x4 1. " RXRDY_set/clr ,Receiver Ready Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x08 0. -0x4 0. " CMDRDY_set/clr ,Command Ready Interrupt Mask" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAM4S*"))
|
|
group.long 0x50++0x3
|
|
line.long 0x00 "HSMCI_DMA,HSMCI DMA Configuration Register"
|
|
bitfld.long 0x00 12. " ROPT ,Read Optimization with padding" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DMAEN ,DMA Hardware Handshaking Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CHKSIZE ,DMA Channel Read and Write Chunk Size" "1,4"
|
|
bitfld.long 0x00 0.--1. " OFFSET ,DMA Write Buffer Offset" "0,1,2,3"
|
|
endif
|
|
group.long 0x54++0x3
|
|
line.long 0x00 "HSMCI_CFG,HSMCI Configuration Register"
|
|
bitfld.long 0x00 12. " LSYNC ,Synchronize on the last block" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HSMODE ,High Speed Mode" "Normal,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " FERRCTRL ,Flow Error flag reset control mode" "Write/Read command,Read status"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FIFOMODE ,HSMCI Internal FIFO control mode" "Sufficient level,One data written"
|
|
group.long 0xe4++0x3
|
|
line.long 0x00 "HSMCI_WPMR,HSMCI Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WP_KEY ,HSMCI Write Protect Mode Register"
|
|
bitfld.long 0x00 0. " WP_EN ,Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "HSMCI_WPSR,HSMCI Write Protect Status Register"
|
|
in
|
|
group.long 0x200++0x3
|
|
hide.long 0x00 "HSMCI_FIFO$2,HSMCI FIFO Memory Aperture"
|
|
button "FIFO Memory Aperture" "d (ad:0x40000000+0x200)--(ad:0x40000000+0x5FF) /long"
|
|
width 0xb
|
|
tree.end
|
|
tree "PWM (Pulse Width Modulation Controller)"
|
|
base ad:0x40094000
|
|
width 0x11
|
|
tree "Common Registers"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PWM_CLK,PWM Clock Register"
|
|
bitfld.long 0x00 24.--27. " PREB ,Divider Input Clock" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,?..."
|
|
hexmask.long.byte 0x00 16.--23. 1. " DIVB ,CLKB Divide Factor"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " PREA ,Divider Input Clock" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIVA ,CLKA Divide Factor"
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "PWM_SR,PWM Disable/Enable and Status Register"
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " CHID7_set/clr ,PWM output for channel 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " CHID6_set/clr ,PWM output for channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " CHID5_set/clr ,PWM output for channel 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " CHID4_set/clr ,PWM output for channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " CHID3_set/clr ,PWM output for channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " CHID2_set/clr ,PWM output for channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " CHID1_set/clr ,PWM output for channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " CHID0_set/clr ,PWM output for channel 0" "Disabled,Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PWM_IMR1,PWM Interrupt Enable/Mask Register"
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 23. -0x8 23. -0x4 23. " FCHID7_set/clr ,Fault Protection Trigger on Channel 7 Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x8 22. -0x4 22. " FCHID6_set/clr ,Fault Protection Trigger on Channel 6 Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x8 21. -0x4 21. " FCHID5_set/clr ,Fault Protection Trigger on Channel 5 Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x8 20. -0x4 20. " FCHID4_set/clr ,Fault Protection Trigger on Channel 4 Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " FCHID3_set/clr ,Fault Protection Trigger on Channel 3 Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " FCHID2_set/clr ,Fault Protection Trigger on Channel 2 Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " FCHID1_set/clr ,Fault Protection Trigger on Channel 1 Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " FCHID0_set/clr ,Fault Protection Trigger on Channel 0 Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 7. -0x8 7. -0x4 7. " CHID7_set/clr ,Counter Event on Channel 7 Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x8 6. -0x4 6. " CHID6_set/clr ,Counter Event on Channel 6 Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x8 5. -0x4 5. " CHID5_set/clr ,Counter Event on Channel 5 Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x8 4. -0x4 4. " CHID4_set/clr ,Counter Event on Channel 4 Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " CHID3_set/clr ,Counter Event on Channel 3 Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " CHID2_set/clr ,Counter Event on Channel 2 Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " CHID1_set/clr ,Counter Event on Channel 1 Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " CHID0_set/clr , Counter Event on Channel 0 Interrupt" "Disabled,Enabled"
|
|
hgroup.long 0x1c++0x03
|
|
hide.long 0x0 "PWM_ISR1,PWM Interrupt Status Register 1"
|
|
in
|
|
width 0x11
|
|
if ((d.l(ad:0x40094000+0x20)&0x30000)==0x20000)
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "PWM_SCM,PWM Sync Channels Mode Register"
|
|
sif (cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36"))
|
|
bitfld.long 0x00 16.--17. " UPDM ,Synchronous Channels Update Mode (write of duty-cycle update registers/update of synchronous channels)" "Manual/Manual,Manual/Automatic,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 21.--23. " PTRCS ,PDC Transfer Request Comparison Selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. " PTRM ,PDC Transfer Request Mode (WRDY flag and PDC transfer request)" "Update period is elapsed,Selected comparison matches"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " UPDM ,Synchronous Channels Update Mode (write of duty-cycle update registers/update of synchronous channels)" "Manual/Manual,Manual/Automatic,Automatic/Automatic,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 7. " SYNC7 ,Synchronous Channel 7" "Not synchronous,Synchronous"
|
|
bitfld.long 0x00 6. " SYNC6 ,Synchronous Channel 6" "Not synchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SYNC5 ,Synchronous Channel 5" "Not synchronous,Synchronous"
|
|
bitfld.long 0x00 4. " SYNC4 ,Synchronous Channel 4" "Not synchronous,Synchronous"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " SYNC3 ,Synchronous Channel 3" "Not synchronous,Synchronous"
|
|
bitfld.long 0x00 2. " SYNC2 ,Synchronous Channel 2" "Not synchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SYNC1 ,Synchronous Channel 1" "Not synchronous,Synchronous"
|
|
bitfld.long 0x00 0. " SYNC0 ,Synchronous Channel 0" "Not synchronous,Synchronous"
|
|
elif ((d.l(ad:0x40094000+0x20)&0x30000)==0x10000)
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "PWM_SCM,PWM Sync Channels Mode Register"
|
|
sif (cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36"))
|
|
bitfld.long 0x00 16.--17. " UPDM ,Synchronous Channels Update Mode (write of duty-cycle update registers/update of synchronous channels)" "Manual/Manual,Manual/Automatic,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 21.--23. " PTRCS ,PDC Transfer Request Comparison Selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. " PTRM ,PDC Transfer Request Mode (WRDY flag/PDC transfer request)" "Update period is elapsed/Never set,Update period is elapsed/Never set"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " UPDM ,Synchronous Channels Update Mode (write of duty-cycle update registers/update of synchronous channels)" "Manual/Manual,Manual/Automatic,Automatic/Automatic,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 7. " SYNC7 ,Synchronous Channel 7" "Not synchronous,Synchronous"
|
|
bitfld.long 0x00 6. " SYNC6 ,Synchronous Channel 6" "Not synchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SYNC5 ,Synchronous Channel 5" "Not synchronous,Synchronous"
|
|
bitfld.long 0x00 4. " SYNC4 ,Synchronous Channel 4" "Not synchronous,Synchronous"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " SYNC3 ,Synchronous Channel 3" "Not synchronous,Synchronous"
|
|
bitfld.long 0x00 2. " SYNC2 ,Synchronous Channel 2" "Not synchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SYNC1 ,Synchronous Channel 1" "Not synchronous,Synchronous"
|
|
bitfld.long 0x00 0. " SYNC0 ,Synchronous Channel 0" "Not synchronous,Synchronous"
|
|
else
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "PWM_SCM,PWM Sync Channels Mode Register"
|
|
sif (cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36"))
|
|
bitfld.long 0x00 16.--17. " UPDM ,Synchronous Channels Update Mode (write of duty-cycle update registers/update of synchronous channels)" "Manual/Manual,Manual/Automatic,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 21.--23. " PTRCS ,PDC Transfer Request Comparison Selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. " PTRM ,PDC Transfer Request Mode(WRDY flag/PDC transfer request)" "Never set/Never set,Never set/Never set"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " UPDM ,Synchronous Channels Update Mode (write of duty-cycle update registers/update of synchronous channels)" "Manual/Manual,Manual/Automatic,Automatic/Automatic,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 7. " SYNC7 ,Synchronous Channel 7" "Not synchronous,Synchronous"
|
|
bitfld.long 0x00 6. " SYNC6 ,Synchronous Channel 6" "Not synchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SYNC5 ,Synchronous Channel 5" "Not synchronous,Synchronous"
|
|
bitfld.long 0x00 4. " SYNC4 ,Synchronous Channel 4" "Not synchronous,Synchronous"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " SYNC3 ,Synchronous Channel 3" "Not synchronous,Synchronous"
|
|
bitfld.long 0x00 2. " SYNC2 ,Synchronous Channel 2" "Not synchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SYNC1 ,Synchronous Channel 1" "Not synchronous,Synchronous"
|
|
bitfld.long 0x00 0. " SYNC0 ,Synchronous Channel 0" "Not synchronous,Synchronous"
|
|
endif
|
|
group.long 0x28++0x7
|
|
line.long 0x00 "PWM_SCUC,PWM Sync Channels Update Control Register"
|
|
bitfld.long 0x00 0. " UPDULOCK ,Synchronous Channels Update Unlock" "No effect,Update"
|
|
line.long 0x04 "PWM_SCUP,PWM Sync Channels Update Period Register"
|
|
bitfld.long 0x04 4.--7. " UPRCNT ,Update Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. " UPR ,Update Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long 0x30++0x3
|
|
line.long 0x00 "PWM_SCUPUPD,PWM Sync Channels Update Period Update Register"
|
|
bitfld.long 0x00 0.--3. " UPRUPD ,Update Period Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x3c++0x3
|
|
line.long 0x00 "PWM_IMR2,PWM Interrupt Mask Register 2"
|
|
setclrfld.long 0x00 23. -0x8 23. -0x4 23. " CMPU7_set/clr ,Comparison 7 Update Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x8 22. -0x4 22. " CMPU6_set/clr ,Comparison 6 Update Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 21. -0x8 21. -0x4 21. " CMPU5_set/clr ,Comparison 5 Update Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x8 20. -0x4 20. " CMPU4_set/clr ,Comparison 4 Update Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x8 19. -0x4 19. " CMPU3_set/clr ,Comparison 3 Update Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x8 18. -0x4 18. " CMPU2_set/clr ,Comparison 2 Update Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. -0x8 17. -0x4 17. " CMPU1_set/clr ,Comparison 1 Update Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x8 16. -0x4 16. " CMPU0_set/clr ,Comparison 0 Update Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x8 15. -0x4 15. " CMPM7_set/clr ,Comparison 7 Match Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x8 14. -0x4 14. " CMPM6_set/clr ,Comparison 6 Match Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x8 13. -0x4 13. " CMPM5_set/clr ,Comparison 5 Match Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x8 12. -0x4 12. " CMPM4_set/clr ,Comparison 4 Match Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. -0x8 11. -0x4 11. " CMPM3_set/clr ,Comparison 3 Match Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x8 10. -0x4 10. " CMPM2_set/clr ,Comparison 2 Match Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x8 9. -0x4 9. " CMPM1_set/clr ,Comparison 1 Match Interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x8 8. -0x4 8. " CMPM0_set/clr ,Comparison 0 Match Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. -0x8 3. -0x4 3. " UNRE_set/clr ,Synchronous Channels Update Underrun Error Interrupt" "Disabled,Enabled"
|
|
sif (!cpuis("ATSAMA5D31")&&!cpuis("ATSAMA5D33")&&!cpuis("ATSAMA5D34")&&!cpuis("ATSAMA5D35")&&!cpuis("ATSAMA5D36"))
|
|
setclrfld.long 0x00 2. -0x8 2. -0x4 2. " TXBUFE_set/clr ,PDC TX Buffer Empty Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x8 1. -0x4 1. " ENDTX_set/clr ,PDC End of TX Buffer Interrupt" "Disabled,Enabled"
|
|
endif
|
|
setclrfld.long 0x00 0. -0x8 0. -0x4 0. " WRDY_set/clr ,Write Ready for Synchronous Channels Update Interrupt" "Disabled,Enabled"
|
|
hgroup.long 0x40++0x3
|
|
hide.long 0x00 "PWM_ISR2,PWM Interrupt Status Register 2"
|
|
in
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "PWM_OOV,PWM Output Override Value Register"
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 23. " OOVL7 ,Output Override Value for PWML output of the channel 7" "Low,High"
|
|
bitfld.long 0x00 22. " OOVL6 ,Output Override Value for PWML output of the channel 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " OOVL5 ,Output Override Value for PWML output of the channel 5" "Low,High"
|
|
bitfld.long 0x00 20. " OOVL4 ,Output Override Value for PWML output of the channel 4" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " OOVL3 ,Output Override Value for PWML output of the channel 3" "Low,High"
|
|
bitfld.long 0x00 18. " OOVL2 ,Output Override Value for PWML output of the channel 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " OOVL1 ,Output Override Value for PWML output of the channel 1" "Low,High"
|
|
bitfld.long 0x00 16. " OOVL0 ,Output Override Value for PWML output of the channel 0" "Low,High"
|
|
textline " "
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 7. " OOVH7 ,Output Override Value for PWMH output of the channel 7" "Low,High"
|
|
bitfld.long 0x00 6. " OOVH6 ,Output Override Value for PWMH output of the channel 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " OOVH5 ,Output Override Value for PWMH output of the channel 5" "Low,High"
|
|
bitfld.long 0x00 4. " OOVH4 ,Output Override Value for PWMH output of the channel 4" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 3. " OOVH3 ,Output Override Value for PWMH output of the channel 3" "Low,High"
|
|
bitfld.long 0x00 2. " OOVH2 ,Output Override Value for PWMH output of the channel 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OOVH1 ,Output Override Value for PWMH output of the channel 1" "Low,High"
|
|
bitfld.long 0x00 0. " OOVH0 ,Output Override Value for PWMH output of the channel 0" "Low,High"
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "PWM_OS,PWM Output Selection Register"
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " OSL7_set/clr ,Output Selection for PWML output of the channel 7" "DTOL3,OOVL3"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " OSL6_set/clr ,Output Selection for PWML output of the channel 6" "DTOL2,OOVL2"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " OSL5_set/clr ,Output Selection for PWML output of the channel 5" "DTOL1,OOVL1"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " OSL4_set/clr ,Output Selection for PWML output of the channel 4" "DTOL0,OOVL0"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " OSL3_set/clr ,Output Selection for PWML output of the channel 3" "DTOL3,OOVL3"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " OSL2_set/clr ,Output Selection for PWML output of the channel 2" "DTOL2,OOVL2"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " OSL1_set/clr ,Output Selection for PWML output of the channel 1" "DTOL1,OOVL1"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " OSL0_set/clr ,Output Selection for PWML output of the channel 0" "DTOL0,OOVL0"
|
|
textline " "
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " OSH7_set/clr ,Output Selection for PWMH output of the channel 7" "DTOH3,OOVH3"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " OSH6_set/clr ,Output Selection for PWMH output of the channel 6" "DTOH2,OOVH2"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " OSH5_set/clr ,Output Selection for PWMH output of the channel 5" "DTOH1,OOVH1"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " OSH4_set/clr ,Output Selection for PWMH output of the channel 4" "DTOH0,OOVH0"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " OSH3_set/clr ,Output Selection for PWMH output of the channel 3" "DTOH3,OOVH3"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " OSH2_set/clr ,Output Selection for PWMH output of the channel 2" "DTOH2,OOVH2"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " OSH1_set/clr ,Output Selection for PWMH output of the channel 1" "DTOH1,OOVH1"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " OSH0_set/clr ,Output Selection for PWMH output of the channel 0" "DTOH0,OOVH0"
|
|
wgroup.long 0x54++0x7
|
|
line.long 0x00 "PWM_OSSUPD,PWM Output Selection Set Update Register"
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 23. " OSSUPL7 ,Output Selection Set for PWML output of the channel 7" "No effect,OOVL3"
|
|
bitfld.long 0x00 22. " OSSUPL6 ,Output Selection Set for PWML output of the channel 6" "No effect,OOVL2"
|
|
textline " "
|
|
bitfld.long 0x00 21. " OSSUPL5 ,Output Selection Set for PWML output of the channel 5" "No effect,OOVL1"
|
|
bitfld.long 0x00 20. " OSSUPL4 ,Output Selection Set for PWML output of the channel 4" "No effect,OOVL0"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " OSSUPL3 ,Output Selection Set for PWML output of the channel 3" "No effect,OOVL3"
|
|
bitfld.long 0x00 18. " OSSUPL2 ,Output Selection Set for PWML output of the channel 2" "No effect,OOVL2"
|
|
textline " "
|
|
bitfld.long 0x00 17. " OSSUPL1 ,Output Selection Set for PWML output of the channel 1" "No effect,OOVL1"
|
|
bitfld.long 0x00 16. " OSSUPL0 ,Output Selection Set for PWML output of the channel 0" "No effect,OOVL0"
|
|
textline " "
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 7. " OSSUPH7 ,Output Selection Set for PWMH output of the channel 7" "No effect,OOVH3"
|
|
bitfld.long 0x00 6. " OSSUPH6 ,Output Selection Set for PWMH output of the channel 6" "No effect,OOVH2"
|
|
textline " "
|
|
bitfld.long 0x00 5. " OSSUPH5 ,Output Selection Set for PWMH output of the channel 5" "No effect,OOVH1"
|
|
bitfld.long 0x00 4. " OSSUPH4 ,Output Selection Set for PWMH output of the channel 4" "No effect,OOVH0"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 3. " OSSUPH3 ,Output Selection Set for PWMH output of the channel 3" "No effect,OOVH3"
|
|
bitfld.long 0x00 2. " OSSUPH2 ,Output Selection Set for PWMH output of the channel 2" "No effect,OOVH2"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OSSUPH1 ,Output Selection Set for PWMH output of the channel 1" "No effect,OOVH1"
|
|
bitfld.long 0x00 0. " OSSUPH0 ,Output Selection Set for PWMH output of the channel 0" "No effect,OOVH0"
|
|
line.long 0x04 "PWM_OSCUPD,PWM Output Selection Clear Update Register"
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x04 23. " OSCUPL7 ,Output Selection Clear for PWML output of the channel 7" "Clear,OOVL3"
|
|
bitfld.long 0x04 22. " OSCUPL6 ,Output Selection Clear for PWML output of the channel 6" "Clear,OOVL2"
|
|
textline " "
|
|
bitfld.long 0x04 21. " OSCUPL5 ,Output Selection Clear for PWML output of the channel 5" "Clear,OOVL1"
|
|
bitfld.long 0x04 20. " OSCUPL4 ,Output Selection Clear for PWML output of the channel 4" "Clear,OOVL0"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 19. " OSCUPL3 ,Output Selection Clear for PWML output of the channel 3" "Clear,OOVL3"
|
|
bitfld.long 0x04 18. " OSCUPL2 ,Output Selection Clear for PWML output of the channel 2" "Clear,OOVL2"
|
|
textline " "
|
|
bitfld.long 0x04 17. " OSCUPL1 ,Output Selection Clear for PWML output of the channel 1" "Clear,OOVL1"
|
|
bitfld.long 0x04 16. " OSCUPL0 ,Output Selection Clear for PWML output of the channel 0" "Clear,OOVL0"
|
|
textline " "
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x04 7. " OSCUPH7 ,Output Selection Clear for PWMH output of the channel 7" "Clear,OOVH3"
|
|
bitfld.long 0x04 6. " OSCUPH6 ,Output Selection Clear for PWMH output of the channel 6" "Clear,OOVH2"
|
|
textline " "
|
|
bitfld.long 0x04 5. " OSCUPH5 ,Output Selection Clear for PWMH output of the channel 5" "Clear,OOVH1"
|
|
bitfld.long 0x04 4. " OSCUPH4 ,Output Selection Clear for PWMH output of the channel 4" "Clear,OOVH0"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 3. " OSCUPH3 ,Output Selection Clear for PWMH output of the channel 3" "Clear,OOVH3"
|
|
bitfld.long 0x04 2. " OSCUPH2 ,Output Selection Clear for PWMH output of the channel 2" "Clear,OOVH2"
|
|
textline " "
|
|
bitfld.long 0x04 1. " OSCUPH1 ,Output Selection Clear for PWMH output of the channel 1" "Clear,OOVH1"
|
|
bitfld.long 0x04 0. " OSCUPH0 ,Output Selection Clear for PWMH output of the channel 0" "Clear,OOVH0"
|
|
sif (cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36"))
|
|
group.long 0x5c++0x3
|
|
line.long 0x00 "PWM_FMR,PWM Fault Mode Register"
|
|
bitfld.long 0x00 23. " FFIL7 ,Fault 7 Filtering" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " FFIL6 ,Fault 6 Filtering" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FFIL5 ,Fault 5 Filtering" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " FFIL4 ,Fault 4 Filtering" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FFIL3 ,Fault 3 Filtering" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " FFIL2 ,Fault 2 Filtering" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FFIL1 ,Fault 1 Filtering" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " FFIL0 ,Fault 0 Filtering" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FMOD7 ,Fault 7 Activation Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " FMOD6 ,Fault 6 Activation Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FMOD5 ,Fault 5 Activation Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " FMOD4 ,Fault 4 Activation Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FMOD3 ,Fault 3 Activation Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " FMOD2 ,Fault 2 Activation Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FMOD1 ,Fault 1 Activation Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FMOD0 ,Fault 0 Activation Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FPOL7 ,Fault 7 Polarity" "Active-Low,Active-High"
|
|
bitfld.long 0x00 6. " FPOL6 ,Fault 6 Polarity" "Active-Low,Active-High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FPOL5 ,Fault 5 Polarity" "Active-Low,Active-High"
|
|
bitfld.long 0x00 4. " FPOL4 ,Fault 4 Polarity" "Active-Low,Active-High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FPOL3 ,Fault 3 Polarity" "Active-Low,Active-High"
|
|
bitfld.long 0x00 2. " FPOL2 ,Fault 2 Polarity" "Active-Low,Active-High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FPOL1 ,Fault 1 Polarity" "Active-Low,Active-High"
|
|
bitfld.long 0x00 0. " FPOL0 ,Fault 0 Polarity" "Active-Low,Active-High"
|
|
else
|
|
group.long 0x5c++0x3
|
|
line.long 0x00 "PWM_FMR,PWM Fault Mode Register"
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 23. " FFIL7 ,Fault 7 Polarity" "Active-Low,Active-High"
|
|
bitfld.long 0x00 22. " FFIL6 ,Fault 6 Polarity" "Active-Low,Active-High"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*"))
|
|
bitfld.long 0x00 21. " FFIL5 ,Fault 5 Polarity" "Active-Low,Active-High"
|
|
bitfld.long 0x00 20. " FFIL4 ,Fault 4 Polarity" "Active-Low,Active-High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " FFIL3 ,Fault 3 Polarity" "Active-Low,Active-High"
|
|
bitfld.long 0x00 18. " FFIL2 ,Fault 2 Polarity" "Active-Low,Active-High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FFIL1 ,Fault 1 Polarity" "Active-Low,Active-High"
|
|
bitfld.long 0x00 16. " FFIL0 ,Fault 0 Polarity" "Active-Low,Active-High"
|
|
textline " "
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 15. " FMOD7 ,Fault 7 Activation Mode" "Input level,Input level & clear"
|
|
bitfld.long 0x00 14. " FMOD6 ,Fault 6 Activation Mode" "Input level,Input level & clear"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*"))
|
|
bitfld.long 0x00 13. " FMOD5 ,Fault 5 Activation Mode" "Input level,Input level & clear"
|
|
bitfld.long 0x00 12. " FMOD4 ,Fault 4 Activation Mode" "Input level,Input level & clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 11. " FMOD3 ,Fault 3 Activation Mode" "Input level,Input level & clear"
|
|
bitfld.long 0x00 10. " FMOD2 ,Fault 2 Activation Mode" "Input level,Input level & clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FMOD1 ,Fault 1 Activation Mode" "Input level,Input level & clear"
|
|
bitfld.long 0x00 8. " FMOD0 ,Fault 0 Activation Mode" "Input level,Input level & clear"
|
|
textline " "
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 7. " FPOL7 ,Fault 7 Filtering" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FPOL6 ,Fault 6 Filtering" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*"))
|
|
bitfld.long 0x00 5. " FPOL5 ,Fault 5 Filtering" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FPOL4 ,Fault 4 Filtering" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " FPOL3 ,Fault 3 Filtering" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FPOL2 ,Fault 2 Filtering" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FPOL1 ,Fault 1 Filtering" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FPOL0 ,Fault 0 Filtering" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x60++0x3
|
|
line.long 0x00 "PWM_FSR,PWM Fault Status Register"
|
|
sif (cpuis("AT91SAM3A*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 15. " FS7 , Fault 7 Status" "Inactive,Active"
|
|
bitfld.long 0x00 14. " FS6 ,Fault 6 Status" "Inactive,Active"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*"))
|
|
bitfld.long 0x00 13. " FS5 , Fault 5 Status" "Inactive,Active"
|
|
bitfld.long 0x00 12. " FS4 ,Fault 4 Status" "Inactive,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 11. " FS3 , Fault 3 Status" "Inactive,Active"
|
|
bitfld.long 0x00 10. " FS2 ,Fault 2 Status" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FS1 ,Fault 1 Status" "Inactive,Active"
|
|
bitfld.long 0x00 8. " FS0 ,Fault 0 Status" "Inactive,Active"
|
|
textline " "
|
|
sif (cpuis("AT91SAM3A*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 7. " FIV7 ,Fault Input 7 Value" "Low,High"
|
|
bitfld.long 0x00 6. " FIV6 ,Fault Input 6 Value" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*"))
|
|
bitfld.long 0x00 5. " FIV5 ,Fault Input 5 Value" "Low,High"
|
|
bitfld.long 0x00 4. " FIV4 ,Fault Input 4 Value" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " FIV3 ,Fault Input 3 Value" "Low,High"
|
|
bitfld.long 0x00 2. " FIV2 ,Fault Input 2 Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FIV1 ,Fault Input 1 Value" "Low,High"
|
|
bitfld.long 0x00 0. " FIV0 ,Fault Input 0 Value" "Low,High"
|
|
wgroup.long 0x64++0x3
|
|
line.long 0x00 "PWM_FCR,PWM Fault Clear Register"
|
|
sif (cpuis("AT91SAM3A*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 7. " FCLR6 ,Fault 6 Clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " FCLR7 ,Fault 7 Clear" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*"))
|
|
bitfld.long 0x00 5. " FCLR5 ,Fault 5 Clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " FCLR4 ,Fault 4 Clear" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " FCLR3 ,Fault 3 Clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " FCLR2 ,Fault 2 Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FCLR1 ,Fault 1 Clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " FCLR0 ,Fault 0 Clear" "No effect,Clear"
|
|
group.long 0x68++0x7
|
|
line.long 0x00 "PWM_FPV,PWM Fault Protection Value Register"
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 23. " FPVL7 ,Fault Protection Value for PWML output on channel 7" "Low,High"
|
|
bitfld.long 0x00 22. " FPVL6 ,Fault Protection Value for PWML output on channel 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FPVL5 ,Fault Protection Value for PWML output on channel 5" "Low,High"
|
|
bitfld.long 0x00 20. " FPVL4 ,Fault Protection Value for PWML output on channel 4" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " FPVL3 ,Fault Protection Value for PWML output on channel 3" "Low,High"
|
|
bitfld.long 0x00 18. " FPVL2 ,Fault Protection Value for PWML output on channel 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FPVL1 ,Fault Protection Value for PWML output on channel 1" "Low,High"
|
|
bitfld.long 0x00 16. " FPVL0 ,Fault Protection Value for PWML output on channel 0" "Low,High"
|
|
textline " "
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 7. " FPVH7 ,Fault Protection Value for PWMH output on channel 7" "Low,High"
|
|
bitfld.long 0x00 6. " FPVH6 ,Fault Protection Value for PWMH output on channel 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FPVH5 ,Fault Protection Value for PWMH output on channel 5" "Low,High"
|
|
bitfld.long 0x00 4. " FPVH4 ,Fault Protection Value for PWMH output on channel 4" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " FPVH3 ,Fault Protection Value for PWMH output on channel 3" "Low,High"
|
|
bitfld.long 0x00 2. " FPVH2 ,Fault Protection Value for PWMH output on channel 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FPVH1 ,Fault Protection Value for PWMH output on channel 1" "Low,High"
|
|
bitfld.long 0x00 0. " FPVH0 ,Fault Protection Value for PWMH output on channel 0" "Low,High"
|
|
line.long 0x04 "PWM_FPE,PWM Fault Protection Enable Register"
|
|
sif (cpuis("AT91SAM3A*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x04 31. " FPE3[7] ,Fault Protection Enable with Fault 7 for channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " FPE3[6] ,Fault Protection Enable with Fault 6 for channel 3" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*"))
|
|
bitfld.long 0x04 29. " FPE3[5] ,Fault Protection Enable with Fault 5 for channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " FPE3[4] ,Fault Protection Enable with Fault 4 for channel 3" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 27. " FPE3[3] ,Fault Protection Enable with Fault 3 for channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " FPE3[2] ,Fault Protection Enable with Fault 2 for channel 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FPE3[1] ,Fault Protection Enable with Fault 1 for channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " FPE3[0] ,Fault Protection Enable with Fault 0 for channel 3" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("AT91SAM3A*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x04 23. " FPE2[7] ,Fault Protection Enable with Fault 7 for channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " FPE2[6] ,Fault Protection Enable with Fault 6 for channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*"))
|
|
bitfld.long 0x04 21. " FPE2[5] ,Fault Protection Enable with Fault 5 for channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " FPE2[4] ,Fault Protection Enable with Fault 4 for channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 19. " FPE2[3] ,Fault Protection Enable with Fault 3 for channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " FPE2[2] ,Fault Protection Enable with Fault 2 for channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FPE2[1] ,Fault Protection Enable with Fault 1 for channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " FPE2[0] ,Fault Protection Enable with Fault 0 for channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("AT91SAM3A*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x04 15. " FPE1[7] ,Fault Protection Enable with Fault 7 for channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " FPE1[6] ,Fault Protection Enable with Fault 6 for channel 1" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*"))
|
|
bitfld.long 0x04 13. " FPE1[5] ,Fault Protection Enable with Fault 5 for channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " FPE1[4] ,Fault Protection Enable with Fault 4 for channel 1" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 11. " FPE1[3] ,Fault Protection Enable with Fault 3 for channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " FPE1[2] ,Fault Protection Enable with Fault 2 for channel 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FPE1[1] ,Fault Protection Enable with Fault 1 for channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " FPE1[0] ,Fault Protection Enable with Fault 0 for channel 1" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("AT91SAM3A*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36"))
|
|
bitfld.long 0x04 7. " FPE0[7] ,Fault Protection Enable with Fault 7 for channel 0" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " FPE0[6] ,Fault Protection Enable with Fault 6 for channel 0" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("AT91SAM3A*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*"))
|
|
bitfld.long 0x04 5. " FPE0[5] ,Fault Protection Enable with Fault 5 for channel 0" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " FPE0[4] ,Fault Protection Enable with Fault 4 for channel 0" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 3. " FPE0[3] ,Fault Protection Enable with Fault 3 for channel 0" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " FPE0[2] ,Fault Protection Enable with Fault 2 for channel 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FPE0[1] ,Fault Protection Enable with Fault 1 for channel 0" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " FPE0[0] ,Fault Protection Enable with Fault 0 for channel 0" "Disabled,Enabled"
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "PWM_FPE2,PWM Fault Protection Enable Register 2"
|
|
bitfld.long 0x00 31. " FPE3[7] ,Fault Protection Enable with Fault 7 for channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " FPE3[6] ,Fault Protection Enable with Fault 6 for channel 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FPE3[5] ,Fault Protection Enable with Fault 5 for channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FPE3[4] ,Fault Protection Enable with Fault 4 for channel 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FPE3[3] ,Fault Protection Enable with Fault 3 for channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " FPE3[2] ,Fault Protection Enable with Fault 2 for channel 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FPE3[1] ,Fault Protection Enable with Fault 1 for channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " FPE3[0] ,Fault Protection Enable with Fault 0 for channel 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FPE2[7] ,Fault Protection Enable with Fault 7 for channel 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " FPE2[6] ,Fault Protection Enable with Fault 6 for channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FPE2[5] ,Fault Protection Enable with Fault 5 for channel 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " FPE2[4] ,Fault Protection Enable with Fault 4 for channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FPE2[3] ,Fault Protection Enable with Fault 3 for channel 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " FPE2[2] ,Fault Protection Enable with Fault 2 for channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FPE2[1] ,Fault Protection Enable with Fault 1 for channel 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " FPE2[0] ,Fault Protection Enable with Fault 0 for channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FPE1[7] ,Fault Protection Enable with Fault 7 for channel 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " FPE1[6] ,Fault Protection Enable with Fault 6 for channel 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FPE1[5] ,Fault Protection Enable with Fault 5 for channel 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " FPE1[4] ,Fault Protection Enable with Fault 4 for channel 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FPE1[3] ,Fault Protection Enable with Fault 3 for channel 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " FPE1[2] ,Fault Protection Enable with Fault 2 for channel 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FPE1[1] ,Fault Protection Enable with Fault 1 for channel 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FPE1[0] ,Fault Protection Enable with Fault 0 for channel 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FPE0[7] ,Fault Protection Enable with Fault 7 for channel 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FPE0[6] ,Fault Protection Enable with Fault 6 for channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FPE0[5] ,Fault Protection Enable with Fault 5 for channel 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FPE0[4] ,Fault Protection Enable with Fault 4 for channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FPE0[3] ,Fault Protection Enable with Fault 3 for channel 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FPE0[2] ,Fault Protection Enable with Fault 2 for channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FPE0[1] ,Fault Protection Enable with Fault 1 for channel 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FPE0[0] ,Fault Protection Enable with Fault 0 for channel 4" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x7c++0x7
|
|
line.long 0x0 "PWM_ELMR0,PWM Event Line 0 Register"
|
|
bitfld.long 0x0 7. " CSEL7 , Comparison 7 Selection" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " CSEL6 , Comparison 6 Selection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " CSEL5 , Comparison 5 Selection" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " CSEL4 , Comparison 4 Selection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " CSEL3 , Comparison 3 Selection" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " CSEL2 , Comparison 2 Selection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CSEL1 , Comparison 1 Selection" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " CSEL0 , Comparison 0 Selection" "Disabled,Enabled"
|
|
line.long 0x4 "PWM_ELMR1,PWM Event Line 1 Register"
|
|
bitfld.long 0x4 7. " CSEL7 , Comparison 7 Selection" "Disabled,Enabled"
|
|
bitfld.long 0x4 6. " CSEL6 , Comparison 6 Selection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 5. " CSEL5 , Comparison 5 Selection" "Disabled,Enabled"
|
|
bitfld.long 0x4 4. " CSEL4 , Comparison 4 Selection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 3. " CSEL3 , Comparison 3 Selection" "Disabled,Enabled"
|
|
bitfld.long 0x4 2. " CSEL2 , Comparison 2 Selection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 1. " CSEL1 , Comparison 1 Selection" "Disabled,Enabled"
|
|
bitfld.long 0x4 0. " CSEL0 , Comparison 0 Selection" "Disabled,Enabled"
|
|
sif (cpuis("ATSAM4S*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long 0xB0++0x3
|
|
line.long 0x00 "PWM_SMMR,PWM Stepper Motor Mode Register"
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 19. " DOWN3 ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 18. " DOWN2 ,Down Count" "Up,Down"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " DOWN1 ,DOWN Count" "Up,Down"
|
|
bitfld.long 0x00 16. " DOWN0 ,Down Count" "Up,Down"
|
|
textline " "
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 3. " GCEN3 ,Gray Count ENable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " GCEN2 ,Gray Count ENable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " GCEN1 ,Gray Count ENable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " GCEN0 ,Gray Count ENable" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0xe4++0x3
|
|
line.long 0x00 "PWM_WPCR,PWM Write Protect Control Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect Key"
|
|
bitfld.long 0x00 7. " WPRG5 ,Write Protect Register Group 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " WPRG4 ,Write Protect Register Group 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " WPRG3 ,Write Protect Register Group 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WPRG2 ,Write Protect Register Group 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " WPRG1 ,Write Protect Register Group 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WPRG0 ,Write Protect Register Group 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " WPCMD ,Write Protect Command" "Disable the Write Protect SW,Enable the Write Protect SW,Enable the Write Protect HW,No effect"
|
|
hgroup.long 0xe8++0x3
|
|
hide.long 0x00 "PWM_WPSR,PWM Write Protect Status Register"
|
|
in
|
|
tree.end
|
|
width 14.
|
|
tree "Comparison Registers"
|
|
group.long (0x130+0x0)++0x03 "Comparison 0"
|
|
line.long 0x00 "PWM_CMP0V,PWM Comparison 0 Value Register"
|
|
bitfld.long 0x00 24. " CVM ,Comparison 0 Value Mode" "Incrementing,Decrementing"
|
|
sif (cpuis("AT91SAM3A*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*"))
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CV ,Comparison 0 Value"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 0 Value"
|
|
endif
|
|
wgroup.long (0x134+0x0)++0x3
|
|
line.long 0x00 "PWM_CMP0VUPD,Comparison 0 Value Update"
|
|
bitfld.long 0x00 24. " CVMUPD ,Comparison 0 Value Mode Update" "Incrementing,Decrementing"
|
|
sif (cpuis("AT91SAM3A*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*"))
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CVUPD ,Comparison 0 Value Update"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 0 Value Update"
|
|
endif
|
|
group.long (0x138+0x0)++0x3
|
|
line.long 0x00 "PWM_CMP0M,PWM Comparison 0 Mode Register"
|
|
bitfld.long 0x00 20.--23. " CUPRCNT ,Comparison 0 Update Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CUPR ,Comparison 0 Update Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("ATSAM4S*"))
|
|
rbitfld.long 0x00 12.--15. " CPRCNT ,Comparison 0 Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x00 12.--15. " CPRCNT ,Comparison 0 Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
bitfld.long 0x00 8.--11. " CPR ,Comparison 0 Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CTR ,Comparison 0 Trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CEN ,Comparison 0 Enable" "Disabled,Enabled"
|
|
wgroup.long (0x13c+0x0)++0x3
|
|
line.long 0x00 "PWM_CMP0MUPD,PWM Comparison 0 Mode Update Register"
|
|
bitfld.long 0x00 16.--19. " CUPRUPD ,Comparison 0 Update Period Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPRUPD ,Comparison 0 Period Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CTRUPD ,Comparison 0 Trigger Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CENUPD ,Comparison 0 Enable Update" "Disabled,Enabled"
|
|
group.long (0x130+0x10)++0x03 "Comparison 1"
|
|
line.long 0x00 "PWM_CMP1V,PWM Comparison 1 Value Register"
|
|
bitfld.long 0x00 24. " CVM ,Comparison 1 Value Mode" "Incrementing,Decrementing"
|
|
sif (cpuis("AT91SAM3A*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*"))
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CV ,Comparison 1 Value"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 1 Value"
|
|
endif
|
|
wgroup.long (0x134+0x10)++0x3
|
|
line.long 0x00 "PWM_CMP1VUPD,Comparison 1 Value Update"
|
|
bitfld.long 0x00 24. " CVMUPD ,Comparison 1 Value Mode Update" "Incrementing,Decrementing"
|
|
sif (cpuis("AT91SAM3A*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*"))
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CVUPD ,Comparison 1 Value Update"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 1 Value Update"
|
|
endif
|
|
group.long (0x138+0x10)++0x3
|
|
line.long 0x00 "PWM_CMP1M,PWM Comparison 1 Mode Register"
|
|
bitfld.long 0x00 20.--23. " CUPRCNT ,Comparison 1 Update Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CUPR ,Comparison 1 Update Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("ATSAM4S*"))
|
|
rbitfld.long 0x00 12.--15. " CPRCNT ,Comparison 1 Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x00 12.--15. " CPRCNT ,Comparison 1 Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
bitfld.long 0x00 8.--11. " CPR ,Comparison 1 Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CTR ,Comparison 1 Trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CEN ,Comparison 1 Enable" "Disabled,Enabled"
|
|
wgroup.long (0x13c+0x10)++0x3
|
|
line.long 0x00 "PWM_CMP1MUPD,PWM Comparison 1 Mode Update Register"
|
|
bitfld.long 0x00 16.--19. " CUPRUPD ,Comparison 1 Update Period Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPRUPD ,Comparison 1 Period Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CTRUPD ,Comparison 1 Trigger Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CENUPD ,Comparison 1 Enable Update" "Disabled,Enabled"
|
|
group.long (0x130+0x20)++0x03 "Comparison 2"
|
|
line.long 0x00 "PWM_CMP2V,PWM Comparison 2 Value Register"
|
|
bitfld.long 0x00 24. " CVM ,Comparison 2 Value Mode" "Incrementing,Decrementing"
|
|
sif (cpuis("AT91SAM3A*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*"))
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CV ,Comparison 2 Value"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 2 Value"
|
|
endif
|
|
wgroup.long (0x134+0x20)++0x3
|
|
line.long 0x00 "PWM_CMP2VUPD,Comparison 2 Value Update"
|
|
bitfld.long 0x00 24. " CVMUPD ,Comparison 2 Value Mode Update" "Incrementing,Decrementing"
|
|
sif (cpuis("AT91SAM3A*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*"))
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CVUPD ,Comparison 2 Value Update"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 2 Value Update"
|
|
endif
|
|
group.long (0x138+0x20)++0x3
|
|
line.long 0x00 "PWM_CMP2M,PWM Comparison 2 Mode Register"
|
|
bitfld.long 0x00 20.--23. " CUPRCNT ,Comparison 2 Update Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CUPR ,Comparison 2 Update Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("ATSAM4S*"))
|
|
rbitfld.long 0x00 12.--15. " CPRCNT ,Comparison 2 Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x00 12.--15. " CPRCNT ,Comparison 2 Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
bitfld.long 0x00 8.--11. " CPR ,Comparison 2 Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CTR ,Comparison 2 Trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CEN ,Comparison 2 Enable" "Disabled,Enabled"
|
|
wgroup.long (0x13c+0x20)++0x3
|
|
line.long 0x00 "PWM_CMP2MUPD,PWM Comparison 2 Mode Update Register"
|
|
bitfld.long 0x00 16.--19. " CUPRUPD ,Comparison 2 Update Period Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPRUPD ,Comparison 2 Period Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CTRUPD ,Comparison 2 Trigger Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CENUPD ,Comparison 2 Enable Update" "Disabled,Enabled"
|
|
group.long (0x130+0x30)++0x03 "Comparison 3"
|
|
line.long 0x00 "PWM_CMP3V,PWM Comparison 3 Value Register"
|
|
bitfld.long 0x00 24. " CVM ,Comparison 3 Value Mode" "Incrementing,Decrementing"
|
|
sif (cpuis("AT91SAM3A*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*"))
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CV ,Comparison 3 Value"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 3 Value"
|
|
endif
|
|
wgroup.long (0x134+0x30)++0x3
|
|
line.long 0x00 "PWM_CMP3VUPD,Comparison 3 Value Update"
|
|
bitfld.long 0x00 24. " CVMUPD ,Comparison 3 Value Mode Update" "Incrementing,Decrementing"
|
|
sif (cpuis("AT91SAM3A*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*"))
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CVUPD ,Comparison 3 Value Update"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 3 Value Update"
|
|
endif
|
|
group.long (0x138+0x30)++0x3
|
|
line.long 0x00 "PWM_CMP3M,PWM Comparison 3 Mode Register"
|
|
bitfld.long 0x00 20.--23. " CUPRCNT ,Comparison 3 Update Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CUPR ,Comparison 3 Update Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("ATSAM4S*"))
|
|
rbitfld.long 0x00 12.--15. " CPRCNT ,Comparison 3 Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x00 12.--15. " CPRCNT ,Comparison 3 Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
bitfld.long 0x00 8.--11. " CPR ,Comparison 3 Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CTR ,Comparison 3 Trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CEN ,Comparison 3 Enable" "Disabled,Enabled"
|
|
wgroup.long (0x13c+0x30)++0x3
|
|
line.long 0x00 "PWM_CMP3MUPD,PWM Comparison 3 Mode Update Register"
|
|
bitfld.long 0x00 16.--19. " CUPRUPD ,Comparison 3 Update Period Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPRUPD ,Comparison 3 Period Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CTRUPD ,Comparison 3 Trigger Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CENUPD ,Comparison 3 Enable Update" "Disabled,Enabled"
|
|
group.long (0x130+0x40)++0x03 "Comparison 4"
|
|
line.long 0x00 "PWM_CMP4V,PWM Comparison 4 Value Register"
|
|
bitfld.long 0x00 24. " CVM ,Comparison 4 Value Mode" "Incrementing,Decrementing"
|
|
sif (cpuis("AT91SAM3A*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*"))
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CV ,Comparison 4 Value"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 4 Value"
|
|
endif
|
|
wgroup.long (0x134+0x40)++0x3
|
|
line.long 0x00 "PWM_CMP4VUPD,Comparison 4 Value Update"
|
|
bitfld.long 0x00 24. " CVMUPD ,Comparison 4 Value Mode Update" "Incrementing,Decrementing"
|
|
sif (cpuis("AT91SAM3A*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*"))
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CVUPD ,Comparison 4 Value Update"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 4 Value Update"
|
|
endif
|
|
group.long (0x138+0x40)++0x3
|
|
line.long 0x00 "PWM_CMP4M,PWM Comparison 4 Mode Register"
|
|
bitfld.long 0x00 20.--23. " CUPRCNT ,Comparison 4 Update Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CUPR ,Comparison 4 Update Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("ATSAM4S*"))
|
|
rbitfld.long 0x00 12.--15. " CPRCNT ,Comparison 4 Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x00 12.--15. " CPRCNT ,Comparison 4 Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
bitfld.long 0x00 8.--11. " CPR ,Comparison 4 Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CTR ,Comparison 4 Trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CEN ,Comparison 4 Enable" "Disabled,Enabled"
|
|
wgroup.long (0x13c+0x40)++0x3
|
|
line.long 0x00 "PWM_CMP4MUPD,PWM Comparison 4 Mode Update Register"
|
|
bitfld.long 0x00 16.--19. " CUPRUPD ,Comparison 4 Update Period Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPRUPD ,Comparison 4 Period Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CTRUPD ,Comparison 4 Trigger Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CENUPD ,Comparison 4 Enable Update" "Disabled,Enabled"
|
|
group.long (0x130+0x50)++0x03 "Comparison 5"
|
|
line.long 0x00 "PWM_CMP5V,PWM Comparison 5 Value Register"
|
|
bitfld.long 0x00 24. " CVM ,Comparison 5 Value Mode" "Incrementing,Decrementing"
|
|
sif (cpuis("AT91SAM3A*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*"))
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CV ,Comparison 5 Value"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 5 Value"
|
|
endif
|
|
wgroup.long (0x134+0x50)++0x3
|
|
line.long 0x00 "PWM_CMP5VUPD,Comparison 5 Value Update"
|
|
bitfld.long 0x00 24. " CVMUPD ,Comparison 5 Value Mode Update" "Incrementing,Decrementing"
|
|
sif (cpuis("AT91SAM3A*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*"))
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CVUPD ,Comparison 5 Value Update"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 5 Value Update"
|
|
endif
|
|
group.long (0x138+0x50)++0x3
|
|
line.long 0x00 "PWM_CMP5M,PWM Comparison 5 Mode Register"
|
|
bitfld.long 0x00 20.--23. " CUPRCNT ,Comparison 5 Update Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CUPR ,Comparison 5 Update Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("ATSAM4S*"))
|
|
rbitfld.long 0x00 12.--15. " CPRCNT ,Comparison 5 Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x00 12.--15. " CPRCNT ,Comparison 5 Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
bitfld.long 0x00 8.--11. " CPR ,Comparison 5 Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CTR ,Comparison 5 Trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CEN ,Comparison 5 Enable" "Disabled,Enabled"
|
|
wgroup.long (0x13c+0x50)++0x3
|
|
line.long 0x00 "PWM_CMP5MUPD,PWM Comparison 5 Mode Update Register"
|
|
bitfld.long 0x00 16.--19. " CUPRUPD ,Comparison 5 Update Period Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPRUPD ,Comparison 5 Period Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CTRUPD ,Comparison 5 Trigger Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CENUPD ,Comparison 5 Enable Update" "Disabled,Enabled"
|
|
group.long (0x130+0x60)++0x03 "Comparison 6"
|
|
line.long 0x00 "PWM_CMP6V,PWM Comparison 6 Value Register"
|
|
bitfld.long 0x00 24. " CVM ,Comparison 6 Value Mode" "Incrementing,Decrementing"
|
|
sif (cpuis("AT91SAM3A*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*"))
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CV ,Comparison 6 Value"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 6 Value"
|
|
endif
|
|
wgroup.long (0x134+0x60)++0x3
|
|
line.long 0x00 "PWM_CMP6VUPD,Comparison 6 Value Update"
|
|
bitfld.long 0x00 24. " CVMUPD ,Comparison 6 Value Mode Update" "Incrementing,Decrementing"
|
|
sif (cpuis("AT91SAM3A*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*"))
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CVUPD ,Comparison 6 Value Update"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 6 Value Update"
|
|
endif
|
|
group.long (0x138+0x60)++0x3
|
|
line.long 0x00 "PWM_CMP6M,PWM Comparison 6 Mode Register"
|
|
bitfld.long 0x00 20.--23. " CUPRCNT ,Comparison 6 Update Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CUPR ,Comparison 6 Update Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("ATSAM4S*"))
|
|
rbitfld.long 0x00 12.--15. " CPRCNT ,Comparison 6 Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x00 12.--15. " CPRCNT ,Comparison 6 Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
bitfld.long 0x00 8.--11. " CPR ,Comparison 6 Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CTR ,Comparison 6 Trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CEN ,Comparison 6 Enable" "Disabled,Enabled"
|
|
wgroup.long (0x13c+0x60)++0x3
|
|
line.long 0x00 "PWM_CMP6MUPD,PWM Comparison 6 Mode Update Register"
|
|
bitfld.long 0x00 16.--19. " CUPRUPD ,Comparison 6 Update Period Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPRUPD ,Comparison 6 Period Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CTRUPD ,Comparison 6 Trigger Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CENUPD ,Comparison 6 Enable Update" "Disabled,Enabled"
|
|
group.long (0x130+0x70)++0x03 "Comparison 7"
|
|
line.long 0x00 "PWM_CMP7V,PWM Comparison 7 Value Register"
|
|
bitfld.long 0x00 24. " CVM ,Comparison 7 Value Mode" "Incrementing,Decrementing"
|
|
sif (cpuis("AT91SAM3A*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*"))
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CV ,Comparison 7 Value"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 7 Value"
|
|
endif
|
|
wgroup.long (0x134+0x70)++0x3
|
|
line.long 0x00 "PWM_CMP7VUPD,Comparison 7 Value Update"
|
|
bitfld.long 0x00 24. " CVMUPD ,Comparison 7 Value Mode Update" "Incrementing,Decrementing"
|
|
sif (cpuis("AT91SAM3A*")||cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*"))
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CVUPD ,Comparison 7 Value Update"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 7 Value Update"
|
|
endif
|
|
group.long (0x138+0x70)++0x3
|
|
line.long 0x00 "PWM_CMP7M,PWM Comparison 7 Mode Register"
|
|
bitfld.long 0x00 20.--23. " CUPRCNT ,Comparison 7 Update Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CUPR ,Comparison 7 Update Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("ATSAM4S*"))
|
|
rbitfld.long 0x00 12.--15. " CPRCNT ,Comparison 7 Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x00 12.--15. " CPRCNT ,Comparison 7 Period Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
bitfld.long 0x00 8.--11. " CPR ,Comparison 7 Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CTR ,Comparison 7 Trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CEN ,Comparison 7 Enable" "Disabled,Enabled"
|
|
wgroup.long (0x13c+0x70)++0x3
|
|
line.long 0x00 "PWM_CMP7MUPD,PWM Comparison 7 Mode Update Register"
|
|
bitfld.long 0x00 16.--19. " CUPRUPD ,Comparison 7 Update Period Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPRUPD ,Comparison 7 Period Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CTRUPD ,Comparison 7 Trigger Update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CENUPD ,Comparison 7 Enable Update" "Disabled,Enabled"
|
|
tree.end
|
|
width 0x11
|
|
sif (cpuis("ATSAMA5D31")||cpuis("ATSAMA5D33")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")||cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*"))
|
|
tree "Channel 0"
|
|
if ((d.l(ad:0x40094000+0x200+0x0)&0x100)==0x100)
|
|
group.long (0x200+0x0)++0x3
|
|
line.long 0x00 "PWM_CMR0,Channel 0 Mode Register"
|
|
bitfld.long 0x00 18. " DTLI ,Dead-Time PWML0 Output Inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " DTHI ,Dead-Time PWMH0 Output Inverted" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DTE ,Dead-Time Generator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CES ,Counter Event Selection" "At the end of period,At the end and half the period"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low level,High level"
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
else
|
|
group.long (0x200+0x0)++0x3
|
|
line.long 0x00 "PWM_CMR0,Channel 0 Mode Register"
|
|
bitfld.long 0x00 18. " DTLI ,Dead-Time PWML0 Output Inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " DTHI ,Dead-Time PWMH0 Output Inverted" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DTE ,Dead-Time Generator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CES ,Counter Event Selection" "At the end of period,At the end of period"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low level,High level"
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
endif
|
|
group.long (0x204+0x0)++0x3
|
|
line.long 0x00 "PWM_CDTY0,PWM Channel 0 Duty Cycle Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CDTY ,Channel Duty-Cycle"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CDTY ,Channel Duty-Cycle"
|
|
endif
|
|
wgroup.long (0x208+0x0)++0x3
|
|
line.long 0x00 "PWM_CDTYUPD0,PWM Channel 0 Duty Cycle Update Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CDTYUPD ,Channel Duty-Cycle Update"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CDTYUPD ,Channel Duty-Cycle Update"
|
|
endif
|
|
group.long (0x20c+0x0)++0x03
|
|
line.long 0x00 "PWM_CPRD0,PWM Channel 0 Period Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*"))
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CPRD ,Channel Period"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CPRD ,Channel Period"
|
|
endif
|
|
wgroup.long (0x210+0x0)++0x03
|
|
line.long 0x00 "PWM_CPRDUPD0,Channel 0 Update Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.tbyte 0x0 0.--23. 1. " CPRDUPD ,Channel Period Update"
|
|
else
|
|
hexmask.long.word 0x0 0.--15. 1. " CPRDUPD ,Channel Period Update"
|
|
endif
|
|
rgroup.long (0x214+0x0)++0x03
|
|
line.long 0x00 "PWM_CCNT0,PWM Channel 0 Counter Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.tbyte 0x0 0.--23. 1. " CNT ,Channel Counter Register"
|
|
else
|
|
hexmask.long.word 0x0 0.--15. 1. " CNT ,Channel Counter Register"
|
|
endif
|
|
group.long (0x218+0x0)++0x03
|
|
line.long 0x00 "PWM_DT0,PWM Channel Dead Time Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.word 0x00 16.--31. 1. " DTL ,Dead-Time Value for PWML0 Output"
|
|
hexmask.long.word 0x00 0.--15. 1. " DTH ,Dead-Time Value for PWMH0 Output"
|
|
else
|
|
hexmask.long.word 0x00 16.--27. 1. " DTL ,Dead-Time Value for PWML0 Output"
|
|
hexmask.long.word 0x00 0.--11. 1. " DTH ,Dead-Time Value for PWMH0 Output"
|
|
endif
|
|
wgroup.long (0x21c+0x0)++0x03
|
|
line.long 0x00 "PWM_DTUPD0,PWM Channel Dead Time Update Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.word 0x00 16.--31. 1. " DTLUPD ,Dead-Time Value Update for PWML0 Output"
|
|
hexmask.long.word 0x00 0.--15. 1. " DTHUPD ,Dead-Time Value Update for PWMH0 Output"
|
|
else
|
|
hexmask.long.word 0x00 16.--27. 1. " DTLUPD ,Dead-Time Value Update for PWML0 Output"
|
|
hexmask.long.word 0x00 0.--11. 1. " DTHUPD ,Dead-Time Value Update for PWMH0 Output"
|
|
endif
|
|
tree.end
|
|
tree "Channel 1"
|
|
if ((d.l(ad:0x40094000+0x200+0x20)&0x100)==0x100)
|
|
group.long (0x200+0x20)++0x3
|
|
line.long 0x00 "PWM_CMR1,Channel 1 Mode Register"
|
|
bitfld.long 0x00 18. " DTLI ,Dead-Time PWML1 Output Inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " DTHI ,Dead-Time PWMH1 Output Inverted" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DTE ,Dead-Time Generator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CES ,Counter Event Selection" "At the end of period,At the end and half the period"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low level,High level"
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
else
|
|
group.long (0x200+0x20)++0x3
|
|
line.long 0x00 "PWM_CMR1,Channel 1 Mode Register"
|
|
bitfld.long 0x00 18. " DTLI ,Dead-Time PWML1 Output Inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " DTHI ,Dead-Time PWMH1 Output Inverted" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DTE ,Dead-Time Generator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CES ,Counter Event Selection" "At the end of period,At the end of period"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low level,High level"
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
endif
|
|
group.long (0x204+0x20)++0x3
|
|
line.long 0x00 "PWM_CDTY1,PWM Channel 1 Duty Cycle Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CDTY ,Channel Duty-Cycle"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CDTY ,Channel Duty-Cycle"
|
|
endif
|
|
wgroup.long (0x208+0x20)++0x3
|
|
line.long 0x00 "PWM_CDTYUPD1,PWM Channel 1 Duty Cycle Update Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CDTYUPD ,Channel Duty-Cycle Update"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CDTYUPD ,Channel Duty-Cycle Update"
|
|
endif
|
|
group.long (0x20c+0x20)++0x03
|
|
line.long 0x00 "PWM_CPRD1,PWM Channel 1 Period Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*"))
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CPRD ,Channel Period"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CPRD ,Channel Period"
|
|
endif
|
|
wgroup.long (0x210+0x20)++0x03
|
|
line.long 0x00 "PWM_CPRDUPD1,Channel 1 Update Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.tbyte 0x0 0.--23. 1. " CPRDUPD ,Channel Period Update"
|
|
else
|
|
hexmask.long.word 0x0 0.--15. 1. " CPRDUPD ,Channel Period Update"
|
|
endif
|
|
rgroup.long (0x214+0x20)++0x03
|
|
line.long 0x00 "PWM_CCNT1,PWM Channel 1 Counter Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.tbyte 0x0 0.--23. 1. " CNT ,Channel Counter Register"
|
|
else
|
|
hexmask.long.word 0x0 0.--15. 1. " CNT ,Channel Counter Register"
|
|
endif
|
|
group.long (0x218+0x20)++0x03
|
|
line.long 0x00 "PWM_DT1,PWM Channel Dead Time Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.word 0x00 16.--31. 1. " DTL ,Dead-Time Value for PWML1 Output"
|
|
hexmask.long.word 0x00 0.--15. 1. " DTH ,Dead-Time Value for PWMH1 Output"
|
|
else
|
|
hexmask.long.word 0x00 16.--27. 1. " DTL ,Dead-Time Value for PWML1 Output"
|
|
hexmask.long.word 0x00 0.--11. 1. " DTH ,Dead-Time Value for PWMH1 Output"
|
|
endif
|
|
wgroup.long (0x21c+0x20)++0x03
|
|
line.long 0x00 "PWM_DTUPD1,PWM Channel Dead Time Update Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.word 0x00 16.--31. 1. " DTLUPD ,Dead-Time Value Update for PWML1 Output"
|
|
hexmask.long.word 0x00 0.--15. 1. " DTHUPD ,Dead-Time Value Update for PWMH1 Output"
|
|
else
|
|
hexmask.long.word 0x00 16.--27. 1. " DTLUPD ,Dead-Time Value Update for PWML1 Output"
|
|
hexmask.long.word 0x00 0.--11. 1. " DTHUPD ,Dead-Time Value Update for PWMH1 Output"
|
|
endif
|
|
tree.end
|
|
tree "Channel 2"
|
|
if ((d.l(ad:0x40094000+0x200+0x40)&0x100)==0x100)
|
|
group.long (0x200+0x40)++0x3
|
|
line.long 0x00 "PWM_CMR2,Channel 2 Mode Register"
|
|
bitfld.long 0x00 18. " DTLI ,Dead-Time PWML2 Output Inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " DTHI ,Dead-Time PWMH2 Output Inverted" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DTE ,Dead-Time Generator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CES ,Counter Event Selection" "At the end of period,At the end and half the period"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low level,High level"
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
else
|
|
group.long (0x200+0x40)++0x3
|
|
line.long 0x00 "PWM_CMR2,Channel 2 Mode Register"
|
|
bitfld.long 0x00 18. " DTLI ,Dead-Time PWML2 Output Inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " DTHI ,Dead-Time PWMH2 Output Inverted" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DTE ,Dead-Time Generator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CES ,Counter Event Selection" "At the end of period,At the end of period"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low level,High level"
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
endif
|
|
group.long (0x204+0x40)++0x3
|
|
line.long 0x00 "PWM_CDTY2,PWM Channel 2 Duty Cycle Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CDTY ,Channel Duty-Cycle"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CDTY ,Channel Duty-Cycle"
|
|
endif
|
|
wgroup.long (0x208+0x40)++0x3
|
|
line.long 0x00 "PWM_CDTYUPD2,PWM Channel 2 Duty Cycle Update Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CDTYUPD ,Channel Duty-Cycle Update"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CDTYUPD ,Channel Duty-Cycle Update"
|
|
endif
|
|
group.long (0x20c+0x40)++0x03
|
|
line.long 0x00 "PWM_CPRD2,PWM Channel 2 Period Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*"))
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CPRD ,Channel Period"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CPRD ,Channel Period"
|
|
endif
|
|
wgroup.long (0x210+0x40)++0x03
|
|
line.long 0x00 "PWM_CPRDUPD2,Channel 2 Update Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.tbyte 0x0 0.--23. 1. " CPRDUPD ,Channel Period Update"
|
|
else
|
|
hexmask.long.word 0x0 0.--15. 1. " CPRDUPD ,Channel Period Update"
|
|
endif
|
|
rgroup.long (0x214+0x40)++0x03
|
|
line.long 0x00 "PWM_CCNT2,PWM Channel 2 Counter Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.tbyte 0x0 0.--23. 1. " CNT ,Channel Counter Register"
|
|
else
|
|
hexmask.long.word 0x0 0.--15. 1. " CNT ,Channel Counter Register"
|
|
endif
|
|
group.long (0x218+0x40)++0x03
|
|
line.long 0x00 "PWM_DT2,PWM Channel Dead Time Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.word 0x00 16.--31. 1. " DTL ,Dead-Time Value for PWML2 Output"
|
|
hexmask.long.word 0x00 0.--15. 1. " DTH ,Dead-Time Value for PWMH2 Output"
|
|
else
|
|
hexmask.long.word 0x00 16.--27. 1. " DTL ,Dead-Time Value for PWML2 Output"
|
|
hexmask.long.word 0x00 0.--11. 1. " DTH ,Dead-Time Value for PWMH2 Output"
|
|
endif
|
|
wgroup.long (0x21c+0x40)++0x03
|
|
line.long 0x00 "PWM_DTUPD2,PWM Channel Dead Time Update Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.word 0x00 16.--31. 1. " DTLUPD ,Dead-Time Value Update for PWML2 Output"
|
|
hexmask.long.word 0x00 0.--15. 1. " DTHUPD ,Dead-Time Value Update for PWMH2 Output"
|
|
else
|
|
hexmask.long.word 0x00 16.--27. 1. " DTLUPD ,Dead-Time Value Update for PWML2 Output"
|
|
hexmask.long.word 0x00 0.--11. 1. " DTHUPD ,Dead-Time Value Update for PWMH2 Output"
|
|
endif
|
|
tree.end
|
|
tree "Channel 3"
|
|
if ((d.l(ad:0x40094000+0x200+0x60)&0x100)==0x100)
|
|
group.long (0x200+0x60)++0x3
|
|
line.long 0x00 "PWM_CMR3,Channel 3 Mode Register"
|
|
bitfld.long 0x00 18. " DTLI ,Dead-Time PWML3 Output Inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " DTHI ,Dead-Time PWMH3 Output Inverted" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DTE ,Dead-Time Generator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CES ,Counter Event Selection" "At the end of period,At the end and half the period"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low level,High level"
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
else
|
|
group.long (0x200+0x60)++0x3
|
|
line.long 0x00 "PWM_CMR3,Channel 3 Mode Register"
|
|
bitfld.long 0x00 18. " DTLI ,Dead-Time PWML3 Output Inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " DTHI ,Dead-Time PWMH3 Output Inverted" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DTE ,Dead-Time Generator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CES ,Counter Event Selection" "At the end of period,At the end of period"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low level,High level"
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
endif
|
|
group.long (0x204+0x60)++0x3
|
|
line.long 0x00 "PWM_CDTY3,PWM Channel 3 Duty Cycle Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CDTY ,Channel Duty-Cycle"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CDTY ,Channel Duty-Cycle"
|
|
endif
|
|
wgroup.long (0x208+0x60)++0x3
|
|
line.long 0x00 "PWM_CDTYUPD3,PWM Channel 3 Duty Cycle Update Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CDTYUPD ,Channel Duty-Cycle Update"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CDTYUPD ,Channel Duty-Cycle Update"
|
|
endif
|
|
group.long (0x20c+0x60)++0x03
|
|
line.long 0x00 "PWM_CPRD3,PWM Channel 3 Period Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*"))
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CPRD ,Channel Period"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CPRD ,Channel Period"
|
|
endif
|
|
wgroup.long (0x210+0x60)++0x03
|
|
line.long 0x00 "PWM_CPRDUPD3,Channel 3 Update Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.tbyte 0x0 0.--23. 1. " CPRDUPD ,Channel Period Update"
|
|
else
|
|
hexmask.long.word 0x0 0.--15. 1. " CPRDUPD ,Channel Period Update"
|
|
endif
|
|
rgroup.long (0x214+0x60)++0x03
|
|
line.long 0x00 "PWM_CCNT3,PWM Channel 3 Counter Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.tbyte 0x0 0.--23. 1. " CNT ,Channel Counter Register"
|
|
else
|
|
hexmask.long.word 0x0 0.--15. 1. " CNT ,Channel Counter Register"
|
|
endif
|
|
group.long (0x218+0x60)++0x03
|
|
line.long 0x00 "PWM_DT3,PWM Channel Dead Time Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.word 0x00 16.--31. 1. " DTL ,Dead-Time Value for PWML3 Output"
|
|
hexmask.long.word 0x00 0.--15. 1. " DTH ,Dead-Time Value for PWMH3 Output"
|
|
else
|
|
hexmask.long.word 0x00 16.--27. 1. " DTL ,Dead-Time Value for PWML3 Output"
|
|
hexmask.long.word 0x00 0.--11. 1. " DTH ,Dead-Time Value for PWMH3 Output"
|
|
endif
|
|
wgroup.long (0x21c+0x60)++0x03
|
|
line.long 0x00 "PWM_DTUPD3,PWM Channel Dead Time Update Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.word 0x00 16.--31. 1. " DTLUPD ,Dead-Time Value Update for PWML3 Output"
|
|
hexmask.long.word 0x00 0.--15. 1. " DTHUPD ,Dead-Time Value Update for PWMH3 Output"
|
|
else
|
|
hexmask.long.word 0x00 16.--27. 1. " DTLUPD ,Dead-Time Value Update for PWML3 Output"
|
|
hexmask.long.word 0x00 0.--11. 1. " DTHUPD ,Dead-Time Value Update for PWMH3 Output"
|
|
endif
|
|
tree.end
|
|
tree "Channel 4"
|
|
if ((d.l(ad:0x40094000+0x200+0x80)&0x100)==0x100)
|
|
group.long (0x200+0x80)++0x3
|
|
line.long 0x00 "PWM_CMR4,Channel 4 Mode Register"
|
|
bitfld.long 0x00 18. " DTLI ,Dead-Time PWML4 Output Inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " DTHI ,Dead-Time PWMH4 Output Inverted" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DTE ,Dead-Time Generator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CES ,Counter Event Selection" "At the end of period,At the end and half the period"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low level,High level"
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
else
|
|
group.long (0x200+0x80)++0x3
|
|
line.long 0x00 "PWM_CMR4,Channel 4 Mode Register"
|
|
bitfld.long 0x00 18. " DTLI ,Dead-Time PWML4 Output Inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " DTHI ,Dead-Time PWMH4 Output Inverted" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DTE ,Dead-Time Generator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CES ,Counter Event Selection" "At the end of period,At the end of period"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low level,High level"
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
endif
|
|
group.long (0x204+0x80)++0x3
|
|
line.long 0x00 "PWM_CDTY4,PWM Channel 4 Duty Cycle Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CDTY ,Channel Duty-Cycle"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CDTY ,Channel Duty-Cycle"
|
|
endif
|
|
wgroup.long (0x208+0x80)++0x3
|
|
line.long 0x00 "PWM_CDTYUPD4,PWM Channel 4 Duty Cycle Update Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CDTYUPD ,Channel Duty-Cycle Update"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CDTYUPD ,Channel Duty-Cycle Update"
|
|
endif
|
|
group.long (0x20c+0x80)++0x03
|
|
line.long 0x00 "PWM_CPRD4,PWM Channel 4 Period Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*"))
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CPRD ,Channel Period"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CPRD ,Channel Period"
|
|
endif
|
|
wgroup.long (0x210+0x80)++0x03
|
|
line.long 0x00 "PWM_CPRDUPD4,Channel 4 Update Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.tbyte 0x0 0.--23. 1. " CPRDUPD ,Channel Period Update"
|
|
else
|
|
hexmask.long.word 0x0 0.--15. 1. " CPRDUPD ,Channel Period Update"
|
|
endif
|
|
rgroup.long (0x214+0x80)++0x03
|
|
line.long 0x00 "PWM_CCNT4,PWM Channel 4 Counter Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.tbyte 0x0 0.--23. 1. " CNT ,Channel Counter Register"
|
|
else
|
|
hexmask.long.word 0x0 0.--15. 1. " CNT ,Channel Counter Register"
|
|
endif
|
|
group.long (0x218+0x80)++0x03
|
|
line.long 0x00 "PWM_DT4,PWM Channel Dead Time Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.word 0x00 16.--31. 1. " DTL ,Dead-Time Value for PWML4 Output"
|
|
hexmask.long.word 0x00 0.--15. 1. " DTH ,Dead-Time Value for PWMH4 Output"
|
|
else
|
|
hexmask.long.word 0x00 16.--27. 1. " DTL ,Dead-Time Value for PWML4 Output"
|
|
hexmask.long.word 0x00 0.--11. 1. " DTH ,Dead-Time Value for PWMH4 Output"
|
|
endif
|
|
wgroup.long (0x21c+0x80)++0x03
|
|
line.long 0x00 "PWM_DTUPD4,PWM Channel Dead Time Update Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.word 0x00 16.--31. 1. " DTLUPD ,Dead-Time Value Update for PWML4 Output"
|
|
hexmask.long.word 0x00 0.--15. 1. " DTHUPD ,Dead-Time Value Update for PWMH4 Output"
|
|
else
|
|
hexmask.long.word 0x00 16.--27. 1. " DTLUPD ,Dead-Time Value Update for PWML4 Output"
|
|
hexmask.long.word 0x00 0.--11. 1. " DTHUPD ,Dead-Time Value Update for PWMH4 Output"
|
|
endif
|
|
tree.end
|
|
tree "Channel 5"
|
|
if ((d.l(ad:0x40094000+0x200+0xA0)&0x100)==0x100)
|
|
group.long (0x200+0xA0)++0x3
|
|
line.long 0x00 "PWM_CMR5,Channel 5 Mode Register"
|
|
bitfld.long 0x00 18. " DTLI ,Dead-Time PWML5 Output Inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " DTHI ,Dead-Time PWMH5 Output Inverted" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DTE ,Dead-Time Generator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CES ,Counter Event Selection" "At the end of period,At the end and half the period"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low level,High level"
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
else
|
|
group.long (0x200+0xA0)++0x3
|
|
line.long 0x00 "PWM_CMR5,Channel 5 Mode Register"
|
|
bitfld.long 0x00 18. " DTLI ,Dead-Time PWML5 Output Inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " DTHI ,Dead-Time PWMH5 Output Inverted" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DTE ,Dead-Time Generator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CES ,Counter Event Selection" "At the end of period,At the end of period"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low level,High level"
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
endif
|
|
group.long (0x204+0xA0)++0x3
|
|
line.long 0x00 "PWM_CDTY5,PWM Channel 5 Duty Cycle Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CDTY ,Channel Duty-Cycle"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CDTY ,Channel Duty-Cycle"
|
|
endif
|
|
wgroup.long (0x208+0xA0)++0x3
|
|
line.long 0x00 "PWM_CDTYUPD5,PWM Channel 5 Duty Cycle Update Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CDTYUPD ,Channel Duty-Cycle Update"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CDTYUPD ,Channel Duty-Cycle Update"
|
|
endif
|
|
group.long (0x20c+0xA0)++0x03
|
|
line.long 0x00 "PWM_CPRD5,PWM Channel 5 Period Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*"))
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CPRD ,Channel Period"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CPRD ,Channel Period"
|
|
endif
|
|
wgroup.long (0x210+0xA0)++0x03
|
|
line.long 0x00 "PWM_CPRDUPD5,Channel 5 Update Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.tbyte 0x0 0.--23. 1. " CPRDUPD ,Channel Period Update"
|
|
else
|
|
hexmask.long.word 0x0 0.--15. 1. " CPRDUPD ,Channel Period Update"
|
|
endif
|
|
rgroup.long (0x214+0xA0)++0x03
|
|
line.long 0x00 "PWM_CCNT5,PWM Channel 5 Counter Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.tbyte 0x0 0.--23. 1. " CNT ,Channel Counter Register"
|
|
else
|
|
hexmask.long.word 0x0 0.--15. 1. " CNT ,Channel Counter Register"
|
|
endif
|
|
group.long (0x218+0xA0)++0x03
|
|
line.long 0x00 "PWM_DT5,PWM Channel Dead Time Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.word 0x00 16.--31. 1. " DTL ,Dead-Time Value for PWML5 Output"
|
|
hexmask.long.word 0x00 0.--15. 1. " DTH ,Dead-Time Value for PWMH5 Output"
|
|
else
|
|
hexmask.long.word 0x00 16.--27. 1. " DTL ,Dead-Time Value for PWML5 Output"
|
|
hexmask.long.word 0x00 0.--11. 1. " DTH ,Dead-Time Value for PWMH5 Output"
|
|
endif
|
|
wgroup.long (0x21c+0xA0)++0x03
|
|
line.long 0x00 "PWM_DTUPD5,PWM Channel Dead Time Update Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.word 0x00 16.--31. 1. " DTLUPD ,Dead-Time Value Update for PWML5 Output"
|
|
hexmask.long.word 0x00 0.--15. 1. " DTHUPD ,Dead-Time Value Update for PWMH5 Output"
|
|
else
|
|
hexmask.long.word 0x00 16.--27. 1. " DTLUPD ,Dead-Time Value Update for PWML5 Output"
|
|
hexmask.long.word 0x00 0.--11. 1. " DTHUPD ,Dead-Time Value Update for PWMH5 Output"
|
|
endif
|
|
tree.end
|
|
tree "Channel 6"
|
|
if ((d.l(ad:0x40094000+0x200+0xC0)&0x100)==0x100)
|
|
group.long (0x200+0xC0)++0x3
|
|
line.long 0x00 "PWM_CMR6,Channel 6 Mode Register"
|
|
bitfld.long 0x00 18. " DTLI ,Dead-Time PWML6 Output Inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " DTHI ,Dead-Time PWMH6 Output Inverted" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DTE ,Dead-Time Generator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CES ,Counter Event Selection" "At the end of period,At the end and half the period"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low level,High level"
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
else
|
|
group.long (0x200+0xC0)++0x3
|
|
line.long 0x00 "PWM_CMR6,Channel 6 Mode Register"
|
|
bitfld.long 0x00 18. " DTLI ,Dead-Time PWML6 Output Inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " DTHI ,Dead-Time PWMH6 Output Inverted" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DTE ,Dead-Time Generator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CES ,Counter Event Selection" "At the end of period,At the end of period"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low level,High level"
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
endif
|
|
group.long (0x204+0xC0)++0x3
|
|
line.long 0x00 "PWM_CDTY6,PWM Channel 6 Duty Cycle Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CDTY ,Channel Duty-Cycle"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CDTY ,Channel Duty-Cycle"
|
|
endif
|
|
wgroup.long (0x208+0xC0)++0x3
|
|
line.long 0x00 "PWM_CDTYUPD6,PWM Channel 6 Duty Cycle Update Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CDTYUPD ,Channel Duty-Cycle Update"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CDTYUPD ,Channel Duty-Cycle Update"
|
|
endif
|
|
group.long (0x20c+0xC0)++0x03
|
|
line.long 0x00 "PWM_CPRD6,PWM Channel 6 Period Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*"))
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CPRD ,Channel Period"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CPRD ,Channel Period"
|
|
endif
|
|
wgroup.long (0x210+0xC0)++0x03
|
|
line.long 0x00 "PWM_CPRDUPD6,Channel 6 Update Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.tbyte 0x0 0.--23. 1. " CPRDUPD ,Channel Period Update"
|
|
else
|
|
hexmask.long.word 0x0 0.--15. 1. " CPRDUPD ,Channel Period Update"
|
|
endif
|
|
rgroup.long (0x214+0xC0)++0x03
|
|
line.long 0x00 "PWM_CCNT6,PWM Channel 6 Counter Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.tbyte 0x0 0.--23. 1. " CNT ,Channel Counter Register"
|
|
else
|
|
hexmask.long.word 0x0 0.--15. 1. " CNT ,Channel Counter Register"
|
|
endif
|
|
group.long (0x218+0xC0)++0x03
|
|
line.long 0x00 "PWM_DT6,PWM Channel Dead Time Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.word 0x00 16.--31. 1. " DTL ,Dead-Time Value for PWML6 Output"
|
|
hexmask.long.word 0x00 0.--15. 1. " DTH ,Dead-Time Value for PWMH6 Output"
|
|
else
|
|
hexmask.long.word 0x00 16.--27. 1. " DTL ,Dead-Time Value for PWML6 Output"
|
|
hexmask.long.word 0x00 0.--11. 1. " DTH ,Dead-Time Value for PWMH6 Output"
|
|
endif
|
|
wgroup.long (0x21c+0xC0)++0x03
|
|
line.long 0x00 "PWM_DTUPD6,PWM Channel Dead Time Update Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.word 0x00 16.--31. 1. " DTLUPD ,Dead-Time Value Update for PWML6 Output"
|
|
hexmask.long.word 0x00 0.--15. 1. " DTHUPD ,Dead-Time Value Update for PWMH6 Output"
|
|
else
|
|
hexmask.long.word 0x00 16.--27. 1. " DTLUPD ,Dead-Time Value Update for PWML6 Output"
|
|
hexmask.long.word 0x00 0.--11. 1. " DTHUPD ,Dead-Time Value Update for PWMH6 Output"
|
|
endif
|
|
tree.end
|
|
tree "Channel 7"
|
|
if ((d.l(ad:0x40094000+0x200+0xE0)&0x100)==0x100)
|
|
group.long (0x200+0xE0)++0x3
|
|
line.long 0x00 "PWM_CMR7,Channel 7 Mode Register"
|
|
bitfld.long 0x00 18. " DTLI ,Dead-Time PWML7 Output Inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " DTHI ,Dead-Time PWMH7 Output Inverted" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DTE ,Dead-Time Generator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CES ,Counter Event Selection" "At the end of period,At the end and half the period"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low level,High level"
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
else
|
|
group.long (0x200+0xE0)++0x3
|
|
line.long 0x00 "PWM_CMR7,Channel 7 Mode Register"
|
|
bitfld.long 0x00 18. " DTLI ,Dead-Time PWML7 Output Inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " DTHI ,Dead-Time PWMH7 Output Inverted" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DTE ,Dead-Time Generator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CES ,Counter Event Selection" "At the end of period,At the end of period"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CPOL ,Channel Polarity" "Low level,High level"
|
|
bitfld.long 0x00 8. " CALG ,Channel Alignment" "Left,Center"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel Pre-scaler" "MCK,MCK/2,MCK/4,MCK/8,MCK/16,MCK/32,MCK/64,MCK/128,MCK/256,MCK/512,MCK/1024,CLKA,CLKB,?..."
|
|
endif
|
|
group.long (0x204+0xE0)++0x3
|
|
line.long 0x00 "PWM_CDTY7,PWM Channel 7 Duty Cycle Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CDTY ,Channel Duty-Cycle"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CDTY ,Channel Duty-Cycle"
|
|
endif
|
|
wgroup.long (0x208+0xE0)++0x3
|
|
line.long 0x00 "PWM_CDTYUPD7,PWM Channel 7 Duty Cycle Update Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CDTYUPD ,Channel Duty-Cycle Update"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CDTYUPD ,Channel Duty-Cycle Update"
|
|
endif
|
|
group.long (0x20c+0xE0)++0x03
|
|
line.long 0x00 "PWM_CPRD7,PWM Channel 7 Period Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*"))
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CPRD ,Channel Period"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " CPRD ,Channel Period"
|
|
endif
|
|
wgroup.long (0x210+0xE0)++0x03
|
|
line.long 0x00 "PWM_CPRDUPD7,Channel 7 Update Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.tbyte 0x0 0.--23. 1. " CPRDUPD ,Channel Period Update"
|
|
else
|
|
hexmask.long.word 0x0 0.--15. 1. " CPRDUPD ,Channel Period Update"
|
|
endif
|
|
rgroup.long (0x214+0xE0)++0x03
|
|
line.long 0x00 "PWM_CCNT7,PWM Channel 7 Counter Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.tbyte 0x0 0.--23. 1. " CNT ,Channel Counter Register"
|
|
else
|
|
hexmask.long.word 0x0 0.--15. 1. " CNT ,Channel Counter Register"
|
|
endif
|
|
group.long (0x218+0xE0)++0x03
|
|
line.long 0x00 "PWM_DT7,PWM Channel Dead Time Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.word 0x00 16.--31. 1. " DTL ,Dead-Time Value for PWML7 Output"
|
|
hexmask.long.word 0x00 0.--15. 1. " DTH ,Dead-Time Value for PWMH7 Output"
|
|
else
|
|
hexmask.long.word 0x00 16.--27. 1. " DTL ,Dead-Time Value for PWML7 Output"
|
|
hexmask.long.word 0x00 0.--11. 1. " DTH ,Dead-Time Value for PWMH7 Output"
|
|
endif
|
|
wgroup.long (0x21c+0xE0)++0x03
|
|
line.long 0x00 "PWM_DTUPD7,PWM Channel Dead Time Update Register"
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E")||cpuis("ATSAM4S*")||cpuis("ATSAMA5D36"))
|
|
hexmask.long.word 0x00 16.--31. 1. " DTLUPD ,Dead-Time Value Update for PWML7 Output"
|
|
hexmask.long.word 0x00 0.--15. 1. " DTHUPD ,Dead-Time Value Update for PWMH7 Output"
|
|
else
|
|
hexmask.long.word 0x00 16.--27. 1. " DTLUPD ,Dead-Time Value Update for PWML7 Output"
|
|
hexmask.long.word 0x00 0.--11. 1. " DTHUPD ,Dead-Time Value Update for PWMH7 Output"
|
|
endif
|
|
tree.end
|
|
endif
|
|
width 0xb
|
|
tree "PDC (Peripheral DMA Controller)"
|
|
base ad:0x40094000
|
|
width 10.
|
|
group.long 0x100++0x01F
|
|
line.long 0x00 "PWM_RPR,Receive Pointer Register"
|
|
line.long 0x04 "PWM_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RXCTR ,Receive Counter Value"
|
|
line.long 0x08 "PWM_TPR,Transmit Pointer Register"
|
|
line.long 0x0c "PWM_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TXCTR ,Transmit Counter Value"
|
|
line.long 0x10 "PWM_RNPR,Receive Next Pointer Register"
|
|
line.long 0x14 "PWM_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " RXNCR ,Receive Next Counter Value"
|
|
line.long 0x18 "PWM_TNPR,Transmit Next Pointer Register"
|
|
line.long 0x1c "PWM_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TXNCR ,Transmit Next Counter Value"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "PWM_PTCR,PDC Transfer Control Register"
|
|
bitfld.long 0x00 9. " TXTDIS ,Transmitter Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " RXTDIS ,Receiver Transfer Disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "No effect,Enable"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "PWM_PTSR,PDC Transfer Status Register"
|
|
bitfld.long 0x00 8. " TXTEN ,Transmitter Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RXTEN ,Receiver Transfer Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "UOTGHS (USB On-The-Go Interface)"
|
|
base ad:0x400AC000
|
|
width 23.
|
|
tree "General registers"
|
|
group.long 0x800++0x3
|
|
line.long 0x00 "UOTGHS_CTRL,General Control Register"
|
|
bitfld.long 0x00 25. " UIMOD ,UOTGHS Mode" "Host,Device"
|
|
bitfld.long 0x00 24. " UIDE ,UOTGID Pin Enable" "UIMOD bit,UOTGID pin"
|
|
newline
|
|
bitfld.long 0x00 22. " UNLOCK ,Timer Access Unlock" "Locked,Unlocked"
|
|
bitfld.long 0x00 20.--21. " TIMPAGE ,Timer Page" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " TIMVALUE ,Timer Value" "0,1,2,3"
|
|
bitfld.long 0x00 15. " USBE ,UOTGHS Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " FRZCLK ,Freeze USB Clock" "Enabled,Disabled"
|
|
bitfld.long 0x00 13. " VBUSPO ,VBus Polarity Off" "Default mode,Inverted"
|
|
newline
|
|
bitfld.long 0x00 12. " OTGPADE ,OTG Pad Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " HNPREQ ,HNP Request(Host/Device)" "Reject/No effect,Accept/Initiated"
|
|
newline
|
|
bitfld.long 0x00 10. " SRPREQ ,SRP Request" "No effect,Initiated"
|
|
bitfld.long 0x00 9. " SRPSEL ,SRP Selection" "No effect,Initiated"
|
|
newline
|
|
bitfld.long 0x00 8. " VBUSHWC ,VBus Hardware Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 7. " STOE ,Suspend Time-Out Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " HNPERRE ,HNP Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ROLEEXE ,Role Exchange Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " BCERRE ,B-Connection Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " VBERRE ,VBus Error Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " SRPE ,SRP Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " VBUSTE ,VBus Transition Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " IDTE ,ID Transition Interrupt Enable" "Disabled,Enabled"
|
|
group.long 0x804++0x3
|
|
line.long 0x00 "UOTGHS_SR,General Status Register"
|
|
bitfld.long 0x00 14. " CLKUSABLE ,UTMI Clock Usable" "Not usable,Usable"
|
|
bitfld.long 0x00 12.--13. " SPEED ,Speed Status" "Full-speed,High-speed,Low-speed,?..."
|
|
newline
|
|
bitfld.long 0x00 11. " VBUS ,VBus Level" "Low,High"
|
|
bitfld.long 0x00 10. " ID ,UOTGID Pin State" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x08 9. 0x04 9. " VBUSRQ_set/clr ,VBus Request" "Low,High"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " STOI_set/clr ,Suspend Time-Out Interrupt" "Not detected,Detected"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " HNPERRI_set/clr ,HNP Error Interrupt" "Not detected,Detected"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " ROLEEXI_set/clr ,Role Exchange Interrupt" "No effect,Switched"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " BCERRI_set/clr ,B-Connection Error Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " VBERRI_set/clr ,VBus Error Interrupt" "Not detected,Detected"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " SRPI_set/clr ,SRP Interrupt" "Not detected,Detected"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " VBUSTI_set/clr ,VBus Transition Interrupt" "Not detected,Detected"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " IDTI_set/clr ,ID Transition Interrupt" "Not detected,Detected"
|
|
rgroup.long 0x82C++0x3
|
|
line.long 0x00 "UOTGHS_FSM,General Finite State Machine Register"
|
|
bitfld.long 0x00 0.--3. " DRDSTATE ,The state of the UOTGHS" "A_IDLESTATE,A_WAIT_VRISE,A_WAIT_BCON,A_HOST,A_SUSPEND,A_PERIPHERAL,A_WAIT_VFALL,A_VBUS_ERR,A_WAIT_DISCHARGE,B_IDLE,B_PERIPHERAL,B_WAIT_BEGIN_HNP,B_WAIT_DISCHARGE,B_WAIT_ACON,B_HOST,B_SRP_INIT"
|
|
tree.end
|
|
width 23.
|
|
tree "Device registers"
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "UOTGHS_DEVCTRL,Device General Control Register"
|
|
bitfld.long 0x00 16. " OPMODE2 ,Specific Operational mode" "Normal mode,Operational mode"
|
|
bitfld.long 0x00 15. " TSTPCKT ,Test packet mode" "Normal mode,Test mode"
|
|
newline
|
|
bitfld.long 0x00 14. " TSTK ,Test mode K" "Normal mode,K test"
|
|
bitfld.long 0x00 13. " TSTJ ,Test mode J" "Normal mode,J test"
|
|
newline
|
|
bitfld.long 0x00 12. " LS ,Low-Speed Mode Force" "Full-speed,Low-speed"
|
|
bitfld.long 0x00 10.--11. " SPDCONF ,Mode Configuration" "Normal,Low-power,High-speed,Forced full-speed"
|
|
newline
|
|
bitfld.long 0x00 9. " RMWKUP ,Remote Wake-Up" "No effect,Remote wake-up"
|
|
bitfld.long 0x00 8. " DETACH ,Detach" "Reconnect,Detach"
|
|
newline
|
|
bitfld.long 0x00 7. " ADDEN ,Address Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " UADD ,USB Address"
|
|
line.long 0x04 "UOTGHS_DEVISR,Device Global Interrupt Status Register"
|
|
bitfld.long 0x04 30. " DMA_6 ,DMA Channel 6 Interrupt" "Cleared,Triggered"
|
|
bitfld.long 0x04 29. " DMA_5 ,DMA Channel 5 Interrupt" "Cleared,Triggered"
|
|
newline
|
|
bitfld.long 0x04 28. " DMA_4 ,DMA Channel 4 Interrupt" "Cleared,Triggered"
|
|
bitfld.long 0x04 27. " DMA_3 ,DMA Channel 3 Interrupt" "Cleared,Triggered"
|
|
newline
|
|
bitfld.long 0x04 26. " DMA_2 ,DMA Channel 2 Interrupt" "Cleared,Triggered"
|
|
bitfld.long 0x04 25. " DMA_1 ,DMA Channel 1 Interrupt" "Cleared,Triggered"
|
|
newline
|
|
bitfld.long 0x04 21. " PEP_9 ,Endpoint 9 Interrupt" "Serviced,Triggered"
|
|
bitfld.long 0x04 20. " PEP_8 ,Endpoint 8 Interrupt" "Serviced,Triggered"
|
|
newline
|
|
bitfld.long 0x04 19. " PEP_7 ,Endpoint 7 Interrupt" "Serviced,Triggered"
|
|
bitfld.long 0x04 18. " PEP_6 ,Endpoint 6 Interrupt" "Serviced,Triggered"
|
|
newline
|
|
bitfld.long 0x04 17. " PEP_5 ,Endpoint 5 Interrupt" "Serviced,Triggered"
|
|
bitfld.long 0x04 16. " PEP_4 ,Endpoint 4 Interrupt" "Serviced,Triggered"
|
|
newline
|
|
bitfld.long 0x04 15. " PEP_3 ,Endpoint 3 Interrupt" "Serviced,Triggered"
|
|
bitfld.long 0x04 14. " PEP_2 ,Endpoint 2 Interrupt" "Serviced,Triggered"
|
|
newline
|
|
bitfld.long 0x04 13. " PEP_1 ,Endpoint 1 Interrupt" "Serviced,Triggered"
|
|
bitfld.long 0x04 12. " PEP_0 ,Endpoint 0 Interrupt" "Serviced,Triggered"
|
|
newline
|
|
setclrfld.long 0x04 6. 0x08 6. 0x04 6. " UPRSM_set/clr ,Upstream Resume Interrupt" "UPRSMC is written,Upstream Resume"
|
|
setclrfld.long 0x04 5. 0x08 5. 0x04 5. " EORSM_set/clr ,End of Resume Interrupt" "EORSMC is written,End of Resume"
|
|
newline
|
|
setclrfld.long 0x04 4. 0x08 4. 0x04 4. " WAKEUPv ,Wake-Up Interrupt" "WAKEUPC is written,Reactivated"
|
|
setclrfld.long 0x04 3. 0x08 3. 0x04 3. " EORST_set/clr ,End of Reset Interrupt" "EORSTC is written,Detected"
|
|
newline
|
|
setclrfld.long 0x04 2. 0x08 2. 0x04 2. " SOF_set/clr ,Start of Frame Interrupt" "SOFC is written,Detected"
|
|
setclrfld.long 0x04 1. 0x08 1. 0x04 1. " MSOF_set/clr ,Micro Start of Frame Interrupt" "MSOFC is written,Detected"
|
|
newline
|
|
setclrfld.long 0x04 0. 0x08 0. 0x04 0. " SUSP_set/clr ,Suspend Interrupt" "SUSPC is written,Dtected"
|
|
wgroup.long 0x0C++0x3
|
|
line.long 0x00 "UOTGHS_DEVIFR,Device Global Interrupt Set Register"
|
|
bitfld.long 0x00 30. " DMA_6 ,DMA Channel 6 Interrupt Set" "No effect,Set"
|
|
bitfld.long 0x00 29. " DMA_5 ,DMA Channel 5 Interrupt Set" "No effect,Set"
|
|
newline
|
|
bitfld.long 0x00 28. " DMA_4 ,DMA Channel 4 Interrupt Set" "No effect,Set"
|
|
bitfld.long 0x00 27. " DMA_3 ,DMA Channel 3 Interrupt Set" "No effect,Set"
|
|
newline
|
|
bitfld.long 0x00 26. " DMA_2 ,DMA Channel 2 Interrupt Set" "No effect,Set"
|
|
bitfld.long 0x00 25. " DMA_1 ,DMA Channel 1 Interrupt Set" "No effect,Set"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "UOTGHS_DEVIMR,Device Global Interrupt Mask Register"
|
|
setclrfld.long 0x00 30. 0x08 0. 0x04 0. " DMA_6_set/clr ,DMA Channel 6 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x08 0. 0x04 0. " DMA_5_set/clr ,DMA Channel 5 Interrupt Mask" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 28. 0x08 0. 0x04 0. " DMA_4_set/clr ,DMA Channel 4 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x08 0. 0x04 0. " DMA_3_set/clr ,DMA Channel 3 Interrupt Mask" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 26. 0x08 0. 0x04 0. " DMA_2_set/clr ,DMA Channel 2 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x08 0. 0x04 0. " DMA_1_set/clr ,DMA Channel 1 Interrupt Mask" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 21. 0x08 0. 0x04 0. " PEP_9_set/clr ,Endpoint 9 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x08 0. 0x04 0. " PEP_8_set/clr ,Endpoint 8 Interrupt Mask" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x08 0. 0x04 0. " PEP_7_set/clr ,Endpoint 7 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x08 0. 0x04 0. " PEP_6_set/clr ,Endpoint 6 Interrupt Mask" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x08 0. 0x04 0. " PEP_5_set/clr ,Endpoint 5 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x08 0. 0x04 0. " PEP_4_set/clr ,Endpoint 4 Interrupt Mask" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x08 0. 0x04 0. " PEP_3_set/clr ,Endpoint 3 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x08 0. 0x04 0. " PEP_2_set/clr ,Endpoint 2 Interrupt Mask" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x08 0. 0x04 0. " PEP_1_set/clr ,Endpoint 1 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x08 0. 0x04 0. " PEP_0_set/clr ,Endpoint 0 Interrupt Mask" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " UPRSM_set/clr ,Upstream Resume Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " EORSM_set/clr ,End of Resume Interrupt Mask" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " WAKEUP_set/clr ,Wake-Up Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " EORST_set/clr ,End of Reset Interrupt Mask" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " SOF_set/clr ,Start of Frame Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " MSOF_set/clr ,Micro Start of Frame Interrupt Mask" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " SUSP_set/clr ,Suspend Interrupt Mask" "Disabled,Enabled"
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPT,Device Endpoint Register"
|
|
bitfld.long 0x00 24. " EPRST8 ,Endpoint 8 Reset" "No reset,Reset"
|
|
bitfld.long 0x00 23. " EPRST7 ,Endpoint 7 Reset" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 22. " EPRST6 ,Endpoint 6 Reset" "No reset,Reset"
|
|
bitfld.long 0x00 21. " EPRST5 ,Endpoint 5 Reset" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 20. " EPRST4 ,Endpoint 4 Reset" "No reset,Reset"
|
|
bitfld.long 0x00 19. " EPRST3 ,Endpoint 3 Reset" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 18. " EPRST2 ,Endpoint 2 Reset" "No reset,Reset"
|
|
bitfld.long 0x00 17. " EPRST1 ,Endpoint 1 Reset" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 16. " EPRST0 ,Endpoint 0 Reset" "No reset,Reset"
|
|
bitfld.long 0x00 8. " EPEN8 ,Endpoint 8 Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " EPEN7 ,Endpoint 7 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " EPEN6 ,Endpoint 6 Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " EPEN5 ,Endpoint 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " EPEN4 ,Endpoint 4 Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " EPEN3 ,Endpoint 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EPEN2 ,Endpoint 2 Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " EPEN1 ,Endpoint 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EPEN0 ,Endpoint 0 Enable" "Disabled,Enabled"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x00 "UOTGHS_DEVFNUM,Device Frame Number Register"
|
|
bitfld.long 0x00 15. " FNCERR ,Frame Number CRC Error" "Not received,Received"
|
|
hexmask.long.word 0x00 3.--13. 1. " FNUM ,Frame Number"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " MFNUM ,Micro Frame Number" "0,1,2,3,4,5,6,7"
|
|
width 23.
|
|
tree "Endpoint 0"
|
|
group.long 0x100++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTCFG0,Device Endpoint 0 Configuration Register"
|
|
bitfld.long 0x00 13.--14. " NBTRANS ,Number of transaction per microframe for isochronous endpoint" ",1,2,3"
|
|
bitfld.long 0x00 11.--12. " EPTYPE ,Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 9. " AUTOSW ,Automatic Switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EPDIR ,Endpoint Direction" "Out,In"
|
|
newline
|
|
group.long (0x100+0x30)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTISR0,Device Endpoint 0 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte Count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK Status" "Uncorrect,Correct"
|
|
newline
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control Direction" "Out,In"
|
|
bitfld.long 0x00 16. " RWALL ,Read-write Allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current Bank" "Bank0,Bank1,Bank2,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of Busy Banks" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10. " ERRORTRANS ,High-bandwidth isochronous OUT endpoint transaction error Interrupt" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data Toggle Sequence" "Data0,Data1,Data2,MData"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_set/clr ,Short Packet Interrupt" "Not received,Received"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " STALLEDI/CRCERRI_set/clr ,STALLed Interrupt/CRC Error Interrupt" "Not sent/Not detected,Sent/Detected"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_set/clr ,Overflow Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKINI/HBISOFLUSHI_set/clr ,NAKed IN Interrupt/High Bandwidth Isochronous IN Flush Interrupt" "Not sent/Not detected,Sent/Detected"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " NAKOUTI/HBISOINERRI_set/clr ,NAKed OUT Interrupt/High bandwidth isochronous IN Underflow Error Interrupt" "Not sent/Not occurred,Sent/Occurred"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " RXSTPI/UNDERFI_set/clr ,Received SETUP Interrupt/Underflow Interrupt" "No effect/Not occurred,New SETUP packet/Occurred"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXOUTI_set/clr ,Received OUT Data Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " TXINI_set/clr ,Transmitted IN Data Interrupt" "Not ready,Ready"
|
|
wgroup.long (0x100+0x60)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTIFR0,Device Endpoint 0 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of Busy Banks Interrupt Set" "Not set,UOTGHS_DEVEPTISR0 set"
|
|
group.long (0x100+0x90)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTIMR0,Device Endpoint 0 Mask Register"
|
|
setclrfld.long 0x00 19. 0x30 19. 0x60 19. " STALLRQ_set/clr ,STALL Request" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset Data Toggle" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " NYETDIS_set/clr ,NYET Token Disable" "Masked,Not masked"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " EPDISHDMA_set/clr ,Endpoint Interrupts Disable HDMA Request" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 14. " FIFOCON ,FIFO Control" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN Bank" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_set/clr ,Number of Busy Banks Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 10. 0x30 10. 0x60 10. " ERRORTRANSE_set/clr ,Transaction Error Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x30 9. 0x60 9. " DATAXE_set/clr ,DataX Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. 0x30 8. 0x60 8. " MDATAE_set/clr ,MData Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETE_set/clr ,Short Packet Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " STALLEDE/CRCERRE_set/clr ,STALLed Interrupt/CRC Error Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFE_set/clr ,Overflow Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKINE/HBISOFLUSHE_set/clr ,NAKed IN Interrupt/High Bandwidth Isochronous IN Flush Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " NAKOUTE/HBISOINERRE_set/clr ,NAKed OUT Interrupt/High Bandwidth Isochronous IN Error Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " RXSTPE/UNDERFE_set/clr ,Received SETUP Interrupt/Underflow Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " RXOUTE_set/clr ,Received OUT Data Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " TXINE_set/clr ,Transmitted IN Data Interrupt" "Masked,Not masked"
|
|
wgroup.long (0x100+0x120)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTIDR0,Device Endpoint 0 Disable Register"
|
|
bitfld.long 0x00 14. " FIFOCONC ,FIFO Control Clear" "Not clear,Clear"
|
|
wgroup.long (0x100+0xB0)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTIER0,Device Endpoint 0 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDTS ,Reset Data Toggle Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 13. " KILLBKS ,Kill IN Bank" "No effect,Enabled"
|
|
tree.end
|
|
tree "Endpoint 1"
|
|
group.long 0x104++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTCFG1,Device Endpoint 1 Configuration Register"
|
|
bitfld.long 0x00 13.--14. " NBTRANS ,Number of transaction per microframe for isochronous endpoint" ",1,2,3"
|
|
bitfld.long 0x00 11.--12. " EPTYPE ,Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 9. " AUTOSW ,Automatic Switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EPDIR ,Endpoint Direction" "Out,In"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " EPSIZE ,Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " EPBK ,Endpoint Banks" "Single-bank,Double-bank,Triple-bank,?..."
|
|
newline
|
|
bitfld.long 0x00 1. " ALLOC ,Endpoint Memory Allocate" "Not allocated,Allocated"
|
|
group.long (0x104+0x30)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTISR1,Device Endpoint 1 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte Count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK Status" "Uncorrect,Correct"
|
|
newline
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control Direction" "Out,In"
|
|
bitfld.long 0x00 16. " RWALL ,Read-write Allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current Bank" "Bank0,Bank1,Bank2,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of Busy Banks" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10. " ERRORTRANS ,High-bandwidth isochronous OUT endpoint transaction error Interrupt" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data Toggle Sequence" "Data0,Data1,Data2,MData"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_set/clr ,Short Packet Interrupt" "Not received,Received"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " STALLEDI/CRCERRI_set/clr ,STALLed Interrupt/CRC Error Interrupt" "Not sent/Not detected,Sent/Detected"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_set/clr ,Overflow Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKINI/HBISOFLUSHI_set/clr ,NAKed IN Interrupt/High Bandwidth Isochronous IN Flush Interrupt" "Not sent/Not detected,Sent/Detected"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " NAKOUTI/HBISOINERRI_set/clr ,NAKed OUT Interrupt/High bandwidth isochronous IN Underflow Error Interrupt" "Not sent/Not occurred,Sent/Occurred"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " RXSTPI/UNDERFI_set/clr ,Received SETUP Interrupt/Underflow Interrupt" "No effect/Not occurred,New SETUP packet/Occurred"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXOUTI_set/clr ,Received OUT Data Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " TXINI_set/clr ,Transmitted IN Data Interrupt" "Not ready,Ready"
|
|
wgroup.long (0x104+0x60)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTIFR1,Device Endpoint 1 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of Busy Banks Interrupt Set" "Not set,UOTGHS_DEVEPTISR1 set"
|
|
group.long (0x104+0x90)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTIMR1,Device Endpoint 1 Mask Register"
|
|
setclrfld.long 0x00 19. 0x30 19. 0x60 19. " STALLRQ_set/clr ,STALL Request" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset Data Toggle" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " NYETDIS_set/clr ,NYET Token Disable" "Masked,Not masked"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " EPDISHDMA_set/clr ,Endpoint Interrupts Disable HDMA Request" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 14. " FIFOCON ,FIFO Control" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN Bank" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_set/clr ,Number of Busy Banks Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 10. 0x30 10. 0x60 10. " ERRORTRANSE_set/clr ,Transaction Error Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x30 9. 0x60 9. " DATAXE_set/clr ,DataX Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. 0x30 8. 0x60 8. " MDATAE_set/clr ,MData Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETE_set/clr ,Short Packet Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " STALLEDE/CRCERRE_set/clr ,STALLed Interrupt/CRC Error Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFE_set/clr ,Overflow Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKINE/HBISOFLUSHE_set/clr ,NAKed IN Interrupt/High Bandwidth Isochronous IN Flush Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " NAKOUTE/HBISOINERRE_set/clr ,NAKed OUT Interrupt/High Bandwidth Isochronous IN Error Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " RXSTPE/UNDERFE_set/clr ,Received SETUP Interrupt/Underflow Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " RXOUTE_set/clr ,Received OUT Data Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " TXINE_set/clr ,Transmitted IN Data Interrupt" "Masked,Not masked"
|
|
wgroup.long (0x104+0x120)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTIDR1,Device Endpoint 1 Disable Register"
|
|
bitfld.long 0x00 14. " FIFOCONC ,FIFO Control Clear" "Not clear,Clear"
|
|
wgroup.long (0x104+0xB0)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTIER1,Device Endpoint 1 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDTS ,Reset Data Toggle Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 13. " KILLBKS ,Kill IN Bank" "No effect,Enabled"
|
|
tree.end
|
|
tree "Endpoint 2"
|
|
group.long 0x108++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTCFG2,Device Endpoint 2 Configuration Register"
|
|
bitfld.long 0x00 13.--14. " NBTRANS ,Number of transaction per microframe for isochronous endpoint" ",1,2,3"
|
|
bitfld.long 0x00 11.--12. " EPTYPE ,Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 9. " AUTOSW ,Automatic Switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EPDIR ,Endpoint Direction" "Out,In"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " EPSIZE ,Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " EPBK ,Endpoint Banks" "Single-bank,Double-bank,Triple-bank,?..."
|
|
newline
|
|
bitfld.long 0x00 1. " ALLOC ,Endpoint Memory Allocate" "Not allocated,Allocated"
|
|
group.long (0x108+0x30)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTISR2,Device Endpoint 2 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte Count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK Status" "Uncorrect,Correct"
|
|
newline
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control Direction" "Out,In"
|
|
bitfld.long 0x00 16. " RWALL ,Read-write Allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current Bank" "Bank0,Bank1,Bank2,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of Busy Banks" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10. " ERRORTRANS ,High-bandwidth isochronous OUT endpoint transaction error Interrupt" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data Toggle Sequence" "Data0,Data1,Data2,MData"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_set/clr ,Short Packet Interrupt" "Not received,Received"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " STALLEDI/CRCERRI_set/clr ,STALLed Interrupt/CRC Error Interrupt" "Not sent/Not detected,Sent/Detected"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_set/clr ,Overflow Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKINI/HBISOFLUSHI_set/clr ,NAKed IN Interrupt/High Bandwidth Isochronous IN Flush Interrupt" "Not sent/Not detected,Sent/Detected"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " NAKOUTI/HBISOINERRI_set/clr ,NAKed OUT Interrupt/High bandwidth isochronous IN Underflow Error Interrupt" "Not sent/Not occurred,Sent/Occurred"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " RXSTPI/UNDERFI_set/clr ,Received SETUP Interrupt/Underflow Interrupt" "No effect/Not occurred,New SETUP packet/Occurred"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXOUTI_set/clr ,Received OUT Data Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " TXINI_set/clr ,Transmitted IN Data Interrupt" "Not ready,Ready"
|
|
wgroup.long (0x108+0x60)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTIFR2,Device Endpoint 2 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of Busy Banks Interrupt Set" "Not set,UOTGHS_DEVEPTISR2 set"
|
|
group.long (0x108+0x90)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTIMR2,Device Endpoint 2 Mask Register"
|
|
setclrfld.long 0x00 19. 0x30 19. 0x60 19. " STALLRQ_set/clr ,STALL Request" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset Data Toggle" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " NYETDIS_set/clr ,NYET Token Disable" "Masked,Not masked"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " EPDISHDMA_set/clr ,Endpoint Interrupts Disable HDMA Request" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 14. " FIFOCON ,FIFO Control" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN Bank" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_set/clr ,Number of Busy Banks Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 10. 0x30 10. 0x60 10. " ERRORTRANSE_set/clr ,Transaction Error Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x30 9. 0x60 9. " DATAXE_set/clr ,DataX Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. 0x30 8. 0x60 8. " MDATAE_set/clr ,MData Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETE_set/clr ,Short Packet Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " STALLEDE/CRCERRE_set/clr ,STALLed Interrupt/CRC Error Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFE_set/clr ,Overflow Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKINE/HBISOFLUSHE_set/clr ,NAKed IN Interrupt/High Bandwidth Isochronous IN Flush Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " NAKOUTE/HBISOINERRE_set/clr ,NAKed OUT Interrupt/High Bandwidth Isochronous IN Error Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " RXSTPE/UNDERFE_set/clr ,Received SETUP Interrupt/Underflow Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " RXOUTE_set/clr ,Received OUT Data Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " TXINE_set/clr ,Transmitted IN Data Interrupt" "Masked,Not masked"
|
|
wgroup.long (0x108+0x120)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTIDR2,Device Endpoint 2 Disable Register"
|
|
bitfld.long 0x00 14. " FIFOCONC ,FIFO Control Clear" "Not clear,Clear"
|
|
wgroup.long (0x108+0xB0)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTIER2,Device Endpoint 2 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDTS ,Reset Data Toggle Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 13. " KILLBKS ,Kill IN Bank" "No effect,Enabled"
|
|
tree.end
|
|
tree "Endpoint 3"
|
|
group.long 0x10C++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTCFG3,Device Endpoint 3 Configuration Register"
|
|
bitfld.long 0x00 13.--14. " NBTRANS ,Number of transaction per microframe for isochronous endpoint" ",1,2,3"
|
|
bitfld.long 0x00 11.--12. " EPTYPE ,Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 9. " AUTOSW ,Automatic Switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EPDIR ,Endpoint Direction" "Out,In"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " EPSIZE ,Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " EPBK ,Endpoint Banks" "Single-bank,Double-bank,Triple-bank,?..."
|
|
newline
|
|
bitfld.long 0x00 1. " ALLOC ,Endpoint Memory Allocate" "Not allocated,Allocated"
|
|
group.long (0x10C+0x30)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTISR3,Device Endpoint 3 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte Count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK Status" "Uncorrect,Correct"
|
|
newline
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control Direction" "Out,In"
|
|
bitfld.long 0x00 16. " RWALL ,Read-write Allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current Bank" "Bank0,Bank1,Bank2,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of Busy Banks" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10. " ERRORTRANS ,High-bandwidth isochronous OUT endpoint transaction error Interrupt" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data Toggle Sequence" "Data0,Data1,Data2,MData"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_set/clr ,Short Packet Interrupt" "Not received,Received"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " STALLEDI/CRCERRI_set/clr ,STALLed Interrupt/CRC Error Interrupt" "Not sent/Not detected,Sent/Detected"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_set/clr ,Overflow Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKINI/HBISOFLUSHI_set/clr ,NAKed IN Interrupt/High Bandwidth Isochronous IN Flush Interrupt" "Not sent/Not detected,Sent/Detected"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " NAKOUTI/HBISOINERRI_set/clr ,NAKed OUT Interrupt/High bandwidth isochronous IN Underflow Error Interrupt" "Not sent/Not occurred,Sent/Occurred"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " RXSTPI/UNDERFI_set/clr ,Received SETUP Interrupt/Underflow Interrupt" "No effect/Not occurred,New SETUP packet/Occurred"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXOUTI_set/clr ,Received OUT Data Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " TXINI_set/clr ,Transmitted IN Data Interrupt" "Not ready,Ready"
|
|
wgroup.long (0x10C+0x60)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTIFR3,Device Endpoint 3 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of Busy Banks Interrupt Set" "Not set,UOTGHS_DEVEPTISR3 set"
|
|
group.long (0x10C+0x90)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTIMR3,Device Endpoint 3 Mask Register"
|
|
setclrfld.long 0x00 19. 0x30 19. 0x60 19. " STALLRQ_set/clr ,STALL Request" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset Data Toggle" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " NYETDIS_set/clr ,NYET Token Disable" "Masked,Not masked"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " EPDISHDMA_set/clr ,Endpoint Interrupts Disable HDMA Request" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 14. " FIFOCON ,FIFO Control" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN Bank" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_set/clr ,Number of Busy Banks Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 10. 0x30 10. 0x60 10. " ERRORTRANSE_set/clr ,Transaction Error Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x30 9. 0x60 9. " DATAXE_set/clr ,DataX Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. 0x30 8. 0x60 8. " MDATAE_set/clr ,MData Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETE_set/clr ,Short Packet Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " STALLEDE/CRCERRE_set/clr ,STALLed Interrupt/CRC Error Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFE_set/clr ,Overflow Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKINE/HBISOFLUSHE_set/clr ,NAKed IN Interrupt/High Bandwidth Isochronous IN Flush Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " NAKOUTE/HBISOINERRE_set/clr ,NAKed OUT Interrupt/High Bandwidth Isochronous IN Error Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " RXSTPE/UNDERFE_set/clr ,Received SETUP Interrupt/Underflow Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " RXOUTE_set/clr ,Received OUT Data Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " TXINE_set/clr ,Transmitted IN Data Interrupt" "Masked,Not masked"
|
|
wgroup.long (0x10C+0x120)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTIDR3,Device Endpoint 3 Disable Register"
|
|
bitfld.long 0x00 14. " FIFOCONC ,FIFO Control Clear" "Not clear,Clear"
|
|
wgroup.long (0x10C+0xB0)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTIER3,Device Endpoint 3 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDTS ,Reset Data Toggle Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 13. " KILLBKS ,Kill IN Bank" "No effect,Enabled"
|
|
tree.end
|
|
tree "Endpoint 4"
|
|
group.long 0x110++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTCFG4,Device Endpoint 4 Configuration Register"
|
|
bitfld.long 0x00 13.--14. " NBTRANS ,Number of transaction per microframe for isochronous endpoint" ",1,2,3"
|
|
bitfld.long 0x00 11.--12. " EPTYPE ,Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 9. " AUTOSW ,Automatic Switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EPDIR ,Endpoint Direction" "Out,In"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " EPSIZE ,Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " EPBK ,Endpoint Banks" "Single-bank,Double-bank,Triple-bank,?..."
|
|
newline
|
|
bitfld.long 0x00 1. " ALLOC ,Endpoint Memory Allocate" "Not allocated,Allocated"
|
|
group.long (0x110+0x30)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTISR4,Device Endpoint 4 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte Count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK Status" "Uncorrect,Correct"
|
|
newline
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control Direction" "Out,In"
|
|
bitfld.long 0x00 16. " RWALL ,Read-write Allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current Bank" "Bank0,Bank1,Bank2,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of Busy Banks" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10. " ERRORTRANS ,High-bandwidth isochronous OUT endpoint transaction error Interrupt" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data Toggle Sequence" "Data0,Data1,Data2,MData"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_set/clr ,Short Packet Interrupt" "Not received,Received"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " STALLEDI/CRCERRI_set/clr ,STALLed Interrupt/CRC Error Interrupt" "Not sent/Not detected,Sent/Detected"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_set/clr ,Overflow Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKINI/HBISOFLUSHI_set/clr ,NAKed IN Interrupt/High Bandwidth Isochronous IN Flush Interrupt" "Not sent/Not detected,Sent/Detected"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " NAKOUTI/HBISOINERRI_set/clr ,NAKed OUT Interrupt/High bandwidth isochronous IN Underflow Error Interrupt" "Not sent/Not occurred,Sent/Occurred"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " RXSTPI/UNDERFI_set/clr ,Received SETUP Interrupt/Underflow Interrupt" "No effect/Not occurred,New SETUP packet/Occurred"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXOUTI_set/clr ,Received OUT Data Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " TXINI_set/clr ,Transmitted IN Data Interrupt" "Not ready,Ready"
|
|
wgroup.long (0x110+0x60)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTIFR4,Device Endpoint 4 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of Busy Banks Interrupt Set" "Not set,UOTGHS_DEVEPTISR4 set"
|
|
group.long (0x110+0x90)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTIMR4,Device Endpoint 4 Mask Register"
|
|
setclrfld.long 0x00 19. 0x30 19. 0x60 19. " STALLRQ_set/clr ,STALL Request" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset Data Toggle" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " NYETDIS_set/clr ,NYET Token Disable" "Masked,Not masked"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " EPDISHDMA_set/clr ,Endpoint Interrupts Disable HDMA Request" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 14. " FIFOCON ,FIFO Control" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN Bank" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_set/clr ,Number of Busy Banks Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 10. 0x30 10. 0x60 10. " ERRORTRANSE_set/clr ,Transaction Error Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x30 9. 0x60 9. " DATAXE_set/clr ,DataX Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. 0x30 8. 0x60 8. " MDATAE_set/clr ,MData Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETE_set/clr ,Short Packet Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " STALLEDE/CRCERRE_set/clr ,STALLed Interrupt/CRC Error Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFE_set/clr ,Overflow Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKINE/HBISOFLUSHE_set/clr ,NAKed IN Interrupt/High Bandwidth Isochronous IN Flush Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " NAKOUTE/HBISOINERRE_set/clr ,NAKed OUT Interrupt/High Bandwidth Isochronous IN Error Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " RXSTPE/UNDERFE_set/clr ,Received SETUP Interrupt/Underflow Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " RXOUTE_set/clr ,Received OUT Data Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " TXINE_set/clr ,Transmitted IN Data Interrupt" "Masked,Not masked"
|
|
wgroup.long (0x110+0x120)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTIDR4,Device Endpoint 4 Disable Register"
|
|
bitfld.long 0x00 14. " FIFOCONC ,FIFO Control Clear" "Not clear,Clear"
|
|
wgroup.long (0x110+0xB0)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTIER4,Device Endpoint 4 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDTS ,Reset Data Toggle Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 13. " KILLBKS ,Kill IN Bank" "No effect,Enabled"
|
|
tree.end
|
|
tree "Endpoint 5"
|
|
group.long 0x114++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTCFG5,Device Endpoint 5 Configuration Register"
|
|
bitfld.long 0x00 13.--14. " NBTRANS ,Number of transaction per microframe for isochronous endpoint" ",1,2,3"
|
|
bitfld.long 0x00 11.--12. " EPTYPE ,Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 9. " AUTOSW ,Automatic Switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EPDIR ,Endpoint Direction" "Out,In"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " EPSIZE ,Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " EPBK ,Endpoint Banks" "Single-bank,Double-bank,Triple-bank,?..."
|
|
newline
|
|
bitfld.long 0x00 1. " ALLOC ,Endpoint Memory Allocate" "Not allocated,Allocated"
|
|
group.long (0x114+0x30)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTISR5,Device Endpoint 5 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte Count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK Status" "Uncorrect,Correct"
|
|
newline
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control Direction" "Out,In"
|
|
bitfld.long 0x00 16. " RWALL ,Read-write Allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current Bank" "Bank0,Bank1,Bank2,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of Busy Banks" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10. " ERRORTRANS ,High-bandwidth isochronous OUT endpoint transaction error Interrupt" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data Toggle Sequence" "Data0,Data1,Data2,MData"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_set/clr ,Short Packet Interrupt" "Not received,Received"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " STALLEDI/CRCERRI_set/clr ,STALLed Interrupt/CRC Error Interrupt" "Not sent/Not detected,Sent/Detected"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_set/clr ,Overflow Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKINI/HBISOFLUSHI_set/clr ,NAKed IN Interrupt/High Bandwidth Isochronous IN Flush Interrupt" "Not sent/Not detected,Sent/Detected"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " NAKOUTI/HBISOINERRI_set/clr ,NAKed OUT Interrupt/High bandwidth isochronous IN Underflow Error Interrupt" "Not sent/Not occurred,Sent/Occurred"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " RXSTPI/UNDERFI_set/clr ,Received SETUP Interrupt/Underflow Interrupt" "No effect/Not occurred,New SETUP packet/Occurred"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXOUTI_set/clr ,Received OUT Data Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " TXINI_set/clr ,Transmitted IN Data Interrupt" "Not ready,Ready"
|
|
wgroup.long (0x114+0x60)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTIFR5,Device Endpoint 5 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of Busy Banks Interrupt Set" "Not set,UOTGHS_DEVEPTISR5 set"
|
|
group.long (0x114+0x90)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTIMR5,Device Endpoint 5 Mask Register"
|
|
setclrfld.long 0x00 19. 0x30 19. 0x60 19. " STALLRQ_set/clr ,STALL Request" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset Data Toggle" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " NYETDIS_set/clr ,NYET Token Disable" "Masked,Not masked"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " EPDISHDMA_set/clr ,Endpoint Interrupts Disable HDMA Request" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 14. " FIFOCON ,FIFO Control" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN Bank" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_set/clr ,Number of Busy Banks Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 10. 0x30 10. 0x60 10. " ERRORTRANSE_set/clr ,Transaction Error Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x30 9. 0x60 9. " DATAXE_set/clr ,DataX Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. 0x30 8. 0x60 8. " MDATAE_set/clr ,MData Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETE_set/clr ,Short Packet Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " STALLEDE/CRCERRE_set/clr ,STALLed Interrupt/CRC Error Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFE_set/clr ,Overflow Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKINE/HBISOFLUSHE_set/clr ,NAKed IN Interrupt/High Bandwidth Isochronous IN Flush Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " NAKOUTE/HBISOINERRE_set/clr ,NAKed OUT Interrupt/High Bandwidth Isochronous IN Error Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " RXSTPE/UNDERFE_set/clr ,Received SETUP Interrupt/Underflow Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " RXOUTE_set/clr ,Received OUT Data Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " TXINE_set/clr ,Transmitted IN Data Interrupt" "Masked,Not masked"
|
|
wgroup.long (0x114+0x120)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTIDR5,Device Endpoint 5 Disable Register"
|
|
bitfld.long 0x00 14. " FIFOCONC ,FIFO Control Clear" "Not clear,Clear"
|
|
wgroup.long (0x114+0xB0)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTIER5,Device Endpoint 5 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDTS ,Reset Data Toggle Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 13. " KILLBKS ,Kill IN Bank" "No effect,Enabled"
|
|
tree.end
|
|
tree "Endpoint 6"
|
|
group.long 0x118++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTCFG6,Device Endpoint 6 Configuration Register"
|
|
bitfld.long 0x00 13.--14. " NBTRANS ,Number of transaction per microframe for isochronous endpoint" ",1,2,3"
|
|
bitfld.long 0x00 11.--12. " EPTYPE ,Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 9. " AUTOSW ,Automatic Switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EPDIR ,Endpoint Direction" "Out,In"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " EPSIZE ,Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " EPBK ,Endpoint Banks" "Single-bank,Double-bank,Triple-bank,?..."
|
|
newline
|
|
bitfld.long 0x00 1. " ALLOC ,Endpoint Memory Allocate" "Not allocated,Allocated"
|
|
group.long (0x118+0x30)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTISR6,Device Endpoint 6 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte Count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK Status" "Uncorrect,Correct"
|
|
newline
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control Direction" "Out,In"
|
|
bitfld.long 0x00 16. " RWALL ,Read-write Allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current Bank" "Bank0,Bank1,Bank2,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of Busy Banks" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10. " ERRORTRANS ,High-bandwidth isochronous OUT endpoint transaction error Interrupt" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data Toggle Sequence" "Data0,Data1,Data2,MData"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_set/clr ,Short Packet Interrupt" "Not received,Received"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " STALLEDI/CRCERRI_set/clr ,STALLed Interrupt/CRC Error Interrupt" "Not sent/Not detected,Sent/Detected"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_set/clr ,Overflow Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKINI/HBISOFLUSHI_set/clr ,NAKed IN Interrupt/High Bandwidth Isochronous IN Flush Interrupt" "Not sent/Not detected,Sent/Detected"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " NAKOUTI/HBISOINERRI_set/clr ,NAKed OUT Interrupt/High bandwidth isochronous IN Underflow Error Interrupt" "Not sent/Not occurred,Sent/Occurred"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " RXSTPI/UNDERFI_set/clr ,Received SETUP Interrupt/Underflow Interrupt" "No effect/Not occurred,New SETUP packet/Occurred"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXOUTI_set/clr ,Received OUT Data Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " TXINI_set/clr ,Transmitted IN Data Interrupt" "Not ready,Ready"
|
|
wgroup.long (0x118+0x60)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTIFR6,Device Endpoint 6 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of Busy Banks Interrupt Set" "Not set,UOTGHS_DEVEPTISR6 set"
|
|
group.long (0x118+0x90)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTIMR6,Device Endpoint 6 Mask Register"
|
|
setclrfld.long 0x00 19. 0x30 19. 0x60 19. " STALLRQ_set/clr ,STALL Request" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset Data Toggle" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " NYETDIS_set/clr ,NYET Token Disable" "Masked,Not masked"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " EPDISHDMA_set/clr ,Endpoint Interrupts Disable HDMA Request" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 14. " FIFOCON ,FIFO Control" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN Bank" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_set/clr ,Number of Busy Banks Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 10. 0x30 10. 0x60 10. " ERRORTRANSE_set/clr ,Transaction Error Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x30 9. 0x60 9. " DATAXE_set/clr ,DataX Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. 0x30 8. 0x60 8. " MDATAE_set/clr ,MData Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETE_set/clr ,Short Packet Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " STALLEDE/CRCERRE_set/clr ,STALLed Interrupt/CRC Error Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFE_set/clr ,Overflow Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKINE/HBISOFLUSHE_set/clr ,NAKed IN Interrupt/High Bandwidth Isochronous IN Flush Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " NAKOUTE/HBISOINERRE_set/clr ,NAKed OUT Interrupt/High Bandwidth Isochronous IN Error Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " RXSTPE/UNDERFE_set/clr ,Received SETUP Interrupt/Underflow Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " RXOUTE_set/clr ,Received OUT Data Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " TXINE_set/clr ,Transmitted IN Data Interrupt" "Masked,Not masked"
|
|
wgroup.long (0x118+0x120)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTIDR6,Device Endpoint 6 Disable Register"
|
|
bitfld.long 0x00 14. " FIFOCONC ,FIFO Control Clear" "Not clear,Clear"
|
|
wgroup.long (0x118+0xB0)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTIER6,Device Endpoint 6 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDTS ,Reset Data Toggle Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 13. " KILLBKS ,Kill IN Bank" "No effect,Enabled"
|
|
tree.end
|
|
tree "Endpoint 7"
|
|
group.long 0x11C++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTCFG7,Device Endpoint 7 Configuration Register"
|
|
bitfld.long 0x00 13.--14. " NBTRANS ,Number of transaction per microframe for isochronous endpoint" ",1,2,3"
|
|
bitfld.long 0x00 11.--12. " EPTYPE ,Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 9. " AUTOSW ,Automatic Switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EPDIR ,Endpoint Direction" "Out,In"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " EPSIZE ,Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " EPBK ,Endpoint Banks" "Single-bank,Double-bank,Triple-bank,?..."
|
|
newline
|
|
bitfld.long 0x00 1. " ALLOC ,Endpoint Memory Allocate" "Not allocated,Allocated"
|
|
group.long (0x11C+0x30)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTISR7,Device Endpoint 7 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte Count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK Status" "Uncorrect,Correct"
|
|
newline
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control Direction" "Out,In"
|
|
bitfld.long 0x00 16. " RWALL ,Read-write Allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current Bank" "Bank0,Bank1,Bank2,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of Busy Banks" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10. " ERRORTRANS ,High-bandwidth isochronous OUT endpoint transaction error Interrupt" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data Toggle Sequence" "Data0,Data1,Data2,MData"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_set/clr ,Short Packet Interrupt" "Not received,Received"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " STALLEDI/CRCERRI_set/clr ,STALLed Interrupt/CRC Error Interrupt" "Not sent/Not detected,Sent/Detected"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_set/clr ,Overflow Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKINI/HBISOFLUSHI_set/clr ,NAKed IN Interrupt/High Bandwidth Isochronous IN Flush Interrupt" "Not sent/Not detected,Sent/Detected"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " NAKOUTI/HBISOINERRI_set/clr ,NAKed OUT Interrupt/High bandwidth isochronous IN Underflow Error Interrupt" "Not sent/Not occurred,Sent/Occurred"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " RXSTPI/UNDERFI_set/clr ,Received SETUP Interrupt/Underflow Interrupt" "No effect/Not occurred,New SETUP packet/Occurred"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXOUTI_set/clr ,Received OUT Data Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " TXINI_set/clr ,Transmitted IN Data Interrupt" "Not ready,Ready"
|
|
wgroup.long (0x11C+0x60)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTIFR7,Device Endpoint 7 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of Busy Banks Interrupt Set" "Not set,UOTGHS_DEVEPTISR7 set"
|
|
group.long (0x11C+0x90)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTIMR7,Device Endpoint 7 Mask Register"
|
|
setclrfld.long 0x00 19. 0x30 19. 0x60 19. " STALLRQ_set/clr ,STALL Request" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset Data Toggle" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " NYETDIS_set/clr ,NYET Token Disable" "Masked,Not masked"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " EPDISHDMA_set/clr ,Endpoint Interrupts Disable HDMA Request" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 14. " FIFOCON ,FIFO Control" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN Bank" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_set/clr ,Number of Busy Banks Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 10. 0x30 10. 0x60 10. " ERRORTRANSE_set/clr ,Transaction Error Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x30 9. 0x60 9. " DATAXE_set/clr ,DataX Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. 0x30 8. 0x60 8. " MDATAE_set/clr ,MData Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETE_set/clr ,Short Packet Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " STALLEDE/CRCERRE_set/clr ,STALLed Interrupt/CRC Error Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFE_set/clr ,Overflow Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKINE/HBISOFLUSHE_set/clr ,NAKed IN Interrupt/High Bandwidth Isochronous IN Flush Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " NAKOUTE/HBISOINERRE_set/clr ,NAKed OUT Interrupt/High Bandwidth Isochronous IN Error Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " RXSTPE/UNDERFE_set/clr ,Received SETUP Interrupt/Underflow Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " RXOUTE_set/clr ,Received OUT Data Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " TXINE_set/clr ,Transmitted IN Data Interrupt" "Masked,Not masked"
|
|
wgroup.long (0x11C+0x120)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTIDR7,Device Endpoint 7 Disable Register"
|
|
bitfld.long 0x00 14. " FIFOCONC ,FIFO Control Clear" "Not clear,Clear"
|
|
wgroup.long (0x11C+0xB0)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTIER7,Device Endpoint 7 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDTS ,Reset Data Toggle Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 13. " KILLBKS ,Kill IN Bank" "No effect,Enabled"
|
|
tree.end
|
|
tree "Endpoint 8"
|
|
group.long 0x120++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTCFG8,Device Endpoint 8 Configuration Register"
|
|
bitfld.long 0x00 13.--14. " NBTRANS ,Number of transaction per microframe for isochronous endpoint" ",1,2,3"
|
|
bitfld.long 0x00 11.--12. " EPTYPE ,Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 9. " AUTOSW ,Automatic Switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EPDIR ,Endpoint Direction" "Out,In"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " EPSIZE ,Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " EPBK ,Endpoint Banks" "Single-bank,Double-bank,Triple-bank,?..."
|
|
newline
|
|
bitfld.long 0x00 1. " ALLOC ,Endpoint Memory Allocate" "Not allocated,Allocated"
|
|
group.long (0x120+0x30)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTISR8,Device Endpoint 8 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte Count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK Status" "Uncorrect,Correct"
|
|
newline
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control Direction" "Out,In"
|
|
bitfld.long 0x00 16. " RWALL ,Read-write Allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current Bank" "Bank0,Bank1,Bank2,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of Busy Banks" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10. " ERRORTRANS ,High-bandwidth isochronous OUT endpoint transaction error Interrupt" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data Toggle Sequence" "Data0,Data1,Data2,MData"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_set/clr ,Short Packet Interrupt" "Not received,Received"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " STALLEDI/CRCERRI_set/clr ,STALLed Interrupt/CRC Error Interrupt" "Not sent/Not detected,Sent/Detected"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_set/clr ,Overflow Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKINI/HBISOFLUSHI_set/clr ,NAKed IN Interrupt/High Bandwidth Isochronous IN Flush Interrupt" "Not sent/Not detected,Sent/Detected"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " NAKOUTI/HBISOINERRI_set/clr ,NAKed OUT Interrupt/High bandwidth isochronous IN Underflow Error Interrupt" "Not sent/Not occurred,Sent/Occurred"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " RXSTPI/UNDERFI_set/clr ,Received SETUP Interrupt/Underflow Interrupt" "No effect/Not occurred,New SETUP packet/Occurred"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXOUTI_set/clr ,Received OUT Data Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " TXINI_set/clr ,Transmitted IN Data Interrupt" "Not ready,Ready"
|
|
wgroup.long (0x120+0x60)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTIFR8,Device Endpoint 8 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of Busy Banks Interrupt Set" "Not set,UOTGHS_DEVEPTISR8 set"
|
|
group.long (0x120+0x90)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTIMR8,Device Endpoint 8 Mask Register"
|
|
setclrfld.long 0x00 19. 0x30 19. 0x60 19. " STALLRQ_set/clr ,STALL Request" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset Data Toggle" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " NYETDIS_set/clr ,NYET Token Disable" "Masked,Not masked"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " EPDISHDMA_set/clr ,Endpoint Interrupts Disable HDMA Request" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 14. " FIFOCON ,FIFO Control" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN Bank" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_set/clr ,Number of Busy Banks Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 10. 0x30 10. 0x60 10. " ERRORTRANSE_set/clr ,Transaction Error Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x30 9. 0x60 9. " DATAXE_set/clr ,DataX Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. 0x30 8. 0x60 8. " MDATAE_set/clr ,MData Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETE_set/clr ,Short Packet Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " STALLEDE/CRCERRE_set/clr ,STALLed Interrupt/CRC Error Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFE_set/clr ,Overflow Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKINE/HBISOFLUSHE_set/clr ,NAKed IN Interrupt/High Bandwidth Isochronous IN Flush Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " NAKOUTE/HBISOINERRE_set/clr ,NAKed OUT Interrupt/High Bandwidth Isochronous IN Error Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " RXSTPE/UNDERFE_set/clr ,Received SETUP Interrupt/Underflow Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " RXOUTE_set/clr ,Received OUT Data Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " TXINE_set/clr ,Transmitted IN Data Interrupt" "Masked,Not masked"
|
|
wgroup.long (0x120+0x120)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTIDR8,Device Endpoint 8 Disable Register"
|
|
bitfld.long 0x00 14. " FIFOCONC ,FIFO Control Clear" "Not clear,Clear"
|
|
wgroup.long (0x120+0xB0)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTIER8,Device Endpoint 8 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDTS ,Reset Data Toggle Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 13. " KILLBKS ,Kill IN Bank" "No effect,Enabled"
|
|
tree.end
|
|
tree "Endpoint 9"
|
|
group.long 0x124++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTCFG9,Device Endpoint 9 Configuration Register"
|
|
bitfld.long 0x00 13.--14. " NBTRANS ,Number of transaction per microframe for isochronous endpoint" ",1,2,3"
|
|
bitfld.long 0x00 11.--12. " EPTYPE ,Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 9. " AUTOSW ,Automatic Switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EPDIR ,Endpoint Direction" "Out,In"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " EPSIZE ,Endpoint Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " EPBK ,Endpoint Banks" "Single-bank,Double-bank,Triple-bank,?..."
|
|
newline
|
|
bitfld.long 0x00 1. " ALLOC ,Endpoint Memory Allocate" "Not allocated,Allocated"
|
|
group.long (0x124+0x30)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTISR9,Device Endpoint 9 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte Count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK Status" "Uncorrect,Correct"
|
|
newline
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control Direction" "Out,In"
|
|
bitfld.long 0x00 16. " RWALL ,Read-write Allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current Bank" "Bank0,Bank1,Bank2,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of Busy Banks" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 10. " ERRORTRANS ,High-bandwidth isochronous OUT endpoint transaction error Interrupt" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data Toggle Sequence" "Data0,Data1,Data2,MData"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_set/clr ,Short Packet Interrupt" "Not received,Received"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " STALLEDI/CRCERRI_set/clr ,STALLed Interrupt/CRC Error Interrupt" "Not sent/Not detected,Sent/Detected"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_set/clr ,Overflow Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKINI/HBISOFLUSHI_set/clr ,NAKed IN Interrupt/High Bandwidth Isochronous IN Flush Interrupt" "Not sent/Not detected,Sent/Detected"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " NAKOUTI/HBISOINERRI_set/clr ,NAKed OUT Interrupt/High bandwidth isochronous IN Underflow Error Interrupt" "Not sent/Not occurred,Sent/Occurred"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " RXSTPI/UNDERFI_set/clr ,Received SETUP Interrupt/Underflow Interrupt" "No effect/Not occurred,New SETUP packet/Occurred"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXOUTI_set/clr ,Received OUT Data Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " TXINI_set/clr ,Transmitted IN Data Interrupt" "Not ready,Ready"
|
|
wgroup.long (0x124+0x60)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTIFR9,Device Endpoint 9 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of Busy Banks Interrupt Set" "Not set,UOTGHS_DEVEPTISR9 set"
|
|
group.long (0x124+0x90)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTIMR9,Device Endpoint 9 Mask Register"
|
|
setclrfld.long 0x00 19. 0x30 19. 0x60 19. " STALLRQ_set/clr ,STALL Request" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset Data Toggle" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " NYETDIS_set/clr ,NYET Token Disable" "Masked,Not masked"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " EPDISHDMA_set/clr ,Endpoint Interrupts Disable HDMA Request" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 14. " FIFOCON ,FIFO Control" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN Bank" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_set/clr ,Number of Busy Banks Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 10. 0x30 10. 0x60 10. " ERRORTRANSE_set/clr ,Transaction Error Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x30 9. 0x60 9. " DATAXE_set/clr ,DataX Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. 0x30 8. 0x60 8. " MDATAE_set/clr ,MData Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETE_set/clr ,Short Packet Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " STALLEDE/CRCERRE_set/clr ,STALLed Interrupt/CRC Error Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFE_set/clr ,Overflow Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKINE/HBISOFLUSHE_set/clr ,NAKed IN Interrupt/High Bandwidth Isochronous IN Flush Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " NAKOUTE/HBISOINERRE_set/clr ,NAKed OUT Interrupt/High Bandwidth Isochronous IN Error Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " RXSTPE/UNDERFE_set/clr ,Received SETUP Interrupt/Underflow Interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " RXOUTE_set/clr ,Received OUT Data Interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " TXINE_set/clr ,Transmitted IN Data Interrupt" "Masked,Not masked"
|
|
wgroup.long (0x124+0x120)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTIDR9,Device Endpoint 9 Disable Register"
|
|
bitfld.long 0x00 14. " FIFOCONC ,FIFO Control Clear" "Not clear,Clear"
|
|
wgroup.long (0x124+0xB0)++0x3
|
|
line.long 0x00 "UOTGHS_DEVEPTIER9,Device Endpoint 9 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDTS ,Reset Data Toggle Enable" "No effect,Enabled"
|
|
bitfld.long 0x00 13. " KILLBKS ,Kill IN Bank" "No effect,Enabled"
|
|
tree.end
|
|
width 23.
|
|
tree "Channel 1"
|
|
group.long 0x310++0x0F
|
|
line.long 0x00 "UOTGHS_DEVDMANXTDSC1,Device DMA Channel 1 Next Descriptor Address Register"
|
|
line.long 0x04 "UOTGHS_DEVDMAADDRESS1,Device DMA Channel 1 Address Register"
|
|
line.long 0x08 "UOTGHS_DEVDMACONTROL1,Device DMA Channel 1 Control Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " BUFF_LENGTH ,Buffer Byte Length"
|
|
bitfld.long 0x08 7. " BURST_LCK ,Burst Lock Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 6. " DESC_LD_IT ,Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " END_BUFFIT ,End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 4. " END_TR_IT ,End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " END_B_EN ,End of Buffer Enable Control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 2. " END_TR_EN ,End of Transfer Enable Control" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " LDNXT_DSC ,Load Next Channel Transfer Descriptor Enable Command" "Not loaded,Loaded"
|
|
newline
|
|
bitfld.long 0x08 0. " CHANN_ENB ,Channel Enable Command" "Disabled,Enabled"
|
|
line.long 0x0C "UOTGHS_DEVDMASTATUS1,Device DMA Channel 1 Status Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " BUFF_COUNT ,Buffer Byte Count"
|
|
bitfld.long 0x0c 6. " DESC_LDST ,Descriptor Loaded Status" "No effect,Cleared"
|
|
newline
|
|
bitfld.long 0x0c 5. " END_BF_ST ,End of Channel Buffer Status" "No effect,Loaded"
|
|
bitfld.long 0x0c 4. " END_TR_ST ,End of Channel Transfer Status" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x0c 1. " CHANN_ACT ,Channel Active Status" "No active,Active"
|
|
bitfld.long 0x0c 0. " CHANN_ENB ,Channel Enable Status" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Channel 2"
|
|
group.long 0x320++0x0F
|
|
line.long 0x00 "UOTGHS_DEVDMANXTDSC2,Device DMA Channel 2 Next Descriptor Address Register"
|
|
line.long 0x04 "UOTGHS_DEVDMAADDRESS2,Device DMA Channel 2 Address Register"
|
|
line.long 0x08 "UOTGHS_DEVDMACONTROL2,Device DMA Channel 2 Control Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " BUFF_LENGTH ,Buffer Byte Length"
|
|
bitfld.long 0x08 7. " BURST_LCK ,Burst Lock Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 6. " DESC_LD_IT ,Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " END_BUFFIT ,End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 4. " END_TR_IT ,End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " END_B_EN ,End of Buffer Enable Control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 2. " END_TR_EN ,End of Transfer Enable Control" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " LDNXT_DSC ,Load Next Channel Transfer Descriptor Enable Command" "Not loaded,Loaded"
|
|
newline
|
|
bitfld.long 0x08 0. " CHANN_ENB ,Channel Enable Command" "Disabled,Enabled"
|
|
line.long 0x0C "UOTGHS_DEVDMASTATUS2,Device DMA Channel 2 Status Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " BUFF_COUNT ,Buffer Byte Count"
|
|
bitfld.long 0x0c 6. " DESC_LDST ,Descriptor Loaded Status" "No effect,Cleared"
|
|
newline
|
|
bitfld.long 0x0c 5. " END_BF_ST ,End of Channel Buffer Status" "No effect,Loaded"
|
|
bitfld.long 0x0c 4. " END_TR_ST ,End of Channel Transfer Status" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x0c 1. " CHANN_ACT ,Channel Active Status" "No active,Active"
|
|
bitfld.long 0x0c 0. " CHANN_ENB ,Channel Enable Status" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Channel 3"
|
|
group.long 0x330++0x0F
|
|
line.long 0x00 "UOTGHS_DEVDMANXTDSC3,Device DMA Channel 3 Next Descriptor Address Register"
|
|
line.long 0x04 "UOTGHS_DEVDMAADDRESS3,Device DMA Channel 3 Address Register"
|
|
line.long 0x08 "UOTGHS_DEVDMACONTROL3,Device DMA Channel 3 Control Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " BUFF_LENGTH ,Buffer Byte Length"
|
|
bitfld.long 0x08 7. " BURST_LCK ,Burst Lock Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 6. " DESC_LD_IT ,Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " END_BUFFIT ,End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 4. " END_TR_IT ,End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " END_B_EN ,End of Buffer Enable Control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 2. " END_TR_EN ,End of Transfer Enable Control" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " LDNXT_DSC ,Load Next Channel Transfer Descriptor Enable Command" "Not loaded,Loaded"
|
|
newline
|
|
bitfld.long 0x08 0. " CHANN_ENB ,Channel Enable Command" "Disabled,Enabled"
|
|
line.long 0x0C "UOTGHS_DEVDMASTATUS3,Device DMA Channel 3 Status Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " BUFF_COUNT ,Buffer Byte Count"
|
|
bitfld.long 0x0c 6. " DESC_LDST ,Descriptor Loaded Status" "No effect,Cleared"
|
|
newline
|
|
bitfld.long 0x0c 5. " END_BF_ST ,End of Channel Buffer Status" "No effect,Loaded"
|
|
bitfld.long 0x0c 4. " END_TR_ST ,End of Channel Transfer Status" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x0c 1. " CHANN_ACT ,Channel Active Status" "No active,Active"
|
|
bitfld.long 0x0c 0. " CHANN_ENB ,Channel Enable Status" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Channel 4"
|
|
group.long 0x340++0x0F
|
|
line.long 0x00 "UOTGHS_DEVDMANXTDSC4,Device DMA Channel 4 Next Descriptor Address Register"
|
|
line.long 0x04 "UOTGHS_DEVDMAADDRESS4,Device DMA Channel 4 Address Register"
|
|
line.long 0x08 "UOTGHS_DEVDMACONTROL4,Device DMA Channel 4 Control Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " BUFF_LENGTH ,Buffer Byte Length"
|
|
bitfld.long 0x08 7. " BURST_LCK ,Burst Lock Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 6. " DESC_LD_IT ,Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " END_BUFFIT ,End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 4. " END_TR_IT ,End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " END_B_EN ,End of Buffer Enable Control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 2. " END_TR_EN ,End of Transfer Enable Control" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " LDNXT_DSC ,Load Next Channel Transfer Descriptor Enable Command" "Not loaded,Loaded"
|
|
newline
|
|
bitfld.long 0x08 0. " CHANN_ENB ,Channel Enable Command" "Disabled,Enabled"
|
|
line.long 0x0C "UOTGHS_DEVDMASTATUS4,Device DMA Channel 4 Status Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " BUFF_COUNT ,Buffer Byte Count"
|
|
bitfld.long 0x0c 6. " DESC_LDST ,Descriptor Loaded Status" "No effect,Cleared"
|
|
newline
|
|
bitfld.long 0x0c 5. " END_BF_ST ,End of Channel Buffer Status" "No effect,Loaded"
|
|
bitfld.long 0x0c 4. " END_TR_ST ,End of Channel Transfer Status" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x0c 1. " CHANN_ACT ,Channel Active Status" "No active,Active"
|
|
bitfld.long 0x0c 0. " CHANN_ENB ,Channel Enable Status" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Channel 5"
|
|
group.long 0x350++0x0F
|
|
line.long 0x00 "UOTGHS_DEVDMANXTDSC5,Device DMA Channel 5 Next Descriptor Address Register"
|
|
line.long 0x04 "UOTGHS_DEVDMAADDRESS5,Device DMA Channel 5 Address Register"
|
|
line.long 0x08 "UOTGHS_DEVDMACONTROL5,Device DMA Channel 5 Control Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " BUFF_LENGTH ,Buffer Byte Length"
|
|
bitfld.long 0x08 7. " BURST_LCK ,Burst Lock Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 6. " DESC_LD_IT ,Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " END_BUFFIT ,End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 4. " END_TR_IT ,End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " END_B_EN ,End of Buffer Enable Control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 2. " END_TR_EN ,End of Transfer Enable Control" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " LDNXT_DSC ,Load Next Channel Transfer Descriptor Enable Command" "Not loaded,Loaded"
|
|
newline
|
|
bitfld.long 0x08 0. " CHANN_ENB ,Channel Enable Command" "Disabled,Enabled"
|
|
line.long 0x0C "UOTGHS_DEVDMASTATUS5,Device DMA Channel 5 Status Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " BUFF_COUNT ,Buffer Byte Count"
|
|
bitfld.long 0x0c 6. " DESC_LDST ,Descriptor Loaded Status" "No effect,Cleared"
|
|
newline
|
|
bitfld.long 0x0c 5. " END_BF_ST ,End of Channel Buffer Status" "No effect,Loaded"
|
|
bitfld.long 0x0c 4. " END_TR_ST ,End of Channel Transfer Status" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x0c 1. " CHANN_ACT ,Channel Active Status" "No active,Active"
|
|
bitfld.long 0x0c 0. " CHANN_ENB ,Channel Enable Status" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Channel 6"
|
|
group.long 0x360++0x0F
|
|
line.long 0x00 "UOTGHS_DEVDMANXTDSC6,Device DMA Channel 6 Next Descriptor Address Register"
|
|
line.long 0x04 "UOTGHS_DEVDMAADDRESS6,Device DMA Channel 6 Address Register"
|
|
line.long 0x08 "UOTGHS_DEVDMACONTROL6,Device DMA Channel 6 Control Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " BUFF_LENGTH ,Buffer Byte Length"
|
|
bitfld.long 0x08 7. " BURST_LCK ,Burst Lock Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 6. " DESC_LD_IT ,Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " END_BUFFIT ,End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 4. " END_TR_IT ,End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " END_B_EN ,End of Buffer Enable Control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 2. " END_TR_EN ,End of Transfer Enable Control" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " LDNXT_DSC ,Load Next Channel Transfer Descriptor Enable Command" "Not loaded,Loaded"
|
|
newline
|
|
bitfld.long 0x08 0. " CHANN_ENB ,Channel Enable Command" "Disabled,Enabled"
|
|
line.long 0x0C "UOTGHS_DEVDMASTATUS6,Device DMA Channel 6 Status Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " BUFF_COUNT ,Buffer Byte Count"
|
|
bitfld.long 0x0c 6. " DESC_LDST ,Descriptor Loaded Status" "No effect,Cleared"
|
|
newline
|
|
bitfld.long 0x0c 5. " END_BF_ST ,End of Channel Buffer Status" "No effect,Loaded"
|
|
bitfld.long 0x0c 4. " END_TR_ST ,End of Channel Transfer Status" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x0c 1. " CHANN_ACT ,Channel Active Status" "No active,Active"
|
|
bitfld.long 0x0c 0. " CHANN_ENB ,Channel Enable Status" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Channel 7"
|
|
group.long 0x370++0x0F
|
|
line.long 0x00 "UOTGHS_DEVDMANXTDSC7,Device DMA Channel 7 Next Descriptor Address Register"
|
|
line.long 0x04 "UOTGHS_DEVDMAADDRESS7,Device DMA Channel 7 Address Register"
|
|
line.long 0x08 "UOTGHS_DEVDMACONTROL7,Device DMA Channel 7 Control Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " BUFF_LENGTH ,Buffer Byte Length"
|
|
bitfld.long 0x08 7. " BURST_LCK ,Burst Lock Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 6. " DESC_LD_IT ,Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " END_BUFFIT ,End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 4. " END_TR_IT ,End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " END_B_EN ,End of Buffer Enable Control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 2. " END_TR_EN ,End of Transfer Enable Control" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " LDNXT_DSC ,Load Next Channel Transfer Descriptor Enable Command" "Not loaded,Loaded"
|
|
newline
|
|
bitfld.long 0x08 0. " CHANN_ENB ,Channel Enable Command" "Disabled,Enabled"
|
|
line.long 0x0C "UOTGHS_DEVDMASTATUS7,Device DMA Channel 7 Status Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " BUFF_COUNT ,Buffer Byte Count"
|
|
bitfld.long 0x0c 6. " DESC_LDST ,Descriptor Loaded Status" "No effect,Cleared"
|
|
newline
|
|
bitfld.long 0x0c 5. " END_BF_ST ,End of Channel Buffer Status" "No effect,Loaded"
|
|
bitfld.long 0x0c 4. " END_TR_ST ,End of Channel Transfer Status" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x0c 1. " CHANN_ACT ,Channel Active Status" "No active,Active"
|
|
bitfld.long 0x0c 0. " CHANN_ENB ,Channel Enable Status" "Disabled,Enabled"
|
|
tree.end
|
|
group.long 0x404++0x3
|
|
line.long 0x00 "UOTGHS_DEVISR,Device Global Interrupt Status Register"
|
|
bitfld.long 0x00 30. " DMA_6 ,DMA Channel 6 Interrupt" "Cleared,Triggered"
|
|
bitfld.long 0x00 29. " DMA_5 ,DMA Channel 5 Interrupt" "Cleared,Triggered"
|
|
newline
|
|
bitfld.long 0x00 28. " DMA_4 ,DMA Channel 4 Interrupt" "Cleared,Triggered"
|
|
bitfld.long 0x00 27. " DMA_3 ,DMA Channel 3 Interrupt" "Cleared,Triggered"
|
|
newline
|
|
bitfld.long 0x00 26. " DMA_2 ,DMA Channel 2 Interrupt" "Cleared,Triggered"
|
|
bitfld.long 0x00 25. " DMA_1 ,DMA Channel 1 Interrupt" "Cleared,Triggered"
|
|
newline
|
|
bitfld.long 0x00 17. " PEP_9 ,Endpoint 9 Interrupt" "Serviced,Triggered"
|
|
bitfld.long 0x00 16. " PEP_8 ,Endpoint 8 Interrupt" "Serviced,Triggered"
|
|
newline
|
|
bitfld.long 0x00 15. " PEP_7 ,Endpoint 7 Interrupt" "Serviced,Triggered"
|
|
bitfld.long 0x00 14. " PEP_6 ,Endpoint 6 Interrupt" "Serviced,Triggered"
|
|
newline
|
|
bitfld.long 0x00 13. " PEP_5 ,Endpoint 5 Interrupt" "Serviced,Triggered"
|
|
bitfld.long 0x00 12. " PEP_4 ,Endpoint 4 Interrupt" "Serviced,Triggered"
|
|
newline
|
|
bitfld.long 0x00 11. " PEP_3 ,Endpoint 3 Interrupt" "Serviced,Triggered"
|
|
bitfld.long 0x00 10. " PEP_2 ,Endpoint 2 Interrupt" "Serviced,Triggered"
|
|
newline
|
|
bitfld.long 0x00 9. " PEP_1 ,Endpoint 1 Interrupt" "Serviced,Triggered"
|
|
bitfld.long 0x00 8. " PEP_0 ,Endpoint 0 Interrupt" "Serviced,Triggered"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " HWUPI_set/clr ,Host Wake-Up Interrupt" "Not detected,Detected"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " HSOFI_set/clr ,Host Start of Frame Interrupt" "No effect,Issued"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " RXRSMI_set/clr ,Upstream Resume Received Interrupt" "Not received,Received"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " RSMEDI_set/clr ,Downstream Resume Sent Interrupt" "Not sent,sent"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " RSTI_set/clr ,USB Reset Sent Interrupt" "Not sent,sent"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " DDISCI_set/clr ,Device Disconnection Interrupt" "Not removed,Removed"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " DCONNI_set/clr ,Device Connection Interrupt" "Not connected,Connected"
|
|
tree.end
|
|
tree "Host Registers"
|
|
group.long 0x400++0x3
|
|
line.long 0x00 "UOTGHS_HSTCTRL,Host General Control Register"
|
|
bitfld.long 0x00 12.--13. " SPDCONF ,Mode Configuration" "Normal,Low-power,High-speed,Forced full-speed"
|
|
bitfld.long 0x00 10. " RESUME ,Send USB Resume" "No reset,reset"
|
|
newline
|
|
bitfld.long 0x00 9. " RESET ,Send USB Reset" "No effect,USB reset"
|
|
bitfld.long 0x00 8. " SOFE ,Start of Frame Generation Enable" "Disabled,Enabled"
|
|
group.long 0x404++0x3
|
|
line.long 0x00 "UOTGHS_HSTISR,Host Global Interrupt Status Register"
|
|
bitfld.long 0x00 30. " DMA_6 ,DMA Channel 6 Interrupt" "Cleared,Triggered"
|
|
bitfld.long 0x00 29. " DMA_5 ,DMA Channel 5 Interrupt" "Cleared,Triggered"
|
|
newline
|
|
bitfld.long 0x00 28. " DMA_4 ,DMA Channel 4 Interrupt" "Cleared,Triggered"
|
|
bitfld.long 0x00 27. " DMA_3 ,DMA Channel 3 Interrupt" "Cleared,Triggered"
|
|
newline
|
|
bitfld.long 0x00 26. " DMA_2 ,DMA Channel 2 Interrupt" "Cleared,Triggered"
|
|
bitfld.long 0x00 25. " DMA_1 ,DMA Channel 1 Interrupt" "Cleared,Triggered"
|
|
newline
|
|
bitfld.long 0x00 17. " PEP_9 ,Endpoint 9 Interrupt" "Serviced,Triggered"
|
|
bitfld.long 0x00 16. " PEP_8 ,Endpoint 8 Interrupt" "Serviced,Triggered"
|
|
newline
|
|
bitfld.long 0x00 15. " PEP_7 ,Endpoint 7 Interrupt" "Serviced,Triggered"
|
|
bitfld.long 0x00 14. " PEP_6 ,Endpoint 6 Interrupt" "Serviced,Triggered"
|
|
newline
|
|
bitfld.long 0x00 13. " PEP_5 ,Endpoint 5 Interrupt" "Serviced,Triggered"
|
|
bitfld.long 0x00 12. " PEP_4 ,Endpoint 4 Interrupt" "Serviced,Triggered"
|
|
newline
|
|
bitfld.long 0x00 11. " PEP_3 ,Endpoint 3 Interrupt" "Serviced,Triggered"
|
|
bitfld.long 0x00 10. " PEP_2 ,Endpoint 2 Interrupt" "Serviced,Triggered"
|
|
newline
|
|
bitfld.long 0x00 9. " PEP_1 ,Endpoint 1 Interrupt" "Serviced,Triggered"
|
|
bitfld.long 0x00 8. " PEP_0 ,Endpoint 0 Interrupt" "Serviced,Triggered"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " HWUPI_set/clr ,Host Wake-Up Interrupt" "Not detected,Detected"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " HSOFI_set/clr ,Host Start of Frame Interrupt" "No effect,Issued"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " RXRSMI_set/clr ,Upstream Resume Received Interrupt" "Not received,Received"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " RSMEDI_set/clr ,Downstream Resume Sent Interrupt" "Not sent,sent"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " RSTI_set/clr ,USB Reset Sent Interrupt" "Not sent,sent"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " DDISCI_set/clr ,Device Disconnection Interrupt" "Not removed,Removed"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " DCONNI_set/clr ,Device Connection Interrupt" "Not connected,Connected"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x00 "UOTGHS_HSTIFR,Host Global Interrupt Set Register"
|
|
bitfld.long 0x00 30. " DMA_6 ,DMA Channel 6 Interrupt Set" "Not set,Set"
|
|
bitfld.long 0x00 29. " DMA_5 ,DMA Channel 5 Interrupt Set" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 28. " DMA_4 ,DMA Channel 4 Interrupt Set" "Not set,Set"
|
|
bitfld.long 0x00 27. " DMA_3 ,DMA Channel 3 Interrupt Set" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 26. " DMA_2 ,DMA Channel 2 Interrupt Set" "Not set,Set"
|
|
bitfld.long 0x00 25. " DMA_1 ,DMA Channel 1 Interrupt Set" "Not set,Set"
|
|
group.long 0x410++0x3
|
|
line.long 0x00 "UOTGHS_HSTIMR,Host Global Interrupt Mask Register"
|
|
bitfld.long 0x00 30. " DMA_6 ,DMA Channel 6 Interrupt" "Cleared,Triggered"
|
|
bitfld.long 0x00 29. " DMA_5 ,DMA Channel 5 Interrupt" "Cleared,Triggered"
|
|
newline
|
|
bitfld.long 0x00 28. " DMA_4 ,DMA Channel 4 Interrupt" "Cleared,Triggered"
|
|
bitfld.long 0x00 27. " DMA_3 ,DMA Channel 3 Interrupt" "Cleared,Triggered"
|
|
newline
|
|
bitfld.long 0x00 26. " DMA_2 ,DMA Channel 2 Interrupt" "Cleared,Triggered"
|
|
bitfld.long 0x00 25. " DMA_1 ,DMA Channel 1 Interrupt" "Cleared,Triggered"
|
|
newline
|
|
bitfld.long 0x00 17. " PEP_9 ,Endpoint 9 Interrupt" "Serviced,Triggered"
|
|
bitfld.long 0x00 16. " PEP_8 ,Endpoint 8 Interrupt" "Serviced,Triggered"
|
|
newline
|
|
bitfld.long 0x00 15. " PEP_7 ,Endpoint 7 Interrupt" "Serviced,Triggered"
|
|
bitfld.long 0x00 14. " PEP_6 ,Endpoint 6 Interrupt" "Serviced,Triggered"
|
|
newline
|
|
bitfld.long 0x00 13. " PEP_5 ,Endpoint 5 Interrupt" "Serviced,Triggered"
|
|
bitfld.long 0x00 12. " PEP_4 ,Endpoint 4 Interrupt" "Serviced,Triggered"
|
|
newline
|
|
bitfld.long 0x00 11. " PEP_3 ,Endpoint 3 Interrupt" "Serviced,Triggered"
|
|
bitfld.long 0x00 10. " PEP_2 ,Endpoint 2 Interrupt" "Serviced,Triggered"
|
|
newline
|
|
bitfld.long 0x00 9. " PEP_1 ,Endpoint 1 Interrupt" "Serviced,Triggered"
|
|
bitfld.long 0x00 8. " PEP_0 ,Endpoint 0 Interrupt" "Serviced,Triggered"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " HWUPIE_set/clr ,Host Wake-Up Interrupt" "Not detected,Detected"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " HSOFIE_set/clr ,Host Start of Frame Interrupt" "No effect,Issued"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " RXRSMIE_set/clr ,Upstream Resume Received Interrupt" "Not received,Received"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " RSMEDIE_set/clr ,Downstream Resume Sent Interrupt" "Not sent,sent"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " RSTIE_set/clr ,USB Reset Sent Interrupt" "Not sent,sent"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " DDISCIE_set/clr ,Device Disconnection Interrupt" "Not removed,Removed"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " DCONNIE_set/clr ,Device Connection Interrupt" "Not connected,Connected"
|
|
group.long 0x41C++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIP,Host Pipe Register"
|
|
bitfld.long 0x00 24. " PRST8 ,Pipe 8 Reset" "No reset,Reset"
|
|
bitfld.long 0x00 23. " PRST7 ,Pipe 7 Reset" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 22. " PRST6 ,Pipe 6 Reset" "No reset,Reset"
|
|
bitfld.long 0x00 21. " PRST5 ,Pipe 5 Reset" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 20. " PRST4 ,Pipe 4 Reset" "No reset,Reset"
|
|
bitfld.long 0x00 19. " PRST3 ,Pipe 3 Reset" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 18. " PRST2 ,Pipe 2 Reset" "No reset,Reset"
|
|
bitfld.long 0x00 17. " PRST1 ,Pipe 1 Reset" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 16. " PRST0 ,Pipe 0 Reset" "No reset,Reset"
|
|
bitfld.long 0x00 8. " PEN8 ,Pipe 8 Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " PEN7 ,Pipe 7 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PEN6 ,Pipe 6 Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " PEN5 ,Pipe 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PEN4 ,Pipe 4 Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " PEN3 ,Pipe 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PEN2 ,Pipe 2 Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " PEN1 ,Pipe 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PEN0 ,Pipe 0 Enable" "Disabled,Enabled"
|
|
group.long 0x420++0xF
|
|
line.long 0x00 "UOTGHS_HSTFNUM,Host Frame Number Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " FLENHIGH ,Frame Length"
|
|
hexmask.long.word 0x00 3.--13. 1. " FNUM ,Frame Number"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " MFNUM ,Micro Frame Number" "0,1,2,3,4,5,6,7,?..."
|
|
line.long 0x04 "UOTGHS_HSTADDR1,Host Address 1 Register"
|
|
hexmask.long.byte 0x04 24.--30. 1. " HSTADDRP3 ,USB Host Address"
|
|
hexmask.long.byte 0x04 16.--22. 1. " HSTADDRP2 ,USB Host Address"
|
|
newline
|
|
hexmask.long.byte 0x04 8.--14. 1. " HSTADDRP1 ,USB Host Address"
|
|
hexmask.long.byte 0x04 0.--6. 1. " HSTADDRP0 ,USB Host Address"
|
|
line.long 0x08 "UOTGHS_HSTADDR2,Host Address 2 Register"
|
|
hexmask.long.byte 0x08 24.--30. 1. " HSTADDRP7 ,USB Host Address"
|
|
hexmask.long.byte 0x08 16.--22. 1. " HSTADDRP6 ,USB Host Address"
|
|
newline
|
|
hexmask.long.byte 0x08 8.--14. 1. " HSTADDRP5 ,USB Host Address"
|
|
hexmask.long.byte 0x08 0.--6. 1. " HSTADDRP4 ,USB Host Address"
|
|
line.long 0x0C "UOTGHS_HSTADDR3,Host Address 3 Register"
|
|
hexmask.long.byte 0x0C 8.--14. 1. " HSTADDRP9 ,USB Host Address"
|
|
hexmask.long.byte 0x0c 0.--6. 1. " HSTADDRP8 ,USB Host Address"
|
|
tree "Pipe 0"
|
|
group.long 0x500++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPCFG0,Host Pipe 0 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTFRQ/BINTERVAL ,Pipe Interrupt Request Frequency/bInterval parameter for the Bulk-Out/Ping transaction"
|
|
bitfld.long 0x00 20. " PINGEN ,Ping Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PEPNUM ,Pipe Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,?..."
|
|
bitfld.long 0x00 12.--13. " PTYPE ,Pipe Type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 10. " AUTOSW ,Automatic Switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " PTOKEN ,Pipe Token" "Setup,In,Out,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PSIZE ,Pipe Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " PBK ,Pipe Banks" "Single-bank,Double-bank,Triple-bank,?..."
|
|
newline
|
|
bitfld.long 0x00 1. " ALLOC ,Pipe Memory Allocate" "Free the pipe memory,Allocate pipe memory"
|
|
group.long (0x500+0x30)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPISR0,Host Pipe 0 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " PBYCT ,Pipe Byte Count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK Status" "Correct,Uncorrect"
|
|
newline
|
|
bitfld.long 0x00 16. " RWALL ,Read-write Allowed" "Not allowed,Allowed"
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current Bank" "Bank0,Bank1,Bank2,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of Busy Banks" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data Toggle Sequence" "Data0,Data1,?..."
|
|
newline
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_set/clr ,Short Packet Interrupt" "Not received,Received"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " RXSTALLEDI/CRCERRI_set/clr ,Received STALLed Interrupt/CRC Error Interrupt" "Not received/Not occurred,Received/Occurred"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_set/clr ,Overflow Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKEDI_set/clr ,NAKed IN Interrupt" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 3. " PERRI ,Pipe Error Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " TXSTPI/UNDERFI_set/clr ,Transmitted SETUP Interrupt/Underflow Interrupt" "Not occurred/Not occurred,Occurred/Occurred"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " TXOUTI_set/clr ,Transmitted OUT Data Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " RXINI_set/clr ,Received IN Data Interrupt" "Not occurred,Occurred"
|
|
wgroup.long (0x500+0x90)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPIFR0,Host Pipe 0 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of Busy Banks Set" "Not set,NBUSYBK set"
|
|
bitfld.long 0x00 3. " PERRIS ,Pipe Error Interrupt Set" "Not set,PERRI set"
|
|
group.long (0x500+0xC0)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPIMR0,Host Pipe 0 Mask Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset Data Toggle" "No reset,Reset"
|
|
setclrfld.long 0x00 17. 0x08 17. 0x04 17. " PFREEZE_set/clr ,Pipe Freeze" "Not freezed,Freezed"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x08 16. 0x04 16. " PDISHDMA_set/clr ,Pipe Interrupts Disable HDMA Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " FIFOCON ,FIFO Control" "Not occurred,Occurred"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x08 12. 0x04 12. " NBUSYBKE_set/clr ,Number of Busy Banks Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKETIE_set/clr ,Short Packet Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " RXSTALLDE/CRCERRE_set/clr ,Received STALLed Interrupt Enable/CRC Error Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFIE_set/clr ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKEDE_set/clr ,NAKed Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " PERRE_set/clr ,Pipe Error Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " TXSTPE/UNDERFIE_set/clr ,Transmitted SETUP Interrupt Enable/Underflow Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " TXOUTE_set/clr ,Transmitted OUT Data Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " RXINE_set/clr ,Received IN Data Interrupt Enable" "Disabled,Enabled"
|
|
wgroup.long (0x500+0xf0)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPIER0,Host Pipe 0 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDTS ,Reset Data Toggle Enable" "Disabled,Enabled"
|
|
wgroup.long (0x500+0x120)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPIDR0,Host Pipe 0 Disable Register"
|
|
bitfld.long 0x00 14. " FIFOCONC ,FIFO Control Disable" "No,Yes"
|
|
group.long (0x500+0x150)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPINRQ0,Host Pipe 0 IN Request Register"
|
|
bitfld.long 0x00 8. " INMODE ,IN Request Mode" "Not allowed,Allowed"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INRQ ,IN Request Number before Freeze"
|
|
group.long (0x500+0x180)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPERR0,Host Pipe 0 Error Register"
|
|
bitfld.long 0x00 5.--6. " COUNTER ,Error Counter" "0,1,2,3"
|
|
bitfld.long 0x00 4. " CRC16 ,CRC16 Error" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 3. " TIMEOUT ,Time-Out Error" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " PID ,PID Error" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 1. " DATAPID ,Data PID Error" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " DATATGL ,Data Toggle Error" "Not detected,Detected"
|
|
tree.end
|
|
tree "Pipe 1"
|
|
group.long 0x504++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPCFG1,Host Pipe 1 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTFRQ/BINTERVAL ,Pipe Interrupt Request Frequency/bInterval parameter for the Bulk-Out/Ping transaction"
|
|
bitfld.long 0x00 20. " PINGEN ,Ping Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PEPNUM ,Pipe Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,?..."
|
|
bitfld.long 0x00 12.--13. " PTYPE ,Pipe Type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 10. " AUTOSW ,Automatic Switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " PTOKEN ,Pipe Token" "Setup,In,Out,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PSIZE ,Pipe Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " PBK ,Pipe Banks" "Single-bank,Double-bank,Triple-bank,?..."
|
|
newline
|
|
bitfld.long 0x00 1. " ALLOC ,Pipe Memory Allocate" "Free the pipe memory,Allocate pipe memory"
|
|
group.long (0x504+0x30)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPISR1,Host Pipe 1 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " PBYCT ,Pipe Byte Count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK Status" "Correct,Uncorrect"
|
|
newline
|
|
bitfld.long 0x00 16. " RWALL ,Read-write Allowed" "Not allowed,Allowed"
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current Bank" "Bank0,Bank1,Bank2,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of Busy Banks" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data Toggle Sequence" "Data0,Data1,?..."
|
|
newline
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_set/clr ,Short Packet Interrupt" "Not received,Received"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " RXSTALLEDI/CRCERRI_set/clr ,Received STALLed Interrupt/CRC Error Interrupt" "Not received/Not occurred,Received/Occurred"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_set/clr ,Overflow Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKEDI_set/clr ,NAKed IN Interrupt" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 3. " PERRI ,Pipe Error Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " TXSTPI/UNDERFI_set/clr ,Transmitted SETUP Interrupt/Underflow Interrupt" "Not occurred/Not occurred,Occurred/Occurred"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " TXOUTI_set/clr ,Transmitted OUT Data Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " RXINI_set/clr ,Received IN Data Interrupt" "Not occurred,Occurred"
|
|
wgroup.long (0x504+0x90)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPIFR1,Host Pipe 1 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of Busy Banks Set" "Not set,NBUSYBK set"
|
|
bitfld.long 0x00 3. " PERRIS ,Pipe Error Interrupt Set" "Not set,PERRI set"
|
|
group.long (0x504+0xC0)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPIMR1,Host Pipe 1 Mask Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset Data Toggle" "No reset,Reset"
|
|
setclrfld.long 0x00 17. 0x08 17. 0x04 17. " PFREEZE_set/clr ,Pipe Freeze" "Not freezed,Freezed"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x08 16. 0x04 16. " PDISHDMA_set/clr ,Pipe Interrupts Disable HDMA Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " FIFOCON ,FIFO Control" "Not occurred,Occurred"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x08 12. 0x04 12. " NBUSYBKE_set/clr ,Number of Busy Banks Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKETIE_set/clr ,Short Packet Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " RXSTALLDE/CRCERRE_set/clr ,Received STALLed Interrupt Enable/CRC Error Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFIE_set/clr ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKEDE_set/clr ,NAKed Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " PERRE_set/clr ,Pipe Error Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " TXSTPE/UNDERFIE_set/clr ,Transmitted SETUP Interrupt Enable/Underflow Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " TXOUTE_set/clr ,Transmitted OUT Data Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " RXINE_set/clr ,Received IN Data Interrupt Enable" "Disabled,Enabled"
|
|
wgroup.long (0x504+0xf0)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPIER1,Host Pipe 1 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDTS ,Reset Data Toggle Enable" "Disabled,Enabled"
|
|
wgroup.long (0x504+0x120)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPIDR1,Host Pipe 1 Disable Register"
|
|
bitfld.long 0x00 14. " FIFOCONC ,FIFO Control Disable" "No,Yes"
|
|
group.long (0x504+0x150)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPINRQ1,Host Pipe 1 IN Request Register"
|
|
bitfld.long 0x00 8. " INMODE ,IN Request Mode" "Not allowed,Allowed"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INRQ ,IN Request Number before Freeze"
|
|
group.long (0x504+0x180)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPERR1,Host Pipe 1 Error Register"
|
|
bitfld.long 0x00 5.--6. " COUNTER ,Error Counter" "0,1,2,3"
|
|
bitfld.long 0x00 4. " CRC16 ,CRC16 Error" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 3. " TIMEOUT ,Time-Out Error" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " PID ,PID Error" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 1. " DATAPID ,Data PID Error" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " DATATGL ,Data Toggle Error" "Not detected,Detected"
|
|
tree.end
|
|
tree "Pipe 2"
|
|
group.long 0x508++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPCFG2,Host Pipe 2 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTFRQ/BINTERVAL ,Pipe Interrupt Request Frequency/bInterval parameter for the Bulk-Out/Ping transaction"
|
|
bitfld.long 0x00 20. " PINGEN ,Ping Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PEPNUM ,Pipe Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,?..."
|
|
bitfld.long 0x00 12.--13. " PTYPE ,Pipe Type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 10. " AUTOSW ,Automatic Switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " PTOKEN ,Pipe Token" "Setup,In,Out,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PSIZE ,Pipe Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " PBK ,Pipe Banks" "Single-bank,Double-bank,Triple-bank,?..."
|
|
newline
|
|
bitfld.long 0x00 1. " ALLOC ,Pipe Memory Allocate" "Free the pipe memory,Allocate pipe memory"
|
|
group.long (0x508+0x30)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPISR2,Host Pipe 2 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " PBYCT ,Pipe Byte Count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK Status" "Correct,Uncorrect"
|
|
newline
|
|
bitfld.long 0x00 16. " RWALL ,Read-write Allowed" "Not allowed,Allowed"
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current Bank" "Bank0,Bank1,Bank2,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of Busy Banks" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data Toggle Sequence" "Data0,Data1,?..."
|
|
newline
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_set/clr ,Short Packet Interrupt" "Not received,Received"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " RXSTALLEDI/CRCERRI_set/clr ,Received STALLed Interrupt/CRC Error Interrupt" "Not received/Not occurred,Received/Occurred"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_set/clr ,Overflow Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKEDI_set/clr ,NAKed IN Interrupt" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 3. " PERRI ,Pipe Error Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " TXSTPI/UNDERFI_set/clr ,Transmitted SETUP Interrupt/Underflow Interrupt" "Not occurred/Not occurred,Occurred/Occurred"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " TXOUTI_set/clr ,Transmitted OUT Data Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " RXINI_set/clr ,Received IN Data Interrupt" "Not occurred,Occurred"
|
|
wgroup.long (0x508+0x90)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPIFR2,Host Pipe 2 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of Busy Banks Set" "Not set,NBUSYBK set"
|
|
bitfld.long 0x00 3. " PERRIS ,Pipe Error Interrupt Set" "Not set,PERRI set"
|
|
group.long (0x508+0xC0)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPIMR2,Host Pipe 2 Mask Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset Data Toggle" "No reset,Reset"
|
|
setclrfld.long 0x00 17. 0x08 17. 0x04 17. " PFREEZE_set/clr ,Pipe Freeze" "Not freezed,Freezed"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x08 16. 0x04 16. " PDISHDMA_set/clr ,Pipe Interrupts Disable HDMA Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " FIFOCON ,FIFO Control" "Not occurred,Occurred"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x08 12. 0x04 12. " NBUSYBKE_set/clr ,Number of Busy Banks Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKETIE_set/clr ,Short Packet Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " RXSTALLDE/CRCERRE_set/clr ,Received STALLed Interrupt Enable/CRC Error Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFIE_set/clr ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKEDE_set/clr ,NAKed Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " PERRE_set/clr ,Pipe Error Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " TXSTPE/UNDERFIE_set/clr ,Transmitted SETUP Interrupt Enable/Underflow Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " TXOUTE_set/clr ,Transmitted OUT Data Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " RXINE_set/clr ,Received IN Data Interrupt Enable" "Disabled,Enabled"
|
|
wgroup.long (0x508+0xf0)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPIER2,Host Pipe 2 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDTS ,Reset Data Toggle Enable" "Disabled,Enabled"
|
|
wgroup.long (0x508+0x120)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPIDR2,Host Pipe 2 Disable Register"
|
|
bitfld.long 0x00 14. " FIFOCONC ,FIFO Control Disable" "No,Yes"
|
|
group.long (0x508+0x150)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPINRQ2,Host Pipe 2 IN Request Register"
|
|
bitfld.long 0x00 8. " INMODE ,IN Request Mode" "Not allowed,Allowed"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INRQ ,IN Request Number before Freeze"
|
|
group.long (0x508+0x180)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPERR2,Host Pipe 2 Error Register"
|
|
bitfld.long 0x00 5.--6. " COUNTER ,Error Counter" "0,1,2,3"
|
|
bitfld.long 0x00 4. " CRC16 ,CRC16 Error" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 3. " TIMEOUT ,Time-Out Error" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " PID ,PID Error" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 1. " DATAPID ,Data PID Error" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " DATATGL ,Data Toggle Error" "Not detected,Detected"
|
|
tree.end
|
|
tree "Pipe 3"
|
|
group.long 0x50C++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPCFG3,Host Pipe 3 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTFRQ/BINTERVAL ,Pipe Interrupt Request Frequency/bInterval parameter for the Bulk-Out/Ping transaction"
|
|
bitfld.long 0x00 20. " PINGEN ,Ping Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PEPNUM ,Pipe Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,?..."
|
|
bitfld.long 0x00 12.--13. " PTYPE ,Pipe Type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 10. " AUTOSW ,Automatic Switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " PTOKEN ,Pipe Token" "Setup,In,Out,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PSIZE ,Pipe Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " PBK ,Pipe Banks" "Single-bank,Double-bank,Triple-bank,?..."
|
|
newline
|
|
bitfld.long 0x00 1. " ALLOC ,Pipe Memory Allocate" "Free the pipe memory,Allocate pipe memory"
|
|
group.long (0x50C+0x30)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPISR3,Host Pipe 3 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " PBYCT ,Pipe Byte Count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK Status" "Correct,Uncorrect"
|
|
newline
|
|
bitfld.long 0x00 16. " RWALL ,Read-write Allowed" "Not allowed,Allowed"
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current Bank" "Bank0,Bank1,Bank2,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of Busy Banks" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data Toggle Sequence" "Data0,Data1,?..."
|
|
newline
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_set/clr ,Short Packet Interrupt" "Not received,Received"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " RXSTALLEDI/CRCERRI_set/clr ,Received STALLed Interrupt/CRC Error Interrupt" "Not received/Not occurred,Received/Occurred"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_set/clr ,Overflow Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKEDI_set/clr ,NAKed IN Interrupt" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 3. " PERRI ,Pipe Error Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " TXSTPI/UNDERFI_set/clr ,Transmitted SETUP Interrupt/Underflow Interrupt" "Not occurred/Not occurred,Occurred/Occurred"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " TXOUTI_set/clr ,Transmitted OUT Data Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " RXINI_set/clr ,Received IN Data Interrupt" "Not occurred,Occurred"
|
|
wgroup.long (0x50C+0x90)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPIFR3,Host Pipe 3 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of Busy Banks Set" "Not set,NBUSYBK set"
|
|
bitfld.long 0x00 3. " PERRIS ,Pipe Error Interrupt Set" "Not set,PERRI set"
|
|
group.long (0x50C+0xC0)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPIMR3,Host Pipe 3 Mask Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset Data Toggle" "No reset,Reset"
|
|
setclrfld.long 0x00 17. 0x08 17. 0x04 17. " PFREEZE_set/clr ,Pipe Freeze" "Not freezed,Freezed"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x08 16. 0x04 16. " PDISHDMA_set/clr ,Pipe Interrupts Disable HDMA Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " FIFOCON ,FIFO Control" "Not occurred,Occurred"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x08 12. 0x04 12. " NBUSYBKE_set/clr ,Number of Busy Banks Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKETIE_set/clr ,Short Packet Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " RXSTALLDE/CRCERRE_set/clr ,Received STALLed Interrupt Enable/CRC Error Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFIE_set/clr ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKEDE_set/clr ,NAKed Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " PERRE_set/clr ,Pipe Error Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " TXSTPE/UNDERFIE_set/clr ,Transmitted SETUP Interrupt Enable/Underflow Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " TXOUTE_set/clr ,Transmitted OUT Data Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " RXINE_set/clr ,Received IN Data Interrupt Enable" "Disabled,Enabled"
|
|
wgroup.long (0x50C+0xf0)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPIER3,Host Pipe 3 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDTS ,Reset Data Toggle Enable" "Disabled,Enabled"
|
|
wgroup.long (0x50C+0x120)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPIDR3,Host Pipe 3 Disable Register"
|
|
bitfld.long 0x00 14. " FIFOCONC ,FIFO Control Disable" "No,Yes"
|
|
group.long (0x50C+0x150)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPINRQ3,Host Pipe 3 IN Request Register"
|
|
bitfld.long 0x00 8. " INMODE ,IN Request Mode" "Not allowed,Allowed"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INRQ ,IN Request Number before Freeze"
|
|
group.long (0x50C+0x180)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPERR3,Host Pipe 3 Error Register"
|
|
bitfld.long 0x00 5.--6. " COUNTER ,Error Counter" "0,1,2,3"
|
|
bitfld.long 0x00 4. " CRC16 ,CRC16 Error" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 3. " TIMEOUT ,Time-Out Error" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " PID ,PID Error" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 1. " DATAPID ,Data PID Error" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " DATATGL ,Data Toggle Error" "Not detected,Detected"
|
|
tree.end
|
|
tree "Pipe 4"
|
|
group.long 0x510++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPCFG4,Host Pipe 4 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTFRQ/BINTERVAL ,Pipe Interrupt Request Frequency/bInterval parameter for the Bulk-Out/Ping transaction"
|
|
bitfld.long 0x00 20. " PINGEN ,Ping Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PEPNUM ,Pipe Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,?..."
|
|
bitfld.long 0x00 12.--13. " PTYPE ,Pipe Type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 10. " AUTOSW ,Automatic Switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " PTOKEN ,Pipe Token" "Setup,In,Out,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PSIZE ,Pipe Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " PBK ,Pipe Banks" "Single-bank,Double-bank,Triple-bank,?..."
|
|
newline
|
|
bitfld.long 0x00 1. " ALLOC ,Pipe Memory Allocate" "Free the pipe memory,Allocate pipe memory"
|
|
group.long (0x510+0x30)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPISR4,Host Pipe 4 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " PBYCT ,Pipe Byte Count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK Status" "Correct,Uncorrect"
|
|
newline
|
|
bitfld.long 0x00 16. " RWALL ,Read-write Allowed" "Not allowed,Allowed"
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current Bank" "Bank0,Bank1,Bank2,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of Busy Banks" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data Toggle Sequence" "Data0,Data1,?..."
|
|
newline
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_set/clr ,Short Packet Interrupt" "Not received,Received"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " RXSTALLEDI/CRCERRI_set/clr ,Received STALLed Interrupt/CRC Error Interrupt" "Not received/Not occurred,Received/Occurred"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_set/clr ,Overflow Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKEDI_set/clr ,NAKed IN Interrupt" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 3. " PERRI ,Pipe Error Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " TXSTPI/UNDERFI_set/clr ,Transmitted SETUP Interrupt/Underflow Interrupt" "Not occurred/Not occurred,Occurred/Occurred"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " TXOUTI_set/clr ,Transmitted OUT Data Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " RXINI_set/clr ,Received IN Data Interrupt" "Not occurred,Occurred"
|
|
wgroup.long (0x510+0x90)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPIFR4,Host Pipe 4 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of Busy Banks Set" "Not set,NBUSYBK set"
|
|
bitfld.long 0x00 3. " PERRIS ,Pipe Error Interrupt Set" "Not set,PERRI set"
|
|
group.long (0x510+0xC0)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPIMR4,Host Pipe 4 Mask Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset Data Toggle" "No reset,Reset"
|
|
setclrfld.long 0x00 17. 0x08 17. 0x04 17. " PFREEZE_set/clr ,Pipe Freeze" "Not freezed,Freezed"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x08 16. 0x04 16. " PDISHDMA_set/clr ,Pipe Interrupts Disable HDMA Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " FIFOCON ,FIFO Control" "Not occurred,Occurred"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x08 12. 0x04 12. " NBUSYBKE_set/clr ,Number of Busy Banks Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKETIE_set/clr ,Short Packet Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " RXSTALLDE/CRCERRE_set/clr ,Received STALLed Interrupt Enable/CRC Error Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFIE_set/clr ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKEDE_set/clr ,NAKed Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " PERRE_set/clr ,Pipe Error Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " TXSTPE/UNDERFIE_set/clr ,Transmitted SETUP Interrupt Enable/Underflow Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " TXOUTE_set/clr ,Transmitted OUT Data Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " RXINE_set/clr ,Received IN Data Interrupt Enable" "Disabled,Enabled"
|
|
wgroup.long (0x510+0xf0)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPIER4,Host Pipe 4 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDTS ,Reset Data Toggle Enable" "Disabled,Enabled"
|
|
wgroup.long (0x510+0x120)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPIDR4,Host Pipe 4 Disable Register"
|
|
bitfld.long 0x00 14. " FIFOCONC ,FIFO Control Disable" "No,Yes"
|
|
group.long (0x510+0x150)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPINRQ4,Host Pipe 4 IN Request Register"
|
|
bitfld.long 0x00 8. " INMODE ,IN Request Mode" "Not allowed,Allowed"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INRQ ,IN Request Number before Freeze"
|
|
group.long (0x510+0x180)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPERR4,Host Pipe 4 Error Register"
|
|
bitfld.long 0x00 5.--6. " COUNTER ,Error Counter" "0,1,2,3"
|
|
bitfld.long 0x00 4. " CRC16 ,CRC16 Error" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 3. " TIMEOUT ,Time-Out Error" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " PID ,PID Error" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 1. " DATAPID ,Data PID Error" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " DATATGL ,Data Toggle Error" "Not detected,Detected"
|
|
tree.end
|
|
tree "Pipe 5"
|
|
group.long 0x514++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPCFG5,Host Pipe 5 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTFRQ/BINTERVAL ,Pipe Interrupt Request Frequency/bInterval parameter for the Bulk-Out/Ping transaction"
|
|
bitfld.long 0x00 20. " PINGEN ,Ping Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PEPNUM ,Pipe Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,?..."
|
|
bitfld.long 0x00 12.--13. " PTYPE ,Pipe Type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 10. " AUTOSW ,Automatic Switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " PTOKEN ,Pipe Token" "Setup,In,Out,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PSIZE ,Pipe Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " PBK ,Pipe Banks" "Single-bank,Double-bank,Triple-bank,?..."
|
|
newline
|
|
bitfld.long 0x00 1. " ALLOC ,Pipe Memory Allocate" "Free the pipe memory,Allocate pipe memory"
|
|
group.long (0x514+0x30)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPISR5,Host Pipe 5 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " PBYCT ,Pipe Byte Count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK Status" "Correct,Uncorrect"
|
|
newline
|
|
bitfld.long 0x00 16. " RWALL ,Read-write Allowed" "Not allowed,Allowed"
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current Bank" "Bank0,Bank1,Bank2,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of Busy Banks" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data Toggle Sequence" "Data0,Data1,?..."
|
|
newline
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_set/clr ,Short Packet Interrupt" "Not received,Received"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " RXSTALLEDI/CRCERRI_set/clr ,Received STALLed Interrupt/CRC Error Interrupt" "Not received/Not occurred,Received/Occurred"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_set/clr ,Overflow Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKEDI_set/clr ,NAKed IN Interrupt" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 3. " PERRI ,Pipe Error Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " TXSTPI/UNDERFI_set/clr ,Transmitted SETUP Interrupt/Underflow Interrupt" "Not occurred/Not occurred,Occurred/Occurred"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " TXOUTI_set/clr ,Transmitted OUT Data Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " RXINI_set/clr ,Received IN Data Interrupt" "Not occurred,Occurred"
|
|
wgroup.long (0x514+0x90)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPIFR5,Host Pipe 5 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of Busy Banks Set" "Not set,NBUSYBK set"
|
|
bitfld.long 0x00 3. " PERRIS ,Pipe Error Interrupt Set" "Not set,PERRI set"
|
|
group.long (0x514+0xC0)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPIMR5,Host Pipe 5 Mask Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset Data Toggle" "No reset,Reset"
|
|
setclrfld.long 0x00 17. 0x08 17. 0x04 17. " PFREEZE_set/clr ,Pipe Freeze" "Not freezed,Freezed"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x08 16. 0x04 16. " PDISHDMA_set/clr ,Pipe Interrupts Disable HDMA Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " FIFOCON ,FIFO Control" "Not occurred,Occurred"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x08 12. 0x04 12. " NBUSYBKE_set/clr ,Number of Busy Banks Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKETIE_set/clr ,Short Packet Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " RXSTALLDE/CRCERRE_set/clr ,Received STALLed Interrupt Enable/CRC Error Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFIE_set/clr ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKEDE_set/clr ,NAKed Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " PERRE_set/clr ,Pipe Error Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " TXSTPE/UNDERFIE_set/clr ,Transmitted SETUP Interrupt Enable/Underflow Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " TXOUTE_set/clr ,Transmitted OUT Data Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " RXINE_set/clr ,Received IN Data Interrupt Enable" "Disabled,Enabled"
|
|
wgroup.long (0x514+0xf0)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPIER5,Host Pipe 5 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDTS ,Reset Data Toggle Enable" "Disabled,Enabled"
|
|
wgroup.long (0x514+0x120)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPIDR5,Host Pipe 5 Disable Register"
|
|
bitfld.long 0x00 14. " FIFOCONC ,FIFO Control Disable" "No,Yes"
|
|
group.long (0x514+0x150)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPINRQ5,Host Pipe 5 IN Request Register"
|
|
bitfld.long 0x00 8. " INMODE ,IN Request Mode" "Not allowed,Allowed"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INRQ ,IN Request Number before Freeze"
|
|
group.long (0x514+0x180)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPERR5,Host Pipe 5 Error Register"
|
|
bitfld.long 0x00 5.--6. " COUNTER ,Error Counter" "0,1,2,3"
|
|
bitfld.long 0x00 4. " CRC16 ,CRC16 Error" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 3. " TIMEOUT ,Time-Out Error" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " PID ,PID Error" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 1. " DATAPID ,Data PID Error" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " DATATGL ,Data Toggle Error" "Not detected,Detected"
|
|
tree.end
|
|
tree "Pipe 6"
|
|
group.long 0x518++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPCFG6,Host Pipe 6 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTFRQ/BINTERVAL ,Pipe Interrupt Request Frequency/bInterval parameter for the Bulk-Out/Ping transaction"
|
|
bitfld.long 0x00 20. " PINGEN ,Ping Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PEPNUM ,Pipe Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,?..."
|
|
bitfld.long 0x00 12.--13. " PTYPE ,Pipe Type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 10. " AUTOSW ,Automatic Switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " PTOKEN ,Pipe Token" "Setup,In,Out,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PSIZE ,Pipe Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " PBK ,Pipe Banks" "Single-bank,Double-bank,Triple-bank,?..."
|
|
newline
|
|
bitfld.long 0x00 1. " ALLOC ,Pipe Memory Allocate" "Free the pipe memory,Allocate pipe memory"
|
|
group.long (0x518+0x30)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPISR6,Host Pipe 6 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " PBYCT ,Pipe Byte Count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK Status" "Correct,Uncorrect"
|
|
newline
|
|
bitfld.long 0x00 16. " RWALL ,Read-write Allowed" "Not allowed,Allowed"
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current Bank" "Bank0,Bank1,Bank2,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of Busy Banks" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data Toggle Sequence" "Data0,Data1,?..."
|
|
newline
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_set/clr ,Short Packet Interrupt" "Not received,Received"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " RXSTALLEDI/CRCERRI_set/clr ,Received STALLed Interrupt/CRC Error Interrupt" "Not received/Not occurred,Received/Occurred"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_set/clr ,Overflow Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKEDI_set/clr ,NAKed IN Interrupt" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 3. " PERRI ,Pipe Error Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " TXSTPI/UNDERFI_set/clr ,Transmitted SETUP Interrupt/Underflow Interrupt" "Not occurred/Not occurred,Occurred/Occurred"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " TXOUTI_set/clr ,Transmitted OUT Data Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " RXINI_set/clr ,Received IN Data Interrupt" "Not occurred,Occurred"
|
|
wgroup.long (0x518+0x90)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPIFR6,Host Pipe 6 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of Busy Banks Set" "Not set,NBUSYBK set"
|
|
bitfld.long 0x00 3. " PERRIS ,Pipe Error Interrupt Set" "Not set,PERRI set"
|
|
group.long (0x518+0xC0)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPIMR6,Host Pipe 6 Mask Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset Data Toggle" "No reset,Reset"
|
|
setclrfld.long 0x00 17. 0x08 17. 0x04 17. " PFREEZE_set/clr ,Pipe Freeze" "Not freezed,Freezed"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x08 16. 0x04 16. " PDISHDMA_set/clr ,Pipe Interrupts Disable HDMA Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " FIFOCON ,FIFO Control" "Not occurred,Occurred"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x08 12. 0x04 12. " NBUSYBKE_set/clr ,Number of Busy Banks Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKETIE_set/clr ,Short Packet Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " RXSTALLDE/CRCERRE_set/clr ,Received STALLed Interrupt Enable/CRC Error Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFIE_set/clr ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKEDE_set/clr ,NAKed Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " PERRE_set/clr ,Pipe Error Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " TXSTPE/UNDERFIE_set/clr ,Transmitted SETUP Interrupt Enable/Underflow Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " TXOUTE_set/clr ,Transmitted OUT Data Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " RXINE_set/clr ,Received IN Data Interrupt Enable" "Disabled,Enabled"
|
|
wgroup.long (0x518+0xf0)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPIER6,Host Pipe 6 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDTS ,Reset Data Toggle Enable" "Disabled,Enabled"
|
|
wgroup.long (0x518+0x120)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPIDR6,Host Pipe 6 Disable Register"
|
|
bitfld.long 0x00 14. " FIFOCONC ,FIFO Control Disable" "No,Yes"
|
|
group.long (0x518+0x150)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPINRQ6,Host Pipe 6 IN Request Register"
|
|
bitfld.long 0x00 8. " INMODE ,IN Request Mode" "Not allowed,Allowed"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INRQ ,IN Request Number before Freeze"
|
|
group.long (0x518+0x180)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPERR6,Host Pipe 6 Error Register"
|
|
bitfld.long 0x00 5.--6. " COUNTER ,Error Counter" "0,1,2,3"
|
|
bitfld.long 0x00 4. " CRC16 ,CRC16 Error" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 3. " TIMEOUT ,Time-Out Error" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " PID ,PID Error" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 1. " DATAPID ,Data PID Error" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " DATATGL ,Data Toggle Error" "Not detected,Detected"
|
|
tree.end
|
|
tree "Pipe 7"
|
|
group.long 0x51C++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPCFG7,Host Pipe 7 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTFRQ/BINTERVAL ,Pipe Interrupt Request Frequency/bInterval parameter for the Bulk-Out/Ping transaction"
|
|
bitfld.long 0x00 20. " PINGEN ,Ping Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PEPNUM ,Pipe Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,?..."
|
|
bitfld.long 0x00 12.--13. " PTYPE ,Pipe Type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 10. " AUTOSW ,Automatic Switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " PTOKEN ,Pipe Token" "Setup,In,Out,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PSIZE ,Pipe Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " PBK ,Pipe Banks" "Single-bank,Double-bank,Triple-bank,?..."
|
|
newline
|
|
bitfld.long 0x00 1. " ALLOC ,Pipe Memory Allocate" "Free the pipe memory,Allocate pipe memory"
|
|
group.long (0x51C+0x30)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPISR7,Host Pipe 7 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " PBYCT ,Pipe Byte Count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK Status" "Correct,Uncorrect"
|
|
newline
|
|
bitfld.long 0x00 16. " RWALL ,Read-write Allowed" "Not allowed,Allowed"
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current Bank" "Bank0,Bank1,Bank2,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of Busy Banks" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data Toggle Sequence" "Data0,Data1,?..."
|
|
newline
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_set/clr ,Short Packet Interrupt" "Not received,Received"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " RXSTALLEDI/CRCERRI_set/clr ,Received STALLed Interrupt/CRC Error Interrupt" "Not received/Not occurred,Received/Occurred"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_set/clr ,Overflow Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKEDI_set/clr ,NAKed IN Interrupt" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 3. " PERRI ,Pipe Error Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " TXSTPI/UNDERFI_set/clr ,Transmitted SETUP Interrupt/Underflow Interrupt" "Not occurred/Not occurred,Occurred/Occurred"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " TXOUTI_set/clr ,Transmitted OUT Data Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " RXINI_set/clr ,Received IN Data Interrupt" "Not occurred,Occurred"
|
|
wgroup.long (0x51C+0x90)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPIFR7,Host Pipe 7 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of Busy Banks Set" "Not set,NBUSYBK set"
|
|
bitfld.long 0x00 3. " PERRIS ,Pipe Error Interrupt Set" "Not set,PERRI set"
|
|
group.long (0x51C+0xC0)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPIMR7,Host Pipe 7 Mask Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset Data Toggle" "No reset,Reset"
|
|
setclrfld.long 0x00 17. 0x08 17. 0x04 17. " PFREEZE_set/clr ,Pipe Freeze" "Not freezed,Freezed"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x08 16. 0x04 16. " PDISHDMA_set/clr ,Pipe Interrupts Disable HDMA Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " FIFOCON ,FIFO Control" "Not occurred,Occurred"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x08 12. 0x04 12. " NBUSYBKE_set/clr ,Number of Busy Banks Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKETIE_set/clr ,Short Packet Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " RXSTALLDE/CRCERRE_set/clr ,Received STALLed Interrupt Enable/CRC Error Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFIE_set/clr ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKEDE_set/clr ,NAKed Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " PERRE_set/clr ,Pipe Error Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " TXSTPE/UNDERFIE_set/clr ,Transmitted SETUP Interrupt Enable/Underflow Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " TXOUTE_set/clr ,Transmitted OUT Data Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " RXINE_set/clr ,Received IN Data Interrupt Enable" "Disabled,Enabled"
|
|
wgroup.long (0x51C+0xf0)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPIER7,Host Pipe 7 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDTS ,Reset Data Toggle Enable" "Disabled,Enabled"
|
|
wgroup.long (0x51C+0x120)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPIDR7,Host Pipe 7 Disable Register"
|
|
bitfld.long 0x00 14. " FIFOCONC ,FIFO Control Disable" "No,Yes"
|
|
group.long (0x51C+0x150)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPINRQ7,Host Pipe 7 IN Request Register"
|
|
bitfld.long 0x00 8. " INMODE ,IN Request Mode" "Not allowed,Allowed"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INRQ ,IN Request Number before Freeze"
|
|
group.long (0x51C+0x180)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPERR7,Host Pipe 7 Error Register"
|
|
bitfld.long 0x00 5.--6. " COUNTER ,Error Counter" "0,1,2,3"
|
|
bitfld.long 0x00 4. " CRC16 ,CRC16 Error" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 3. " TIMEOUT ,Time-Out Error" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " PID ,PID Error" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 1. " DATAPID ,Data PID Error" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " DATATGL ,Data Toggle Error" "Not detected,Detected"
|
|
tree.end
|
|
tree "Pipe 8"
|
|
group.long 0x520++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPCFG8,Host Pipe 8 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTFRQ/BINTERVAL ,Pipe Interrupt Request Frequency/bInterval parameter for the Bulk-Out/Ping transaction"
|
|
bitfld.long 0x00 20. " PINGEN ,Ping Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PEPNUM ,Pipe Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,?..."
|
|
bitfld.long 0x00 12.--13. " PTYPE ,Pipe Type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 10. " AUTOSW ,Automatic Switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " PTOKEN ,Pipe Token" "Setup,In,Out,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PSIZE ,Pipe Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " PBK ,Pipe Banks" "Single-bank,Double-bank,Triple-bank,?..."
|
|
newline
|
|
bitfld.long 0x00 1. " ALLOC ,Pipe Memory Allocate" "Free the pipe memory,Allocate pipe memory"
|
|
group.long (0x520+0x30)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPISR8,Host Pipe 8 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " PBYCT ,Pipe Byte Count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK Status" "Correct,Uncorrect"
|
|
newline
|
|
bitfld.long 0x00 16. " RWALL ,Read-write Allowed" "Not allowed,Allowed"
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current Bank" "Bank0,Bank1,Bank2,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of Busy Banks" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data Toggle Sequence" "Data0,Data1,?..."
|
|
newline
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_set/clr ,Short Packet Interrupt" "Not received,Received"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " RXSTALLEDI/CRCERRI_set/clr ,Received STALLed Interrupt/CRC Error Interrupt" "Not received/Not occurred,Received/Occurred"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_set/clr ,Overflow Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKEDI_set/clr ,NAKed IN Interrupt" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 3. " PERRI ,Pipe Error Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " TXSTPI/UNDERFI_set/clr ,Transmitted SETUP Interrupt/Underflow Interrupt" "Not occurred/Not occurred,Occurred/Occurred"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " TXOUTI_set/clr ,Transmitted OUT Data Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " RXINI_set/clr ,Received IN Data Interrupt" "Not occurred,Occurred"
|
|
wgroup.long (0x520+0x90)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPIFR8,Host Pipe 8 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of Busy Banks Set" "Not set,NBUSYBK set"
|
|
bitfld.long 0x00 3. " PERRIS ,Pipe Error Interrupt Set" "Not set,PERRI set"
|
|
group.long (0x520+0xC0)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPIMR8,Host Pipe 8 Mask Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset Data Toggle" "No reset,Reset"
|
|
setclrfld.long 0x00 17. 0x08 17. 0x04 17. " PFREEZE_set/clr ,Pipe Freeze" "Not freezed,Freezed"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x08 16. 0x04 16. " PDISHDMA_set/clr ,Pipe Interrupts Disable HDMA Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " FIFOCON ,FIFO Control" "Not occurred,Occurred"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x08 12. 0x04 12. " NBUSYBKE_set/clr ,Number of Busy Banks Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKETIE_set/clr ,Short Packet Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " RXSTALLDE/CRCERRE_set/clr ,Received STALLed Interrupt Enable/CRC Error Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFIE_set/clr ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKEDE_set/clr ,NAKed Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " PERRE_set/clr ,Pipe Error Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " TXSTPE/UNDERFIE_set/clr ,Transmitted SETUP Interrupt Enable/Underflow Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " TXOUTE_set/clr ,Transmitted OUT Data Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " RXINE_set/clr ,Received IN Data Interrupt Enable" "Disabled,Enabled"
|
|
wgroup.long (0x520+0xf0)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPIER8,Host Pipe 8 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDTS ,Reset Data Toggle Enable" "Disabled,Enabled"
|
|
wgroup.long (0x520+0x120)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPIDR8,Host Pipe 8 Disable Register"
|
|
bitfld.long 0x00 14. " FIFOCONC ,FIFO Control Disable" "No,Yes"
|
|
group.long (0x520+0x150)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPINRQ8,Host Pipe 8 IN Request Register"
|
|
bitfld.long 0x00 8. " INMODE ,IN Request Mode" "Not allowed,Allowed"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INRQ ,IN Request Number before Freeze"
|
|
group.long (0x520+0x180)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPERR8,Host Pipe 8 Error Register"
|
|
bitfld.long 0x00 5.--6. " COUNTER ,Error Counter" "0,1,2,3"
|
|
bitfld.long 0x00 4. " CRC16 ,CRC16 Error" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 3. " TIMEOUT ,Time-Out Error" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " PID ,PID Error" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 1. " DATAPID ,Data PID Error" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " DATATGL ,Data Toggle Error" "Not detected,Detected"
|
|
tree.end
|
|
tree "Pipe 9"
|
|
group.long 0x524++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPCFG9,Host Pipe 9 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTFRQ/BINTERVAL ,Pipe Interrupt Request Frequency/bInterval parameter for the Bulk-Out/Ping transaction"
|
|
bitfld.long 0x00 20. " PINGEN ,Ping Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PEPNUM ,Pipe Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,?..."
|
|
bitfld.long 0x00 12.--13. " PTYPE ,Pipe Type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 10. " AUTOSW ,Automatic Switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " PTOKEN ,Pipe Token" "Setup,In,Out,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PSIZE ,Pipe Size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " PBK ,Pipe Banks" "Single-bank,Double-bank,Triple-bank,?..."
|
|
newline
|
|
bitfld.long 0x00 1. " ALLOC ,Pipe Memory Allocate" "Free the pipe memory,Allocate pipe memory"
|
|
group.long (0x524+0x30)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPISR9,Host Pipe 9 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " PBYCT ,Pipe Byte Count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK Status" "Correct,Uncorrect"
|
|
newline
|
|
bitfld.long 0x00 16. " RWALL ,Read-write Allowed" "Not allowed,Allowed"
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current Bank" "Bank0,Bank1,Bank2,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of Busy Banks" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data Toggle Sequence" "Data0,Data1,?..."
|
|
newline
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_set/clr ,Short Packet Interrupt" "Not received,Received"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " RXSTALLEDI/CRCERRI_set/clr ,Received STALLed Interrupt/CRC Error Interrupt" "Not received/Not occurred,Received/Occurred"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_set/clr ,Overflow Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKEDI_set/clr ,NAKed IN Interrupt" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 3. " PERRI ,Pipe Error Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " TXSTPI/UNDERFI_set/clr ,Transmitted SETUP Interrupt/Underflow Interrupt" "Not occurred/Not occurred,Occurred/Occurred"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " TXOUTI_set/clr ,Transmitted OUT Data Interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " RXINI_set/clr ,Received IN Data Interrupt" "Not occurred,Occurred"
|
|
wgroup.long (0x524+0x90)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPIFR9,Host Pipe 9 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of Busy Banks Set" "Not set,NBUSYBK set"
|
|
bitfld.long 0x00 3. " PERRIS ,Pipe Error Interrupt Set" "Not set,PERRI set"
|
|
group.long (0x524+0xC0)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPIMR9,Host Pipe 9 Mask Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset Data Toggle" "No reset,Reset"
|
|
setclrfld.long 0x00 17. 0x08 17. 0x04 17. " PFREEZE_set/clr ,Pipe Freeze" "Not freezed,Freezed"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x08 16. 0x04 16. " PDISHDMA_set/clr ,Pipe Interrupts Disable HDMA Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " FIFOCON ,FIFO Control" "Not occurred,Occurred"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x08 12. 0x04 12. " NBUSYBKE_set/clr ,Number of Busy Banks Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKETIE_set/clr ,Short Packet Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " RXSTALLDE/CRCERRE_set/clr ,Received STALLed Interrupt Enable/CRC Error Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFIE_set/clr ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKEDE_set/clr ,NAKed Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " PERRE_set/clr ,Pipe Error Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " TXSTPE/UNDERFIE_set/clr ,Transmitted SETUP Interrupt Enable/Underflow Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " TXOUTE_set/clr ,Transmitted OUT Data Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " RXINE_set/clr ,Received IN Data Interrupt Enable" "Disabled,Enabled"
|
|
wgroup.long (0x524+0xf0)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPIER9,Host Pipe 9 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDTS ,Reset Data Toggle Enable" "Disabled,Enabled"
|
|
wgroup.long (0x524+0x120)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPIDR9,Host Pipe 9 Disable Register"
|
|
bitfld.long 0x00 14. " FIFOCONC ,FIFO Control Disable" "No,Yes"
|
|
group.long (0x524+0x150)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPINRQ9,Host Pipe 9 IN Request Register"
|
|
bitfld.long 0x00 8. " INMODE ,IN Request Mode" "Not allowed,Allowed"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INRQ ,IN Request Number before Freeze"
|
|
group.long (0x524+0x180)++0x3
|
|
line.long 0x00 "UOTGHS_HSTPIPERR9,Host Pipe 9 Error Register"
|
|
bitfld.long 0x00 5.--6. " COUNTER ,Error Counter" "0,1,2,3"
|
|
bitfld.long 0x00 4. " CRC16 ,CRC16 Error" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 3. " TIMEOUT ,Time-Out Error" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " PID ,PID Error" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 1. " DATAPID ,Data PID Error" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " DATATGL ,Data Toggle Error" "Not detected,Detected"
|
|
tree.end
|
|
tree "Channel 1"
|
|
group.long 0x710++0xF
|
|
line.long 0x00 "UOTGHS_HSTDMANXTDSC1,Host DMA Channel 1 Next Descriptor Address Register"
|
|
line.long 0x04 "UOTGHS_HSTDMAADDRESS1,Host DMA Channel 1 Address Register"
|
|
line.long 0x08 "UOTGHS_HSTDMACONTROL1,Host DMA Channel 1 Control Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " BUFF_LENGTH ,Buffer Byte Length"
|
|
bitfld.long 0x08 7. " BURST_LCK ,Burst Lock Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 6. " DESC_LD_IT ,Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " END_BUFFIT ,End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 4. " END_TR_IT ,End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " END_B_EN ,End of Buffer Enable Control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 2. " END_TR_EN ,End of Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " LDNXT_DSC ,Load Next Channel Transfer Descriptor Enable Command" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 0. " CHANN_ENB ,Channel Enable Command" "Disabled,Enabled"
|
|
line.long 0x0C "UOTGHS__HSTDMASTATUS1,Host DMA Channel 1 Status Registe"
|
|
hexmask.long.word 0x0C 16.--31. 1. " BUFF_COUNT ,Buffer Byte Count"
|
|
bitfld.long 0x0C 6. " DESC_LDST ,Descriptor Loaded Status" "Not loaded,Loaded"
|
|
newline
|
|
bitfld.long 0x0C 5. " END_BF_ST ,End of Buffer Status" "Zero not reached,Zero reached"
|
|
bitfld.long 0x0C 4. " END_TR_ST ,End of Transfer Status" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x0C 1. " CHANN_ACT ,Channel Active Status" "Idle,Active"
|
|
bitfld.long 0x0C 0. " CHANN_ENB ,Channel Enable Status" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Channel 2"
|
|
group.long 0x720++0xF
|
|
line.long 0x00 "UOTGHS_HSTDMANXTDSC2,Host DMA Channel 2 Next Descriptor Address Register"
|
|
line.long 0x04 "UOTGHS_HSTDMAADDRESS2,Host DMA Channel 2 Address Register"
|
|
line.long 0x08 "UOTGHS_HSTDMACONTROL2,Host DMA Channel 2 Control Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " BUFF_LENGTH ,Buffer Byte Length"
|
|
bitfld.long 0x08 7. " BURST_LCK ,Burst Lock Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 6. " DESC_LD_IT ,Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " END_BUFFIT ,End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 4. " END_TR_IT ,End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " END_B_EN ,End of Buffer Enable Control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 2. " END_TR_EN ,End of Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " LDNXT_DSC ,Load Next Channel Transfer Descriptor Enable Command" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 0. " CHANN_ENB ,Channel Enable Command" "Disabled,Enabled"
|
|
line.long 0x0C "UOTGHS__HSTDMASTATUS2,Host DMA Channel 2 Status Registe"
|
|
hexmask.long.word 0x0C 16.--31. 1. " BUFF_COUNT ,Buffer Byte Count"
|
|
bitfld.long 0x0C 6. " DESC_LDST ,Descriptor Loaded Status" "Not loaded,Loaded"
|
|
newline
|
|
bitfld.long 0x0C 5. " END_BF_ST ,End of Buffer Status" "Zero not reached,Zero reached"
|
|
bitfld.long 0x0C 4. " END_TR_ST ,End of Transfer Status" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x0C 1. " CHANN_ACT ,Channel Active Status" "Idle,Active"
|
|
bitfld.long 0x0C 0. " CHANN_ENB ,Channel Enable Status" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Channel 3"
|
|
group.long 0x730++0xF
|
|
line.long 0x00 "UOTGHS_HSTDMANXTDSC3,Host DMA Channel 3 Next Descriptor Address Register"
|
|
line.long 0x04 "UOTGHS_HSTDMAADDRESS3,Host DMA Channel 3 Address Register"
|
|
line.long 0x08 "UOTGHS_HSTDMACONTROL3,Host DMA Channel 3 Control Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " BUFF_LENGTH ,Buffer Byte Length"
|
|
bitfld.long 0x08 7. " BURST_LCK ,Burst Lock Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 6. " DESC_LD_IT ,Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " END_BUFFIT ,End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 4. " END_TR_IT ,End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " END_B_EN ,End of Buffer Enable Control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 2. " END_TR_EN ,End of Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " LDNXT_DSC ,Load Next Channel Transfer Descriptor Enable Command" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 0. " CHANN_ENB ,Channel Enable Command" "Disabled,Enabled"
|
|
line.long 0x0C "UOTGHS__HSTDMASTATUS3,Host DMA Channel 3 Status Registe"
|
|
hexmask.long.word 0x0C 16.--31. 1. " BUFF_COUNT ,Buffer Byte Count"
|
|
bitfld.long 0x0C 6. " DESC_LDST ,Descriptor Loaded Status" "Not loaded,Loaded"
|
|
newline
|
|
bitfld.long 0x0C 5. " END_BF_ST ,End of Buffer Status" "Zero not reached,Zero reached"
|
|
bitfld.long 0x0C 4. " END_TR_ST ,End of Transfer Status" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x0C 1. " CHANN_ACT ,Channel Active Status" "Idle,Active"
|
|
bitfld.long 0x0C 0. " CHANN_ENB ,Channel Enable Status" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Channel 4"
|
|
group.long 0x740++0xF
|
|
line.long 0x00 "UOTGHS_HSTDMANXTDSC4,Host DMA Channel 4 Next Descriptor Address Register"
|
|
line.long 0x04 "UOTGHS_HSTDMAADDRESS4,Host DMA Channel 4 Address Register"
|
|
line.long 0x08 "UOTGHS_HSTDMACONTROL4,Host DMA Channel 4 Control Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " BUFF_LENGTH ,Buffer Byte Length"
|
|
bitfld.long 0x08 7. " BURST_LCK ,Burst Lock Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 6. " DESC_LD_IT ,Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " END_BUFFIT ,End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 4. " END_TR_IT ,End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " END_B_EN ,End of Buffer Enable Control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 2. " END_TR_EN ,End of Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " LDNXT_DSC ,Load Next Channel Transfer Descriptor Enable Command" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 0. " CHANN_ENB ,Channel Enable Command" "Disabled,Enabled"
|
|
line.long 0x0C "UOTGHS__HSTDMASTATUS4,Host DMA Channel 4 Status Registe"
|
|
hexmask.long.word 0x0C 16.--31. 1. " BUFF_COUNT ,Buffer Byte Count"
|
|
bitfld.long 0x0C 6. " DESC_LDST ,Descriptor Loaded Status" "Not loaded,Loaded"
|
|
newline
|
|
bitfld.long 0x0C 5. " END_BF_ST ,End of Buffer Status" "Zero not reached,Zero reached"
|
|
bitfld.long 0x0C 4. " END_TR_ST ,End of Transfer Status" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x0C 1. " CHANN_ACT ,Channel Active Status" "Idle,Active"
|
|
bitfld.long 0x0C 0. " CHANN_ENB ,Channel Enable Status" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Channel 5"
|
|
group.long 0x750++0xF
|
|
line.long 0x00 "UOTGHS_HSTDMANXTDSC5,Host DMA Channel 5 Next Descriptor Address Register"
|
|
line.long 0x04 "UOTGHS_HSTDMAADDRESS5,Host DMA Channel 5 Address Register"
|
|
line.long 0x08 "UOTGHS_HSTDMACONTROL5,Host DMA Channel 5 Control Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " BUFF_LENGTH ,Buffer Byte Length"
|
|
bitfld.long 0x08 7. " BURST_LCK ,Burst Lock Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 6. " DESC_LD_IT ,Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " END_BUFFIT ,End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 4. " END_TR_IT ,End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " END_B_EN ,End of Buffer Enable Control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 2. " END_TR_EN ,End of Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " LDNXT_DSC ,Load Next Channel Transfer Descriptor Enable Command" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 0. " CHANN_ENB ,Channel Enable Command" "Disabled,Enabled"
|
|
line.long 0x0C "UOTGHS__HSTDMASTATUS5,Host DMA Channel 5 Status Registe"
|
|
hexmask.long.word 0x0C 16.--31. 1. " BUFF_COUNT ,Buffer Byte Count"
|
|
bitfld.long 0x0C 6. " DESC_LDST ,Descriptor Loaded Status" "Not loaded,Loaded"
|
|
newline
|
|
bitfld.long 0x0C 5. " END_BF_ST ,End of Buffer Status" "Zero not reached,Zero reached"
|
|
bitfld.long 0x0C 4. " END_TR_ST ,End of Transfer Status" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x0C 1. " CHANN_ACT ,Channel Active Status" "Idle,Active"
|
|
bitfld.long 0x0C 0. " CHANN_ENB ,Channel Enable Status" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Channel 6"
|
|
group.long 0x760++0xF
|
|
line.long 0x00 "UOTGHS_HSTDMANXTDSC6,Host DMA Channel 6 Next Descriptor Address Register"
|
|
line.long 0x04 "UOTGHS_HSTDMAADDRESS6,Host DMA Channel 6 Address Register"
|
|
line.long 0x08 "UOTGHS_HSTDMACONTROL6,Host DMA Channel 6 Control Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " BUFF_LENGTH ,Buffer Byte Length"
|
|
bitfld.long 0x08 7. " BURST_LCK ,Burst Lock Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 6. " DESC_LD_IT ,Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " END_BUFFIT ,End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 4. " END_TR_IT ,End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " END_B_EN ,End of Buffer Enable Control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 2. " END_TR_EN ,End of Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " LDNXT_DSC ,Load Next Channel Transfer Descriptor Enable Command" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 0. " CHANN_ENB ,Channel Enable Command" "Disabled,Enabled"
|
|
line.long 0x0C "UOTGHS__HSTDMASTATUS6,Host DMA Channel 6 Status Registe"
|
|
hexmask.long.word 0x0C 16.--31. 1. " BUFF_COUNT ,Buffer Byte Count"
|
|
bitfld.long 0x0C 6. " DESC_LDST ,Descriptor Loaded Status" "Not loaded,Loaded"
|
|
newline
|
|
bitfld.long 0x0C 5. " END_BF_ST ,End of Buffer Status" "Zero not reached,Zero reached"
|
|
bitfld.long 0x0C 4. " END_TR_ST ,End of Transfer Status" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x0C 1. " CHANN_ACT ,Channel Active Status" "Idle,Active"
|
|
bitfld.long 0x0C 0. " CHANN_ENB ,Channel Enable Status" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Channel 7"
|
|
group.long 0x770++0xF
|
|
line.long 0x00 "UOTGHS_HSTDMANXTDSC7,Host DMA Channel 7 Next Descriptor Address Register"
|
|
line.long 0x04 "UOTGHS_HSTDMAADDRESS7,Host DMA Channel 7 Address Register"
|
|
line.long 0x08 "UOTGHS_HSTDMACONTROL7,Host DMA Channel 7 Control Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " BUFF_LENGTH ,Buffer Byte Length"
|
|
bitfld.long 0x08 7. " BURST_LCK ,Burst Lock Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 6. " DESC_LD_IT ,Descriptor Loaded Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " END_BUFFIT ,End of Buffer Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 4. " END_TR_IT ,End of Transfer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " END_B_EN ,End of Buffer Enable Control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 2. " END_TR_EN ,End of Transfer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " LDNXT_DSC ,Load Next Channel Transfer Descriptor Enable Command" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 0. " CHANN_ENB ,Channel Enable Command" "Disabled,Enabled"
|
|
line.long 0x0C "UOTGHS__HSTDMASTATUS7,Host DMA Channel 7 Status Registe"
|
|
hexmask.long.word 0x0C 16.--31. 1. " BUFF_COUNT ,Buffer Byte Count"
|
|
bitfld.long 0x0C 6. " DESC_LDST ,Descriptor Loaded Status" "Not loaded,Loaded"
|
|
newline
|
|
bitfld.long 0x0C 5. " END_BF_ST ,End of Buffer Status" "Zero not reached,Zero reached"
|
|
bitfld.long 0x0C 4. " END_TR_ST ,End of Transfer Status" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x0C 1. " CHANN_ACT ,Channel Active Status" "Idle,Active"
|
|
bitfld.long 0x0C 0. " CHANN_ENB ,Channel Enable Status" "Disabled,Enabled"
|
|
tree.end
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree.open "CAN (Controller Area Network)"
|
|
tree "CAN0"
|
|
base ad:0x400B4000
|
|
width 13.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "CAN_MR,CAN Mode Register"
|
|
bitfld.long 0x00 7. " DRPT ,Disable Repeat" "No,Yes"
|
|
bitfld.long 0x00 6. " TIMFRZ ,Enable Timer Freeze" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TTM ,Disable/Enable Time Triggered Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TEOF ,Timestamp messages at each end of Frame" "Start Of Frame,End Of Frame"
|
|
bitfld.long 0x00 3. " OVL ,Disable/Enable Overload Frame" "Not generated,Generated"
|
|
bitfld.long 0x00 2. " ABM ,Disable/Enable Autobaud/Listen mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LPM ,Disable/Enable Low Power Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CANEN ,CAN Controller Enable" "Disabled,Enabled"
|
|
group.long 0xc++0x3
|
|
line.long 0x00 "CAN_IMR,CAN Interrupt Mask Register"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x4 28. " BERR_set/clr ,Bit Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x4 27. " FERR_set/clr ,Form Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x4 26. " AERR_set/clr ,Acknowledgment Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x4 25. " SERR_set/clr ,Stuffing Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x4 24. " CERR_set/clr ,CRC Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x4 23. " TSTP_set/clr ,Timestamp Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x08 22. -0x4 22. " TOVF_set/clr ,Timer Overflow Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x4 21. " WAKEUP_set/clr ,Wakeup Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x4 20. " SLEEP_set/clr ,Sleep Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x4 19. " BOFF_set/clr ,Bus Off Mode Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x4 18. " ERRP_set/clr ,Error Passive Mode Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x4 17. " WARN_set/clr ,Warning Limit Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x4 16. " ERRA_set/clr ,Error Active Mode Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x4 7. " MB7_set/clr ,Mailbox 7 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x4 6. " MB6_set/clr ,Mailbox 6 Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x4 5. " MB5_set/clr ,Mailbox 5 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x4 4. " MB4_set/clr ,Mailbox 4 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x4 3. " MB3_set/clr ,Mailbox 3 Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x4 2. " MB2_set/clr ,Mailbox 2 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x4 1. " MB1_set/clr ,Mailbox 1 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x4 0. " MB0_set/clr ,Mailbox 0 Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x10++0x3
|
|
hide.long 0x00 "CAN_SR,CAN Status Register"
|
|
in
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "CAN_BR,CAN Baudrate Register"
|
|
bitfld.long 0x00 24. " SMP ,Sampling Mode" "Sampled once,Sampled three times"
|
|
hexmask.long.byte 0x00 16.--22. 1. " BRP ,Baudrate Prescaler"
|
|
bitfld.long 0x00 12.--13. " SJW ,Re-synchronization jump width" "1,2,3,4"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " PROPAG ,Programming time segment" "1,2,3,4,5,6,7,8"
|
|
bitfld.long 0x00 4.--6. " PHASE1 ,Phase 1 segment" "1,2,3,4,5,6,7,8"
|
|
bitfld.long 0x00 0.--2. " PHASE2 ,Phase 2 segment" "1,2,3,4,5,6,7,8"
|
|
rgroup.long 0x18++0xB
|
|
line.long 0x00 "CAN_TIM,CAN Timer Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMER ,Timer"
|
|
line.long 0x04 "CAN_TIMESTP,CAN Timestamp Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " MTIMESTAMP ,Timestamp"
|
|
line.long 0x08 "CAN_ECR,CAN Error Counter Register"
|
|
hexmask.long.byte 0x08 16.--23. 1. " TEC ,Transmit Error Counter"
|
|
hexmask.long.byte 0x08 0.--7. 1. " REC ,Receive Error Counter"
|
|
wgroup.long 0x24++0x7
|
|
line.long 0x00 "CAN_TCR,CAN Transfer Command Register"
|
|
bitfld.long 0x00 31. " TIMRST ,Timer Reset" "No reset,Reset"
|
|
bitfld.long 0x00 7. " MB7 ,Transfer Request for Mailbox 7" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " MB6 ,Transfer Request for Mailbox 6" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MB5 ,Transfer Request for Mailbox 5" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " MB4 ,Transfer Request for Mailbox 4" "Not requested,Requested"
|
|
bitfld.long 0x00 3. " MB3 ,Transfer Request for Mailbox 3" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MB2 ,Transfer Request for Mailbox 2" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " MB1 ,Transfer Request for Mailbox 1" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " MB0 ,Transfer Request for Mailbox 0" "Not requested,Requested"
|
|
line.long 0x04 "CAN_ACR,CAN Abort Command Register"
|
|
bitfld.long 0x04 7. " MB7 ,Abort Request for Mailbox 7" "Not aborted,Aborted"
|
|
bitfld.long 0x04 6. " MB6 ,Abort Request for Mailbox 6" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x04 5. " MB5 ,Abort Request for Mailbox 5" "Not aborted,Aborted"
|
|
bitfld.long 0x04 4. " MB4 ,Abort Request for Mailbox 4" "Not aborted,Aborted"
|
|
bitfld.long 0x04 3. " MB3 ,Abort Request for Mailbox 3" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x04 2. " MB2 ,Abort Request for Mailbox 2" "Not aborted,Aborted"
|
|
bitfld.long 0x04 1. " MB1 ,Abort Request for Mailbox 1" "Not aborted,Aborted"
|
|
bitfld.long 0x04 0. " MB0 ,Abort Request for Mailbox 0" "Not aborted,Aborted"
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "CAN_WPMR,CAN Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,SPI Write Protection Key Password"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x3
|
|
hide.long 0x00 "CAN_WPSR,CAN Write Protection Status Register"
|
|
in
|
|
tree "Mailbox 0"
|
|
group.long 0x400B4000++0xB
|
|
line.long 0x00 "CAN_MMR0,CAN Message Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception with overwrite,Transmit,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark"
|
|
line.long 0x04 "CAN_MAM0,CAN Message Acceptance Mask Register"
|
|
bitfld.long 0x04 29. " MIDE ,Identifier Version" "Compared IDvA with CAN_MID0,Compared IDvA with IDvB"
|
|
textline " "
|
|
hexmask.long.word 0x04 18.--28. 1. " MIDvA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " MIDvB ,Complementary bits for identifier in extended frame mode"
|
|
line.long 0x08 "CAN_MID0,CAN Message ID Register"
|
|
bitfld.long 0x08 29. " MIDE ,Identifier Version" "2.0 Part A,2.0 Part B"
|
|
hexmask.long.word 0x08 18.--28. 1. " MIDvA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " MIDvB ,Complementary bits for identifier in extended frame mode"
|
|
rgroup.long (0x400B4000+0x0C)++0x3
|
|
line.long 0x0 "CAN_MFID0,CAN Message Family ID Register"
|
|
hexmask.long 0x0 0.--28. 1. " MFID ,Family ID"
|
|
hgroup.long (0x400B4000+0x10)++0x3
|
|
hide.long 0x04 "CAN_MSR0,CAN Message Status Register"
|
|
in
|
|
group.long (0x400B4000+0x14)++0x7
|
|
line.long 0x00 "CAN_MDL0,CAN Message Data Low Register"
|
|
line.long 0x04 "CAN_MDH0,CAN Message Data High Register"
|
|
wgroup.long (0x400B4000+0x1C)++0x3
|
|
line.long 0x00 "CAN_MCR0,CAN Message Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " MACR ,Abort Request for Mailbox 0" "No effect,Aborted"
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Mailbox 1"
|
|
group.long 0x400B4020++0xB
|
|
line.long 0x00 "CAN_MMR1,CAN Message Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception with overwrite,Transmit,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark"
|
|
line.long 0x04 "CAN_MAM1,CAN Message Acceptance Mask Register"
|
|
bitfld.long 0x04 29. " MIDE ,Identifier Version" "Compared IDvA with CAN_MID1,Compared IDvA with IDvB"
|
|
textline " "
|
|
hexmask.long.word 0x04 18.--28. 1. " MIDvA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " MIDvB ,Complementary bits for identifier in extended frame mode"
|
|
line.long 0x08 "CAN_MID1,CAN Message ID Register"
|
|
bitfld.long 0x08 29. " MIDE ,Identifier Version" "2.0 Part A,2.0 Part B"
|
|
hexmask.long.word 0x08 18.--28. 1. " MIDvA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " MIDvB ,Complementary bits for identifier in extended frame mode"
|
|
rgroup.long (0x400B4020+0x0C)++0x3
|
|
line.long 0x0 "CAN_MFID1,CAN Message Family ID Register"
|
|
hexmask.long 0x0 0.--28. 1. " MFID ,Family ID"
|
|
hgroup.long (0x400B4020+0x10)++0x3
|
|
hide.long 0x04 "CAN_MSR1,CAN Message Status Register"
|
|
in
|
|
group.long (0x400B4020+0x14)++0x7
|
|
line.long 0x00 "CAN_MDL1,CAN Message Data Low Register"
|
|
line.long 0x04 "CAN_MDH1,CAN Message Data High Register"
|
|
wgroup.long (0x400B4020+0x1C)++0x3
|
|
line.long 0x00 "CAN_MCR1,CAN Message Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " MACR ,Abort Request for Mailbox 1" "No effect,Aborted"
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Mailbox 2"
|
|
group.long 0x400B4040++0xB
|
|
line.long 0x00 "CAN_MMR2,CAN Message Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception with overwrite,Transmit,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark"
|
|
line.long 0x04 "CAN_MAM2,CAN Message Acceptance Mask Register"
|
|
bitfld.long 0x04 29. " MIDE ,Identifier Version" "Compared IDvA with CAN_MID2,Compared IDvA with IDvB"
|
|
textline " "
|
|
hexmask.long.word 0x04 18.--28. 1. " MIDvA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " MIDvB ,Complementary bits for identifier in extended frame mode"
|
|
line.long 0x08 "CAN_MID2,CAN Message ID Register"
|
|
bitfld.long 0x08 29. " MIDE ,Identifier Version" "2.0 Part A,2.0 Part B"
|
|
hexmask.long.word 0x08 18.--28. 1. " MIDvA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " MIDvB ,Complementary bits for identifier in extended frame mode"
|
|
rgroup.long (0x400B4040+0x0C)++0x3
|
|
line.long 0x0 "CAN_MFID2,CAN Message Family ID Register"
|
|
hexmask.long 0x0 0.--28. 1. " MFID ,Family ID"
|
|
hgroup.long (0x400B4040+0x10)++0x3
|
|
hide.long 0x04 "CAN_MSR2,CAN Message Status Register"
|
|
in
|
|
group.long (0x400B4040+0x14)++0x7
|
|
line.long 0x00 "CAN_MDL2,CAN Message Data Low Register"
|
|
line.long 0x04 "CAN_MDH2,CAN Message Data High Register"
|
|
wgroup.long (0x400B4040+0x1C)++0x3
|
|
line.long 0x00 "CAN_MCR2,CAN Message Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " MACR ,Abort Request for Mailbox 2" "No effect,Aborted"
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Mailbox 3"
|
|
group.long 0x400B4060++0xB
|
|
line.long 0x00 "CAN_MMR3,CAN Message Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception with overwrite,Transmit,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark"
|
|
line.long 0x04 "CAN_MAM3,CAN Message Acceptance Mask Register"
|
|
bitfld.long 0x04 29. " MIDE ,Identifier Version" "Compared IDvA with CAN_MID3,Compared IDvA with IDvB"
|
|
textline " "
|
|
hexmask.long.word 0x04 18.--28. 1. " MIDvA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " MIDvB ,Complementary bits for identifier in extended frame mode"
|
|
line.long 0x08 "CAN_MID3,CAN Message ID Register"
|
|
bitfld.long 0x08 29. " MIDE ,Identifier Version" "2.0 Part A,2.0 Part B"
|
|
hexmask.long.word 0x08 18.--28. 1. " MIDvA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " MIDvB ,Complementary bits for identifier in extended frame mode"
|
|
rgroup.long (0x400B4060+0x0C)++0x3
|
|
line.long 0x0 "CAN_MFID3,CAN Message Family ID Register"
|
|
hexmask.long 0x0 0.--28. 1. " MFID ,Family ID"
|
|
hgroup.long (0x400B4060+0x10)++0x3
|
|
hide.long 0x04 "CAN_MSR3,CAN Message Status Register"
|
|
in
|
|
group.long (0x400B4060+0x14)++0x7
|
|
line.long 0x00 "CAN_MDL3,CAN Message Data Low Register"
|
|
line.long 0x04 "CAN_MDH3,CAN Message Data High Register"
|
|
wgroup.long (0x400B4060+0x1C)++0x3
|
|
line.long 0x00 "CAN_MCR3,CAN Message Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " MACR ,Abort Request for Mailbox 3" "No effect,Aborted"
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Mailbox 4"
|
|
group.long 0x400B4080++0xB
|
|
line.long 0x00 "CAN_MMR4,CAN Message Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception with overwrite,Transmit,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark"
|
|
line.long 0x04 "CAN_MAM4,CAN Message Acceptance Mask Register"
|
|
bitfld.long 0x04 29. " MIDE ,Identifier Version" "Compared IDvA with CAN_MID4,Compared IDvA with IDvB"
|
|
textline " "
|
|
hexmask.long.word 0x04 18.--28. 1. " MIDvA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " MIDvB ,Complementary bits for identifier in extended frame mode"
|
|
line.long 0x08 "CAN_MID4,CAN Message ID Register"
|
|
bitfld.long 0x08 29. " MIDE ,Identifier Version" "2.0 Part A,2.0 Part B"
|
|
hexmask.long.word 0x08 18.--28. 1. " MIDvA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " MIDvB ,Complementary bits for identifier in extended frame mode"
|
|
rgroup.long (0x400B4080+0x0C)++0x3
|
|
line.long 0x0 "CAN_MFID4,CAN Message Family ID Register"
|
|
hexmask.long 0x0 0.--28. 1. " MFID ,Family ID"
|
|
hgroup.long (0x400B4080+0x10)++0x3
|
|
hide.long 0x04 "CAN_MSR4,CAN Message Status Register"
|
|
in
|
|
group.long (0x400B4080+0x14)++0x7
|
|
line.long 0x00 "CAN_MDL4,CAN Message Data Low Register"
|
|
line.long 0x04 "CAN_MDH4,CAN Message Data High Register"
|
|
wgroup.long (0x400B4080+0x1C)++0x3
|
|
line.long 0x00 "CAN_MCR4,CAN Message Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " MACR ,Abort Request for Mailbox 4" "No effect,Aborted"
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Mailbox 5"
|
|
group.long 0x400B40A0++0xB
|
|
line.long 0x00 "CAN_MMR5,CAN Message Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception with overwrite,Transmit,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark"
|
|
line.long 0x04 "CAN_MAM5,CAN Message Acceptance Mask Register"
|
|
bitfld.long 0x04 29. " MIDE ,Identifier Version" "Compared IDvA with CAN_MID5,Compared IDvA with IDvB"
|
|
textline " "
|
|
hexmask.long.word 0x04 18.--28. 1. " MIDvA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " MIDvB ,Complementary bits for identifier in extended frame mode"
|
|
line.long 0x08 "CAN_MID5,CAN Message ID Register"
|
|
bitfld.long 0x08 29. " MIDE ,Identifier Version" "2.0 Part A,2.0 Part B"
|
|
hexmask.long.word 0x08 18.--28. 1. " MIDvA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " MIDvB ,Complementary bits for identifier in extended frame mode"
|
|
rgroup.long (0x400B40A0+0x0C)++0x3
|
|
line.long 0x0 "CAN_MFID5,CAN Message Family ID Register"
|
|
hexmask.long 0x0 0.--28. 1. " MFID ,Family ID"
|
|
hgroup.long (0x400B40A0+0x10)++0x3
|
|
hide.long 0x04 "CAN_MSR5,CAN Message Status Register"
|
|
in
|
|
group.long (0x400B40A0+0x14)++0x7
|
|
line.long 0x00 "CAN_MDL5,CAN Message Data Low Register"
|
|
line.long 0x04 "CAN_MDH5,CAN Message Data High Register"
|
|
wgroup.long (0x400B40A0+0x1C)++0x3
|
|
line.long 0x00 "CAN_MCR5,CAN Message Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " MACR ,Abort Request for Mailbox 5" "No effect,Aborted"
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Mailbox 6"
|
|
group.long 0x400B40C0++0xB
|
|
line.long 0x00 "CAN_MMR6,CAN Message Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception with overwrite,Transmit,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark"
|
|
line.long 0x04 "CAN_MAM6,CAN Message Acceptance Mask Register"
|
|
bitfld.long 0x04 29. " MIDE ,Identifier Version" "Compared IDvA with CAN_MID6,Compared IDvA with IDvB"
|
|
textline " "
|
|
hexmask.long.word 0x04 18.--28. 1. " MIDvA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " MIDvB ,Complementary bits for identifier in extended frame mode"
|
|
line.long 0x08 "CAN_MID6,CAN Message ID Register"
|
|
bitfld.long 0x08 29. " MIDE ,Identifier Version" "2.0 Part A,2.0 Part B"
|
|
hexmask.long.word 0x08 18.--28. 1. " MIDvA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " MIDvB ,Complementary bits for identifier in extended frame mode"
|
|
rgroup.long (0x400B40C0+0x0C)++0x3
|
|
line.long 0x0 "CAN_MFID6,CAN Message Family ID Register"
|
|
hexmask.long 0x0 0.--28. 1. " MFID ,Family ID"
|
|
hgroup.long (0x400B40C0+0x10)++0x3
|
|
hide.long 0x04 "CAN_MSR6,CAN Message Status Register"
|
|
in
|
|
group.long (0x400B40C0+0x14)++0x7
|
|
line.long 0x00 "CAN_MDL6,CAN Message Data Low Register"
|
|
line.long 0x04 "CAN_MDH6,CAN Message Data High Register"
|
|
wgroup.long (0x400B40C0+0x1C)++0x3
|
|
line.long 0x00 "CAN_MCR6,CAN Message Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " MACR ,Abort Request for Mailbox 6" "No effect,Aborted"
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Mailbox 7"
|
|
group.long 0x400B40E0++0xB
|
|
line.long 0x00 "CAN_MMR7,CAN Message Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception with overwrite,Transmit,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark"
|
|
line.long 0x04 "CAN_MAM7,CAN Message Acceptance Mask Register"
|
|
bitfld.long 0x04 29. " MIDE ,Identifier Version" "Compared IDvA with CAN_MID7,Compared IDvA with IDvB"
|
|
textline " "
|
|
hexmask.long.word 0x04 18.--28. 1. " MIDvA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " MIDvB ,Complementary bits for identifier in extended frame mode"
|
|
line.long 0x08 "CAN_MID7,CAN Message ID Register"
|
|
bitfld.long 0x08 29. " MIDE ,Identifier Version" "2.0 Part A,2.0 Part B"
|
|
hexmask.long.word 0x08 18.--28. 1. " MIDvA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " MIDvB ,Complementary bits for identifier in extended frame mode"
|
|
rgroup.long (0x400B40E0+0x0C)++0x3
|
|
line.long 0x0 "CAN_MFID7,CAN Message Family ID Register"
|
|
hexmask.long 0x0 0.--28. 1. " MFID ,Family ID"
|
|
hgroup.long (0x400B40E0+0x10)++0x3
|
|
hide.long 0x04 "CAN_MSR7,CAN Message Status Register"
|
|
in
|
|
group.long (0x400B40E0+0x14)++0x7
|
|
line.long 0x00 "CAN_MDL7,CAN Message Data Low Register"
|
|
line.long 0x04 "CAN_MDH7,CAN Message Data High Register"
|
|
wgroup.long (0x400B40E0+0x1C)++0x3
|
|
line.long 0x00 "CAN_MCR7,CAN Message Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " MACR ,Abort Request for Mailbox 7" "No effect,Aborted"
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree "CAN1"
|
|
base ad:0x400B8000
|
|
width 13.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "CAN_MR,CAN Mode Register"
|
|
bitfld.long 0x00 7. " DRPT ,Disable Repeat" "No,Yes"
|
|
bitfld.long 0x00 6. " TIMFRZ ,Enable Timer Freeze" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TTM ,Disable/Enable Time Triggered Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TEOF ,Timestamp messages at each end of Frame" "Start Of Frame,End Of Frame"
|
|
bitfld.long 0x00 3. " OVL ,Disable/Enable Overload Frame" "Not generated,Generated"
|
|
bitfld.long 0x00 2. " ABM ,Disable/Enable Autobaud/Listen mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LPM ,Disable/Enable Low Power Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CANEN ,CAN Controller Enable" "Disabled,Enabled"
|
|
group.long 0xc++0x3
|
|
line.long 0x00 "CAN_IMR,CAN Interrupt Mask Register"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x4 28. " BERR_set/clr ,Bit Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x4 27. " FERR_set/clr ,Form Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x4 26. " AERR_set/clr ,Acknowledgment Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x08 25. -0x4 25. " SERR_set/clr ,Stuffing Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x4 24. " CERR_set/clr ,CRC Error Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x4 23. " TSTP_set/clr ,Timestamp Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x08 22. -0x4 22. " TOVF_set/clr ,Timer Overflow Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x4 21. " WAKEUP_set/clr ,Wakeup Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x4 20. " SLEEP_set/clr ,Sleep Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x08 19. -0x4 19. " BOFF_set/clr ,Bus Off Mode Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x4 18. " ERRP_set/clr ,Error Passive Mode Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x4 17. " WARN_set/clr ,Warning Limit Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x08 16. -0x4 16. " ERRA_set/clr ,Error Active Mode Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x4 7. " MB7_set/clr ,Mailbox 7 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x4 6. " MB6_set/clr ,Mailbox 6 Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x4 5. " MB5_set/clr ,Mailbox 5 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x4 4. " MB4_set/clr ,Mailbox 4 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x4 3. " MB3_set/clr ,Mailbox 3 Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x4 2. " MB2_set/clr ,Mailbox 2 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x4 1. " MB1_set/clr ,Mailbox 1 Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x4 0. " MB0_set/clr ,Mailbox 0 Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x10++0x3
|
|
hide.long 0x00 "CAN_SR,CAN Status Register"
|
|
in
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "CAN_BR,CAN Baudrate Register"
|
|
bitfld.long 0x00 24. " SMP ,Sampling Mode" "Sampled once,Sampled three times"
|
|
hexmask.long.byte 0x00 16.--22. 1. " BRP ,Baudrate Prescaler"
|
|
bitfld.long 0x00 12.--13. " SJW ,Re-synchronization jump width" "1,2,3,4"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " PROPAG ,Programming time segment" "1,2,3,4,5,6,7,8"
|
|
bitfld.long 0x00 4.--6. " PHASE1 ,Phase 1 segment" "1,2,3,4,5,6,7,8"
|
|
bitfld.long 0x00 0.--2. " PHASE2 ,Phase 2 segment" "1,2,3,4,5,6,7,8"
|
|
rgroup.long 0x18++0xB
|
|
line.long 0x00 "CAN_TIM,CAN Timer Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMER ,Timer"
|
|
line.long 0x04 "CAN_TIMESTP,CAN Timestamp Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " MTIMESTAMP ,Timestamp"
|
|
line.long 0x08 "CAN_ECR,CAN Error Counter Register"
|
|
hexmask.long.byte 0x08 16.--23. 1. " TEC ,Transmit Error Counter"
|
|
hexmask.long.byte 0x08 0.--7. 1. " REC ,Receive Error Counter"
|
|
wgroup.long 0x24++0x7
|
|
line.long 0x00 "CAN_TCR,CAN Transfer Command Register"
|
|
bitfld.long 0x00 31. " TIMRST ,Timer Reset" "No reset,Reset"
|
|
bitfld.long 0x00 7. " MB7 ,Transfer Request for Mailbox 7" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " MB6 ,Transfer Request for Mailbox 6" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MB5 ,Transfer Request for Mailbox 5" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " MB4 ,Transfer Request for Mailbox 4" "Not requested,Requested"
|
|
bitfld.long 0x00 3. " MB3 ,Transfer Request for Mailbox 3" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MB2 ,Transfer Request for Mailbox 2" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " MB1 ,Transfer Request for Mailbox 1" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " MB0 ,Transfer Request for Mailbox 0" "Not requested,Requested"
|
|
line.long 0x04 "CAN_ACR,CAN Abort Command Register"
|
|
bitfld.long 0x04 7. " MB7 ,Abort Request for Mailbox 7" "Not aborted,Aborted"
|
|
bitfld.long 0x04 6. " MB6 ,Abort Request for Mailbox 6" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x04 5. " MB5 ,Abort Request for Mailbox 5" "Not aborted,Aborted"
|
|
bitfld.long 0x04 4. " MB4 ,Abort Request for Mailbox 4" "Not aborted,Aborted"
|
|
bitfld.long 0x04 3. " MB3 ,Abort Request for Mailbox 3" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x04 2. " MB2 ,Abort Request for Mailbox 2" "Not aborted,Aborted"
|
|
bitfld.long 0x04 1. " MB1 ,Abort Request for Mailbox 1" "Not aborted,Aborted"
|
|
bitfld.long 0x04 0. " MB0 ,Abort Request for Mailbox 0" "Not aborted,Aborted"
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "CAN_WPMR,CAN Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,SPI Write Protection Key Password"
|
|
bitfld.long 0x00 0. " WPEN ,Write Protection Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x3
|
|
hide.long 0x00 "CAN_WPSR,CAN Write Protection Status Register"
|
|
in
|
|
tree "Mailbox 0"
|
|
group.long 0x400B8000++0xB
|
|
line.long 0x00 "CAN_MMR0,CAN Message Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception with overwrite,Transmit,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark"
|
|
line.long 0x04 "CAN_MAM0,CAN Message Acceptance Mask Register"
|
|
bitfld.long 0x04 29. " MIDE ,Identifier Version" "Compared IDvA with CAN_MID0,Compared IDvA with IDvB"
|
|
textline " "
|
|
hexmask.long.word 0x04 18.--28. 1. " MIDvA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " MIDvB ,Complementary bits for identifier in extended frame mode"
|
|
line.long 0x08 "CAN_MID0,CAN Message ID Register"
|
|
bitfld.long 0x08 29. " MIDE ,Identifier Version" "2.0 Part A,2.0 Part B"
|
|
hexmask.long.word 0x08 18.--28. 1. " MIDvA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " MIDvB ,Complementary bits for identifier in extended frame mode"
|
|
rgroup.long (0x400B8000+0x0C)++0x3
|
|
line.long 0x0 "CAN_MFID0,CAN Message Family ID Register"
|
|
hexmask.long 0x0 0.--28. 1. " MFID ,Family ID"
|
|
hgroup.long (0x400B8000+0x10)++0x3
|
|
hide.long 0x04 "CAN_MSR0,CAN Message Status Register"
|
|
in
|
|
group.long (0x400B8000+0x14)++0x7
|
|
line.long 0x00 "CAN_MDL0,CAN Message Data Low Register"
|
|
line.long 0x04 "CAN_MDH0,CAN Message Data High Register"
|
|
wgroup.long (0x400B8000+0x1C)++0x3
|
|
line.long 0x00 "CAN_MCR0,CAN Message Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " MACR ,Abort Request for Mailbox 0" "No effect,Aborted"
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Mailbox 1"
|
|
group.long 0x400B8020++0xB
|
|
line.long 0x00 "CAN_MMR1,CAN Message Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception with overwrite,Transmit,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark"
|
|
line.long 0x04 "CAN_MAM1,CAN Message Acceptance Mask Register"
|
|
bitfld.long 0x04 29. " MIDE ,Identifier Version" "Compared IDvA with CAN_MID1,Compared IDvA with IDvB"
|
|
textline " "
|
|
hexmask.long.word 0x04 18.--28. 1. " MIDvA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " MIDvB ,Complementary bits for identifier in extended frame mode"
|
|
line.long 0x08 "CAN_MID1,CAN Message ID Register"
|
|
bitfld.long 0x08 29. " MIDE ,Identifier Version" "2.0 Part A,2.0 Part B"
|
|
hexmask.long.word 0x08 18.--28. 1. " MIDvA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " MIDvB ,Complementary bits for identifier in extended frame mode"
|
|
rgroup.long (0x400B8020+0x0C)++0x3
|
|
line.long 0x0 "CAN_MFID1,CAN Message Family ID Register"
|
|
hexmask.long 0x0 0.--28. 1. " MFID ,Family ID"
|
|
hgroup.long (0x400B8020+0x10)++0x3
|
|
hide.long 0x04 "CAN_MSR1,CAN Message Status Register"
|
|
in
|
|
group.long (0x400B8020+0x14)++0x7
|
|
line.long 0x00 "CAN_MDL1,CAN Message Data Low Register"
|
|
line.long 0x04 "CAN_MDH1,CAN Message Data High Register"
|
|
wgroup.long (0x400B8020+0x1C)++0x3
|
|
line.long 0x00 "CAN_MCR1,CAN Message Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " MACR ,Abort Request for Mailbox 1" "No effect,Aborted"
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Mailbox 2"
|
|
group.long 0x400B8040++0xB
|
|
line.long 0x00 "CAN_MMR2,CAN Message Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception with overwrite,Transmit,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark"
|
|
line.long 0x04 "CAN_MAM2,CAN Message Acceptance Mask Register"
|
|
bitfld.long 0x04 29. " MIDE ,Identifier Version" "Compared IDvA with CAN_MID2,Compared IDvA with IDvB"
|
|
textline " "
|
|
hexmask.long.word 0x04 18.--28. 1. " MIDvA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " MIDvB ,Complementary bits for identifier in extended frame mode"
|
|
line.long 0x08 "CAN_MID2,CAN Message ID Register"
|
|
bitfld.long 0x08 29. " MIDE ,Identifier Version" "2.0 Part A,2.0 Part B"
|
|
hexmask.long.word 0x08 18.--28. 1. " MIDvA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " MIDvB ,Complementary bits for identifier in extended frame mode"
|
|
rgroup.long (0x400B8040+0x0C)++0x3
|
|
line.long 0x0 "CAN_MFID2,CAN Message Family ID Register"
|
|
hexmask.long 0x0 0.--28. 1. " MFID ,Family ID"
|
|
hgroup.long (0x400B8040+0x10)++0x3
|
|
hide.long 0x04 "CAN_MSR2,CAN Message Status Register"
|
|
in
|
|
group.long (0x400B8040+0x14)++0x7
|
|
line.long 0x00 "CAN_MDL2,CAN Message Data Low Register"
|
|
line.long 0x04 "CAN_MDH2,CAN Message Data High Register"
|
|
wgroup.long (0x400B8040+0x1C)++0x3
|
|
line.long 0x00 "CAN_MCR2,CAN Message Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " MACR ,Abort Request for Mailbox 2" "No effect,Aborted"
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Mailbox 3"
|
|
group.long 0x400B8060++0xB
|
|
line.long 0x00 "CAN_MMR3,CAN Message Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception with overwrite,Transmit,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark"
|
|
line.long 0x04 "CAN_MAM3,CAN Message Acceptance Mask Register"
|
|
bitfld.long 0x04 29. " MIDE ,Identifier Version" "Compared IDvA with CAN_MID3,Compared IDvA with IDvB"
|
|
textline " "
|
|
hexmask.long.word 0x04 18.--28. 1. " MIDvA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " MIDvB ,Complementary bits for identifier in extended frame mode"
|
|
line.long 0x08 "CAN_MID3,CAN Message ID Register"
|
|
bitfld.long 0x08 29. " MIDE ,Identifier Version" "2.0 Part A,2.0 Part B"
|
|
hexmask.long.word 0x08 18.--28. 1. " MIDvA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " MIDvB ,Complementary bits for identifier in extended frame mode"
|
|
rgroup.long (0x400B8060+0x0C)++0x3
|
|
line.long 0x0 "CAN_MFID3,CAN Message Family ID Register"
|
|
hexmask.long 0x0 0.--28. 1. " MFID ,Family ID"
|
|
hgroup.long (0x400B8060+0x10)++0x3
|
|
hide.long 0x04 "CAN_MSR3,CAN Message Status Register"
|
|
in
|
|
group.long (0x400B8060+0x14)++0x7
|
|
line.long 0x00 "CAN_MDL3,CAN Message Data Low Register"
|
|
line.long 0x04 "CAN_MDH3,CAN Message Data High Register"
|
|
wgroup.long (0x400B8060+0x1C)++0x3
|
|
line.long 0x00 "CAN_MCR3,CAN Message Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " MACR ,Abort Request for Mailbox 3" "No effect,Aborted"
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Mailbox 4"
|
|
group.long 0x400B8080++0xB
|
|
line.long 0x00 "CAN_MMR4,CAN Message Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception with overwrite,Transmit,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark"
|
|
line.long 0x04 "CAN_MAM4,CAN Message Acceptance Mask Register"
|
|
bitfld.long 0x04 29. " MIDE ,Identifier Version" "Compared IDvA with CAN_MID4,Compared IDvA with IDvB"
|
|
textline " "
|
|
hexmask.long.word 0x04 18.--28. 1. " MIDvA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " MIDvB ,Complementary bits for identifier in extended frame mode"
|
|
line.long 0x08 "CAN_MID4,CAN Message ID Register"
|
|
bitfld.long 0x08 29. " MIDE ,Identifier Version" "2.0 Part A,2.0 Part B"
|
|
hexmask.long.word 0x08 18.--28. 1. " MIDvA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " MIDvB ,Complementary bits for identifier in extended frame mode"
|
|
rgroup.long (0x400B8080+0x0C)++0x3
|
|
line.long 0x0 "CAN_MFID4,CAN Message Family ID Register"
|
|
hexmask.long 0x0 0.--28. 1. " MFID ,Family ID"
|
|
hgroup.long (0x400B8080+0x10)++0x3
|
|
hide.long 0x04 "CAN_MSR4,CAN Message Status Register"
|
|
in
|
|
group.long (0x400B8080+0x14)++0x7
|
|
line.long 0x00 "CAN_MDL4,CAN Message Data Low Register"
|
|
line.long 0x04 "CAN_MDH4,CAN Message Data High Register"
|
|
wgroup.long (0x400B8080+0x1C)++0x3
|
|
line.long 0x00 "CAN_MCR4,CAN Message Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " MACR ,Abort Request for Mailbox 4" "No effect,Aborted"
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Mailbox 5"
|
|
group.long 0x400B80A0++0xB
|
|
line.long 0x00 "CAN_MMR5,CAN Message Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception with overwrite,Transmit,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark"
|
|
line.long 0x04 "CAN_MAM5,CAN Message Acceptance Mask Register"
|
|
bitfld.long 0x04 29. " MIDE ,Identifier Version" "Compared IDvA with CAN_MID5,Compared IDvA with IDvB"
|
|
textline " "
|
|
hexmask.long.word 0x04 18.--28. 1. " MIDvA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " MIDvB ,Complementary bits for identifier in extended frame mode"
|
|
line.long 0x08 "CAN_MID5,CAN Message ID Register"
|
|
bitfld.long 0x08 29. " MIDE ,Identifier Version" "2.0 Part A,2.0 Part B"
|
|
hexmask.long.word 0x08 18.--28. 1. " MIDvA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " MIDvB ,Complementary bits for identifier in extended frame mode"
|
|
rgroup.long (0x400B80A0+0x0C)++0x3
|
|
line.long 0x0 "CAN_MFID5,CAN Message Family ID Register"
|
|
hexmask.long 0x0 0.--28. 1. " MFID ,Family ID"
|
|
hgroup.long (0x400B80A0+0x10)++0x3
|
|
hide.long 0x04 "CAN_MSR5,CAN Message Status Register"
|
|
in
|
|
group.long (0x400B80A0+0x14)++0x7
|
|
line.long 0x00 "CAN_MDL5,CAN Message Data Low Register"
|
|
line.long 0x04 "CAN_MDH5,CAN Message Data High Register"
|
|
wgroup.long (0x400B80A0+0x1C)++0x3
|
|
line.long 0x00 "CAN_MCR5,CAN Message Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " MACR ,Abort Request for Mailbox 5" "No effect,Aborted"
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Mailbox 6"
|
|
group.long 0x400B80C0++0xB
|
|
line.long 0x00 "CAN_MMR6,CAN Message Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception with overwrite,Transmit,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark"
|
|
line.long 0x04 "CAN_MAM6,CAN Message Acceptance Mask Register"
|
|
bitfld.long 0x04 29. " MIDE ,Identifier Version" "Compared IDvA with CAN_MID6,Compared IDvA with IDvB"
|
|
textline " "
|
|
hexmask.long.word 0x04 18.--28. 1. " MIDvA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " MIDvB ,Complementary bits for identifier in extended frame mode"
|
|
line.long 0x08 "CAN_MID6,CAN Message ID Register"
|
|
bitfld.long 0x08 29. " MIDE ,Identifier Version" "2.0 Part A,2.0 Part B"
|
|
hexmask.long.word 0x08 18.--28. 1. " MIDvA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " MIDvB ,Complementary bits for identifier in extended frame mode"
|
|
rgroup.long (0x400B80C0+0x0C)++0x3
|
|
line.long 0x0 "CAN_MFID6,CAN Message Family ID Register"
|
|
hexmask.long 0x0 0.--28. 1. " MFID ,Family ID"
|
|
hgroup.long (0x400B80C0+0x10)++0x3
|
|
hide.long 0x04 "CAN_MSR6,CAN Message Status Register"
|
|
in
|
|
group.long (0x400B80C0+0x14)++0x7
|
|
line.long 0x00 "CAN_MDL6,CAN Message Data Low Register"
|
|
line.long 0x04 "CAN_MDH6,CAN Message Data High Register"
|
|
wgroup.long (0x400B80C0+0x1C)++0x3
|
|
line.long 0x00 "CAN_MCR6,CAN Message Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " MACR ,Abort Request for Mailbox 6" "No effect,Aborted"
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Mailbox 7"
|
|
group.long 0x400B80E0++0xB
|
|
line.long 0x00 "CAN_MMR7,CAN Message Mode Register"
|
|
bitfld.long 0x00 24.--26. " MOT ,Mailbox Object Type" "Disabled,Reception,Reception with overwrite,Transmit,?..."
|
|
bitfld.long 0x00 16.--19. " PRIOR ,Mailbox Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " MTIMEMARK ,Mailbox Timemark"
|
|
line.long 0x04 "CAN_MAM7,CAN Message Acceptance Mask Register"
|
|
bitfld.long 0x04 29. " MIDE ,Identifier Version" "Compared IDvA with CAN_MID7,Compared IDvA with IDvB"
|
|
textline " "
|
|
hexmask.long.word 0x04 18.--28. 1. " MIDvA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " MIDvB ,Complementary bits for identifier in extended frame mode"
|
|
line.long 0x08 "CAN_MID7,CAN Message ID Register"
|
|
bitfld.long 0x08 29. " MIDE ,Identifier Version" "2.0 Part A,2.0 Part B"
|
|
hexmask.long.word 0x08 18.--28. 1. " MIDvA ,Identifier for standard frame mode"
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " MIDvB ,Complementary bits for identifier in extended frame mode"
|
|
rgroup.long (0x400B80E0+0x0C)++0x3
|
|
line.long 0x0 "CAN_MFID7,CAN Message Family ID Register"
|
|
hexmask.long 0x0 0.--28. 1. " MFID ,Family ID"
|
|
hgroup.long (0x400B80E0+0x10)++0x3
|
|
hide.long 0x04 "CAN_MSR7,CAN Message Status Register"
|
|
in
|
|
group.long (0x400B80E0+0x14)++0x7
|
|
line.long 0x00 "CAN_MDL7,CAN Message Data Low Register"
|
|
line.long 0x04 "CAN_MDH7,CAN Message Data High Register"
|
|
wgroup.long (0x400B80E0+0x1C)++0x3
|
|
line.long 0x00 "CAN_MCR7,CAN Message Control Register"
|
|
bitfld.long 0x00 23. " MTCR ,Mailbox Transfer Command" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " MACR ,Abort Request for Mailbox 7" "No effect,Aborted"
|
|
bitfld.long 0x00 20. " MRTR ,Mailbox Remote Transmission Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " MDLC ,Mailbox Data Length Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "EMAC (Ethernet MAC 10/100)"
|
|
base ad:0x400B0000
|
|
width 13.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "NCR,Network Control Register"
|
|
bitfld.long 0x00 10. " THALT ,Transmit halt" "No effect,Halt"
|
|
bitfld.long 0x00 9. " TSTART ,Start transmission" "No effect,Start"
|
|
bitfld.long 0x00 8. " BP ,Back pressure" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WESTAT ,Write enable for statistics registers" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INCSTAT ,Increment statistics registers" "No effect,Increment"
|
|
bitfld.long 0x00 5. " CLRSTAT ,Clear statistics registers" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MPE ,Management port enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmit enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receive enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LLB ,Loopback local" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LB ,LoopBack" "Disabled,Enabled"
|
|
line.long 0x04 "NCFGR,Network Configuration Register"
|
|
bitfld.long 0x04 19. " IRXFCS ,Ignore RX FCS" "Not ignored,Ignored"
|
|
bitfld.long 0x04 18. " EFRHD ,Enable Frames to be received in half-duplex mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " DRFCS ,Discard Receive FCS" "Not discarded,Discarded"
|
|
textline " "
|
|
bitfld.long 0x04 16. " RLCE ,Receive Length field Checking Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14.--15. " RBF ,Receive Buffer Offset" "No offset,One-byte,Two-byte,Three-byte"
|
|
bitfld.long 0x04 13. " PAE ,Pause Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RTY ,Retry test" "Normal operation,Retry test"
|
|
bitfld.long 0x04 10.--11. " CLK ,MDC clock divider" "/8,/16,/32,/64"
|
|
bitfld.long 0x04 8. " BIG ,Receive 1536 bytes frames" "Up to 1518 frames,Up to 1536 frames"
|
|
textline " "
|
|
bitfld.long 0x04 7. " UNI ,Unicast Hash Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " MTI ,Multicast Hash Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " NBC ,No Broadcast" "Broadcast,No broadcast"
|
|
textline " "
|
|
bitfld.long 0x04 4. " CAF ,Copy All Frames" "Not all frames,Copy all"
|
|
bitfld.long 0x04 3. " JFRAME ,Jumbo Frames" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " FD ,Full Duplex" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " SPD ,Speed" "10 Mbit/s,100 Mbit/s"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "NSR,Network Status Register"
|
|
bitfld.long 0x00 2. " IDLE ,PHY Management Logic Status" "PHY is running,PHY is idle"
|
|
bitfld.long 0x00 1. " MDIO ,Management Data Input/Output" "0,1"
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "TSR,Transmit Status Register"
|
|
eventfld.long 0x00 6. " UND ,Transmit Underrun" "No,Yes"
|
|
eventfld.long 0x00 5. " COMP ,Transmit Complete" "Not transmitted,Transmitted"
|
|
eventfld.long 0x00 4. " BEX ,Buffers exhausted mid frame" "No,Yes"
|
|
textline " "
|
|
eventfld.long 0x00 3. " TGO ,Transmit Go" "Not active,Active"
|
|
eventfld.long 0x00 2. " RLES ,Retry Limit exceeded" "No effect,Retry"
|
|
eventfld.long 0x00 1. " COL ,Collision Occurred" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " UBR ,Used Bit Read" "No effect,Read"
|
|
line.long 0x04 "RBQP,Receive Buffer Queue Pointer Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " ADDR ,Receive buffer queue pointer address"
|
|
if ((d.l(ad:0+0x14)&0x08)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TBQP,Transmit Buffer Queue Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " ADDR ,Transmit buffer queue pointer address"
|
|
else
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "TBQP,Transmit Buffer Queue Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " ADDR ,Transmit buffer queue pointer address"
|
|
endif
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "RSR,Receive Status Register"
|
|
eventfld.long 0x00 2. " OVR ,Receive Overrun" "No overrun,Overrun"
|
|
eventfld.long 0x00 1. " REC ,Frame Received" "Not received,Received"
|
|
eventfld.long 0x00 0. " BNA ,Buffer Not Available" "Available,Not available"
|
|
sif cpuis("ATSAMA5D3*")
|
|
textline " "
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "ISR,Interrupt Status Register"
|
|
in
|
|
textline " "
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PTZ_set/clr ,Pause Time Zero" "No action,Decremented to 0"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PFRE_set/clr ,PPause Frame Received" "Not received,Received"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " HRESP_set/clr ,Pause Time Zero" "No action,Bus error"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " ROVR_set/clr ,Pause Time Zero" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " TCOMP_set/clr ,Pause Time Zero" "Not complete,Complete"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " TXERR_set/clr ,Pause Time Zero" "No Error,Error"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " RLEX_set/clr ,Pause Time Zero" "Not exceeded,Exceeded"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " TUND_set/clr ,Pause Time Zero" "No action,Decremented to 0"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " TXUBR_set/clr ,Pause Time Zero" "No action,Decremented to 0"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " RXUBR_set/clr ,Pause Time Zero" "No action,Decremented to 0"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " RCOMP_set/clr ,Pause Time Zero" "No action,Decremented to 0"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " MFD_set/clr ,Pause Time Zero" "No action,Decremented to 0"
|
|
endif
|
|
sif cpuis("ATSAMA5D3*")
|
|
group.long 0x30++0x03
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " WOL_set/clr ,Wake On LAN" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " PTZ_set/clr ,Pause Time Zero" "Masked,Not masked"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " PFR_set/clr ,Pause Frame Received" "Masked,Not masked"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " HRESP_set/clr ,Hresp not OK" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " ROVR_set/clr ,Receive Overrun" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " TCOMP_set/clr ,Transmit Complete" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " TXERR_set/clr ,Transmit Error" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " RLE_set/clr ,Retry Limit Exceeded" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " TUND_set/clr ,Ethernet Transmit Buffer Underrun" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " TXUBR_set/clr ,Transmit Used Bit Read" "Masked,Not masked"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " RXUBR_set/clr ,Receive Used Bit Read" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " RCOMP_set/clr ,Receive Complete" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " MFD_set/clr ,Management Frame Done" "Masked,Not masked"
|
|
else
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x00 13. " PTZ ,Pause Time Zero" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " PFR ,Pause Frame Received" "Not masked,Masked"
|
|
bitfld.long 0x00 11. " HRESP ,Hresp not OK" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ROVR ,Receive Overrun" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " TCOMP ,Transmit Complete" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " TXERR ,Transmit buffers exhausted in mid-frame" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RLE ,Retry Limit Exceeded" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " TUND ,Ethernet Transmit Buffer Underrun" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " TXUBR ,Transmit Used Bit Read" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RXUBR ,Receive Used Bit Read" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " RCOMP ,Receive Complete" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " MFD ,Management Frame sent" "Not masked,Masked"
|
|
endif
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "MAN,PHY Maintenance Register"
|
|
bitfld.long 0x00 30.--31. " SOF ,Start of frame" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " RW ,Read-write" ",Write,Read,?..."
|
|
hexmask.long.byte 0x00 23.--27. 0x80 " PHYA ,PHY Address"
|
|
textline " "
|
|
hexmask.long.byte 0x00 18.--22. 0x04 " REGA ,Register Address"
|
|
bitfld.long 0x00 16.--17. " CODE ,Code" ",,2,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Data"
|
|
line.long 0x04 "PTR,Pause Time Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " PTIME ,Pause Time"
|
|
group.long 0x90++0x2B
|
|
line.long 0x00 "HRB,Hash Register Bottom"
|
|
line.long 0x04 "HRT,Hash Register Top"
|
|
line.long 0x08 "SA1B,Specific Address 1 Bottom Register"
|
|
line.long 0x0C "SA1T,Specific Address 1 Top Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " ADDR ,Address"
|
|
line.long 0x10 "SA2B,Specific Address 2 Bottom Register"
|
|
line.long 0x14 "SA2T,Specific Address 2 Top Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " ADDR ,Address"
|
|
line.long 0x18 "SA3B,Specific Address 3 Bottom Register"
|
|
line.long 0x1C "SA3T,Specific Address 3 Top Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " ADDR ,Address"
|
|
line.long 0x20 "SA4B,Specific Address 4 Bottom Register"
|
|
line.long 0x24 "SA4T,Specific Address 4 Top Register"
|
|
hexmask.long.word 0x24 0.--15. 1. " ADDR ,Address"
|
|
line.long 0x28 "TID,Type ID Checking Register"
|
|
hexmask.long.word 0x28 0.--15. 1. " TID ,Type ID checking"
|
|
group.long 0xC0++0x3
|
|
line.long 0x00 "USRIO,User Input/Output Register"
|
|
bitfld.long 0x00 1. " CLKEN ,Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("ATSAMA5D3*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 0. " RMII ,Reduce MII" "MII mode,RMII mode"
|
|
else
|
|
bitfld.long 0x00 0. " RMII ,Reduce MII" "MII mode,?..."
|
|
endif
|
|
sif cpuis("ATSAMA5D3*")
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "WOL,Wake-on-LAN Register"
|
|
bitfld.long 0x00 19. " MTI ,Multicast hash event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SA1 ,Specific address register 1 event enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ARP ,ARP request event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MAG ,Magic packet event enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--15. 1. " IP ,ARP request IP address"
|
|
endif
|
|
tree "Statistic Registers"
|
|
group.long 0x3C++0x4F
|
|
line.long 0x00 "PFR,Pause Frames Received Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " FROK ,Pause Frames received OK"
|
|
line.long 0x04 "FTO,Frames Transmitted OK Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " FTOK ,Frames Transmitted OK"
|
|
line.long 0x08 "SCF,Single Collision Frames Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " SCF ,Single Collision Frames"
|
|
line.long 0x0C "MCF,Multicollision Frames Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " MCF ,Multicollision Frames"
|
|
line.long 0x10 "FRO,Frames Received OK Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " FROK ,Frames Received OK"
|
|
line.long 0x14 "FCSE,Frames Check Sequence Errors Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " FCSE ,Frame Check Sequence Errors"
|
|
line.long 0x18 "ALE,Alignment Errors Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " ALE ,Alignment Errors"
|
|
line.long 0x1C "DTF,Deferred Transmission Frames Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " DTF ,Deferred Transmission Frames"
|
|
line.long 0x20 "LCOL,Late Collisions Register"
|
|
hexmask.long.byte 0x20 0.--7. 1. " LCOL ,Late Collisions"
|
|
line.long 0x24 "ECOL,Excessive Collisions Register"
|
|
hexmask.long.byte 0x24 0.--7. 1. " EXCOL ,Excessive Collisions"
|
|
line.long 0x28 "TUND,Transmit Underrun Errors Register"
|
|
hexmask.long.byte 0x28 0.--7. 1. " TUND ,Transmit Underruns"
|
|
line.long 0x2C "CSE,Carrier Sense Errors Register"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " CSE ,Carrier Sense Errors"
|
|
line.long 0x30 "RRE,Receive Resource Errors Register"
|
|
hexmask.long.word 0x30 0.--15. 1. " RRE ,Receive Resource Errors"
|
|
line.long 0x34 "ROV,Receive Overrun Errors Register"
|
|
hexmask.long.byte 0x34 0.--7. 1. " ROVR ,Receive Overrun"
|
|
line.long 0x38 "RSE,Receive Symbol Errors Register"
|
|
hexmask.long.byte 0x38 0.--7. 1. " RSE ,Receive Symbol Errors"
|
|
line.long 0x3C "ELE,Excessive Length Errors Register"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " EXL ,Excessive Length Errors"
|
|
line.long 0x40 "RJA,Receive Jabbers Register"
|
|
hexmask.long.byte 0x40 0.--7. 1. " RJB ,Receive Jabbers"
|
|
line.long 0x44 "USF,Undersize Frames Register"
|
|
hexmask.long.byte 0x44 0.--7. 1. " USF ,Undersize frames"
|
|
line.long 0x48 "STE,SQE Test Errors Register"
|
|
hexmask.long.byte 0x48 0.--7. 1. " SQER ,SQE test errors"
|
|
line.long 0x4C "RLE,Received Length Field Mismatch Register"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " RLFM ,Receive Length Field Mismatch"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "TRNG (True Random Number Generator)"
|
|
base ad:0x400BC000
|
|
width 13.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,TRNG Control Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " KEY ,Security key"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the TRNG to provide random values" "Disable,Enable"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IMR_SET/CLR,TRNG Interrupt Mask Register"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DATRDY ,Data ready" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "ISR,TRNG Interrupt Status Register"
|
|
in
|
|
newline
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "ODATA,TRNG Output Data Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ADC (Analog-to-Digital Converter)"
|
|
base ad:0x400C0000
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "ADC_CR,ADC Control Register"
|
|
bitfld.long 0x00 1. " START ,Conversion Start" "No effect,Start"
|
|
bitfld.long 0x00 0. " SWRST ,Software Reset" "No effect,Reset"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ADC_MR,ADC Mode Register"
|
|
bitfld.long 0x00 31. " USEQ ,User Sequence Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 28.--29. " TRANSFER ,Transfer Period" "3,5,7,9"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " TRACKTIM ,Tracking Time" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 23. " ANACH ,Analog Change" "None,Allowed"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 20.--21. " SETTLING ,Analog Settling Time" "3,5,9,17"
|
|
elif (!cpuis("AT91SAM3N*"))
|
|
bitfld.long 0x00 20.--21. " SETTLING ,Analog Settling Time" "1,2,3,4"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " STARTUP ,Start Up Time" "0,8,16,24,64,80,96,112,512,576,640,704,768,832,896,960"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCAL ,Prescaler Rate Selection"
|
|
bitfld.long 0x00 7. " FREERUN ,Free Run Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FWUP ,Fast Wake Up" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SLEEP ,Sleep Mode" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 4. " LOWRES ,Selected Resolution" "12 bit,10 bit"
|
|
bitfld.long 0x00 1.--3. " TRGSEL ,Trigger Selection" "External,TIO Output of the TC C0,TIO Output of the TC C1,TIO Output of the TC C2,PWM Event Line 0,PWM Event Line 1,?..."
|
|
else
|
|
bitfld.long 0x00 4. " LOWRES ,Selected Resolution" "10 bit,8 bit"
|
|
bitfld.long 0x00 1.--3. " TRGSEL ,Trigger Selection" "External,TIO Output of the TC C0,TIO Output of the TC C1,TIO Output of the TC C2,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " TRGEN ,Trigger Enable" "Disabled,Enabled"
|
|
if (((data.long((ad:0x400C0000+0x04)))&0x80000000)==0x80000000)
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "ADC_SEQR1,ADC Channel Sequence 1 Register"
|
|
bitfld.long 0x00 28.--31. " USCH8 ,User Sequence Number 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " USCH7 ,User Sequence Number 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " USCH6 ,User Sequence Number 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " USCH5 ,User Sequence Number 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " USCH4 ,User Sequence Number 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " USCH3 ,User Sequence Number 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " USCH2 ,User Sequence Number 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " USCH1 ,User Sequence Number 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif ((cpuis("AT91SAM3N*C")||cpuis("AT91SAM3N00A")||cpuis("AT91SAM3N00B")||cpuis("AT91SAM3N0A")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N0C"))||cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC_SEQR2,ADC Channel Sequence 2 Register"
|
|
bitfld.long 0x00 28.--31. " USCH16 ,User Sequence Number 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " USCH15 ,User Sequence Number 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " USCH14 ,User Sequence Number 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " USCH13 ,User Sequence Number 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " USCH12 ,User Sequence Number 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " USCH11 ,User Sequence Number 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " USCH10 ,User Sequence Number 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " USCH9 ,User Sequence Number 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
elif (cpuis("AT91SAM3N*B"))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC_SEQR2,ADC Channel Sequence 2 Register"
|
|
bitfld.long 0x00 4.--7. " USCH10 ,User Sequence Number 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " USCH9 ,User Sequence Number 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
else
|
|
hgroup.long 0x8++0x3
|
|
hide.long 0x00 "ADC_SEQR1,ADC Channel Sequence 1 Register"
|
|
sif ((cpuis("AT91SAM3N*B"))||(cpuis("AT91SAM3N*C"))||cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
hgroup.long 0xC++0x3
|
|
hide.long 0x00 "ADC_SEQR2,ADC Channel Sequence 2 Register"
|
|
endif
|
|
endif
|
|
sif ((cpuis("AT91SAM3N*C")||cpuis("AT91SAM3N00A")||cpuis("AT91SAM3N00B")||cpuis("AT91SAM3N0A")||cpuis("AT91SAM3N0B")||cpuis("AT91SAM3N0C"))||cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ADC_CHSR,ADC Channel Status Register"
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " CH15_Clear/Set ,Channel 15 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " CH14_Clear/Set ,Channel 14 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " CH13_Clear/Set ,Channel 13 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " CH12_Clear/Set ,Channel 12 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " CH11_Clear/Set ,Channel 11 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " CH10_Clear/Set ,Channel 10 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " CH9_Clear/Set ,Channel 9 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " CH8_Clear/Set ,Channel 8 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " CH7_Clear/Set ,Channel 7 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " CH6_Clear/Set ,Channel 6 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " CH5_Clear/Set ,Channel 5 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " CH4_Clear/Set ,Channel 4 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " CH3_Clear/Set ,Channel 3 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 4. -0x4 2. " CH2_Clear/Set ,Channel 2 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " CH1_Clear/Set ,Channel 1 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " CH0_Clear/Set ,Channel 0 Status" "Disabled,Enabled"
|
|
elif (cpuis("AT91SAM3N*B"))
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ADC_CHSR,ADC Channel Status Register"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " CH9_Clear/Set ,Channel 9 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " CH8_Clear/Set ,Channel 8 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " CH7_Clear/Set ,Channel 7 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " CH6_Clear/Set ,Channel 6 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " CH5_Clear/Set ,Channel 5 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " CH4_Clear/Set ,Channel 4 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " CH3_Clear/Set ,Channel 3 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 4. -0x4 2. " CH2_Clear/Set ,Channel 2 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " CH1_Clear/Set ,Channel 1 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " CH0_Clear/Set ,Channel 0 Status" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ADC_CHSR,ADC Channel Status Register"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " CH7_Clear/Set ,Channel 7 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " CH6_Clear/Set ,Channel 6 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " CH5_Clear/Set ,Channel 5 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " CH4_Clear/Set ,Channel 4 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " CH3_Clear/Set ,Channel 3 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 4. -0x4 2. " CH2_Clear/Set ,Channel 2 Status" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " CH1_Clear/Set ,Channel 1 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " CH0_Clear/Set ,Channel 0 Status" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long 0x20++0x3
|
|
hide.long 0x00 "ADC_LCDR,ADC Last Data Converted"
|
|
in
|
|
sif (cpuis("AT91SAM3N*C")||cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long 0x2c++0x03
|
|
line.long 0x0 "ADC_IMR,ADC Interrupt Mask Register"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " RXBUFF ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " ENDRX ,Receive Buffer End Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " COMPE ,Comparison Event Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " GOVRE ,General Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " DRDY ,Data Ready Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " EOC15 ,Conversion End Interrupt Mask 15" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " EOC14 ,Conversion End Interrupt Mask 14" "Disabled,Enabled"
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " EOC13 ,Conversion End Interrupt Mask 13" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " EOC12 ,Conversion End Interrupt Mask 12" "Disabled,Enabled"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " EOC11 ,Conversion End Interrupt Mask 11" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " EOC10 ,Conversion End Interrupt Mask 10" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " EOC9 ,Conversion End Interrupt Mask 9" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " EOC8 ,Conversion End Interrupt Mask 8" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " EOC7 ,Conversion End Interrupt Mask 7" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " EOC6 ,Conversion End Interrupt Mask 6" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " EOC5 ,Conversion End Interrupt Mask 5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " EOC4 ,Conversion End Interrupt Mask 4" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " EOC3 ,Conversion End Interrupt Mask 3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " EOC2 ,Conversion End Interrupt Mask 2" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " EOC1 ,Conversion End Interrupt Mask 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " EOC0 ,Conversion End Interrupt Mask 0" "Disabled,Enabled"
|
|
elif (cpuis("AT91SAM3N*B"))
|
|
group.long 0x2c++0x03
|
|
line.long 0x0 "ADC_IMR,ADC Interrupt Mask Register"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " RXBUFF ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " ENDRX ,Receive Buffer End Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " COMPE ,Comparison Event Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " GOVRE ,General Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " DRDY ,Data Ready Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " EOC9 ,Conversion End Interrupt Mask 9" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " EOC8 ,Conversion End Interrupt Mask 8" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " EOC7 ,Conversion End Interrupt Mask 7" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " EOC6 ,Conversion End Interrupt Mask 6" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " EOC5 ,Conversion End Interrupt Mask 5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " EOC4 ,Conversion End Interrupt Mask 4" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " EOC3 ,Conversion End Interrupt Mask 3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " EOC2 ,Conversion End Interrupt Mask 2" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " EOC1 ,Conversion End Interrupt Mask 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " EOC0 ,Conversion End Interrupt Mask 0" "Disabled,Enabled"
|
|
else
|
|
group.long 0x2c++0x03
|
|
line.long 0x0 "ADC_IMR,ADC Interrupt Mask Register"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " RXBUFF ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " ENDRX ,Receive Buffer End Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " COMPE ,Comparison Event Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " GOVRE ,General Overrun Error Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 24. -0x8 24. -0x4 24. " DRDY ,Data Ready Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " EOC7 ,Conversion End Interrupt Mask 7" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " EOC6 ,Conversion End Interrupt Mask 6" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " EOC5 ,Conversion End Interrupt Mask 5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " EOC4 ,Conversion End Interrupt Mask 4" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " EOC3 ,Conversion End Interrupt Mask 3" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " EOC2 ,Conversion End Interrupt Mask 2" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " EOC1 ,Conversion End Interrupt Mask 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " EOC0 ,Conversion End Interrupt Mask 0" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "ADC_ISR,ADC Interrupt Status Register"
|
|
in
|
|
hgroup.long 0x3C++0x03
|
|
hide.long 0x00 "ADC_OVER,ADC Overrun Status Register"
|
|
in
|
|
sif (cpuis("AT91SAM3N*")||cpuis("AT91SAM3A4C")||cpuis("AT91SAM3A8C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
group.long 0x40++0x7
|
|
line.long 0x00 "ADC_EMR,ADC Extended Mode Register"
|
|
bitfld.long 0x00 24. " TAG ,TAG of ADC_LCDR register" "CHNB to zero,Channel number"
|
|
sif (cpuis("AT91SAM3A*")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
bitfld.long 0x00 12.--13. " CMPFILTER ,Compare Event Filtering" "1,2,3,4"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " CMPALL ,Compare All Channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CMPSEL ,Comparison Selected Channel(CMPALL must be 0)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--1. " CMPMODE ,Comparison Mode" "LOW,HIGH,IN,OUT"
|
|
line.long 0x04 "ADC_CWR,ADC Compare Window Register"
|
|
hexmask.long.word 0x04 16.--27. 1. " HIGHTHRES ,High Threshold"
|
|
hexmask.long.word 0x04 0.--11. 1. " LOWTHRES ,Low Threshold"
|
|
group.long 0x48++0x7
|
|
line.long 0x00 "ADC_CGR,ADC Channel Gain Register"
|
|
sif (!cpuis("AT91SAM3N*B"))
|
|
sif (!cpuis("AT91SAM3N*A"))
|
|
bitfld.long 0x00 30.--31. " GAIN15 ,Gain for channel 15(DIFF15 0/1)" "1/0.5,1/1,2/2,4/2"
|
|
bitfld.long 0x00 28.--29. " GAIN14 ,Gain for channel 14(DIFF14 0/1)" "1/0.5,1/1,2/2,4/2"
|
|
bitfld.long 0x00 26.--27. " GAIN13 ,Gain for channel 13(DIFF13 0/1)" "1/0.5,1/1,2/2,4/2"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " GAIN12 ,Gain for channel 12(DIFF12 0/1)" "1/0.5,1/1,2/2,4/2"
|
|
bitfld.long 0x00 22.--23. " GAIN11 ,Gain for channel 11(DIFF11 0/1)" "1/0.5,1/1,2/2,4/2"
|
|
bitfld.long 0x00 20.--21. " GAIN10 ,Gain for channel 10(DIFF10 0/1)" "1/0.5,1/1,2/2,4/2"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18.--19. " GAIN9 ,Gain for channel 9(DIFF9 0/1)" "1/0.5,1/1,2/2,4/2"
|
|
bitfld.long 0x00 16.--17. " GAIN8 ,Gain for channel 8(DIFF8 0/1)" "1/0.5,1/1,2/2,4/2"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " GAIN7 ,Gain for channel 7(DIFF7 0/1)" "1/0.5,1/1,2/2,4/2"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " GAIN6 ,Gain for channel 6(DIFF6 0/1)" "1/0.5,1/1,2/2,4/2"
|
|
bitfld.long 0x00 10.--11. " GAIN5 ,Gain for channel 5(DIFF5 0/1)" "1/0.5,1/1,2/2,4/2"
|
|
bitfld.long 0x00 8.--9. " GAIN4 ,Gain for channel 4(DIFF4 0/1)" "1/0.5,1/1,2/2,4/2"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " GAIN3 ,Gain for channel 3(DIFF3 0/1)" "1/0.5,1/1,2/2,4/2"
|
|
bitfld.long 0x00 4.--5. " GAIN2 ,Gain for channel 2(DIFF2 0/1)" "1/0.5,1/1,2/2,4/2"
|
|
bitfld.long 0x00 2.--3. " GAIN1 ,Gain for channel 1(DIFF1 0/1)" "1/0.5,1/1,2/2,4/2"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " GAIN0 ,Gain for channel 0(DIFF0 0/1)" "1/0.5,1/1,2/2,4/2"
|
|
line.long 0x04 "ADC_COR,ADC Channel Offset Register"
|
|
sif (!cpuis("AT91SAM3N*B"))
|
|
sif (!cpuis("AT91SAM3N*A"))
|
|
bitfld.long 0x04 31. " DIFF15 ,Differential inputs for channel 15" "Single Ended,Fully Differential"
|
|
bitfld.long 0x04 30. " DIFF14 ,Differential inputs for channel 14" "Single Ended,Fully Differential"
|
|
bitfld.long 0x04 29. " DIFF13 ,Differential inputs for channel 13" "Single Ended,Fully Differential"
|
|
textline " "
|
|
bitfld.long 0x04 28. " DIFF12 ,Differential inputs for channel 12" "Single Ended,Fully Differential"
|
|
bitfld.long 0x04 27. " DIFF11 ,Differential inputs for channel 11" "Single Ended,Fully Differential"
|
|
bitfld.long 0x04 26. " DIFF10 ,Differential inputs for channel 10" "Single Ended,Fully Differential"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 25. " DIFF9 ,Differential inputs for channel 9" "Single Ended,Fully Differential"
|
|
bitfld.long 0x04 24. " DIFF8 ,Differential inputs for channel 8" "Single Ended,Fully Differential"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 23. " DIFF7 ,Differential inputs for channel 7" "Single Ended,Fully Differential"
|
|
textline " "
|
|
bitfld.long 0x04 22. " DIFF6 ,Differential inputs for channel 6" "Single Ended,Fully Differential"
|
|
bitfld.long 0x04 21. " DIFF5 ,Differential inputs for channel 5" "Single Ended,Fully Differential"
|
|
bitfld.long 0x04 20. " DIFF4 ,Differential inputs for channel 4" "Single Ended,Fully Differential"
|
|
textline " "
|
|
bitfld.long 0x04 19. " DIFF3 ,Differential inputs for channel 3" "Single Ended,Fully Differential"
|
|
bitfld.long 0x04 18. " DIFF2 ,Differential inputs for channel 2" "Single Ended,Fully Differential"
|
|
bitfld.long 0x04 17. " DIFF1 ,Differential inputs for channel 1" "Single Ended,Fully Differential"
|
|
textline " "
|
|
bitfld.long 0x04 16. " DIFF0 ,Differential inputs for channel 0" "Single Ended,Fully Differential"
|
|
sif (!cpuis("AT91SAM3N*B"))
|
|
sif (!cpuis("AT91SAM3N*A"))
|
|
textline " "
|
|
bitfld.long 0x04 15. " OFF15 ,Offset for channel 15" "No offset,Offset"
|
|
textline " "
|
|
bitfld.long 0x04 14. " OFF14 ,Offset for channel 14" "No offset,Offset"
|
|
bitfld.long 0x04 13. " OFF13 ,Offset for channel 13" "No offset,Offset"
|
|
textline " "
|
|
bitfld.long 0x04 12. " OFF12 ,Offset for channel 12" "No offset,Offset"
|
|
bitfld.long 0x04 11. " OFF11 ,Offset for channel 11" "No offset,Offset"
|
|
bitfld.long 0x04 10. " OFF10 ,Offset for channel 10" "No offset,Offset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 9. " OFF9 ,Offset for channel 9" "No offset,Offset"
|
|
bitfld.long 0x04 8. " OFF8 ,Offset for channel 8" "No offset,Offset"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 7. " OFF7 ,Offset for channel 7" "No offset,Offset"
|
|
textline " "
|
|
bitfld.long 0x04 6. " OFF6 ,Offset for channel 6" "No offset,Offset"
|
|
bitfld.long 0x04 5. " OFF5 ,Offset for channel 5" "No offset,Offset"
|
|
bitfld.long 0x04 4. " OFF4 ,Offset for channel 4" "No offset,Offset"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OFF3 ,Offset for channel 3" "No offset,Offset"
|
|
bitfld.long 0x04 2. " OFF2 ,Offset for channel 2" "No offset,Offset"
|
|
bitfld.long 0x04 1. " OFF1 ,Offset for channel 1" "No offset,Offset"
|
|
textline " "
|
|
bitfld.long 0x04 0. " OFF0 ,Offset for channel 0" "No offset,Offset"
|
|
endif
|
|
sif (cpuis("AT91SAM3A8C")||cpuis("AT91SAM3A4C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long 0x50++0x3F
|
|
line.long 0x0 "ADC_CDR0,ADC Channel 0 Data Register"
|
|
hexmask.long.word 0x0 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0x4 "ADC_CDR1,ADC Channel 1 Data Register"
|
|
hexmask.long.word 0x4 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0x8 "ADC_CDR2,ADC Channel 2 Data Register"
|
|
hexmask.long.word 0x8 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0xC "ADC_CDR3,ADC Channel 3 Data Register"
|
|
hexmask.long.word 0xC 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0x10 "ADC_CDR4,ADC Channel 4 Data Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0x14 "ADC_CDR5,ADC Channel 5 Data Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0x18 "ADC_CDR6,ADC Channel 6 Data Register"
|
|
hexmask.long.word 0x18 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0x1C "ADC_CDR7,ADC Channel 7 Data Register"
|
|
hexmask.long.word 0x1C 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0x20 "ADC_CDR8,ADC Channel 8 Data Register"
|
|
hexmask.long.word 0x20 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0x24 "ADC_CDR9,ADC Channel 9 Data Register"
|
|
hexmask.long.word 0x24 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0x28 "ADC_CDR10,ADC Channel 10 Data Register"
|
|
hexmask.long.word 0x28 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0x2C "ADC_CDR11,ADC Channel 11 Data Register"
|
|
hexmask.long.word 0x2C 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0x30 "ADC_CDR12,ADC Channel 12 Data Register"
|
|
hexmask.long.word 0x30 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0x34 "ADC_CDR13,ADC Channel 13 Data Register"
|
|
hexmask.long.word 0x34 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0x38 "ADC_CDR14,ADC Channel 14 Data Register"
|
|
hexmask.long.word 0x38 0.--11. 1. " DATA ,Converted Data"
|
|
line.long 0x3C "ADC_CDR15,ADC Channel 15 Data Register"
|
|
hexmask.long.word 0x3C 0.--11. 1. " DATA ,Converted Data"
|
|
elif (cpuis("AT91SAM3N*B"))
|
|
group.long 0x40++0x7
|
|
line.long 0x00 "ADC_EMR,ADC Extended Mode Register"
|
|
bitfld.long 0x00 24. " TAG ,TAG of ADC_LCDR register" "CHNB to zero,Channel number"
|
|
bitfld.long 0x00 9. " CMPALL ,Compare All Channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CMPSEL ,Comparison Selected Channel" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 0.--1. " CMPMODE ,Comparison Mode" "LOW,HIGH,IN,OUT"
|
|
line.long 0x04 "ADC_CWR,ADC Compare Window Register"
|
|
hexmask.long.word 0x04 16.--27. 1. " HIGHTHRES ,High Threshold"
|
|
hexmask.long.word 0x04 0.--11. 1. " LOWTHRES ,Low Threshold"
|
|
rgroup.long 0x50++0x2B
|
|
line.long 0x0 "ADC_CDR0,ADC Channel 0 Data Register"
|
|
hexmask.long.word 0x0 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x4 "ADC_CDR1,ADC Channel 1 Data Register"
|
|
hexmask.long.word 0x4 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x8 "ADC_CDR2,ADC Channel 2 Data Register"
|
|
hexmask.long.word 0x8 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0xC "ADC_CDR3,ADC Channel 3 Data Register"
|
|
hexmask.long.word 0xC 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x10 "ADC_CDR4,ADC Channel 4 Data Register"
|
|
hexmask.long.word 0x10 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x14 "ADC_CDR5,ADC Channel 5 Data Register"
|
|
hexmask.long.word 0x14 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x18 "ADC_CDR6,ADC Channel 6 Data Register"
|
|
hexmask.long.word 0x18 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x1C "ADC_CDR7,ADC Channel 7 Data Register"
|
|
hexmask.long.word 0x1C 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x20 "ADC_CDR8,ADC Channel 8 Data Register"
|
|
hexmask.long.word 0x20 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x24 "ADC_CDR9,ADC Channel 9 Data Register"
|
|
hexmask.long.word 0x24 0.--9. 1. " DATA ,Converted Data"
|
|
elif (cpuis("AT91SAM3N*A"))
|
|
group.long 0x40++0x7
|
|
line.long 0x00 "ADC_EMR,ADC Extended Mode Register"
|
|
bitfld.long 0x00 24. " TAG ,TAG of ADC_LCDR register" "CHNB to zero,Channel number"
|
|
bitfld.long 0x00 9. " CMPALL ,Compare All Channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CMPSEL ,Comparison Selected Channel" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 0.--1. " CMPMODE ,Comparison Mode" "LOW,HIGH,IN,OUT"
|
|
line.long 0x04 "ADC_CWR,ADC Compare Window Register"
|
|
hexmask.long.word 0x04 16.--27. 1. " HIGHTHRES ,High Threshold"
|
|
hexmask.long.word 0x04 0.--11. 1. " LOWTHRES ,Low Threshold"
|
|
rgroup.long 0x50++0x1F
|
|
line.long 0x0 "ADC_CDR0,ADC Channel 0 Data Register"
|
|
hexmask.long.word 0x0 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x4 "ADC_CDR1,ADC Channel 1 Data Register"
|
|
hexmask.long.word 0x4 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x8 "ADC_CDR2,ADC Channel 2 Data Register"
|
|
hexmask.long.word 0x8 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0xC "ADC_CDR3,ADC Channel 3 Data Register"
|
|
hexmask.long.word 0xC 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x10 "ADC_CDR4,ADC Channel 4 Data Register"
|
|
hexmask.long.word 0x10 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x14 "ADC_CDR5,ADC Channel 5 Data Register"
|
|
hexmask.long.word 0x14 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x18 "ADC_CDR6,ADC Channel 6 Data Register"
|
|
hexmask.long.word 0x18 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x1C "ADC_CDR7,ADC Channel 7 Data Register"
|
|
hexmask.long.word 0x1C 0.--9. 1. " DATA ,Converted Data"
|
|
elif (cpuis("AT91SAM3N*C"))
|
|
group.long 0x40++0x7
|
|
line.long 0x00 "ADC_EMR,ADC Extended Mode Register"
|
|
bitfld.long 0x00 24. " TAG ,TAG of ADC_LCDR register" "CHNB to zero,Channel number"
|
|
bitfld.long 0x00 9. " CMPALL ,Compare All Channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CMPSEL ,Comparison Selected Channel" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 0.--1. " CMPMODE ,Comparison Mode" "LOW,HIGH,IN,OUT"
|
|
line.long 0x04 "ADC_CWR,ADC Compare Window Register"
|
|
hexmask.long.word 0x04 16.--27. 1. " HIGHTHRES ,High Threshold"
|
|
hexmask.long.word 0x04 0.--11. 1. " LOWTHRES ,Low Threshold"
|
|
rgroup.long 0x50++0x3F
|
|
line.long 0x0 "ADC_CDR0,ADC Channel 0 Data Register"
|
|
hexmask.long.word 0x0 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x4 "ADC_CDR1,ADC Channel 1 Data Register"
|
|
hexmask.long.word 0x4 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x8 "ADC_CDR2,ADC Channel 2 Data Register"
|
|
hexmask.long.word 0x8 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0xC "ADC_CDR3,ADC Channel 3 Data Register"
|
|
hexmask.long.word 0xC 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x10 "ADC_CDR4,ADC Channel 4 Data Register"
|
|
hexmask.long.word 0x10 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x14 "ADC_CDR5,ADC Channel 5 Data Register"
|
|
hexmask.long.word 0x14 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x18 "ADC_CDR6,ADC Channel 6 Data Register"
|
|
hexmask.long.word 0x18 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x1C "ADC_CDR7,ADC Channel 7 Data Register"
|
|
hexmask.long.word 0x1C 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x20 "ADC_CDR8,ADC Channel 8 Data Register"
|
|
hexmask.long.word 0x20 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x24 "ADC_CDR9,ADC Channel 9 Data Register"
|
|
hexmask.long.word 0x24 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x28 "ADC_CDR10,ADC Channel 10 Data Register"
|
|
hexmask.long.word 0x28 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x2C "ADC_CDR11,ADC Channel 11 Data Register"
|
|
hexmask.long.word 0x2C 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x30 "ADC_CDR12,ADC Channel 12 Data Register"
|
|
hexmask.long.word 0x30 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x34 "ADC_CDR13,ADC Channel 13 Data Register"
|
|
hexmask.long.word 0x34 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x38 "ADC_CDR14,ADC Channel 14 Data Register"
|
|
hexmask.long.word 0x38 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x3C "ADC_CDR15,ADC Channel 15 Data Register"
|
|
hexmask.long.word 0x3C 0.--9. 1. " DATA ,Converted Data"
|
|
else
|
|
group.long 0x40++0x7
|
|
line.long 0x00 "ADC_EMR,ADC Extended Mode Register"
|
|
bitfld.long 0x00 24. " TAG ,TAG of ADC_LCDR register" "CHNB to zero,Channel number"
|
|
bitfld.long 0x00 9. " CMPALL ,Compare All Channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CMPSEL ,Comparison Selected Channel" "0,1,2,3,4,5,6,7,?..."
|
|
bitfld.long 0x00 0.--1. " CMPMODE ,Comparison Mode" "LOW,HIGH,IN,OUT"
|
|
line.long 0x04 "ADC_CWR,ADC Compare Window Register"
|
|
hexmask.long.word 0x04 16.--27. 1. " HIGHTHRES ,High Threshold"
|
|
hexmask.long.word 0x04 0.--11. 1. " LOWTHRES ,Low Threshold"
|
|
rgroup.long 0x50++0x1f
|
|
line.long 0x0 "ADC_CDR0,ADC Channel 0 Data Register"
|
|
hexmask.long.word 0x0 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x4 "ADC_CDR1,ADC Channel 1 Data Register"
|
|
hexmask.long.word 0x4 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x8 "ADC_CDR2,ADC Channel 2 Data Register"
|
|
hexmask.long.word 0x8 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0xC "ADC_CDR3,ADC Channel 3 Data Register"
|
|
hexmask.long.word 0xC 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x10 "ADC_CDR4,ADC Channel 4 Data Register"
|
|
hexmask.long.word 0x10 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x14 "ADC_CDR5,ADC Channel 5 Data Register"
|
|
hexmask.long.word 0x14 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x18 "ADC_CDR6,ADC Channel 6 Data Register"
|
|
hexmask.long.word 0x18 0.--9. 1. " DATA ,Converted Data"
|
|
line.long 0x1C "ADC_CDR7,ADC Channel 7 Data Register"
|
|
hexmask.long.word 0x1C 0.--9. 1. " DATA ,Converted Data"
|
|
endif
|
|
sif (cpuis("AT91SAM3A8C")||cpuis("AT91SAM3A4C")||cpuis("AT91SAM3X4C")||cpuis("AT91SAM3X4E")||cpuis("AT91SAM3X8C")||cpuis("AT91SAM3X8E"))
|
|
rgroup.long 0x94++0x3
|
|
line.long 0x00 "ADC_ACR,ADC Analog Control Register"
|
|
bitfld.long 0x00 8.--9. " IBCTL ,ADC Bias Current Control" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TSON ,Temperature Sensor On" "Off,On"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "ADC_WPMR,ADC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
|
|
textline " "
|
|
bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x3
|
|
hide.long 0x00 "ADC_WPSR,ADC Write Protect Status Register"
|
|
in
|
|
width 0xb
|
|
tree.end
|
|
tree "DACC (Analog Converter Controller)"
|
|
base ad:0x400C8000
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "DACC_CR,DACC Control Register"
|
|
bitfld.long 0x00 0. " SWRST ,Software Reset" "No effect,Reset"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DACC_MR,DACC Mode Register"
|
|
sif cpuis("ATSAM4E*")
|
|
bitfld.long 0x00 24.--29. " STARTUP ,Startup Time Selection (in DACClock periods)" "0,8,16,24,64,80,96,112,512,576,640,704,768,832,896,960,1024,1088,1152,1216,1280,1344,1408,1472,1536,1600,1664,1728,1792,1856,1920,1984,2048,2112,2176,2240,2304,2368,2432,2496,2560,2624,2688,2688,2816,2880,2944,3008,3072,3136,3200,3264,3328,3392,3456,3520,3584,3648,3712,3776,3840,3904,3968,4032"
|
|
bitfld.long 0x00 22. " CLKDIV ,Clock Divider" "MCK/2,MCK/4"
|
|
else
|
|
bitfld.long 0x00 24.--29. " STARTUP ,Startup Time Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21. " MAXS ,Max Speed Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TAG ,Tag Selection Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " USER_SEL ,User Channel Selection" "CHANNEL0,CHANNEL1,?..."
|
|
hexmask.long.byte 0x00 8.--15. 1. " REFRESH ,Refresh Period"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FASTWKUP ,Fast Wake up Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SLEEP ,Sleep Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WORD ,Word Transfer" "Half-Word,Word"
|
|
bitfld.long 0x00 1.--3. " TRGSEL ,Trigger Selection" "External,TIO Output of the TC C0,TIO Output of the TC C1,TIO Output of the TC C2,PWM Event Line 0,PWM Event Line 1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " TRGEN ,Trigger Enable" "Disabled,Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "DACC_CHSR,DACC Channel Status Register"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " CH1_set/clr ,Channel 1 Status" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " CH0_set/clr ,Channel 0 Status" "Disabled,Enabled"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "DACC_CDR,DACC Conversion Data Register"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "DACC_IMR,DACC Interrupt Mask Register"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " EOC_set/clr ,End of Conversion Interrupt Mask" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " TXRDY_set/clr ,Transmit Ready Interrupt Mask" "Disabled,Enabled"
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "DACC_ISR,DACC Interrupt Status Register"
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in
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group.long 0x94++0x03
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line.long 0x00 "DACC_ACR,DACC Analog Current Register"
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bitfld.long 0x00 8.--9. " IBCTLDACCORE ,Bias Current Control for DAC Core" "0,1,2,3"
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bitfld.long 0x00 2.--3. " IBCTLCH1 ,Analog Output Current Control 1" "0,1,2,3"
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textline " "
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bitfld.long 0x00 0.--1. " IBCTLCH0 ,Analog Output Current Control 0" "0,1,2,3"
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group.long 0xE4++0x03
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line.long 0x00 "DACC_WPMR,DACC Write Protect Mode Register"
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hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write Protect KEY"
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bitfld.long 0x00 0. " WPEN ,Write Protect Enable" "Disabled,Enabled"
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hgroup.long 0xE8++0x03
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hide.long 0x00 "DACC_WPSR,DACC Write Protect Status Register"
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in
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width 0x0B
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tree.end
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textline ""
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