17400 lines
1.1 MiB
17400 lines
1.1 MiB
; --------------------------------------------------------------------------------
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; @Title: ARMv8 MMU600 System MMU Global Config
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; @Description: PER file to show SMMU Stream Map Group and Context Bank registers
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; @Props: Released
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; @Author: KRZ
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; @Changelog: 2020-10-22 KRZ
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; @Manufacturer: ARM - ARM Ltd.
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; @Doc: SMMUv3_architecture_specification_IHI0070B.pdf (2017-06-14, issue B)
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; corelink_mmu600_system_memory_management_unit_technical_reference_manual_100310_0201_00_en.pdf (2018-10-05, issue 0201-00)
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; corelink_mmu600_system_memory_management_unit_technical_reference_manual_100310_0202_00_en.pdf (2020-05-07, issue 0202-00)
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; IHI_0070_D_a_System_Memory_Management_Unit_Arm_Architecture_Specification.pdf (2020-08-31, issue D.a)
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; @Core: ARMv8
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; @Copyright: (C) 1989-2020 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perarmsmmu600.per 12458 2020-10-22 14:32:00Z kwitkowski $
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AUTOINDENT.ON CENTER TREE
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endian.le
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entry &SMMU_name="unknown" &SMMU_base=D:0x0 &STE_base=D:0x0 &CD_base=D:0x0 &PMU_base=D:0x0 &MMU600_base=D:0x0
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wait per.l(&SMMU_base)
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sif ("&SMMU_base"!="-")
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base &SMMU_base
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tree "System MMU '&SMMU_name' (MMU600) - Global Configuration Registers"
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rgroup.long 0x00++0x0F "Non-secure Stream Configuration Registers"
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line.long 0x00 "SMMU_IDR0,SMMU Feature Identification Register 0"
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bitfld.long 0x00 27.--28. "ST_LEVEL,Multi-level stream table support" "Linear,Linear / 2-level,?..."
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bitfld.long 0x00 26. "TERM_MODEL,Terminate model behavior" "CD.A flag dependent,Always abort"
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bitfld.long 0x00 24.--25. "STALL_MODEL,Stall model support" "Supported,Not supported,Forced,?..."
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newline
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bitfld.long 0x00 21.--22. "TTENDIAN,Endianness support for translation table walks" "Mixed-endian,Reserved,Little-endian,Big-endian"
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bitfld.long 0x00 20. "VATOS,Virtual ATOS page interface support" "Not supported,Supported"
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newline
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bitfld.long 0x00 19. "CD2L,2-level context descriptor table support" "Not supported,Supported"
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bitfld.long 0x00 18. "VMID16,16-bit VMID support" "Not supported,Supported"
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bitfld.long 0x00 17. "VMW,VMID wildcard-matching supported for TLB invalidation" "Not supported,Supported"
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newline
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bitfld.long 0x00 16. "PRI,Page request interface support" "Not supported,Supported"
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bitfld.long 0x00 15. "ATOS,Address translation operations support" "Not supported,Supported"
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bitfld.long 0x00 14. "SEV,SMMU and system support generation of WFE wake-up events to PE" "Not supported,Supported"
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newline
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bitfld.long 0x00 13. "MSI,Message signalled interrupts support" "Not supported,Supported"
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bitfld.long 0x00 12. "ASID16,16-bit ASID support" "Not supported,Supported"
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bitfld.long 0x00 11. "NS1ATS,Split-stage (stage 1-only) ATS not supported" "Supported,Not supported"
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newline
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bitfld.long 0x00 10. "ATS,PCIe ATS supported by SMMU" "Not supported,Supported"
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bitfld.long 0x00 9. "HYP,Hypervisor stage 1 contexts support" "Not supported,Supported"
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bitfld.long 0x00 8. "DORMHINT,Dormant hint support" "Not supported,Supported"
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newline
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bitfld.long 0x00 6.--7. "HTTU,H/W translation table access flag and dirty state of the page updates supported" "Not supported,Access flag,Access flag / Dirty page,?..."
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bitfld.long 0x00 5. "BTM,Broadcast TLB maintenance support" "Not supported,Supported"
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bitfld.long 0x00 4. "COHACC,Coherent access supported to translations, structures and queues" "Not supported,Supported"
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newline
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bitfld.long 0x00 2.--3. "TTF,Translation table formats supported at both stage 1 and stage 2" ",AArch32 (LPAE),AArch64,AArch32 and AArch64"
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bitfld.long 0x00 1. "S1P,Stage 1 translation support" "Not supported,Supported"
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bitfld.long 0x00 0. "S2P,Stage 2 translation support" "Not supported,Supported"
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line.long 0x04 "SMMU_IDR1,SMMU Feature Identification Register 1"
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bitfld.long 0x04 30. "TABLES_PRESET,Table base addresses fixed" "Not fixed,Fixed"
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bitfld.long 0x04 29. "QUEUES_PRESET,Queue base addresses fixed" "Not fixed,Fixed"
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newline
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bitfld.long 0x04 28. "REL,Relative base pointers" "Absolute address,Address offset"
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bitfld.long 0x04 27. "ATTR_TYPES_OVR,Incoming MemType, shareability, allocation/transient hints override" "Not possible,Possible"
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bitfld.long 0x04 26. "ATTR_PERMS_OVR,Incoming Data/Inst, User/Privileged, NS override" "Not possible,Possible"
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newline
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bitfld.long 0x04 21.--25. "CMDQS,Maximum number of command queue entries (as log2(entries))" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,?..."
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bitfld.long 0x04 16.--20. "EVENTQS,Maximum number of event queue entries (as log2(entries))" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,?..."
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bitfld.long 0x04 11.--15. "PRIQS,Maximum number of PRI queue entries (as log2(entries))" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,?..."
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newline
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bitfld.long 0x04 6.--10. "SSIDSIZE,Max bits of SubstreamID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,?..."
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bitfld.long 0x04 0.--5. "SIDSIZE,Max bits of StreamID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
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line.long 0x08 "SMMU_IDR2,SMMU Feature Identification Register 2"
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hexmask.long.word 0x08 0.--9. 0x01 "BA_VATOS,VATOS page base address offset"
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line.long 0x0C "SMMU_IDR3,SMMU Feature Identification Register 3"
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bitfld.long 0x0C 5. "PPS,PRI auto-generated response PASID TLP prefix behavior" "STE.PPAR dependent,Always included"
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bitfld.long 0x0C 4. "XNX,EL0/EL1 execute control distinction at stage 2 support" "Not supported,Supported"
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newline
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bitfld.long 0x0C 3. "PBHA,Page-based hardware attributes presence" "Not supported,Supported"
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bitfld.long 0x0C 2. "HAD,Hierarchical attribute disable presence" "Not supported,Supported"
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rgroup.long 0x10++0x03
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line.long 0x00 "SMMU_IDR4,SMMU Feature Identification Register 4"
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rgroup.long 0x14++0x03
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line.long 0x00 "SMMU_IDR5,SMMU Feature Identification Register 5"
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hexmask.long.word 0x00 16.--31. 1. "STALL_MAX,Maximum number of outstanding stalled transactions supported by SMMU and system"
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bitfld.long 0x00 10.--11. "VAX,Virtual address eXtend" "Up to 48 bits,Up to 52 bits,?..."
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bitfld.long 0x00 6. "GRAN64K,64KB translation granule support" "Not supported,Supported"
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newline
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bitfld.long 0x00 5. "GRAN16K,16KB translation granule support" "Not supported,Supported"
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bitfld.long 0x00 4. "GRAN4K,4KB translation granule support" "Not supported,Supported"
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bitfld.long 0x00 0.--2. "OAS,Size of physical address output from SMMU" "32 bits,36 bits,40 bits,42 bits,44 bits,48 bits,52 bits,?..."
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rgroup.long 0x190++0x03
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line.long 0x00 "SMMU_IDR6,SMMU Feature Identification Register 6"
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rgroup.long 0x18++0x07
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line.long 0x00 "SMMU_IIDR,Implementation Identification Register"
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hexmask.long.word 0x00 20.--31. 1. "PRODUCTID,Value identifying the SMMU part"
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bitfld.long 0x00 16.--19. "VARIANT,Value used to distinguish product variants or major revisions of the product" "Reserved,Reserved,r2,?..."
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bitfld.long 0x00 12.--15. "REVISION,Value used to distinguish minor revisions of the product" "Reserved,Reserved,p2,?..."
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newline
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hexmask.long.word 0x00 0.--11. 1. "IMPLEMENTER,Contains the JEP106 code of the company that implemented the SMMU"
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line.long 0x04 "SMMU_AIDR,Architecture Identification Register"
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bitfld.long 0x04 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
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bitfld.long 0x04 0.--3. "ARCHMINORREV,Architecture minor revision" "Reserved,SMMUv3.1,?..."
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newline
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group.long 0x20++0x03
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line.long 0x00 "SMMU_CR0,Non-secure Global Control Register 0"
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bitfld.long 0x00 6.--8. "VMW,VMID wildcard (TLB invalidation to VMID tag match)" "Exact,TLB inv to VMID[N:1],TLB inv to VMID[N:2],TLB inv to VMID[N:3],TLB inv to VMID[N:4],?..."
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bitfld.long 0x00 4. "ATSCHK,ATS behavior" "Fast mode,Safe mode"
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bitfld.long 0x00 3. "CMDQEN,Enable command queue processing" "Disabled,Enabled"
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newline
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bitfld.long 0x00 2. "EVENTQEN,Enable event queue writes" "Disabled,Enabled"
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bitfld.long 0x00 1. "PRIQEN,Enable PRI queue writes" "Disabled,Enabled"
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bitfld.long 0x00 0. "SMMUEN,Non-secure SMMU enable" "Disabled,Enabled"
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rgroup.long 0x24++0x03
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line.long 0x00 "SMMU_CR0ACK,Non-secure Global Control Register 0 Update Acknowledge Register"
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bitfld.long 0x00 6.--8. "VMW,VMID wildcard (TLB invalidation to VMID tag match)" "Exact,TLB inv to VMID[N:1],TLB inv to VMID[N:2],TLB inv to VMID[N:3],TLB inv to VMID[N:4],?..."
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bitfld.long 0x00 4. "ATSCHK,ATS behavior" "Fast mode,Safe mode"
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bitfld.long 0x00 3. "CMDQEN,Enable command queue processing" "Disabled,Enabled"
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newline
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bitfld.long 0x00 2. "EVENTQEN,Enable event queue writes" "Disabled,Enabled"
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bitfld.long 0x00 1. "PRIQEN,Enable PRI queue writes" "Disabled,Enabled"
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bitfld.long 0x00 0. "SMMUEN,Non-secure SMMU enable" "Disabled,Enabled"
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if ((per.l(&SMMU_base+0x04)&0x40000000)==0x00)&&((per.l(&SMMU_base+0x20)&0x01)==0x00)&&((per.l(&SMMU_base+0x04)&0x20000000)==0x00)&&((per.l(&SMMU_base+0x20)&0x0E)==0x00)
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group.long 0x28++0x03
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line.long 0x00 "SMMU_CR1,Non-secure Global Control Register 1"
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bitfld.long 0x00 10.--11. "TABLE_SH,Table access shareability" "Non-shareable,Reserved,Outer shareable,Inner shareable"
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bitfld.long 0x00 8.--9. "TABLE_OC,Table access outer cacheability" "Non-cacheable,Write-back cacheable,Write-through cacheable,?..."
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bitfld.long 0x00 6.--7. "TABLE_IC,Table access inner cacheability" "Non-cacheable,Write-back cacheable,Write-through cacheable,?..."
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newline
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bitfld.long 0x00 4.--5. "QUEUE_SH,Queue access shareability" "Non-shareable,Reserved,Outer shareable,Inner shareable"
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bitfld.long 0x00 2.--3. "QUEUE_OC,Queue access outer cacheability" "Non-cacheable,Write-back cacheable,Write-through cacheable,?..."
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bitfld.long 0x00 0.--1. "QUEUE_IC,Queue access inner cacheability" "Non-cacheable,Write-back cacheable,Write-through cacheable,?..."
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elif (((per.l(&SMMU_base+0x04)&0x40000000)==0x40000000)||((per.l(&SMMU_base+0x20)&0x01)==0x01))&&((per.l(&SMMU_base+0x04)&0x20000000)==0x00)&&((per.l(&SMMU_base+0x20)&0x0E)==0x00)
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group.long 0x28++0x03
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line.long 0x00 "SMMU_CR1,Non-secure Global Control Register 1"
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rbitfld.long 0x00 10.--11. "TABLE_SH,Table access shareability" "Non-shareable,Reserved,Outer shareable,Inner shareable"
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rbitfld.long 0x00 8.--9. "TABLE_OC,Table access outer cacheability" "Non-cacheable,Write-back cacheable,Write-through cacheable,?..."
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rbitfld.long 0x00 6.--7. "TABLE_IC,Table access inner cacheability" "Non-cacheable,Write-back cacheable,Write-through cacheable,?..."
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newline
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bitfld.long 0x00 4.--5. "QUEUE_SH,Queue access shareability" "Non-shareable,Reserved,Outer shareable,Inner shareable"
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bitfld.long 0x00 2.--3. "QUEUE_OC,Queue access outer cacheability" "Non-cacheable,Write-back cacheable,Write-through cacheable,?..."
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bitfld.long 0x00 0.--1. "QUEUE_IC,Queue access inner cacheability" "Non-cacheable,Write-back cacheable,Write-through cacheable,?..."
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elif ((per.l(&SMMU_base+0x04)&0x40000000)==0x00)&&((per.l(&SMMU_base+0x20)&0x01)==0x00)&&(((per.l(&SMMU_base+0x04)&0x20000000)==0x20000000)||((per.l(&SMMU_base+0x20)&0x0E)!=0x00))
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group.long 0x28++0x03
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line.long 0x00 "SMMU_CR1,Non-secure Global Control Register 1"
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bitfld.long 0x00 10.--11. "TABLE_SH,Table access shareability" "Non-shareable,Reserved,Outer shareable,Inner shareable"
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bitfld.long 0x00 8.--9. "TABLE_OC,Table access outer cacheability" "Non-cacheable,Write-back cacheable,Write-through cacheable,?..."
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bitfld.long 0x00 6.--7. "TABLE_IC,Table access inner cacheability" "Non-cacheable,Write-back cacheable,Write-through cacheable,?..."
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newline
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rbitfld.long 0x00 4.--5. "QUEUE_SH,Queue access shareability" "Non-shareable,Reserved,Outer shareable,Inner shareable"
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rbitfld.long 0x00 2.--3. "QUEUE_OC,Queue access outer cacheability" "Non-cacheable,Write-back cacheable,Write-through cacheable,?..."
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rbitfld.long 0x00 0.--1. "QUEUE_IC,Queue access inner cacheability" "Non-cacheable,Write-back cacheable,Write-through cacheable,?..."
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else
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rgroup.long 0x28++0x03
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line.long 0x00 "SMMU_CR1,Non-secure Global Control Register 1"
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bitfld.long 0x00 10.--11. "TABLE_SH,Table access shareability" "Non-shareable,Reserved,Outer shareable,Inner shareable"
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bitfld.long 0x00 8.--9. "TABLE_OC,Table access outer cacheability" "Non-cacheable,Write-back cacheable,Write-through cacheable,?..."
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bitfld.long 0x00 6.--7. "TABLE_IC,Table access inner cacheability" "Non-cacheable,Write-back cacheable,Write-through cacheable,?..."
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newline
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bitfld.long 0x00 4.--5. "QUEUE_SH,Queue access shareability" "Non-shareable,Reserved,Outer shareable,Inner shareable"
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bitfld.long 0x00 2.--3. "QUEUE_OC,Queue access outer cacheability" "Non-cacheable,Write-back cacheable,Write-through cacheable,?..."
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bitfld.long 0x00 0.--1. "QUEUE_IC,Queue access inner cacheability" "Non-cacheable,Write-back cacheable,Write-through cacheable,?..."
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endif
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if ((per.l(&SMMU_base+0x20)&0x01)==0x00)
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group.long 0x2C++0x03
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line.long 0x00 "SMMU_CR2,Non-secure Global Control Register 2"
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bitfld.long 0x00 2. "PTM,Private TLB maintenance" "Disabled,Enabled"
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bitfld.long 0x00 1. "RECINVSID,Record event C_BAD_STREAMID from invalid input StreamIDs" "Disabled,Enabled"
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bitfld.long 0x00 0. "E2H,Enable EL2-E2H translation regime" "Disabled,Enabled"
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else
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rgroup.long 0x2C++0x03
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line.long 0x00 "SMMU_CR2,Non-secure Global Control Register 2"
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bitfld.long 0x00 2. "PTM,Private TLB maintenance" "Disabled,Enabled"
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bitfld.long 0x00 1. "RECINVSID,Record event C_BAD_STREAMID from invalid input StreamIDs" "Disabled,Enabled"
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bitfld.long 0x00 0. "E2H,Enable EL2-E2H translation regime" "Disabled,Enabled"
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endif
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rgroup.long 0x40++0x03
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line.long 0x00 "SMMU_STATUSR,SMMU_STATUSR"
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if ((per.l(&SMMU_base+0x20)&0x01)==0x00)&&((per.l(&SMMU_base+0x44)&0x80000000)==0x00)
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group.long 0x44++0x03
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line.long 0x00 "SMMU_GBPA,Non-secure Global Bypass Attribute Register"
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bitfld.long 0x00 31. "UPDATE,Update completion flags" "Completed,Running"
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bitfld.long 0x00 20. "ABORT,Abort all incoming transactions" "Do not abort,Abort"
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bitfld.long 0x00 18.--19. "INSTCFG,Instruction/data override" "Use incoming,Reserved,Data,Instruction"
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newline
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bitfld.long 0x00 16.--17. "PRIVCFG,User/privileged override" "Use incoming,Reserved,Unprivileged,Privileged"
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bitfld.long 0x00 12.--13. "SHCFG,Shareability override" "Non-shareable,Use incoming,Outer shareable,Inner Shareable"
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newline
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bitfld.long 0x00 10. 11. "ALLOCCFG[2],Read allocate hint (RA) override" "Use incoming,Use incoming,No read-allocate,Read allocate"
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bitfld.long 0x00 9. 11. "ALLOCCFG[1],Write allocate hint (WA) override" "Use incoming,Use incoming,No write-allocate,Write allocate"
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bitfld.long 0x00 8. 11. "ALLOCCFG[0],Transient hint (TR) override" "Use incoming,Use incoming,Non-transient,Transient"
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newline
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bitfld.long 0x00 4. "MTCFG,Memory type override enable" "Use incoming,Override by MEMATTR fld"
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bitfld.long 0x00 0.--3. "MEMATTR,Memory type override" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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else
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rgroup.long 0x44++0x03
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line.long 0x00 "SMMU_GBPA,Non-secure Global Bypass Attribute Register"
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bitfld.long 0x00 31. "UPDATE,Update completion flags" "Completed,Running"
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bitfld.long 0x00 20. "ABORT,Abort all incoming transactions" "Do not abort,Abort"
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bitfld.long 0x00 18.--19. "INSTCFG,Instruction/data override" "Use incoming,Reserved,Data,Instruction"
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newline
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bitfld.long 0x00 16.--17. "PRIVCFG,User/privileged override" "Use incoming,Reserved,Unprivileged,Privileged"
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bitfld.long 0x00 12.--13. "SHCFG,Shareability override" "Non-shareable,Use incoming,Outer shareable,Inner Shareable"
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newline
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bitfld.long 0x00 10. 11. "ALLOCCFG[2],Read allocate hint (RA) override" "Use incoming,Use incoming,No read-allocate,Read allocate"
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bitfld.long 0x00 9. 11. "ALLOCCFG[1],Write allocate hint (WA) override" "Use incoming,Use incoming,No write-allocate,Write allocate"
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bitfld.long 0x00 8. 11. "ALLOCCFG[0],Transient hint (TR) override" "Use incoming,Use incoming,Non-transient,Transient"
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newline
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bitfld.long 0x00 4. "MTCFG,Memory type override enable" "Use incoming,Override by MEMATTR fld"
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bitfld.long 0x00 0.--3. "MEMATTR,Memory type override" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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endif
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rgroup.long 0x48++0x03
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line.long 0x00 "SMMU_AGBPA,Alternate Non-secure Global Bypass Attribute Register"
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group.long 0x50++0x03
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line.long 0x00 "SMMU_IRQ_CTRL,Non-secure Interrupt Control Register"
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bitfld.long 0x00 2. "EVENTQ_IRQEN,Non-secure event queue interrupts enable" "Disabled,Enabled"
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bitfld.long 0x00 1. "PRIQ_IRQEN,PRI queue interrupts enable" "Disabled,Enabled"
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bitfld.long 0x00 0. "GERROR_IRQEN,Non-secure global interrupts enable" "Disabled,Enabled"
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rgroup.long 0x54++0x03
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line.long 0x00 "SMMU_IRQ_CTRLACK,Non-secure Interrupt Control Register Update Acknowledge Register"
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bitfld.long 0x00 2. "EVENTQ_IRQEN,Non-secure event queue interrupts enable" "Disabled,Enabled"
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bitfld.long 0x00 1. "PRIQ_IRQEN,PRI queue interrupts enable" "Disabled,Enabled"
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bitfld.long 0x00 0. "GERROR_IRQEN,Non-secure global interrupts enable" "Disabled,Enabled"
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rgroup.long 0x60++0x03
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line.long 0x00 "SMMU_GERROR,Non-secure Global Error Status Register"
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bitfld.long 0x00 8. "SFM_ERR,The SMMU has entered service failure mode" "Not occurred,Occurred"
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bitfld.long 0x00 7. "MSI_GERROR_ABT_ERR,A GERROR MSI was terminated with abort" "Not occurred,Occurred"
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newline
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bitfld.long 0x00 6. "MSI_PRIQ_ABT_ERR,A PRI queue MSI was terminated with abort" "Not occurred,Occurred"
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bitfld.long 0x00 5. "MSI_EVENTQ_ABT_ERR,An event queue MSI was terminated with abort" "Not occurred,Occurred"
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bitfld.long 0x00 4. "MSI_CMDQ_ABT_ERR,A CMD_SYNC MSI was terminated with abort" "Not occurred,Occurred"
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newline
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bitfld.long 0x00 3. "PRIQ_ABT_ERR,An access to the PRI queue was terminated with abort" "Not occurred,Occurred"
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bitfld.long 0x00 2. "EVENTQ_ABT_ERR,An access to the event queue was terminated with abort" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. "CMDQ_ERR,Command has been encountered that cannot be processed" "Not occurred,Occurred"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "SMMU_GERRORN,Non-secure Global Error Acknowledgment Register"
|
|
bitfld.long 0x00 8. "SFM_ERR,The SMMU has entered service failure mode" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. "MSI_GERROR_ABT_ERR,A GERROR MSI was terminated with abort" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "MSI_PRIQ_ABT_ERR,A PRI queue MSI was terminated with abort" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. "MSI_EVENTQ_ABT_ERR,An event queue MSI was terminated with abort" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. "MSI_CMDQ_ABT_ERR,A CMD_SYNC MSI was terminated with abort" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 3. "PRIQ_ABT_ERR,An access to the PRI queue was terminated with abort" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. "EVENTQ_ABT_ERR,An access to the event queue was terminated with abort" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. "CMDQ_ERR,Command has been encountered that cannot be processed" "Not occurred,Occurred"
|
|
if ((per.l(&SMMU_base+0x50)&0x01)==0x00)
|
|
group.quad 0x68++0x07
|
|
line.quad 0x00 "SMMU_GERROR_IRQ_CFG0,Non-secure Global Error IRQ Configuration Register 0"
|
|
hexmask.quad 0x00 2.--51. 0x04 "ADDR,PA of MSI target register"
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "SMMU_GERROR_IRQ_CFG1,Non-secure Global Error IRQ Configuration Register 1"
|
|
line.long 0x04 "SMMU_GERROR_IRQ_CFG2,Non-secure Global Error IRQ Configuration Register 2"
|
|
bitfld.long 0x04 4.--5. "SH,Shareability" "Non-shareable,Reserved,Outer shareable,Inner sharable"
|
|
bitfld.long 0x04 0.--3. "MEMATTR,Memory type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.quad 0x68++0x07
|
|
line.quad 0x00 "SMMU_GERROR_IRQ_CFG0,Non-secure Global Error IRQ Configuration Register 0"
|
|
hexmask.quad 0x00 2.--51. 0x04 "ADDR,PA of MSI target register"
|
|
rgroup.long 0x70++0x07
|
|
line.long 0x00 "SMMU_GERROR_IRQ_CFG1,Non-secure Global Error IRQ Configuration Register 1"
|
|
line.long 0x04 "SMMU_GERROR_IRQ_CFG2,Non-secure Global Error IRQ Configuration Register 2"
|
|
bitfld.long 0x04 4.--5. "SH,Shareability" "Non-shareable,Reserved,Outer shareable,Inner sharable"
|
|
bitfld.long 0x04 0.--3. "MEMATTR,Memory type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if ((per.l(&SMMU_base+0x20)&0x01)==0x00)
|
|
group.quad 0x80++0x07
|
|
line.quad 0x00 "SMMU_STRTAB_BASE,Non-secure Stream Table Base Address Register"
|
|
bitfld.quad 0x00 62. "RA,Read allocate hint" "No read-allocate,Read-allocate"
|
|
hexmask.quad 0x00 6.--51. 0x40 "ADDR,Physical address of stream table base"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "SMMU_STRTAB_BASE_CFG,Non-secure Stream Table Configuration Register"
|
|
bitfld.long 0x00 16.--17. "FMT,Format of stream table" "Linear,2-level,?..."
|
|
bitfld.long 0x00 6.--10. "SPLIT,StreamID split point for multi-level table (number of bits at the bottom level)" ",Reserved,Reserved,Reserved,Reserved,Reserved,4 KB leaf,Reserved,16 KB leaf,Reserved,64 KB leaf,?..."
|
|
bitfld.long 0x00 0.--5. "LOG2SIZE,Table size as log2(entries)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
rgroup.quad 0x80++0x07
|
|
line.quad 0x00 "SMMU_STRTAB_BASE,Non-secure Stream Table Base Address Register"
|
|
bitfld.quad 0x00 62. "RA,Read allocate hint" "No read-allocate,Read-allocate"
|
|
hexmask.quad 0x00 6.--51. 0x40 "ADDR,Physical address of stream table base"
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "SMMU_STRTAB_BASE_CFG,Non-secure Stream Table Configuration Register"
|
|
bitfld.long 0x00 16.--17. "FMT,Format of stream table" "Linear,2-level,?..."
|
|
bitfld.long 0x00 6.--10. "SPLIT,StreamID split point for multi-level table (number of bits at the bottom level)" ",Reserved,Reserved,Reserved,Reserved,Reserved,4 KB leaf,Reserved,16 KB leaf,Reserved,64 KB leaf,?..."
|
|
bitfld.long 0x00 0.--5. "LOG2SIZE,Table size as log2(entries)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
if ((per.l(&SMMU_base+0x20)&0x08)==0x00)
|
|
group.quad 0x90++0x07
|
|
line.quad 0x00 "SMMU_CMDQ_BASE,Non-secure Command Queue Base Address Register"
|
|
bitfld.quad 0x00 62. "RA,Read allocate hint" "No read-allocate,Read-allocate"
|
|
hexmask.quad 0x00 5.--51. 0x20 "ADDR,Physical address of command queue base"
|
|
bitfld.quad 0x00 0.--4. "LOG2SIZE,Queue size as log2(entries)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,?..."
|
|
else
|
|
rgroup.quad 0x90++0x07
|
|
line.quad 0x00 "SMMU_CMDQ_BASE,Non-secure Command Queue Base Address Register"
|
|
bitfld.quad 0x00 62. "RA,Read allocate hint" "No read-allocate,Read-allocate"
|
|
hexmask.quad 0x00 5.--51. 0x20 "ADDR,Physical address of command queue base"
|
|
bitfld.quad 0x00 0.--4. "LOG2SIZE,Queue size as log2(entries)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,?..."
|
|
endif
|
|
newline
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "SMMU_CMDQ_PROD,Non-secure Command Queue Producer Index Register"
|
|
hexmask.long 0x00 0.--19. 0x01 "WR,Event queue write index wrap flag and write index"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "SMMU_CMDQ_CONS,Non-secure Command Queue Consumer Index Register"
|
|
hexmask.long.byte 0x00 24.--30. 0x01 "ERR,Error reason code"
|
|
hexmask.long 0x00 0.--19. 0x01 "RD,Queue read index wrap flag and read index"
|
|
newline
|
|
if ((per.l(&SMMU_base+0x20)&0x04)==0x00)
|
|
group.quad 0xA0++0x07
|
|
line.quad 0x00 "SMMU_EVENTQ_BASE,Non-secure Event Queue Base Address Register"
|
|
bitfld.quad 0x00 62. "WA,Write allocate hint" "No write-allocate,Write-allocate"
|
|
hexmask.quad 0x00 5.--51. 0x20 "ADDR,PA of queue base"
|
|
bitfld.quad 0x00 0.--4. "LOG2SIZE,Queue size as log2(entries)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,?..."
|
|
else
|
|
rgroup.quad 0xA0++0x07
|
|
line.quad 0x00 "SMMU_EVENTQ_BASE,Non-secure Event Queue Base Address Register"
|
|
bitfld.quad 0x00 62. "WA,Write allocate hint" "No write-allocate,Write-allocate"
|
|
hexmask.quad 0x00 5.--51. 0x20 "ADDR,PA of queue base"
|
|
bitfld.quad 0x00 0.--4. "LOG2SIZE,Queue size as log2(entries)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,?..."
|
|
endif
|
|
newline
|
|
group.long 0x100A8++0x03
|
|
line.long 0x00 "SMMU_EVENTQ_PROD,Non-secure Event Queue Producer Index Register"
|
|
bitfld.long 0x00 31. "OVFLG,Queue overflowed" "No overflow occured,Overflow occured"
|
|
hexmask.long 0x00 0.--19. 0x01 "WR,Event queue write index wrap flag and write index"
|
|
group.long 0x100AC++0x03
|
|
line.long 0x00 "SMMU_EVENTQ_CONS,Non-secure Event Queue Consumer Index Register"
|
|
bitfld.long 0x00 31. "OVACKFLG,Overflow acknowledge flag"
|
|
hexmask.long 0x00 0.--19. 0x01 "RD,Queue read index wrap flag and read index"
|
|
newline
|
|
if ((per.l(&SMMU_base+0x50)&0x04)==0x00)
|
|
group.quad 0xB0++0x07
|
|
line.quad 0x00 "SMMU_EVENTQ_IRQ_CFG0,Non-secure Event Queue IRQ Configuration Register 0"
|
|
hexmask.quad 0x00 2.--51. 0x04 "ADDR,PA of MSI target register"
|
|
group.long 0xB8++0x07
|
|
line.long 0x00 "SMMU_EVENTQ_IRQ_CFG1,Non-secure Event Queue IRQ Configuration Register 1"
|
|
line.long 0x04 "SMMU_EVENTQ_IRQ_CFG2,Non-secure Event Queue IRQ Configuration Register 2"
|
|
bitfld.long 0x04 4.--5. "SH,Shareability" "Non-shareable,Reserved,Outer shareable,Inner sharable"
|
|
bitfld.long 0x04 0.--3. "MEMATTR,Memory type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.quad 0xB0++0x07
|
|
line.quad 0x00 "SMMU_EVENTQ_IRQ_CFG0,Non-secure Event Queue IRQ Configuration Register 0"
|
|
hexmask.quad 0x00 2.--51. 0x04 "ADDR,PA of MSI target register"
|
|
rgroup.long 0xB8++0x07
|
|
line.long 0x00 "SMMU_EVENTQ_IRQ_CFG1,Non-secure Event Queue IRQ Configuration Register 1"
|
|
line.long 0x04 "SMMU_EVENTQ_IRQ_CFG2,Non-secure Event Queue IRQ Configuration Register 2"
|
|
bitfld.long 0x04 4.--5. "SH,Shareability" "Non-shareable,Reserved,Outer shareable,Inner sharable"
|
|
bitfld.long 0x04 0.--3. "MEMATTR,Memory type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if ((per.l(&SMMU_base+0x20)&0x02)==0x00)
|
|
group.quad 0xC0++0x07
|
|
line.quad 0x00 "SMMU_PRIQ_BASE,Non-secure PRI Queue Base Address Register"
|
|
bitfld.quad 0x00 62. "WA,Write allocate hint" "No write-allocate,Write-allocate"
|
|
hexmask.quad 0x00 5.--51. 0x20 "ADDR,PA of queue base"
|
|
bitfld.quad 0x00 0.--4. "LOG2SIZE,Queue size as log2(entries)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,?..."
|
|
else
|
|
rgroup.quad 0xC0++0x07
|
|
line.quad 0x00 "SMMU_PRIQ_BASE,Non-secure PRI Queue Base Address Register"
|
|
bitfld.quad 0x00 62. "WA,Write allocate hint" "No write-allocate,Write-allocate"
|
|
hexmask.quad 0x00 5.--51. 0x20 "ADDR,PA of queue base"
|
|
bitfld.quad 0x00 0.--4. "LOG2SIZE,Queue size as log2(entries)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,?..."
|
|
endif
|
|
newline
|
|
group.long 0x100C8++0x03
|
|
line.long 0x00 "SMMU_PRIQ_PROD,Non-secure PRI Queue Producer Index Register"
|
|
bitfld.long 0x00 31. "OVFLG,Queue overflowed" "No overflow occured,Overflow occured"
|
|
hexmask.long 0x00 0.--19. 0x01 "WR,Event queue write index wrap flag and write index"
|
|
group.long 0x100CC++0x03
|
|
line.long 0x00 "SMMU_PRIQ_CONS,Non-secure PRI Queue Consumer Index Register"
|
|
bitfld.long 0x00 31. "OVACKFLG,Overflow acknowledge flag"
|
|
hexmask.long 0x00 0.--19. 0x01 "RD,Queue read index wrap flag and read index"
|
|
newline
|
|
if ((per.l(&SMMU_base+0x50)&0x02)==0x00)
|
|
group.quad 0xD0++0x07
|
|
line.quad 0x00 "SMMU_PRIQ_IRQ_CFG0,Non-secure PRI Queue IRQ Configuration Register 0"
|
|
hexmask.quad 0x00 2.--51. 0x04 "ADDR,PA of MSI target register"
|
|
group.long 0xD8++0x07
|
|
line.long 0x00 "SMMU_PRIQ_IRQ_CFG1,Non-secure PRI Queue IRQ Configuration Register 1"
|
|
line.long 0x04 "SMMU_PRIQ_IRQ_CFG2,Non-secure PRI Queue IRQ Configuration Register 2"
|
|
bitfld.long 0x04 4.--5. "SH,Shareability" "Non-shareable,Reserved,Outer shareable,Inner sharable"
|
|
bitfld.long 0x04 0.--3. "MEMATTR,Memory type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.quad 0xD0++0x07
|
|
line.quad 0x00 "SMMU_PRIQ_IRQ_CFG0,Non-secure PRI Queue IRQ Configuration Register 0"
|
|
hexmask.quad 0x00 2.--51. 0x04 "ADDR,PA of MSI target register"
|
|
rgroup.long 0xD8++0x07
|
|
line.long 0x00 "SMMU_PRIQ_IRQ_CFG1,Non-secure PRI Queue IRQ Configuration Register 1"
|
|
line.long 0x04 "SMMU_PRIQ_IRQ_CFG2,Non-secure PRI Queue IRQ Configuration Register 2"
|
|
bitfld.long 0x04 4.--5. "SH,Shareability" "Non-shareable,Reserved,Outer shareable,Inner sharable"
|
|
bitfld.long 0x04 0.--3. "MEMATTR,Memory type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "SMMU_GATOS_CTRL,Non-secure SMMU_GATOS_CTRL"
|
|
rgroup.quad 0x108++0x17
|
|
line.quad 0x00 "SMMU_GATOS_SID,Non-secure SMMU_GATOS_SID"
|
|
line.quad 0x08 "SMMU_GATOS_ADDR,Non-secure SMMU_GATOS_ADDR"
|
|
line.quad 0x10 "SMMU_GATOS_PAR,Non-secure SMMU_GATOS_PAR"
|
|
rgroup.long 0x180++0x03
|
|
line.long 0x00 "SMMU_VATOS_SEL,Non-secure SMMU_VATOS_SEL"
|
|
rgroup.long 0x130++0x03
|
|
line.long 0x00 "SMMU_MPAMIDR,Non-secure MPAM Capability Identification Register"
|
|
rgroup.long 0x138++0x07
|
|
line.long 0x00 "SMMU_GMPAM,Non-secure Global MPAM Configuration Register"
|
|
line.long 0x04 "SMMU_GBPMPAM,Non-secure MPAM Configuration Register For Global Bypass Transactions"
|
|
tree "SMMU CoreSight ID Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long 0xFD0++0x0F
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
line.long 0x04 "SMMU_PIDR5,Peripheral Identification Register 5"
|
|
line.long 0x08 "SMMU_PIDR6,Peripheral Identification Register 6"
|
|
line.long 0x0C "SMMU_PIDR7,Peripheral Identification Register 7"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree.end
|
|
newline
|
|
rgroup.long 0x8000++0x13 "Secure Stream Configuration Registers"
|
|
line.long 0x00 "SMMU_S_IDR0,SMMU Secure Feature Identification Register 0"
|
|
bitfld.long 0x00 24.--25. "STALL_MODEL,Stall model support" "Supported,Not supported,Forced,?..."
|
|
bitfld.long 0x00 13. "MSI,Secure message signalled interrupts support" "Not supported,Supported"
|
|
line.long 0x04 "SMMU_S_IDR1,SMMU Secure Feature Identification Register 1"
|
|
bitfld.long 0x04 31. "SECURE_IMPL,Security implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x04 0.--5. "S_SIDSIZE,Max bits of secure StreamID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
line.long 0x08 "SMMU_S_IDR2,SMMU Secure Feature Identification Register 2"
|
|
line.long 0x0C "SMMU_S_IDR3,SMMU Secure Feature Identification Register 3"
|
|
bitfld.long 0x0C 6. "SAMS,Secure ATS maintenance support" "Reserved,Supported"
|
|
line.long 0x10 "SMMU_S_IDR4,SMMU Secure Feature Identification Register 4"
|
|
rgroup.long 0x8190++0x03
|
|
line.long 0x00 "SMMU_S_IDR6,SMMU Secure Feature Identification Register 6"
|
|
group.long 0x8020++0x03
|
|
line.long 0x00 "SMMU_S_CR0,Secure Global Control Register 0"
|
|
bitfld.long 0x00 9. "NSSTALLD,Non-secure stall disable" "No,Yes"
|
|
bitfld.long 0x00 5. "SIF,Secure instruction fetch" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "CMDQEN,Enable secure command queue processing" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. "EVENTQEN,Enable secure event queue writes" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SMMUEN,Secure SMMU enable" "Disabled,Enabled"
|
|
rgroup.long 0x8024++0x03
|
|
line.long 0x00 "SMMU_S_CR0ACK,Secure Global Control Register 0 Update Acknowledge Register"
|
|
bitfld.long 0x00 9. "NSSTALLD,Non-secure stall disable" "No,Yes"
|
|
bitfld.long 0x00 5. "SIF,Secure instruction fetch" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "CMDQEN,Enable secure command queue processing" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. "EVENTQEN,Enable secure event queue writes" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SMMUEN,Secure SMMU enable" "Disabled,Enabled"
|
|
if ((per.l(&SMMU_base+0x8004)&0x80000000)==0x80000000)
|
|
if ((per.l(&SMMU_base+0x8020)&0x01)==0x00)&&((per.l(&SMMU_base+0x8020)&0x04)==0x00)&&((per.l(&SMMU_base+0x8020)&0x08)==0x00)
|
|
group.long 0x8028++0x03
|
|
line.long 0x00 "SMMU_S_CR1,Secure Global Control Register 1"
|
|
bitfld.long 0x00 10.--11. "TABLE_SH,Secure stream table access shareability" "Non-shareable,Reserved,Outer shareable,Inner shareable"
|
|
bitfld.long 0x00 8.--9. "TABLE_OC,Secure stream table access outer cacheability" "Non-cacheable,Write-back cacheable,Write-through cacheable,?..."
|
|
bitfld.long 0x00 6.--7. "TABLE_IC,Secure stream table access inner cacheability" "Non-cacheable,Write-back cacheable,Write-through cacheable,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--5. "QUEUE_SH,Secure queue access shareability" "Non-shareable,Reserved,Outer shareable,Inner shareable"
|
|
bitfld.long 0x00 2.--3. "QUEUE_OC,Secure queue access outer cacheability" "Non-cacheable,Write-back cacheable,Write-through cacheable,?..."
|
|
bitfld.long 0x00 0.--1. "QUEUE_IC,Secure queue access inner cacheability" "Non-cacheable,Write-back cacheable,Write-through cacheable,?..."
|
|
elif ((per.l(&SMMU_base+0x8020)&0x01)==0x00)&&(((per.l(&SMMU_base+0x8020)&0x04)==0x04)||((per.l(&SMMU_base+0x8020)&0x08)==0x08))
|
|
group.long 0x8028++0x03
|
|
line.long 0x00 "SMMU_S_CR1,Secure Global Control Register 1"
|
|
bitfld.long 0x00 10.--11. "TABLE_SH,Secure stream table access shareability" "Non-shareable,Reserved,Outer shareable,Inner shareable"
|
|
bitfld.long 0x00 8.--9. "TABLE_OC,Secure stream table access outer cacheability" "Non-cacheable,Write-back cacheable,Write-through cacheable,?..."
|
|
bitfld.long 0x00 6.--7. "TABLE_IC,Secure stream table access inner cacheability" "Non-cacheable,Write-back cacheable,Write-through cacheable,?..."
|
|
newline
|
|
rbitfld.long 0x00 4.--5. "QUEUE_SH,Secure queue access shareability" "Non-shareable,Reserved,Outer shareable,Inner shareable"
|
|
rbitfld.long 0x00 2.--3. "QUEUE_OC,Secure queue access outer cacheability" "Non-cacheable,Write-back cacheable,Write-through cacheable,?..."
|
|
rbitfld.long 0x00 0.--1. "QUEUE_IC,Secure queue access inner cacheability" "Non-cacheable,Write-back cacheable,Write-through cacheable,?..."
|
|
elif ((per.l(&SMMU_base+0x8020)&0x01)==0x01)&&((per.l(&SMMU_base+0x8020)&0x04)==0x00)&&((per.l(&SMMU_base+0x8020)&0x08)==0x00)
|
|
group.long 0x8028++0x03
|
|
line.long 0x00 "SMMU_S_CR1,Secure Global Control Register 1"
|
|
rbitfld.long 0x00 10.--11. "TABLE_SH,Secure stream table access shareability" "Non-shareable,Reserved,Outer shareable,Inner shareable"
|
|
rbitfld.long 0x00 8.--9. "TABLE_OC,Secure stream table access outer cacheability" "Non-cacheable,Write-back cacheable,Write-through cacheable,?..."
|
|
rbitfld.long 0x00 6.--7. "TABLE_IC,Secure stream table access inner cacheability" "Non-cacheable,Write-back cacheable,Write-through cacheable,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--5. "QUEUE_SH,Secure queue access shareability" "Non-shareable,Reserved,Outer shareable,Inner shareable"
|
|
bitfld.long 0x00 2.--3. "QUEUE_OC,Secure queue access outer cacheability" "Non-cacheable,Write-back cacheable,Write-through cacheable,?..."
|
|
bitfld.long 0x00 0.--1. "QUEUE_IC,Secure queue access inner cacheability" "Non-cacheable,Write-back cacheable,Write-through cacheable,?..."
|
|
else
|
|
group.long 0x8028++0x03
|
|
line.long 0x00 "SMMU_S_CR1,Secure Global Control Register 1"
|
|
rbitfld.long 0x00 10.--11. "TABLE_SH,Secure stream table access shareability" "Non-shareable,Reserved,Outer shareable,Inner shareable"
|
|
rbitfld.long 0x00 8.--9. "TABLE_OC,Secure stream table access outer cacheability" "Non-cacheable,Write-back cacheable,Write-through cacheable,?..."
|
|
rbitfld.long 0x00 6.--7. "TABLE_IC,Secure stream table access inner cacheability" "Non-cacheable,Write-back cacheable,Write-through cacheable,?..."
|
|
newline
|
|
rbitfld.long 0x00 4.--5. "QUEUE_SH,Secure queue access shareability" "Non-shareable,Reserved,Outer shareable,Inner shareable"
|
|
rbitfld.long 0x00 2.--3. "QUEUE_OC,Secure queue access outer cacheability" "Non-cacheable,Write-back cacheable,Write-through cacheable,?..."
|
|
rbitfld.long 0x00 0.--1. "QUEUE_IC,Secure queue access inner cacheability" "Non-cacheable,Write-back cacheable,Write-through cacheable,?..."
|
|
endif
|
|
else
|
|
rgroup.long 0x8028++0x03
|
|
line.long 0x00 "SMMU_S_CR1,Secure Global Control Register 1"
|
|
endif
|
|
if ((per.l(&SMMU_base+0x8020)&0x01)==0x00)
|
|
group.long 0x802C++0x03
|
|
line.long 0x00 "SMMU_S_CR2,Secure Global Control Register 2"
|
|
bitfld.long 0x00 2. "PTM,Private TLB maintenance" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. "RECINVSID,Record event C_BAD_STREAMID from invalid input StreamIDs" "Not permitted,Permitted"
|
|
else
|
|
rgroup.long 0x802C++0x03
|
|
line.long 0x00 "SMMU_S_CR2,Secure Global Control Register 2"
|
|
bitfld.long 0x00 2. "PTM,Private TLB maintenance" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. "RECINVSID,Record event C_BAD_STREAMID from invalid input StreamIDs" "Not permitted,Permitted"
|
|
endif
|
|
if ((per.l(&SMMU_base+0x8020)&0x01)==0x00)
|
|
group.long 0x8044++0x03
|
|
line.long 0x00 "SMMU_S_GBPA,Secure Global Bypass Attribute Register"
|
|
bitfld.long 0x00 31. "UPDATE,Update completion flags" "Completed,Running"
|
|
bitfld.long 0x00 20. "ABORT,Abort all incoming transactions" "Do not abort,Abort"
|
|
bitfld.long 0x00 18.--19. "INSTCFG,Instruction/data override" "Use incoming,Reserved,Data,Instruction"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "PRIVCFG,User/privileged override" "Use incoming,Reserved,Unprivileged,Privileged"
|
|
bitfld.long 0x00 14.--15. "NSCFG,NS override" "Use incoming,Reserved,Secure,Non-secure"
|
|
bitfld.long 0x00 12.--13. "SHCFG,Shareability override" "Non-shareable,Use incoming,Outer shareable,Inner Shareable"
|
|
newline
|
|
bitfld.long 0x00 10. 11. "ALLOCCFG[2],Read allocate hint (RA) override" "Use incoming,Use incoming,No read-allocate,Read allocate"
|
|
bitfld.long 0x00 9. 11. "ALLOCCFG[1],Write allocate hint (WA) override" "Use incoming,Use incoming,No write-allocate,Write allocate"
|
|
bitfld.long 0x00 8. 11. "ALLOCCFG[0],Transient hint (TR) override" "Use incoming,Use incoming,Non-transient,Transient"
|
|
newline
|
|
bitfld.long 0x00 4. "MTCFG,Memory type override enable" "Use incoming,Override by MEMATTR fld"
|
|
bitfld.long 0x00 0.--3. "MEMATTR,Memory type override" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x8044++0x03
|
|
line.long 0x00 "SMMU_S_GBPA,Secure Global Bypass Attribute Register"
|
|
bitfld.long 0x00 31. "UPDATE,Update completion flags" "Completed,Running"
|
|
bitfld.long 0x00 20. "ABORT,Abort all incoming transactions" "Do not abort,Abort"
|
|
bitfld.long 0x00 18.--19. "INSTCFG,Instruction/data override" "Use incoming,Reserved,Data,Instruction"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "PRIVCFG,User/privileged override" "Use incoming,Reserved,Unprivileged,Privileged"
|
|
bitfld.long 0x00 14.--15. "NSCFG,NS override" "Use incoming,Reserved,Secure,Non-secure"
|
|
bitfld.long 0x00 12.--13. "SHCFG,Shareability override" "Non-shareable,Use incoming,Outer shareable,Inner Shareable"
|
|
newline
|
|
bitfld.long 0x00 10. 11. "ALLOCCFG[2],Read allocate hint (RA) override" "Use incoming,Use incoming,No read-allocate,Read allocate"
|
|
bitfld.long 0x00 9. 11. "ALLOCCFG[1],Write allocate hint (WA) override" "Use incoming,Use incoming,No write-allocate,Write allocate"
|
|
bitfld.long 0x00 8. 11. "ALLOCCFG[0],Transient hint (TR) override" "Use incoming,Use incoming,Non-transient,Transient"
|
|
newline
|
|
bitfld.long 0x00 4. "MTCFG,Memory type override enable" "Use incoming,Override by MEMATTR fld"
|
|
bitfld.long 0x00 0.--3. "MEMATTR,Memory type override" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
rgroup.long 0x8048++0x03
|
|
line.long 0x00 "SMMU_S_AGBPA,Alternate Secure Global Bypass Attribute Register"
|
|
if ((per.l(&SMMU_base+0x8020)&0x01)==0x00)&&((per.l(&SMMU_base+0x20)&0x01)==0x00)
|
|
group.long 0x803C++0x03
|
|
line.long 0x00 "SMMU_S_INIT,Secure Initialization Control Register"
|
|
bitfld.long 0x00 0. "INV_ALL,Invalidate all cache and TLB contents" "No effect,Invalidate"
|
|
else
|
|
rgroup.long 0x803C++0x03
|
|
line.long 0x00 "SMMU_S_INIT,Secure Initialization Control Register"
|
|
bitfld.long 0x00 0. "INV_ALL,Invalidate all cache and TLB contents" "No effect,Invalidate"
|
|
endif
|
|
group.long 0x8050++0x03
|
|
line.long 0x00 "SMMU_S_IRQ_CTRL,Secure Interrupt Control Register"
|
|
bitfld.long 0x00 2. "EVENTQ_IRQEN,Secure event queue interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "GERROR_IRQEN,Secure GERROR interrupt enable" "Disabled,Enabled"
|
|
rgroup.long 0x8054++0x03
|
|
line.long 0x00 "SMMU_S_IRQ_CTRLACK,Secure Interrupt Control Register Update Acknowledge"
|
|
bitfld.long 0x00 2. "EVENTQ_IRQEN,Secure event queue interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "GERROR_IRQEN,Secure GERROR interrupt enable" "Disabled,Enabled"
|
|
rgroup.long 0x8060++0x03
|
|
line.long 0x00 "SMMU_S_GERROR,Secure Global Error Status Register"
|
|
bitfld.long 0x00 8. "SFM_ERR,The SMMU has entered service failure mode" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. "MSI_GERROR_ABT_ERR,A secure GERROR MSI was terminated with abort" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 5. "MSI_EVENTQ_ABT_ERR,A secure event queue MSI was terminated with abort" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. "MSI_CMDQ_ABT_ERR,A secure CMD_SYNC MSI was terminated with abort" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 2. "EVENTQ_ABT_ERR,An access to the secure event queue was terminated with abort" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. "CMDQ_ERR,Command has been encountered that cannot be processed on the secure command queue" "Not occurred,Occurred"
|
|
group.long 0x8064++0x03
|
|
line.long 0x00 "SMMU_S_GERRORN,Secure Global Error Acknowledgment Register"
|
|
bitfld.long 0x00 8. "SFM_ERR,The SMMU has entered service failure mode" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. "MSI_GERROR_ABT_ERR,A secure GERROR MSI was terminated with abort" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 5. "MSI_EVENTQ_ABT_ERR,A secure event queue MSI was terminated with abort" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. "MSI_CMDQ_ABT_ERR,A secure CMD_SYNC MSI was terminated with abort" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 2. "EVENTQ_ABT_ERR,An access to the secure event queue was terminated with abort" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. "CMDQ_ERR,Command has been encountered that cannot be processed on the secure command queue" "Not occurred,Occurred"
|
|
if ((per.l(&SMMU_base+0x8050)&0x01)==0x00)
|
|
group.quad 0x8068++0x07
|
|
line.quad 0x00 "SMMU_S_GERROR_IRQ_CFG0,Secure Global Error IRQ Configuration Register 0"
|
|
hexmask.quad 0x00 2.--51. 0x04 "ADDR,PA of MSI target register"
|
|
group.long 0x8070++0x07
|
|
line.long 0x00 "SMMU_S_GERROR_IRQ_CFG1,Secure Global Error IRQ Configuration Register 1"
|
|
line.long 0x04 "SMMU_S_GERROR_IRQ_CFG2,Secure Global Error IRQ Configuration Register 2"
|
|
bitfld.long 0x04 4.--5. "SH,Shareability" "Non-shareable,Reserved,Outer shareable,Inner sharable"
|
|
bitfld.long 0x04 0.--3. "MEMATTR,Memory type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.quad 0x8068++0x07
|
|
line.quad 0x00 "SMMU_S_GERROR_IRQ_CFG0,Secure Global Error IRQ Configuration Register 0"
|
|
hexmask.quad 0x00 2.--51. 0x04 "ADDR,PA of MSI target register"
|
|
rgroup.long 0x8070++0x07
|
|
line.long 0x00 "SMMU_S_GERROR_IRQ_CFG1,Secure Global Error IRQ Configuration Register 1"
|
|
line.long 0x04 "SMMU_S_GERROR_IRQ_CFG2,Secure Global Error IRQ Configuration Register 2"
|
|
bitfld.long 0x04 4.--5. "SH,Shareability" "Non-shareable,Reserved,Outer shareable,Inner sharable"
|
|
bitfld.long 0x04 0.--3. "MEMATTR,Memory type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if ((per.l(&SMMU_base+0x8020)&0x01)==0x00)
|
|
group.quad 0x8080++0x07
|
|
line.quad 0x00 "SMMU_S_STRTAB_BASE,Secure Stream Table Base Address Register"
|
|
bitfld.quad 0x00 62. "RA,Read allocate hint" "No read-allocate,Read-allocate"
|
|
hexmask.quad 0x00 6.--51. 0x40 "ADDR,Physical address of secure stream table base"
|
|
group.long 0x8088++0x03
|
|
line.long 0x00 "SMMU_S_STRTAB_BASE_CFG,Secure Stream Table Configuration Register"
|
|
bitfld.long 0x00 16.--17. "FMT,Format of secure stream table" "Linear,2-level,?..."
|
|
bitfld.long 0x00 6.--10. "SPLIT,StreamID split point for multi-level table (number of bits at the bottom level)" ",Reserved,Reserved,Reserved,Reserved,Reserved,4 KB leaf,Reserved,16 KB leaf,Reserved,64 KB leaf,?..."
|
|
bitfld.long 0x00 0.--5. "LOG2SIZE,Table size as log2(entries)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
rgroup.quad 0x8080++0x07
|
|
line.quad 0x00 "SMMU_S_STRTAB_BASE,Secure Stream Table Base Address Register"
|
|
bitfld.quad 0x00 62. "RA,Read allocate hint" "No read-allocate,Read-allocate"
|
|
hexmask.quad 0x00 6.--51. 0x40 "ADDR,Physical address of secure stream table base"
|
|
rgroup.long 0x8088++0x03
|
|
line.long 0x00 "SMMU_S_STRTAB_BASE_CFG,Secure Stream Table Configuration Register"
|
|
bitfld.long 0x00 16.--17. "FMT,Format of secure stream table" "Linear,2-level,?..."
|
|
bitfld.long 0x00 6.--10. "SPLIT,StreamID split point for multi-level table (number of bits at the bottom level)" ",Reserved,Reserved,Reserved,Reserved,Reserved,4 KB leaf,Reserved,16 KB leaf,Reserved,64 KB leaf,?..."
|
|
bitfld.long 0x00 0.--5. "LOG2SIZE,Table size as log2(entries)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
if ((per.l(&SMMU_base+0x8020)&0x08)==0x00)
|
|
group.quad 0x8090++0x07
|
|
line.quad 0x00 "SMMU_S_CMDQ_BASE,Secure Command Queue Base Address Register"
|
|
bitfld.quad 0x00 62. "RA,Read allocate hint" "No read-allocate,Read-allocate"
|
|
hexmask.quad 0x00 5.--51. 0x20 "ADDR,Physical address of secure command queue base"
|
|
bitfld.quad 0x00 0.--4. "LOG2SIZE,Queue size as log2(entries)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,?..."
|
|
else
|
|
rgroup.quad 0x8090++0x07
|
|
line.quad 0x00 "SMMU_S_CMDQ_BASE,Secure Command Queue Base Address Register"
|
|
bitfld.quad 0x00 62. "RA,Read allocate hint" "No read-allocate,Read-allocate"
|
|
hexmask.quad 0x00 5.--51. 0x20 "ADDR,Physical address of secure command queue base"
|
|
bitfld.quad 0x00 0.--4. "LOG2SIZE,Queue size as log2(entries)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,?..."
|
|
endif
|
|
newline
|
|
group.long 0x8098++0x03
|
|
line.long 0x00 "SMMU_S_CMDQ_PROD,Secure Command Queue Producer Index Register"
|
|
hexmask.long 0x00 0.--19. 0x01 "WR,Event queue write index wrap flag and write index"
|
|
group.long 0x809C++0x03
|
|
line.long 0x00 "SMMU_S_CMDQ_CONS,Secure Command Queue Consumer Index Register"
|
|
hexmask.long.byte 0x00 24.--30. 0x01 "ERR,Error reason code"
|
|
hexmask.long 0x00 0.--19. 0x01 "RD,Queue read index wrap flag and read index"
|
|
newline
|
|
if ((per.l(&SMMU_base+0x8020)&0x04)==0x00)
|
|
group.quad 0x80A0++0x07
|
|
line.quad 0x00 "SMMU_S_EVENTQ_BASE,Secure Event Queue Base Address Register"
|
|
bitfld.quad 0x00 62. "WA,Write allocate hint" "No write-allocate,Write-allocate"
|
|
hexmask.quad 0x00 5.--51. 0x20 "ADDR,Physical address of secure event queue base"
|
|
bitfld.quad 0x00 0.--4. "LOG2SIZE,Queue size as log2(entries)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,?..."
|
|
else
|
|
rgroup.quad 0x80A0++0x07
|
|
line.quad 0x00 "SMMU_S_EVENTQ_BASE,Secure Event Queue Base Address Register"
|
|
bitfld.quad 0x00 62. "WA,Write allocate hint" "No write-allocate,Write-allocate"
|
|
hexmask.quad 0x00 5.--51. 0x20 "ADDR,Physical address of secure event queue base"
|
|
bitfld.quad 0x00 0.--4. "LOG2SIZE,Queue size as log2(entries)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,?..."
|
|
endif
|
|
newline
|
|
group.long 0x80A8++0x03
|
|
line.long 0x00 "SMMU_S_EVENTQ_PROD,Secure Event Queue Producer Index Register"
|
|
bitfld.long 0x00 31. "OVFLG,Queue overflowed" "No overflow occured,Overflow occured"
|
|
hexmask.long 0x00 0.--19. 0x01 "WR,Event queue write index wrap flag and write index"
|
|
group.long 0x80AC++0x03
|
|
line.long 0x00 "SMMU_S_EVENTQ_CONS,Secure Event Queue Consumer Index Register"
|
|
bitfld.long 0x00 31. "OVACKFLG,Overflow acknowledge flag"
|
|
hexmask.long 0x00 0.--19. 0x01 "RD,Queue read index wrap flag and read index"
|
|
newline
|
|
if ((per.l(&SMMU_base+0x8050)&0x04)==0x00)
|
|
group.quad 0x80B0++0x07
|
|
line.quad 0x00 "SMMU_S_EVENTQ_IRQ_CFG0,Secure Event Queue IRQ Configuration Register 0"
|
|
hexmask.quad 0x00 2.--51. 0x04 "ADDR,PA of MSI target register"
|
|
group.long 0x80B8++0x07
|
|
line.long 0x00 "SMMU_S_EVENTQ_IRQ_CFG1,Secure Event Queue IRQ Configuration Register 1"
|
|
line.long 0x04 "SMMU_S_EVENTQ_IRQ_CFG2,Secure Event Queue IRQ Configuration Register 2"
|
|
bitfld.long 0x04 4.--5. "SH,Shareability" "Non-shareable,Reserved,Outer shareable,Inner sharable"
|
|
bitfld.long 0x04 0.--3. "MEMATTR,Memory type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.quad 0x80B0++0x07
|
|
line.quad 0x00 "SMMU_S_EVENTQ_IRQ_CFG0,Secure Event Queue IRQ Configuration Register 0"
|
|
hexmask.quad 0x00 2.--51. 0x04 "ADDR,PA of MSI target register"
|
|
rgroup.long 0x80B8++0x07
|
|
line.long 0x00 "SMMU_S_EVENTQ_IRQ_CFG1,Secure Event Queue IRQ Configuration Register 1"
|
|
line.long 0x04 "SMMU_S_EVENTQ_IRQ_CFG2,Secure Event Queue IRQ Configuration Register 2"
|
|
bitfld.long 0x04 4.--5. "SH,Shareability" "Non-shareable,Reserved,Outer shareable,Inner sharable"
|
|
bitfld.long 0x04 0.--3. "MEMATTR,Memory type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
rgroup.long 0x8100++0x03
|
|
line.long 0x00 "SMMU_S_GATOS_CTRL,Secure SMMU_GATOS_CTRL"
|
|
rgroup.quad 0x8108++0x17
|
|
line.quad 0x00 "SMMU_S_GATOS_SID,Secure SMMU_GATOS_SID"
|
|
line.quad 0x08 "SMMU_S_GATOS_ADDR,Secure SMMU_GATOS_ADDR"
|
|
line.quad 0x10 "SMMU_S_GATOS_PAR,Secure SMMU_GATOS_PAR"
|
|
rgroup.long 0x8130++0x03
|
|
line.long 0x00 "SMMU_S_MPAMIDR,Secure MPAM Capability Identification Register"
|
|
rgroup.long 0x8138++0x07
|
|
line.long 0x00 "SMMU_S_GMPAM,Secure Global MPAM Configuration Register"
|
|
line.long 0x04 "SMMU_S_GBPMPAM,Secure MPAM Configuration Register For Global Bypass Transactions"
|
|
tree.end
|
|
endif
|
|
sif ("&STE_base"!="-")
|
|
tree "System MMU '&SMMU_name' (MMU600) - Stream Table Entry"
|
|
base &STE_base
|
|
group.quad 0x00++0x07
|
|
line.quad 0x00 "STE0,Stream Table Entry 0"
|
|
bitfld.quad 0x00 59.--63. "S1CDMAX,Number of CDs pointed to by S1ContextPtr" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,?..."
|
|
hexmask.quad 0x00 6.--51. 0x40 "S1CONTEXTPTR,Stage 1 context descriptor pointer"
|
|
bitfld.quad 0x00 4.--5. "S1FMT,S1ContextPtr pointer target" "Linear table indexed by SubstreamID,2-level table with 4KB L2 leafs,2-level table with 64KB L2 leafs,?..."
|
|
newline
|
|
bitfld.quad 0x00 1.--3. "CONFIG,Stream configuration [Traffic/Stage 1/Stage 2]" "Not allowed/-/-,Reserved,Reserved,Reserved,Allowed/Bypass/Bypass,Allowed/Translate/Bypass,Allowed/Bypass/Translate,Allowed/Translate/Translate"
|
|
bitfld.quad 0x00 0. "V,Structure contents are valid" "Invalid,Valid"
|
|
group.quad 0x08++0x07
|
|
line.quad 0x00 "STE1,Stream Table Entry 1"
|
|
bitfld.quad 0x00 50.--51. "INSTCFG,Inst/Data attribute configuration" "Use incoming,Reserved,Data,Instruction"
|
|
bitfld.quad 0x00 48.--49. "PRIVCFG,User/privileged attribute configuration" "Use incoming,Reserved,Unprivileged,Privileged"
|
|
bitfld.quad 0x00 46.--47. "NSCFG,Bypass NS attribute configuration" "Use incoming,Reserved,Secure,Non-secure"
|
|
newline
|
|
bitfld.quad 0x00 44.--45. "SHCFG,Shareability override" "Non-shareable,Use incoming,Outer shareable,Inner shareable"
|
|
newline
|
|
bitfld.quad 0x00 39. 40. "ALLOCCFG[2],Read allocate hint (RA) override" "Use incoming,Use incoming,No read-allocate,Read allocate"
|
|
bitfld.quad 0x00 38. 40. "ALLOCCFG[1],Write allocate hint (WA) override" "Use incoming,Use incoming,No write-allocate,Write allocate"
|
|
bitfld.quad 0x00 37. 40. "ALLOCCFG[0],Transient hint (TR) override" "Use incoming,Use incoming,Non-transient,Transient"
|
|
newline
|
|
bitfld.quad 0x00 36. "MTCFG,Memory type configuration override" "Use incoming,MEMATTR dependent"
|
|
bitfld.quad 0x00 32.--35. "MEMATTR,Memory type override" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.quad 0x00 30.--31. "STRW,StreamWorld control [NS stream/S stream]" "NS-EL1/Secure,-/EL3,EL2/-,?..."
|
|
bitfld.quad 0x00 28.--29. "EATS,Enable PCIe ATS translation and traffic" "Disabled,Full ATS,Split-stage ATS,?..."
|
|
bitfld.quad 0x00 27. "S1STALLD,Stage 1 stall disable" "No,Yes"
|
|
newline
|
|
bitfld.quad 0x00 19. "MEV,Merge events arising from terminated transactions from this stream" "Disabled,Enabled"
|
|
bitfld.quad 0x00 18. "PPAR,PRI page request auto response PASID TLP prefix" "Not included,Included"
|
|
bitfld.quad 0x00 17. "DCP,Directed cache prefetch operations" "Inhibited,Permitted"
|
|
newline
|
|
bitfld.quad 0x00 13.--16. "CONT,Contiguous hint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.quad 0x00 12. "DRE,Destructive read enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 11. "S2HWU62,Controls the interpretation of bit [62] of the stage 2 translation table final-level(page or block) descriptor" "Not interpreted,Interpreted"
|
|
bitfld.quad 0x00 10. "S2HWU61,Controls the interpretation of bit [61] of the stage 2 translation table final-level(page or block) descriptor" "Not interpreted,Interpreted"
|
|
newline
|
|
bitfld.quad 0x00 9. "S2HWU60,Controls the interpretation of bit [60] of the stage 2 translation table final-level(page or block) descriptor" "Not interpreted,Interpreted"
|
|
bitfld.quad 0x00 8. "S2HWU59,Controls the interpretation of bit [59] of the stage 2 translation table final-level(page or block) descriptor" "Not interpreted,Interpreted"
|
|
newline
|
|
bitfld.quad 0x00 6.--7. "S1CSH,S1ContextPtr memory shareability attribute" "Non-shareable,Reserved,Outer shareable,Inner shareable"
|
|
bitfld.quad 0x00 4.--5. "S1COR,S1ContextPtr memory outer region attribute" "Non-cacheable,Write-back cacheable + RA,Write-through cacheable,Write-back cacheable"
|
|
bitfld.quad 0x00 2.--3. "S1CIR,S1ContextPtr memory inner region attribute" "Non-cacheable,Write-back cacheable + RA,Write-through cacheable,Write-back cacheable"
|
|
newline
|
|
bitfld.quad 0x00 0.--1. "S1DSS,Determines the behavior of a transaction or translation request that arrives without an associated substream" "Terminate,Bypass stage 1,Use CD from substream 0,?..."
|
|
group.quad 0x10++0x07
|
|
line.quad 0x00 "STE2,Stream Table Entry 2"
|
|
bitfld.quad 0x00 57.--58. "S2R_S2S,Stage 2 fault behavior [Transaction / Fault event]" "Terminated with report/Not recorded,Stalled/Recorded,Terminated with report/Recorded,Stalled/Recorded"
|
|
bitfld.quad 0x00 55.--56. "S2HA_S2HD,Hardware translation table update of stage 2 access/dirty flags" "Disabled,Access flag,Reserved,Access flag / Dirty page"
|
|
bitfld.quad 0x00 54. "S2PTW,Protected table walk" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 53. "S2AFFD,Stage 2 access flag fault disable" "No,Yes"
|
|
bitfld.quad 0x00 52. "S2ENDI,Stage 2 translation table endianness" "Little endian,Big endian"
|
|
bitfld.quad 0x00 51. "S2AA64,Stage 2 translation table format" "AArch32 (LPAE),AArch64"
|
|
newline
|
|
bitfld.quad 0x00 48.--50. "S2PS,Physical address size" "32 bits,36 bits,40 bits,42 bits,44 bits,48 bits,52 bits,?..."
|
|
bitfld.quad 0x00 46.--47. "S2TG,Stage 2 translation granule size" "4 KB,64 KB,16 KB,?..."
|
|
bitfld.quad 0x00 44.--45. "S2SH0,Shareability for stage 2 translation table access" "Non-shareable,Reserved,Outer shareable,Inner shareable"
|
|
newline
|
|
bitfld.quad 0x00 42.--43. "S2OR0,Outer region cacheability for stage 2 translation table access" "Non-cacheable,Write-back cacheable/RA/WA,Write-through cacheable/RA,Write-back cacheable/RA"
|
|
bitfld.quad 0x00 40.--41. "S21R0,Inner region cacheability for stage 2 translation table access" "Non-cacheable,Write-back cacheable/RA/WA,Write-through cacheable/RA,Write-back cacheable/RA"
|
|
bitfld.quad 0x00 38.--39. "S2SL0,Starting level of stage 2 translation table walk" "0,1,2,3"
|
|
newline
|
|
bitfld.quad 0x00 32.--37. "S2T0SZ,Size of IPA input region covered by stage 2 translation table" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.quad.word 0x00 0.--15. 1. "S2VMID,Virtual machine identifier"
|
|
group.quad 0x18++0x07
|
|
line.quad 0x00 "STE3,Stream Table Entry 3"
|
|
hexmask.quad 0x00 4.--51. 0x10 "S2TTB,Address of translation table base"
|
|
tree.end
|
|
endif
|
|
sif ("&CD_base"!="-")
|
|
tree "System MMU '&SMMU_name' (MMU600) - Context Descriptor"
|
|
base &CD_base
|
|
if ((per.q(&CD_base+0x00)&0x20000000000)==0x00)
|
|
group.quad 0x00++0x07
|
|
line.quad 0x00 "CD0,Context Descriptor 0"
|
|
hexmask.quad.word 0x00 48.--63. 1. "ASID,Address space identifier"
|
|
bitfld.quad 0x00 47. "ASET,ASID set" "Shared,Non-shared"
|
|
bitfld.quad 0x00 44.--46. "ARS,Stage 1 fault behavior [Transaction / Fault event]" "Terminated silently/Not recorded,Stalled/Recorded,Terminated silently/Recorded,Stalled/Recorded,Terminated with report/Not recorded,Stalled/Recorded,Terminated with report/Recorded,Stalled/Recorded"
|
|
newline
|
|
bitfld.quad 0x00 42.--43. "HA_HD,Hardware translation table update of access/dirty flags for TT0 and TT1" "Disabled,Access flag,Reserved,Access flag / Dirty page"
|
|
bitfld.quad 0x00 41. "AA64,Translation table format" "AArch32,AArch64"
|
|
bitfld.quad 0x00 40. "PAN,Privileged access never" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 39. "TBI1,Top byte ignore for TTB1" "0,1"
|
|
bitfld.quad 0x00 38. "TBI0,Top byte ignore for TTB0" "0,1"
|
|
newline
|
|
bitfld.quad 0x00 37. "UWXN,Unprivileged write eXecute never" "Allowed,Not allowed"
|
|
bitfld.quad 0x00 36. "WXN,Write eXecute never" "Allowed,Not allowed"
|
|
bitfld.quad 0x00 35. "AFFD,Access flag fault disable" "No,Yes"
|
|
newline
|
|
bitfld.quad 0x00 32.--34. "IPS,Intermediate physical size" "32 bits,36 bits,40 bits,42 bits,44 bits,48 bits,52 bits,?..."
|
|
bitfld.quad 0x00 31. "V,CD valid" "Invalid,Valid"
|
|
bitfld.quad 0x00 30. "EPD1,TT1 translation table walk disable" "No,Yes"
|
|
newline
|
|
bitfld.quad 0x00 28.--29. "SH1,Shareability for TT1 access" "Non-shareable,Reserved,Outer shareable,Inner shareable"
|
|
bitfld.quad 0x00 26.--27. "OR1,Outer region cacheability for TT1 access" "Non-cacheable,Write-back cacheable/RA/WA,Write-through cacheable/RA,Write-back cacheable/RA"
|
|
bitfld.quad 0x00 24.--25. "IR1,Inner region cacheability for TT1 access" "Non-cacheable,Write-back cacheable/RA/WA,Write-through cacheable/RA,Write-back cacheable/RA"
|
|
newline
|
|
bitfld.quad 0x00 22.--23. "TG1,TT1 translation granule size" ",16 KB,4 KB,64 KB"
|
|
bitfld.quad 0x00 19.--21. "T1SZ,VA region size covered by TT1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.quad 0x00 15. "ENDI,Translation table endianness" "Little endian,Big endian"
|
|
bitfld.quad 0x00 14. "EPD0,TT0 translation table walk disable" "No,Yes"
|
|
newline
|
|
bitfld.quad 0x00 12.--13. "SH0,Shareability for TT0 access" "Non-shareable,Reserved,Outer shareable,Inner shareable"
|
|
bitfld.quad 0x00 10.--11. "OR0,Outer region cacheability for TT0 access" "Non-cacheable,Write-back cacheable/RA/WA,Write-through cacheable/RA,Write-back cacheable/RA"
|
|
bitfld.quad 0x00 8.--9. "IR0,Inner region cacheability for TT0 access" "Non-cacheable,Write-back cacheable/RA/WA,Write-through cacheable/RA,Write-back cacheable/RA"
|
|
newline
|
|
bitfld.quad 0x00 6.--7. "TG0,TT0 translation granule size" "4 KB,64 KB,16 KB,?..."
|
|
bitfld.quad 0x00 3.--5. "T0SZ,VA region size covered by TT0" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.quad 0x00++0x07
|
|
line.quad 0x00 "CD0,Context Descriptor 0"
|
|
hexmask.quad.word 0x00 48.--63. 1. "ASID,Address space identifier"
|
|
bitfld.quad 0x00 47. "ASET,ASID set" "Shared,Non-shared"
|
|
bitfld.quad 0x00 44.--46. "ARS,Stage 1 fault behavior [Transaction / Fault event]" "Terminated silently/Not recorded,Stalled/Recorded,Terminated silently/Recorded,Stalled/Recorded,Terminated with report/Not recorded,Stalled/Recorded,Terminated with report/Recorded,Stalled/Recorded"
|
|
newline
|
|
bitfld.quad 0x00 42.--43. "HA_HD,Hardware translation table update of access/dirty flags for TT0 and TT1" "Disabled,Access flag,Reserved,Access flag / Dirty page"
|
|
bitfld.quad 0x00 41. "AA64,Translation table format" "AArch32,AArch64"
|
|
bitfld.quad 0x00 40. "PAN,Privileged access never" "Disabled,Enabled"
|
|
newline
|
|
bitfld.quad 0x00 39. "TBI1,Top byte ignore for TTB1" "0,1"
|
|
bitfld.quad 0x00 38. "TBI0,Top byte ignore for TTB0" "0,1"
|
|
newline
|
|
bitfld.quad 0x00 37. "UWXN,Unprivileged write eXecute never" "Allowed,Not allowed"
|
|
bitfld.quad 0x00 36. "WXN,Write eXecute never" "Allowed,Not allowed"
|
|
bitfld.quad 0x00 35. "AFFD,Access flag fault disable" "No,Yes"
|
|
newline
|
|
bitfld.quad 0x00 32.--34. "IPS,Intermediate physical size" "32 bits,36 bits,40 bits,42 bits,44 bits,48 bits,52 bits,?..."
|
|
bitfld.quad 0x00 31. "V,CD valid" "Invalid,Valid"
|
|
bitfld.quad 0x00 30. "EPD1,TT1 translation table walk disable" "No,Yes"
|
|
newline
|
|
bitfld.quad 0x00 28.--29. "SH1,Shareability for TT1 access" "Non-shareable,Reserved,Outer shareable,Inner shareable"
|
|
bitfld.quad 0x00 26.--27. "OR1,Outer region cacheability for TT1 access" "Non-cacheable,Write-back cacheable/RA/WA,Write-through cacheable/RA,Write-back cacheable/RA"
|
|
bitfld.quad 0x00 24.--25. "IR1,Inner region cacheability for TT1 access" "Non-cacheable,Write-back cacheable/RA/WA,Write-through cacheable/RA,Write-back cacheable/RA"
|
|
newline
|
|
bitfld.quad 0x00 22.--23. "TG1,TT1 translation granule size" ",16 KB,4 KB,64 KB"
|
|
bitfld.quad 0x00 16.--21. "T1SZ,VA region size covered by TT1" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,?..."
|
|
newline
|
|
bitfld.quad 0x00 15. "ENDI,Translation table endianness" "Little endian,Big endian"
|
|
bitfld.quad 0x00 14. "EPD0,TT0 translation table walk disable" "No,Yes"
|
|
newline
|
|
bitfld.quad 0x00 12.--13. "SH0,Shareability for TT0 access" "Non-shareable,Reserved,Outer shareable,Inner shareable"
|
|
bitfld.quad 0x00 10.--11. "OR0,Outer region cacheability for TT0 access" "Non-cacheable,Write-back cacheable/RA/WA,Write-through cacheable/RA,Write-back cacheable/RA"
|
|
bitfld.quad 0x00 8.--9. "IR0,Inner region cacheability for TT0 access" "Non-cacheable,Write-back cacheable/RA/WA,Write-through cacheable/RA,Write-back cacheable/RA"
|
|
newline
|
|
bitfld.quad 0x00 6.--7. "TG0,TT0 translation granule size" "4 KB,64 KB,16 KB,?..."
|
|
bitfld.quad 0x00 0.--5. "T0SZ,VA region size covered by TT0" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,?..."
|
|
endif
|
|
group.quad 0x08++0x07
|
|
line.quad 0x00 "CD1,Context Descriptor 1"
|
|
bitfld.quad 0x00 63. "HWU062,Controls the interpretation of bit [62] of the stage 1 translation table final-level(page or block) descriptor pointed at by CD.TTB0" "Not interpreted,Interpreted"
|
|
bitfld.quad 0x00 62. "HWU061,Controls the interpretation of bit [61] of the stage 1 translation table final-level(page or block) descriptor pointed at by CD.TTB0" "Not interpreted,Interpreted"
|
|
newline
|
|
bitfld.quad 0x00 61. "HWU060,Controls the interpretation of bit [60] of the stage 1 translation table final-level(page or block) descriptor pointed at by CD.TTB0" "Not interpreted,Interpreted"
|
|
bitfld.quad 0x00 60. "HWU059,Controls the interpretation of bit [59] of the stage 1 translation table final-level(page or block) descriptor pointed at by CD.TTB0" "Not interpreted,Interpreted"
|
|
newline
|
|
hexmask.quad 0x00 4.--51. 0x10 "TTB0,Address of TT0 base"
|
|
newline
|
|
bitfld.quad 0x00 1. "HAD0,Hierarchical attribute disable for the TTB0 region" "No,Yes"
|
|
bitfld.quad 0x00 0. "NSCFG0,Non-secure attribute for the memory associated with the starting level translation table to which TTB0 points" "NS == 0,NS == 1"
|
|
group.quad 0x10++0x07
|
|
line.quad 0x00 "CD2,Context Descriptor 2"
|
|
bitfld.quad 0x00 63. "HWU162,Controls the interpretation of bit [62] of the stage 1 translation table final-level(page or block) descriptor pointed at by CD.TTB1" "Not interpreted,Interpreted"
|
|
bitfld.quad 0x00 62. "HWU161,Controls the interpretation of bit [61] of the stage 1 translation table final-level(page or block) descriptor pointed at by CD.TTB1" "Not interpreted,Interpreted"
|
|
newline
|
|
bitfld.quad 0x00 61. "HWU160,Controls the interpretation of bit [60] of the stage 1 translation table final-level(page or block) descriptor pointed at by CD.TTB1" "Not interpreted,Interpreted"
|
|
bitfld.quad 0x00 60. "HWU159,Controls the interpretation of bit [59] of the stage 1 translation table final-level(page or block) descriptor pointed at by CD.TTB1" "Not interpreted,Interpreted"
|
|
newline
|
|
hexmask.quad 0x00 4.--51. 0x10 "TTB1,Address of TT1 base"
|
|
newline
|
|
bitfld.quad 0x00 1. "HAD1,Hierarchical attribute disable for the TTB1 region" "No,Yes"
|
|
bitfld.quad 0x00 0. "NSCFG1,Non-secure attribute for the memory associated with the starting level translation table to which TTB1 points" "NS == 0,NS == 1"
|
|
group.quad 0x18++0x07
|
|
line.quad 0x00 "CD3,Context Descriptor 3"
|
|
hexmask.quad.long 0x00 32.--63. 1. "MAIR1,Memory attribute indirection register 1"
|
|
hexmask.quad.long 0x00 0.--31. 1. "MAIR0,Memory attribute indirection register 0"
|
|
group.quad 0x20++0x07
|
|
line.quad 0x00 "CD4,Context Descriptor 4"
|
|
hexmask.quad.long 0x00 32.--63. 1. "AMAIR1,Auxiliary memory attribute indirection register 1"
|
|
hexmask.quad.long 0x00 0.--31. 1. "AMAIR0,Auxiliary memory attribute indirection register 0"
|
|
tree.end
|
|
endif
|
|
sif ("&MMU600_base"!="-")
|
|
tree "System MMU '&SMMU_name' (MMU600) - MMU600 Specific Registers"
|
|
base &MMU600_base
|
|
tree "Translation Control Unit (TCU) Registers"
|
|
tree "TCU Component and Peripheral ID Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree.end
|
|
tree "TCU Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
tree "TCU Microarchitectural Registers"
|
|
group.long 0x8E00++0x07
|
|
line.long 0x00 "TCU_CTRL,TCU Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "AUX,AUX"
|
|
newline
|
|
bitfld.long 0x00 15. "WCS2L3_DIS,Stage 2 level 3 walk cache disable" "No,Yes"
|
|
bitfld.long 0x00 14. "WCS2L2_DIS,Stage 2 level 2 walk cache disable" "No,Yes"
|
|
bitfld.long 0x00 13. "WCS2L1_DIS,Stage 2 level 1 walk cache disable" "No,Yes"
|
|
bitfld.long 0x00 12. "WCS2L0_DIS,Stage 2 level 0 walk cache disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. "WCS1L3_DIS,Stage 1 level 3 walk cache disable" "No,Yes"
|
|
bitfld.long 0x00 10. "WCS1L2_DIS,Stage 1 level 2 walk cache disable" "No,Yes"
|
|
bitfld.long 0x00 9. "WCS1L1_DIS,Stage 1 level 1 walk cache disable" "No,Yes"
|
|
bitfld.long 0x00 8. "WCS1L0_DIS,Stage 1 level 0 walk cache disable" "No,Yes"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "AUX,AUX"
|
|
line.long 0x04 "TCU_QOS,TCU Quality Of Service Register"
|
|
bitfld.long 0x04 24.--27. "QOS_DVMSYNC,AxQOS value that is used for DVM sync completion messages" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--23. "QOS_MSI,AxQOS value that is used for MSIs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. "QOS_QUEUE,AxQOS value that is used for queue accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 12.--15. "QOS_PTW3,AxQOS value that is used for translation table walks for translations where TCU_NODE_CTRLn.PRIORITY = 3 for the requesting node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. "QOS_PTW2,AxQOS value that is used for translation table walks for translations where TCU_NODE_CTRLn.PRIORITY = 2 for the requesting node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 4.--7. "QOS_PTW1,AxQOS value that is used for translation table walks for translations where TCU_NODE_CTRLn.PRIORITY = 1 for the requesting node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. "QOS_PTW0,AxQOS value that is used for translation table walks for translations where TCU_NODE_CTRLn.PRIORITY = 0 for the requesting node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x8E08++0x03
|
|
line.long 0x00 "TCU_CFG,TCU Configuration Information Register"
|
|
hexmask.long.word 0x00 4.--15. 1. "XLATE_SLOTS,Number of translation slots that are available for sharing between all nodes"
|
|
rgroup.long 0x8E10++0x03
|
|
line.long 0x00 "TCU_STATUS,TCU Status Information Register"
|
|
hexmask.long.word 0x00 4.--15. 1. "GNT_XLATE_SLOTS,Number of translation slots that are currently allocated to connected nodes"
|
|
group.long 0x8E18++0x03
|
|
line.long 0x00 "TCU_SCR,TCU Secure Control Register"
|
|
bitfld.long 0x00 3. "NS_INIT,Non-secure register access to SMMU_S_INIT is permitted" "Not permitted,Permitted"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted for RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted for MMU-600 registers" "Not permitted,Permitted"
|
|
tree "TCU Node Control Registers"
|
|
group.long 0x9000++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[0],TCU Node 0 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 0 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 0 priority level" "0,1,2,3"
|
|
rgroup.long (0x9000+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[0],TCU Node 0 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9004++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[1],TCU Node 1 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 1 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 1 priority level" "0,1,2,3"
|
|
rgroup.long (0x9004+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[1],TCU Node 1 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9008++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[2],TCU Node 2 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 2 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 2 priority level" "0,1,2,3"
|
|
rgroup.long (0x9008+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[2],TCU Node 2 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x900C++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[3],TCU Node 3 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 3 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 3 priority level" "0,1,2,3"
|
|
rgroup.long (0x900C+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[3],TCU Node 3 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9010++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[4],TCU Node 4 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 4 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 4 priority level" "0,1,2,3"
|
|
rgroup.long (0x9010+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[4],TCU Node 4 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9014++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[5],TCU Node 5 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 5 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 5 priority level" "0,1,2,3"
|
|
rgroup.long (0x9014+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[5],TCU Node 5 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9018++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[6],TCU Node 6 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 6 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 6 priority level" "0,1,2,3"
|
|
rgroup.long (0x9018+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[6],TCU Node 6 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x901C++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[7],TCU Node 7 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 7 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 7 priority level" "0,1,2,3"
|
|
rgroup.long (0x901C+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[7],TCU Node 7 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9020++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[8],TCU Node 8 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 8 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 8 priority level" "0,1,2,3"
|
|
rgroup.long (0x9020+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[8],TCU Node 8 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9024++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[9],TCU Node 9 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 9 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 9 priority level" "0,1,2,3"
|
|
rgroup.long (0x9024+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[9],TCU Node 9 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9028++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[10],TCU Node 10 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 10 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 10 priority level" "0,1,2,3"
|
|
rgroup.long (0x9028+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[10],TCU Node 10 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x902C++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[11],TCU Node 11 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 11 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 11 priority level" "0,1,2,3"
|
|
rgroup.long (0x902C+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[11],TCU Node 11 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9030++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[12],TCU Node 12 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 12 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 12 priority level" "0,1,2,3"
|
|
rgroup.long (0x9030+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[12],TCU Node 12 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9034++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[13],TCU Node 13 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 13 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 13 priority level" "0,1,2,3"
|
|
rgroup.long (0x9034+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[13],TCU Node 13 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9038++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[14],TCU Node 14 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 14 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 14 priority level" "0,1,2,3"
|
|
rgroup.long (0x9038+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[14],TCU Node 14 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x903C++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[15],TCU Node 15 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 15 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 15 priority level" "0,1,2,3"
|
|
rgroup.long (0x903C+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[15],TCU Node 15 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9040++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[16],TCU Node 16 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 16 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 16 priority level" "0,1,2,3"
|
|
rgroup.long (0x9040+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[16],TCU Node 16 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9044++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[17],TCU Node 17 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 17 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 17 priority level" "0,1,2,3"
|
|
rgroup.long (0x9044+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[17],TCU Node 17 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9048++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[18],TCU Node 18 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 18 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 18 priority level" "0,1,2,3"
|
|
rgroup.long (0x9048+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[18],TCU Node 18 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x904C++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[19],TCU Node 19 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 19 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 19 priority level" "0,1,2,3"
|
|
rgroup.long (0x904C+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[19],TCU Node 19 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9050++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[20],TCU Node 20 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 20 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 20 priority level" "0,1,2,3"
|
|
rgroup.long (0x9050+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[20],TCU Node 20 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9054++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[21],TCU Node 21 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 21 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 21 priority level" "0,1,2,3"
|
|
rgroup.long (0x9054+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[21],TCU Node 21 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9058++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[22],TCU Node 22 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 22 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 22 priority level" "0,1,2,3"
|
|
rgroup.long (0x9058+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[22],TCU Node 22 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x905C++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[23],TCU Node 23 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 23 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 23 priority level" "0,1,2,3"
|
|
rgroup.long (0x905C+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[23],TCU Node 23 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9060++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[24],TCU Node 24 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 24 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 24 priority level" "0,1,2,3"
|
|
rgroup.long (0x9060+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[24],TCU Node 24 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9064++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[25],TCU Node 25 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 25 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 25 priority level" "0,1,2,3"
|
|
rgroup.long (0x9064+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[25],TCU Node 25 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9068++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[26],TCU Node 26 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 26 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 26 priority level" "0,1,2,3"
|
|
rgroup.long (0x9068+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[26],TCU Node 26 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x906C++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[27],TCU Node 27 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 27 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 27 priority level" "0,1,2,3"
|
|
rgroup.long (0x906C+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[27],TCU Node 27 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9070++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[28],TCU Node 28 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 28 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 28 priority level" "0,1,2,3"
|
|
rgroup.long (0x9070+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[28],TCU Node 28 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9074++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[29],TCU Node 29 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 29 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 29 priority level" "0,1,2,3"
|
|
rgroup.long (0x9074+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[29],TCU Node 29 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9078++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[30],TCU Node 30 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 30 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 30 priority level" "0,1,2,3"
|
|
rgroup.long (0x9078+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[30],TCU Node 30 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x907C++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[31],TCU Node 31 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 31 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 31 priority level" "0,1,2,3"
|
|
rgroup.long (0x907C+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[31],TCU Node 31 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9080++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[32],TCU Node 32 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 32 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 32 priority level" "0,1,2,3"
|
|
rgroup.long (0x9080+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[32],TCU Node 32 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9084++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[33],TCU Node 33 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 33 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 33 priority level" "0,1,2,3"
|
|
rgroup.long (0x9084+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[33],TCU Node 33 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9088++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[34],TCU Node 34 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 34 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 34 priority level" "0,1,2,3"
|
|
rgroup.long (0x9088+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[34],TCU Node 34 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x908C++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[35],TCU Node 35 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 35 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 35 priority level" "0,1,2,3"
|
|
rgroup.long (0x908C+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[35],TCU Node 35 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9090++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[36],TCU Node 36 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 36 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 36 priority level" "0,1,2,3"
|
|
rgroup.long (0x9090+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[36],TCU Node 36 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9094++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[37],TCU Node 37 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 37 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 37 priority level" "0,1,2,3"
|
|
rgroup.long (0x9094+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[37],TCU Node 37 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9098++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[38],TCU Node 38 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 38 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 38 priority level" "0,1,2,3"
|
|
rgroup.long (0x9098+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[38],TCU Node 38 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x909C++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[39],TCU Node 39 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 39 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 39 priority level" "0,1,2,3"
|
|
rgroup.long (0x909C+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[39],TCU Node 39 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x90A0++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[40],TCU Node 40 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 40 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 40 priority level" "0,1,2,3"
|
|
rgroup.long (0x90A0+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[40],TCU Node 40 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x90A4++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[41],TCU Node 41 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 41 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 41 priority level" "0,1,2,3"
|
|
rgroup.long (0x90A4+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[41],TCU Node 41 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x90A8++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[42],TCU Node 42 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 42 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 42 priority level" "0,1,2,3"
|
|
rgroup.long (0x90A8+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[42],TCU Node 42 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x90AC++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[43],TCU Node 43 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 43 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 43 priority level" "0,1,2,3"
|
|
rgroup.long (0x90AC+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[43],TCU Node 43 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x90B0++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[44],TCU Node 44 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 44 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 44 priority level" "0,1,2,3"
|
|
rgroup.long (0x90B0+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[44],TCU Node 44 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x90B4++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[45],TCU Node 45 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 45 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 45 priority level" "0,1,2,3"
|
|
rgroup.long (0x90B4+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[45],TCU Node 45 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x90B8++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[46],TCU Node 46 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 46 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 46 priority level" "0,1,2,3"
|
|
rgroup.long (0x90B8+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[46],TCU Node 46 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x90BC++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[47],TCU Node 47 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 47 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 47 priority level" "0,1,2,3"
|
|
rgroup.long (0x90BC+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[47],TCU Node 47 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x90C0++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[48],TCU Node 48 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 48 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 48 priority level" "0,1,2,3"
|
|
rgroup.long (0x90C0+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[48],TCU Node 48 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x90C4++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[49],TCU Node 49 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 49 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 49 priority level" "0,1,2,3"
|
|
rgroup.long (0x90C4+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[49],TCU Node 49 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x90C8++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[50],TCU Node 50 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 50 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 50 priority level" "0,1,2,3"
|
|
rgroup.long (0x90C8+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[50],TCU Node 50 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x90CC++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[51],TCU Node 51 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 51 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 51 priority level" "0,1,2,3"
|
|
rgroup.long (0x90CC+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[51],TCU Node 51 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x90D0++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[52],TCU Node 52 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 52 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 52 priority level" "0,1,2,3"
|
|
rgroup.long (0x90D0+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[52],TCU Node 52 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x90D4++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[53],TCU Node 53 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 53 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 53 priority level" "0,1,2,3"
|
|
rgroup.long (0x90D4+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[53],TCU Node 53 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x90D8++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[54],TCU Node 54 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 54 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 54 priority level" "0,1,2,3"
|
|
rgroup.long (0x90D8+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[54],TCU Node 54 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x90DC++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[55],TCU Node 55 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 55 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 55 priority level" "0,1,2,3"
|
|
rgroup.long (0x90DC+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[55],TCU Node 55 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x90E0++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[56],TCU Node 56 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 56 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 56 priority level" "0,1,2,3"
|
|
rgroup.long (0x90E0+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[56],TCU Node 56 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x90E4++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[57],TCU Node 57 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 57 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 57 priority level" "0,1,2,3"
|
|
rgroup.long (0x90E4+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[57],TCU Node 57 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x90E8++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[58],TCU Node 58 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 58 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 58 priority level" "0,1,2,3"
|
|
rgroup.long (0x90E8+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[58],TCU Node 58 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x90EC++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[59],TCU Node 59 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 59 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 59 priority level" "0,1,2,3"
|
|
rgroup.long (0x90EC+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[59],TCU Node 59 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x90F0++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[60],TCU Node 60 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 60 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 60 priority level" "0,1,2,3"
|
|
rgroup.long (0x90F0+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[60],TCU Node 60 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x90F4++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[61],TCU Node 61 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 61 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 61 priority level" "0,1,2,3"
|
|
rgroup.long (0x90F4+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[61],TCU Node 61 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x90F8++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[62],TCU Node 62 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 62 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 62 priority level" "0,1,2,3"
|
|
rgroup.long (0x90F8+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[62],TCU Node 62 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x90FC++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[63],TCU Node 63 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 63 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 63 priority level" "0,1,2,3"
|
|
rgroup.long (0x90FC+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[63],TCU Node 63 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9100++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[64],TCU Node 64 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 64 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 64 priority level" "0,1,2,3"
|
|
rgroup.long (0x9100+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[64],TCU Node 64 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9104++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[65],TCU Node 65 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 65 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 65 priority level" "0,1,2,3"
|
|
rgroup.long (0x9104+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[65],TCU Node 65 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9108++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[66],TCU Node 66 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 66 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 66 priority level" "0,1,2,3"
|
|
rgroup.long (0x9108+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[66],TCU Node 66 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x910C++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[67],TCU Node 67 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 67 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 67 priority level" "0,1,2,3"
|
|
rgroup.long (0x910C+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[67],TCU Node 67 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9110++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[68],TCU Node 68 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 68 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 68 priority level" "0,1,2,3"
|
|
rgroup.long (0x9110+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[68],TCU Node 68 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9114++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[69],TCU Node 69 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 69 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 69 priority level" "0,1,2,3"
|
|
rgroup.long (0x9114+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[69],TCU Node 69 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9118++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[70],TCU Node 70 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 70 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 70 priority level" "0,1,2,3"
|
|
rgroup.long (0x9118+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[70],TCU Node 70 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x911C++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[71],TCU Node 71 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 71 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 71 priority level" "0,1,2,3"
|
|
rgroup.long (0x911C+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[71],TCU Node 71 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9120++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[72],TCU Node 72 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 72 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 72 priority level" "0,1,2,3"
|
|
rgroup.long (0x9120+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[72],TCU Node 72 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9124++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[73],TCU Node 73 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 73 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 73 priority level" "0,1,2,3"
|
|
rgroup.long (0x9124+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[73],TCU Node 73 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9128++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[74],TCU Node 74 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 74 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 74 priority level" "0,1,2,3"
|
|
rgroup.long (0x9128+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[74],TCU Node 74 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x912C++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[75],TCU Node 75 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 75 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 75 priority level" "0,1,2,3"
|
|
rgroup.long (0x912C+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[75],TCU Node 75 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9130++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[76],TCU Node 76 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 76 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 76 priority level" "0,1,2,3"
|
|
rgroup.long (0x9130+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[76],TCU Node 76 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9134++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[77],TCU Node 77 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 77 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 77 priority level" "0,1,2,3"
|
|
rgroup.long (0x9134+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[77],TCU Node 77 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9138++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[78],TCU Node 78 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 78 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 78 priority level" "0,1,2,3"
|
|
rgroup.long (0x9138+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[78],TCU Node 78 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x913C++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[79],TCU Node 79 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 79 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 79 priority level" "0,1,2,3"
|
|
rgroup.long (0x913C+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[79],TCU Node 79 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9140++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[80],TCU Node 80 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 80 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 80 priority level" "0,1,2,3"
|
|
rgroup.long (0x9140+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[80],TCU Node 80 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9144++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[81],TCU Node 81 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 81 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 81 priority level" "0,1,2,3"
|
|
rgroup.long (0x9144+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[81],TCU Node 81 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9148++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[82],TCU Node 82 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 82 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 82 priority level" "0,1,2,3"
|
|
rgroup.long (0x9148+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[82],TCU Node 82 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x914C++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[83],TCU Node 83 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 83 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 83 priority level" "0,1,2,3"
|
|
rgroup.long (0x914C+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[83],TCU Node 83 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9150++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[84],TCU Node 84 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 84 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 84 priority level" "0,1,2,3"
|
|
rgroup.long (0x9150+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[84],TCU Node 84 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9154++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[85],TCU Node 85 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 85 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 85 priority level" "0,1,2,3"
|
|
rgroup.long (0x9154+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[85],TCU Node 85 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9158++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[86],TCU Node 86 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 86 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 86 priority level" "0,1,2,3"
|
|
rgroup.long (0x9158+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[86],TCU Node 86 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x915C++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[87],TCU Node 87 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 87 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 87 priority level" "0,1,2,3"
|
|
rgroup.long (0x915C+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[87],TCU Node 87 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9160++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[88],TCU Node 88 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 88 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 88 priority level" "0,1,2,3"
|
|
rgroup.long (0x9160+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[88],TCU Node 88 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9164++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[89],TCU Node 89 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 89 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 89 priority level" "0,1,2,3"
|
|
rgroup.long (0x9164+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[89],TCU Node 89 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9168++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[90],TCU Node 90 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 90 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 90 priority level" "0,1,2,3"
|
|
rgroup.long (0x9168+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[90],TCU Node 90 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x916C++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[91],TCU Node 91 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 91 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 91 priority level" "0,1,2,3"
|
|
rgroup.long (0x916C+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[91],TCU Node 91 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9170++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[92],TCU Node 92 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 92 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 92 priority level" "0,1,2,3"
|
|
rgroup.long (0x9170+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[92],TCU Node 92 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9174++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[93],TCU Node 93 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 93 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 93 priority level" "0,1,2,3"
|
|
rgroup.long (0x9174+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[93],TCU Node 93 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9178++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[94],TCU Node 94 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 94 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 94 priority level" "0,1,2,3"
|
|
rgroup.long (0x9178+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[94],TCU Node 94 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x917C++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[95],TCU Node 95 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 95 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 95 priority level" "0,1,2,3"
|
|
rgroup.long (0x917C+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[95],TCU Node 95 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9180++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[96],TCU Node 96 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 96 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 96 priority level" "0,1,2,3"
|
|
rgroup.long (0x9180+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[96],TCU Node 96 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9184++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[97],TCU Node 97 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 97 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 97 priority level" "0,1,2,3"
|
|
rgroup.long (0x9184+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[97],TCU Node 97 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9188++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[98],TCU Node 98 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 98 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 98 priority level" "0,1,2,3"
|
|
rgroup.long (0x9188+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[98],TCU Node 98 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x918C++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[99],TCU Node 99 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 99 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 99 priority level" "0,1,2,3"
|
|
rgroup.long (0x918C+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[99],TCU Node 99 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9190++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[100],TCU Node 100 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 100 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 100 priority level" "0,1,2,3"
|
|
rgroup.long (0x9190+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[100],TCU Node 100 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9194++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[101],TCU Node 101 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 101 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 101 priority level" "0,1,2,3"
|
|
rgroup.long (0x9194+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[101],TCU Node 101 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9198++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[102],TCU Node 102 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 102 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 102 priority level" "0,1,2,3"
|
|
rgroup.long (0x9198+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[102],TCU Node 102 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x919C++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[103],TCU Node 103 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 103 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 103 priority level" "0,1,2,3"
|
|
rgroup.long (0x919C+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[103],TCU Node 103 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x91A0++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[104],TCU Node 104 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 104 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 104 priority level" "0,1,2,3"
|
|
rgroup.long (0x91A0+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[104],TCU Node 104 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x91A4++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[105],TCU Node 105 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 105 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 105 priority level" "0,1,2,3"
|
|
rgroup.long (0x91A4+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[105],TCU Node 105 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x91A8++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[106],TCU Node 106 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 106 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 106 priority level" "0,1,2,3"
|
|
rgroup.long (0x91A8+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[106],TCU Node 106 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x91AC++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[107],TCU Node 107 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 107 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 107 priority level" "0,1,2,3"
|
|
rgroup.long (0x91AC+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[107],TCU Node 107 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x91B0++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[108],TCU Node 108 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 108 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 108 priority level" "0,1,2,3"
|
|
rgroup.long (0x91B0+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[108],TCU Node 108 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x91B4++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[109],TCU Node 109 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 109 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 109 priority level" "0,1,2,3"
|
|
rgroup.long (0x91B4+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[109],TCU Node 109 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x91B8++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[110],TCU Node 110 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 110 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 110 priority level" "0,1,2,3"
|
|
rgroup.long (0x91B8+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[110],TCU Node 110 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x91BC++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[111],TCU Node 111 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 111 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 111 priority level" "0,1,2,3"
|
|
rgroup.long (0x91BC+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[111],TCU Node 111 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x91C0++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[112],TCU Node 112 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 112 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 112 priority level" "0,1,2,3"
|
|
rgroup.long (0x91C0+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[112],TCU Node 112 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x91C4++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[113],TCU Node 113 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 113 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 113 priority level" "0,1,2,3"
|
|
rgroup.long (0x91C4+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[113],TCU Node 113 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x91C8++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[114],TCU Node 114 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 114 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 114 priority level" "0,1,2,3"
|
|
rgroup.long (0x91C8+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[114],TCU Node 114 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x91CC++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[115],TCU Node 115 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 115 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 115 priority level" "0,1,2,3"
|
|
rgroup.long (0x91CC+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[115],TCU Node 115 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x91D0++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[116],TCU Node 116 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 116 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 116 priority level" "0,1,2,3"
|
|
rgroup.long (0x91D0+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[116],TCU Node 116 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x91D4++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[117],TCU Node 117 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 117 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 117 priority level" "0,1,2,3"
|
|
rgroup.long (0x91D4+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[117],TCU Node 117 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x91D8++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[118],TCU Node 118 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 118 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 118 priority level" "0,1,2,3"
|
|
rgroup.long (0x91D8+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[118],TCU Node 118 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x91DC++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[119],TCU Node 119 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 119 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 119 priority level" "0,1,2,3"
|
|
rgroup.long (0x91DC+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[119],TCU Node 119 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x91E0++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[120],TCU Node 120 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 120 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 120 priority level" "0,1,2,3"
|
|
rgroup.long (0x91E0+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[120],TCU Node 120 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x91E4++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[121],TCU Node 121 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 121 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 121 priority level" "0,1,2,3"
|
|
rgroup.long (0x91E4+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[121],TCU Node 121 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x91E8++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[122],TCU Node 122 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 122 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 122 priority level" "0,1,2,3"
|
|
rgroup.long (0x91E8+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[122],TCU Node 122 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x91EC++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[123],TCU Node 123 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 123 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 123 priority level" "0,1,2,3"
|
|
rgroup.long (0x91EC+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[123],TCU Node 123 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x91F0++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[124],TCU Node 124 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 124 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 124 priority level" "0,1,2,3"
|
|
rgroup.long (0x91F0+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[124],TCU Node 124 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x91F4++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[125],TCU Node 125 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 125 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 125 priority level" "0,1,2,3"
|
|
rgroup.long (0x91F4+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[125],TCU Node 125 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x91F8++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[126],TCU Node 126 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 126 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 126 priority level" "0,1,2,3"
|
|
rgroup.long (0x91F8+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[126],TCU Node 126 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x91FC++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[127],TCU Node 127 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 127 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 127 priority level" "0,1,2,3"
|
|
rgroup.long (0x91FC+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[127],TCU Node 127 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9200++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[128],TCU Node 128 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 128 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 128 priority level" "0,1,2,3"
|
|
rgroup.long (0x9200+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[128],TCU Node 128 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9204++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[129],TCU Node 129 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 129 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 129 priority level" "0,1,2,3"
|
|
rgroup.long (0x9204+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[129],TCU Node 129 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9208++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[130],TCU Node 130 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 130 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 130 priority level" "0,1,2,3"
|
|
rgroup.long (0x9208+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[130],TCU Node 130 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x920C++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[131],TCU Node 131 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 131 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 131 priority level" "0,1,2,3"
|
|
rgroup.long (0x920C+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[131],TCU Node 131 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9210++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[132],TCU Node 132 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 132 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 132 priority level" "0,1,2,3"
|
|
rgroup.long (0x9210+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[132],TCU Node 132 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9214++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[133],TCU Node 133 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 133 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 133 priority level" "0,1,2,3"
|
|
rgroup.long (0x9214+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[133],TCU Node 133 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9218++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[134],TCU Node 134 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 134 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 134 priority level" "0,1,2,3"
|
|
rgroup.long (0x9218+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[134],TCU Node 134 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x921C++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[135],TCU Node 135 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 135 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 135 priority level" "0,1,2,3"
|
|
rgroup.long (0x921C+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[135],TCU Node 135 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9220++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[136],TCU Node 136 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 136 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 136 priority level" "0,1,2,3"
|
|
rgroup.long (0x9220+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[136],TCU Node 136 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9224++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[137],TCU Node 137 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 137 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 137 priority level" "0,1,2,3"
|
|
rgroup.long (0x9224+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[137],TCU Node 137 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9228++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[138],TCU Node 138 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 138 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 138 priority level" "0,1,2,3"
|
|
rgroup.long (0x9228+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[138],TCU Node 138 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x922C++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[139],TCU Node 139 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 139 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 139 priority level" "0,1,2,3"
|
|
rgroup.long (0x922C+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[139],TCU Node 139 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9230++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[140],TCU Node 140 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 140 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 140 priority level" "0,1,2,3"
|
|
rgroup.long (0x9230+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[140],TCU Node 140 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9234++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[141],TCU Node 141 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 141 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 141 priority level" "0,1,2,3"
|
|
rgroup.long (0x9234+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[141],TCU Node 141 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9238++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[142],TCU Node 142 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 142 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 142 priority level" "0,1,2,3"
|
|
rgroup.long (0x9238+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[142],TCU Node 142 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x923C++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[143],TCU Node 143 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 143 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 143 priority level" "0,1,2,3"
|
|
rgroup.long (0x923C+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[143],TCU Node 143 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9240++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[144],TCU Node 144 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 144 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 144 priority level" "0,1,2,3"
|
|
rgroup.long (0x9240+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[144],TCU Node 144 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9244++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[145],TCU Node 145 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 145 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 145 priority level" "0,1,2,3"
|
|
rgroup.long (0x9244+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[145],TCU Node 145 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9248++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[146],TCU Node 146 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 146 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 146 priority level" "0,1,2,3"
|
|
rgroup.long (0x9248+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[146],TCU Node 146 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x924C++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[147],TCU Node 147 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 147 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 147 priority level" "0,1,2,3"
|
|
rgroup.long (0x924C+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[147],TCU Node 147 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9250++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[148],TCU Node 148 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 148 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 148 priority level" "0,1,2,3"
|
|
rgroup.long (0x9250+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[148],TCU Node 148 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9254++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[149],TCU Node 149 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 149 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 149 priority level" "0,1,2,3"
|
|
rgroup.long (0x9254+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[149],TCU Node 149 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9258++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[150],TCU Node 150 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 150 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 150 priority level" "0,1,2,3"
|
|
rgroup.long (0x9258+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[150],TCU Node 150 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x925C++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[151],TCU Node 151 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 151 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 151 priority level" "0,1,2,3"
|
|
rgroup.long (0x925C+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[151],TCU Node 151 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9260++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[152],TCU Node 152 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 152 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 152 priority level" "0,1,2,3"
|
|
rgroup.long (0x9260+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[152],TCU Node 152 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9264++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[153],TCU Node 153 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 153 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 153 priority level" "0,1,2,3"
|
|
rgroup.long (0x9264+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[153],TCU Node 153 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9268++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[154],TCU Node 154 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 154 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 154 priority level" "0,1,2,3"
|
|
rgroup.long (0x9268+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[154],TCU Node 154 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x926C++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[155],TCU Node 155 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 155 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 155 priority level" "0,1,2,3"
|
|
rgroup.long (0x926C+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[155],TCU Node 155 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9270++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[156],TCU Node 156 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 156 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 156 priority level" "0,1,2,3"
|
|
rgroup.long (0x9270+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[156],TCU Node 156 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9274++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[157],TCU Node 157 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 157 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 157 priority level" "0,1,2,3"
|
|
rgroup.long (0x9274+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[157],TCU Node 157 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9278++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[158],TCU Node 158 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 158 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 158 priority level" "0,1,2,3"
|
|
rgroup.long (0x9278+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[158],TCU Node 158 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x927C++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[159],TCU Node 159 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 159 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 159 priority level" "0,1,2,3"
|
|
rgroup.long (0x927C+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[159],TCU Node 159 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9280++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[160],TCU Node 160 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 160 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 160 priority level" "0,1,2,3"
|
|
rgroup.long (0x9280+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[160],TCU Node 160 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9284++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[161],TCU Node 161 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 161 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 161 priority level" "0,1,2,3"
|
|
rgroup.long (0x9284+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[161],TCU Node 161 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9288++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[162],TCU Node 162 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 162 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 162 priority level" "0,1,2,3"
|
|
rgroup.long (0x9288+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[162],TCU Node 162 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x928C++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[163],TCU Node 163 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 163 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 163 priority level" "0,1,2,3"
|
|
rgroup.long (0x928C+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[163],TCU Node 163 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9290++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[164],TCU Node 164 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 164 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 164 priority level" "0,1,2,3"
|
|
rgroup.long (0x9290+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[164],TCU Node 164 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9294++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[165],TCU Node 165 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 165 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 165 priority level" "0,1,2,3"
|
|
rgroup.long (0x9294+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[165],TCU Node 165 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9298++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[166],TCU Node 166 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 166 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 166 priority level" "0,1,2,3"
|
|
rgroup.long (0x9298+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[166],TCU Node 166 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x929C++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[167],TCU Node 167 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 167 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 167 priority level" "0,1,2,3"
|
|
rgroup.long (0x929C+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[167],TCU Node 167 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x92A0++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[168],TCU Node 168 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 168 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 168 priority level" "0,1,2,3"
|
|
rgroup.long (0x92A0+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[168],TCU Node 168 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x92A4++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[169],TCU Node 169 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 169 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 169 priority level" "0,1,2,3"
|
|
rgroup.long (0x92A4+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[169],TCU Node 169 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x92A8++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[170],TCU Node 170 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 170 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 170 priority level" "0,1,2,3"
|
|
rgroup.long (0x92A8+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[170],TCU Node 170 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x92AC++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[171],TCU Node 171 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 171 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 171 priority level" "0,1,2,3"
|
|
rgroup.long (0x92AC+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[171],TCU Node 171 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x92B0++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[172],TCU Node 172 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 172 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 172 priority level" "0,1,2,3"
|
|
rgroup.long (0x92B0+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[172],TCU Node 172 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x92B4++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[173],TCU Node 173 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 173 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 173 priority level" "0,1,2,3"
|
|
rgroup.long (0x92B4+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[173],TCU Node 173 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x92B8++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[174],TCU Node 174 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 174 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 174 priority level" "0,1,2,3"
|
|
rgroup.long (0x92B8+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[174],TCU Node 174 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x92BC++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[175],TCU Node 175 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 175 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 175 priority level" "0,1,2,3"
|
|
rgroup.long (0x92BC+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[175],TCU Node 175 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x92C0++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[176],TCU Node 176 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 176 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 176 priority level" "0,1,2,3"
|
|
rgroup.long (0x92C0+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[176],TCU Node 176 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x92C4++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[177],TCU Node 177 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 177 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 177 priority level" "0,1,2,3"
|
|
rgroup.long (0x92C4+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[177],TCU Node 177 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x92C8++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[178],TCU Node 178 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 178 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 178 priority level" "0,1,2,3"
|
|
rgroup.long (0x92C8+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[178],TCU Node 178 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x92CC++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[179],TCU Node 179 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 179 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 179 priority level" "0,1,2,3"
|
|
rgroup.long (0x92CC+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[179],TCU Node 179 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x92D0++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[180],TCU Node 180 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 180 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 180 priority level" "0,1,2,3"
|
|
rgroup.long (0x92D0+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[180],TCU Node 180 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x92D4++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[181],TCU Node 181 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 181 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 181 priority level" "0,1,2,3"
|
|
rgroup.long (0x92D4+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[181],TCU Node 181 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x92D8++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[182],TCU Node 182 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 182 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 182 priority level" "0,1,2,3"
|
|
rgroup.long (0x92D8+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[182],TCU Node 182 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x92DC++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[183],TCU Node 183 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 183 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 183 priority level" "0,1,2,3"
|
|
rgroup.long (0x92DC+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[183],TCU Node 183 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x92E0++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[184],TCU Node 184 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 184 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 184 priority level" "0,1,2,3"
|
|
rgroup.long (0x92E0+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[184],TCU Node 184 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x92E4++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[185],TCU Node 185 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 185 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 185 priority level" "0,1,2,3"
|
|
rgroup.long (0x92E4+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[185],TCU Node 185 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x92E8++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[186],TCU Node 186 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 186 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 186 priority level" "0,1,2,3"
|
|
rgroup.long (0x92E8+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[186],TCU Node 186 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x92EC++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[187],TCU Node 187 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 187 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 187 priority level" "0,1,2,3"
|
|
rgroup.long (0x92EC+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[187],TCU Node 187 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x92F0++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[188],TCU Node 188 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 188 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 188 priority level" "0,1,2,3"
|
|
rgroup.long (0x92F0+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[188],TCU Node 188 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x92F4++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[189],TCU Node 189 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 189 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 189 priority level" "0,1,2,3"
|
|
rgroup.long (0x92F4+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[189],TCU Node 189 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x92F8++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[190],TCU Node 190 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 190 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 190 priority level" "0,1,2,3"
|
|
rgroup.long (0x92F8+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[190],TCU Node 190 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x92FC++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[191],TCU Node 191 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 191 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 191 priority level" "0,1,2,3"
|
|
rgroup.long (0x92FC+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[191],TCU Node 191 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9300++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[192],TCU Node 192 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 192 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 192 priority level" "0,1,2,3"
|
|
rgroup.long (0x9300+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[192],TCU Node 192 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9304++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[193],TCU Node 193 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 193 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 193 priority level" "0,1,2,3"
|
|
rgroup.long (0x9304+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[193],TCU Node 193 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9308++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[194],TCU Node 194 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 194 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 194 priority level" "0,1,2,3"
|
|
rgroup.long (0x9308+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[194],TCU Node 194 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x930C++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[195],TCU Node 195 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 195 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 195 priority level" "0,1,2,3"
|
|
rgroup.long (0x930C+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[195],TCU Node 195 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9310++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[196],TCU Node 196 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 196 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 196 priority level" "0,1,2,3"
|
|
rgroup.long (0x9310+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[196],TCU Node 196 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9314++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[197],TCU Node 197 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 197 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 197 priority level" "0,1,2,3"
|
|
rgroup.long (0x9314+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[197],TCU Node 197 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9318++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[198],TCU Node 198 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 198 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 198 priority level" "0,1,2,3"
|
|
rgroup.long (0x9318+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[198],TCU Node 198 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x931C++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[199],TCU Node 199 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 199 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 199 priority level" "0,1,2,3"
|
|
rgroup.long (0x931C+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[199],TCU Node 199 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9320++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[200],TCU Node 200 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 200 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 200 priority level" "0,1,2,3"
|
|
rgroup.long (0x9320+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[200],TCU Node 200 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9324++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[201],TCU Node 201 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 201 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 201 priority level" "0,1,2,3"
|
|
rgroup.long (0x9324+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[201],TCU Node 201 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9328++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[202],TCU Node 202 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 202 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 202 priority level" "0,1,2,3"
|
|
rgroup.long (0x9328+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[202],TCU Node 202 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x932C++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[203],TCU Node 203 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 203 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 203 priority level" "0,1,2,3"
|
|
rgroup.long (0x932C+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[203],TCU Node 203 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9330++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[204],TCU Node 204 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 204 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 204 priority level" "0,1,2,3"
|
|
rgroup.long (0x9330+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[204],TCU Node 204 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9334++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[205],TCU Node 205 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 205 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 205 priority level" "0,1,2,3"
|
|
rgroup.long (0x9334+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[205],TCU Node 205 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9338++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[206],TCU Node 206 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 206 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 206 priority level" "0,1,2,3"
|
|
rgroup.long (0x9338+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[206],TCU Node 206 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x933C++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[207],TCU Node 207 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 207 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 207 priority level" "0,1,2,3"
|
|
rgroup.long (0x933C+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[207],TCU Node 207 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9340++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[208],TCU Node 208 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 208 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 208 priority level" "0,1,2,3"
|
|
rgroup.long (0x9340+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[208],TCU Node 208 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9344++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[209],TCU Node 209 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 209 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 209 priority level" "0,1,2,3"
|
|
rgroup.long (0x9344+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[209],TCU Node 209 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9348++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[210],TCU Node 210 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 210 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 210 priority level" "0,1,2,3"
|
|
rgroup.long (0x9348+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[210],TCU Node 210 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x934C++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[211],TCU Node 211 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 211 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 211 priority level" "0,1,2,3"
|
|
rgroup.long (0x934C+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[211],TCU Node 211 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9350++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[212],TCU Node 212 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 212 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 212 priority level" "0,1,2,3"
|
|
rgroup.long (0x9350+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[212],TCU Node 212 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9354++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[213],TCU Node 213 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 213 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 213 priority level" "0,1,2,3"
|
|
rgroup.long (0x9354+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[213],TCU Node 213 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9358++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[214],TCU Node 214 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 214 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 214 priority level" "0,1,2,3"
|
|
rgroup.long (0x9358+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[214],TCU Node 214 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x935C++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[215],TCU Node 215 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 215 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 215 priority level" "0,1,2,3"
|
|
rgroup.long (0x935C+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[215],TCU Node 215 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9360++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[216],TCU Node 216 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 216 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 216 priority level" "0,1,2,3"
|
|
rgroup.long (0x9360+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[216],TCU Node 216 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9364++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[217],TCU Node 217 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 217 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 217 priority level" "0,1,2,3"
|
|
rgroup.long (0x9364+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[217],TCU Node 217 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9368++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[218],TCU Node 218 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 218 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 218 priority level" "0,1,2,3"
|
|
rgroup.long (0x9368+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[218],TCU Node 218 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x936C++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[219],TCU Node 219 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 219 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 219 priority level" "0,1,2,3"
|
|
rgroup.long (0x936C+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[219],TCU Node 219 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9370++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[220],TCU Node 220 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 220 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 220 priority level" "0,1,2,3"
|
|
rgroup.long (0x9370+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[220],TCU Node 220 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9374++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[221],TCU Node 221 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 221 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 221 priority level" "0,1,2,3"
|
|
rgroup.long (0x9374+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[221],TCU Node 221 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9378++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[222],TCU Node 222 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 222 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 222 priority level" "0,1,2,3"
|
|
rgroup.long (0x9378+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[222],TCU Node 222 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x937C++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[223],TCU Node 223 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 223 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 223 priority level" "0,1,2,3"
|
|
rgroup.long (0x937C+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[223],TCU Node 223 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9380++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[224],TCU Node 224 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 224 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 224 priority level" "0,1,2,3"
|
|
rgroup.long (0x9380+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[224],TCU Node 224 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9384++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[225],TCU Node 225 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 225 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 225 priority level" "0,1,2,3"
|
|
rgroup.long (0x9384+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[225],TCU Node 225 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9388++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[226],TCU Node 226 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 226 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 226 priority level" "0,1,2,3"
|
|
rgroup.long (0x9388+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[226],TCU Node 226 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x938C++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[227],TCU Node 227 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 227 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 227 priority level" "0,1,2,3"
|
|
rgroup.long (0x938C+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[227],TCU Node 227 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9390++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[228],TCU Node 228 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 228 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 228 priority level" "0,1,2,3"
|
|
rgroup.long (0x9390+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[228],TCU Node 228 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9394++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[229],TCU Node 229 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 229 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 229 priority level" "0,1,2,3"
|
|
rgroup.long (0x9394+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[229],TCU Node 229 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x9398++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[230],TCU Node 230 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 230 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 230 priority level" "0,1,2,3"
|
|
rgroup.long (0x9398+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[230],TCU Node 230 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x939C++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[231],TCU Node 231 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 231 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 231 priority level" "0,1,2,3"
|
|
rgroup.long (0x939C+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[231],TCU Node 231 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x93A0++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[232],TCU Node 232 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 232 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 232 priority level" "0,1,2,3"
|
|
rgroup.long (0x93A0+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[232],TCU Node 232 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x93A4++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[233],TCU Node 233 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 233 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 233 priority level" "0,1,2,3"
|
|
rgroup.long (0x93A4+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[233],TCU Node 233 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x93A8++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[234],TCU Node 234 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 234 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 234 priority level" "0,1,2,3"
|
|
rgroup.long (0x93A8+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[234],TCU Node 234 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x93AC++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[235],TCU Node 235 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 235 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 235 priority level" "0,1,2,3"
|
|
rgroup.long (0x93AC+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[235],TCU Node 235 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x93B0++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[236],TCU Node 236 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 236 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 236 priority level" "0,1,2,3"
|
|
rgroup.long (0x93B0+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[236],TCU Node 236 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x93B4++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[237],TCU Node 237 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 237 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 237 priority level" "0,1,2,3"
|
|
rgroup.long (0x93B4+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[237],TCU Node 237 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x93B8++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[238],TCU Node 238 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 238 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 238 priority level" "0,1,2,3"
|
|
rgroup.long (0x93B8+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[238],TCU Node 238 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x93BC++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[239],TCU Node 239 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 239 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 239 priority level" "0,1,2,3"
|
|
rgroup.long (0x93BC+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[239],TCU Node 239 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x93C0++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[240],TCU Node 240 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 240 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 240 priority level" "0,1,2,3"
|
|
rgroup.long (0x93C0+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[240],TCU Node 240 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x93C4++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[241],TCU Node 241 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 241 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 241 priority level" "0,1,2,3"
|
|
rgroup.long (0x93C4+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[241],TCU Node 241 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x93C8++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[242],TCU Node 242 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 242 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 242 priority level" "0,1,2,3"
|
|
rgroup.long (0x93C8+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[242],TCU Node 242 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x93CC++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[243],TCU Node 243 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 243 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 243 priority level" "0,1,2,3"
|
|
rgroup.long (0x93CC+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[243],TCU Node 243 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x93D0++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[244],TCU Node 244 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 244 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 244 priority level" "0,1,2,3"
|
|
rgroup.long (0x93D0+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[244],TCU Node 244 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x93D4++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[245],TCU Node 245 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 245 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 245 priority level" "0,1,2,3"
|
|
rgroup.long (0x93D4+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[245],TCU Node 245 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x93D8++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[246],TCU Node 246 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 246 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 246 priority level" "0,1,2,3"
|
|
rgroup.long (0x93D8+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[246],TCU Node 246 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x93DC++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[247],TCU Node 247 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 247 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 247 priority level" "0,1,2,3"
|
|
rgroup.long (0x93DC+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[247],TCU Node 247 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x93E0++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[248],TCU Node 248 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 248 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 248 priority level" "0,1,2,3"
|
|
rgroup.long (0x93E0+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[248],TCU Node 248 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x93E4++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[249],TCU Node 249 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 249 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 249 priority level" "0,1,2,3"
|
|
rgroup.long (0x93E4+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[249],TCU Node 249 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x93E8++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[250],TCU Node 250 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 250 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 250 priority level" "0,1,2,3"
|
|
rgroup.long (0x93E8+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[250],TCU Node 250 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x93EC++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[251],TCU Node 251 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 251 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 251 priority level" "0,1,2,3"
|
|
rgroup.long (0x93EC+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[251],TCU Node 251 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x93F0++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[252],TCU Node 252 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 252 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 252 priority level" "0,1,2,3"
|
|
rgroup.long (0x93F0+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[252],TCU Node 252 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x93F4++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[253],TCU Node 253 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 253 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 253 priority level" "0,1,2,3"
|
|
rgroup.long (0x93F4+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[253],TCU Node 253 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x93F8++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[254],TCU Node 254 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 254 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 254 priority level" "0,1,2,3"
|
|
rgroup.long (0x93F8+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[254],TCU Node 254 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
group.long 0x93FC++0x03
|
|
line.long 0x00 "TCU_NODE_CTRL[255],TCU Node 255 Control Register"
|
|
bitfld.long 0x00 4. "DIS_DVM,Node 255 DVM invalidation disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. "PRI_LEVEL,Node 255 priority level" "0,1,2,3"
|
|
rgroup.long (0x93FC+0x400)++0x03
|
|
line.long 0x00 "TCU_NODE_STATUS[255],TCU Node 255 Status Register"
|
|
bitfld.long 0x00 1. "ATS,ATS implemented" "DTI-TBU protocol,DTI_ATS protocol"
|
|
bitfld.long 0x00 0. "CONNECTED,DTI link is connected" "Not connected,Connected"
|
|
newline
|
|
tree.end
|
|
tree.end
|
|
tree "TCU RAS Registers"
|
|
rgroup.long 0x8E80++0x03
|
|
line.long 0x00 "TCU_ERRFR,TCU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long 0x8E88++0x03
|
|
line.long 0x00 "TCU_ERRCTLR,TCU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long 0x8E90++0x03
|
|
line.long 0x00 "TCU_ERRSTATUS,TCU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 8.--15. 1. "IERR,Indicates the source of the error"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad 0x8EC0++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 3. "TCC,Force configuration cache tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 2. "DCC,Force configuration cache data parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 1. "TWC,Force walk cache tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DWC,Force walk cache data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree.end
|
|
tree "Translation Buffer Unit (TBU) Registers"
|
|
tree "TBU0"
|
|
rgroup.long (0x40000+0xFE0)++0x0F "TBU0 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x40000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x40000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x40000+0x2FB8)++0x03 "TBU0 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x40000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x40000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x40000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU0 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x40000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x40000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x40000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x40000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x40000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x40000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x40000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x40000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x40000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x40000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x40000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x40000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x40000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x40000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x40000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x40000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x40000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x40000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x40000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x40000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x40000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x40000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x40000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x40000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x40000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x40000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x40000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x40000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x40000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x40000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x40000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x40000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x40000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x40000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x40000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x40000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x40000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x40000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x40000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x40000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x40000+0x8E00)++0x03 "TBU0 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x40000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x40000+0x8E80)++0x03 "TBU0 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x40000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x40000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x40000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU1"
|
|
rgroup.long (0x60000+0xFE0)++0x0F "TBU1 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x60000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x60000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x60000+0x2FB8)++0x03 "TBU1 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x60000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x60000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x60000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU1 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x60000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x60000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x60000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x60000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x60000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x60000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x60000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x60000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x60000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x60000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x60000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x60000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x60000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x60000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x60000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x60000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x60000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x60000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x60000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x60000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x60000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x60000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x60000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x60000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x60000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x60000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x60000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x60000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x60000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x60000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x60000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x60000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x60000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x60000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x60000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x60000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x60000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x60000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x60000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x60000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x60000+0x8E00)++0x03 "TBU1 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x60000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x60000+0x8E80)++0x03 "TBU1 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x60000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x60000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x60000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU2"
|
|
rgroup.long (0x80000+0xFE0)++0x0F "TBU2 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x80000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x80000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x80000+0x2FB8)++0x03 "TBU2 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x80000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x80000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x80000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU2 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x80000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x80000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x80000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x80000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x80000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x80000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x80000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x80000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x80000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x80000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x80000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x80000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x80000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x80000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x80000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x80000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x80000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x80000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x80000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x80000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x80000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x80000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x80000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x80000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x80000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x80000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x80000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x80000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x80000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x80000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x80000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x80000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x80000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x80000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x80000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x80000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x80000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x80000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x80000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x80000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x80000+0x8E00)++0x03 "TBU2 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x80000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x80000+0x8E80)++0x03 "TBU2 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x80000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x80000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x80000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU3"
|
|
rgroup.long (0xA0000+0xFE0)++0x0F "TBU3 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0xA0000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0xA0000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0xA0000+0x2FB8)++0x03 "TBU3 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0xA0000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0xA0000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0xA0000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU3 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0xA0000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0xA0000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0xA0000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0xA0000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0xA0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0xA0000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0xA0000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0xA0000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0xA0000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0xA0000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0xA0000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0xA0000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0xA0000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0xA0000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0xA0000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0xA0000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0xA0000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0xA0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0xA0000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0xA0000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0xA0000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0xA0000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0xA0000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0xA0000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0xA0000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0xA0000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0xA0000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0xA0000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0xA0000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0xA0000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0xA0000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0xA0000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0xA0000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0xA0000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0xA0000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0xA0000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0xA0000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0xA0000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0xA0000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0xA0000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0xA0000+0x8E00)++0x03 "TBU3 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0xA0000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0xA0000+0x8E80)++0x03 "TBU3 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0xA0000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0xA0000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0xA0000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU4"
|
|
rgroup.long (0xC0000+0xFE0)++0x0F "TBU4 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0xC0000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0xC0000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0xC0000+0x2FB8)++0x03 "TBU4 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0xC0000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0xC0000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0xC0000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU4 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0xC0000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0xC0000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0xC0000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0xC0000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0xC0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0xC0000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0xC0000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0xC0000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0xC0000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0xC0000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0xC0000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0xC0000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0xC0000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0xC0000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0xC0000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0xC0000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0xC0000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0xC0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0xC0000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0xC0000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0xC0000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0xC0000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0xC0000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0xC0000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0xC0000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0xC0000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0xC0000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0xC0000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0xC0000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0xC0000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0xC0000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0xC0000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0xC0000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0xC0000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0xC0000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0xC0000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0xC0000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0xC0000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0xC0000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0xC0000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0xC0000+0x8E00)++0x03 "TBU4 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0xC0000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0xC0000+0x8E80)++0x03 "TBU4 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0xC0000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0xC0000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0xC0000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU5"
|
|
rgroup.long (0xE0000+0xFE0)++0x0F "TBU5 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0xE0000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0xE0000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0xE0000+0x2FB8)++0x03 "TBU5 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0xE0000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0xE0000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0xE0000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU5 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0xE0000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0xE0000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0xE0000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0xE0000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0xE0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0xE0000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0xE0000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0xE0000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0xE0000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0xE0000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0xE0000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0xE0000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0xE0000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0xE0000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0xE0000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0xE0000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0xE0000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0xE0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0xE0000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0xE0000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0xE0000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0xE0000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0xE0000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0xE0000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0xE0000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0xE0000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0xE0000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0xE0000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0xE0000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0xE0000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0xE0000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0xE0000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0xE0000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0xE0000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0xE0000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0xE0000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0xE0000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0xE0000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0xE0000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0xE0000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0xE0000+0x8E00)++0x03 "TBU5 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0xE0000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0xE0000+0x8E80)++0x03 "TBU5 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0xE0000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0xE0000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0xE0000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU6"
|
|
rgroup.long (0x100000+0xFE0)++0x0F "TBU6 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x100000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x100000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x100000+0x2FB8)++0x03 "TBU6 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x100000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x100000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x100000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU6 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x100000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x100000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x100000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x100000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x100000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x100000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x100000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x100000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x100000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x100000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x100000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x100000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x100000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x100000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x100000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x100000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x100000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x100000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x100000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x100000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x100000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x100000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x100000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x100000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x100000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x100000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x100000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x100000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x100000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x100000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x100000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x100000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x100000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x100000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x100000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x100000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x100000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x100000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x100000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x100000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x100000+0x8E00)++0x03 "TBU6 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x100000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x100000+0x8E80)++0x03 "TBU6 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x100000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x100000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x100000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU7"
|
|
rgroup.long (0x120000+0xFE0)++0x0F "TBU7 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x120000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x120000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x120000+0x2FB8)++0x03 "TBU7 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x120000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x120000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x120000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU7 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x120000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x120000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x120000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x120000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x120000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x120000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x120000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x120000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x120000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x120000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x120000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x120000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x120000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x120000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x120000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x120000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x120000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x120000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x120000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x120000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x120000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x120000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x120000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x120000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x120000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x120000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x120000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x120000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x120000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x120000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x120000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x120000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x120000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x120000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x120000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x120000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x120000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x120000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x120000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x120000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x120000+0x8E00)++0x03 "TBU7 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x120000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x120000+0x8E80)++0x03 "TBU7 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x120000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x120000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x120000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU8"
|
|
rgroup.long (0x140000+0xFE0)++0x0F "TBU8 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x140000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x140000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x140000+0x2FB8)++0x03 "TBU8 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x140000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x140000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x140000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU8 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x140000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x140000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x140000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x140000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x140000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x140000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x140000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x140000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x140000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x140000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x140000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x140000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x140000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x140000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x140000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x140000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x140000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x140000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x140000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x140000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x140000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x140000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x140000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x140000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x140000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x140000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x140000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x140000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x140000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x140000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x140000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x140000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x140000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x140000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x140000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x140000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x140000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x140000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x140000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x140000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x140000+0x8E00)++0x03 "TBU8 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x140000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x140000+0x8E80)++0x03 "TBU8 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x140000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x140000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x140000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU9"
|
|
rgroup.long (0x160000+0xFE0)++0x0F "TBU9 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x160000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x160000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x160000+0x2FB8)++0x03 "TBU9 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x160000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x160000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x160000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU9 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x160000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x160000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x160000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x160000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x160000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x160000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x160000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x160000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x160000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x160000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x160000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x160000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x160000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x160000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x160000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x160000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x160000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x160000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x160000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x160000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x160000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x160000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x160000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x160000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x160000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x160000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x160000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x160000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x160000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x160000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x160000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x160000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x160000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x160000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x160000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x160000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x160000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x160000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x160000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x160000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x160000+0x8E00)++0x03 "TBU9 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x160000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x160000+0x8E80)++0x03 "TBU9 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x160000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x160000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x160000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU10"
|
|
rgroup.long (0x180000+0xFE0)++0x0F "TBU10 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x180000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x180000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x180000+0x2FB8)++0x03 "TBU10 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x180000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x180000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x180000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU10 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x180000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x180000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x180000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x180000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x180000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x180000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x180000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x180000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x180000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x180000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x180000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x180000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x180000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x180000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x180000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x180000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x180000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x180000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x180000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x180000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x180000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x180000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x180000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x180000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x180000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x180000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x180000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x180000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x180000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x180000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x180000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x180000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x180000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x180000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x180000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x180000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x180000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x180000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x180000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x180000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x180000+0x8E00)++0x03 "TBU10 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x180000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x180000+0x8E80)++0x03 "TBU10 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x180000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x180000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x180000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU11"
|
|
rgroup.long (0x1A0000+0xFE0)++0x0F "TBU11 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x1A0000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x1A0000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x1A0000+0x2FB8)++0x03 "TBU11 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x1A0000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x1A0000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x1A0000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU11 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x1A0000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x1A0000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x1A0000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x1A0000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x1A0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x1A0000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x1A0000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x1A0000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x1A0000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x1A0000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x1A0000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x1A0000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x1A0000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x1A0000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x1A0000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x1A0000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x1A0000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x1A0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x1A0000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x1A0000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x1A0000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x1A0000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x1A0000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x1A0000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x1A0000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x1A0000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x1A0000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x1A0000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x1A0000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x1A0000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x1A0000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x1A0000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x1A0000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x1A0000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x1A0000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x1A0000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x1A0000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x1A0000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x1A0000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x1A0000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x1A0000+0x8E00)++0x03 "TBU11 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x1A0000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x1A0000+0x8E80)++0x03 "TBU11 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x1A0000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x1A0000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x1A0000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU12"
|
|
rgroup.long (0x1C0000+0xFE0)++0x0F "TBU12 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x1C0000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x1C0000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x1C0000+0x2FB8)++0x03 "TBU12 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x1C0000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x1C0000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x1C0000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU12 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x1C0000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x1C0000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x1C0000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x1C0000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x1C0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x1C0000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x1C0000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x1C0000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x1C0000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x1C0000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x1C0000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x1C0000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x1C0000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x1C0000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x1C0000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x1C0000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x1C0000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x1C0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x1C0000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x1C0000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x1C0000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x1C0000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x1C0000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x1C0000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x1C0000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x1C0000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x1C0000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x1C0000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x1C0000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x1C0000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x1C0000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x1C0000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x1C0000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x1C0000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x1C0000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x1C0000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x1C0000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x1C0000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x1C0000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x1C0000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x1C0000+0x8E00)++0x03 "TBU12 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x1C0000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x1C0000+0x8E80)++0x03 "TBU12 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x1C0000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x1C0000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x1C0000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU13"
|
|
rgroup.long (0x1E0000+0xFE0)++0x0F "TBU13 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x1E0000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x1E0000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x1E0000+0x2FB8)++0x03 "TBU13 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x1E0000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x1E0000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x1E0000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU13 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x1E0000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x1E0000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x1E0000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x1E0000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x1E0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x1E0000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x1E0000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x1E0000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x1E0000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x1E0000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x1E0000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x1E0000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x1E0000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x1E0000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x1E0000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x1E0000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x1E0000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x1E0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x1E0000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x1E0000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x1E0000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x1E0000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x1E0000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x1E0000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x1E0000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x1E0000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x1E0000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x1E0000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x1E0000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x1E0000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x1E0000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x1E0000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x1E0000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x1E0000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x1E0000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x1E0000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x1E0000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x1E0000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x1E0000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x1E0000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x1E0000+0x8E00)++0x03 "TBU13 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x1E0000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x1E0000+0x8E80)++0x03 "TBU13 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x1E0000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x1E0000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x1E0000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU14"
|
|
rgroup.long (0x200000+0xFE0)++0x0F "TBU14 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x200000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x200000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x200000+0x2FB8)++0x03 "TBU14 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x200000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x200000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x200000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU14 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x200000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x200000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x200000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x200000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x200000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x200000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x200000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x200000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x200000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x200000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x200000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x200000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x200000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x200000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x200000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x200000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x200000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x200000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x200000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x200000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x200000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x200000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x200000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x200000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x200000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x200000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x200000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x200000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x200000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x200000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x200000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x200000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x200000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x200000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x200000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x200000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x200000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x200000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x200000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x200000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x200000+0x8E00)++0x03 "TBU14 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x200000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x200000+0x8E80)++0x03 "TBU14 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x200000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x200000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x200000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU15"
|
|
rgroup.long (0x220000+0xFE0)++0x0F "TBU15 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x220000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x220000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x220000+0x2FB8)++0x03 "TBU15 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x220000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x220000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x220000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU15 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x220000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x220000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x220000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x220000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x220000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x220000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x220000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x220000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x220000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x220000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x220000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x220000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x220000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x220000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x220000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x220000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x220000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x220000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x220000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x220000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x220000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x220000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x220000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x220000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x220000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x220000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x220000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x220000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x220000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x220000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x220000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x220000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x220000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x220000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x220000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x220000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x220000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x220000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x220000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x220000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x220000+0x8E00)++0x03 "TBU15 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x220000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x220000+0x8E80)++0x03 "TBU15 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x220000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x220000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x220000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU16"
|
|
rgroup.long (0x240000+0xFE0)++0x0F "TBU16 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x240000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x240000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x240000+0x2FB8)++0x03 "TBU16 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x240000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x240000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x240000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU16 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x240000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x240000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x240000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x240000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x240000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x240000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x240000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x240000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x240000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x240000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x240000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x240000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x240000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x240000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x240000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x240000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x240000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x240000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x240000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x240000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x240000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x240000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x240000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x240000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x240000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x240000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x240000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x240000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x240000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x240000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x240000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x240000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x240000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x240000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x240000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x240000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x240000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x240000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x240000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x240000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x240000+0x8E00)++0x03 "TBU16 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x240000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x240000+0x8E80)++0x03 "TBU16 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x240000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x240000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x240000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU17"
|
|
rgroup.long (0x260000+0xFE0)++0x0F "TBU17 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x260000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x260000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x260000+0x2FB8)++0x03 "TBU17 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x260000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x260000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x260000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU17 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x260000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x260000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x260000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x260000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x260000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x260000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x260000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x260000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x260000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x260000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x260000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x260000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x260000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x260000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x260000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x260000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x260000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x260000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x260000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x260000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x260000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x260000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x260000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x260000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x260000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x260000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x260000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x260000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x260000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x260000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x260000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x260000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x260000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x260000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x260000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x260000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x260000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x260000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x260000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x260000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x260000+0x8E00)++0x03 "TBU17 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x260000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x260000+0x8E80)++0x03 "TBU17 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x260000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x260000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x260000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU18"
|
|
rgroup.long (0x280000+0xFE0)++0x0F "TBU18 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x280000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x280000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x280000+0x2FB8)++0x03 "TBU18 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x280000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x280000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x280000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU18 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x280000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x280000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x280000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x280000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x280000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x280000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x280000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x280000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x280000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x280000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x280000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x280000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x280000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x280000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x280000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x280000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x280000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x280000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x280000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x280000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x280000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x280000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x280000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x280000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x280000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x280000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x280000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x280000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x280000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x280000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x280000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x280000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x280000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x280000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x280000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x280000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x280000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x280000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x280000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x280000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x280000+0x8E00)++0x03 "TBU18 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x280000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x280000+0x8E80)++0x03 "TBU18 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x280000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x280000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x280000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU19"
|
|
rgroup.long (0x2A0000+0xFE0)++0x0F "TBU19 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x2A0000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x2A0000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x2A0000+0x2FB8)++0x03 "TBU19 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x2A0000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x2A0000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x2A0000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU19 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x2A0000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x2A0000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x2A0000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x2A0000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x2A0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x2A0000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x2A0000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x2A0000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x2A0000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x2A0000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x2A0000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x2A0000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x2A0000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x2A0000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x2A0000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x2A0000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x2A0000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x2A0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x2A0000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x2A0000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x2A0000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x2A0000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x2A0000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x2A0000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x2A0000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x2A0000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x2A0000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x2A0000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x2A0000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x2A0000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x2A0000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x2A0000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x2A0000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x2A0000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x2A0000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x2A0000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x2A0000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x2A0000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x2A0000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x2A0000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x2A0000+0x8E00)++0x03 "TBU19 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x2A0000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x2A0000+0x8E80)++0x03 "TBU19 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x2A0000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x2A0000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x2A0000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU20"
|
|
rgroup.long (0x2C0000+0xFE0)++0x0F "TBU20 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x2C0000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x2C0000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x2C0000+0x2FB8)++0x03 "TBU20 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x2C0000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x2C0000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x2C0000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU20 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x2C0000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x2C0000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x2C0000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x2C0000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x2C0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x2C0000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x2C0000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x2C0000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x2C0000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x2C0000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x2C0000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x2C0000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x2C0000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x2C0000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x2C0000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x2C0000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x2C0000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x2C0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x2C0000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x2C0000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x2C0000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x2C0000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x2C0000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x2C0000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x2C0000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x2C0000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x2C0000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x2C0000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x2C0000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x2C0000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x2C0000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x2C0000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x2C0000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x2C0000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x2C0000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x2C0000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x2C0000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x2C0000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x2C0000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x2C0000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x2C0000+0x8E00)++0x03 "TBU20 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x2C0000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x2C0000+0x8E80)++0x03 "TBU20 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x2C0000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x2C0000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x2C0000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU21"
|
|
rgroup.long (0x2E0000+0xFE0)++0x0F "TBU21 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x2E0000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x2E0000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x2E0000+0x2FB8)++0x03 "TBU21 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x2E0000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x2E0000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x2E0000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU21 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x2E0000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x2E0000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x2E0000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x2E0000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x2E0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x2E0000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x2E0000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x2E0000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x2E0000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x2E0000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x2E0000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x2E0000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x2E0000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x2E0000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x2E0000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x2E0000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x2E0000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x2E0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x2E0000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x2E0000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x2E0000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x2E0000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x2E0000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x2E0000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x2E0000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x2E0000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x2E0000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x2E0000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x2E0000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x2E0000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x2E0000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x2E0000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x2E0000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x2E0000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x2E0000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x2E0000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x2E0000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x2E0000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x2E0000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x2E0000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x2E0000+0x8E00)++0x03 "TBU21 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x2E0000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x2E0000+0x8E80)++0x03 "TBU21 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x2E0000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x2E0000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x2E0000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU22"
|
|
rgroup.long (0x300000+0xFE0)++0x0F "TBU22 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x300000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x300000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x300000+0x2FB8)++0x03 "TBU22 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x300000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x300000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x300000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU22 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x300000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x300000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x300000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x300000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x300000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x300000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x300000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x300000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x300000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x300000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x300000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x300000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x300000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x300000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x300000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x300000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x300000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x300000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x300000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x300000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x300000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x300000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x300000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x300000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x300000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x300000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x300000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x300000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x300000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x300000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x300000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x300000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x300000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x300000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x300000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x300000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x300000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x300000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x300000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x300000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x300000+0x8E00)++0x03 "TBU22 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x300000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x300000+0x8E80)++0x03 "TBU22 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x300000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x300000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x300000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU23"
|
|
rgroup.long (0x320000+0xFE0)++0x0F "TBU23 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x320000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x320000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x320000+0x2FB8)++0x03 "TBU23 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x320000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x320000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x320000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU23 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x320000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x320000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x320000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x320000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x320000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x320000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x320000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x320000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x320000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x320000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x320000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x320000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x320000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x320000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x320000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x320000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x320000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x320000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x320000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x320000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x320000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x320000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x320000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x320000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x320000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x320000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x320000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x320000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x320000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x320000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x320000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x320000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x320000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x320000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x320000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x320000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x320000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x320000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x320000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x320000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x320000+0x8E00)++0x03 "TBU23 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x320000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x320000+0x8E80)++0x03 "TBU23 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x320000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x320000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x320000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU24"
|
|
rgroup.long (0x340000+0xFE0)++0x0F "TBU24 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x340000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x340000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x340000+0x2FB8)++0x03 "TBU24 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x340000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x340000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x340000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU24 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x340000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x340000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x340000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x340000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x340000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x340000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x340000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x340000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x340000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x340000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x340000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x340000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x340000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x340000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x340000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x340000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x340000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x340000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x340000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x340000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x340000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x340000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x340000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x340000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x340000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x340000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x340000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x340000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x340000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x340000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x340000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x340000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x340000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x340000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x340000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x340000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x340000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x340000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x340000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x340000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x340000+0x8E00)++0x03 "TBU24 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x340000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x340000+0x8E80)++0x03 "TBU24 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x340000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x340000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x340000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU25"
|
|
rgroup.long (0x360000+0xFE0)++0x0F "TBU25 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x360000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x360000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x360000+0x2FB8)++0x03 "TBU25 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x360000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x360000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x360000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU25 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x360000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x360000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x360000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x360000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x360000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x360000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x360000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x360000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x360000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x360000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x360000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x360000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x360000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x360000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x360000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x360000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x360000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x360000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x360000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x360000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x360000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x360000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x360000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x360000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x360000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x360000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x360000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x360000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x360000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x360000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x360000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x360000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x360000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x360000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x360000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x360000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x360000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x360000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x360000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x360000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x360000+0x8E00)++0x03 "TBU25 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x360000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x360000+0x8E80)++0x03 "TBU25 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x360000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x360000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x360000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU26"
|
|
rgroup.long (0x380000+0xFE0)++0x0F "TBU26 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x380000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x380000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x380000+0x2FB8)++0x03 "TBU26 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x380000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x380000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x380000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU26 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x380000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x380000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x380000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x380000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x380000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x380000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x380000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x380000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x380000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x380000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x380000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x380000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x380000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x380000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x380000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x380000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x380000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x380000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x380000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x380000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x380000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x380000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x380000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x380000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x380000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x380000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x380000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x380000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x380000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x380000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x380000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x380000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x380000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x380000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x380000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x380000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x380000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x380000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x380000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x380000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x380000+0x8E00)++0x03 "TBU26 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x380000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x380000+0x8E80)++0x03 "TBU26 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x380000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x380000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x380000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU27"
|
|
rgroup.long (0x3A0000+0xFE0)++0x0F "TBU27 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x3A0000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x3A0000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x3A0000+0x2FB8)++0x03 "TBU27 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x3A0000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x3A0000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x3A0000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU27 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x3A0000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x3A0000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x3A0000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x3A0000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x3A0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x3A0000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x3A0000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x3A0000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x3A0000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x3A0000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x3A0000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x3A0000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x3A0000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x3A0000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x3A0000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x3A0000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x3A0000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x3A0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x3A0000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x3A0000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x3A0000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x3A0000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x3A0000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x3A0000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x3A0000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x3A0000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x3A0000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x3A0000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x3A0000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x3A0000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x3A0000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x3A0000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x3A0000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x3A0000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x3A0000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x3A0000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x3A0000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x3A0000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x3A0000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x3A0000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x3A0000+0x8E00)++0x03 "TBU27 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x3A0000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x3A0000+0x8E80)++0x03 "TBU27 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x3A0000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x3A0000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x3A0000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU28"
|
|
rgroup.long (0x3C0000+0xFE0)++0x0F "TBU28 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x3C0000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x3C0000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x3C0000+0x2FB8)++0x03 "TBU28 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x3C0000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x3C0000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x3C0000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU28 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x3C0000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x3C0000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x3C0000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x3C0000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x3C0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x3C0000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x3C0000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x3C0000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x3C0000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x3C0000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x3C0000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x3C0000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x3C0000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x3C0000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x3C0000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x3C0000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x3C0000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x3C0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x3C0000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x3C0000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x3C0000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x3C0000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x3C0000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x3C0000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x3C0000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x3C0000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x3C0000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x3C0000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x3C0000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x3C0000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x3C0000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x3C0000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x3C0000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x3C0000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x3C0000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x3C0000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x3C0000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x3C0000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x3C0000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x3C0000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x3C0000+0x8E00)++0x03 "TBU28 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x3C0000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x3C0000+0x8E80)++0x03 "TBU28 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x3C0000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x3C0000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x3C0000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU29"
|
|
rgroup.long (0x3E0000+0xFE0)++0x0F "TBU29 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x3E0000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x3E0000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x3E0000+0x2FB8)++0x03 "TBU29 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x3E0000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x3E0000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x3E0000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU29 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x3E0000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x3E0000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x3E0000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x3E0000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x3E0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x3E0000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x3E0000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x3E0000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x3E0000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x3E0000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x3E0000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x3E0000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x3E0000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x3E0000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x3E0000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x3E0000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x3E0000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x3E0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x3E0000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x3E0000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x3E0000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x3E0000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x3E0000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x3E0000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x3E0000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x3E0000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x3E0000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x3E0000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x3E0000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x3E0000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x3E0000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x3E0000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x3E0000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x3E0000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x3E0000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x3E0000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x3E0000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x3E0000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x3E0000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x3E0000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x3E0000+0x8E00)++0x03 "TBU29 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x3E0000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x3E0000+0x8E80)++0x03 "TBU29 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x3E0000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x3E0000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x3E0000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU30"
|
|
rgroup.long (0x400000+0xFE0)++0x0F "TBU30 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x400000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x400000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x400000+0x2FB8)++0x03 "TBU30 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x400000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x400000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x400000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU30 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x400000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x400000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x400000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x400000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x400000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x400000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x400000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x400000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x400000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x400000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x400000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x400000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x400000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x400000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x400000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x400000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x400000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x400000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x400000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x400000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x400000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x400000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x400000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x400000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x400000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x400000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x400000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x400000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x400000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x400000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x400000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x400000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x400000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x400000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x400000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x400000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x400000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x400000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x400000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x400000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x400000+0x8E00)++0x03 "TBU30 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x400000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x400000+0x8E80)++0x03 "TBU30 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x400000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x400000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x400000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU31"
|
|
rgroup.long (0x420000+0xFE0)++0x0F "TBU31 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x420000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x420000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x420000+0x2FB8)++0x03 "TBU31 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x420000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x420000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x420000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU31 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x420000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x420000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x420000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x420000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x420000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x420000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x420000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x420000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x420000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x420000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x420000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x420000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x420000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x420000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x420000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x420000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x420000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x420000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x420000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x420000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x420000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x420000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x420000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x420000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x420000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x420000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x420000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x420000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x420000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x420000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x420000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x420000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x420000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x420000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x420000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x420000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x420000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x420000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x420000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x420000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x420000+0x8E00)++0x03 "TBU31 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x420000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x420000+0x8E80)++0x03 "TBU31 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x420000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x420000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x420000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU32"
|
|
rgroup.long (0x440000+0xFE0)++0x0F "TBU32 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x440000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x440000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x440000+0x2FB8)++0x03 "TBU32 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x440000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x440000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x440000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU32 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x440000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x440000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x440000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x440000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x440000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x440000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x440000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x440000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x440000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x440000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x440000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x440000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x440000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x440000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x440000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x440000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x440000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x440000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x440000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x440000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x440000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x440000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x440000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x440000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x440000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x440000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x440000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x440000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x440000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x440000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x440000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x440000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x440000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x440000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x440000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x440000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x440000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x440000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x440000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x440000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x440000+0x8E00)++0x03 "TBU32 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x440000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x440000+0x8E80)++0x03 "TBU32 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x440000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x440000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x440000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU33"
|
|
rgroup.long (0x460000+0xFE0)++0x0F "TBU33 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x460000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x460000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x460000+0x2FB8)++0x03 "TBU33 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x460000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x460000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x460000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU33 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x460000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x460000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x460000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x460000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x460000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x460000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x460000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x460000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x460000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x460000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x460000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x460000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x460000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x460000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x460000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x460000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x460000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x460000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x460000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x460000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x460000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x460000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x460000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x460000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x460000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x460000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x460000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x460000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x460000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x460000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x460000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x460000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x460000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x460000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x460000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x460000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x460000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x460000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x460000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x460000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x460000+0x8E00)++0x03 "TBU33 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x460000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x460000+0x8E80)++0x03 "TBU33 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x460000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x460000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x460000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU34"
|
|
rgroup.long (0x480000+0xFE0)++0x0F "TBU34 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x480000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x480000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x480000+0x2FB8)++0x03 "TBU34 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x480000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x480000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x480000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU34 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x480000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x480000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x480000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x480000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x480000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x480000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x480000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x480000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x480000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x480000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x480000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x480000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x480000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x480000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x480000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x480000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x480000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x480000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x480000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x480000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x480000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x480000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x480000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x480000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x480000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x480000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x480000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x480000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x480000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x480000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x480000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x480000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x480000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x480000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x480000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x480000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x480000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x480000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x480000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x480000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x480000+0x8E00)++0x03 "TBU34 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x480000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x480000+0x8E80)++0x03 "TBU34 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x480000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x480000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x480000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU35"
|
|
rgroup.long (0x4A0000+0xFE0)++0x0F "TBU35 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x4A0000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x4A0000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x4A0000+0x2FB8)++0x03 "TBU35 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x4A0000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x4A0000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x4A0000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU35 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x4A0000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x4A0000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x4A0000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x4A0000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x4A0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x4A0000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x4A0000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x4A0000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x4A0000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x4A0000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x4A0000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x4A0000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x4A0000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x4A0000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x4A0000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x4A0000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x4A0000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x4A0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x4A0000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x4A0000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x4A0000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x4A0000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x4A0000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x4A0000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x4A0000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x4A0000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x4A0000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x4A0000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x4A0000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x4A0000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x4A0000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x4A0000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x4A0000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x4A0000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x4A0000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x4A0000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x4A0000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x4A0000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x4A0000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x4A0000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x4A0000+0x8E00)++0x03 "TBU35 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x4A0000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x4A0000+0x8E80)++0x03 "TBU35 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x4A0000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x4A0000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x4A0000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU36"
|
|
rgroup.long (0x4C0000+0xFE0)++0x0F "TBU36 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x4C0000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x4C0000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x4C0000+0x2FB8)++0x03 "TBU36 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x4C0000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x4C0000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x4C0000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU36 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x4C0000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x4C0000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x4C0000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x4C0000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x4C0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x4C0000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x4C0000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x4C0000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x4C0000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x4C0000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x4C0000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x4C0000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x4C0000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x4C0000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x4C0000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x4C0000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x4C0000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x4C0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x4C0000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x4C0000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x4C0000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x4C0000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x4C0000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x4C0000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x4C0000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x4C0000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x4C0000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x4C0000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x4C0000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x4C0000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x4C0000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x4C0000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x4C0000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x4C0000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x4C0000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x4C0000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x4C0000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x4C0000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x4C0000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x4C0000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x4C0000+0x8E00)++0x03 "TBU36 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x4C0000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x4C0000+0x8E80)++0x03 "TBU36 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x4C0000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x4C0000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x4C0000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU37"
|
|
rgroup.long (0x4E0000+0xFE0)++0x0F "TBU37 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x4E0000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x4E0000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x4E0000+0x2FB8)++0x03 "TBU37 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x4E0000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x4E0000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x4E0000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU37 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x4E0000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x4E0000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x4E0000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x4E0000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x4E0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x4E0000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x4E0000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x4E0000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x4E0000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x4E0000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x4E0000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x4E0000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x4E0000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x4E0000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x4E0000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x4E0000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x4E0000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x4E0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x4E0000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x4E0000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x4E0000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x4E0000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x4E0000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x4E0000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x4E0000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x4E0000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x4E0000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x4E0000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x4E0000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x4E0000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x4E0000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x4E0000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x4E0000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x4E0000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x4E0000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x4E0000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x4E0000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x4E0000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x4E0000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x4E0000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x4E0000+0x8E00)++0x03 "TBU37 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x4E0000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x4E0000+0x8E80)++0x03 "TBU37 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x4E0000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x4E0000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x4E0000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU38"
|
|
rgroup.long (0x500000+0xFE0)++0x0F "TBU38 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x500000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x500000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x500000+0x2FB8)++0x03 "TBU38 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x500000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x500000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x500000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU38 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x500000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x500000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x500000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x500000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x500000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x500000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x500000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x500000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x500000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x500000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x500000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x500000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x500000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x500000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x500000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x500000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x500000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x500000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x500000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x500000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x500000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x500000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x500000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x500000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x500000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x500000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x500000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x500000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x500000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x500000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x500000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x500000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x500000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x500000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x500000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x500000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x500000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x500000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x500000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x500000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x500000+0x8E00)++0x03 "TBU38 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x500000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x500000+0x8E80)++0x03 "TBU38 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x500000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x500000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x500000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU39"
|
|
rgroup.long (0x520000+0xFE0)++0x0F "TBU39 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x520000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x520000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x520000+0x2FB8)++0x03 "TBU39 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x520000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x520000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x520000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU39 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x520000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x520000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x520000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x520000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x520000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x520000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x520000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x520000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x520000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x520000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x520000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x520000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x520000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x520000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x520000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x520000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x520000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x520000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x520000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x520000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x520000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x520000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x520000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x520000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x520000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x520000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x520000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x520000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x520000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x520000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x520000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x520000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x520000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x520000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x520000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x520000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x520000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x520000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x520000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x520000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x520000+0x8E00)++0x03 "TBU39 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x520000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x520000+0x8E80)++0x03 "TBU39 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x520000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x520000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x520000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU40"
|
|
rgroup.long (0x540000+0xFE0)++0x0F "TBU40 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x540000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x540000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x540000+0x2FB8)++0x03 "TBU40 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x540000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x540000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x540000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU40 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x540000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x540000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x540000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x540000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x540000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x540000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x540000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x540000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x540000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x540000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x540000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x540000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x540000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x540000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x540000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x540000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x540000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x540000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x540000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x540000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x540000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x540000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x540000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x540000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x540000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x540000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x540000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x540000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x540000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x540000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x540000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x540000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x540000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x540000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x540000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x540000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x540000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x540000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x540000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x540000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x540000+0x8E00)++0x03 "TBU40 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x540000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x540000+0x8E80)++0x03 "TBU40 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x540000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x540000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x540000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU41"
|
|
rgroup.long (0x560000+0xFE0)++0x0F "TBU41 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x560000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x560000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x560000+0x2FB8)++0x03 "TBU41 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x560000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x560000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x560000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU41 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x560000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x560000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x560000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x560000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x560000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x560000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x560000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x560000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x560000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x560000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x560000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x560000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x560000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x560000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x560000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x560000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x560000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x560000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x560000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x560000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x560000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x560000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x560000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x560000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x560000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x560000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x560000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x560000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x560000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x560000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x560000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x560000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x560000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x560000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x560000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x560000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x560000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x560000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x560000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x560000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x560000+0x8E00)++0x03 "TBU41 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x560000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x560000+0x8E80)++0x03 "TBU41 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x560000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x560000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x560000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU42"
|
|
rgroup.long (0x580000+0xFE0)++0x0F "TBU42 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x580000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x580000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x580000+0x2FB8)++0x03 "TBU42 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x580000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x580000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x580000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU42 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x580000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x580000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x580000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x580000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x580000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x580000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x580000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x580000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x580000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x580000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x580000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x580000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x580000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x580000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x580000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x580000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x580000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x580000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x580000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x580000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x580000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x580000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x580000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x580000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x580000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x580000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x580000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x580000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x580000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x580000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x580000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x580000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x580000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x580000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x580000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x580000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x580000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x580000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x580000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x580000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x580000+0x8E00)++0x03 "TBU42 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x580000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x580000+0x8E80)++0x03 "TBU42 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x580000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x580000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x580000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU43"
|
|
rgroup.long (0x5A0000+0xFE0)++0x0F "TBU43 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x5A0000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x5A0000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x5A0000+0x2FB8)++0x03 "TBU43 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x5A0000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x5A0000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x5A0000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU43 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x5A0000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x5A0000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x5A0000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x5A0000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x5A0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x5A0000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x5A0000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x5A0000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x5A0000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x5A0000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x5A0000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x5A0000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x5A0000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x5A0000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x5A0000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x5A0000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x5A0000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x5A0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x5A0000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x5A0000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x5A0000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x5A0000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x5A0000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x5A0000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x5A0000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x5A0000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x5A0000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x5A0000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x5A0000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x5A0000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x5A0000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x5A0000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x5A0000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x5A0000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x5A0000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x5A0000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x5A0000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x5A0000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x5A0000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x5A0000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x5A0000+0x8E00)++0x03 "TBU43 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x5A0000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x5A0000+0x8E80)++0x03 "TBU43 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x5A0000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x5A0000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x5A0000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU44"
|
|
rgroup.long (0x5C0000+0xFE0)++0x0F "TBU44 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x5C0000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x5C0000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x5C0000+0x2FB8)++0x03 "TBU44 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x5C0000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x5C0000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x5C0000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU44 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x5C0000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x5C0000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x5C0000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x5C0000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x5C0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x5C0000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x5C0000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x5C0000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x5C0000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x5C0000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x5C0000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x5C0000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x5C0000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x5C0000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x5C0000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x5C0000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x5C0000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x5C0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x5C0000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x5C0000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x5C0000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x5C0000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x5C0000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x5C0000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x5C0000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x5C0000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x5C0000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x5C0000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x5C0000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x5C0000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x5C0000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x5C0000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x5C0000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x5C0000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x5C0000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x5C0000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x5C0000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x5C0000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x5C0000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x5C0000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x5C0000+0x8E00)++0x03 "TBU44 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x5C0000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x5C0000+0x8E80)++0x03 "TBU44 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x5C0000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x5C0000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x5C0000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU45"
|
|
rgroup.long (0x5E0000+0xFE0)++0x0F "TBU45 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x5E0000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x5E0000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x5E0000+0x2FB8)++0x03 "TBU45 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x5E0000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x5E0000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x5E0000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU45 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x5E0000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x5E0000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x5E0000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x5E0000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x5E0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x5E0000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x5E0000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x5E0000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x5E0000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x5E0000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x5E0000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x5E0000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x5E0000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x5E0000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x5E0000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x5E0000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x5E0000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x5E0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x5E0000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x5E0000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x5E0000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x5E0000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x5E0000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x5E0000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x5E0000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x5E0000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x5E0000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x5E0000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x5E0000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x5E0000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x5E0000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x5E0000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x5E0000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x5E0000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x5E0000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x5E0000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x5E0000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x5E0000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x5E0000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x5E0000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x5E0000+0x8E00)++0x03 "TBU45 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x5E0000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x5E0000+0x8E80)++0x03 "TBU45 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x5E0000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x5E0000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x5E0000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU46"
|
|
rgroup.long (0x600000+0xFE0)++0x0F "TBU46 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x600000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x600000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x600000+0x2FB8)++0x03 "TBU46 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x600000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x600000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x600000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU46 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x600000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x600000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x600000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x600000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x600000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x600000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x600000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x600000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x600000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x600000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x600000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x600000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x600000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x600000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x600000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x600000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x600000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x600000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x600000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x600000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x600000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x600000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x600000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x600000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x600000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x600000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x600000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x600000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x600000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x600000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x600000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x600000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x600000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x600000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x600000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x600000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x600000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x600000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x600000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x600000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x600000+0x8E00)++0x03 "TBU46 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x600000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x600000+0x8E80)++0x03 "TBU46 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x600000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x600000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x600000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU47"
|
|
rgroup.long (0x620000+0xFE0)++0x0F "TBU47 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x620000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x620000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x620000+0x2FB8)++0x03 "TBU47 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x620000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x620000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x620000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU47 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x620000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x620000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x620000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x620000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x620000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x620000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x620000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x620000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x620000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x620000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x620000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x620000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x620000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x620000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x620000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x620000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x620000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x620000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x620000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x620000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x620000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x620000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x620000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x620000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x620000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x620000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x620000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x620000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x620000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x620000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x620000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x620000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x620000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x620000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x620000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x620000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x620000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x620000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x620000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x620000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x620000+0x8E00)++0x03 "TBU47 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x620000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x620000+0x8E80)++0x03 "TBU47 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x620000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x620000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x620000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU48"
|
|
rgroup.long (0x640000+0xFE0)++0x0F "TBU48 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x640000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x640000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x640000+0x2FB8)++0x03 "TBU48 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x640000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x640000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x640000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU48 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x640000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x640000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x640000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x640000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x640000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x640000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x640000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x640000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x640000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x640000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x640000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x640000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x640000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x640000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x640000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x640000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x640000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x640000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x640000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x640000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x640000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x640000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x640000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x640000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x640000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x640000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x640000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x640000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x640000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x640000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x640000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x640000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x640000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x640000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x640000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x640000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x640000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x640000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x640000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x640000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x640000+0x8E00)++0x03 "TBU48 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x640000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x640000+0x8E80)++0x03 "TBU48 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x640000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x640000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x640000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU49"
|
|
rgroup.long (0x660000+0xFE0)++0x0F "TBU49 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x660000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x660000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x660000+0x2FB8)++0x03 "TBU49 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x660000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x660000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x660000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU49 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x660000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x660000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x660000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x660000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x660000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x660000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x660000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x660000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x660000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x660000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x660000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x660000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x660000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x660000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x660000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x660000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x660000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x660000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x660000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x660000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x660000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x660000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x660000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x660000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x660000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x660000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x660000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x660000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x660000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x660000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x660000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x660000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x660000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x660000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x660000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x660000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x660000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x660000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x660000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x660000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x660000+0x8E00)++0x03 "TBU49 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x660000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x660000+0x8E80)++0x03 "TBU49 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x660000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x660000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x660000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU50"
|
|
rgroup.long (0x680000+0xFE0)++0x0F "TBU50 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x680000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x680000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x680000+0x2FB8)++0x03 "TBU50 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x680000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x680000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x680000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU50 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x680000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x680000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x680000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x680000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x680000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x680000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x680000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x680000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x680000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x680000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x680000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x680000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x680000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x680000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x680000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x680000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x680000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x680000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x680000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x680000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x680000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x680000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x680000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x680000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x680000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x680000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x680000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x680000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x680000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x680000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x680000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x680000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x680000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x680000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x680000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x680000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x680000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x680000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x680000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x680000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x680000+0x8E00)++0x03 "TBU50 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x680000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x680000+0x8E80)++0x03 "TBU50 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x680000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x680000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x680000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU51"
|
|
rgroup.long (0x6A0000+0xFE0)++0x0F "TBU51 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x6A0000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x6A0000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x6A0000+0x2FB8)++0x03 "TBU51 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x6A0000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x6A0000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x6A0000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU51 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x6A0000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x6A0000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x6A0000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x6A0000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x6A0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x6A0000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x6A0000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x6A0000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x6A0000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x6A0000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x6A0000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x6A0000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x6A0000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x6A0000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x6A0000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x6A0000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x6A0000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x6A0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x6A0000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x6A0000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x6A0000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x6A0000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x6A0000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x6A0000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x6A0000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x6A0000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x6A0000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x6A0000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x6A0000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x6A0000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x6A0000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x6A0000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x6A0000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x6A0000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x6A0000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x6A0000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x6A0000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x6A0000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x6A0000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x6A0000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x6A0000+0x8E00)++0x03 "TBU51 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x6A0000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x6A0000+0x8E80)++0x03 "TBU51 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x6A0000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x6A0000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x6A0000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU52"
|
|
rgroup.long (0x6C0000+0xFE0)++0x0F "TBU52 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x6C0000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x6C0000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x6C0000+0x2FB8)++0x03 "TBU52 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x6C0000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x6C0000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x6C0000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU52 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x6C0000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x6C0000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x6C0000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x6C0000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x6C0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x6C0000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x6C0000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x6C0000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x6C0000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x6C0000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x6C0000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x6C0000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x6C0000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x6C0000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x6C0000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x6C0000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x6C0000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x6C0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x6C0000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x6C0000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x6C0000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x6C0000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x6C0000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x6C0000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x6C0000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x6C0000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x6C0000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x6C0000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x6C0000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x6C0000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x6C0000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x6C0000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x6C0000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x6C0000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x6C0000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x6C0000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x6C0000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x6C0000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x6C0000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x6C0000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x6C0000+0x8E00)++0x03 "TBU52 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x6C0000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x6C0000+0x8E80)++0x03 "TBU52 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x6C0000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x6C0000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x6C0000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU53"
|
|
rgroup.long (0x6E0000+0xFE0)++0x0F "TBU53 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x6E0000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x6E0000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x6E0000+0x2FB8)++0x03 "TBU53 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x6E0000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x6E0000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x6E0000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU53 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x6E0000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x6E0000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x6E0000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x6E0000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x6E0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x6E0000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x6E0000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x6E0000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x6E0000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x6E0000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x6E0000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x6E0000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x6E0000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x6E0000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x6E0000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x6E0000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x6E0000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x6E0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x6E0000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x6E0000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x6E0000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x6E0000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x6E0000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x6E0000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x6E0000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x6E0000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x6E0000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x6E0000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x6E0000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x6E0000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x6E0000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x6E0000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x6E0000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x6E0000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x6E0000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x6E0000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x6E0000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x6E0000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x6E0000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x6E0000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x6E0000+0x8E00)++0x03 "TBU53 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x6E0000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x6E0000+0x8E80)++0x03 "TBU53 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x6E0000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x6E0000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x6E0000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU54"
|
|
rgroup.long (0x700000+0xFE0)++0x0F "TBU54 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x700000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x700000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x700000+0x2FB8)++0x03 "TBU54 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x700000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x700000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x700000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU54 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x700000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x700000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x700000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x700000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x700000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x700000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x700000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x700000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x700000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x700000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x700000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x700000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x700000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x700000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x700000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x700000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x700000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x700000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x700000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x700000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x700000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x700000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x700000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x700000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x700000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x700000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x700000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x700000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x700000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x700000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x700000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x700000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x700000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x700000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x700000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x700000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x700000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x700000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x700000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x700000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x700000+0x8E00)++0x03 "TBU54 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x700000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x700000+0x8E80)++0x03 "TBU54 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x700000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x700000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x700000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU55"
|
|
rgroup.long (0x720000+0xFE0)++0x0F "TBU55 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x720000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x720000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x720000+0x2FB8)++0x03 "TBU55 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x720000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x720000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x720000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU55 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x720000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x720000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x720000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x720000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x720000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x720000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x720000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x720000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x720000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x720000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x720000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x720000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x720000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x720000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x720000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x720000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x720000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x720000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x720000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x720000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x720000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x720000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x720000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x720000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x720000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x720000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x720000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x720000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x720000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x720000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x720000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x720000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x720000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x720000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x720000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x720000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x720000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x720000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x720000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x720000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x720000+0x8E00)++0x03 "TBU55 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x720000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x720000+0x8E80)++0x03 "TBU55 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x720000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x720000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x720000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU56"
|
|
rgroup.long (0x740000+0xFE0)++0x0F "TBU56 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x740000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x740000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x740000+0x2FB8)++0x03 "TBU56 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x740000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x740000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x740000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU56 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x740000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x740000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x740000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x740000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x740000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x740000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x740000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x740000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x740000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x740000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x740000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x740000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x740000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x740000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x740000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x740000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x740000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x740000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x740000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x740000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x740000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x740000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x740000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x740000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x740000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x740000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x740000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x740000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x740000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x740000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x740000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x740000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x740000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x740000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x740000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x740000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x740000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x740000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x740000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x740000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x740000+0x8E00)++0x03 "TBU56 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x740000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x740000+0x8E80)++0x03 "TBU56 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x740000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x740000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x740000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU57"
|
|
rgroup.long (0x760000+0xFE0)++0x0F "TBU57 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x760000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x760000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x760000+0x2FB8)++0x03 "TBU57 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x760000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x760000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x760000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU57 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x760000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x760000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x760000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x760000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x760000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x760000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x760000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x760000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x760000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x760000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x760000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x760000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x760000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x760000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x760000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x760000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x760000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x760000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x760000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x760000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x760000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x760000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x760000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x760000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x760000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x760000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x760000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x760000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x760000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x760000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x760000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x760000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x760000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x760000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x760000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x760000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x760000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x760000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x760000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x760000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x760000+0x8E00)++0x03 "TBU57 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x760000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x760000+0x8E80)++0x03 "TBU57 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x760000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x760000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x760000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU58"
|
|
rgroup.long (0x780000+0xFE0)++0x0F "TBU58 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x780000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x780000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x780000+0x2FB8)++0x03 "TBU58 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x780000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x780000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x780000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU58 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x780000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x780000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x780000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x780000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x780000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x780000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x780000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x780000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x780000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x780000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x780000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x780000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x780000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x780000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x780000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x780000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x780000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x780000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x780000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x780000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x780000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x780000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x780000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x780000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x780000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x780000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x780000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x780000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x780000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x780000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x780000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x780000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x780000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x780000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x780000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x780000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x780000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x780000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x780000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x780000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x780000+0x8E00)++0x03 "TBU58 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x780000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x780000+0x8E80)++0x03 "TBU58 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x780000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x780000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x780000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU59"
|
|
rgroup.long (0x7A0000+0xFE0)++0x0F "TBU59 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x7A0000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x7A0000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x7A0000+0x2FB8)++0x03 "TBU59 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x7A0000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x7A0000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x7A0000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU59 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x7A0000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x7A0000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x7A0000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x7A0000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x7A0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x7A0000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x7A0000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x7A0000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x7A0000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x7A0000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x7A0000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x7A0000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x7A0000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x7A0000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x7A0000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x7A0000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x7A0000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x7A0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x7A0000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x7A0000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x7A0000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x7A0000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x7A0000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x7A0000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x7A0000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x7A0000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x7A0000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x7A0000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x7A0000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x7A0000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x7A0000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x7A0000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x7A0000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x7A0000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x7A0000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x7A0000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x7A0000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x7A0000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x7A0000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x7A0000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x7A0000+0x8E00)++0x03 "TBU59 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x7A0000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x7A0000+0x8E80)++0x03 "TBU59 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x7A0000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x7A0000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x7A0000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU60"
|
|
rgroup.long (0x7C0000+0xFE0)++0x0F "TBU60 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x7C0000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x7C0000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x7C0000+0x2FB8)++0x03 "TBU60 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x7C0000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x7C0000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x7C0000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU60 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x7C0000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x7C0000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x7C0000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x7C0000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x7C0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x7C0000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x7C0000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x7C0000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x7C0000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x7C0000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x7C0000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x7C0000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x7C0000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x7C0000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x7C0000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x7C0000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x7C0000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x7C0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x7C0000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x7C0000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x7C0000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x7C0000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x7C0000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x7C0000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x7C0000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x7C0000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x7C0000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x7C0000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x7C0000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x7C0000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x7C0000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x7C0000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x7C0000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x7C0000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x7C0000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x7C0000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x7C0000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x7C0000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x7C0000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x7C0000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x7C0000+0x8E00)++0x03 "TBU60 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x7C0000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x7C0000+0x8E80)++0x03 "TBU60 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x7C0000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x7C0000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x7C0000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree "TBU61"
|
|
rgroup.long (0x7E0000+0xFE0)++0x0F "TBU61 Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x7E0000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x7E0000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
rgroup.long (0x7E0000+0x2FB8)++0x03 "TBU61 PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x7E0000+0x2FE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x7E0000+0x2FD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x7E0000+0x2FF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
tree "TBU61 Performance Monitoring Unit Registers"
|
|
//args: <smmu_baseaddr> <pmu_baseaddr> <smmu_name>
|
|
rgroup.long (0x7E0000+0x2000+0xFB8)++0x03 "PMU Component and Peripheral ID Registers"
|
|
line.long 0x00 "SMMU_PMCG_PMAUTHSTATUS,PMU Authentication Status Register"
|
|
rgroup.long (0x7E0000+0x2000+0xFE0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_PIDR0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number bits [7:0]"
|
|
line.long 0x04 "SMMU_PMCG_PIDR1,Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "DES_0,JEP106 designer code bits [3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PART_1,Part number bits [11:8]"
|
|
line.long 0x08 "SMMU_PMCG_PIDR2,Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x08 4.--7. 1. "REVISION,Major revision field"
|
|
bitfld.long 0x08 3. "JEDEC,JEDEC-assigned value for DES always used" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. "DES_1,JEP106 designer code bits [6:4]"
|
|
line.long 0x0C "SMMU_PMCG_PIDR3,Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. "REVAND,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. "CMOD,Customer modified"
|
|
rgroup.long (0x7E0000+0x2000+0xFD0)++0x03
|
|
line.long 0x00 "SMMU_PMCG_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. "SIZE,Size of the configuration space value"
|
|
hexmask.long.byte 0x00 0.--3. 1. "DES_2,JEP106 designer continuation code"
|
|
rgroup.long (0x7E0000+0x2000+0xFF0)++0x0F
|
|
line.long 0x00 "SMMU_PMCG_CIDR0,Component Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x04 "SMMU_PMCG_CIDR1,Component Identification Register 1"
|
|
hexmask.long.byte 0x04 4.--7. 1. "CLASS,Component class"
|
|
hexmask.long.byte 0x04 0.--3. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x08 "SMMU_PMCG_CIDR2,Component Identification Register 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
line.long 0x0C "SMMU_PMCG_CIDR3,Component Identification Register 3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. "PREAMBLE,Preamble identification value"
|
|
if ((per.q(&MMU600_base+0x7E0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
group.long (0x7E0000+0x2000+0x0)++0x03 "Performance Monitor Counter Group Registers"
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.long (0x7E0000+0x2000+0x4)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.long (0x7E0000+0x2000+0x8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.long (0x7E0000+0x2000+0xC)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
else
|
|
group.quad (0x7E0000+0x2000+0x0)++0x07 "Performance Monitor Counter Group Registers"
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR0,SMMU PMCG Event Counter 0"
|
|
group.quad (0x7E0000+0x2000+0x8)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR1,SMMU PMCG Event Counter 1"
|
|
group.quad (0x7E0000+0x2000+0x10)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR2,SMMU PMCG Event Counter 2"
|
|
group.quad (0x7E0000+0x2000+0x18)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_EVCNTR3,SMMU PMCG Event Counter 3"
|
|
endif
|
|
group.long (0x7E0000+0x2000+0x400)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER0,SMMU PMCG Event Counter 0 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 0 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR0.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x7E0000+0x2000+0x404)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER1,SMMU PMCG Event Counter 1 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 1 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR1.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x7E0000+0x2000+0x408)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER2,SMMU PMCG Event Counter 2 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 2 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR2.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
group.long (0x7E0000+0x2000+0x40C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_EVTYPER3,SMMU PMCG Event Counter 3 Event Type Configuration Register"
|
|
bitfld.long 0x00 31. "OVFCAP,An overflow of counter 3 triggers a capture of all counters" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. "FILTER_SEC_SID,StreamIDs events type to count" "Non-secure,Secure"
|
|
bitfld.long 0x00 29. "FILTER_SID_SPAN,Match span of StreamID values" "Exact match,SMMU_PMCG_SMR3.STREAMID dependent"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "EVENT,Event type that causes this counter to increment"
|
|
if ((per.q(&MMU600_base+0x7E0000+0x2000+0xE00)&0x3F00)<=0x1F00)
|
|
rgroup.long (0x7E0000+0x2000+0x600)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.long (0x7E0000+0x2000+0x604)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.long (0x7E0000+0x2000+0x608)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.long (0x7E0000+0x2000+0x60C)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
else
|
|
rgroup.quad (0x7E0000+0x2000+0x600)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR0,SMMU PMCG Event Counter 0 Shadow Value Register"
|
|
rgroup.quad (0x7E0000+0x2000+0x608)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR1,SMMU PMCG Event Counter 1 Shadow Value Register"
|
|
rgroup.quad (0x7E0000+0x2000+0x610)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR2,SMMU PMCG Event Counter 2 Shadow Value Register"
|
|
rgroup.quad (0x7E0000+0x2000+0x618)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_SVR3,SMMU PMCG Event Counter 3 Shadow Value Register"
|
|
endif
|
|
group.quad (0x7E0000+0x2000+0xC00)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENSET0,SMMU PMCG Counter Enable Set Register"
|
|
group.quad (0x7E0000+0x2000+0xC20)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_CNTENCLR0,SMMU PMCG Counter Enable Clear Register"
|
|
group.quad (0x7E0000+0x2000+0xC40)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENSET0,SMMU PMCG Interrupt Contribution Enable Set Register"
|
|
group.quad (0x7E0000+0x2000+0xC60)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_INTENCLR0,SMMU PMCG Interrupt Contribution Enable Clear Register"
|
|
group.quad (0x7E0000+0x2000+0xC80)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSCLR0,SMMU PMCG Overflow Status Clear Register"
|
|
group.quad (0x7E0000+0x2000+0xCC0)++0x07
|
|
line.quad 0x00 "SMMU_PMCG_OVSSET0,SMMU PMCG Overflow Status Set Register"
|
|
wgroup.long (0x7E0000+0x2000+0xD88)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CAPR,SMMU PMCG Counter Shadow Value Capture Register"
|
|
bitfld.long 0x00 0. "CAPTURE,Capture all SMMU_PMCG_EVCNTRn values within the PMCG into their respective SMMU_PMCG_SVRn shadow register" "No effect,Capture"
|
|
group.long (0x7E0000+0x2000+0xDF8)++0x03
|
|
line.long 0x00 "SMMU_PMCG_SCR,SMMU PMCG Secure Control Register"
|
|
bitfld.long 0x00 2. "NSMSI,Generated MSI NS attribute" "NS == 0,NS == 1"
|
|
bitfld.long 0x00 1. "NSRA,Non-secure register access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. "SO,Secure observation enable" "Disabled,Enabled"
|
|
rgroup.long (0x7E0000+0x2000+0xE00)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CFGR,SMMU PMCG Configuration Information Register"
|
|
bitfld.long 0x00 23. "SID_FILTER_TYPE,StreamID filtering type for each counter" "Separate,Global"
|
|
bitfld.long 0x00 22. "CAPTURE,Capture of counter values support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. "MSI,Message signalled interrupt support" "Not supported,Supported"
|
|
newline
|
|
bitfld.long 0x00 20. "RELOC_CTRS,Relocate registers to page 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. "SIZE,Size of PMCG counters in bits" ",Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32 bit,Reserved,Reserved,Reserved,36 bit,Reserved,Reserved,Reserved,40 bit,Reserved,Reserved,Reserved,44 bit,Reserved,Reserved,Reserved,48 bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64 bit"
|
|
bitfld.long 0x00 0.--5. "NCTR,Number of counters available in the group" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
group.long (0x7E0000+0x2000+0xE04)++0x03
|
|
line.long 0x00 "SMMU_PMCG_CR,SMMU PMCG Control Register"
|
|
bitfld.long 0x00 0. "E,Global counter enable" "Disabled,Enabled"
|
|
rgroup.quad (0x7E0000+0x2000+0xE20)++0x0F
|
|
line.quad 0x00 "SMMU_PMCG_CEID0,SMMU PMCG Common Event ID Register 0"
|
|
line.quad 0x08 "SMMU_PMCG_CEID1,SMMU PMCG Common Event ID Register 1"
|
|
group.long (0x7E0000+0x2000+0xE50)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRL,SMMU PMCG IRQ Enable Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x7E0000+0x2000+0xE54)++0x03
|
|
line.long 0x00 "SMMU_PMCG_IRQ_CTRLACK,SMMU PMCG IRQ Enable Acknowledge Register"
|
|
bitfld.long 0x00 0. "IRQEN,IRQ enable global flag" "Disabled,Enabled"
|
|
rgroup.long (0x7E0000+0x2000+0xE70)++0x03
|
|
line.long 0x00 "SMMU_PMCG_AIDR,SMMU PMCG Architecture Identification Register"
|
|
bitfld.long 0x00 4.--7. "ARCHMAJORREV,Architecture major revision" "SMMUv3,?..."
|
|
bitfld.long 0x00 0.--3. "ARCHMINORREV,Architecture minor revision" "SMMUv3.0,SMMUv3.1,?..."
|
|
tree.end
|
|
group.long (0x7E0000+0x8E00)++0x03 "TBU61 Microarchitectural Registers"
|
|
line.long 0x00 "TBU_CTRL,TBU Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "AUX,AUX"
|
|
group.long (0x7E0000+0x8E18)++0x03
|
|
line.long 0x00 "TBU_SCR,TBU Secure Control Register"
|
|
bitfld.long 0x00 1. "NS_RAS,Non-secure register access is permitted to RAS registers" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. "NS_UARCH,Non-secure register access is permitted to TBU_CTRL register" "Not permitted,Permitted"
|
|
rgroup.long (0x7E0000+0x8E80)++0x03 "TBU61 RAS Registers"
|
|
line.long 0x00 "TBU_ERRFR,TBU Error Feature Register"
|
|
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "0,1,Controllable,3"
|
|
bitfld.long 0x00 0.--1. "ED,TCU error detection" "0,Always enabled,2,3"
|
|
group.long (0x7E0000+0x8E88)++0x03
|
|
line.long 0x00 "TBU_ERRCTLR,TBU Error Control Register"
|
|
bitfld.long 0x00 3. "FI,Fault handling interrupts enable" "Disabled,Enabled"
|
|
group.long (0x7E0000+0x8E90)++0x03
|
|
line.long 0x00 "TBU_ERRSTATUS,TBU Error Record Primary Syndrome Register"
|
|
bitfld.long 0x00 30. "V,Register valid" "Invalid,Valid"
|
|
bitfld.long 0x00 27. "OF,Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 24.--25. "CE,Correctable error" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SERR,Error code"
|
|
group.quad (0x7E0000+0x8EC0)++0x07
|
|
line.quad 0x00 "TCU_ERRGEN,TCU Error Generation Register"
|
|
bitfld.quad 0x00 1. "TMTLB,Force main TLB tag parity error" "Not forced,Forced"
|
|
bitfld.quad 0x00 0. "DMTLB,Force main TLB data parity error" "Not forced,Forced"
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
AUTOINDENT.OFF
|
|
newline
|