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Gen4_R-Car_Trace32/2_Trunk/pera31g3xx.per
woody d411edd9b4 add Trace32 File
2025-10-14 09:52:32 +09:00

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; --------------------------------------------------------------------------------
; @Title: A31G3xx On-Chip Peripherals
; @Props: Released
; @Author: JDU, NEJ
; @Changelog: 2023-02-06 JDU
; 2023-10-31 NEJ
; @Manufacturer: ABOV - ABOV Semiconductor Co., Ltd.
; @Doc: Generated (TRACE32, build: 164232.), based on:
; A31G31x_fixed.svd (Ver. 1.0), A31G32x_fixed.svd (Ver. 1.0)
; @Core: Cortex-M0+
; @Chip: A31G313CLN, A31G313CUN, A31G313RLN, A31G313RMN, A31G313SNN, A31G314CLN,
; A31G314CUN, A31G314MLN, A31G314MMN, A31G314RLN, A31G314RMN, A31G314SNN,
; A31G316MLN, A31G316MMN, A31G316RLN, A31G316RMN, A31G323CLN, A31G323CUN,
; A31G323RLN, A31G324CLN, A31G324CUN, A31G324RLN
; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: pera31g3xx.per 16938 2023-11-07 18:43:11Z kwisniewski $
AUTOINDENT.ON CENTER TREE
ENUMDELIMITER ","
base ad:0x0
tree.close "Core Registers (Cortex-M0+)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0x8
if (CORENAME()=="CORTEXM1")
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
else
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
endif
if (CORENAME()=="CORTEXM1")
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
else
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
endif
rgroup.long 0xd00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
textline " "
hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
group.long 0xd04++0x03
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
textline " "
bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
textline " "
bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
textline " "
bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
textline " "
hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
if (CORENAME()=="CORTEXM0+")
group.long 0xd08++0x03
line.long 0x00 "VTOR,Vector Table Offset Register"
hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
else
textline " "
endif
group.long 0xd0c++0x03
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
textline " "
bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
group.long 0xd10++0x03
line.long 0x00 "SCR,System Control Register"
bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline " "
bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
rgroup.long 0xd14++0x03
line.long 0x00 "CCR,Configuration and Control Register"
bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
group.long 0xd1c++0x0b
line.long 0x00 "SHPR2,System Handler Priority Register 2"
bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
line.long 0x04 "SHPR3,System Handler Priority Register 3"
bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
line.long 0x08 "SHCSR,System Handler Control and State Register"
bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
if (CORENAME()=="CORTEXM0+")
hgroup.long 0x08++0x03
hide.long 0x00 "ACTLR,Auxiliary Control Register"
else
textline " "
endif
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Memory Protection Unit (MPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
rgroup.long 0xD90++0x03
line.long 0x00 "MPU_TYPE,MPU Type Register"
bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..."
group.long 0xD94++0x03
line.long 0x00 "MPU_CTRL,MPU Control Register"
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
group.long 0xD98++0x03
line.long 0x00 "MPU_RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
tree.close "MPU regions"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
group.long 0xD9C++0x03 "Region 0"
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
group.long 0xD9C++0x03 "Region 1"
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
group.long 0xD9C++0x03 "Region 2"
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
group.long 0xD9C++0x03 "Region 3"
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
group.long 0xD9C++0x03 "Region 4"
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
group.long 0xD9C++0x03 "Region 5"
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
group.long 0xD9C++0x03 "Region 6"
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
group.long 0xD9C++0x03 "Region 7"
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
textline " "
textline " "
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
tree "Interrupt Enable Registers"
group.long 0x100++0x03
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
tree.end
tree "Interrupt Pending Registers"
group.long 0x200++0x03
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
tree.end
width 6.
tree "Interrupt Priority Registers"
group.long 0x400++0x1F
line.long 0x00 "INT0,Interrupt Priority Register"
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
line.long 0x04 "INT1,Interrupt Priority Register"
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
line.long 0x08 "INT2,Interrupt Priority Register"
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
line.long 0x0C "INT3,Interrupt Priority Register"
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
line.long 0x10 "INT4,Interrupt Priority Register"
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
line.long 0x14 "INT5,Interrupt Priority Register"
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
line.long 0x18 "INT6,Interrupt Priority Register"
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
line.long 0x1C "INT7,Interrupt Priority Register"
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0xA
group.long 0xD30++0x03
line.long 0x00 "DFSR,Data Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
textline " "
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
textline " "
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
if (CORENAME()=="CORTEXM1")
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
else
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
endif
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Selector Register"
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
group.long 0xDF8++0x07
line.long 0x00 "DCRDR,Debug Core Register Data Register"
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
textline " "
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Breakpoint Unit (BPU)"
sif COMPonent.AVAILABLE("BPU")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
width 8.
group.long 0x00++0x03
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
group.long 0x8++0x03
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
group.long 0xC++0x03
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
group.long 0x10++0x03
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
group.long 0x14++0x03
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
else
newline
textline "BPU component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 14.
rgroup.long 0x00++0x03
line.long 0x00 "DW_CTRL,DW Control Register "
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x1c++0x03
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
group.long 0x20++0x0b
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
line.long 0x04 "DW_MASK0,DW Mask Register 0"
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
group.long 0x30++0x0b
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
tree "ADC (12-bit A/D Converter)"
base ad:0x40003000
sif (cpuis("A31G31*"))
group.long 0x0++0x3
line.long 0x0 "CR,A/D Converter Control Register"
bitfld.long 0x0 15. "ADCEN,A/DC Module Enable bit (The A/DC is automatically disabled at power down mode)" "0: Disable A/DC module operation,1: Enable A/DC module operation"
bitfld.long 0x0 11.--13. "TRIG,A/DC Trigger Signal Selection bits" "0: ADST,1: Timer 10 A-match signal,2: Timer 11 A-match signal,3: Timer 12 A-match signal,4: A/DC trigger signal from timer 30,?,?,?"
newline
bitfld.long 0x0 10. "REFSEL,A/DC Reference Selection bit" "0: Select analog power (VDD),1: Select external reference (AVREF)"
bitfld.long 0x0 8. "ADST,A/DC Conversion Start bit. This bit is automatically cleared to '0b' after operation" "0: No effect,1: Trigger signal generation for conversion start"
newline
bitfld.long 0x0 5. "ADCIEN,A/DC Interrupt Enable bit" "0: Disable A/DC interrupt,1: Enable A/DC interrupt"
bitfld.long 0x0 4. "ADCIFLAG,A/DC Interrupt Flag bit" "0: No request occurred,1: Request occurred This bit is cleared to '0' when.."
newline
hexmask.long.byte 0x0 0.--3. 1. "ADSEL,A/D Converter Channel Selection bits"
rgroup.long 0x4++0x3
line.long 0x0 "DR,A/D Converter Data Register"
hexmask.long.word 0x0 0.--11. 1. "ADDATA,A/D Converter Result Data bits"
group.long 0x8++0x3
line.long 0x0 "PREDR,A/D Converter Prescaler Data Register"
hexmask.long.byte 0x0 0.--4. 1. "PRED,A/D Converter Prescaler Data bits."
endif
sif (cpuis("A31G32*"))
group.long 0x0++0xF
line.long 0x0 "MR,A/D Converter Mode Register"
bitfld.long 0x0 21. "TRGINFO,Trigger information option (In external trigger mode)" "0,1"
bitfld.long 0x0 20. "CHINFO,Channel information option" "0,1"
newline
bitfld.long 0x0 17. "DMAEN,DMA Enable bit (Must be set When ADCEN = 1)" "0,1"
hexmask.long.byte 0x0 12.--16. 1. "STSEL,Sampling Time Selection"
newline
bitfld.long 0x0 8.--10. "SEQCNT,Number of coversion in a sequence" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 7. "ADEN,ADC Enable bit" "0,1"
newline
bitfld.long 0x0 6. "ARST,After sequence finish restart bit" "0,1"
bitfld.long 0x0 4.--5. "ADMOD,ADC Mode Selection bit" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "TRGSEL,Trigger Selection bit" "0,1,2,3"
line.long 0x4 "CSCR,A/D Converter Current Sequence/Channel Register"
bitfld.long 0x4 8.--10. "CSEQN,Current Sequence Number" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 0.--4. 1. "CACH,Current Active Channel"
line.long 0x8 "CCR,A/D Converter Clock Register"
bitfld.long 0x8 15. "ADCPDA,ADC R DAC disable to save power Don't set '1' here(it's optional bit)" "0,1"
hexmask.long.byte 0x8 8.--14. 1. "CLKDIV,ADC clock division value bit(When EXTCLK is 0 CLKDIV Enable)"
newline
bitfld.long 0x8 7. "ADCPD,ADC Deep sleep" "0,1"
bitfld.long 0x8 5. "CLKINIVT,Divide Clock Inversion (Option bit)" "0,1"
line.long 0xC "TRG,A/D Converter Trigger Selection Register"
hexmask.long.byte 0xC 28.--31. 1. "SEQTRG7,8th Sequence Trigger Source"
hexmask.long.byte 0xC 24.--27. 1. "SEQTRG6,7th Sequence Trigger Source"
newline
hexmask.long.byte 0xC 20.--23. 1. "SEQTRG5,6th Sequence Trigger Source"
hexmask.long.byte 0xC 16.--19. 1. "SEQTRG4,5th Sequence Trigger Source"
newline
hexmask.long.byte 0xC 12.--15. 1. "SEQTRG3,4th Sequence Trigger Source"
hexmask.long.byte 0xC 8.--11. 1. "SEQTRG2,3th Sequence Trigger Source"
newline
hexmask.long.byte 0xC 4.--7. 1. "SEQTRG1,2nd Sequence Trigger Source"
hexmask.long.byte 0xC 0.--3. 1. "SEQTRG0,1st Sequence Trigger Source"
group.long 0x18++0x13
line.long 0x0 "SCSR1,A/D Converter Channel Selection 1 Register"
hexmask.long.byte 0x0 24.--28. 1. "SEQ3CH,4th Conversion Sequence Channel Selection"
hexmask.long.byte 0x0 16.--20. 1. "SEQ2CH,3th Conversion Sequence Channel Selection"
newline
hexmask.long.byte 0x0 8.--12. 1. "SEQ1CH,2nd Conversion Sequence Channel Selection"
hexmask.long.byte 0x0 0.--4. 1. "SEQ0CH,1st Conversion Sequence Channel Selection"
line.long 0x4 "SCSR2,A/D Converter Channel Selection 2 Register"
hexmask.long.byte 0x4 24.--28. 1. "SEQ7CH,8th Conversion Sequence Channel Selection"
hexmask.long.byte 0x4 16.--20. 1. "SEQ6CH,7th Conversion Sequence Channel Selection"
newline
hexmask.long.byte 0x4 8.--12. 1. "SEQ5CH,6th Conversion Sequence Channel Selection"
hexmask.long.byte 0x4 0.--4. 1. "SEQ4CH,5th Conversion Sequence Channel Selection"
line.long 0x8 "CR,A/D Converter Control Register"
bitfld.long 0x8 7. "ASTOP,ADC STOP bit" "0,1"
bitfld.long 0x8 1. "TRGCLR,ADC all trigger flags cleared option" "0,1"
newline
bitfld.long 0x8 0. "ASTART,ADC START bit" "0,1"
line.long 0xC "SR,A/D Converter State Register"
bitfld.long 0xC 8. "COMPIFLG,Compare Interrupt Flag bit" "0,1"
rbitfld.long 0xC 5. "DOVRUN,DMA Overrun Flag(Not Interrupt)" "0,1"
newline
rbitfld.long 0xC 4. "DMAF,DMA Done Received Flag(DMA transfer is completed)" "0,1"
bitfld.long 0xC 3. "TRGIF,ADC Trigger Interrupt Flag" "0,1"
newline
bitfld.long 0xC 2. "EOSIF,Sequence End Interrupt Flag" "0,1"
bitfld.long 0xC 0. "EOCIF,Sequence Conversion End Interrupt Flag" "0,1"
line.long 0x10 "IER,A/D Converter Interrupt Enable Register"
bitfld.long 0x10 4. "DMAIE,DMA Done Interrupt Enable" "0,1"
bitfld.long 0x10 3. "TRGIE,ADC Trigger Conversion Interrupt Enable" "0,1"
newline
bitfld.long 0x10 2. "EOSIE,ADC Sequence Conversion Interrupt Enable" "0,1"
bitfld.long 0x10 0. "EOCIE,ADC Single Conversion" "0,1"
rgroup.long 0x2C++0x23
line.long 0x0 "DDR,A/D Converter DMA Data Register"
bitfld.long 0x0 31. "TRGINFO7,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
bitfld.long 0x0 30. "TRGINFO6,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
newline
bitfld.long 0x0 29. "TRGINFO5,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
bitfld.long 0x0 28. "TRGINFO4,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
newline
bitfld.long 0x0 27. "TRGINFO3,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
bitfld.long 0x0 26. "TRGINFO2,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
newline
bitfld.long 0x0 25. "TRGINFO1,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
bitfld.long 0x0 24. "TRGINFO0,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
newline
hexmask.long.byte 0x0 16.--20. 1. "ADMACH,DMA ADC Channel Indicator"
hexmask.long.word 0x0 4.--15. 1. "ADDMAR,DMA ADC Conversion Result Data(12-bit)"
line.long 0x4 "DR0,A/D Converter Sequence 0~7 Data Register"
bitfld.long 0x4 31. "TRGINFO7,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
bitfld.long 0x4 30. "TRGINFO6,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
newline
bitfld.long 0x4 29. "TRGINFO5,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
bitfld.long 0x4 28. "TRGINFO4,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
newline
bitfld.long 0x4 27. "TRGINFO3,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
bitfld.long 0x4 26. "TRGINFO2,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
newline
bitfld.long 0x4 25. "TRGINFO1,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
bitfld.long 0x4 24. "TRGINFO0,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
newline
hexmask.long.byte 0x4 16.--20. 1. "ACH,ADC Channel Information"
hexmask.long.word 0x4 4.--15. 1. "ADDATA,ADC Input data"
line.long 0x8 "DR1,A/D Converter Sequence 0~7 Data Register"
bitfld.long 0x8 31. "TRGINFO7,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
bitfld.long 0x8 30. "TRGINFO6,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
newline
bitfld.long 0x8 29. "TRGINFO5,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
bitfld.long 0x8 28. "TRGINFO4,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
newline
bitfld.long 0x8 27. "TRGINFO3,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
bitfld.long 0x8 26. "TRGINFO2,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
newline
bitfld.long 0x8 25. "TRGINFO1,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
bitfld.long 0x8 24. "TRGINFO0,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
newline
hexmask.long.byte 0x8 16.--20. 1. "ACH,ADC Channel Information"
hexmask.long.word 0x8 4.--15. 1. "ADDATA,ADC Input data"
line.long 0xC "DR2,A/D Converter Sequence 0~7 Data Register"
bitfld.long 0xC 31. "TRGINFO7,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
bitfld.long 0xC 30. "TRGINFO6,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
newline
bitfld.long 0xC 29. "TRGINFO5,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
bitfld.long 0xC 28. "TRGINFO4,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
newline
bitfld.long 0xC 27. "TRGINFO3,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
bitfld.long 0xC 26. "TRGINFO2,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
newline
bitfld.long 0xC 25. "TRGINFO1,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
bitfld.long 0xC 24. "TRGINFO0,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
newline
hexmask.long.byte 0xC 16.--20. 1. "ACH,ADC Channel Information"
hexmask.long.word 0xC 4.--15. 1. "ADDATA,ADC Input data"
line.long 0x10 "DR3,A/D Converter Sequence 0~7 Data Register"
bitfld.long 0x10 31. "TRGINFO7,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
bitfld.long 0x10 30. "TRGINFO6,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
newline
bitfld.long 0x10 29. "TRGINFO5,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
bitfld.long 0x10 28. "TRGINFO4,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
newline
bitfld.long 0x10 27. "TRGINFO3,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
bitfld.long 0x10 26. "TRGINFO2,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
newline
bitfld.long 0x10 25. "TRGINFO1,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
bitfld.long 0x10 24. "TRGINFO0,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
newline
hexmask.long.byte 0x10 16.--20. 1. "ACH,ADC Channel Information"
hexmask.long.word 0x10 4.--15. 1. "ADDATA,ADC Input data"
line.long 0x14 "DR4,A/D Converter Sequence 0~7 Data Register"
bitfld.long 0x14 31. "TRGINFO7,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
bitfld.long 0x14 30. "TRGINFO6,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
newline
bitfld.long 0x14 29. "TRGINFO5,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
bitfld.long 0x14 28. "TRGINFO4,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
newline
bitfld.long 0x14 27. "TRGINFO3,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
bitfld.long 0x14 26. "TRGINFO2,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
newline
bitfld.long 0x14 25. "TRGINFO1,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
bitfld.long 0x14 24. "TRGINFO0,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
newline
hexmask.long.byte 0x14 16.--20. 1. "ACH,ADC Channel Information"
hexmask.long.word 0x14 4.--15. 1. "ADDATA,ADC Input data"
line.long 0x18 "DR5,A/D Converter Sequence 0~7 Data Register"
bitfld.long 0x18 31. "TRGINFO7,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
bitfld.long 0x18 30. "TRGINFO6,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
newline
bitfld.long 0x18 29. "TRGINFO5,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
bitfld.long 0x18 28. "TRGINFO4,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
newline
bitfld.long 0x18 27. "TRGINFO3,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
bitfld.long 0x18 26. "TRGINFO2,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
newline
bitfld.long 0x18 25. "TRGINFO1,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
bitfld.long 0x18 24. "TRGINFO0,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
newline
hexmask.long.byte 0x18 16.--20. 1. "ACH,ADC Channel Information"
hexmask.long.word 0x18 4.--15. 1. "ADDATA,ADC Input data"
line.long 0x1C "DR6,A/D Converter Sequence 0~7 Data Register"
bitfld.long 0x1C 31. "TRGINFO7,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
bitfld.long 0x1C 30. "TRGINFO6,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
newline
bitfld.long 0x1C 29. "TRGINFO5,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
bitfld.long 0x1C 28. "TRGINFO4,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
newline
bitfld.long 0x1C 27. "TRGINFO3,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
bitfld.long 0x1C 26. "TRGINFO2,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
newline
bitfld.long 0x1C 25. "TRGINFO1,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
bitfld.long 0x1C 24. "TRGINFO0,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
newline
hexmask.long.byte 0x1C 16.--20. 1. "ACH,ADC Channel Information"
hexmask.long.word 0x1C 4.--15. 1. "ADDATA,ADC Input data"
line.long 0x20 "DR7,A/D Converter Sequence 0~7 Data Register"
bitfld.long 0x20 31. "TRGINFO7,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
bitfld.long 0x20 30. "TRGINFO6,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
newline
bitfld.long 0x20 29. "TRGINFO5,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
bitfld.long 0x20 28. "TRGINFO4,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
newline
bitfld.long 0x20 27. "TRGINFO3,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
bitfld.long 0x20 26. "TRGINFO2,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
newline
bitfld.long 0x20 25. "TRGINFO1,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
bitfld.long 0x20 24. "TRGINFO0,ADC Trigger Information(ADC Trigger Information is Trigger source captured at EOC time.)" "0,1"
newline
hexmask.long.byte 0x20 16.--20. 1. "ACH,ADC Channel Information"
hexmask.long.word 0x20 4.--15. 1. "ADDATA,ADC Input data"
group.long 0x70++0x3
line.long 0x0 "CMPR,A/D Converter Channel Compare Register"
bitfld.long 0x0 24. "COMPIEN,Compare Interrupt Enable bit" "0,1"
bitfld.long 0x0 23. "COMPEN,Compare Operation Enable bit" "0,1"
newline
bitfld.long 0x0 21. "LTE,AD Conversion Value Output Timing Setting" "0,1"
hexmask.long.byte 0x0 16.--20. 1. "CCH,Compare Channel"
newline
hexmask.long.word 0x0 4.--15. 1. "CVAL,Compare Value Bit"
endif
tree.end
sif (cpuis("A31G31*"))
tree "ADPCM (ADPCM Decoder)"
base ad:0x40004700
group.long 0x0++0xF
line.long 0x0 "DECCR,A/D ADPCM Decoder Control Register"
bitfld.long 0x0 9. "SPIEN,ADPCM Interrupt Enable" "0,1"
bitfld.long 0x0 8. "DFEIE,Decoder FIFO Empty Interrupt Enable" "0,1"
bitfld.long 0x0 7. "DMIE,Decoder Match Interrupt Enable" "0,1"
bitfld.long 0x0 6. "DFFF,Decoder FIFO Full Flag" "0,1"
bitfld.long 0x0 5. "DECEN,Decoder Block Enable" "0,1"
bitfld.long 0x0 4. "DIVS,Decoder Initial Value Setting" "0,1"
bitfld.long 0x0 3. "DCEN,Decoder Counting Enable" "0,1"
bitfld.long 0x0 0.--2. "DCLKS,Decoder Clock Select (fx/(2^(DCLKS+1)))" "0,1,2,3,4,5,6,7"
line.long 0x4 "DFIFOR,ADPCM Decoder FIFO Register"
hexmask.long.byte 0x4 0.--7. 1. "DFIFOR,Decoder FIFO Data. The data goes to the decoder FIFO (8-bytes length) if data are written in this register."
line.long 0x8 "DECDR,ADPCM Decoder Sampling Frequency Data Register"
hexmask.long.byte 0x8 0.--7. 1. "DECDR,Decoder Sampling Frequency Set Register. The sampling time (ts) is 1/(sampling frequency). The voice data get out every ts and interpolation data get out between every the voice data."
line.long 0xC "DBDLR,ADPCM Decoder Bundle Register"
hexmask.long.byte 0xC 0.--7. 1. "DBDLR,Decoder Bundle Size. This value should be greater than 6. If this value is '00' the bundle size is 256-bytes. This value should be same with encoder's bundle size"
rgroup.long 0x10++0x7
line.long 0x0 "DODRL,ADPCM Decoder Result Output Low Register"
hexmask.long.byte 0x0 0.--7. 1. "DODRL,Decoder Result Output Data Low Byte."
line.long 0x4 "DODRH,ADPCM Decoder Result Output High Register"
hexmask.long.byte 0x4 0.--7. 1. "DODRH,Decoder Result Output Data High Byte"
group.long 0x18++0x2F
line.long 0x0 "FAFLAG,ADPCM Interrupt Flag Register"
bitfld.long 0x0 7. "SFSTOP,Stop the Serial Flash Interface for reading voice data" "0,1"
bitfld.long 0x0 3. "VPEDIFR,When voice prompt end interrupt occurs this bit becomes '1'. The flag is cleared only by writing a '0' to the bit. So the flag should be cleared by software. Write '1' has no effect." "0,1"
bitfld.long 0x0 2. "VPTBLIFR,When voice prompt table data receive end interrupt occurs this bit becomes '1'. The flag is cleared only by writing a '0' to the bit. So the flag should be cleared by software. Write '1' has no effect." "0,1"
bitfld.long 0x0 1. "DFEIFR,When FADPCM decoder FIFO empty interrupt occurs this bit becomes '1'. The flag is cleared only by writing a '0' to the bit. So the flag should be cleared by software. Write '1' has no effect." "0,1"
bitfld.long 0x0 0. "DMIFR,When FADPCM decoder match interrupt occurs this bit becomes '1'. The flag is cleared only by writing a '0' to the bit. So the flag should be cleared by software. Write '1' has no effect." "0,1"
line.long 0x4 "VPCR,Voice Prompt Control Register"
bitfld.long 0x4 7. "VPEDIE,Voice Prompt End Interrupt Enable" "0,1"
bitfld.long 0x4 6. "VPTBLIE,Voice Prompt Table Data Receive End Interrupt Enable" "0,1"
bitfld.long 0x4 5. "SFRDST,Serial Flash Data Read Start Signal" "0,1"
bitfld.long 0x4 4. "SPICSS,Enable SPI interface for serial flash" "0,1"
bitfld.long 0x4 3. "VPSDEC,Voice Prompt Size Register Decrement Enable" "0,1"
bitfld.long 0x4 2. "DTRS,Enable Data Transfer from SPI" "0,1"
bitfld.long 0x4 0.--1. "ATRIGS,Automatically Read Trigger Selection for SPI" "0,1,2,3"
line.long 0x8 "SFDDNO,Serial Flash Dummy and Data Number"
hexmask.long.byte 0x8 4.--7. 1. "DUMY,The number of dummy for serial flash interface. The number of dummy is (n). Where n = 0 1 2 ----- and 15."
bitfld.long 0x8 0.--2. "RDNO,The number of data to read from a serial flash. The number of data to read is (n+1). Where n = 0 1 2 ----- and 7." "0,1,2,3,4,5,6,7"
line.long 0xC "SFCMD,Serial Flash Command Register"
hexmask.long.byte 0xC 0.--7. 1. "SFCMD,Serial Flash Command Data."
line.long 0x10 "VPADDR1,Voice Prompt Address Register 1"
hexmask.long.byte 0x10 0.--7. 1. "VPAR,Voice Prompt Address MSB-byte."
line.long 0x14 "VPADDR2,Voice Prompt Address Register 2"
hexmask.long.byte 0x14 0.--7. 1. "VPAR,Voice Prompt Address Mid-byte."
line.long 0x18 "VPADDR3,Voice Prompt Address Register 3"
hexmask.long.byte 0x18 0.--7. 1. "VPAR,Voice Prompt Address LSB-byte."
line.long 0x1C "VPSIZE1,Voice Prompt Size Register 1"
hexmask.long.byte 0x1C 0.--7. 1. "VPSZ,Voice Prompt Size MSB-byte."
line.long 0x20 "VPSIZE2,Voice Prompt Size Register 2"
hexmask.long.byte 0x20 0.--7. 1. "VPSZ,Voice Prompt Size Mid-byte."
line.long 0x24 "VPSIZE3,Voice Prompt Size Register 3"
hexmask.long.byte 0x24 0.--7. 1. "VPSZ,Voice Prompt Size LSB-byte."
line.long 0x28 "VPINF1,Voice Prompt Inform Register 1"
hexmask.long.byte 0x28 0.--7. 1. "VPINF,Voice Prompt Inform High-byte."
line.long 0x2C "VPINF2,Voice Prompt Inform Register 2"
hexmask.long.byte 0x2C 0.--7. 1. "VPINF,Voice Prompt Inform Low-byte."
group.long 0x50++0xB
line.long 0x0 "SPICR,SPI Control Register"
bitfld.long 0x0 7. "SPIEN,This bit controls the SPI operation" "0,1"
bitfld.long 0x0 6. "FLSB,This bit selects the data transmission sequence" "0,1"
bitfld.long 0x0 5. "SPIMS,This bit selects whether Master or Slave mode" "0,1"
bitfld.long 0x0 4. "CPOL,This two bits control the serial clock (SCK) mode." "0,1"
bitfld.long 0x0 3. "CPHA,This two bits control the serial clock (SCK) mode." "0,1"
bitfld.long 0x0 2. "SPIDSCR,These three bits select the SCK3 rate of the device configured as a master. When DSCR bit is written one SCK3 will be doubled in master mode." "0,1"
bitfld.long 0x0 0.--1. "SPISCR,These three bits select the SCK3 rate of the device configured as a master. When DSCR bit is written one SCK3 will be doubled in master mode." "0,1,2,3"
line.long 0x4 "SPIDR,SPI Data Register"
bitfld.long 0x4 7. "SPIDR,SPI Data" "0,1"
line.long 0x8 "SPISR,SPI Status Register"
bitfld.long 0x8 7. "SPIIFR,When SPI Interrupt occurs this bit becomes '1'. IF SPI interrupt is enable this bit is auto cleared by INT_ACK signal. And if SPI Interrupt is disable this bit is cleared when the status register SPISR is read and then access (read/write) the.." "0,1"
bitfld.long 0x8 6. "WCOL,This bit is set if any data are written to the data register SPIDR during transfer. This bit is cleared when the status register SPISR is read and then access (read/write) the data register SPIDR" "0,1"
bitfld.long 0x8 5. "SS_HIGH,When the SS pin is configured as input if 'HIGH' signal comes into the pin this flag bit will be set." "0,1"
bitfld.long 0x8 3. "FXCH,SPI port function exchange control bit." "0,1"
bitfld.long 0x8 2. "SPISSEN,This bit controls the SS pin operation" "0,1"
tree.end
tree "LCD (LCD Driver)"
base ad:0x40005000
group.long 0x0++0x7
line.long 0x0 "CR,LCD Driver Control Register"
bitfld.long 0x0 6.--7. "IRSEL,Internal LCD Bias Dividing Resistor Selection bits" "0: RLCD3: 105/105/80[kohm] @(1/2)/(1/3)/(1/4) bias,1: RLCD1: 10/10/10[kohm] @(1/2)/(1/3)/(1/4) bias,2: RLCD2: 66/66/50[kohm] @(1/2)/(1/3)/(1/4) bias,3: RLCD4: 320/320/240[kohm] @(1/2)/(1/3)/(1/4) bias"
bitfld.long 0x0 3.--5. "DBS,LCD Duty and Bias Selection bits" "0: 1/8 duty 1/4 bias,1: 1/6 duty 1/4 bias,2: 1/5 duty 1/3 bias,3: 1/4 duty 1/3 bias,4: 1/3 duty 1/3 bias,5: 1/3 duty 1/2 bias,?,?"
bitfld.long 0x0 1.--2. "LCLK,LCD Clock Selection bits (When fLCD = 32.768kHz)" "0: 128Hz,1: 256Hz,2: 512Hz,3: 1024Hz"
newline
bitfld.long 0x0 0. "DISP,LCD Display Control bit" "0: Display off,1: Normal display on"
line.long 0x4 "BCCR,LCD Automatic Bias and Contrast Control Register. Notes: 1. The above LCD contrast step is based on 1/3 bias with 66kohm RLCD and on 1/4 bias with 50kohm RLCD 2. The 'LCD driver contrast control' is disabled during the LCDABC bit (LCD automatic.."
bitfld.long 0x4 12. "LCDABC,LCD Automatic Bias Control bit" "0: LCD automatic bias is off,1: LCD automatic bias is on"
bitfld.long 0x4 8.--10. "BMSEL,'Bias Mode A' fsTime Selection bits" "0: 'Bias Mode A' for 1-clock of fLCD,1: 'Bias Mode A' for 2-clock of fLCD,2: 'Bias Mode A' for 3-clock of fLCD,3: 'Bias Mode A' for 4-clock of fLCD,4: 'Bias Mode A' for 5-clock of fLCD,5: 'Bias Mode A' for 6-clock of fLCD,6: 'Bias Mode A' for 7-clock of fLCD,7: 'Bias Mode A' for 8-clock of fLCD"
bitfld.long 0x4 5. "LCTEN,LCD Driver Contrast Control bit" "0: Disable LCD driver contrast,1: Enable LCD driver contrast"
newline
hexmask.long.byte 0x4 0.--3. 1. "VLCD,VLC0 Voltage Control when the contrast is enabled"
group.long 0xC++0x3
line.long 0x0 "BSSR,LCD Bias Source Selection Register is 32-bit register."
bitfld.long 0x0 9. "LCDDR,LCD Driving Resistor for Bias Select" "0,1"
bitfld.long 0x0 8. "LCDEPEN,LCD External Bias Path Enable bit" "0,1"
bitfld.long 0x0 7. "VLC3EN,Extenal Bias VLC3 Enable bit" "0,1"
newline
bitfld.long 0x0 6. "VLC2EN,Extenal Bias VLC2 Enable bit" "0,1"
bitfld.long 0x0 5. "VLC1EN,Extenal Bias VLC1 Enable bit" "0,1"
bitfld.long 0x0 4. "VLC0EN,Extenal Bias VLC0 Enable bit" "0,1"
group.byte 0x10++0x1B
line.byte 0x0 "DR0,LCD Display Data Register 0"
line.byte 0x1 "DR1,LCD Display Data Register 1"
line.byte 0x2 "DR2,LCD Display Data Register 2"
line.byte 0x3 "DR3,LCD Display Data Register 3"
line.byte 0x4 "DR4,LCD Display Data Register 4"
line.byte 0x5 "DR5,LCD Display Data Register 5"
line.byte 0x6 "DR6,LCD Display Data Register 6"
line.byte 0x7 "DR7,LCD Display Data Register 7"
line.byte 0x8 "DR8,LCD Display Data Register 8"
line.byte 0x9 "DR9,LCD Display Data Register 9"
line.byte 0xA "DR10,LCD Display Data Register 10"
line.byte 0xB "DR11,LCD Display Data Register 11"
line.byte 0xC "DR12,LCD Display Data Register 12"
line.byte 0xD "DR13,LCD Display Data Register 13"
line.byte 0xE "DR14,LCD Display Data Register 14"
line.byte 0xF "DR15,LCD Display Data Register 15"
line.byte 0x10 "DR16,LCD Display Data Register 16"
line.byte 0x11 "DR17,LCD Display Data Register 17"
line.byte 0x12 "DR18,LCD Display Data Register 18"
line.byte 0x13 "DR19,LCD Display Data Register 19"
line.byte 0x14 "DR20,LCD Display Data Register 20"
line.byte 0x15 "DR21,LCD Display Data Register 21"
line.byte 0x16 "DR22,LCD Display Data Register 22"
line.byte 0x17 "DR23,LCD Display Data Register 23"
line.byte 0x18 "DR24,LCD Display Data Register 24"
line.byte 0x19 "DR25,LCD Display Data Register 25"
line.byte 0x1A "DR26,LCD Display Data Register 26"
line.byte 0x1B "DR27,LCD Display Data Register 27"
tree.end
tree "LED (LED Driver)"
base ad:0x40006000
group.long 0x0++0x3F
line.long 0x0 "COMOE,COM Output Enable Register"
bitfld.long 0x0 24.--26. "COMOE4,Port Mode Select4" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 16.--23. 1. "COMOE3,Port Mode Select3"
hexmask.long.byte 0x0 8.--15. 1. "COMOE2,Port Mode Select2"
hexmask.long.byte 0x0 0.--7. 1. "COMOE1,Port Mode Select1"
line.long 0x4 "SEGOE,SEG Output Enable Register"
bitfld.long 0x4 8.--10. "SEGOE2,Port Mode Select2" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 0.--7. 1. "SEGOE1,Port Mode Select1"
line.long 0x8 "PRESD,LED Prescaler Data Register"
hexmask.long.word 0x8 0.--15. 1. "PRESD,Pre-scale value of LED clock"
line.long 0xC "COMER,COM EnableRegister"
bitfld.long 0xC 26. "COM26,Only Selected COM of COM0 and COM26 is active." "0,1"
bitfld.long 0xC 25. "COM25,Only Selected COM of COM0 and COM26 is active." "0,1"
bitfld.long 0xC 24. "COM24,Only Selected COM of COM0 and COM26 is active." "0,1"
bitfld.long 0xC 23. "COM23,Only Selected COM of COM0 and COM26 is active." "0,1"
bitfld.long 0xC 22. "COM22,Only Selected COM of COM0 and COM26 is active." "0,1"
bitfld.long 0xC 21. "COM21,Only Selected COM of COM0 and COM26 is active." "0,1"
bitfld.long 0xC 20. "COM20,Only Selected COM of COM0 and COM26 is active." "0,1"
bitfld.long 0xC 19. "COM19,Only Selected COM of COM0 and COM26 is active." "0,1"
bitfld.long 0xC 18. "COM18,Only Selected COM of COM0 and COM26 is active." "0,1"
newline
bitfld.long 0xC 17. "COM17,Only Selected COM of COM0 and COM26 is active." "0,1"
bitfld.long 0xC 16. "COM16,Only Selected COM of COM0 and COM26 is active." "0,1"
bitfld.long 0xC 15. "COM15,Only Selected COM of COM0 and COM26 is active." "0,1"
bitfld.long 0xC 14. "COM14,Only Selected COM of COM0 and COM26 is active." "0,1"
bitfld.long 0xC 13. "COM13,Only Selected COM of COM0 and COM26 is active." "0,1"
bitfld.long 0xC 12. "COM12,Only Selected COM of COM0 and COM26 is active." "0,1"
bitfld.long 0xC 11. "COM11,Only Selected COM of COM0 and COM26 is active." "0,1"
bitfld.long 0xC 10. "COM10,Only Selected COM of COM0 and COM26 is active." "0,1"
bitfld.long 0xC 9. "COM9,Only Selected COM of COM0 and COM26 is active." "0,1"
newline
bitfld.long 0xC 8. "COM8,Only Selected COM of COM0 and COM26 is active." "0,1"
bitfld.long 0xC 7. "COM7,Only Selected COM of COM0 and COM26 is active." "0,1"
bitfld.long 0xC 6. "COM6,Only Selected COM of COM0 and COM26 is active." "0,1"
bitfld.long 0xC 5. "COM5,Only Selected COM of COM0 and COM26 is active." "0,1"
bitfld.long 0xC 4. "COM4,Only Selected COM of COM0 and COM26 is active." "0,1"
bitfld.long 0xC 3. "COM3,Only Selected COM of COM0 and COM26 is active." "0,1"
bitfld.long 0xC 2. "COM2,Only Selected COM of COM0 and COM26 is active." "0,1"
bitfld.long 0xC 1. "COM1,Only Selected COM of COM0 and COM26 is active." "0,1"
bitfld.long 0xC 0. "COM0,Only Selected COM of COM0 and COM26 is active." "0,1"
line.long 0x10 "COMPWID,COM Pulse Width Control Register"
hexmask.long.byte 0x10 0.--7. 1. "COMPWID,COM Pulse Width Control bits"
line.long 0x14 "DIMM0,COM Dimming Control Register0"
hexmask.long.byte 0x14 24.--31. 1. "COMDIMM3,COM3 Dimming Control bits"
hexmask.long.byte 0x14 16.--23. 1. "COMDIMM2,COM2 Dimming Control bits"
hexmask.long.byte 0x14 8.--15. 1. "COMDIMM1,COM1 Dimming Control bits"
hexmask.long.byte 0x14 0.--7. 1. "COMDIMM0,COM0 Dimming Control bits"
line.long 0x18 "DIMM1,COM Dimming Control Register1"
hexmask.long.byte 0x18 24.--31. 1. "COMDIMM7,COM7 Dimming Control bits"
hexmask.long.byte 0x18 16.--23. 1. "COMDIMM6,COM6 Dimming Control bits"
hexmask.long.byte 0x18 8.--15. 1. "COMDIMM5,COM5 Dimming Control bits"
hexmask.long.byte 0x18 0.--7. 1. "COMDIMM4,COM4 Dimming Control bits"
line.long 0x1C "DIMM2,COM Dimming Control Register2"
hexmask.long.byte 0x1C 24.--31. 1. "COMDIMM11,COM11 Dimming Control bits"
hexmask.long.byte 0x1C 16.--23. 1. "COMDIMM10,COM10 Dimming Control bits"
hexmask.long.byte 0x1C 8.--15. 1. "COMDIMM9,COM9 Dimming Control bits"
hexmask.long.byte 0x1C 0.--7. 1. "COMDIMM8,COM8 Dimming Control bits"
line.long 0x20 "DIMM3,COM Dimming Control Register3"
hexmask.long.byte 0x20 24.--31. 1. "COMDIMM15,COM15 Dimming Control bits"
hexmask.long.byte 0x20 16.--23. 1. "COMDIMM14,COM14 Dimming Control bits"
hexmask.long.byte 0x20 8.--15. 1. "COMDIMM13,COM13 Dimming Control bits"
hexmask.long.byte 0x20 0.--7. 1. "COMDIMM12,COM12 Dimming Control bits"
line.long 0x24 "DIMM4,COM Dimming Control Register4"
hexmask.long.byte 0x24 24.--31. 1. "COMDIMM19,COM19 Dimming Control bits"
hexmask.long.byte 0x24 16.--23. 1. "COMDIMM18,COM18 Dimming Control bits"
hexmask.long.byte 0x24 8.--15. 1. "COMDIMM17,COM17 Dimming Control bits"
hexmask.long.byte 0x24 0.--7. 1. "COMDIMM16,COM16 Dimming Control bits"
line.long 0x28 "DIMM5,COM Dimming Control Register5"
hexmask.long.byte 0x28 24.--31. 1. "COMDIMM23,COM23 Dimming Control bits"
hexmask.long.byte 0x28 16.--23. 1. "COMDIMM22,COM22 Dimming Control bits"
hexmask.long.byte 0x28 8.--15. 1. "COMDIMM21,COM21 Dimming Control bits"
hexmask.long.byte 0x28 0.--7. 1. "COMDIMM20,COM20 Dimming Control bits"
line.long 0x2C "DIMM6,COM Dimming Control Register0"
hexmask.long.byte 0x2C 16.--23. 1. "COMDIMM26,COM26 Dimming Control bits"
hexmask.long.byte 0x2C 8.--15. 1. "COMDIMM25,COM25 Dimming Control bits"
hexmask.long.byte 0x2C 0.--7. 1. "COMDIMM24,COM24 Dimming Control bits"
line.long 0x30 "STPD,LED STOP Duration Register"
hexmask.long.tbyte 0x30 0.--19. 1. "LEDSTPD,LED STOP Duration Register (since LED Start)"
line.long 0x34 "SR,LED STATUS Register"
bitfld.long 0x34 3. "MATCHF,Flag to occur when LEDSTPD reg match with counter" "0,1"
bitfld.long 0x34 2. "LED_INT,LED Interrupt Flag(in LED_INTE=1)" "0,1"
bitfld.long 0x34 1. "LED_INTE,LED Interrupt Enable" "0,1"
bitfld.long 0x34 0. "LED_ENDF,LED Operation End Flag" "0,1"
line.long 0x38 "CON2,LED Control Register2"
bitfld.long 0x38 4.--5. "COM_SEGN,COM & SEG Share Pin Select" "0,1,2,3"
bitfld.long 0x38 3. "OVERLAP,OVERLAP TIME Select" "0,1"
bitfld.long 0x38 0.--2. "OVERTS,OVERLAP TIME Select" "0,1,2,3,4,5,6,7"
line.long 0x3C "CON1,LED Control Register1"
bitfld.long 0x3C 2.--3. "MD,Mode Select" "0,1,2,3"
bitfld.long 0x3C 1. "LEDEN,LED Enable" "0,1"
bitfld.long 0x3C 0. "LEDST,LED START STOP Operation" "0,1"
tree.end
tree "TOUCH (Touch Sensor)"
base ad:0x40003600
rgroup.long 0x0++0x5F
line.long 0x0 "SUM_CH0,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x0 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
line.long 0x4 "SUM_CH1,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x4 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
line.long 0x8 "SUM_CH2,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x8 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
line.long 0xC "SUM_CH3,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0xC 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
line.long 0x10 "SUM_CH4,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x10 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
line.long 0x14 "SUM_CH5,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x14 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
line.long 0x18 "SUM_CH6,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x18 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
line.long 0x1C "SUM_CH7,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x1C 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
line.long 0x20 "SUM_CH8,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x20 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
line.long 0x24 "SUM_CH9,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x24 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
line.long 0x28 "SUM_CH10,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x28 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
line.long 0x2C "SUM_CH11,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x2C 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
line.long 0x30 "SUM_CH12,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x30 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
line.long 0x34 "SUM_CH13,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x34 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
line.long 0x38 "SUM_CH14,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x38 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
line.long 0x3C "SUM_CH15,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x3C 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
line.long 0x40 "SUM_CH16,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x40 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
line.long 0x44 "SUM_CH17,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x44 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
line.long 0x48 "SUM_CH18,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x48 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
line.long 0x4C "SUM_CH19,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x4C 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
line.long 0x50 "SUM_CH20,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x50 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
line.long 0x54 "SUM_CH21,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x54 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
line.long 0x58 "SUM_CH22,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x58 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
line.long 0x5C "SUM_CH23,Touch Sensor Channel 0~23 Sum Register"
hexmask.long.word 0x5C 0.--15. 1. "SUM_CH_DATA,Touch Sensor Channel n Sum or ADC Data"
group.long 0x60++0x5F
line.long 0x0 "SCO0,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x0 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x4 "SCO1,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x4 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x8 "SCO2,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x8 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0xC "SCO3,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0xC 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x10 "SCO4,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x10 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x14 "SCO5,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x14 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x18 "SCO6,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x18 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x1C "SCO7,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x1C 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x20 "SCO8,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x20 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x24 "SCO9,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x24 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x28 "SCO10,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x28 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x2C "SCO11,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x2C 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x30 "SCO12,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x30 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x34 "SCO13,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x34 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x38 "SCO14,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x38 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x3C "SCO15,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x3C 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x40 "SCO16,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x40 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x44 "SCO17,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x44 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x48 "SCO18,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x48 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x4C "SCO19,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x4C 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x50 "SCO20,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x50 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x54 "SCO21,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x54 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x58 "SCO22,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x58 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
line.long 0x5C "SCO23,Touch Sensor Offset Capacitor Selection Register for CH0~23"
hexmask.long.word 0x5C 0.--8. 1. "SCO,Touch Sensor Offset Capacitor Selection"
group.long 0x100++0xF
line.long 0x0 "CON,Touch Sensor Control Register"
bitfld.long 0x0 4. "OSC_EN,Oscillator Enable" "0,1"
bitfld.long 0x0 3. "BGR_EN,Band Gap Reference Enable" "0,1"
bitfld.long 0x0 2. "TS_IF,Touch Sensor Interrupt Flag" "0,1"
newline
bitfld.long 0x0 0. "TS_RUN,Touch Sensor Enable" "0,1"
line.long 0x4 "MODE,Touch Sensor Mode Register"
bitfld.long 0x4 7. "SREF,External Reference Offset Enable" "0: Disable,1: Enable"
bitfld.long 0x4 6. "SC_GAIN,Gain Calibration Capacitor Enable" "0: Gain Calibration Capacitor Disable,1: Gain Calibration Capacitor Enable"
bitfld.long 0x4 4.--5. "SAP,Touch Sensor Selection" "?,1: Touch Sensor mode Select,?,?"
newline
bitfld.long 0x4 0.--1. "PORT,Port Configuration During Inactive Status" "0: Input Floating,1: Output Low,?,?"
line.long 0x8 "SUM_CNT,Touch Sensor Sum Repeat Count Register"
hexmask.long.byte 0x8 0.--7. 1. "TS_SUM_CNT,Touch Sensor Sum Repeat Count"
line.long 0xC "CH_SEL,Touch Sensor Channel Selection Register"
bitfld.long 0xC 23. "CH23_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
bitfld.long 0xC 22. "CH22_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
bitfld.long 0xC 21. "CH21_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
newline
bitfld.long 0xC 20. "CH20_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
bitfld.long 0xC 19. "CH19_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
bitfld.long 0xC 18. "CH18_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
newline
bitfld.long 0xC 17. "CH17_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
bitfld.long 0xC 16. "CH16_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
bitfld.long 0xC 15. "CH15_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
newline
bitfld.long 0xC 14. "CH14_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
bitfld.long 0xC 13. "CH13_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
bitfld.long 0xC 12. "CH12_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
newline
bitfld.long 0xC 11. "CH11_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
bitfld.long 0xC 10. "CH10_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
bitfld.long 0xC 9. "CH9_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
newline
bitfld.long 0xC 8. "CH8_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
bitfld.long 0xC 7. "CH7_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
bitfld.long 0xC 6. "CH6_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
newline
bitfld.long 0xC 5. "CH5_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
bitfld.long 0xC 4. "CH4_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
bitfld.long 0xC 3. "CH3_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
newline
bitfld.long 0xC 2. "CH2_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
bitfld.long 0xC 1. "CH1_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
bitfld.long 0xC 0. "CH0_SEL,Touch Sensor Channel Selection Register" "0: Disable,1: Enable Touch Key"
group.long 0x114++0x47
line.long 0x0 "SLP_CR,Touch Sensor Low Pass Filter Control Register"
bitfld.long 0x0 4.--6. "SLP_C,Capacitor Trimming for Input Low Pass Filter" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 0.--3. 1. "SLP_R,Resistor Trimming for Input Low Pass Filter"
line.long 0x4 "ADC_CH_SEL,ADC Channel Selection Register"
bitfld.long 0x4 23. "CH23_SEL,ADC Channel Selection" "0: Disable,1: Enable"
bitfld.long 0x4 22. "CH22_SEL,ADC Channel Selection" "0: Disable,1: Enable"
bitfld.long 0x4 21. "CH21_SEL,ADC Channel Selection" "0: Disable,1: Enable"
newline
bitfld.long 0x4 20. "CH20_SEL,ADC Channel Selection" "0: Disable,1: Enable"
bitfld.long 0x4 19. "CH19_SEL,ADC Channel Selection" "0: Disable,1: Enable"
bitfld.long 0x4 18. "CH18_SEL,ADC Channel Selection" "0: Disable,1: Enable"
newline
bitfld.long 0x4 17. "CH17_SEL,ADC Channel Selection" "0: Disable,1: Enable"
bitfld.long 0x4 16. "CH16_SEL,ADC Channel Selection" "0: Disable,1: Enable"
bitfld.long 0x4 15. "CH15_SEL,ADC Channel Selection" "0: Disable,1: Enable"
newline
bitfld.long 0x4 14. "CH14_SEL,ADC Channel Selection" "0: Disable,1: Enable"
bitfld.long 0x4 13. "CH13_SEL,ADC Channel Selection" "0: Disable,1: Enable"
bitfld.long 0x4 12. "CH12_SEL,ADC Channel Selection" "0: Disable,1: Enable"
newline
bitfld.long 0x4 11. "CH11_SEL,ADC Channel Selection" "0: Disable,1: Enable"
bitfld.long 0x4 10. "CH10_SEL,ADC Channel Selection" "0: Disable,1: Enable"
bitfld.long 0x4 9. "CH9_SEL,ADC Channel Selection" "0: Disable,1: Enable"
newline
bitfld.long 0x4 8. "CH8_SEL,ADC Channel Selection" "0: Disable,1: Enable"
bitfld.long 0x4 7. "CH7_SEL,ADC Channel Selection" "0: Disable,1: Enable"
bitfld.long 0x4 6. "CH6_SEL,ADC Channel Selection" "0: Disable,1: Enable"
newline
bitfld.long 0x4 5. "CH5_SEL,ADC Channel Selection" "0: Disable,1: Enable"
bitfld.long 0x4 4. "CH4_SEL,ADC Channel Selection" "0: Disable,1: Enable"
bitfld.long 0x4 3. "CH3_SEL,ADC Channel Selection" "0: Disable,1: Enable"
newline
bitfld.long 0x4 2. "CH2_SEL,ADC Channel Selection" "0: Disable,1: Enable"
bitfld.long 0x4 1. "CH1_SEL,ADC Channel Selection" "0: Disable,1: Enable"
bitfld.long 0x4 0. "CH0_SEL,ADC Channel Selection" "0: Disable,1: Enable"
line.long 0x8 "INTEG_CNT,Touch Sensor Sensing Integration Count Register"
hexmask.long.byte 0x8 0.--7. 1. "TS_INTEG_CNT,Touch Sensor Sensing Integration Count"
line.long 0xC "FREQ_NUM,Touch Sensor Frequency Number Register"
hexmask.long.byte 0xC 0.--7. 1. "TS_FREQ_NUM,Touch Sensor Frequency Number"
line.long 0x10 "FREQ_DEL,Touch Sensor Frequency Delta Register"
hexmask.long.byte 0x10 0.--7. 1. "TS_FREQ_DEL,Touch Sensor Frequency Delta Register"
line.long 0x14 "CLK_CFG,Touch Sensor Clock Configuration Register"
bitfld.long 0x14 7. "ACLKSEL,ADC Clock Source Select" "0: Touch Sensor Clock,1: System MCU Clock"
bitfld.long 0x14 4.--6. "ACLKDIV,ADC Clock Divider" "0: OSCsys / 1,1: OSCsys / 2,?,?,?,?,?,?"
bitfld.long 0x14 3. "TSCLKOE,Divided Touch Sensor Clock Output Enable" "0: Clock Output Disable,1: Clock Output Enable"
newline
bitfld.long 0x14 0.--2. "TSCLKDIV,Touch Sensor Clock Divider" "0: OSCts / 1,1: OSCts / 2,?,?,?,?,?,?"
line.long 0x18 "TRIM_OSC,Touch Sensor RING Oscillator Trimming Selection Register"
hexmask.long.byte 0x18 0.--7. 1. "TRIM_OSC,Touch Sensor RING Oscillator Trimming Selection"
line.long 0x1C "TRIM_A_OSC,Touch Sensor RING Oscillator Trimming for ADC Register"
hexmask.long.byte 0x1C 0.--7. 1. "TRIM_A_OSC,Touch Sensor RING Oscillator Trimming for ADC"
line.long 0x20 "SCI,Touch Sensor Input Capacitor Selection Register"
hexmask.long.byte 0x20 4.--7. 1. "IBIAS_TRIM,BGR Current Bias Control"
bitfld.long 0x20 0.--2. "SCI,Touch Sensor Input Capacitor Selection" "0,1,2,3,4,5,6,7"
line.long 0x24 "SCC,Touch Sensor Conversion Capacitor Selection Register"
bitfld.long 0x24 0.--2. "SCC,Touch Sensor Conversion Capacitor Selection" "0,1,2,3,4,5,6,7"
line.long 0x28 "SVREF,Touch Sensor VREF Resistor Selection Register"
hexmask.long.byte 0x28 0.--3. 1. "SVREF,Touch Sensor VREF Resistor Selection"
line.long 0x2C "TAR,Touch Sensor Integration AMP Reset Register"
hexmask.long.byte 0x2C 0.--7. 1. "TAR,Touch Sensor Integration AMP Reset Register"
line.long 0x30 "TRST,Touch Sensor Reset time of Sensing Register"
hexmask.long.byte 0x30 0.--7. 1. "TRST,Touch Sensor Reset time of Sensing"
line.long 0x34 "TDRV,Touch Sensor Sample time of Sensing Register"
hexmask.long.byte 0x34 0.--7. 1. "TDRV,Touch Sensor Driving time of Sensing"
line.long 0x38 "TINT,Touch Sensor Integration time of Sensing Register"
hexmask.long.byte 0x38 0.--7. 1. "TINT,Touch Sensor Integration time of Sensing"
line.long 0x3C "TD,Touch Sensor Differential AMP Sampling Register"
hexmask.long.byte 0x3C 0.--7. 1. "TD,Touch Sensor Differential AMP Sampling"
line.long 0x40 "TWR,Touch Sensor Wait time Register"
hexmask.long.byte 0x40 0.--7. 1. "TWR,Touch Sensor Wait Time"
line.long 0x44 "TLED,LED stable time Register"
hexmask.long.byte 0x44 0.--7. 1. "TLED,LED stable Time"
tree.end
tree "UART (Universal Asynchronous Receiver/Transmitter)"
base ad:0x0
tree "UART0"
base ad:0x40004000
rgroup.long 0x0++0x3
line.long 0x0 "RBR,Receive Buffer Register"
hexmask.long.byte 0x0 0.--7. 1. "RBR,recevied/transmit data"
wgroup.long 0x0++0x3
line.long 0x0 "THR,Transmit Data Hold Register"
hexmask.long.byte 0x0 0.--7. 1. "THR,recevied/transmit data"
group.long 0x4++0x13
line.long 0x0 "IER,UART Interrupt Enable Register"
bitfld.long 0x0 5. "DTXIEN,DMA transmit done interrupt enable" "0,1"
bitfld.long 0x0 4. "DRXIEN,DMA Receiver line status interrupt enable" "0,1"
bitfld.long 0x0 2. "RLSIE,receiver line status interrupt enable" "0,1"
bitfld.long 0x0 1. "THREIE,Transmit holding register empty interrupt enable" "0,1"
bitfld.long 0x0 0. "DRIE,Data receive interrupt enable" "0,1"
line.long 0x4 "IIR,UART Interrupt ID Register"
bitfld.long 0x4 4. "TXE,Interrupt source ID" "0,1"
bitfld.long 0x4 1.--3. "IID,Interrupt source ID" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 0. "IPEN,Interrupt pending bit" "0,1"
line.long 0x8 "LCR,UART Line Control Register"
bitfld.long 0x8 6. "BREAK,BREAK" "0,1"
bitfld.long 0x8 5. "STICKP,STICK" "0,1"
bitfld.long 0x8 4. "PARITY,PARITY" "0,1"
bitfld.long 0x8 3. "PEN,parity bit transfer enable" "0,1"
bitfld.long 0x8 2. "STOPBIT,STOPBIT" "0,1"
bitfld.long 0x8 0.--1. "DLEN,Data length in one transfer word" "0,1,2,3"
line.long 0xC "DCR,UART Data Control Register"
bitfld.long 0xC 4. "LBON,Local loopback test mode enable" "0,1"
bitfld.long 0xC 3. "RXINV,Rx Data Inversion selection" "0,1"
bitfld.long 0xC 2. "TXINV,TX Data Inversion selection" "0,1"
line.long 0x10 "LSR,UART Line Status Register"
bitfld.long 0x10 6. "TEMT,Transmit empty" "0,1"
bitfld.long 0x10 5. "THRE,Transmit holding register empty" "0,1"
bitfld.long 0x10 4. "BI,break condition indication bit" "0,1"
bitfld.long 0x10 3. "FE,frame error" "0,1"
bitfld.long 0x10 2. "PE,parity error" "0,1"
bitfld.long 0x10 1. "OE,overrun error" "0,1"
bitfld.long 0x10 0. "DR,Data recevied" "0,1"
group.long 0x20++0x7
line.long 0x0 "BDR,Baud rate Divisor Latch Register"
hexmask.long.word 0x0 0.--15. 1. "BDR,baudrate setting"
line.long 0x4 "BFR,Baud rate Fraction Counter Register"
hexmask.long.byte 0x4 0.--7. 1. "BFR,Fraction counter value"
group.long 0x30++0x3
line.long 0x0 "IDTR,Inter-frame Delay Time Register"
bitfld.long 0x0 0.--2. "WAITVAL,wait time is decied by this value" "0,1,2,3,4,5,6,7"
tree.end
tree "UART1"
base ad:0x40004100
rgroup.long 0x0++0x3
line.long 0x0 "RBR,Receive Buffer Register"
hexmask.long.byte 0x0 0.--7. 1. "RBR,recevied/transmit data"
wgroup.long 0x0++0x3
line.long 0x0 "THR,Transmit Data Hold Register"
hexmask.long.byte 0x0 0.--7. 1. "THR,recevied/transmit data"
group.long 0x4++0x13
line.long 0x0 "IER,UART Interrupt Enable Register"
bitfld.long 0x0 5. "DTXIEN,DMA transmit done interrupt enable" "0,1"
bitfld.long 0x0 4. "DRXIEN,DMA Receiver line status interrupt enable" "0,1"
bitfld.long 0x0 2. "RLSIE,receiver line status interrupt enable" "0,1"
bitfld.long 0x0 1. "THREIE,Transmit holding register empty interrupt enable" "0,1"
bitfld.long 0x0 0. "DRIE,Data receive interrupt enable" "0,1"
line.long 0x4 "IIR,UART Interrupt ID Register"
bitfld.long 0x4 4. "TXE,Interrupt source ID" "0,1"
bitfld.long 0x4 1.--3. "IID,Interrupt source ID" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 0. "IPEN,Interrupt pending bit" "0,1"
line.long 0x8 "LCR,UART Line Control Register"
bitfld.long 0x8 6. "BREAK,BREAK" "0,1"
bitfld.long 0x8 5. "STICKP,STICK" "0,1"
bitfld.long 0x8 4. "PARITY,PARITY" "0,1"
bitfld.long 0x8 3. "PEN,parity bit transfer enable" "0,1"
bitfld.long 0x8 2. "STOPBIT,STOPBIT" "0,1"
bitfld.long 0x8 0.--1. "DLEN,Data length in one transfer word" "0,1,2,3"
line.long 0xC "DCR,UART Data Control Register"
bitfld.long 0xC 4. "LBON,Local loopback test mode enable" "0,1"
bitfld.long 0xC 3. "RXINV,Rx Data Inversion selection" "0,1"
bitfld.long 0xC 2. "TXINV,TX Data Inversion selection" "0,1"
line.long 0x10 "LSR,UART Line Status Register"
bitfld.long 0x10 6. "TEMT,Transmit empty" "0,1"
bitfld.long 0x10 5. "THRE,Transmit holding register empty" "0,1"
bitfld.long 0x10 4. "BI,break condition indication bit" "0,1"
bitfld.long 0x10 3. "FE,frame error" "0,1"
bitfld.long 0x10 2. "PE,parity error" "0,1"
bitfld.long 0x10 1. "OE,overrun error" "0,1"
bitfld.long 0x10 0. "DR,Data recevied" "0,1"
group.long 0x20++0x7
line.long 0x0 "BDR,Baud rate Divisor Latch Register"
hexmask.long.word 0x0 0.--15. 1. "BDR,baudrate setting"
line.long 0x4 "BFR,Baud rate Fraction Counter Register"
hexmask.long.byte 0x4 0.--7. 1. "BFR,Fraction counter value"
group.long 0x30++0x3
line.long 0x0 "IDTR,Inter-frame Delay Time Register"
bitfld.long 0x0 0.--2. "WAITVAL,wait time is decied by this value" "0,1,2,3,4,5,6,7"
tree.end
tree.end
endif
tree "CMP (Comparator)"
base ad:0x40003420
sif (cpuis("A31G31*"))
group.long 0x0++0x7
line.long 0x0 "CMP0CR,Comparator 0 Control Register"
bitfld.long 0x0 20. "HYSEN0,Comparator Hysteresis Enable" "0: Disable Hysteresis,1: Enable Hysteresis"
bitfld.long 0x0 16. "HYSSEL0,Comparator Hysteresis Select" "0,1"
newline
bitfld.long 0x0 12. "CMP0EN,Comparator Enable bits" "0: Disable Comparator,1: Enable Comparator"
bitfld.long 0x0 4.--5. "C0INNSEL,Comparator Reference(input -) Selection bit" "0: CREF0,1: BGR 1V,?,?"
newline
bitfld.long 0x0 0.--1. "C0INPSEL,Comparator Input(input -) Selection bit" "0: CP0,1: CP1B,?,?"
line.long 0x4 "CMP1CR,Comparator 1 Control Register"
bitfld.long 0x4 20. "HYSEN1,Comparator Hysteresis Enable" "0: Disable Hysteresis,1: Enable Hysteresis"
bitfld.long 0x4 16. "HYSSEL1,Comparator Hysteresis Select" "0,1"
newline
bitfld.long 0x4 12. "CMP1EN,Comparator Enable bits" "0: Disable Comparator,1: Enable Comparator"
bitfld.long 0x4 4.--5. "C1INNSEL,Comparator Reference(input -) Selection bit" "0: CREF1,1: BGR 1V,?,?"
newline
bitfld.long 0x4 0.--1. "C0INPSEL,Comparator Input(input -) Selection bit" "0: CP1A,1: CP1B,?,?"
group.long 0x10++0xB
line.long 0x0 "DBNC,Comparator Debounce Register"
hexmask.long.word 0x0 16.--31. 1. "DBINCTB,Debounce time base counter"
hexmask.long.byte 0x0 4.--7. 1. "C1DBNC,Debounce shift Selection"
newline
hexmask.long.byte 0x0 0.--3. 1. "C0DBNC,Debounce shift Selection"
line.long 0x4 "ICON,Comparator Interrupt Control Register"
bitfld.long 0x4 13. "TPOL1,Comparator Trigger output polarity(to trigger other IP)" "0: output normal,1: output inverted"
bitfld.long 0x4 12. "TPOL0,Comparator Trigger output polarity(to trigger other IP)" "0: output normal,1: output inverted"
newline
bitfld.long 0x4 9. "IPOL1,Comparator 1 interrupt polarity(level mode)" "0: interrupt at comparator out high,1: interrupt at comparator out low"
bitfld.long 0x4 8. "IPOL0,Comparator 0 interrupt polarity(level mode)" "0: interrupt at comparator out high,1: interrupt at comparator out low"
newline
bitfld.long 0x4 2.--3. "C1IMODE,Comparator 1 Interrupt Flag bit." "0: level interrupt,1: rising edge interrupt,?,?"
bitfld.long 0x4 0.--1. "C0IMODE,Comparator 0 Interrupt Flag bit." "0: level interrupt,1: rising edge interrupt,?,?"
line.long 0x8 "IEN,Comparator Interrupt Enable Register"
bitfld.long 0x8 1. "C1IEN,Comparator 1 Enable" "0: Disable,1: Enable"
bitfld.long 0x8 0. "C0IEN,Comparator 0 Enable" "0: Disable,1: Enable"
rgroup.long 0x1C++0x3
line.long 0x0 "IST,Comparator Interrupt Status Register"
bitfld.long 0x0 1. "C1IRQ,Comparator 1 interrupt Status" "0: No Comparator Interrupt,1: Comparator Interrupt asserted"
bitfld.long 0x0 0. "C0IRQ,Comparator 0 interrupt Status" "0: No Comparator Interrupt,1: Comparator Interrupt asserted"
group.long 0x20++0x3
line.long 0x0 "ICLR,Comparator Interrupt Clear Register"
bitfld.long 0x0 1. "C1ICLR,Comparator 1 Interrupt Clear (write '1' to clear C1IRQ)" "0,1"
bitfld.long 0x0 0. "C0ICLR,Comparator 0 Interrupt Clear (write '1' to clear C0IRQ)" "0,1"
endif
sif (cpuis("A31G32*"))
group.long 0x0++0x7
line.long 0x0 "COMP0CR,Comparator 0 Control Register"
bitfld.long 0x0 25. "COMPREFEN,Comparator internal reference voltage enable" "0: Disable internal reference voltage,1: Enable internal reference voltage"
bitfld.long 0x0 24. "WINDEN,Window mode Enable" "0: Disable Window mode,1: Enable Window mode"
newline
bitfld.long 0x0 20.--21. "MODE0,Comparator 0 mode Selection" "0: UL power,1: Low power,2: Medium power,3: High speed"
bitfld.long 0x0 16.--17. "HYSSEL,Comparator 0 Hysteresis mode selection" "0: Off,1: Low,2: Medium,3: High"
newline
bitfld.long 0x0 12. "COMP0EN,Comparator 0 Enable" "0: Disable Comparator,1: Enable Comparator"
bitfld.long 0x0 4.--6. "INNSEL0,Comparator 0 Reference(input -) Selection" "0,1,2,3,4,5,6,7"
line.long 0x4 "COMP1CR,Comparator 1 Control Register"
bitfld.long 0x4 20.--21. "MODE1,Comparator 1 mode Selection" "0: UL power,1: Low power,2: Medium power,3: High speed"
bitfld.long 0x4 16.--17. "HYSSEL1,Comparator 1 Hysteresis mode selection" "0: Off,1: Low,2: Medium,3: High"
newline
bitfld.long 0x4 12. "COMP1EN,Comparator 1 Enable" "0: Disable Comparator,1: Enable Comparator"
bitfld.long 0x4 4.--6. "INNSEL1,Comparator 0 Reference(input -) Selection" "0,1,2,3,4,5,6,7"
group.long 0x10++0xB
line.long 0x0 "COMPDBNC,Comparator Debounce Register"
hexmask.long.word 0x0 16.--31. 1. "DBINCTB,Debounce time base counter"
bitfld.long 0x0 8. "DBCSEL,Debounce clock selection" "0: System clock,1: LSI500kHz"
newline
hexmask.long.byte 0x0 4.--7. 1. "C1DBNC,Debounce shift Selection"
hexmask.long.byte 0x0 0.--3. 1. "C0DBNC,Debounce shift Selection"
line.long 0x4 "COMPICON,Comparator Interrupt Control Register"
bitfld.long 0x4 13. "TPOL1,Comparator Trigger output polarity(to trigger other IP)" "0: output normal,1: output inverted"
bitfld.long 0x4 12. "TPOL0,Comparator Trigger output polarity(to trigger other IP)" "0: output normal,1: output inverted"
newline
bitfld.long 0x4 9. "IPOL1,Comparator 1 interrupt polarity(level mode)" "0: interrupt at comparator out high,1: interrupt at comparator out low"
bitfld.long 0x4 8. "IPOL0,Comparator 0 interrupt polarity(level mode)" "0: interrupt at comparator out high,1: interrupt at comparator out low"
newline
bitfld.long 0x4 2.--3. "C1IMODE,Comparator 1 Interrupt Flag bit." "0: level interrupt,1: rising edge interrupt,?,?"
bitfld.long 0x4 0.--1. "C0IMODE,Comparator 0 Interrupt Flag bit." "0: level interrupt,1: rising edge interrupt,?,?"
line.long 0x8 "COMPIEN,Comparator Interrupt Enable Register"
bitfld.long 0x8 1. "C1IEN,Comparator 1 Enable" "0: Disable,1: Enable"
bitfld.long 0x8 0. "C0IEN,Comparator 0 Enable" "0: Disable,1: Enable"
rgroup.long 0x1C++0x3
line.long 0x0 "COMPIST,Comparator Interrupt Status Register"
bitfld.long 0x0 1. "C1IRQ,Comparator 1 interrupt Status" "0: No Comparator Interrupt,1: Comparator Interrupt asserted"
bitfld.long 0x0 0. "C0IRQ,Comparator 0 interrupt Status" "0: No Comparator Interrupt,1: Comparator Interrupt asserted"
group.long 0x20++0x3
line.long 0x0 "COMPICLR,Comparator Interrupt Clear Register"
bitfld.long 0x0 1. "C1ICLR,Comparator 1 Interrupt Clear (write '1' to clear C1IRQ)" "0,1"
bitfld.long 0x0 0. "C0ICLR,Comparator 0 Interrupt Clear (write '1' to clear C0IRQ)" "0,1"
endif
tree.end
tree "CRC (Cyclic Redundancy Check and Checksum)"
base ad:0x40000300
group.long 0x0++0x7
line.long 0x0 "CR,CRC/Checksum Control Register. Notes: 1. The CRCRLT register and the CRC/Checksum block should be initialized by writing '1b' to the RLTCLR bit before a new CRC/Checksum calculation. 2. The CRCRUN bit should be set to '1b' last time after setting.."
bitfld.long 0x0 9. "CRCINTEN,CRC interrupt enable bit" "0,1"
bitfld.long 0x0 8. "CRCINTF,CRC interrupt flag bit" "0,1"
sif (cpuis("A31G31*"))
bitfld.long 0x0 7. "MODS,User/Auto Mode Selection bit" "0,1"
endif
bitfld.long 0x0 6. "RLTCLR,CRC/Checksum Result Data Register (CRCRLT) Initialization bit" "0,1"
bitfld.long 0x0 5. "MDSEL,CRC/Checksum Selection bit" "0,1"
bitfld.long 0x0 4. "POLYS,Polynomial Selection bit (CRC only)" "0,1"
bitfld.long 0x0 1. "FIRSTBS,First Shifted-in Selection bit (CRC only)" "0,1"
bitfld.long 0x0 0. "CRCRUN,CRC/Checksum Start Control and Busy bit" "0,1"
line.long 0x4 "IN,CRC/Checksum Input Data Register"
sif (cpuis("A31G32*"))
hexmask.long 0x4 0.--31. 1. "INDATA,CRC Input Data bits."
endif
rgroup.long 0x8++0x3
line.long 0x0 "RLT,CRC/Checksum Result Data Register"
sif (cpuis("A31G32*"))
hexmask.long.word 0x0 0.--15. 1. "RLTDATA,CRC Result Data bits."
endif
group.long 0xC++0x3
line.long 0x0 "INIT,CRC/Checksum Initial Data Register"
sif (cpuis("A31G32*"))
hexmask.long.word 0x0 0.--15. 1. "INIDATA,CRC Initial Data bits."
endif
tree.end
sif (cpuis("A31G31*"))
base ad:0x40003450
elif (cpuis("A31G32*"))
base ad:0x40003500
endif
tree "DAC (12-bit D/A Converter)"
group.long 0x0++0x3
line.long 0x0 "DR,D/A Converter Data Register"
hexmask.long.word 0x0 0.--15. 1. "DACDR,D/A Converter Data (16-bit)"
rgroup.long 0x4++0x3
line.long 0x0 "BR,D/A Converter Buffer Register"
hexmask.long.word 0x0 0.--15. 1. "DACBR,D/A Converter Buffer Data (16-bit)"
group.long 0x8++0xB
line.long 0x0 "CR,D/A Converter Control Register"
sif (cpuis("A31G32*"))
bitfld.long 0x0 13. "DAC_OUT3_EN,DAC_OUT3 output enable" "0: Disable,1: Enable"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 12. "DAC_OUT2_EN,DAC_OUT2 output enable" "0: Disable,1: Enable"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 11. "DAC_OUT1_EN,DAC_OUT1 output enable" "0: Disable,1: Enable"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 10. "DAC_BUF_EN,DAC Reference Selection" "0: Disable,1: Enable"
endif
bitfld.long 0x0 8. "REFSEL,DAC Reference Selection" "0: AVDD,1: DAVREF Pin"
bitfld.long 0x0 7. "DACIE,Enable or Disable D/AC Interrupt" "0,1"
newline
bitfld.long 0x0 6. "DACIFR,When D/AC Interrupt occurs this bit becomes '1'. The flag is cleared only by writing a '0' to the bit. So the flag should be cleared by software. This interrupt is for a result that the DACDRH register automatically increments to '800xH' or.." "0,1"
bitfld.long 0x0 5. "ADATID,Automatically D/A Converter Data Increment/Decrement" "0,1"
bitfld.long 0x0 4. "DACBC,D/A Converter Buffer Clear" "0,1"
sif (cpuis("A31G31*"))
bitfld.long 0x0 3. "FADFEN,Decoder Result Output Data Fetch Enable" "0,1"
endif
bitfld.long 0x0 1.--2. "DACRLDS,D/A Converter Reload Selection. These bits select a reload signal to load data from D/AC data register to buffer." "0,1,2,3"
bitfld.long 0x0 0. "DACEN,D/A Converter Enable Bit" "0,1"
line.long 0x4 "PGSR,Programmable Gain Control Register"
sif (cpuis("A31G31*"))
hexmask.long.byte 0x4 0.--3. 1. "PSG,Programmable Gain Selection"
endif
sif (cpuis("A31G32*"))
hexmask.long.byte 0x4 0.--3. 1. "DACPGSR,Programmable Gain Selection"
endif
line.long 0x8 "OFSCR,D/A Converter Offset Control Register"
bitfld.long 0x8 7. "OFSEN,D/AC Offset Control Enable Bit" "0,1"
bitfld.long 0x8 6. "OFSDIR,D/AC Offset Direction Selection Bit" "0,1"
hexmask.long.byte 0x8 0.--3. 1. "OFS,D/AC Offset Value"
tree.end
tree "DMAC (Direct Memory Access Controller)"
base ad:0x0
tree "DMAC0"
base ad:0x40000400
group.long 0x0++0xF
line.long 0x0 "CR,DMA Channel n Control Register"
hexmask.long.word 0x0 16.--27. 1. "TRANSCNT,Number of DMA transfer remained"
hexmask.long.byte 0x0 8.--11. 1. "PERISEL,Peripheral selction"
newline
bitfld.long 0x0 2.--3. "SIZE,Bus transfer size." "0: DMA transfer is byte size transfer,1: DMA transfer is half word size transfer,?,?"
bitfld.long 0x0 1. "DIR,Select transfer direction." "0: Transfer direction is from memory to peripheral,1: Transfer direction is from peripheral to memory"
line.long 0x4 "SR,DMA Channel n Status Register"
bitfld.long 0x4 7. "EOT,End of transfer." "0: Data to be transferred is existing,1: All data is transferred"
bitfld.long 0x4 0. "DMAEN,DMA Enable" "0: DMA is in stop or hold state,1: DMA is running or enabled"
line.long 0x8 "PAR,DMA Channel n Peripheral Address"
hexmask.long.word 0x8 0.--15. 1. "PAR,Target Peripheral address of transmit buffer or receive buffer."
line.long 0xC "MAR,DMA Channel n Memory Address"
hexmask.long 0xC 0.--31. 1. "MAR,Target memory address of data transfer."
tree.end
tree "DMAC1"
base ad:0x40000410
group.long 0x0++0xF
line.long 0x0 "CR,DMA Channel n Control Register"
hexmask.long.word 0x0 16.--27. 1. "TRANSCNT,Number of DMA transfer remained"
hexmask.long.byte 0x0 8.--11. 1. "PERISEL,Peripheral selction"
newline
bitfld.long 0x0 2.--3. "SIZE,Bus transfer size." "0: DMA transfer is byte size transfer,1: DMA transfer is half word size transfer,?,?"
bitfld.long 0x0 1. "DIR,Select transfer direction." "0: Transfer direction is from memory to peripheral,1: Transfer direction is from peripheral to memory"
line.long 0x4 "SR,DMA Channel n Status Register"
bitfld.long 0x4 7. "EOT,End of transfer." "0: Data to be transferred is existing,1: All data is transferred"
bitfld.long 0x4 0. "DMAEN,DMA Enable" "0: DMA is in stop or hold state,1: DMA is running or enabled"
line.long 0x8 "PAR,DMA Channel n Peripheral Address"
hexmask.long.word 0x8 0.--15. 1. "PAR,Target Peripheral address of transmit buffer or receive buffer."
line.long 0xC "MAR,DMA Channel n Memory Address"
hexmask.long 0xC 0.--31. 1. "MAR,Target memory address of data transfer."
tree.end
tree "DMAC2"
base ad:0x40000420
group.long 0x0++0xF
line.long 0x0 "CR,DMA Channel n Control Register"
hexmask.long.word 0x0 16.--27. 1. "TRANSCNT,Number of DMA transfer remained"
hexmask.long.byte 0x0 8.--11. 1. "PERISEL,Peripheral selction"
newline
bitfld.long 0x0 2.--3. "SIZE,Bus transfer size." "0: DMA transfer is byte size transfer,1: DMA transfer is half word size transfer,?,?"
bitfld.long 0x0 1. "DIR,Select transfer direction." "0: Transfer direction is from memory to peripheral,1: Transfer direction is from peripheral to memory"
line.long 0x4 "SR,DMA Channel n Status Register"
bitfld.long 0x4 7. "EOT,End of transfer." "0: Data to be transferred is existing,1: All data is transferred"
bitfld.long 0x4 0. "DMAEN,DMA Enable" "0: DMA is in stop or hold state,1: DMA is running or enabled"
line.long 0x8 "PAR,DMA Channel n Peripheral Address"
hexmask.long.word 0x8 0.--15. 1. "PAR,Target Peripheral address of transmit buffer or receive buffer."
line.long 0xC "MAR,DMA Channel n Memory Address"
hexmask.long 0xC 0.--31. 1. "MAR,Target memory address of data transfer."
tree.end
tree "DMAC3"
base ad:0x40000430
group.long 0x0++0xF
line.long 0x0 "CR,DMA Channel n Control Register"
hexmask.long.word 0x0 16.--27. 1. "TRANSCNT,Number of DMA transfer remained"
hexmask.long.byte 0x0 8.--11. 1. "PERISEL,Peripheral selction"
newline
bitfld.long 0x0 2.--3. "SIZE,Bus transfer size." "0: DMA transfer is byte size transfer,1: DMA transfer is half word size transfer,?,?"
bitfld.long 0x0 1. "DIR,Select transfer direction." "0: Transfer direction is from memory to peripheral,1: Transfer direction is from peripheral to memory"
line.long 0x4 "SR,DMA Channel n Status Register"
bitfld.long 0x4 7. "EOT,End of transfer." "0: Data to be transferred is existing,1: All data is transferred"
bitfld.long 0x4 0. "DMAEN,DMA Enable" "0: DMA is in stop or hold state,1: DMA is running or enabled"
line.long 0x8 "PAR,DMA Channel n Peripheral Address"
hexmask.long.word 0x8 0.--15. 1. "PAR,Target Peripheral address of transmit buffer or receive buffer."
line.long 0xC "MAR,DMA Channel n Memory Address"
hexmask.long 0xC 0.--31. 1. "MAR,Target memory address of data transfer."
tree.end
tree.end
sif (cpuis("A31G32*"))
tree "EBI (Static Memory Controller)"
base ad:0x40006200
group.long 0x0++0xF
line.long 0x0 "SMIBCR0,Memory area configuration Register 0"
bitfld.long 0x0 30.--31. "IDLE,Insert IDLE cycle at memory access time" "0,1,2,3"
bitfld.long 0x0 26.--27. "PREIDL,Changing falling timing of RD and nUWR/nLWR" "0,1,2,3"
bitfld.long 0x0 23. "EWEN,Ignore/Enable external input nWAIT" "0,1"
bitfld.long 0x0 22. "EWP,nWAIT polarity is active low/high" "0,1"
bitfld.long 0x0 21. "IOE,0: Separated muxed Address/Data access" "0: Separated muxed Address/Data access,1: Enable muxed Address/Data access"
bitfld.long 0x0 20. "BLEN,Disable/Enable byte lane selection in case of 8bit memory organization" "0,1"
bitfld.long 0x0 18.--19. "AH,When accessing A/D mux I/O area 'AH' represents the time (the number of clock cycle) while the address is valid." "0,1,2,3"
bitfld.long 0x0 16.--17. "MWIDTH,External memory bus is 8bit/16bit width" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "NORMWAIT,It represents wait value to be used for memory read/write operation."
line.long 0x4 "SMIBCR1,Memory area configuration Register 1"
bitfld.long 0x4 30.--31. "IDLE,Insert IDLE cycle at memory access time" "0,1,2,3"
bitfld.long 0x4 26.--27. "PREIDL,Changing falling timing of RD and nUWR/nLWR" "0,1,2,3"
bitfld.long 0x4 23. "EWEN,Ignore/Enable external input nWAIT" "0,1"
bitfld.long 0x4 22. "EWP,nWAIT polarity is active low/high" "0,1"
bitfld.long 0x4 21. "IOE,0: Separated muxed Address/Data access" "0: Separated muxed Address/Data access,1: Enable muxed Address/Data access"
bitfld.long 0x4 20. "BLEN,Disable/Enable byte lane selection in case of 8bit memory organization" "0,1"
bitfld.long 0x4 18.--19. "AH,When accessing A/D mux I/O area 'AH' represents the time (the number of clock cycle) while the address is valid." "0,1,2,3"
bitfld.long 0x4 16.--17. "MWIDTH,External memory bus is 8bit/16bit width" "0,1,2,3"
hexmask.long.byte 0x4 0.--5. 1. "NORMWAIT,It represents wait value to be used for memory read/write operation."
line.long 0x8 "SMIBCR2,Memory area configuration Register 2"
bitfld.long 0x8 30.--31. "IDLE,Insert IDLE cycle at memory access time" "0,1,2,3"
bitfld.long 0x8 26.--27. "PREIDL,Changing falling timing of RD and nUWR/nLWR" "0,1,2,3"
bitfld.long 0x8 23. "EWEN,Ignore/Enable external input nWAIT" "0,1"
bitfld.long 0x8 22. "EWP,nWAIT polarity is active low/high" "0,1"
bitfld.long 0x8 21. "IOE,0: Separated muxed Address/Data access" "0: Separated muxed Address/Data access,1: Enable muxed Address/Data access"
bitfld.long 0x8 20. "BLEN,Disable/Enable byte lane selection in case of 8bit memory organization" "0,1"
bitfld.long 0x8 18.--19. "AH,When accessing A/D mux I/O area 'AH' represents the time (the number of clock cycle) while the address is valid." "0,1,2,3"
bitfld.long 0x8 16.--17. "MWIDTH,External memory bus is 8bit/16bit width" "0,1,2,3"
hexmask.long.byte 0x8 0.--5. 1. "NORMWAIT,It represents wait value to be used for memory read/write operation."
line.long 0xC "SMIBCR3,Memory area configuration Register 3"
bitfld.long 0xC 30.--31. "IDLE,Insert IDLE cycle at memory access time" "0,1,2,3"
bitfld.long 0xC 26.--27. "PREIDL,Changing falling timing of RD and nUWR/nLWR" "0,1,2,3"
bitfld.long 0xC 23. "EWEN,Ignore/Enable external input nWAIT" "0,1"
bitfld.long 0xC 22. "EWP,nWAIT polarity is active low/high" "0,1"
bitfld.long 0xC 21. "IOE,0: Separated muxed Address/Data access" "0: Separated muxed Address/Data access,1: Enable muxed Address/Data access"
bitfld.long 0xC 20. "BLEN,Disable/Enable byte lane selection in case of 8bit memory organization" "0,1"
bitfld.long 0xC 18.--19. "AH,When accessing A/D mux I/O area 'AH' represents the time (the number of clock cycle) while the address is valid." "0,1,2,3"
bitfld.long 0xC 16.--17. "MWIDTH,External memory bus is 8bit/16bit width" "0,1,2,3"
hexmask.long.byte 0xC 0.--5. 1. "NORMWAIT,It represents wait value to be used for memory read/write operation."
tree.end
tree "HSICMU (High Speed Internal Clock Management Unit)"
base ad:0x40002B00
group.long 0x0++0x7
line.long 0x0 "CR,High Speed Internal OSC Clock Management Unit Control Register"
bitfld.long 0x0 13. "SET_TRIMVALUE,The value of the trim register is applied to the high speed internal OSC" "0: No Action,1: The value of the trim register is applied to the.."
bitfld.long 0x0 12. "SYNC_START,Start synchronized timer" "0: No Action,1: Start synchronized timer"
newline
bitfld.long 0x0 11. "SET_TIMER,The value in the Reload register is written to the FERRCNT" "0: No Action,1: The value in the Reload register is written to.."
bitfld.long 0x0 10. "SW_SYNC,Generate Software SYNC event" "0: No Action,1: A software SYNC event is generate"
newline
bitfld.long 0x0 9. "AUTOTRIM_EN,Auto Trim Enable" "0: Auto trimming disable,1: Auto trimming enable"
bitfld.long 0x0 8. "FERRCNT_EN,Frequency Error Rate Counter Enable" "0: Frequency Error Rate Counter disable,1: Frequency Error Rate Counter enable"
newline
bitfld.long 0x0 4. "SYNCLVL_4_EN,ERROR LEVEL 4 Interrupt ( Flag ) Enable" "0: ERROR LEVEL 4 Interrupt,1: ERROR LEVEL 4 Interrupt"
bitfld.long 0x0 3. "SYNCLVL_3_EN,ERROR LEVEL 3 Interrupt ( Flag ) Enable" "0: ERROR LEVEL 3 Interrupt,1: ERROR LEVEL 3 Interrupt"
newline
bitfld.long 0x0 2. "SYNCLVL_2_EN,ERROR LEVEL 2 Interrupt ( Flag ) Enable" "0: ERROR LEVEL 2 Interrupt,1: ERROR LEVEL 2 Interrupt"
bitfld.long 0x0 1. "SYNCLVL_1_EN,ERROR LEVEL 1 Interrupt ( Flag ) Enable" "0: ERROR LEVEL 1 Interrupt,1: ERROR LEVEL 1 Interrupt"
newline
bitfld.long 0x0 0. "SYNCLVL_0_EN,ERROR LEVEL 0 Interrupt ( Flag ) Enable" "0: ERROR LEVEL 0 Interrupt,1: ERROR LEVEL 0 Interrupt"
line.long 0x4 "CFG,High Speed Internal OSC Clock Management Unit Config Register"
bitfld.long 0x4 30.--31. "SESYNCPOL,This bit is set and cleared by software to select the input polarity for the SYNC signal source." "0: Both edge,1: Rising edge,?,?"
bitfld.long 0x4 28.--29. "SYNCSRC,SYNC Signal Source Selection" "0: Capture Data Update when SOF is successfully..,1: Capture Data Update when SOF is successfully..,?,?"
newline
bitfld.long 0x4 27. "AC_EN,Auto Clear Enable" "0: No Action,1: Auto Clear Enable"
bitfld.long 0x4 24.--26. "SYNCDIV,SYNC Divider" "0: SYNC not divided,1: SYNC divided by 2,?,?,?,?,?,?"
newline
hexmask.long.byte 0x4 16.--23. 1. "FETHR,Frequency Error Rate Threshold Register"
hexmask.long.word 0x4 0.--15. 1. "RELOAD,Sync Timer Reload Value"
rgroup.long 0x8++0x3
line.long 0x0 "ISR,High Speed Internal OSC Clock Management Unit Interrupt & Status Register"
bitfld.long 0x0 15. "FECDIR,Frequency Error Capture Direction" "0: count under reload,1: count over reload"
bitfld.long 0x0 14. "SYNC_FLAG,SYNC_FLAG" "0,1"
newline
bitfld.long 0x0 13. "TRIMOVF,TRIM Over Flow" "0,1"
bitfld.long 0x0 12. "FECOVF,Frequency Error Capture Over Flow" "0,1"
newline
bitfld.long 0x0 4. "SYNCLVL_4,SYNCLVL_4" "0,1"
bitfld.long 0x0 3. "SYNCLVL_3,SYNCLVL_3" "0,1"
newline
bitfld.long 0x0 2. "SYNCLVL_2,SYNCLVL_2" "0,1"
bitfld.long 0x0 1. "SYNCLVL_1,SYNCLVL_1" "0,1"
newline
bitfld.long 0x0 0. "SYNCLVL_0,SYNCLVL_0" "0,1"
wgroup.long 0xC++0x3
line.long 0x0 "ICR,High Speed Internal OSC Clock Management Unit Interrupt & Status Clear Register"
bitfld.long 0x0 14. "SYNC_FLAG,SYNC_FLAG" "0,1"
bitfld.long 0x0 4. "SYNCLVL_4,SYNCLVL_4" "0,1"
newline
bitfld.long 0x0 3. "SYNCLVL_3,SYNCLVL_3" "0,1"
bitfld.long 0x0 2. "SYNCLVL_2,SYNCLVL_2" "0,1"
newline
bitfld.long 0x0 1. "SYNCLVL_1,SYNCLVL_1" "0,1"
bitfld.long 0x0 0. "SYNCLVL_0,SYNCLVL_0" "0,1"
group.long 0x10++0x3
line.long 0x0 "TRIM,High Speed Internal OSC Clock Management Unit TRIM Register"
hexmask.long.byte 0x0 0.--7. 1. "TRIM,TRIM Value"
rgroup.long 0x14++0x7
line.long 0x0 "ATRIM,High Speed Internal OSC Clock Management Unit Auto TRIM Register"
hexmask.long.byte 0x0 0.--7. 1. "ATRIM,Auto TRIM Value"
line.long 0x4 "CAP,High Speed Internal OSC Clock Management Unit Capture Register"
hexmask.long.word 0x4 0.--15. 1. "CAP,Capture Value"
tree.end
tree "RTC (Real-Time Clock)"
base ad:0x40006100
group.long 0x0++0x3
line.long 0x0 "RTCCR,RTC Control Register"
bitfld.long 0x0 31. "RTCEN,RTC clock input enable" "0,1"
bitfld.long 0x0 30. "RTCE,RTC counter run" "0,1"
bitfld.long 0x0 20. "AMPM,Hour system selection" "0,1"
bitfld.long 0x0 17.--19. "CT,Period selection of constant-period matching" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16. "RIFG,Constant-period matching flag" "0,1"
bitfld.long 0x0 15. "TSEN,Timestamp enable" "0,1"
bitfld.long 0x0 13.--14. "TS_EDGE_SEL,Timestamp event active edge selection" "0,1,2,3"
bitfld.long 0x0 12. "TSFG,Time stamp event flag" "0,1"
newline
bitfld.long 0x0 11. "WAIE,Alarm enable" "0,1"
bitfld.long 0x0 8. "WAFG,Alarm flag" "0,1"
bitfld.long 0x0 1. "RWST,RW mode status flag" "0,1"
bitfld.long 0x0 0. "RWAIT,RW mode set" "0,1"
group.long 0x8++0x43
line.long 0x0 "ERRCOR,Error Correction Register"
bitfld.long 0x0 31. "DEV,Setting of watch error correction timing." "0,1"
bitfld.long 0x0 30. "DIR,Setting of watch error correction direction" "0,1"
bitfld.long 0x0 28. "COREN,Enable watch error correction" "0,1"
hexmask.long.tbyte 0x0 0.--16. 1. "CORDATA,Setting of watch error correction data"
line.long 0x4 "SEC,Second Count Register"
hexmask.long.byte 0x4 0.--6. 1. "SEC,The SEC register is an 8-bit register that takes a value of 0 to 59 (decimal) and indicates the count value of"
line.long 0x8 "MIN,Minute Count Register"
hexmask.long.byte 0x8 0.--6. 1. "MIN,The MIN register is an 8-bit register that takes a value of 0 to 59 (decimal) and indicates the count value of minutes."
line.long 0xC "HOUR,Hour Count Register"
hexmask.long.byte 0xC 0.--5. 1. "HOUR,The HOUR register is an 8-bit register that takes a value of 00 to 23 or 01 to 12 and 21 to 32 (decimal) and"
line.long 0x10 "DAY,Day Count Register"
hexmask.long.byte 0x10 0.--5. 1. "DAY,The DAY register is an 8-bit register that takes a value of 1 to 31 (decimal) and indicates the count value of days."
line.long 0x14 "WEEK,Week Count Register"
bitfld.long 0x14 0.--2. "WEEK,The WEEK register is an 8-bit register that takes a value of 0 to 6 (decimal) and indicates the count value of" "0,1,2,3,4,5,6,7"
line.long 0x18 "MONTH,Month Count Register"
hexmask.long.byte 0x18 0.--4. 1. "MONTH,The MONTH register is an 8-bit register that takes a value of 1 to 12 (decimal) and indicates the count value of"
line.long 0x1C "YEAR,Year Count Register"
hexmask.long.byte 0x1C 0.--7. 1. "YEAR,The YEAR register is an 8-bit register that takes a value of 0 to 99 (decimal) and indicates the count value of years."
line.long 0x20 "ALARMWM,Alarm Register"
hexmask.long.byte 0x20 16.--22. 1. "ALARMWW,This register is used to set day of the week for the alarm. Each of the seven bits represents a day of the week so that duplicate days of the week can be selected."
hexmask.long.byte 0x20 8.--13. 1. "ALARMWH,This register is used to set hours of the alarm. Set a decimal value of 00 to 23 01 to 12 or 21 to 32 to this register according to AMPM in BCD code. If a value outside the range is set the alarm is not detected."
hexmask.long.byte 0x20 0.--6. 1. "ALARMWM,This register is used to set minutes of the alarm. Set a decimal value of 00 to 59 to this register in BCD code. If a value outside the range is set the alarm is not detected."
line.long 0x24 "SUBDR,Sub-second counter Compare Reigster"
hexmask.long.tbyte 0x24 0.--16. 1. "SUBDR,Sub-second counter Compare Reigster"
line.long 0x28 "TIME_TS,TimeStamp Time Reigster"
hexmask.long.byte 0x28 16.--23. 1. "HOUR_TS,HOUR stored when the timestamp event occurred"
hexmask.long.byte 0x28 8.--15. 1. "MIN_TS,MIN stored when the timestamp event occurred"
hexmask.long.byte 0x28 0.--7. 1. "SEC_TS,SEC stored when the timestamp event occurred"
line.long 0x2C "DATE_TS,TimeStamp Date Reigster"
hexmask.long.byte 0x2C 24.--31. 1. "YEAR_TS,YEAR stored when the timestamp event occurred"
hexmask.long.byte 0x2C 16.--23. 1. "MONTH_TS,MONTH stored when the timestamp event occurred"
hexmask.long.byte 0x2C 8.--15. 1. "WEEK_TS,WEEK stored when the timestamp event occurred"
hexmask.long.byte 0x2C 0.--7. 1. "DAY_TS,DAY stored when the timestamp event occurred"
line.long 0x30 "BKUPDR1,Backup Register 1"
hexmask.long 0x30 0.--31. 1. "BKUPDR,Backup Register"
line.long 0x34 "BKUPDR2,Backup Register 2"
hexmask.long 0x34 0.--31. 1. "BKUPDR,Backup Register"
line.long 0x38 "BKUPDR3,Backup Register 3"
hexmask.long 0x38 0.--31. 1. "BKUPDR,Backup Register"
line.long 0x3C "BKUPDR4,Backup Register 4"
hexmask.long 0x3C 0.--31. 1. "BKUPDR,Backup Register"
line.long 0x40 "RTCPFCR,RTC Pin Function Configuration Register"
bitfld.long 0x40 9.--10. "WKUPEN,PC13 wakeup event enable" "0,1,2,3"
bitfld.long 0x40 7. "PC15MODE,PC15 mode" "0,1"
bitfld.long 0x40 6. "PC15VALUE,PC15 value" "0,1"
bitfld.long 0x40 5. "PC14MODE,PC14 mode" "0,1"
bitfld.long 0x40 4. "PC14VALUE,PC14 value" "0,1"
bitfld.long 0x40 2.--3. "PC13MODE,PC13 mode" "0,1,2,3"
bitfld.long 0x40 1. "PC13VALUE,PC13 value" "0,1"
bitfld.long 0x40 0. "PC13WKUPEN,Wakeup pin enable" "0,1"
tree.end
tree "SPI (Serial Peripheral Interface)"
base ad:0x0
tree "SPI20"
base ad:0x40004C00
group.long 0x0++0x17
line.long 0x0 "RDR_TDR_DATA_Register,SPI Rx_Tx DATA REGISTER"
hexmask.long.tbyte 0x0 0.--16. 1. "TDR_RDR,TX_RX DATA REGISTER"
line.long 0x4 "CR,SPI Control Register"
bitfld.long 0x4 20. "TXBC,Tx buffer clear bit" "0,1"
bitfld.long 0x4 19. "RXBC,Rx buffer clear bit" "0,1"
bitfld.long 0x4 18. "TXDIE,DMA Tx Done Interrupt Enable bit." "0,1"
bitfld.long 0x4 17. "RXDIE,DMA Rx Done Interrupt Enable bit." "0,1"
bitfld.long 0x4 16. "SSCIE,SS Edge Change Interrupt Enable bit." "0,1"
bitfld.long 0x4 15. "TXIE,Transmit Interrupt Enable bit." "0,1"
bitfld.long 0x4 14. "RXIE,Receive Interrupt Enable bit." "0,1"
bitfld.long 0x4 13. "SSMOD,SS Auto/Manual output select bit." "0,1"
bitfld.long 0x4 12. "SSOUT,SS output signal select bit." "0,1"
bitfld.long 0x4 11. "LBE,Loop-back mode select bit in master mode." "0,1"
newline
bitfld.long 0x4 10. "SSMASK,SS signal masking bit in slave mode." "0,1"
bitfld.long 0x4 9. "SSMO,SS output signal select bit." "0,1"
bitfld.long 0x4 8. "SSPOL,SS output Polarity select bit." "0,1"
bitfld.long 0x4 5. "MS,Master/Slave select bit." "0,1"
bitfld.long 0x4 4. "MSBF,MSB/LSB Transmit select bit." "0,1"
bitfld.long 0x4 3. "CPHA,SPI Clock Phase bit." "0,1"
bitfld.long 0x4 2. "COPL,SPI Clock Polarity bit." "0,1"
bitfld.long 0x4 0.--1. "BITSZ,Transmit/Receive Data Bits select bit." "0,1,2,3"
line.long 0x8 "SR,SPI Status Register"
bitfld.long 0x8 9. "TXDMAF,DMA Transmit Operation Complete flag." "0,1"
bitfld.long 0x8 8. "RXDMAF,DMA Receive Operation Complete flag." "0,1"
bitfld.long 0x8 6. "SSDET,The rising or falling edge of SS signal Detect flag." "0,1"
bitfld.long 0x8 5. "SSON,SS signal Status flag." "0,1"
bitfld.long 0x8 4. "OVRF,Receive Overrun Error flag." "0,1"
bitfld.long 0x8 3. "UDRF,Transmit Underrun Error flag." "0,1"
rbitfld.long 0x8 2. "TXIDLE,Transmit/Receive Operation flag." "0,1"
rbitfld.long 0x8 1. "TRDY,Transmit buffer Empty flag." "0,1"
rbitfld.long 0x8 0. "RRDY,Receive buffer Ready flag." "0,1"
line.long 0xC "BR,SPI Baud Rate Register"
hexmask.long.word 0xC 0.--15. 1. "BR,Baud rate setting bits."
line.long 0x10 "EN,SPI Enable Register"
bitfld.long 0x10 0. "ENABLE,SPI Enable bit" "0,1"
line.long 0x14 "LR,SPI Delay Length Register"
hexmask.long.byte 0x14 16.--23. 1. "SPL,StoPLength value"
hexmask.long.byte 0x14 8.--15. 1. "BTL,BursTLength value"
hexmask.long.byte 0x14 0.--7. 1. "STL,STart Length value"
tree.end
tree "SPI21"
base ad:0x40004D00
group.long 0x0++0x17
line.long 0x0 "RDR_TDR_DATA_Register,SPI Rx_Tx DATA REGISTER"
hexmask.long.tbyte 0x0 0.--16. 1. "TDR_RDR,TX_RX DATA REGISTER"
line.long 0x4 "CR,SPI Control Register"
bitfld.long 0x4 20. "TXBC,Tx buffer clear bit" "0,1"
bitfld.long 0x4 19. "RXBC,Rx buffer clear bit" "0,1"
bitfld.long 0x4 18. "TXDIE,DMA Tx Done Interrupt Enable bit." "0,1"
bitfld.long 0x4 17. "RXDIE,DMA Rx Done Interrupt Enable bit." "0,1"
bitfld.long 0x4 16. "SSCIE,SS Edge Change Interrupt Enable bit." "0,1"
bitfld.long 0x4 15. "TXIE,Transmit Interrupt Enable bit." "0,1"
bitfld.long 0x4 14. "RXIE,Receive Interrupt Enable bit." "0,1"
bitfld.long 0x4 13. "SSMOD,SS Auto/Manual output select bit." "0,1"
bitfld.long 0x4 12. "SSOUT,SS output signal select bit." "0,1"
bitfld.long 0x4 11. "LBE,Loop-back mode select bit in master mode." "0,1"
newline
bitfld.long 0x4 10. "SSMASK,SS signal masking bit in slave mode." "0,1"
bitfld.long 0x4 9. "SSMO,SS output signal select bit." "0,1"
bitfld.long 0x4 8. "SSPOL,SS output Polarity select bit." "0,1"
bitfld.long 0x4 5. "MS,Master/Slave select bit." "0,1"
bitfld.long 0x4 4. "MSBF,MSB/LSB Transmit select bit." "0,1"
bitfld.long 0x4 3. "CPHA,SPI Clock Phase bit." "0,1"
bitfld.long 0x4 2. "COPL,SPI Clock Polarity bit." "0,1"
bitfld.long 0x4 0.--1. "BITSZ,Transmit/Receive Data Bits select bit." "0,1,2,3"
line.long 0x8 "SR,SPI Status Register"
bitfld.long 0x8 9. "TXDMAF,DMA Transmit Operation Complete flag." "0,1"
bitfld.long 0x8 8. "RXDMAF,DMA Receive Operation Complete flag." "0,1"
bitfld.long 0x8 6. "SSDET,The rising or falling edge of SS signal Detect flag." "0,1"
bitfld.long 0x8 5. "SSON,SS signal Status flag." "0,1"
bitfld.long 0x8 4. "OVRF,Receive Overrun Error flag." "0,1"
bitfld.long 0x8 3. "UDRF,Transmit Underrun Error flag." "0,1"
rbitfld.long 0x8 2. "TXIDLE,Transmit/Receive Operation flag." "0,1"
rbitfld.long 0x8 1. "TRDY,Transmit buffer Empty flag." "0,1"
rbitfld.long 0x8 0. "RRDY,Receive buffer Ready flag." "0,1"
line.long 0xC "BR,SPI Baud Rate Register"
hexmask.long.word 0xC 0.--15. 1. "BR,Baud rate setting bits."
line.long 0x10 "EN,SPI Enable Register"
bitfld.long 0x10 0. "ENABLE,SPI Enable bit" "0,1"
line.long 0x14 "LR,SPI Delay Length Register"
hexmask.long.byte 0x14 16.--23. 1. "SPL,StoPLength value"
hexmask.long.byte 0x14 8.--15. 1. "BTL,BursTLength value"
hexmask.long.byte 0x14 0.--7. 1. "STL,STart Length value"
tree.end
tree.end
tree "TEMP (Temperature Sensor)"
base ad:0x40006300
group.long 0x0++0x7
line.long 0x0 "TSENSECON,Temp Sensor Control Register"
bitfld.long 0x0 3. "TSSINTEN,Temp Sensor interrupt enable" "0: Temp sensor interrupt disabled,1: Temp sensor interrupt enabled"
bitfld.long 0x0 2. "TSSFLAG,Temp Sensor CNT match flag" "0,1"
bitfld.long 0x0 1. "TSSTART,Temp Sensor start" "0,1"
bitfld.long 0x0 0. "TSSEN,Temp Sensor enable" "0,1"
line.long 0x4 "TSREFPEROID,Temp Sensor Reference Clock Period Register"
hexmask.long.tbyte 0x4 0.--19. 1. "TSREFPERIOD,Temp Sensor Reference Clock Period Register"
rgroup.long 0x8++0x3
line.long 0x0 "TSSENSECNT,Temp Sensor Sense Clock Count Register"
hexmask.long.word 0x0 0.--15. 1. "TSSENSECNT,Temp Sensor Reference Count Register"
tree.end
endif
tree "FMC (Flash Memory Controller)"
base ad:0x40000100
group.long 0x4++0xF
line.long 0x0 "MR,Flash Memory Mode Select register"
hexmask.long.byte 0x0 0.--6. 1. "ACODE,Access Code."
line.long 0x4 "CR,Flash Memory Control register"
bitfld.long 0x4 24. "LOCKSEL,LOCK(read protection) access enable." "0,1"
bitfld.long 0x4 23. "SELFPGM,When this bit is set('1') PGM/ERS/HVEN will be cleared automatically after WRBUSY falling edge. It also enable CPU wait control when HVEN bit is set(1)" "0,1"
bitfld.long 0x4 12. "IFEN,Info(OTP1/2/3) block enable" "0,1"
bitfld.long 0x4 8. "BBLOCK,Boot Block(1st 4KB) protection enable/disable from Mass(bulk) erase" "0,1"
bitfld.long 0x4 7. "MAS,Mass(bulk) erase enable/disable" "0,1"
bitfld.long 0x4 6. "SECT4K,Sector 4K erase enable/disable" "0,1"
bitfld.long 0x4 5. "SECT1K,Sector 1K erase enable/disable" "0,1"
bitfld.long 0x4 4. "PMODE,PMODE enable/disable" "0,1"
bitfld.long 0x4 3. "WADCK,Program/Erase address data latch clock enable/disable" "0,1"
bitfld.long 0x4 2. "PGM,Program mode enable/disable" "0,1"
newline
bitfld.long 0x4 1. "ERS,Erase mode enable/disable" "0,1"
bitfld.long 0x4 0. "HVEN,High Voltage cycle enable/disable" "0,1"
line.long 0x8 "AR,Flash Memory Address register"
hexmask.long.word 0x8 0.--15. 1. "FADDR,Word(32-bit) base address : 64K-word address for 256KB Flash."
line.long 0xC "DR,Flash Memory Data register"
hexmask.long 0xC 0.--31. 1. "FDATA,Word size(32-bit) data"
group.long 0x18++0x3
line.long 0x0 "BUSY,Flash Write Busy Status Register"
bitfld.long 0x0 0. "WRBUSY,Write Busy status bit" "0,1"
group.long 0x20++0x3
line.long 0x0 "CRC,Flash CRC16 check value"
hexmask.long.word 0x0 0.--15. 1. "CRC16,CRC16 check value read register"
group.long 0x30++0x7
line.long 0x0 "CFG,Flash Memory Config Register"
hexmask.long.word 0x0 16.--31. 1. "WTIDKY,Write Identification Key. On writes write 0x7858 to these bits otherwise the write is ignored."
bitfld.long 0x0 8.--9. "WAIT,This bits only be written in AMBA mode and MSB 16-bit (bit [31:16]) must be 0x7858" "0: wait) /,1: wait) /,2: wait),3: wait)"
bitfld.long 0x0 7. "CRCINIT,When this bit is set('1') CRC register will be initialized" "0,1"
bitfld.long 0x0 6. "CRCEN,CRC16 enable" "0,1"
line.long 0x4 "WPROT,Write Protection Register"
hexmask.long 0x4 0.--31. 1. "WPROT,Write protection"
group.long 0x3C++0x3
line.long 0x0 "LOCK,Flash LOCK register"
sif (cpuis("A31G31*"))
hexmask.long.word 0x0 0.--15. 1. "RPROT,Read protection"
endif
sif (cpuis("A31G32*"))
hexmask.long.byte 0x0 0.--7. 1. "RPROT,Read protection"
endif
tree.end
tree "I2C (Inter-Integrated Circuit)"
base ad:0x0
tree "I2C0"
base ad:0x40004800
group.long 0x0++0x13
line.long 0x0 "CR,I2Cn Control Register"
sif (cpuis("A31G31*"))
bitfld.long 0x0 7. "I2CnEN,Activate I2Cn Block by supplying" "0,1"
bitfld.long 0x0 6. "TXDLYENBn,I2CnSDHR Register Control bit" "0,1"
bitfld.long 0x0 5. "I2CnIEN,I2Cn Interrupt Enable bit" "0,1"
bitfld.long 0x0 4. "I2CnIFLAG,I2Cn Interrupt Flag bit. This bit is cleared when write any values in the I2CnST register." "0,1"
endif
sif (cpuis("A31G32*"))
rbitfld.long 0x0 7. "I2CnIFLAG,Interrupt flag bit" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 6. "I2CnEN,Activate I2Cn Block ( by supplying clock)" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 5. "RESET,Initialize internal register of I2C" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 4. "I2CnIEN,I2Cn Interrupt Enable bit." "0,1"
newline
endif
bitfld.long 0x0 3. "ACKnEN,Controls ACK signal generation at ninth SCL period. Notes) ACK signal is output (SDA = 0) for the following 3 cases. Where x = 0 and 1. 1. When received address packet equals to SLAx[6:0] bits in I2CnSARx register. 2. When received address packet.." "0,1"
rbitfld.long 0x0 2. "IMASTERn,Represent Operation Mode of I2Cn" "0,1"
bitfld.long 0x0 1. "STOPCn,STOP Condition Generation When I2Cn is master." "0,1"
bitfld.long 0x0 0. "STARTCn,START Condition Generation When I2Cn is master." "0,1"
line.long 0x4 "ST,I2Cn Status Register"
bitfld.long 0x4 7. "GCALLn,This bit has different meaning depending on whether I2C is master or slave. When I2C is a master this bit represents whether it received AACK (address ACK) from slave." "0,1"
bitfld.long 0x4 6. "TENDn,This bit is set when 1-byte of data is transferred completely." "?,1: byte of data is transferred completely"
bitfld.long 0x4 5. "STOPDn,This bit is set when a STOP condition is detected." "0,1"
bitfld.long 0x4 4. "SSELn,This bit is set when I2C is addressed by other master." "0,1"
bitfld.long 0x4 3. "MLOSTn,This bit represents the result of bus arbitration in master mode." "0,1"
bitfld.long 0x4 2. "BUSYn,This bit reflects bus status." "0,1"
rbitfld.long 0x4 1. "TMODEn,This bit is used to indicate whether I2C is transmitter or receiver." "0,1"
bitfld.long 0x4 0. "RXACKn,This bit shows the state of ACK signal." "0,1"
line.long 0x8 "SAR1,I2Cn Slave Address Register 1"
hexmask.long.byte 0x8 1.--7. 1. "SLAn,These bits configure the slave address 0 in slave mode."
bitfld.long 0x8 0. "GCALLnEN,This bit decides whether I2Cn allows general call address 0 or not in I2Cn slave mode." "0,1"
line.long 0xC "SAR2,I2Cn Slave Address Register 2"
hexmask.long.byte 0xC 1.--7. 1. "SLAn,These bits configure the slave address 1 in slave mode."
bitfld.long 0xC 0. "GCALLnEN,This bit decides whether I2Cn allows general call address 1 or not in I2Cn slave mode." "0,1"
line.long 0x10 "DR,I2Cn Data Register"
hexmask.long.byte 0x10 0.--7. 1. "DATA,The I2CnDR Transmit buffer and Receive buffer share the same I/O address with this DATA register. The Transmit Data Buffer is the destination for data written to the I2CnDR register. Reading the I2CnDR register returns the contents of the Receive.."
sif (cpuis("A31G31*"))
group.long 0x14++0xB
line.long 0x0 "SDHR,I2Cn SDA Hold Time Register"
hexmask.long.word 0x0 0.--11. 1. "HLDT,This register is used to control SDA output timing from the falling edge of SCL. Note that SDA is changed after tPCLK X (I2CnSDHR+2). In master mode load half the value of I2CnSCLR to this register to make SDA change in the middle of SCL. In slave.."
line.long 0x4 "SCLR,I2Cn SCL Low Period Register"
hexmask.long.word 0x4 0.--11. 1. "SCLL,This register defines the low period of SCL in master mode. The base clock is PCLK and the period is calculated by the formula: tPCLK X (4 X I2CnSCLR + 2) where tPCLK is the period of PCLK."
line.long 0x8 "SCHR,I2Cn SCL High Period Register"
hexmask.long.word 0x8 0.--11. 1. "SCLH,This register defines the high period of SCL in master mode. The base clock is PCLK and the period is calculated by the formula: tPCLK X (4 X I2CnSCHR + 2) where tPCLK is the period of PCLK."
endif
sif (cpuis("A31G32*"))
group.long 0x14++0xF
line.long 0x0 "SDAHR,I2Cn SDA Hold Time Register"
hexmask.long.word 0x0 0.--11. 1. "HLDT,This register is used to control SDA output timing from the falling edge of SCL. Note that SDA is changed after tPCLK X (I2CnSDHR+2). In master mode load half the value of I2CnSCLR to this register to make SDA change in the middle of SCL. In slave.."
line.long 0x4 "SCLLR,I2Cn SCL Low Period Register"
hexmask.long.word 0x4 0.--11. 1. "SCLL,This register defines the low period of SCL in master mode. The base clock is PCLK and the period is calculated by the formula: tPCLK X (4 X I2CnSCLR + 2) where tPCLK is the period of PCLK."
line.long 0x8 "SCLHR,I2Cn SCL High Period Register"
hexmask.long.word 0x8 0.--11. 1. "SCLH,This register defines the high period of SCL in master mode. The base clock is PCLK and the period is calculated by the formula: tPCLK X (4 X I2CnSCHR + 2) where tPCLK is the period of PCLK."
line.long 0xC "MR,I2Cn Mode Control Register"
bitfld.long 0xC 0. "DIS_SDAH,Disable SDA hold time" "0,1"
endif
tree.end
tree "I2C1"
base ad:0x40004900
group.long 0x0++0x13
line.long 0x0 "CR,I2Cn Control Register"
sif (cpuis("A31G31*"))
bitfld.long 0x0 7. "I2CnEN,Activate I2Cn Block by supplying" "0,1"
bitfld.long 0x0 6. "TXDLYENBn,I2CnSDHR Register Control bit" "0,1"
bitfld.long 0x0 5. "I2CnIEN,I2Cn Interrupt Enable bit" "0,1"
bitfld.long 0x0 4. "I2CnIFLAG,I2Cn Interrupt Flag bit. This bit is cleared when write any values in the I2CnST register." "0,1"
endif
sif (cpuis("A31G32*"))
rbitfld.long 0x0 7. "I2CnIFLAG,Interrupt flag bit" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 6. "I2CnEN,Activate I2Cn Block ( by supplying clock)" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 5. "RESET,Initialize internal register of I2C" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 4. "I2CnIEN,I2Cn Interrupt Enable bit." "0,1"
newline
endif
bitfld.long 0x0 3. "ACKnEN,Controls ACK signal generation at ninth SCL period. Notes) ACK signal is output (SDA = 0) for the following 3 cases. Where x = 0 and 1. 1. When received address packet equals to SLAx[6:0] bits in I2CnSARx register. 2. When received address packet.." "0,1"
rbitfld.long 0x0 2. "IMASTERn,Represent Operation Mode of I2Cn" "0,1"
bitfld.long 0x0 1. "STOPCn,STOP Condition Generation When I2Cn is master." "0,1"
bitfld.long 0x0 0. "STARTCn,START Condition Generation When I2Cn is master." "0,1"
line.long 0x4 "ST,I2Cn Status Register"
bitfld.long 0x4 7. "GCALLn,This bit has different meaning depending on whether I2C is master or slave. When I2C is a master this bit represents whether it received AACK (address ACK) from slave." "0,1"
bitfld.long 0x4 6. "TENDn,This bit is set when 1-byte of data is transferred completely." "?,1: byte of data is transferred completely"
bitfld.long 0x4 5. "STOPDn,This bit is set when a STOP condition is detected." "0,1"
bitfld.long 0x4 4. "SSELn,This bit is set when I2C is addressed by other master." "0,1"
bitfld.long 0x4 3. "MLOSTn,This bit represents the result of bus arbitration in master mode." "0,1"
bitfld.long 0x4 2. "BUSYn,This bit reflects bus status." "0,1"
rbitfld.long 0x4 1. "TMODEn,This bit is used to indicate whether I2C is transmitter or receiver." "0,1"
bitfld.long 0x4 0. "RXACKn,This bit shows the state of ACK signal." "0,1"
line.long 0x8 "SAR1,I2Cn Slave Address Register 1"
hexmask.long.byte 0x8 1.--7. 1. "SLAn,These bits configure the slave address 0 in slave mode."
bitfld.long 0x8 0. "GCALLnEN,This bit decides whether I2Cn allows general call address 0 or not in I2Cn slave mode." "0,1"
line.long 0xC "SAR2,I2Cn Slave Address Register 2"
hexmask.long.byte 0xC 1.--7. 1. "SLAn,These bits configure the slave address 1 in slave mode."
bitfld.long 0xC 0. "GCALLnEN,This bit decides whether I2Cn allows general call address 1 or not in I2Cn slave mode." "0,1"
line.long 0x10 "DR,I2Cn Data Register"
hexmask.long.byte 0x10 0.--7. 1. "DATA,The I2CnDR Transmit buffer and Receive buffer share the same I/O address with this DATA register. The Transmit Data Buffer is the destination for data written to the I2CnDR register. Reading the I2CnDR register returns the contents of the Receive.."
sif (cpuis("A31G31*"))
group.long 0x14++0xB
line.long 0x0 "SDHR,I2Cn SDA Hold Time Register"
hexmask.long.word 0x0 0.--11. 1. "HLDT,This register is used to control SDA output timing from the falling edge of SCL. Note that SDA is changed after tPCLK X (I2CnSDHR+2). In master mode load half the value of I2CnSCLR to this register to make SDA change in the middle of SCL. In slave.."
line.long 0x4 "SCLR,I2Cn SCL Low Period Register"
hexmask.long.word 0x4 0.--11. 1. "SCLL,This register defines the low period of SCL in master mode. The base clock is PCLK and the period is calculated by the formula: tPCLK X (4 X I2CnSCLR + 2) where tPCLK is the period of PCLK."
line.long 0x8 "SCHR,I2Cn SCL High Period Register"
hexmask.long.word 0x8 0.--11. 1. "SCLH,This register defines the high period of SCL in master mode. The base clock is PCLK and the period is calculated by the formula: tPCLK X (4 X I2CnSCHR + 2) where tPCLK is the period of PCLK."
endif
sif (cpuis("A31G32*"))
group.long 0x14++0xF
line.long 0x0 "SDAHR,I2Cn SDA Hold Time Register"
hexmask.long.word 0x0 0.--11. 1. "HLDT,This register is used to control SDA output timing from the falling edge of SCL. Note that SDA is changed after tPCLK X (I2CnSDHR+2). In master mode load half the value of I2CnSCLR to this register to make SDA change in the middle of SCL. In slave.."
line.long 0x4 "SCLLR,I2Cn SCL Low Period Register"
hexmask.long.word 0x4 0.--11. 1. "SCLL,This register defines the low period of SCL in master mode. The base clock is PCLK and the period is calculated by the formula: tPCLK X (4 X I2CnSCLR + 2) where tPCLK is the period of PCLK."
line.long 0x8 "SCLHR,I2Cn SCL High Period Register"
hexmask.long.word 0x8 0.--11. 1. "SCLH,This register defines the high period of SCL in master mode. The base clock is PCLK and the period is calculated by the formula: tPCLK X (4 X I2CnSCHR + 2) where tPCLK is the period of PCLK."
line.long 0xC "MR,I2Cn Mode Control Register"
bitfld.long 0xC 0. "DIS_SDAH,Disable SDA hold time" "0,1"
endif
tree.end
sif (cpuis("A31G31*"))
tree "I2C2"
base ad:0x40004A00
group.long 0x0++0x1F
line.long 0x0 "CR,I2Cn Control Register"
bitfld.long 0x0 7. "I2CnEN,Activate I2Cn Block by supplying" "0,1"
bitfld.long 0x0 6. "TXDLYENBn,I2CnSDHR Register Control bit" "0,1"
bitfld.long 0x0 5. "I2CnIEN,I2Cn Interrupt Enable bit" "0,1"
bitfld.long 0x0 4. "I2CnIFLAG,I2Cn Interrupt Flag bit. This bit is cleared when write any values in the I2CnST register." "0,1"
bitfld.long 0x0 3. "ACKnEN,Controls ACK signal generation at ninth SCL period. Notes) ACK signal is output (SDA = 0) for the following 3 cases. Where x = 0 and 1. 1. When received address packet equals to SLAx[6:0] bits in I2CnSARx register. 2. When received address packet.." "0,1"
rbitfld.long 0x0 2. "IMASTERn,Represent Operation Mode of I2Cn" "0,1"
bitfld.long 0x0 1. "STOPCn,STOP Condition Generation When I2Cn is master." "0,1"
newline
bitfld.long 0x0 0. "STARTCn,START Condition Generation When I2Cn is master." "0,1"
line.long 0x4 "ST,I2Cn Status Register"
bitfld.long 0x4 7. "GCALLn,This bit has different meaning depending on whether I2C is master or slave. When I2C is a master this bit represents whether it received AACK (address ACK) from slave." "0,1"
bitfld.long 0x4 6. "TENDn,This bit is set when 1-byte of data is transferred completely." "?,1: byte of data is transferred completely"
bitfld.long 0x4 5. "STOPDn,This bit is set when a STOP condition is detected." "0,1"
bitfld.long 0x4 4. "SSELn,This bit is set when I2C is addressed by other master." "0,1"
bitfld.long 0x4 3. "MLOSTn,This bit represents the result of bus arbitration in master mode." "0,1"
bitfld.long 0x4 2. "BUSYn,This bit reflects bus status." "0,1"
rbitfld.long 0x4 1. "TMODEn,This bit is used to indicate whether I2C is transmitter or receiver." "0,1"
newline
bitfld.long 0x4 0. "RXACKn,This bit shows the state of ACK signal." "0,1"
line.long 0x8 "SAR1,I2Cn Slave Address Register 1"
hexmask.long.byte 0x8 1.--7. 1. "SLAn,These bits configure the slave address 0 in slave mode."
bitfld.long 0x8 0. "GCALLnEN,This bit decides whether I2Cn allows general call address 0 or not in I2Cn slave mode." "0,1"
line.long 0xC "SAR2,I2Cn Slave Address Register 2"
hexmask.long.byte 0xC 1.--7. 1. "SLAn,These bits configure the slave address 1 in slave mode."
bitfld.long 0xC 0. "GCALLnEN,This bit decides whether I2Cn allows general call address 1 or not in I2Cn slave mode." "0,1"
line.long 0x10 "DR,I2Cn Data Register"
hexmask.long.byte 0x10 0.--7. 1. "DATA,The I2CnDR Transmit buffer and Receive buffer share the same I/O address with this DATA register. The Transmit Data Buffer is the destination for data written to the I2CnDR register. Reading the I2CnDR register returns the contents of the Receive.."
line.long 0x14 "SDHR,I2Cn SDA Hold Time Register"
hexmask.long.word 0x14 0.--11. 1. "HLDT,This register is used to control SDA output timing from the falling edge of SCL. Note that SDA is changed after tPCLK X (I2CnSDHR+2). In master mode load half the value of I2CnSCLR to this register to make SDA change in the middle of SCL. In slave.."
line.long 0x18 "SCLR,I2Cn SCL Low Period Register"
hexmask.long.word 0x18 0.--11. 1. "SCLL,This register defines the low period of SCL in master mode. The base clock is PCLK and the period is calculated by the formula: tPCLK X (4 X I2CnSCLR + 2) where tPCLK is the period of PCLK."
line.long 0x1C "SCHR,I2Cn SCL High Period Register"
hexmask.long.word 0x1C 0.--11. 1. "SCLH,This register defines the high period of SCL in master mode. The base clock is PCLK and the period is calculated by the formula: tPCLK X (4 X I2CnSCHR + 2) where tPCLK is the period of PCLK."
tree.end
endif
tree.end
tree "PCU&GPIO (Port Control Unit and General Purpose I/O)"
base ad:0x0
tree "PA"
base ad:0x40001000
group.long 0x0++0x13
line.long 0x0 "MOD,Port n Mode Register"
bitfld.long 0x0 30.--31. "MODE15,Pin 15 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 28.--29. "MODE14,Pin 14 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 26.--27. "MODE13,Pin 13 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 24.--25. "MODE12,Pin 12 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 22.--23. "MODE11,Pin 11 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 20.--21. "MODE10,Pin 10 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 18.--19. "MODE9,Pin 9 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 16.--17. "MODE8,Pin 8 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 14.--15. "MODE7,Pin 7 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 12.--13. "MODE6,Pin 6 Mode Selection bits" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "MODE5,Pin 5 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 8.--9. "MODE4,Pin 4 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 6.--7. "MODE3,Pin 3 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 4.--5. "MODE2,Pin 2 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 2.--3. "MODE1,Pin 1 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 0.--1. "MODE0,Pin 0 Mode Selection bits" "0,1,2,3"
line.long 0x4 "TYP,Port n Output Type Selection Register"
bitfld.long 0x4 15. "TYP15,Pin 15 Output Type Selection bit" "0,1"
bitfld.long 0x4 14. "TYP14,Pin 15 Output Type Selection bit" "0,1"
bitfld.long 0x4 13. "TYP13,Pin 13 Output Type Selection bit" "0,1"
bitfld.long 0x4 12. "TYP12,Pin 12 Output Type Selection bit" "0,1"
bitfld.long 0x4 11. "TYP11,Pin 11 Output Type Selection bit" "0,1"
bitfld.long 0x4 10. "TYP10,Pin 10 Output Type Selection bit" "0,1"
bitfld.long 0x4 9. "TYP9,Pin 9 Output Type Selection bit" "0,1"
bitfld.long 0x4 8. "TYP8,Pin 8 Output Type Selection bit" "0,1"
bitfld.long 0x4 7. "TYP7,Pin 7 Output Type Selection bit" "0,1"
bitfld.long 0x4 6. "TYP6,Pin 6 Output Type Selection bit" "0,1"
newline
bitfld.long 0x4 5. "TYP5,Pin 5 Output Type Selection bit" "0,1"
bitfld.long 0x4 4. "TYP4,Pin 4 Output Type Selection bit" "0,1"
bitfld.long 0x4 3. "TYP3,Pin 3 Output Type Selection bit" "0,1"
bitfld.long 0x4 2. "TYP2,Pin 2 Output Type Selection bit" "0,1"
bitfld.long 0x4 1. "TYP1,Pin 1 Output Type Selection bit" "0,1"
bitfld.long 0x4 0. "TYP0,Pin 0 Output Type Selection bit" "0,1"
line.long 0x8 "AFSR1,Port n Alternative Function Selection Register 1"
hexmask.long.byte 0x8 28.--31. 1. "AFSR7,Pin 7 Alternative Function Selection bits"
hexmask.long.byte 0x8 24.--27. 1. "AFSR6,Pin 6 Alternative Function Selection bits"
hexmask.long.byte 0x8 20.--23. 1. "AFSR5,Pin 5 Alternative Function Selection bits"
hexmask.long.byte 0x8 16.--19. 1. "AFSR4,Pin 4 Alternative Function Selection bits"
hexmask.long.byte 0x8 12.--15. 1. "AFSR3,Pin 3 Alternative Function Selection bits"
hexmask.long.byte 0x8 8.--11. 1. "AFSR2,Pin 2 Alternative Function Selection bits"
hexmask.long.byte 0x8 4.--7. 1. "AFSR1,Pin 1 Alternative Function Selection bits"
hexmask.long.byte 0x8 0.--3. 1. "AFSR0,Pin 0 Alternative Function Selection bits"
line.long 0xC "AFSR2,Port n Alternative Function Selection Register 2"
hexmask.long.byte 0xC 28.--31. 1. "AFSR15,Pin 15 Alternative Function Selection bits"
hexmask.long.byte 0xC 24.--27. 1. "AFSR14,Pin 14 Alternative Function Selection bits"
hexmask.long.byte 0xC 20.--23. 1. "AFSR13,Pin 13 Alternative Function Selection bits"
hexmask.long.byte 0xC 16.--19. 1. "AFSR12,Pin 12 Alternative Function Selection bits"
hexmask.long.byte 0xC 12.--15. 1. "AFSR11,Pin 11 Alternative Function Selection bits"
hexmask.long.byte 0xC 8.--11. 1. "AFSR10,Pin 10 Alternative Function Selection bits"
hexmask.long.byte 0xC 4.--7. 1. "AFSR9,Pin 9 Alternative Function Selection bits"
hexmask.long.byte 0xC 0.--3. 1. "AFSR8,Pin 8 Alternative Function Selection bits"
line.long 0x10 "PUPD,Port n Pull-up/down Resistor Selection Register"
bitfld.long 0x10 30.--31. "PUPD15,Pin 15 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 28.--29. "PUPD14,Pin 14 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 26.--27. "PUPD13,Pin 13 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 24.--25. "PUPD12,Pin 12 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 22.--23. "PUPD11,Pin 11 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 20.--21. "PUPD10,Pin 10 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 18.--19. "PUPD9,Pin 9 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 16.--17. "PUPD8,Pin 8 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 14.--15. "PUPD7,Pin 7 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 12.--13. "PUPD6,Pin 6 Pull-up/down Resistor Selection bits" "0,1,2,3"
newline
bitfld.long 0x10 10.--11. "PUPD5,Pin 5 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 8.--9. "PUPD4,Pin 4 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 6.--7. "PUPD3,Pin 3 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 4.--5. "PUPD2,Pin 2 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 2.--3. "PUPD1,Pin 1 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 0.--1. "PUPD0,Pin 0 Pull-up/down Resistor Selection bits" "0,1,2,3"
rgroup.long 0x14++0x3
line.long 0x0 "INDR,Port n Input Data Register"
bitfld.long 0x0 15. "INDR15,Pin 15 Input Data bit" "0,1"
bitfld.long 0x0 14. "INDR14,Pin 14 Input Data bit" "0,1"
bitfld.long 0x0 13. "INDR13,Pin 13 Input Data bit" "0,1"
bitfld.long 0x0 12. "INDR12,Pin 12 Input Data bit" "0,1"
bitfld.long 0x0 11. "INDR11,Pin 11 Input Data bit" "0,1"
bitfld.long 0x0 10. "INDR10,Pin 10 Input Data bit" "0,1"
bitfld.long 0x0 9. "INDR9,Pin 9 Input Data bit" "0,1"
bitfld.long 0x0 8. "INDR8,Pin 8 Input Data bit" "0,1"
bitfld.long 0x0 7. "INDR7,Pin 7 Input Data bit" "0,1"
bitfld.long 0x0 6. "INDR6,Pin 6 Input Data bit" "0,1"
newline
bitfld.long 0x0 5. "INDR5,Pin 5 Input Data bit" "0,1"
bitfld.long 0x0 4. "INDR4,Pin 4 Input Data bit" "0,1"
bitfld.long 0x0 3. "INDR3,Pin 3 Input Data bit" "0,1"
bitfld.long 0x0 2. "INDR2,Pin 2 Input Data bit" "0,1"
bitfld.long 0x0 1. "INDR1,Pin 1 Input Data bit" "0,1"
bitfld.long 0x0 0. "INDR0,Pin 0 Input Data bit" "0,1"
group.long 0x18++0x3
line.long 0x0 "OUTDR,Port n Output Data Register"
bitfld.long 0x0 15. "OUTDR15,Pin 15 Output Data bit" "0,1"
bitfld.long 0x0 14. "OUTDR14,Pin 14 Output Data bit" "0,1"
bitfld.long 0x0 13. "OUTDR13,Pin 13 Output Data bit" "0,1"
bitfld.long 0x0 12. "OUTDR12,Pin 12 Output Data bit" "0,1"
bitfld.long 0x0 11. "OUTDR11,Pin 11 Output Data bit" "0,1"
bitfld.long 0x0 10. "OUTDR10,Pin 10 Output Data bit" "0,1"
bitfld.long 0x0 9. "OUTDR9,Pin 9 Output Data bit" "0,1"
bitfld.long 0x0 8. "OUTDR8,Pin 8 Output Data bit" "0,1"
bitfld.long 0x0 7. "OUTDR7,Pin 7 Output Data bit" "0,1"
bitfld.long 0x0 6. "OUTDR6,Pin 6 Output Data bit" "0,1"
newline
bitfld.long 0x0 5. "OUTDR5,Pin 5 Output Data bit" "0,1"
bitfld.long 0x0 4. "OUTDR4,Pin 4 Output Data bit" "0,1"
bitfld.long 0x0 3. "OUTDR3,Pin 3 Output Data bit" "0,1"
bitfld.long 0x0 2. "OUTDR2,Pin 2 Output Data bit" "0,1"
bitfld.long 0x0 1. "OUTDR1,Pin 1 Output Data bit" "0,1"
bitfld.long 0x0 0. "OUTDR0,Pin 0 Output Data bit" "0,1"
wgroup.long 0x1C++0x7
line.long 0x0 "BSR,Port n Output Bit Set Register"
bitfld.long 0x0 15. "BSR15,Pin 15 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 14. "BSR14,Pin 14 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 13. "BSR13,Pin 13 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 12. "BSR12,Pin 12 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 11. "BSR11,Pin 11 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 10. "BSR10,Pin 10 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 9. "BSR9,Pin 9 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 8. "BSR8,Pin 8 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 7. "BSR7,Pin 7 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 6. "BSR6,Pin 6 Output Set bit. This bit is always read to 0" "0,1"
newline
bitfld.long 0x0 5. "BSR5,Pin 5 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 4. "BSR4,Pin 4 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 3. "BSR3,Pin 3 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 2. "BSR2,Pin 2 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 1. "BSR1,Pin 1 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 0. "BSR0,Pin 0 Output Set bit. This bit is always read to 0" "0,1"
line.long 0x4 "BCR,Port n Output Bit Clear Register"
bitfld.long 0x4 15. "BCR15,Pin 15 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 14. "BCR14,Pin 14 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 13. "BCR13,Pin 13 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 12. "BCR12,Pin 12 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 11. "BCR11,Pin 11 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 10. "BCR10,Pin 10 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 9. "BCR9,Pin 9 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 8. "BCR8,Pin 8 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 7. "BCR7,Pin 7 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 6. "BCR6,Pin 6 Output Clear bit. This bit is always read to 0." "0,1"
newline
bitfld.long 0x4 5. "BCR5,Pin 5 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 4. "BCR4,Pin 4 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 3. "BCR3,Pin 3 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 2. "BCR2,Pin 2 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 1. "BCR1,Pin 1 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 0. "BCR0,Pin 0 Output Clear bit. This bit is always read to 0." "0,1"
group.long 0x24++0x13
line.long 0x0 "OUTDMSK,Port n Output Data Mask Register"
bitfld.long 0x0 15. "OUTDMSK15,Pin 15 Output Data Mask bit" "0,1"
bitfld.long 0x0 14. "OUTDMSK14,Pin 14 Output Data Mask bit" "0,1"
bitfld.long 0x0 13. "OUTDMSK13,Pin 13 Output Data Mask bit" "0,1"
bitfld.long 0x0 12. "OUTDMSK12,Pin 12 Output Data Mask bit" "0,1"
bitfld.long 0x0 11. "OUTDMSK11,Pin 11 Output Data Mask bit" "0,1"
bitfld.long 0x0 10. "OUTDMSK10,Pin 10 Output Data Mask bit" "0,1"
bitfld.long 0x0 9. "OUTDMSK9,Pin 9 Output Data Mask bit" "0,1"
bitfld.long 0x0 8. "OUTDMSK8,Pin 8 Output Data Mask bit" "0,1"
bitfld.long 0x0 7. "OUTDMSK7,Pin 7 Output Data Mask bit" "0,1"
bitfld.long 0x0 6. "OUTDMSK6,Pin 6 Output Data Mask bit" "0,1"
newline
bitfld.long 0x0 5. "OUTDMSK5,Pin 5 Output Data Mask bit" "0,1"
bitfld.long 0x0 4. "OUTDMSK4,Pin 4 Output Data Mask bit" "0,1"
bitfld.long 0x0 3. "OUTDMSK3,Pin 3 Output Data Mask bit" "0,1"
bitfld.long 0x0 2. "OUTDMSK2,Pin 2 Output Data Mask bit" "0,1"
bitfld.long 0x0 1. "OUTDMSK1,Pin 1 Output Data Mask bit" "0,1"
bitfld.long 0x0 0. "OUTDMSK0,Pin 0 Output Data Mask bit" "0,1"
line.long 0x4 "DBCR,Port n Debounce Control Register"
bitfld.long 0x4 15. "DBEN15,Pin 15 Debounce Enable bit" "0,1"
bitfld.long 0x4 14. "DBEN14,Pin 14 Debounce Enable bit" "0,1"
bitfld.long 0x4 13. "DBEN13,Pin 13 Debounce Enable bit" "0,1"
bitfld.long 0x4 12. "DBEN12,Pin 12 Debounce Enable bit" "0,1"
bitfld.long 0x4 11. "DBEN11,Pin 11 Debounce Enable bit" "0,1"
bitfld.long 0x4 10. "DBEN10,Pin 10 Debounce Enable bit" "0,1"
bitfld.long 0x4 9. "DBEN9,Pin 9 Debounce Enable bit" "0,1"
bitfld.long 0x4 8. "DBEN8,Pin 8 Debounce Enable bit" "0,1"
bitfld.long 0x4 7. "DBEN7,Pin 7 Debounce Enable bit" "0,1"
bitfld.long 0x4 6. "DBEN6,Pin 6 Debounce Enable bit" "0,1"
newline
bitfld.long 0x4 5. "DBEN5,Pin 5 Debounce Enable bit" "0,1"
bitfld.long 0x4 4. "DBEN4,Pin 4 Debounce Enable bit" "0,1"
bitfld.long 0x4 3. "DBEN3,Pin 3 Debounce Enable bit" "0,1"
bitfld.long 0x4 2. "DBEN2,Pin 2 Debounce Enable bit" "0,1"
bitfld.long 0x4 1. "DBEN1,Pin 1 Debounce Enable bit" "0,1"
bitfld.long 0x4 0. "DBEN0,Pin 0 Debounce Enable bit" "0,1"
line.long 0x8 "IER,Port n interrupt enable register"
bitfld.long 0x8 30.--31. "P15,P15 interrupt enable" "0,1,2,3"
bitfld.long 0x8 28.--29. "P14,P14 interrupt enable" "0,1,2,3"
bitfld.long 0x8 26.--27. "P13,P13 interrupt enable" "0,1,2,3"
bitfld.long 0x8 24.--25. "P12,P12 interrupt enable" "0,1,2,3"
bitfld.long 0x8 22.--23. "P11,P11 interrupt enable" "0,1,2,3"
bitfld.long 0x8 20.--21. "P10,P10 interrupt enable" "0,1,2,3"
bitfld.long 0x8 18.--19. "P9,P9 interrupt enable" "0,1,2,3"
bitfld.long 0x8 16.--17. "P8,P8 interrupt enable" "0,1,2,3"
bitfld.long 0x8 14.--15. "P7,P7 interrupt enable" "0,1,2,3"
bitfld.long 0x8 12.--13. "P6,P6 interrupt enable" "0,1,2,3"
newline
bitfld.long 0x8 10.--11. "P5,P5 interrupt enable" "0,1,2,3"
bitfld.long 0x8 8.--9. "P4,P4 interrupt enable" "0,1,2,3"
bitfld.long 0x8 6.--7. "P3,P3 interrupt enable" "0,1,2,3"
bitfld.long 0x8 4.--5. "P2,P2 interrupt enable" "0,1,2,3"
bitfld.long 0x8 2.--3. "P1,P1 interrupt enable" "0,1,2,3"
bitfld.long 0x8 0.--1. "P0,P0 interrupt enable" "0,1,2,3"
line.long 0xC "ISR,Port n interrupt status register"
bitfld.long 0xC 30.--31. "P15,P15 interrupt status" "0,1,2,3"
bitfld.long 0xC 28.--29. "P14,P14 interrupt status" "0,1,2,3"
bitfld.long 0xC 26.--27. "P13,P13 interrupt status" "0,1,2,3"
bitfld.long 0xC 24.--25. "P12,P12 interrupt status" "0,1,2,3"
bitfld.long 0xC 22.--23. "P11,P11 interrupt status" "0,1,2,3"
bitfld.long 0xC 20.--21. "P10,P10 interrupt status" "0,1,2,3"
bitfld.long 0xC 18.--19. "P9,P9 interrupt status" "0,1,2,3"
bitfld.long 0xC 16.--17. "P8,P8 interrupt status" "0,1,2,3"
bitfld.long 0xC 14.--15. "P7,P7 interrupt status" "0,1,2,3"
bitfld.long 0xC 12.--13. "P6,P6 interrupt status" "0,1,2,3"
newline
bitfld.long 0xC 10.--11. "P5,P5 interrupt status" "0,1,2,3"
bitfld.long 0xC 8.--9. "P4,P4 interrupt status" "0,1,2,3"
bitfld.long 0xC 6.--7. "P3,P3 interrupt status" "0,1,2,3"
bitfld.long 0xC 4.--5. "P2,P2 interrupt status" "0,1,2,3"
bitfld.long 0xC 2.--3. "P1,P1 interrupt status" "0,1,2,3"
bitfld.long 0xC 0.--1. "P0,P0 interrupt status" "0,1,2,3"
line.long 0x10 "ICR,Port n interrupt control register"
bitfld.long 0x10 30.--31. "P15,P15 interrupt control" "0,1,2,3"
bitfld.long 0x10 28.--29. "P14,P14 interrupt control" "0,1,2,3"
bitfld.long 0x10 26.--27. "P13,P13 interrupt control" "0,1,2,3"
bitfld.long 0x10 24.--25. "P12,P12 interrupt control" "0,1,2,3"
bitfld.long 0x10 22.--23. "P11,P11 interrupt control" "0,1,2,3"
bitfld.long 0x10 20.--21. "P10,P10 interrupt control" "0,1,2,3"
bitfld.long 0x10 18.--19. "P9,P9 interrupt control" "0,1,2,3"
bitfld.long 0x10 16.--17. "P8,P8 interrupt control" "0,1,2,3"
bitfld.long 0x10 14.--15. "P7,P7 interrupt control" "0,1,2,3"
bitfld.long 0x10 12.--13. "P6,P6 interrupt control" "0,1,2,3"
newline
bitfld.long 0x10 10.--11. "P5,P5 interrupt control" "0,1,2,3"
bitfld.long 0x10 8.--9. "P4,P4 interrupt control" "0,1,2,3"
bitfld.long 0x10 6.--7. "P3,P3 interrupt control" "0,1,2,3"
bitfld.long 0x10 4.--5. "P2,P2 interrupt control" "0,1,2,3"
bitfld.long 0x10 2.--3. "P1,P1 interrupt control" "0,1,2,3"
bitfld.long 0x10 0.--1. "P0,P0 interrupt control" "0,1,2,3"
tree.end
tree "PB"
base ad:0x40001100
group.long 0x0++0x13
line.long 0x0 "MOD,Port n Mode Register"
bitfld.long 0x0 30.--31. "MODE15,Pin 15 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 28.--29. "MODE14,Pin 14 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 26.--27. "MODE13,Pin 13 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 24.--25. "MODE12,Pin 12 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 22.--23. "MODE11,Pin 11 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 20.--21. "MODE10,Pin 10 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 18.--19. "MODE9,Pin 9 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 16.--17. "MODE8,Pin 8 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 14.--15. "MODE7,Pin 7 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 12.--13. "MODE6,Pin 6 Mode Selection bits" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "MODE5,Pin 5 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 8.--9. "MODE4,Pin 4 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 6.--7. "MODE3,Pin 3 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 4.--5. "MODE2,Pin 2 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 2.--3. "MODE1,Pin 1 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 0.--1. "MODE0,Pin 0 Mode Selection bits" "0,1,2,3"
line.long 0x4 "TYP,Port n Output Type Selection Register"
bitfld.long 0x4 15. "TYP15,Pin 15 Output Type Selection bit" "0,1"
bitfld.long 0x4 14. "TYP14,Pin 15 Output Type Selection bit" "0,1"
bitfld.long 0x4 13. "TYP13,Pin 13 Output Type Selection bit" "0,1"
bitfld.long 0x4 12. "TYP12,Pin 12 Output Type Selection bit" "0,1"
bitfld.long 0x4 11. "TYP11,Pin 11 Output Type Selection bit" "0,1"
bitfld.long 0x4 10. "TYP10,Pin 10 Output Type Selection bit" "0,1"
bitfld.long 0x4 9. "TYP9,Pin 9 Output Type Selection bit" "0,1"
bitfld.long 0x4 8. "TYP8,Pin 8 Output Type Selection bit" "0,1"
bitfld.long 0x4 7. "TYP7,Pin 7 Output Type Selection bit" "0,1"
bitfld.long 0x4 6. "TYP6,Pin 6 Output Type Selection bit" "0,1"
newline
bitfld.long 0x4 5. "TYP5,Pin 5 Output Type Selection bit" "0,1"
bitfld.long 0x4 4. "TYP4,Pin 4 Output Type Selection bit" "0,1"
bitfld.long 0x4 3. "TYP3,Pin 3 Output Type Selection bit" "0,1"
bitfld.long 0x4 2. "TYP2,Pin 2 Output Type Selection bit" "0,1"
bitfld.long 0x4 1. "TYP1,Pin 1 Output Type Selection bit" "0,1"
bitfld.long 0x4 0. "TYP0,Pin 0 Output Type Selection bit" "0,1"
line.long 0x8 "AFSR1,Port n Alternative Function Selection Register 1"
hexmask.long.byte 0x8 28.--31. 1. "AFSR7,Pin 7 Alternative Function Selection bits"
hexmask.long.byte 0x8 24.--27. 1. "AFSR6,Pin 6 Alternative Function Selection bits"
hexmask.long.byte 0x8 20.--23. 1. "AFSR5,Pin 5 Alternative Function Selection bits"
hexmask.long.byte 0x8 16.--19. 1. "AFSR4,Pin 4 Alternative Function Selection bits"
hexmask.long.byte 0x8 12.--15. 1. "AFSR3,Pin 3 Alternative Function Selection bits"
hexmask.long.byte 0x8 8.--11. 1. "AFSR2,Pin 2 Alternative Function Selection bits"
hexmask.long.byte 0x8 4.--7. 1. "AFSR1,Pin 1 Alternative Function Selection bits"
hexmask.long.byte 0x8 0.--3. 1. "AFSR0,Pin 0 Alternative Function Selection bits"
line.long 0xC "AFSR2,Port n Alternative Function Selection Register 2"
hexmask.long.byte 0xC 28.--31. 1. "AFSR15,Pin 15 Alternative Function Selection bits"
hexmask.long.byte 0xC 24.--27. 1. "AFSR14,Pin 14 Alternative Function Selection bits"
hexmask.long.byte 0xC 20.--23. 1. "AFSR13,Pin 13 Alternative Function Selection bits"
hexmask.long.byte 0xC 16.--19. 1. "AFSR12,Pin 12 Alternative Function Selection bits"
hexmask.long.byte 0xC 12.--15. 1. "AFSR11,Pin 11 Alternative Function Selection bits"
hexmask.long.byte 0xC 8.--11. 1. "AFSR10,Pin 10 Alternative Function Selection bits"
hexmask.long.byte 0xC 4.--7. 1. "AFSR9,Pin 9 Alternative Function Selection bits"
hexmask.long.byte 0xC 0.--3. 1. "AFSR8,Pin 8 Alternative Function Selection bits"
line.long 0x10 "PUPD,Port n Pull-up/down Resistor Selection Register"
bitfld.long 0x10 30.--31. "PUPD15,Pin 15 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 28.--29. "PUPD14,Pin 14 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 26.--27. "PUPD13,Pin 13 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 24.--25. "PUPD12,Pin 12 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 22.--23. "PUPD11,Pin 11 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 20.--21. "PUPD10,Pin 10 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 18.--19. "PUPD9,Pin 9 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 16.--17. "PUPD8,Pin 8 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 14.--15. "PUPD7,Pin 7 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 12.--13. "PUPD6,Pin 6 Pull-up/down Resistor Selection bits" "0,1,2,3"
newline
bitfld.long 0x10 10.--11. "PUPD5,Pin 5 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 8.--9. "PUPD4,Pin 4 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 6.--7. "PUPD3,Pin 3 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 4.--5. "PUPD2,Pin 2 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 2.--3. "PUPD1,Pin 1 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 0.--1. "PUPD0,Pin 0 Pull-up/down Resistor Selection bits" "0,1,2,3"
rgroup.long 0x14++0x3
line.long 0x0 "INDR,Port n Input Data Register"
bitfld.long 0x0 15. "INDR15,Pin 15 Input Data bit" "0,1"
bitfld.long 0x0 14. "INDR14,Pin 14 Input Data bit" "0,1"
bitfld.long 0x0 13. "INDR13,Pin 13 Input Data bit" "0,1"
bitfld.long 0x0 12. "INDR12,Pin 12 Input Data bit" "0,1"
bitfld.long 0x0 11. "INDR11,Pin 11 Input Data bit" "0,1"
bitfld.long 0x0 10. "INDR10,Pin 10 Input Data bit" "0,1"
bitfld.long 0x0 9. "INDR9,Pin 9 Input Data bit" "0,1"
bitfld.long 0x0 8. "INDR8,Pin 8 Input Data bit" "0,1"
bitfld.long 0x0 7. "INDR7,Pin 7 Input Data bit" "0,1"
bitfld.long 0x0 6. "INDR6,Pin 6 Input Data bit" "0,1"
newline
bitfld.long 0x0 5. "INDR5,Pin 5 Input Data bit" "0,1"
bitfld.long 0x0 4. "INDR4,Pin 4 Input Data bit" "0,1"
bitfld.long 0x0 3. "INDR3,Pin 3 Input Data bit" "0,1"
bitfld.long 0x0 2. "INDR2,Pin 2 Input Data bit" "0,1"
bitfld.long 0x0 1. "INDR1,Pin 1 Input Data bit" "0,1"
bitfld.long 0x0 0. "INDR0,Pin 0 Input Data bit" "0,1"
group.long 0x18++0x3
line.long 0x0 "OUTDR,Port n Output Data Register"
bitfld.long 0x0 15. "OUTDR15,Pin 15 Output Data bit" "0,1"
bitfld.long 0x0 14. "OUTDR14,Pin 14 Output Data bit" "0,1"
bitfld.long 0x0 13. "OUTDR13,Pin 13 Output Data bit" "0,1"
bitfld.long 0x0 12. "OUTDR12,Pin 12 Output Data bit" "0,1"
bitfld.long 0x0 11. "OUTDR11,Pin 11 Output Data bit" "0,1"
bitfld.long 0x0 10. "OUTDR10,Pin 10 Output Data bit" "0,1"
bitfld.long 0x0 9. "OUTDR9,Pin 9 Output Data bit" "0,1"
bitfld.long 0x0 8. "OUTDR8,Pin 8 Output Data bit" "0,1"
bitfld.long 0x0 7. "OUTDR7,Pin 7 Output Data bit" "0,1"
bitfld.long 0x0 6. "OUTDR6,Pin 6 Output Data bit" "0,1"
newline
bitfld.long 0x0 5. "OUTDR5,Pin 5 Output Data bit" "0,1"
bitfld.long 0x0 4. "OUTDR4,Pin 4 Output Data bit" "0,1"
bitfld.long 0x0 3. "OUTDR3,Pin 3 Output Data bit" "0,1"
bitfld.long 0x0 2. "OUTDR2,Pin 2 Output Data bit" "0,1"
bitfld.long 0x0 1. "OUTDR1,Pin 1 Output Data bit" "0,1"
bitfld.long 0x0 0. "OUTDR0,Pin 0 Output Data bit" "0,1"
wgroup.long 0x1C++0x7
line.long 0x0 "BSR,Port n Output Bit Set Register"
bitfld.long 0x0 15. "BSR15,Pin 15 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 14. "BSR14,Pin 14 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 13. "BSR13,Pin 13 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 12. "BSR12,Pin 12 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 11. "BSR11,Pin 11 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 10. "BSR10,Pin 10 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 9. "BSR9,Pin 9 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 8. "BSR8,Pin 8 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 7. "BSR7,Pin 7 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 6. "BSR6,Pin 6 Output Set bit. This bit is always read to 0" "0,1"
newline
bitfld.long 0x0 5. "BSR5,Pin 5 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 4. "BSR4,Pin 4 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 3. "BSR3,Pin 3 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 2. "BSR2,Pin 2 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 1. "BSR1,Pin 1 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 0. "BSR0,Pin 0 Output Set bit. This bit is always read to 0" "0,1"
line.long 0x4 "BCR,Port n Output Bit Clear Register"
bitfld.long 0x4 15. "BCR15,Pin 15 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 14. "BCR14,Pin 14 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 13. "BCR13,Pin 13 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 12. "BCR12,Pin 12 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 11. "BCR11,Pin 11 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 10. "BCR10,Pin 10 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 9. "BCR9,Pin 9 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 8. "BCR8,Pin 8 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 7. "BCR7,Pin 7 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 6. "BCR6,Pin 6 Output Clear bit. This bit is always read to 0." "0,1"
newline
bitfld.long 0x4 5. "BCR5,Pin 5 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 4. "BCR4,Pin 4 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 3. "BCR3,Pin 3 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 2. "BCR2,Pin 2 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 1. "BCR1,Pin 1 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 0. "BCR0,Pin 0 Output Clear bit. This bit is always read to 0." "0,1"
group.long 0x24++0x13
line.long 0x0 "OUTDMSK,Port n Output Data Mask Register"
bitfld.long 0x0 15. "OUTDMSK15,Pin 15 Output Data Mask bit" "0,1"
bitfld.long 0x0 14. "OUTDMSK14,Pin 14 Output Data Mask bit" "0,1"
bitfld.long 0x0 13. "OUTDMSK13,Pin 13 Output Data Mask bit" "0,1"
bitfld.long 0x0 12. "OUTDMSK12,Pin 12 Output Data Mask bit" "0,1"
bitfld.long 0x0 11. "OUTDMSK11,Pin 11 Output Data Mask bit" "0,1"
bitfld.long 0x0 10. "OUTDMSK10,Pin 10 Output Data Mask bit" "0,1"
bitfld.long 0x0 9. "OUTDMSK9,Pin 9 Output Data Mask bit" "0,1"
bitfld.long 0x0 8. "OUTDMSK8,Pin 8 Output Data Mask bit" "0,1"
bitfld.long 0x0 7. "OUTDMSK7,Pin 7 Output Data Mask bit" "0,1"
bitfld.long 0x0 6. "OUTDMSK6,Pin 6 Output Data Mask bit" "0,1"
newline
bitfld.long 0x0 5. "OUTDMSK5,Pin 5 Output Data Mask bit" "0,1"
bitfld.long 0x0 4. "OUTDMSK4,Pin 4 Output Data Mask bit" "0,1"
bitfld.long 0x0 3. "OUTDMSK3,Pin 3 Output Data Mask bit" "0,1"
bitfld.long 0x0 2. "OUTDMSK2,Pin 2 Output Data Mask bit" "0,1"
bitfld.long 0x0 1. "OUTDMSK1,Pin 1 Output Data Mask bit" "0,1"
bitfld.long 0x0 0. "OUTDMSK0,Pin 0 Output Data Mask bit" "0,1"
line.long 0x4 "DBCR,Port n Debounce Control Register"
bitfld.long 0x4 15. "DBEN15,Pin 15 Debounce Enable bit" "0,1"
bitfld.long 0x4 14. "DBEN14,Pin 14 Debounce Enable bit" "0,1"
bitfld.long 0x4 13. "DBEN13,Pin 13 Debounce Enable bit" "0,1"
bitfld.long 0x4 12. "DBEN12,Pin 12 Debounce Enable bit" "0,1"
bitfld.long 0x4 11. "DBEN11,Pin 11 Debounce Enable bit" "0,1"
bitfld.long 0x4 10. "DBEN10,Pin 10 Debounce Enable bit" "0,1"
bitfld.long 0x4 9. "DBEN9,Pin 9 Debounce Enable bit" "0,1"
bitfld.long 0x4 8. "DBEN8,Pin 8 Debounce Enable bit" "0,1"
bitfld.long 0x4 7. "DBEN7,Pin 7 Debounce Enable bit" "0,1"
bitfld.long 0x4 6. "DBEN6,Pin 6 Debounce Enable bit" "0,1"
newline
bitfld.long 0x4 5. "DBEN5,Pin 5 Debounce Enable bit" "0,1"
bitfld.long 0x4 4. "DBEN4,Pin 4 Debounce Enable bit" "0,1"
bitfld.long 0x4 3. "DBEN3,Pin 3 Debounce Enable bit" "0,1"
bitfld.long 0x4 2. "DBEN2,Pin 2 Debounce Enable bit" "0,1"
bitfld.long 0x4 1. "DBEN1,Pin 1 Debounce Enable bit" "0,1"
bitfld.long 0x4 0. "DBEN0,Pin 0 Debounce Enable bit" "0,1"
line.long 0x8 "IER,Port n interrupt enable register"
bitfld.long 0x8 30.--31. "P15,P15 interrupt enable" "0,1,2,3"
bitfld.long 0x8 28.--29. "P14,P14 interrupt enable" "0,1,2,3"
bitfld.long 0x8 26.--27. "P13,P13 interrupt enable" "0,1,2,3"
bitfld.long 0x8 24.--25. "P12,P12 interrupt enable" "0,1,2,3"
bitfld.long 0x8 22.--23. "P11,P11 interrupt enable" "0,1,2,3"
bitfld.long 0x8 20.--21. "P10,P10 interrupt enable" "0,1,2,3"
bitfld.long 0x8 18.--19. "P9,P9 interrupt enable" "0,1,2,3"
bitfld.long 0x8 16.--17. "P8,P8 interrupt enable" "0,1,2,3"
bitfld.long 0x8 14.--15. "P7,P7 interrupt enable" "0,1,2,3"
bitfld.long 0x8 12.--13. "P6,P6 interrupt enable" "0,1,2,3"
newline
bitfld.long 0x8 10.--11. "P5,P5 interrupt enable" "0,1,2,3"
bitfld.long 0x8 8.--9. "P4,P4 interrupt enable" "0,1,2,3"
bitfld.long 0x8 6.--7. "P3,P3 interrupt enable" "0,1,2,3"
bitfld.long 0x8 4.--5. "P2,P2 interrupt enable" "0,1,2,3"
bitfld.long 0x8 2.--3. "P1,P1 interrupt enable" "0,1,2,3"
bitfld.long 0x8 0.--1. "P0,P0 interrupt enable" "0,1,2,3"
line.long 0xC "ISR,Port n interrupt status register"
bitfld.long 0xC 30.--31. "P15,P15 interrupt status" "0,1,2,3"
bitfld.long 0xC 28.--29. "P14,P14 interrupt status" "0,1,2,3"
bitfld.long 0xC 26.--27. "P13,P13 interrupt status" "0,1,2,3"
bitfld.long 0xC 24.--25. "P12,P12 interrupt status" "0,1,2,3"
bitfld.long 0xC 22.--23. "P11,P11 interrupt status" "0,1,2,3"
bitfld.long 0xC 20.--21. "P10,P10 interrupt status" "0,1,2,3"
bitfld.long 0xC 18.--19. "P9,P9 interrupt status" "0,1,2,3"
bitfld.long 0xC 16.--17. "P8,P8 interrupt status" "0,1,2,3"
bitfld.long 0xC 14.--15. "P7,P7 interrupt status" "0,1,2,3"
bitfld.long 0xC 12.--13. "P6,P6 interrupt status" "0,1,2,3"
newline
bitfld.long 0xC 10.--11. "P5,P5 interrupt status" "0,1,2,3"
bitfld.long 0xC 8.--9. "P4,P4 interrupt status" "0,1,2,3"
bitfld.long 0xC 6.--7. "P3,P3 interrupt status" "0,1,2,3"
bitfld.long 0xC 4.--5. "P2,P2 interrupt status" "0,1,2,3"
bitfld.long 0xC 2.--3. "P1,P1 interrupt status" "0,1,2,3"
bitfld.long 0xC 0.--1. "P0,P0 interrupt status" "0,1,2,3"
line.long 0x10 "ICR,Port n interrupt control register"
bitfld.long 0x10 30.--31. "P15,P15 interrupt control" "0,1,2,3"
bitfld.long 0x10 28.--29. "P14,P14 interrupt control" "0,1,2,3"
bitfld.long 0x10 26.--27. "P13,P13 interrupt control" "0,1,2,3"
bitfld.long 0x10 24.--25. "P12,P12 interrupt control" "0,1,2,3"
bitfld.long 0x10 22.--23. "P11,P11 interrupt control" "0,1,2,3"
bitfld.long 0x10 20.--21. "P10,P10 interrupt control" "0,1,2,3"
bitfld.long 0x10 18.--19. "P9,P9 interrupt control" "0,1,2,3"
bitfld.long 0x10 16.--17. "P8,P8 interrupt control" "0,1,2,3"
bitfld.long 0x10 14.--15. "P7,P7 interrupt control" "0,1,2,3"
bitfld.long 0x10 12.--13. "P6,P6 interrupt control" "0,1,2,3"
newline
bitfld.long 0x10 10.--11. "P5,P5 interrupt control" "0,1,2,3"
bitfld.long 0x10 8.--9. "P4,P4 interrupt control" "0,1,2,3"
bitfld.long 0x10 6.--7. "P3,P3 interrupt control" "0,1,2,3"
bitfld.long 0x10 4.--5. "P2,P2 interrupt control" "0,1,2,3"
bitfld.long 0x10 2.--3. "P1,P1 interrupt control" "0,1,2,3"
bitfld.long 0x10 0.--1. "P0,P0 interrupt control" "0,1,2,3"
tree.end
tree "PC"
base ad:0x40001200
group.long 0x0++0x13
line.long 0x0 "MOD,Port n Mode Register"
bitfld.long 0x0 30.--31. "MODE15,Pin 15 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 28.--29. "MODE14,Pin 14 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 26.--27. "MODE13,Pin 13 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 24.--25. "MODE12,Pin 12 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 22.--23. "MODE11,Pin 11 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 20.--21. "MODE10,Pin 10 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 18.--19. "MODE9,Pin 9 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 16.--17. "MODE8,Pin 8 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 14.--15. "MODE7,Pin 7 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 12.--13. "MODE6,Pin 6 Mode Selection bits" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "MODE5,Pin 5 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 8.--9. "MODE4,Pin 4 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 6.--7. "MODE3,Pin 3 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 4.--5. "MODE2,Pin 2 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 2.--3. "MODE1,Pin 1 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 0.--1. "MODE0,Pin 0 Mode Selection bits" "0,1,2,3"
line.long 0x4 "TYP,Port n Output Type Selection Register"
bitfld.long 0x4 15. "TYP15,Pin 15 Output Type Selection bit" "0,1"
bitfld.long 0x4 14. "TYP14,Pin 15 Output Type Selection bit" "0,1"
bitfld.long 0x4 13. "TYP13,Pin 13 Output Type Selection bit" "0,1"
bitfld.long 0x4 12. "TYP12,Pin 12 Output Type Selection bit" "0,1"
bitfld.long 0x4 11. "TYP11,Pin 11 Output Type Selection bit" "0,1"
bitfld.long 0x4 10. "TYP10,Pin 10 Output Type Selection bit" "0,1"
bitfld.long 0x4 9. "TYP9,Pin 9 Output Type Selection bit" "0,1"
bitfld.long 0x4 8. "TYP8,Pin 8 Output Type Selection bit" "0,1"
bitfld.long 0x4 7. "TYP7,Pin 7 Output Type Selection bit" "0,1"
bitfld.long 0x4 6. "TYP6,Pin 6 Output Type Selection bit" "0,1"
newline
bitfld.long 0x4 5. "TYP5,Pin 5 Output Type Selection bit" "0,1"
bitfld.long 0x4 4. "TYP4,Pin 4 Output Type Selection bit" "0,1"
bitfld.long 0x4 3. "TYP3,Pin 3 Output Type Selection bit" "0,1"
bitfld.long 0x4 2. "TYP2,Pin 2 Output Type Selection bit" "0,1"
bitfld.long 0x4 1. "TYP1,Pin 1 Output Type Selection bit" "0,1"
bitfld.long 0x4 0. "TYP0,Pin 0 Output Type Selection bit" "0,1"
line.long 0x8 "AFSR1,Port n Alternative Function Selection Register 1"
hexmask.long.byte 0x8 28.--31. 1. "AFSR7,Pin 7 Alternative Function Selection bits"
hexmask.long.byte 0x8 24.--27. 1. "AFSR6,Pin 6 Alternative Function Selection bits"
hexmask.long.byte 0x8 20.--23. 1. "AFSR5,Pin 5 Alternative Function Selection bits"
hexmask.long.byte 0x8 16.--19. 1. "AFSR4,Pin 4 Alternative Function Selection bits"
hexmask.long.byte 0x8 12.--15. 1. "AFSR3,Pin 3 Alternative Function Selection bits"
hexmask.long.byte 0x8 8.--11. 1. "AFSR2,Pin 2 Alternative Function Selection bits"
hexmask.long.byte 0x8 4.--7. 1. "AFSR1,Pin 1 Alternative Function Selection bits"
hexmask.long.byte 0x8 0.--3. 1. "AFSR0,Pin 0 Alternative Function Selection bits"
line.long 0xC "AFSR2,Port n Alternative Function Selection Register 2"
hexmask.long.byte 0xC 28.--31. 1. "AFSR15,Pin 15 Alternative Function Selection bits"
hexmask.long.byte 0xC 24.--27. 1. "AFSR14,Pin 14 Alternative Function Selection bits"
hexmask.long.byte 0xC 20.--23. 1. "AFSR13,Pin 13 Alternative Function Selection bits"
hexmask.long.byte 0xC 16.--19. 1. "AFSR12,Pin 12 Alternative Function Selection bits"
hexmask.long.byte 0xC 12.--15. 1. "AFSR11,Pin 11 Alternative Function Selection bits"
hexmask.long.byte 0xC 8.--11. 1. "AFSR10,Pin 10 Alternative Function Selection bits"
hexmask.long.byte 0xC 4.--7. 1. "AFSR9,Pin 9 Alternative Function Selection bits"
hexmask.long.byte 0xC 0.--3. 1. "AFSR8,Pin 8 Alternative Function Selection bits"
line.long 0x10 "PUPD,Port n Pull-up/down Resistor Selection Register"
bitfld.long 0x10 30.--31. "PUPD15,Pin 15 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 28.--29. "PUPD14,Pin 14 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 26.--27. "PUPD13,Pin 13 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 24.--25. "PUPD12,Pin 12 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 22.--23. "PUPD11,Pin 11 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 20.--21. "PUPD10,Pin 10 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 18.--19. "PUPD9,Pin 9 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 16.--17. "PUPD8,Pin 8 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 14.--15. "PUPD7,Pin 7 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 12.--13. "PUPD6,Pin 6 Pull-up/down Resistor Selection bits" "0,1,2,3"
newline
bitfld.long 0x10 10.--11. "PUPD5,Pin 5 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 8.--9. "PUPD4,Pin 4 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 6.--7. "PUPD3,Pin 3 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 4.--5. "PUPD2,Pin 2 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 2.--3. "PUPD1,Pin 1 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 0.--1. "PUPD0,Pin 0 Pull-up/down Resistor Selection bits" "0,1,2,3"
rgroup.long 0x14++0x3
line.long 0x0 "INDR,Port n Input Data Register"
bitfld.long 0x0 15. "INDR15,Pin 15 Input Data bit" "0,1"
bitfld.long 0x0 14. "INDR14,Pin 14 Input Data bit" "0,1"
bitfld.long 0x0 13. "INDR13,Pin 13 Input Data bit" "0,1"
bitfld.long 0x0 12. "INDR12,Pin 12 Input Data bit" "0,1"
bitfld.long 0x0 11. "INDR11,Pin 11 Input Data bit" "0,1"
bitfld.long 0x0 10. "INDR10,Pin 10 Input Data bit" "0,1"
bitfld.long 0x0 9. "INDR9,Pin 9 Input Data bit" "0,1"
bitfld.long 0x0 8. "INDR8,Pin 8 Input Data bit" "0,1"
bitfld.long 0x0 7. "INDR7,Pin 7 Input Data bit" "0,1"
bitfld.long 0x0 6. "INDR6,Pin 6 Input Data bit" "0,1"
newline
bitfld.long 0x0 5. "INDR5,Pin 5 Input Data bit" "0,1"
bitfld.long 0x0 4. "INDR4,Pin 4 Input Data bit" "0,1"
bitfld.long 0x0 3. "INDR3,Pin 3 Input Data bit" "0,1"
bitfld.long 0x0 2. "INDR2,Pin 2 Input Data bit" "0,1"
bitfld.long 0x0 1. "INDR1,Pin 1 Input Data bit" "0,1"
bitfld.long 0x0 0. "INDR0,Pin 0 Input Data bit" "0,1"
group.long 0x18++0x3
line.long 0x0 "OUTDR,Port n Output Data Register"
bitfld.long 0x0 15. "OUTDR15,Pin 15 Output Data bit" "0,1"
bitfld.long 0x0 14. "OUTDR14,Pin 14 Output Data bit" "0,1"
bitfld.long 0x0 13. "OUTDR13,Pin 13 Output Data bit" "0,1"
bitfld.long 0x0 12. "OUTDR12,Pin 12 Output Data bit" "0,1"
bitfld.long 0x0 11. "OUTDR11,Pin 11 Output Data bit" "0,1"
bitfld.long 0x0 10. "OUTDR10,Pin 10 Output Data bit" "0,1"
bitfld.long 0x0 9. "OUTDR9,Pin 9 Output Data bit" "0,1"
bitfld.long 0x0 8. "OUTDR8,Pin 8 Output Data bit" "0,1"
bitfld.long 0x0 7. "OUTDR7,Pin 7 Output Data bit" "0,1"
bitfld.long 0x0 6. "OUTDR6,Pin 6 Output Data bit" "0,1"
newline
bitfld.long 0x0 5. "OUTDR5,Pin 5 Output Data bit" "0,1"
bitfld.long 0x0 4. "OUTDR4,Pin 4 Output Data bit" "0,1"
bitfld.long 0x0 3. "OUTDR3,Pin 3 Output Data bit" "0,1"
bitfld.long 0x0 2. "OUTDR2,Pin 2 Output Data bit" "0,1"
bitfld.long 0x0 1. "OUTDR1,Pin 1 Output Data bit" "0,1"
bitfld.long 0x0 0. "OUTDR0,Pin 0 Output Data bit" "0,1"
wgroup.long 0x1C++0x7
line.long 0x0 "BSR,Port n Output Bit Set Register"
bitfld.long 0x0 15. "BSR15,Pin 15 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 14. "BSR14,Pin 14 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 13. "BSR13,Pin 13 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 12. "BSR12,Pin 12 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 11. "BSR11,Pin 11 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 10. "BSR10,Pin 10 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 9. "BSR9,Pin 9 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 8. "BSR8,Pin 8 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 7. "BSR7,Pin 7 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 6. "BSR6,Pin 6 Output Set bit. This bit is always read to 0" "0,1"
newline
bitfld.long 0x0 5. "BSR5,Pin 5 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 4. "BSR4,Pin 4 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 3. "BSR3,Pin 3 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 2. "BSR2,Pin 2 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 1. "BSR1,Pin 1 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 0. "BSR0,Pin 0 Output Set bit. This bit is always read to 0" "0,1"
line.long 0x4 "BCR,Port n Output Bit Clear Register"
bitfld.long 0x4 15. "BCR15,Pin 15 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 14. "BCR14,Pin 14 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 13. "BCR13,Pin 13 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 12. "BCR12,Pin 12 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 11. "BCR11,Pin 11 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 10. "BCR10,Pin 10 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 9. "BCR9,Pin 9 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 8. "BCR8,Pin 8 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 7. "BCR7,Pin 7 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 6. "BCR6,Pin 6 Output Clear bit. This bit is always read to 0." "0,1"
newline
bitfld.long 0x4 5. "BCR5,Pin 5 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 4. "BCR4,Pin 4 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 3. "BCR3,Pin 3 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 2. "BCR2,Pin 2 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 1. "BCR1,Pin 1 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 0. "BCR0,Pin 0 Output Clear bit. This bit is always read to 0." "0,1"
group.long 0x24++0x13
line.long 0x0 "OUTDMSK,Port n Output Data Mask Register"
bitfld.long 0x0 15. "OUTDMSK15,Pin 15 Output Data Mask bit" "0,1"
bitfld.long 0x0 14. "OUTDMSK14,Pin 14 Output Data Mask bit" "0,1"
bitfld.long 0x0 13. "OUTDMSK13,Pin 13 Output Data Mask bit" "0,1"
bitfld.long 0x0 12. "OUTDMSK12,Pin 12 Output Data Mask bit" "0,1"
bitfld.long 0x0 11. "OUTDMSK11,Pin 11 Output Data Mask bit" "0,1"
bitfld.long 0x0 10. "OUTDMSK10,Pin 10 Output Data Mask bit" "0,1"
bitfld.long 0x0 9. "OUTDMSK9,Pin 9 Output Data Mask bit" "0,1"
bitfld.long 0x0 8. "OUTDMSK8,Pin 8 Output Data Mask bit" "0,1"
bitfld.long 0x0 7. "OUTDMSK7,Pin 7 Output Data Mask bit" "0,1"
bitfld.long 0x0 6. "OUTDMSK6,Pin 6 Output Data Mask bit" "0,1"
newline
bitfld.long 0x0 5. "OUTDMSK5,Pin 5 Output Data Mask bit" "0,1"
bitfld.long 0x0 4. "OUTDMSK4,Pin 4 Output Data Mask bit" "0,1"
bitfld.long 0x0 3. "OUTDMSK3,Pin 3 Output Data Mask bit" "0,1"
bitfld.long 0x0 2. "OUTDMSK2,Pin 2 Output Data Mask bit" "0,1"
bitfld.long 0x0 1. "OUTDMSK1,Pin 1 Output Data Mask bit" "0,1"
bitfld.long 0x0 0. "OUTDMSK0,Pin 0 Output Data Mask bit" "0,1"
line.long 0x4 "DBCR,Port n Debounce Control Register"
bitfld.long 0x4 15. "DBEN15,Pin 15 Debounce Enable bit" "0,1"
bitfld.long 0x4 14. "DBEN14,Pin 14 Debounce Enable bit" "0,1"
bitfld.long 0x4 13. "DBEN13,Pin 13 Debounce Enable bit" "0,1"
bitfld.long 0x4 12. "DBEN12,Pin 12 Debounce Enable bit" "0,1"
bitfld.long 0x4 11. "DBEN11,Pin 11 Debounce Enable bit" "0,1"
bitfld.long 0x4 10. "DBEN10,Pin 10 Debounce Enable bit" "0,1"
bitfld.long 0x4 9. "DBEN9,Pin 9 Debounce Enable bit" "0,1"
bitfld.long 0x4 8. "DBEN8,Pin 8 Debounce Enable bit" "0,1"
bitfld.long 0x4 7. "DBEN7,Pin 7 Debounce Enable bit" "0,1"
bitfld.long 0x4 6. "DBEN6,Pin 6 Debounce Enable bit" "0,1"
newline
bitfld.long 0x4 5. "DBEN5,Pin 5 Debounce Enable bit" "0,1"
bitfld.long 0x4 4. "DBEN4,Pin 4 Debounce Enable bit" "0,1"
bitfld.long 0x4 3. "DBEN3,Pin 3 Debounce Enable bit" "0,1"
bitfld.long 0x4 2. "DBEN2,Pin 2 Debounce Enable bit" "0,1"
bitfld.long 0x4 1. "DBEN1,Pin 1 Debounce Enable bit" "0,1"
bitfld.long 0x4 0. "DBEN0,Pin 0 Debounce Enable bit" "0,1"
line.long 0x8 "IER,Port n interrupt enable register"
bitfld.long 0x8 30.--31. "P15,P15 interrupt enable" "0,1,2,3"
bitfld.long 0x8 28.--29. "P14,P14 interrupt enable" "0,1,2,3"
bitfld.long 0x8 26.--27. "P13,P13 interrupt enable" "0,1,2,3"
bitfld.long 0x8 24.--25. "P12,P12 interrupt enable" "0,1,2,3"
bitfld.long 0x8 22.--23. "P11,P11 interrupt enable" "0,1,2,3"
bitfld.long 0x8 20.--21. "P10,P10 interrupt enable" "0,1,2,3"
bitfld.long 0x8 18.--19. "P9,P9 interrupt enable" "0,1,2,3"
bitfld.long 0x8 16.--17. "P8,P8 interrupt enable" "0,1,2,3"
bitfld.long 0x8 14.--15. "P7,P7 interrupt enable" "0,1,2,3"
bitfld.long 0x8 12.--13. "P6,P6 interrupt enable" "0,1,2,3"
newline
bitfld.long 0x8 10.--11. "P5,P5 interrupt enable" "0,1,2,3"
bitfld.long 0x8 8.--9. "P4,P4 interrupt enable" "0,1,2,3"
bitfld.long 0x8 6.--7. "P3,P3 interrupt enable" "0,1,2,3"
bitfld.long 0x8 4.--5. "P2,P2 interrupt enable" "0,1,2,3"
bitfld.long 0x8 2.--3. "P1,P1 interrupt enable" "0,1,2,3"
bitfld.long 0x8 0.--1. "P0,P0 interrupt enable" "0,1,2,3"
line.long 0xC "ISR,Port n interrupt status register"
bitfld.long 0xC 30.--31. "P15,P15 interrupt status" "0,1,2,3"
bitfld.long 0xC 28.--29. "P14,P14 interrupt status" "0,1,2,3"
bitfld.long 0xC 26.--27. "P13,P13 interrupt status" "0,1,2,3"
bitfld.long 0xC 24.--25. "P12,P12 interrupt status" "0,1,2,3"
bitfld.long 0xC 22.--23. "P11,P11 interrupt status" "0,1,2,3"
bitfld.long 0xC 20.--21. "P10,P10 interrupt status" "0,1,2,3"
bitfld.long 0xC 18.--19. "P9,P9 interrupt status" "0,1,2,3"
bitfld.long 0xC 16.--17. "P8,P8 interrupt status" "0,1,2,3"
bitfld.long 0xC 14.--15. "P7,P7 interrupt status" "0,1,2,3"
bitfld.long 0xC 12.--13. "P6,P6 interrupt status" "0,1,2,3"
newline
bitfld.long 0xC 10.--11. "P5,P5 interrupt status" "0,1,2,3"
bitfld.long 0xC 8.--9. "P4,P4 interrupt status" "0,1,2,3"
bitfld.long 0xC 6.--7. "P3,P3 interrupt status" "0,1,2,3"
bitfld.long 0xC 4.--5. "P2,P2 interrupt status" "0,1,2,3"
bitfld.long 0xC 2.--3. "P1,P1 interrupt status" "0,1,2,3"
bitfld.long 0xC 0.--1. "P0,P0 interrupt status" "0,1,2,3"
line.long 0x10 "ICR,Port n interrupt control register"
bitfld.long 0x10 30.--31. "P15,P15 interrupt control" "0,1,2,3"
bitfld.long 0x10 28.--29. "P14,P14 interrupt control" "0,1,2,3"
bitfld.long 0x10 26.--27. "P13,P13 interrupt control" "0,1,2,3"
bitfld.long 0x10 24.--25. "P12,P12 interrupt control" "0,1,2,3"
bitfld.long 0x10 22.--23. "P11,P11 interrupt control" "0,1,2,3"
bitfld.long 0x10 20.--21. "P10,P10 interrupt control" "0,1,2,3"
bitfld.long 0x10 18.--19. "P9,P9 interrupt control" "0,1,2,3"
bitfld.long 0x10 16.--17. "P8,P8 interrupt control" "0,1,2,3"
bitfld.long 0x10 14.--15. "P7,P7 interrupt control" "0,1,2,3"
bitfld.long 0x10 12.--13. "P6,P6 interrupt control" "0,1,2,3"
newline
bitfld.long 0x10 10.--11. "P5,P5 interrupt control" "0,1,2,3"
bitfld.long 0x10 8.--9. "P4,P4 interrupt control" "0,1,2,3"
bitfld.long 0x10 6.--7. "P3,P3 interrupt control" "0,1,2,3"
bitfld.long 0x10 4.--5. "P2,P2 interrupt control" "0,1,2,3"
bitfld.long 0x10 2.--3. "P1,P1 interrupt control" "0,1,2,3"
bitfld.long 0x10 0.--1. "P0,P0 interrupt control" "0,1,2,3"
tree.end
sif (cpuis("A31G31*"))
tree "PD"
base ad:0x40001300
group.long 0x0++0x13
line.long 0x0 "MOD,Port n Mode Register"
bitfld.long 0x0 30.--31. "MODE15,Pin 15 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 28.--29. "MODE14,Pin 14 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 26.--27. "MODE13,Pin 13 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 24.--25. "MODE12,Pin 12 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 22.--23. "MODE11,Pin 11 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 20.--21. "MODE10,Pin 10 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 18.--19. "MODE9,Pin 9 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 16.--17. "MODE8,Pin 8 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 14.--15. "MODE7,Pin 7 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 12.--13. "MODE6,Pin 6 Mode Selection bits" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "MODE5,Pin 5 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 8.--9. "MODE4,Pin 4 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 6.--7. "MODE3,Pin 3 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 4.--5. "MODE2,Pin 2 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 2.--3. "MODE1,Pin 1 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 0.--1. "MODE0,Pin 0 Mode Selection bits" "0,1,2,3"
line.long 0x4 "TYP,Port n Output Type Selection Register"
bitfld.long 0x4 15. "TYP15,Pin 15 Output Type Selection bit" "0,1"
bitfld.long 0x4 14. "TYP14,Pin 15 Output Type Selection bit" "0,1"
bitfld.long 0x4 13. "TYP13,Pin 13 Output Type Selection bit" "0,1"
bitfld.long 0x4 12. "TYP12,Pin 12 Output Type Selection bit" "0,1"
bitfld.long 0x4 11. "TYP11,Pin 11 Output Type Selection bit" "0,1"
bitfld.long 0x4 10. "TYP10,Pin 10 Output Type Selection bit" "0,1"
bitfld.long 0x4 9. "TYP9,Pin 9 Output Type Selection bit" "0,1"
bitfld.long 0x4 8. "TYP8,Pin 8 Output Type Selection bit" "0,1"
bitfld.long 0x4 7. "TYP7,Pin 7 Output Type Selection bit" "0,1"
bitfld.long 0x4 6. "TYP6,Pin 6 Output Type Selection bit" "0,1"
newline
bitfld.long 0x4 5. "TYP5,Pin 5 Output Type Selection bit" "0,1"
bitfld.long 0x4 4. "TYP4,Pin 4 Output Type Selection bit" "0,1"
bitfld.long 0x4 3. "TYP3,Pin 3 Output Type Selection bit" "0,1"
bitfld.long 0x4 2. "TYP2,Pin 2 Output Type Selection bit" "0,1"
bitfld.long 0x4 1. "TYP1,Pin 1 Output Type Selection bit" "0,1"
bitfld.long 0x4 0. "TYP0,Pin 0 Output Type Selection bit" "0,1"
line.long 0x8 "AFSR1,Port n Alternative Function Selection Register 1"
hexmask.long.byte 0x8 28.--31. 1. "AFSR7,Pin 7 Alternative Function Selection bits"
hexmask.long.byte 0x8 24.--27. 1. "AFSR6,Pin 6 Alternative Function Selection bits"
hexmask.long.byte 0x8 20.--23. 1. "AFSR5,Pin 5 Alternative Function Selection bits"
hexmask.long.byte 0x8 16.--19. 1. "AFSR4,Pin 4 Alternative Function Selection bits"
hexmask.long.byte 0x8 12.--15. 1. "AFSR3,Pin 3 Alternative Function Selection bits"
hexmask.long.byte 0x8 8.--11. 1. "AFSR2,Pin 2 Alternative Function Selection bits"
hexmask.long.byte 0x8 4.--7. 1. "AFSR1,Pin 1 Alternative Function Selection bits"
hexmask.long.byte 0x8 0.--3. 1. "AFSR0,Pin 0 Alternative Function Selection bits"
line.long 0xC "AFSR2,Port n Alternative Function Selection Register 2"
hexmask.long.byte 0xC 28.--31. 1. "AFSR15,Pin 15 Alternative Function Selection bits"
hexmask.long.byte 0xC 24.--27. 1. "AFSR14,Pin 14 Alternative Function Selection bits"
hexmask.long.byte 0xC 20.--23. 1. "AFSR13,Pin 13 Alternative Function Selection bits"
hexmask.long.byte 0xC 16.--19. 1. "AFSR12,Pin 12 Alternative Function Selection bits"
hexmask.long.byte 0xC 12.--15. 1. "AFSR11,Pin 11 Alternative Function Selection bits"
hexmask.long.byte 0xC 8.--11. 1. "AFSR10,Pin 10 Alternative Function Selection bits"
hexmask.long.byte 0xC 4.--7. 1. "AFSR9,Pin 9 Alternative Function Selection bits"
hexmask.long.byte 0xC 0.--3. 1. "AFSR8,Pin 8 Alternative Function Selection bits"
line.long 0x10 "PUPD,Port n Pull-up/down Resistor Selection Register"
bitfld.long 0x10 30.--31. "PUPD15,Pin 15 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 28.--29. "PUPD14,Pin 14 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 26.--27. "PUPD13,Pin 13 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 24.--25. "PUPD12,Pin 12 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 22.--23. "PUPD11,Pin 11 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 20.--21. "PUPD10,Pin 10 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 18.--19. "PUPD9,Pin 9 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 16.--17. "PUPD8,Pin 8 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 14.--15. "PUPD7,Pin 7 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 12.--13. "PUPD6,Pin 6 Pull-up/down Resistor Selection bits" "0,1,2,3"
newline
bitfld.long 0x10 10.--11. "PUPD5,Pin 5 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 8.--9. "PUPD4,Pin 4 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 6.--7. "PUPD3,Pin 3 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 4.--5. "PUPD2,Pin 2 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 2.--3. "PUPD1,Pin 1 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 0.--1. "PUPD0,Pin 0 Pull-up/down Resistor Selection bits" "0,1,2,3"
rgroup.long 0x14++0x3
line.long 0x0 "INDR,Port n Input Data Register"
bitfld.long 0x0 15. "INDR15,Pin 15 Input Data bit" "0,1"
bitfld.long 0x0 14. "INDR14,Pin 14 Input Data bit" "0,1"
bitfld.long 0x0 13. "INDR13,Pin 13 Input Data bit" "0,1"
bitfld.long 0x0 12. "INDR12,Pin 12 Input Data bit" "0,1"
bitfld.long 0x0 11. "INDR11,Pin 11 Input Data bit" "0,1"
bitfld.long 0x0 10. "INDR10,Pin 10 Input Data bit" "0,1"
bitfld.long 0x0 9. "INDR9,Pin 9 Input Data bit" "0,1"
bitfld.long 0x0 8. "INDR8,Pin 8 Input Data bit" "0,1"
bitfld.long 0x0 7. "INDR7,Pin 7 Input Data bit" "0,1"
bitfld.long 0x0 6. "INDR6,Pin 6 Input Data bit" "0,1"
newline
bitfld.long 0x0 5. "INDR5,Pin 5 Input Data bit" "0,1"
bitfld.long 0x0 4. "INDR4,Pin 4 Input Data bit" "0,1"
bitfld.long 0x0 3. "INDR3,Pin 3 Input Data bit" "0,1"
bitfld.long 0x0 2. "INDR2,Pin 2 Input Data bit" "0,1"
bitfld.long 0x0 1. "INDR1,Pin 1 Input Data bit" "0,1"
bitfld.long 0x0 0. "INDR0,Pin 0 Input Data bit" "0,1"
group.long 0x18++0x3
line.long 0x0 "OUTDR,Port n Output Data Register"
bitfld.long 0x0 15. "OUTDR15,Pin 15 Output Data bit" "0,1"
bitfld.long 0x0 14. "OUTDR14,Pin 14 Output Data bit" "0,1"
bitfld.long 0x0 13. "OUTDR13,Pin 13 Output Data bit" "0,1"
bitfld.long 0x0 12. "OUTDR12,Pin 12 Output Data bit" "0,1"
bitfld.long 0x0 11. "OUTDR11,Pin 11 Output Data bit" "0,1"
bitfld.long 0x0 10. "OUTDR10,Pin 10 Output Data bit" "0,1"
bitfld.long 0x0 9. "OUTDR9,Pin 9 Output Data bit" "0,1"
bitfld.long 0x0 8. "OUTDR8,Pin 8 Output Data bit" "0,1"
bitfld.long 0x0 7. "OUTDR7,Pin 7 Output Data bit" "0,1"
bitfld.long 0x0 6. "OUTDR6,Pin 6 Output Data bit" "0,1"
newline
bitfld.long 0x0 5. "OUTDR5,Pin 5 Output Data bit" "0,1"
bitfld.long 0x0 4. "OUTDR4,Pin 4 Output Data bit" "0,1"
bitfld.long 0x0 3. "OUTDR3,Pin 3 Output Data bit" "0,1"
bitfld.long 0x0 2. "OUTDR2,Pin 2 Output Data bit" "0,1"
bitfld.long 0x0 1. "OUTDR1,Pin 1 Output Data bit" "0,1"
bitfld.long 0x0 0. "OUTDR0,Pin 0 Output Data bit" "0,1"
wgroup.long 0x1C++0x7
line.long 0x0 "BSR,Port n Output Bit Set Register"
bitfld.long 0x0 15. "BSR15,Pin 15 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 14. "BSR14,Pin 14 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 13. "BSR13,Pin 13 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 12. "BSR12,Pin 12 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 11. "BSR11,Pin 11 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 10. "BSR10,Pin 10 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 9. "BSR9,Pin 9 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 8. "BSR8,Pin 8 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 7. "BSR7,Pin 7 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 6. "BSR6,Pin 6 Output Set bit. This bit is always read to 0" "0,1"
newline
bitfld.long 0x0 5. "BSR5,Pin 5 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 4. "BSR4,Pin 4 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 3. "BSR3,Pin 3 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 2. "BSR2,Pin 2 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 1. "BSR1,Pin 1 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 0. "BSR0,Pin 0 Output Set bit. This bit is always read to 0" "0,1"
line.long 0x4 "BCR,Port n Output Bit Clear Register"
bitfld.long 0x4 15. "BCR15,Pin 15 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 14. "BCR14,Pin 14 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 13. "BCR13,Pin 13 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 12. "BCR12,Pin 12 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 11. "BCR11,Pin 11 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 10. "BCR10,Pin 10 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 9. "BCR9,Pin 9 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 8. "BCR8,Pin 8 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 7. "BCR7,Pin 7 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 6. "BCR6,Pin 6 Output Clear bit. This bit is always read to 0." "0,1"
newline
bitfld.long 0x4 5. "BCR5,Pin 5 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 4. "BCR4,Pin 4 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 3. "BCR3,Pin 3 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 2. "BCR2,Pin 2 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 1. "BCR1,Pin 1 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 0. "BCR0,Pin 0 Output Clear bit. This bit is always read to 0." "0,1"
group.long 0x24++0x13
line.long 0x0 "OUTDMSK,Port n Output Data Mask Register"
bitfld.long 0x0 15. "OUTDMSK15,Pin 15 Output Data Mask bit" "0,1"
bitfld.long 0x0 14. "OUTDMSK14,Pin 14 Output Data Mask bit" "0,1"
bitfld.long 0x0 13. "OUTDMSK13,Pin 13 Output Data Mask bit" "0,1"
bitfld.long 0x0 12. "OUTDMSK12,Pin 12 Output Data Mask bit" "0,1"
bitfld.long 0x0 11. "OUTDMSK11,Pin 11 Output Data Mask bit" "0,1"
bitfld.long 0x0 10. "OUTDMSK10,Pin 10 Output Data Mask bit" "0,1"
bitfld.long 0x0 9. "OUTDMSK9,Pin 9 Output Data Mask bit" "0,1"
bitfld.long 0x0 8. "OUTDMSK8,Pin 8 Output Data Mask bit" "0,1"
bitfld.long 0x0 7. "OUTDMSK7,Pin 7 Output Data Mask bit" "0,1"
bitfld.long 0x0 6. "OUTDMSK6,Pin 6 Output Data Mask bit" "0,1"
newline
bitfld.long 0x0 5. "OUTDMSK5,Pin 5 Output Data Mask bit" "0,1"
bitfld.long 0x0 4. "OUTDMSK4,Pin 4 Output Data Mask bit" "0,1"
bitfld.long 0x0 3. "OUTDMSK3,Pin 3 Output Data Mask bit" "0,1"
bitfld.long 0x0 2. "OUTDMSK2,Pin 2 Output Data Mask bit" "0,1"
bitfld.long 0x0 1. "OUTDMSK1,Pin 1 Output Data Mask bit" "0,1"
bitfld.long 0x0 0. "OUTDMSK0,Pin 0 Output Data Mask bit" "0,1"
line.long 0x4 "DBCR,Port n Debounce Control Register"
bitfld.long 0x4 15. "DBEN15,Pin 15 Debounce Enable bit" "0,1"
bitfld.long 0x4 14. "DBEN14,Pin 14 Debounce Enable bit" "0,1"
bitfld.long 0x4 13. "DBEN13,Pin 13 Debounce Enable bit" "0,1"
bitfld.long 0x4 12. "DBEN12,Pin 12 Debounce Enable bit" "0,1"
bitfld.long 0x4 11. "DBEN11,Pin 11 Debounce Enable bit" "0,1"
bitfld.long 0x4 10. "DBEN10,Pin 10 Debounce Enable bit" "0,1"
bitfld.long 0x4 9. "DBEN9,Pin 9 Debounce Enable bit" "0,1"
bitfld.long 0x4 8. "DBEN8,Pin 8 Debounce Enable bit" "0,1"
bitfld.long 0x4 7. "DBEN7,Pin 7 Debounce Enable bit" "0,1"
bitfld.long 0x4 6. "DBEN6,Pin 6 Debounce Enable bit" "0,1"
newline
bitfld.long 0x4 5. "DBEN5,Pin 5 Debounce Enable bit" "0,1"
bitfld.long 0x4 4. "DBEN4,Pin 4 Debounce Enable bit" "0,1"
bitfld.long 0x4 3. "DBEN3,Pin 3 Debounce Enable bit" "0,1"
bitfld.long 0x4 2. "DBEN2,Pin 2 Debounce Enable bit" "0,1"
bitfld.long 0x4 1. "DBEN1,Pin 1 Debounce Enable bit" "0,1"
bitfld.long 0x4 0. "DBEN0,Pin 0 Debounce Enable bit" "0,1"
line.long 0x8 "IER,Port n interrupt enable register"
bitfld.long 0x8 30.--31. "P15,P15 interrupt enable" "0,1,2,3"
bitfld.long 0x8 28.--29. "P14,P14 interrupt enable" "0,1,2,3"
bitfld.long 0x8 26.--27. "P13,P13 interrupt enable" "0,1,2,3"
bitfld.long 0x8 24.--25. "P12,P12 interrupt enable" "0,1,2,3"
bitfld.long 0x8 22.--23. "P11,P11 interrupt enable" "0,1,2,3"
bitfld.long 0x8 20.--21. "P10,P10 interrupt enable" "0,1,2,3"
bitfld.long 0x8 18.--19. "P9,P9 interrupt enable" "0,1,2,3"
bitfld.long 0x8 16.--17. "P8,P8 interrupt enable" "0,1,2,3"
bitfld.long 0x8 14.--15. "P7,P7 interrupt enable" "0,1,2,3"
bitfld.long 0x8 12.--13. "P6,P6 interrupt enable" "0,1,2,3"
newline
bitfld.long 0x8 10.--11. "P5,P5 interrupt enable" "0,1,2,3"
bitfld.long 0x8 8.--9. "P4,P4 interrupt enable" "0,1,2,3"
bitfld.long 0x8 6.--7. "P3,P3 interrupt enable" "0,1,2,3"
bitfld.long 0x8 4.--5. "P2,P2 interrupt enable" "0,1,2,3"
bitfld.long 0x8 2.--3. "P1,P1 interrupt enable" "0,1,2,3"
bitfld.long 0x8 0.--1. "P0,P0 interrupt enable" "0,1,2,3"
line.long 0xC "ISR,Port n interrupt status register"
bitfld.long 0xC 30.--31. "P15,P15 interrupt status" "0,1,2,3"
bitfld.long 0xC 28.--29. "P14,P14 interrupt status" "0,1,2,3"
bitfld.long 0xC 26.--27. "P13,P13 interrupt status" "0,1,2,3"
bitfld.long 0xC 24.--25. "P12,P12 interrupt status" "0,1,2,3"
bitfld.long 0xC 22.--23. "P11,P11 interrupt status" "0,1,2,3"
bitfld.long 0xC 20.--21. "P10,P10 interrupt status" "0,1,2,3"
bitfld.long 0xC 18.--19. "P9,P9 interrupt status" "0,1,2,3"
bitfld.long 0xC 16.--17. "P8,P8 interrupt status" "0,1,2,3"
bitfld.long 0xC 14.--15. "P7,P7 interrupt status" "0,1,2,3"
bitfld.long 0xC 12.--13. "P6,P6 interrupt status" "0,1,2,3"
newline
bitfld.long 0xC 10.--11. "P5,P5 interrupt status" "0,1,2,3"
bitfld.long 0xC 8.--9. "P4,P4 interrupt status" "0,1,2,3"
bitfld.long 0xC 6.--7. "P3,P3 interrupt status" "0,1,2,3"
bitfld.long 0xC 4.--5. "P2,P2 interrupt status" "0,1,2,3"
bitfld.long 0xC 2.--3. "P1,P1 interrupt status" "0,1,2,3"
bitfld.long 0xC 0.--1. "P0,P0 interrupt status" "0,1,2,3"
line.long 0x10 "ICR,Port n interrupt control register"
bitfld.long 0x10 30.--31. "P15,P15 interrupt control" "0,1,2,3"
bitfld.long 0x10 28.--29. "P14,P14 interrupt control" "0,1,2,3"
bitfld.long 0x10 26.--27. "P13,P13 interrupt control" "0,1,2,3"
bitfld.long 0x10 24.--25. "P12,P12 interrupt control" "0,1,2,3"
bitfld.long 0x10 22.--23. "P11,P11 interrupt control" "0,1,2,3"
bitfld.long 0x10 20.--21. "P10,P10 interrupt control" "0,1,2,3"
bitfld.long 0x10 18.--19. "P9,P9 interrupt control" "0,1,2,3"
bitfld.long 0x10 16.--17. "P8,P8 interrupt control" "0,1,2,3"
bitfld.long 0x10 14.--15. "P7,P7 interrupt control" "0,1,2,3"
bitfld.long 0x10 12.--13. "P6,P6 interrupt control" "0,1,2,3"
newline
bitfld.long 0x10 10.--11. "P5,P5 interrupt control" "0,1,2,3"
bitfld.long 0x10 8.--9. "P4,P4 interrupt control" "0,1,2,3"
bitfld.long 0x10 6.--7. "P3,P3 interrupt control" "0,1,2,3"
bitfld.long 0x10 4.--5. "P2,P2 interrupt control" "0,1,2,3"
bitfld.long 0x10 2.--3. "P1,P1 interrupt control" "0,1,2,3"
bitfld.long 0x10 0.--1. "P0,P0 interrupt control" "0,1,2,3"
tree.end
endif
sif (cpuis("A31G31*"))
tree "PE"
base ad:0x40001400
group.long 0x0++0x13
line.long 0x0 "MOD,Port n Mode Register"
bitfld.long 0x0 30.--31. "MODE15,Pin 15 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 28.--29. "MODE14,Pin 14 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 26.--27. "MODE13,Pin 13 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 24.--25. "MODE12,Pin 12 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 22.--23. "MODE11,Pin 11 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 20.--21. "MODE10,Pin 10 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 18.--19. "MODE9,Pin 9 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 16.--17. "MODE8,Pin 8 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 14.--15. "MODE7,Pin 7 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 12.--13. "MODE6,Pin 6 Mode Selection bits" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "MODE5,Pin 5 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 8.--9. "MODE4,Pin 4 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 6.--7. "MODE3,Pin 3 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 4.--5. "MODE2,Pin 2 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 2.--3. "MODE1,Pin 1 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 0.--1. "MODE0,Pin 0 Mode Selection bits" "0,1,2,3"
line.long 0x4 "TYP,Port n Output Type Selection Register"
bitfld.long 0x4 15. "TYP15,Pin 15 Output Type Selection bit" "0,1"
bitfld.long 0x4 14. "TYP14,Pin 15 Output Type Selection bit" "0,1"
bitfld.long 0x4 13. "TYP13,Pin 13 Output Type Selection bit" "0,1"
bitfld.long 0x4 12. "TYP12,Pin 12 Output Type Selection bit" "0,1"
bitfld.long 0x4 11. "TYP11,Pin 11 Output Type Selection bit" "0,1"
bitfld.long 0x4 10. "TYP10,Pin 10 Output Type Selection bit" "0,1"
bitfld.long 0x4 9. "TYP9,Pin 9 Output Type Selection bit" "0,1"
bitfld.long 0x4 8. "TYP8,Pin 8 Output Type Selection bit" "0,1"
bitfld.long 0x4 7. "TYP7,Pin 7 Output Type Selection bit" "0,1"
bitfld.long 0x4 6. "TYP6,Pin 6 Output Type Selection bit" "0,1"
newline
bitfld.long 0x4 5. "TYP5,Pin 5 Output Type Selection bit" "0,1"
bitfld.long 0x4 4. "TYP4,Pin 4 Output Type Selection bit" "0,1"
bitfld.long 0x4 3. "TYP3,Pin 3 Output Type Selection bit" "0,1"
bitfld.long 0x4 2. "TYP2,Pin 2 Output Type Selection bit" "0,1"
bitfld.long 0x4 1. "TYP1,Pin 1 Output Type Selection bit" "0,1"
bitfld.long 0x4 0. "TYP0,Pin 0 Output Type Selection bit" "0,1"
line.long 0x8 "AFSR1,Port n Alternative Function Selection Register 1"
hexmask.long.byte 0x8 28.--31. 1. "AFSR7,Pin 7 Alternative Function Selection bits"
hexmask.long.byte 0x8 24.--27. 1. "AFSR6,Pin 6 Alternative Function Selection bits"
hexmask.long.byte 0x8 20.--23. 1. "AFSR5,Pin 5 Alternative Function Selection bits"
hexmask.long.byte 0x8 16.--19. 1. "AFSR4,Pin 4 Alternative Function Selection bits"
hexmask.long.byte 0x8 12.--15. 1. "AFSR3,Pin 3 Alternative Function Selection bits"
hexmask.long.byte 0x8 8.--11. 1. "AFSR2,Pin 2 Alternative Function Selection bits"
hexmask.long.byte 0x8 4.--7. 1. "AFSR1,Pin 1 Alternative Function Selection bits"
hexmask.long.byte 0x8 0.--3. 1. "AFSR0,Pin 0 Alternative Function Selection bits"
line.long 0xC "AFSR2,Port n Alternative Function Selection Register 2"
hexmask.long.byte 0xC 28.--31. 1. "AFSR15,Pin 15 Alternative Function Selection bits"
hexmask.long.byte 0xC 24.--27. 1. "AFSR14,Pin 14 Alternative Function Selection bits"
hexmask.long.byte 0xC 20.--23. 1. "AFSR13,Pin 13 Alternative Function Selection bits"
hexmask.long.byte 0xC 16.--19. 1. "AFSR12,Pin 12 Alternative Function Selection bits"
hexmask.long.byte 0xC 12.--15. 1. "AFSR11,Pin 11 Alternative Function Selection bits"
hexmask.long.byte 0xC 8.--11. 1. "AFSR10,Pin 10 Alternative Function Selection bits"
hexmask.long.byte 0xC 4.--7. 1. "AFSR9,Pin 9 Alternative Function Selection bits"
hexmask.long.byte 0xC 0.--3. 1. "AFSR8,Pin 8 Alternative Function Selection bits"
line.long 0x10 "PUPD,Port n Pull-up/down Resistor Selection Register"
bitfld.long 0x10 30.--31. "PUPD15,Pin 15 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 28.--29. "PUPD14,Pin 14 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 26.--27. "PUPD13,Pin 13 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 24.--25. "PUPD12,Pin 12 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 22.--23. "PUPD11,Pin 11 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 20.--21. "PUPD10,Pin 10 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 18.--19. "PUPD9,Pin 9 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 16.--17. "PUPD8,Pin 8 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 14.--15. "PUPD7,Pin 7 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 12.--13. "PUPD6,Pin 6 Pull-up/down Resistor Selection bits" "0,1,2,3"
newline
bitfld.long 0x10 10.--11. "PUPD5,Pin 5 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 8.--9. "PUPD4,Pin 4 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 6.--7. "PUPD3,Pin 3 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 4.--5. "PUPD2,Pin 2 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 2.--3. "PUPD1,Pin 1 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 0.--1. "PUPD0,Pin 0 Pull-up/down Resistor Selection bits" "0,1,2,3"
rgroup.long 0x14++0x3
line.long 0x0 "INDR,Port n Input Data Register"
bitfld.long 0x0 15. "INDR15,Pin 15 Input Data bit" "0,1"
bitfld.long 0x0 14. "INDR14,Pin 14 Input Data bit" "0,1"
bitfld.long 0x0 13. "INDR13,Pin 13 Input Data bit" "0,1"
bitfld.long 0x0 12. "INDR12,Pin 12 Input Data bit" "0,1"
bitfld.long 0x0 11. "INDR11,Pin 11 Input Data bit" "0,1"
bitfld.long 0x0 10. "INDR10,Pin 10 Input Data bit" "0,1"
bitfld.long 0x0 9. "INDR9,Pin 9 Input Data bit" "0,1"
bitfld.long 0x0 8. "INDR8,Pin 8 Input Data bit" "0,1"
bitfld.long 0x0 7. "INDR7,Pin 7 Input Data bit" "0,1"
bitfld.long 0x0 6. "INDR6,Pin 6 Input Data bit" "0,1"
newline
bitfld.long 0x0 5. "INDR5,Pin 5 Input Data bit" "0,1"
bitfld.long 0x0 4. "INDR4,Pin 4 Input Data bit" "0,1"
bitfld.long 0x0 3. "INDR3,Pin 3 Input Data bit" "0,1"
bitfld.long 0x0 2. "INDR2,Pin 2 Input Data bit" "0,1"
bitfld.long 0x0 1. "INDR1,Pin 1 Input Data bit" "0,1"
bitfld.long 0x0 0. "INDR0,Pin 0 Input Data bit" "0,1"
group.long 0x18++0x3
line.long 0x0 "OUTDR,Port n Output Data Register"
bitfld.long 0x0 15. "OUTDR15,Pin 15 Output Data bit" "0,1"
bitfld.long 0x0 14. "OUTDR14,Pin 14 Output Data bit" "0,1"
bitfld.long 0x0 13. "OUTDR13,Pin 13 Output Data bit" "0,1"
bitfld.long 0x0 12. "OUTDR12,Pin 12 Output Data bit" "0,1"
bitfld.long 0x0 11. "OUTDR11,Pin 11 Output Data bit" "0,1"
bitfld.long 0x0 10. "OUTDR10,Pin 10 Output Data bit" "0,1"
bitfld.long 0x0 9. "OUTDR9,Pin 9 Output Data bit" "0,1"
bitfld.long 0x0 8. "OUTDR8,Pin 8 Output Data bit" "0,1"
bitfld.long 0x0 7. "OUTDR7,Pin 7 Output Data bit" "0,1"
bitfld.long 0x0 6. "OUTDR6,Pin 6 Output Data bit" "0,1"
newline
bitfld.long 0x0 5. "OUTDR5,Pin 5 Output Data bit" "0,1"
bitfld.long 0x0 4. "OUTDR4,Pin 4 Output Data bit" "0,1"
bitfld.long 0x0 3. "OUTDR3,Pin 3 Output Data bit" "0,1"
bitfld.long 0x0 2. "OUTDR2,Pin 2 Output Data bit" "0,1"
bitfld.long 0x0 1. "OUTDR1,Pin 1 Output Data bit" "0,1"
bitfld.long 0x0 0. "OUTDR0,Pin 0 Output Data bit" "0,1"
wgroup.long 0x1C++0x7
line.long 0x0 "BSR,Port n Output Bit Set Register"
bitfld.long 0x0 15. "BSR15,Pin 15 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 14. "BSR14,Pin 14 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 13. "BSR13,Pin 13 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 12. "BSR12,Pin 12 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 11. "BSR11,Pin 11 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 10. "BSR10,Pin 10 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 9. "BSR9,Pin 9 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 8. "BSR8,Pin 8 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 7. "BSR7,Pin 7 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 6. "BSR6,Pin 6 Output Set bit. This bit is always read to 0" "0,1"
newline
bitfld.long 0x0 5. "BSR5,Pin 5 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 4. "BSR4,Pin 4 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 3. "BSR3,Pin 3 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 2. "BSR2,Pin 2 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 1. "BSR1,Pin 1 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 0. "BSR0,Pin 0 Output Set bit. This bit is always read to 0" "0,1"
line.long 0x4 "BCR,Port n Output Bit Clear Register"
bitfld.long 0x4 15. "BCR15,Pin 15 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 14. "BCR14,Pin 14 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 13. "BCR13,Pin 13 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 12. "BCR12,Pin 12 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 11. "BCR11,Pin 11 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 10. "BCR10,Pin 10 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 9. "BCR9,Pin 9 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 8. "BCR8,Pin 8 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 7. "BCR7,Pin 7 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 6. "BCR6,Pin 6 Output Clear bit. This bit is always read to 0." "0,1"
newline
bitfld.long 0x4 5. "BCR5,Pin 5 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 4. "BCR4,Pin 4 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 3. "BCR3,Pin 3 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 2. "BCR2,Pin 2 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 1. "BCR1,Pin 1 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 0. "BCR0,Pin 0 Output Clear bit. This bit is always read to 0." "0,1"
group.long 0x24++0x13
line.long 0x0 "OUTDMSK,Port n Output Data Mask Register"
bitfld.long 0x0 15. "OUTDMSK15,Pin 15 Output Data Mask bit" "0,1"
bitfld.long 0x0 14. "OUTDMSK14,Pin 14 Output Data Mask bit" "0,1"
bitfld.long 0x0 13. "OUTDMSK13,Pin 13 Output Data Mask bit" "0,1"
bitfld.long 0x0 12. "OUTDMSK12,Pin 12 Output Data Mask bit" "0,1"
bitfld.long 0x0 11. "OUTDMSK11,Pin 11 Output Data Mask bit" "0,1"
bitfld.long 0x0 10. "OUTDMSK10,Pin 10 Output Data Mask bit" "0,1"
bitfld.long 0x0 9. "OUTDMSK9,Pin 9 Output Data Mask bit" "0,1"
bitfld.long 0x0 8. "OUTDMSK8,Pin 8 Output Data Mask bit" "0,1"
bitfld.long 0x0 7. "OUTDMSK7,Pin 7 Output Data Mask bit" "0,1"
bitfld.long 0x0 6. "OUTDMSK6,Pin 6 Output Data Mask bit" "0,1"
newline
bitfld.long 0x0 5. "OUTDMSK5,Pin 5 Output Data Mask bit" "0,1"
bitfld.long 0x0 4. "OUTDMSK4,Pin 4 Output Data Mask bit" "0,1"
bitfld.long 0x0 3. "OUTDMSK3,Pin 3 Output Data Mask bit" "0,1"
bitfld.long 0x0 2. "OUTDMSK2,Pin 2 Output Data Mask bit" "0,1"
bitfld.long 0x0 1. "OUTDMSK1,Pin 1 Output Data Mask bit" "0,1"
bitfld.long 0x0 0. "OUTDMSK0,Pin 0 Output Data Mask bit" "0,1"
line.long 0x4 "DBCR,Port n Debounce Control Register"
bitfld.long 0x4 15. "DBEN15,Pin 15 Debounce Enable bit" "0,1"
bitfld.long 0x4 14. "DBEN14,Pin 14 Debounce Enable bit" "0,1"
bitfld.long 0x4 13. "DBEN13,Pin 13 Debounce Enable bit" "0,1"
bitfld.long 0x4 12. "DBEN12,Pin 12 Debounce Enable bit" "0,1"
bitfld.long 0x4 11. "DBEN11,Pin 11 Debounce Enable bit" "0,1"
bitfld.long 0x4 10. "DBEN10,Pin 10 Debounce Enable bit" "0,1"
bitfld.long 0x4 9. "DBEN9,Pin 9 Debounce Enable bit" "0,1"
bitfld.long 0x4 8. "DBEN8,Pin 8 Debounce Enable bit" "0,1"
bitfld.long 0x4 7. "DBEN7,Pin 7 Debounce Enable bit" "0,1"
bitfld.long 0x4 6. "DBEN6,Pin 6 Debounce Enable bit" "0,1"
newline
bitfld.long 0x4 5. "DBEN5,Pin 5 Debounce Enable bit" "0,1"
bitfld.long 0x4 4. "DBEN4,Pin 4 Debounce Enable bit" "0,1"
bitfld.long 0x4 3. "DBEN3,Pin 3 Debounce Enable bit" "0,1"
bitfld.long 0x4 2. "DBEN2,Pin 2 Debounce Enable bit" "0,1"
bitfld.long 0x4 1. "DBEN1,Pin 1 Debounce Enable bit" "0,1"
bitfld.long 0x4 0. "DBEN0,Pin 0 Debounce Enable bit" "0,1"
line.long 0x8 "IER,Port n interrupt enable register"
bitfld.long 0x8 30.--31. "P15,P15 interrupt enable" "0,1,2,3"
bitfld.long 0x8 28.--29. "P14,P14 interrupt enable" "0,1,2,3"
bitfld.long 0x8 26.--27. "P13,P13 interrupt enable" "0,1,2,3"
bitfld.long 0x8 24.--25. "P12,P12 interrupt enable" "0,1,2,3"
bitfld.long 0x8 22.--23. "P11,P11 interrupt enable" "0,1,2,3"
bitfld.long 0x8 20.--21. "P10,P10 interrupt enable" "0,1,2,3"
bitfld.long 0x8 18.--19. "P9,P9 interrupt enable" "0,1,2,3"
bitfld.long 0x8 16.--17. "P8,P8 interrupt enable" "0,1,2,3"
bitfld.long 0x8 14.--15. "P7,P7 interrupt enable" "0,1,2,3"
bitfld.long 0x8 12.--13. "P6,P6 interrupt enable" "0,1,2,3"
newline
bitfld.long 0x8 10.--11. "P5,P5 interrupt enable" "0,1,2,3"
bitfld.long 0x8 8.--9. "P4,P4 interrupt enable" "0,1,2,3"
bitfld.long 0x8 6.--7. "P3,P3 interrupt enable" "0,1,2,3"
bitfld.long 0x8 4.--5. "P2,P2 interrupt enable" "0,1,2,3"
bitfld.long 0x8 2.--3. "P1,P1 interrupt enable" "0,1,2,3"
bitfld.long 0x8 0.--1. "P0,P0 interrupt enable" "0,1,2,3"
line.long 0xC "ISR,Port n interrupt status register"
bitfld.long 0xC 30.--31. "P15,P15 interrupt status" "0,1,2,3"
bitfld.long 0xC 28.--29. "P14,P14 interrupt status" "0,1,2,3"
bitfld.long 0xC 26.--27. "P13,P13 interrupt status" "0,1,2,3"
bitfld.long 0xC 24.--25. "P12,P12 interrupt status" "0,1,2,3"
bitfld.long 0xC 22.--23. "P11,P11 interrupt status" "0,1,2,3"
bitfld.long 0xC 20.--21. "P10,P10 interrupt status" "0,1,2,3"
bitfld.long 0xC 18.--19. "P9,P9 interrupt status" "0,1,2,3"
bitfld.long 0xC 16.--17. "P8,P8 interrupt status" "0,1,2,3"
bitfld.long 0xC 14.--15. "P7,P7 interrupt status" "0,1,2,3"
bitfld.long 0xC 12.--13. "P6,P6 interrupt status" "0,1,2,3"
newline
bitfld.long 0xC 10.--11. "P5,P5 interrupt status" "0,1,2,3"
bitfld.long 0xC 8.--9. "P4,P4 interrupt status" "0,1,2,3"
bitfld.long 0xC 6.--7. "P3,P3 interrupt status" "0,1,2,3"
bitfld.long 0xC 4.--5. "P2,P2 interrupt status" "0,1,2,3"
bitfld.long 0xC 2.--3. "P1,P1 interrupt status" "0,1,2,3"
bitfld.long 0xC 0.--1. "P0,P0 interrupt status" "0,1,2,3"
line.long 0x10 "ICR,Port n interrupt control register"
bitfld.long 0x10 30.--31. "P15,P15 interrupt control" "0,1,2,3"
bitfld.long 0x10 28.--29. "P14,P14 interrupt control" "0,1,2,3"
bitfld.long 0x10 26.--27. "P13,P13 interrupt control" "0,1,2,3"
bitfld.long 0x10 24.--25. "P12,P12 interrupt control" "0,1,2,3"
bitfld.long 0x10 22.--23. "P11,P11 interrupt control" "0,1,2,3"
bitfld.long 0x10 20.--21. "P10,P10 interrupt control" "0,1,2,3"
bitfld.long 0x10 18.--19. "P9,P9 interrupt control" "0,1,2,3"
bitfld.long 0x10 16.--17. "P8,P8 interrupt control" "0,1,2,3"
bitfld.long 0x10 14.--15. "P7,P7 interrupt control" "0,1,2,3"
bitfld.long 0x10 12.--13. "P6,P6 interrupt control" "0,1,2,3"
newline
bitfld.long 0x10 10.--11. "P5,P5 interrupt control" "0,1,2,3"
bitfld.long 0x10 8.--9. "P4,P4 interrupt control" "0,1,2,3"
bitfld.long 0x10 6.--7. "P3,P3 interrupt control" "0,1,2,3"
bitfld.long 0x10 4.--5. "P2,P2 interrupt control" "0,1,2,3"
bitfld.long 0x10 2.--3. "P1,P1 interrupt control" "0,1,2,3"
bitfld.long 0x10 0.--1. "P0,P0 interrupt control" "0,1,2,3"
tree.end
endif
sif (cpuis("A31G31*"))
tree "PF"
base ad:0x40001500
group.long 0x0++0x13
line.long 0x0 "MOD,Port n Mode Register"
bitfld.long 0x0 30.--31. "MODE15,Pin 15 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 28.--29. "MODE14,Pin 14 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 26.--27. "MODE13,Pin 13 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 24.--25. "MODE12,Pin 12 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 22.--23. "MODE11,Pin 11 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 20.--21. "MODE10,Pin 10 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 18.--19. "MODE9,Pin 9 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 16.--17. "MODE8,Pin 8 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 14.--15. "MODE7,Pin 7 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 12.--13. "MODE6,Pin 6 Mode Selection bits" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "MODE5,Pin 5 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 8.--9. "MODE4,Pin 4 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 6.--7. "MODE3,Pin 3 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 4.--5. "MODE2,Pin 2 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 2.--3. "MODE1,Pin 1 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 0.--1. "MODE0,Pin 0 Mode Selection bits" "0,1,2,3"
line.long 0x4 "TYP,Port n Output Type Selection Register"
bitfld.long 0x4 15. "TYP15,Pin 15 Output Type Selection bit" "0,1"
bitfld.long 0x4 14. "TYP14,Pin 15 Output Type Selection bit" "0,1"
bitfld.long 0x4 13. "TYP13,Pin 13 Output Type Selection bit" "0,1"
bitfld.long 0x4 12. "TYP12,Pin 12 Output Type Selection bit" "0,1"
bitfld.long 0x4 11. "TYP11,Pin 11 Output Type Selection bit" "0,1"
bitfld.long 0x4 10. "TYP10,Pin 10 Output Type Selection bit" "0,1"
bitfld.long 0x4 9. "TYP9,Pin 9 Output Type Selection bit" "0,1"
bitfld.long 0x4 8. "TYP8,Pin 8 Output Type Selection bit" "0,1"
bitfld.long 0x4 7. "TYP7,Pin 7 Output Type Selection bit" "0,1"
bitfld.long 0x4 6. "TYP6,Pin 6 Output Type Selection bit" "0,1"
newline
bitfld.long 0x4 5. "TYP5,Pin 5 Output Type Selection bit" "0,1"
bitfld.long 0x4 4. "TYP4,Pin 4 Output Type Selection bit" "0,1"
bitfld.long 0x4 3. "TYP3,Pin 3 Output Type Selection bit" "0,1"
bitfld.long 0x4 2. "TYP2,Pin 2 Output Type Selection bit" "0,1"
bitfld.long 0x4 1. "TYP1,Pin 1 Output Type Selection bit" "0,1"
bitfld.long 0x4 0. "TYP0,Pin 0 Output Type Selection bit" "0,1"
line.long 0x8 "AFSR1,Port n Alternative Function Selection Register 1"
hexmask.long.byte 0x8 28.--31. 1. "AFSR7,Pin 7 Alternative Function Selection bits"
hexmask.long.byte 0x8 24.--27. 1. "AFSR6,Pin 6 Alternative Function Selection bits"
hexmask.long.byte 0x8 20.--23. 1. "AFSR5,Pin 5 Alternative Function Selection bits"
hexmask.long.byte 0x8 16.--19. 1. "AFSR4,Pin 4 Alternative Function Selection bits"
hexmask.long.byte 0x8 12.--15. 1. "AFSR3,Pin 3 Alternative Function Selection bits"
hexmask.long.byte 0x8 8.--11. 1. "AFSR2,Pin 2 Alternative Function Selection bits"
hexmask.long.byte 0x8 4.--7. 1. "AFSR1,Pin 1 Alternative Function Selection bits"
hexmask.long.byte 0x8 0.--3. 1. "AFSR0,Pin 0 Alternative Function Selection bits"
line.long 0xC "AFSR2,Port n Alternative Function Selection Register 2"
hexmask.long.byte 0xC 28.--31. 1. "AFSR15,Pin 15 Alternative Function Selection bits"
hexmask.long.byte 0xC 24.--27. 1. "AFSR14,Pin 14 Alternative Function Selection bits"
hexmask.long.byte 0xC 20.--23. 1. "AFSR13,Pin 13 Alternative Function Selection bits"
hexmask.long.byte 0xC 16.--19. 1. "AFSR12,Pin 12 Alternative Function Selection bits"
hexmask.long.byte 0xC 12.--15. 1. "AFSR11,Pin 11 Alternative Function Selection bits"
hexmask.long.byte 0xC 8.--11. 1. "AFSR10,Pin 10 Alternative Function Selection bits"
hexmask.long.byte 0xC 4.--7. 1. "AFSR9,Pin 9 Alternative Function Selection bits"
hexmask.long.byte 0xC 0.--3. 1. "AFSR8,Pin 8 Alternative Function Selection bits"
line.long 0x10 "PUPD,Port n Pull-up/down Resistor Selection Register"
bitfld.long 0x10 30.--31. "PUPD15,Pin 15 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 28.--29. "PUPD14,Pin 14 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 26.--27. "PUPD13,Pin 13 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 24.--25. "PUPD12,Pin 12 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 22.--23. "PUPD11,Pin 11 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 20.--21. "PUPD10,Pin 10 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 18.--19. "PUPD9,Pin 9 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 16.--17. "PUPD8,Pin 8 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 14.--15. "PUPD7,Pin 7 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 12.--13. "PUPD6,Pin 6 Pull-up/down Resistor Selection bits" "0,1,2,3"
newline
bitfld.long 0x10 10.--11. "PUPD5,Pin 5 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 8.--9. "PUPD4,Pin 4 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 6.--7. "PUPD3,Pin 3 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 4.--5. "PUPD2,Pin 2 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 2.--3. "PUPD1,Pin 1 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 0.--1. "PUPD0,Pin 0 Pull-up/down Resistor Selection bits" "0,1,2,3"
rgroup.long 0x14++0x3
line.long 0x0 "INDR,Port n Input Data Register"
bitfld.long 0x0 15. "INDR15,Pin 15 Input Data bit" "0,1"
bitfld.long 0x0 14. "INDR14,Pin 14 Input Data bit" "0,1"
bitfld.long 0x0 13. "INDR13,Pin 13 Input Data bit" "0,1"
bitfld.long 0x0 12. "INDR12,Pin 12 Input Data bit" "0,1"
bitfld.long 0x0 11. "INDR11,Pin 11 Input Data bit" "0,1"
bitfld.long 0x0 10. "INDR10,Pin 10 Input Data bit" "0,1"
bitfld.long 0x0 9. "INDR9,Pin 9 Input Data bit" "0,1"
bitfld.long 0x0 8. "INDR8,Pin 8 Input Data bit" "0,1"
bitfld.long 0x0 7. "INDR7,Pin 7 Input Data bit" "0,1"
bitfld.long 0x0 6. "INDR6,Pin 6 Input Data bit" "0,1"
newline
bitfld.long 0x0 5. "INDR5,Pin 5 Input Data bit" "0,1"
bitfld.long 0x0 4. "INDR4,Pin 4 Input Data bit" "0,1"
bitfld.long 0x0 3. "INDR3,Pin 3 Input Data bit" "0,1"
bitfld.long 0x0 2. "INDR2,Pin 2 Input Data bit" "0,1"
bitfld.long 0x0 1. "INDR1,Pin 1 Input Data bit" "0,1"
bitfld.long 0x0 0. "INDR0,Pin 0 Input Data bit" "0,1"
group.long 0x18++0x3
line.long 0x0 "OUTDR,Port n Output Data Register"
bitfld.long 0x0 15. "OUTDR15,Pin 15 Output Data bit" "0,1"
bitfld.long 0x0 14. "OUTDR14,Pin 14 Output Data bit" "0,1"
bitfld.long 0x0 13. "OUTDR13,Pin 13 Output Data bit" "0,1"
bitfld.long 0x0 12. "OUTDR12,Pin 12 Output Data bit" "0,1"
bitfld.long 0x0 11. "OUTDR11,Pin 11 Output Data bit" "0,1"
bitfld.long 0x0 10. "OUTDR10,Pin 10 Output Data bit" "0,1"
bitfld.long 0x0 9. "OUTDR9,Pin 9 Output Data bit" "0,1"
bitfld.long 0x0 8. "OUTDR8,Pin 8 Output Data bit" "0,1"
bitfld.long 0x0 7. "OUTDR7,Pin 7 Output Data bit" "0,1"
bitfld.long 0x0 6. "OUTDR6,Pin 6 Output Data bit" "0,1"
newline
bitfld.long 0x0 5. "OUTDR5,Pin 5 Output Data bit" "0,1"
bitfld.long 0x0 4. "OUTDR4,Pin 4 Output Data bit" "0,1"
bitfld.long 0x0 3. "OUTDR3,Pin 3 Output Data bit" "0,1"
bitfld.long 0x0 2. "OUTDR2,Pin 2 Output Data bit" "0,1"
bitfld.long 0x0 1. "OUTDR1,Pin 1 Output Data bit" "0,1"
bitfld.long 0x0 0. "OUTDR0,Pin 0 Output Data bit" "0,1"
wgroup.long 0x1C++0x7
line.long 0x0 "BSR,Port n Output Bit Set Register"
bitfld.long 0x0 15. "BSR15,Pin 15 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 14. "BSR14,Pin 14 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 13. "BSR13,Pin 13 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 12. "BSR12,Pin 12 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 11. "BSR11,Pin 11 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 10. "BSR10,Pin 10 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 9. "BSR9,Pin 9 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 8. "BSR8,Pin 8 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 7. "BSR7,Pin 7 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 6. "BSR6,Pin 6 Output Set bit. This bit is always read to 0" "0,1"
newline
bitfld.long 0x0 5. "BSR5,Pin 5 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 4. "BSR4,Pin 4 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 3. "BSR3,Pin 3 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 2. "BSR2,Pin 2 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 1. "BSR1,Pin 1 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 0. "BSR0,Pin 0 Output Set bit. This bit is always read to 0" "0,1"
line.long 0x4 "BCR,Port n Output Bit Clear Register"
bitfld.long 0x4 15. "BCR15,Pin 15 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 14. "BCR14,Pin 14 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 13. "BCR13,Pin 13 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 12. "BCR12,Pin 12 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 11. "BCR11,Pin 11 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 10. "BCR10,Pin 10 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 9. "BCR9,Pin 9 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 8. "BCR8,Pin 8 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 7. "BCR7,Pin 7 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 6. "BCR6,Pin 6 Output Clear bit. This bit is always read to 0." "0,1"
newline
bitfld.long 0x4 5. "BCR5,Pin 5 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 4. "BCR4,Pin 4 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 3. "BCR3,Pin 3 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 2. "BCR2,Pin 2 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 1. "BCR1,Pin 1 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 0. "BCR0,Pin 0 Output Clear bit. This bit is always read to 0." "0,1"
group.long 0x24++0x17
line.long 0x0 "OUTDMSK,Port n Output Data Mask Register"
bitfld.long 0x0 15. "OUTDMSK15,Pin 15 Output Data Mask bit" "0,1"
bitfld.long 0x0 14. "OUTDMSK14,Pin 14 Output Data Mask bit" "0,1"
bitfld.long 0x0 13. "OUTDMSK13,Pin 13 Output Data Mask bit" "0,1"
bitfld.long 0x0 12. "OUTDMSK12,Pin 12 Output Data Mask bit" "0,1"
bitfld.long 0x0 11. "OUTDMSK11,Pin 11 Output Data Mask bit" "0,1"
bitfld.long 0x0 10. "OUTDMSK10,Pin 10 Output Data Mask bit" "0,1"
bitfld.long 0x0 9. "OUTDMSK9,Pin 9 Output Data Mask bit" "0,1"
bitfld.long 0x0 8. "OUTDMSK8,Pin 8 Output Data Mask bit" "0,1"
bitfld.long 0x0 7. "OUTDMSK7,Pin 7 Output Data Mask bit" "0,1"
bitfld.long 0x0 6. "OUTDMSK6,Pin 6 Output Data Mask bit" "0,1"
newline
bitfld.long 0x0 5. "OUTDMSK5,Pin 5 Output Data Mask bit" "0,1"
bitfld.long 0x0 4. "OUTDMSK4,Pin 4 Output Data Mask bit" "0,1"
bitfld.long 0x0 3. "OUTDMSK3,Pin 3 Output Data Mask bit" "0,1"
bitfld.long 0x0 2. "OUTDMSK2,Pin 2 Output Data Mask bit" "0,1"
bitfld.long 0x0 1. "OUTDMSK1,Pin 1 Output Data Mask bit" "0,1"
bitfld.long 0x0 0. "OUTDMSK0,Pin 0 Output Data Mask bit" "0,1"
line.long 0x4 "DBCR,Port n Debounce Control Register"
bitfld.long 0x4 15. "DBEN15,Pin 15 Debounce Enable bit" "0,1"
bitfld.long 0x4 14. "DBEN14,Pin 14 Debounce Enable bit" "0,1"
bitfld.long 0x4 13. "DBEN13,Pin 13 Debounce Enable bit" "0,1"
bitfld.long 0x4 12. "DBEN12,Pin 12 Debounce Enable bit" "0,1"
bitfld.long 0x4 11. "DBEN11,Pin 11 Debounce Enable bit" "0,1"
bitfld.long 0x4 10. "DBEN10,Pin 10 Debounce Enable bit" "0,1"
bitfld.long 0x4 9. "DBEN9,Pin 9 Debounce Enable bit" "0,1"
bitfld.long 0x4 8. "DBEN8,Pin 8 Debounce Enable bit" "0,1"
bitfld.long 0x4 7. "DBEN7,Pin 7 Debounce Enable bit" "0,1"
bitfld.long 0x4 6. "DBEN6,Pin 6 Debounce Enable bit" "0,1"
newline
bitfld.long 0x4 5. "DBEN5,Pin 5 Debounce Enable bit" "0,1"
bitfld.long 0x4 4. "DBEN4,Pin 4 Debounce Enable bit" "0,1"
bitfld.long 0x4 3. "DBEN3,Pin 3 Debounce Enable bit" "0,1"
bitfld.long 0x4 2. "DBEN2,Pin 2 Debounce Enable bit" "0,1"
bitfld.long 0x4 1. "DBEN1,Pin 1 Debounce Enable bit" "0,1"
bitfld.long 0x4 0. "DBEN0,Pin 0 Debounce Enable bit" "0,1"
line.long 0x8 "IER,Port n interrupt enable register"
bitfld.long 0x8 30.--31. "P15,P15 interrupt enable" "0,1,2,3"
bitfld.long 0x8 28.--29. "P14,P14 interrupt enable" "0,1,2,3"
bitfld.long 0x8 26.--27. "P13,P13 interrupt enable" "0,1,2,3"
bitfld.long 0x8 24.--25. "P12,P12 interrupt enable" "0,1,2,3"
bitfld.long 0x8 22.--23. "P11,P11 interrupt enable" "0,1,2,3"
bitfld.long 0x8 20.--21. "P10,P10 interrupt enable" "0,1,2,3"
bitfld.long 0x8 18.--19. "P9,P9 interrupt enable" "0,1,2,3"
bitfld.long 0x8 16.--17. "P8,P8 interrupt enable" "0,1,2,3"
bitfld.long 0x8 14.--15. "P7,P7 interrupt enable" "0,1,2,3"
bitfld.long 0x8 12.--13. "P6,P6 interrupt enable" "0,1,2,3"
newline
bitfld.long 0x8 10.--11. "P5,P5 interrupt enable" "0,1,2,3"
bitfld.long 0x8 8.--9. "P4,P4 interrupt enable" "0,1,2,3"
bitfld.long 0x8 6.--7. "P3,P3 interrupt enable" "0,1,2,3"
bitfld.long 0x8 4.--5. "P2,P2 interrupt enable" "0,1,2,3"
bitfld.long 0x8 2.--3. "P1,P1 interrupt enable" "0,1,2,3"
bitfld.long 0x8 0.--1. "P0,P0 interrupt enable" "0,1,2,3"
line.long 0xC "ISR,Port n interrupt status register"
bitfld.long 0xC 30.--31. "P15,P15 interrupt status" "0,1,2,3"
bitfld.long 0xC 28.--29. "P14,P14 interrupt status" "0,1,2,3"
bitfld.long 0xC 26.--27. "P13,P13 interrupt status" "0,1,2,3"
bitfld.long 0xC 24.--25. "P12,P12 interrupt status" "0,1,2,3"
bitfld.long 0xC 22.--23. "P11,P11 interrupt status" "0,1,2,3"
bitfld.long 0xC 20.--21. "P10,P10 interrupt status" "0,1,2,3"
bitfld.long 0xC 18.--19. "P9,P9 interrupt status" "0,1,2,3"
bitfld.long 0xC 16.--17. "P8,P8 interrupt status" "0,1,2,3"
bitfld.long 0xC 14.--15. "P7,P7 interrupt status" "0,1,2,3"
bitfld.long 0xC 12.--13. "P6,P6 interrupt status" "0,1,2,3"
newline
bitfld.long 0xC 10.--11. "P5,P5 interrupt status" "0,1,2,3"
bitfld.long 0xC 8.--9. "P4,P4 interrupt status" "0,1,2,3"
bitfld.long 0xC 6.--7. "P3,P3 interrupt status" "0,1,2,3"
bitfld.long 0xC 4.--5. "P2,P2 interrupt status" "0,1,2,3"
bitfld.long 0xC 2.--3. "P1,P1 interrupt status" "0,1,2,3"
bitfld.long 0xC 0.--1. "P0,P0 interrupt status" "0,1,2,3"
line.long 0x10 "ICR,Port n interrupt control register"
bitfld.long 0x10 30.--31. "P15,P15 interrupt control" "0,1,2,3"
bitfld.long 0x10 28.--29. "P14,P14 interrupt control" "0,1,2,3"
bitfld.long 0x10 26.--27. "P13,P13 interrupt control" "0,1,2,3"
bitfld.long 0x10 24.--25. "P12,P12 interrupt control" "0,1,2,3"
bitfld.long 0x10 22.--23. "P11,P11 interrupt control" "0,1,2,3"
bitfld.long 0x10 20.--21. "P10,P10 interrupt control" "0,1,2,3"
bitfld.long 0x10 18.--19. "P9,P9 interrupt control" "0,1,2,3"
bitfld.long 0x10 16.--17. "P8,P8 interrupt control" "0,1,2,3"
bitfld.long 0x10 14.--15. "P7,P7 interrupt control" "0,1,2,3"
bitfld.long 0x10 12.--13. "P6,P6 interrupt control" "0,1,2,3"
newline
bitfld.long 0x10 10.--11. "P5,P5 interrupt control" "0,1,2,3"
bitfld.long 0x10 8.--9. "P4,P4 interrupt control" "0,1,2,3"
bitfld.long 0x10 6.--7. "P3,P3 interrupt control" "0,1,2,3"
bitfld.long 0x10 4.--5. "P2,P2 interrupt control" "0,1,2,3"
bitfld.long 0x10 2.--3. "P1,P1 interrupt control" "0,1,2,3"
bitfld.long 0x10 0.--1. "P0,P0 interrupt control" "0,1,2,3"
line.long 0x14 "PLSR,PORT F level select register"
bitfld.long 0x14 2. "PF7LSB,PORTF 7 Level Select bit" "0,1"
bitfld.long 0x14 1. "PF6LSB,PORTF 6 Level Select bit" "0,1"
bitfld.long 0x14 0. "PF5LSB,PORTF 5 Level Select bit" "0,1"
tree.end
endif
sif (cpuis("A31G31*"))
tree "USBCON"
base ad:0x40001540
group.long 0x0++0x3
line.long 0x0 "USBCON,USB CONTROL Register"
tree.end
endif
sif (cpuis("A31G31*"))
tree "PCU"
base ad:0x40001540
group.long 0xAB0++0x3
line.long 0x0 "PORTEN,Port Access Enable 0x15->0x51"
tree.end
endif
sif (cpuis("A31G32*"))
tree "PF"
base ad:0x40001500
group.long 0x0++0x13
line.long 0x0 "MOD,Port n Mode Register"
bitfld.long 0x0 30.--31. "MODE15,Pin 15 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 28.--29. "MODE14,Pin 14 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 26.--27. "MODE13,Pin 13 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 24.--25. "MODE12,Pin 12 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 22.--23. "MODE11,Pin 11 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 20.--21. "MODE10,Pin 10 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 18.--19. "MODE9,Pin 9 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 16.--17. "MODE8,Pin 8 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 14.--15. "MODE7,Pin 7 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 12.--13. "MODE6,Pin 6 Mode Selection bits" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "MODE5,Pin 5 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 8.--9. "MODE4,Pin 4 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 6.--7. "MODE3,Pin 3 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 4.--5. "MODE2,Pin 2 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 2.--3. "MODE1,Pin 1 Mode Selection bits" "0,1,2,3"
bitfld.long 0x0 0.--1. "MODE0,Pin 0 Mode Selection bits" "0,1,2,3"
line.long 0x4 "TYP,Port n Output Type Selection Register"
bitfld.long 0x4 15. "TYP15,Pin 15 Output Type Selection bit" "0,1"
bitfld.long 0x4 14. "TYP14,Pin 15 Output Type Selection bit" "0,1"
bitfld.long 0x4 13. "TYP13,Pin 13 Output Type Selection bit" "0,1"
bitfld.long 0x4 12. "TYP12,Pin 12 Output Type Selection bit" "0,1"
bitfld.long 0x4 11. "TYP11,Pin 11 Output Type Selection bit" "0,1"
bitfld.long 0x4 10. "TYP10,Pin 10 Output Type Selection bit" "0,1"
bitfld.long 0x4 9. "TYP9,Pin 9 Output Type Selection bit" "0,1"
bitfld.long 0x4 8. "TYP8,Pin 8 Output Type Selection bit" "0,1"
bitfld.long 0x4 7. "TYP7,Pin 7 Output Type Selection bit" "0,1"
bitfld.long 0x4 6. "TYP6,Pin 6 Output Type Selection bit" "0,1"
newline
bitfld.long 0x4 5. "TYP5,Pin 5 Output Type Selection bit" "0,1"
bitfld.long 0x4 4. "TYP4,Pin 4 Output Type Selection bit" "0,1"
bitfld.long 0x4 3. "TYP3,Pin 3 Output Type Selection bit" "0,1"
bitfld.long 0x4 2. "TYP2,Pin 2 Output Type Selection bit" "0,1"
bitfld.long 0x4 1. "TYP1,Pin 1 Output Type Selection bit" "0,1"
bitfld.long 0x4 0. "TYP0,Pin 0 Output Type Selection bit" "0,1"
line.long 0x8 "AFSR1,Port n Alternative Function Selection Register 1"
hexmask.long.byte 0x8 28.--31. 1. "AFSR7,Pin 7 Alternative Function Selection bits"
hexmask.long.byte 0x8 24.--27. 1. "AFSR6,Pin 6 Alternative Function Selection bits"
hexmask.long.byte 0x8 20.--23. 1. "AFSR5,Pin 5 Alternative Function Selection bits"
hexmask.long.byte 0x8 16.--19. 1. "AFSR4,Pin 4 Alternative Function Selection bits"
hexmask.long.byte 0x8 12.--15. 1. "AFSR3,Pin 3 Alternative Function Selection bits"
hexmask.long.byte 0x8 8.--11. 1. "AFSR2,Pin 2 Alternative Function Selection bits"
hexmask.long.byte 0x8 4.--7. 1. "AFSR1,Pin 1 Alternative Function Selection bits"
hexmask.long.byte 0x8 0.--3. 1. "AFSR0,Pin 0 Alternative Function Selection bits"
line.long 0xC "AFSR2,Port n Alternative Function Selection Register 2"
hexmask.long.byte 0xC 28.--31. 1. "AFSR15,Pin 15 Alternative Function Selection bits"
hexmask.long.byte 0xC 24.--27. 1. "AFSR14,Pin 14 Alternative Function Selection bits"
hexmask.long.byte 0xC 20.--23. 1. "AFSR13,Pin 13 Alternative Function Selection bits"
hexmask.long.byte 0xC 16.--19. 1. "AFSR12,Pin 12 Alternative Function Selection bits"
hexmask.long.byte 0xC 12.--15. 1. "AFSR11,Pin 11 Alternative Function Selection bits"
hexmask.long.byte 0xC 8.--11. 1. "AFSR10,Pin 10 Alternative Function Selection bits"
hexmask.long.byte 0xC 4.--7. 1. "AFSR9,Pin 9 Alternative Function Selection bits"
hexmask.long.byte 0xC 0.--3. 1. "AFSR8,Pin 8 Alternative Function Selection bits"
line.long 0x10 "PUPD,Port n Pull-up/down Resistor Selection Register"
bitfld.long 0x10 30.--31. "PUPD15,Pin 15 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 28.--29. "PUPD14,Pin 14 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 26.--27. "PUPD13,Pin 13 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 24.--25. "PUPD12,Pin 12 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 22.--23. "PUPD11,Pin 11 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 20.--21. "PUPD10,Pin 10 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 18.--19. "PUPD9,Pin 9 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 16.--17. "PUPD8,Pin 8 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 14.--15. "PUPD7,Pin 7 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 12.--13. "PUPD6,Pin 6 Pull-up/down Resistor Selection bits" "0,1,2,3"
newline
bitfld.long 0x10 10.--11. "PUPD5,Pin 5 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 8.--9. "PUPD4,Pin 4 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 6.--7. "PUPD3,Pin 3 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 4.--5. "PUPD2,Pin 2 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 2.--3. "PUPD1,Pin 1 Pull-up/down Resistor Selection bits" "0,1,2,3"
bitfld.long 0x10 0.--1. "PUPD0,Pin 0 Pull-up/down Resistor Selection bits" "0,1,2,3"
rgroup.long 0x14++0x3
line.long 0x0 "INDR,Port n Input Data Register"
bitfld.long 0x0 15. "INDR15,Pin 15 Input Data bit" "0,1"
bitfld.long 0x0 14. "INDR14,Pin 14 Input Data bit" "0,1"
bitfld.long 0x0 13. "INDR13,Pin 13 Input Data bit" "0,1"
bitfld.long 0x0 12. "INDR12,Pin 12 Input Data bit" "0,1"
bitfld.long 0x0 11. "INDR11,Pin 11 Input Data bit" "0,1"
bitfld.long 0x0 10. "INDR10,Pin 10 Input Data bit" "0,1"
bitfld.long 0x0 9. "INDR9,Pin 9 Input Data bit" "0,1"
bitfld.long 0x0 8. "INDR8,Pin 8 Input Data bit" "0,1"
bitfld.long 0x0 7. "INDR7,Pin 7 Input Data bit" "0,1"
bitfld.long 0x0 6. "INDR6,Pin 6 Input Data bit" "0,1"
newline
bitfld.long 0x0 5. "INDR5,Pin 5 Input Data bit" "0,1"
bitfld.long 0x0 4. "INDR4,Pin 4 Input Data bit" "0,1"
bitfld.long 0x0 3. "INDR3,Pin 3 Input Data bit" "0,1"
bitfld.long 0x0 2. "INDR2,Pin 2 Input Data bit" "0,1"
bitfld.long 0x0 1. "INDR1,Pin 1 Input Data bit" "0,1"
bitfld.long 0x0 0. "INDR0,Pin 0 Input Data bit" "0,1"
group.long 0x18++0x3
line.long 0x0 "OUTDR,Port n Output Data Register"
bitfld.long 0x0 15. "OUTDR15,Pin 15 Output Data bit" "0,1"
bitfld.long 0x0 14. "OUTDR14,Pin 14 Output Data bit" "0,1"
bitfld.long 0x0 13. "OUTDR13,Pin 13 Output Data bit" "0,1"
bitfld.long 0x0 12. "OUTDR12,Pin 12 Output Data bit" "0,1"
bitfld.long 0x0 11. "OUTDR11,Pin 11 Output Data bit" "0,1"
bitfld.long 0x0 10. "OUTDR10,Pin 10 Output Data bit" "0,1"
bitfld.long 0x0 9. "OUTDR9,Pin 9 Output Data bit" "0,1"
bitfld.long 0x0 8. "OUTDR8,Pin 8 Output Data bit" "0,1"
bitfld.long 0x0 7. "OUTDR7,Pin 7 Output Data bit" "0,1"
bitfld.long 0x0 6. "OUTDR6,Pin 6 Output Data bit" "0,1"
newline
bitfld.long 0x0 5. "OUTDR5,Pin 5 Output Data bit" "0,1"
bitfld.long 0x0 4. "OUTDR4,Pin 4 Output Data bit" "0,1"
bitfld.long 0x0 3. "OUTDR3,Pin 3 Output Data bit" "0,1"
bitfld.long 0x0 2. "OUTDR2,Pin 2 Output Data bit" "0,1"
bitfld.long 0x0 1. "OUTDR1,Pin 1 Output Data bit" "0,1"
bitfld.long 0x0 0. "OUTDR0,Pin 0 Output Data bit" "0,1"
wgroup.long 0x1C++0x7
line.long 0x0 "BSR,Port n Output Bit Set Register"
bitfld.long 0x0 15. "BSR15,Pin 15 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 14. "BSR14,Pin 14 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 13. "BSR13,Pin 13 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 12. "BSR12,Pin 12 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 11. "BSR11,Pin 11 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 10. "BSR10,Pin 10 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 9. "BSR9,Pin 9 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 8. "BSR8,Pin 8 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 7. "BSR7,Pin 7 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 6. "BSR6,Pin 6 Output Set bit. This bit is always read to 0" "0,1"
newline
bitfld.long 0x0 5. "BSR5,Pin 5 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 4. "BSR4,Pin 4 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 3. "BSR3,Pin 3 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 2. "BSR2,Pin 2 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 1. "BSR1,Pin 1 Output Set bit. This bit is always read to 0" "0,1"
bitfld.long 0x0 0. "BSR0,Pin 0 Output Set bit. This bit is always read to 0" "0,1"
line.long 0x4 "BCR,Port n Output Bit Clear Register"
bitfld.long 0x4 15. "BCR15,Pin 15 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 14. "BCR14,Pin 14 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 13. "BCR13,Pin 13 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 12. "BCR12,Pin 12 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 11. "BCR11,Pin 11 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 10. "BCR10,Pin 10 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 9. "BCR9,Pin 9 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 8. "BCR8,Pin 8 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 7. "BCR7,Pin 7 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 6. "BCR6,Pin 6 Output Clear bit. This bit is always read to 0." "0,1"
newline
bitfld.long 0x4 5. "BCR5,Pin 5 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 4. "BCR4,Pin 4 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 3. "BCR3,Pin 3 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 2. "BCR2,Pin 2 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 1. "BCR1,Pin 1 Output Clear bit. This bit is always read to 0." "0,1"
bitfld.long 0x4 0. "BCR0,Pin 0 Output Clear bit. This bit is always read to 0." "0,1"
group.long 0x24++0x13
line.long 0x0 "OUTDMSK,Port n Output Data Mask Register"
bitfld.long 0x0 15. "OUTDMSK15,Pin 15 Output Data Mask bit" "0,1"
bitfld.long 0x0 14. "OUTDMSK14,Pin 14 Output Data Mask bit" "0,1"
bitfld.long 0x0 13. "OUTDMSK13,Pin 13 Output Data Mask bit" "0,1"
bitfld.long 0x0 12. "OUTDMSK12,Pin 12 Output Data Mask bit" "0,1"
bitfld.long 0x0 11. "OUTDMSK11,Pin 11 Output Data Mask bit" "0,1"
bitfld.long 0x0 10. "OUTDMSK10,Pin 10 Output Data Mask bit" "0,1"
bitfld.long 0x0 9. "OUTDMSK9,Pin 9 Output Data Mask bit" "0,1"
bitfld.long 0x0 8. "OUTDMSK8,Pin 8 Output Data Mask bit" "0,1"
bitfld.long 0x0 7. "OUTDMSK7,Pin 7 Output Data Mask bit" "0,1"
bitfld.long 0x0 6. "OUTDMSK6,Pin 6 Output Data Mask bit" "0,1"
newline
bitfld.long 0x0 5. "OUTDMSK5,Pin 5 Output Data Mask bit" "0,1"
bitfld.long 0x0 4. "OUTDMSK4,Pin 4 Output Data Mask bit" "0,1"
bitfld.long 0x0 3. "OUTDMSK3,Pin 3 Output Data Mask bit" "0,1"
bitfld.long 0x0 2. "OUTDMSK2,Pin 2 Output Data Mask bit" "0,1"
bitfld.long 0x0 1. "OUTDMSK1,Pin 1 Output Data Mask bit" "0,1"
bitfld.long 0x0 0. "OUTDMSK0,Pin 0 Output Data Mask bit" "0,1"
line.long 0x4 "DBCR,Port n Debounce Control Register"
bitfld.long 0x4 15. "DBEN15,Pin 15 Debounce Enable bit" "0,1"
bitfld.long 0x4 14. "DBEN14,Pin 14 Debounce Enable bit" "0,1"
bitfld.long 0x4 13. "DBEN13,Pin 13 Debounce Enable bit" "0,1"
bitfld.long 0x4 12. "DBEN12,Pin 12 Debounce Enable bit" "0,1"
bitfld.long 0x4 11. "DBEN11,Pin 11 Debounce Enable bit" "0,1"
bitfld.long 0x4 10. "DBEN10,Pin 10 Debounce Enable bit" "0,1"
bitfld.long 0x4 9. "DBEN9,Pin 9 Debounce Enable bit" "0,1"
bitfld.long 0x4 8. "DBEN8,Pin 8 Debounce Enable bit" "0,1"
bitfld.long 0x4 7. "DBEN7,Pin 7 Debounce Enable bit" "0,1"
bitfld.long 0x4 6. "DBEN6,Pin 6 Debounce Enable bit" "0,1"
newline
bitfld.long 0x4 5. "DBEN5,Pin 5 Debounce Enable bit" "0,1"
bitfld.long 0x4 4. "DBEN4,Pin 4 Debounce Enable bit" "0,1"
bitfld.long 0x4 3. "DBEN3,Pin 3 Debounce Enable bit" "0,1"
bitfld.long 0x4 2. "DBEN2,Pin 2 Debounce Enable bit" "0,1"
bitfld.long 0x4 1. "DBEN1,Pin 1 Debounce Enable bit" "0,1"
bitfld.long 0x4 0. "DBEN0,Pin 0 Debounce Enable bit" "0,1"
line.long 0x8 "IER,Port n interrupt enable register"
bitfld.long 0x8 30.--31. "P15,P15 interrupt enable" "0,1,2,3"
bitfld.long 0x8 28.--29. "P14,P14 interrupt enable" "0,1,2,3"
bitfld.long 0x8 26.--27. "P13,P13 interrupt enable" "0,1,2,3"
bitfld.long 0x8 24.--25. "P12,P12 interrupt enable" "0,1,2,3"
bitfld.long 0x8 22.--23. "P11,P11 interrupt enable" "0,1,2,3"
bitfld.long 0x8 20.--21. "P10,P10 interrupt enable" "0,1,2,3"
bitfld.long 0x8 18.--19. "P9,P9 interrupt enable" "0,1,2,3"
bitfld.long 0x8 16.--17. "P8,P8 interrupt enable" "0,1,2,3"
bitfld.long 0x8 14.--15. "P7,P7 interrupt enable" "0,1,2,3"
bitfld.long 0x8 12.--13. "P6,P6 interrupt enable" "0,1,2,3"
newline
bitfld.long 0x8 10.--11. "P5,P5 interrupt enable" "0,1,2,3"
bitfld.long 0x8 8.--9. "P4,P4 interrupt enable" "0,1,2,3"
bitfld.long 0x8 6.--7. "P3,P3 interrupt enable" "0,1,2,3"
bitfld.long 0x8 4.--5. "P2,P2 interrupt enable" "0,1,2,3"
bitfld.long 0x8 2.--3. "P1,P1 interrupt enable" "0,1,2,3"
bitfld.long 0x8 0.--1. "P0,P0 interrupt enable" "0,1,2,3"
line.long 0xC "ISR,Port n interrupt status register"
bitfld.long 0xC 30.--31. "P15,P15 interrupt status" "0,1,2,3"
bitfld.long 0xC 28.--29. "P14,P14 interrupt status" "0,1,2,3"
bitfld.long 0xC 26.--27. "P13,P13 interrupt status" "0,1,2,3"
bitfld.long 0xC 24.--25. "P12,P12 interrupt status" "0,1,2,3"
bitfld.long 0xC 22.--23. "P11,P11 interrupt status" "0,1,2,3"
bitfld.long 0xC 20.--21. "P10,P10 interrupt status" "0,1,2,3"
bitfld.long 0xC 18.--19. "P9,P9 interrupt status" "0,1,2,3"
bitfld.long 0xC 16.--17. "P8,P8 interrupt status" "0,1,2,3"
bitfld.long 0xC 14.--15. "P7,P7 interrupt status" "0,1,2,3"
bitfld.long 0xC 12.--13. "P6,P6 interrupt status" "0,1,2,3"
newline
bitfld.long 0xC 10.--11. "P5,P5 interrupt status" "0,1,2,3"
bitfld.long 0xC 8.--9. "P4,P4 interrupt status" "0,1,2,3"
bitfld.long 0xC 6.--7. "P3,P3 interrupt status" "0,1,2,3"
bitfld.long 0xC 4.--5. "P2,P2 interrupt status" "0,1,2,3"
bitfld.long 0xC 2.--3. "P1,P1 interrupt status" "0,1,2,3"
bitfld.long 0xC 0.--1. "P0,P0 interrupt status" "0,1,2,3"
line.long 0x10 "ICR,Port n interrupt control register"
bitfld.long 0x10 30.--31. "P15,P15 interrupt control" "0,1,2,3"
bitfld.long 0x10 28.--29. "P14,P14 interrupt control" "0,1,2,3"
bitfld.long 0x10 26.--27. "P13,P13 interrupt control" "0,1,2,3"
bitfld.long 0x10 24.--25. "P12,P12 interrupt control" "0,1,2,3"
bitfld.long 0x10 22.--23. "P11,P11 interrupt control" "0,1,2,3"
bitfld.long 0x10 20.--21. "P10,P10 interrupt control" "0,1,2,3"
bitfld.long 0x10 18.--19. "P9,P9 interrupt control" "0,1,2,3"
bitfld.long 0x10 16.--17. "P8,P8 interrupt control" "0,1,2,3"
bitfld.long 0x10 14.--15. "P7,P7 interrupt control" "0,1,2,3"
bitfld.long 0x10 12.--13. "P6,P6 interrupt control" "0,1,2,3"
newline
bitfld.long 0x10 10.--11. "P5,P5 interrupt control" "0,1,2,3"
bitfld.long 0x10 8.--9. "P4,P4 interrupt control" "0,1,2,3"
bitfld.long 0x10 6.--7. "P3,P3 interrupt control" "0,1,2,3"
bitfld.long 0x10 4.--5. "P2,P2 interrupt control" "0,1,2,3"
bitfld.long 0x10 2.--3. "P1,P1 interrupt control" "0,1,2,3"
bitfld.long 0x10 0.--1. "P0,P0 interrupt control" "0,1,2,3"
tree.end
endif
sif (cpuis("A31G32*"))
tree "USBCON"
base ad:0x40001540
group.long 0x0++0x3
line.long 0x0 "USBCON,USB CONTROL Register"
bitfld.long 0x0 28.--30. "TX_DNOPT,TX Driver Up Driving Strength Option" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 24.--26. "TX_UPOPT,TX Driver Down Driving Strength Option" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 23. "CONTROL_EN,USB PHY pull up pull down VIL VIH control enable" "0,1"
bitfld.long 0x0 22. "PHY_SUSPND,PHY SUSPEND Signal(active High)" "0,1"
bitfld.long 0x0 21. "VREF_SEL,Single ended Receiver hysteresis reference Voltage Select" "0,1"
bitfld.long 0x0 19. "PD_ENDN,DN Pin Pull Down Enable" "0,1"
bitfld.long 0x0 18. "PD_ENDP,DP pin Pull down enable" "0,1"
bitfld.long 0x0 17. "PU_ENDN,DN pin Pull up enable" "0,1"
bitfld.long 0x0 16. "PU_ENDP,DP pin Pull up enable" "0,1"
bitfld.long 0x0 12.--14. "VIH_CON,VIH level select register" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 8.--10. "VIL_CON,VIL level select register" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 4.--6. "PD_CON,Pull down resister select register" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 0.--2. "PU_CON,Pull up resister select register" "0,1,2,3,4,5,6,7"
tree.end
endif
sif (cpuis("A31G32*"))
tree "PCU"
base ad:0x40001FF0
wgroup.long 0x0++0x3
line.long 0x0 "PORTEN,Port Access Enable 0x15. 0x51"
hexmask.long.byte 0x0 0.--7. 1. "PORTEN,Writing the sequence of 0x15 and 0x51 in this register enables writing to PCU registers "
tree.end
endif
tree.end
tree "SCU (System Control Unit)"
base ad:0x0
tree "SCU"
base ad:0x40000000
group.long 0x4++0x7
line.long 0x0 "SMR,System Mode Register"
sif (cpuis("A31G31*"))
bitfld.long 0x0 10. "ROSCAON,ROSC Always on select bit in power down mode" "0: ROSC is automatically off entering power down mode,1: ROSC isn't automatically off entering power down.."
bitfld.long 0x0 4.--5. "PREVMODE,Previous operating mode before current reset event" "0,1,2,3"
newline
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 10. "LSIAON,LSI Always on select bit in power down mode" "0: LSI is automatically off entering power down mode,1: LSI isn't automatically off entering power down.."
endif
bitfld.long 0x0 9. "BGRAON,BGR Always on select bit in power down mode" "0: BGR is automatically off entering power down mode,1: BGR isn't automatically off entering power down.."
newline
bitfld.long 0x0 8. "VDCAON,VDC Always on select bit in power down mode" "0,1"
sif (cpuis("A31G32*"))
rbitfld.long 0x0 4.--6. "PREVMODE,Previous operating mode before current reset event" "0,1,2,3,4,5,6,7"
endif
line.long 0x4 "SCR,System Control Register"
hexmask.long.word 0x4 16.--31. 1. "WTIDKY,On writes write 0x9EB3 to these bits otherwise the write is ignored."
bitfld.long 0x4 0. "SWRST,Internal soft reset activation bit (check RSER[4] for reset)" "0,1"
group.long 0x10++0x2B
line.long 0x0 "WUER,Wake up source enable register"
sif (cpuis("A31G32*"))
bitfld.long 0x0 15. "I2C1WUE,Enable wakeup source of I2C1 change event" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 14. "I2C0WUE,Enable wakeup source of I2C0 change event" "0,1"
newline
endif
bitfld.long 0x0 13. "GPIOFWUE,Enable wakeup source of GPIOF port pin change event" "0,1"
sif (cpuis("A31G32*"))
bitfld.long 0x0 12. "USART13WUE,Enable wakeup source of USART13 change event" "0,1"
newline
endif
sif (cpuis("A31G31*"))
bitfld.long 0x0 12. "GPIOEWUE,Enable wakeup source of GPIOE port pin change event" "0,1"
bitfld.long 0x0 11. "GPIODWUE,Enable wakeup source of GPIOD port pin change event" "0,1"
newline
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 11. "USART12WUE,Enable wakeup source of USART12 change event" "0,1"
endif
bitfld.long 0x0 10. "GPIOCWUE,Enable wakeup source of GPIOC port pin change event" "0,1"
newline
bitfld.long 0x0 9. "GPIOBWUE,Enable wakeup source of GPIOB port pin change event" "0,1"
bitfld.long 0x0 8. "GPIOAWUE,Enable wakeup source of GPIOA port pin change event" "0,1"
newline
sif (cpuis("A31G32*"))
bitfld.long 0x0 6. "COMPWUE,Enable wakeup source of COMP change event" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 5. "RTCWUE,Enable wakeup source of RTC change event" "0,1"
newline
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 4. "USART11WUE,Enable wakeup source of USART11 change event" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 3. "USART10WUE,Enable wakeup source of USART10 change event" "0,1"
newline
endif
bitfld.long 0x0 2. "WTWUE,Enable wakeup source of watch timer event" "0,1"
bitfld.long 0x0 1. "WDTWUE,Enable wakeup source of watchdog timer event" "0,1"
newline
bitfld.long 0x0 0. "LVDWUE,Enable wakeup source of LVD event" "0,1"
line.long 0x4 "WUSR,Wake up source status register"
sif (cpuis("A31G32*"))
rbitfld.long 0x4 15. "I2C1WU,Status of wakeup source of I2C1 change event" "0,1"
endif
sif (cpuis("A31G32*"))
rbitfld.long 0x4 14. "I2C0WU,Status of wakeup source of I2C0 change event" "0,1"
newline
endif
rbitfld.long 0x4 13. "GPIOFWU,Status of wakeup source of GPIOF port pin change event" "0,1"
sif (cpuis("A31G32*"))
rbitfld.long 0x4 12. "USART13WU,Status of wakeup source of USART13 change event" "0,1"
newline
endif
sif (cpuis("A31G31*"))
rbitfld.long 0x4 12. "GPIOEWU,Status of wakeup source of GPIOE port pin change event" "0,1"
rbitfld.long 0x4 11. "GPIODWU,Status of wakeup source of GPIOD port pin change event" "0,1"
newline
endif
sif (cpuis("A31G32*"))
rbitfld.long 0x4 11. "USART12WU,Status of wakeup source of USART12 change event" "0,1"
endif
rbitfld.long 0x4 10. "GPIOCWU,Status of wakeup source of GPIOC port pin change event" "0,1"
newline
rbitfld.long 0x4 9. "GPIOBWU,Status of wakeup source of GPIOB port pin change event" "0,1"
rbitfld.long 0x4 8. "GPIOAWU,Status of wakeup source of GPIOA port pin change event" "0,1"
newline
sif (cpuis("A31G32*"))
rbitfld.long 0x4 6. "COMPWU,Status of wakeup source of COMP change event" "0,1"
endif
sif (cpuis("A31G32*"))
rbitfld.long 0x4 5. "RTCWU,Status of wakeup source of RTC change event" "0,1"
newline
endif
sif (cpuis("A31G32*"))
rbitfld.long 0x4 4. "USART11WU,Status of wakeup source of USART11 change event" "0,1"
endif
sif (cpuis("A31G32*"))
rbitfld.long 0x4 3. "USART10WU,Status of wakeup source of USART10 change event" "0,1"
newline
endif
rbitfld.long 0x4 2. "WTWU,Status of wakeup source of watch timer event" "0,1"
rbitfld.long 0x4 1. "WDTWU,Status of wakeup source of watchdog timer event" "0,1"
newline
rbitfld.long 0x4 0. "LVDWU,Status of wakeup source of LVD event" "0,1"
line.long 0x8 "RSER,Reset source enable register"
bitfld.long 0x8 6. "PINRST,External pin reset enable bit" "0,1"
bitfld.long 0x8 5. "CPURST,CPU request reset enable bit" "0,1"
newline
bitfld.long 0x8 4. "SWRST,Software reset enable bit" "0,1"
bitfld.long 0x8 3. "WDTRST,Watchdog Timer reset enable bit" "0,1"
newline
bitfld.long 0x8 2. "MCKFRST,MCLK Clock fail reset enable bit" "0,1"
bitfld.long 0x8 1. "MOFRST,MOSC Clock fail reset enable bit" "0,1"
newline
bitfld.long 0x8 0. "LVDRST,LVD reset enable bit" "0,1"
line.long 0xC "RSSR,Reset source status register"
bitfld.long 0xC 7. "PORST,Power on reset status bit" "0,1"
bitfld.long 0xC 6. "PINRST,External pin reset status bit" "0,1"
newline
bitfld.long 0xC 5. "CPURST,CPU request reset status bit" "0,1"
bitfld.long 0xC 4. "SWRST,Software reset status bit" "0,1"
newline
bitfld.long 0xC 3. "WDTRST,Watchdog Timer reset status bit" "0,1"
bitfld.long 0xC 2. "MCKFRST,MCLK Clock fail reset status bit" "0,1"
newline
bitfld.long 0xC 1. "MOFRST,MOSC Clock fail reset status bit" "0,1"
bitfld.long 0xC 0. "LVDRST,LVD reset status bit" "0,1"
line.long 0x10 "PRER1,Peripheral reset enable register 1"
bitfld.long 0x10 31. "WT,WT reset mask" "0,1"
bitfld.long 0x10 26. "TIMER21,TIMER21 reset mask" "0,1"
newline
bitfld.long 0x10 25. "TIMER20,TIMER20 reset mask" "0,1"
bitfld.long 0x10 24. "TIMER30,TIMER30 reset mask" "0,1"
newline
sif (cpuis("A31G31*"))
bitfld.long 0x10 22. "TIMER16,TIMER16 reset mask" "0,1"
bitfld.long 0x10 21. "TIMER15,TIMER15 reset mask" "0,1"
newline
bitfld.long 0x10 20. "TIMER14,TIMER14 reset mask" "0,1"
bitfld.long 0x10 12. "GPIOE,GPIOE reset mask" "0,1"
newline
bitfld.long 0x10 11. "GPIOD,GPIOD reset mask" "0,1"
bitfld.long 0x10 3. "PCU,PCU reset mask" "0,1"
newline
bitfld.long 0x10 2. "WDT,WDT reset mask" "0,1"
bitfld.long 0x10 1. "FMC,FMC reset mask" "0,1"
newline
bitfld.long 0x10 0. "SCU,SCU reset mask" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x10 20. "TIMER40,TIMER40 reset mask" "0,1"
newline
endif
bitfld.long 0x10 19. "TIMER13,TIMER13 reset mask" "0,1"
bitfld.long 0x10 18. "TIMER12,TIMER12 reset mask" "0,1"
newline
bitfld.long 0x10 17. "TIMER11,TIMER11 reset mask" "0,1"
bitfld.long 0x10 16. "TIMER10,TIMER10 reset mask" "0,1"
newline
bitfld.long 0x10 13. "GPIOF,GPIOF reset mask" "0,1"
bitfld.long 0x10 10. "GPIOC,GPIOC reset mask" "0,1"
newline
bitfld.long 0x10 9. "GPIOB,GPIOB reset mask" "0,1"
bitfld.long 0x10 8. "GPIOA,GPIOA reset mask" "0,1"
newline
sif (cpuis("A31G32*"))
bitfld.long 0x10 5. "EBI,EBI reset mask" "0,1"
endif
bitfld.long 0x10 4. "DMA,DMA reset mask" "0,1"
line.long 0x14 "PRER2,Peripheral reset enable register 2"
bitfld.long 0x14 31. "CRC,CRC reset mask" "0,1"
sif (cpuis("A31G32*"))
bitfld.long 0x14 29. "RTC,RTC reset mask" "0,1"
newline
endif
sif (cpuis("A31G31*"))
bitfld.long 0x14 29. "LED,LED reset mask" "0,1"
bitfld.long 0x14 28. "LCD,LCD reset mask" "0,1"
newline
bitfld.long 0x14 25. "TOUCH,TOUCH reset mask" "0,1"
bitfld.long 0x14 24. "ADPCM,ADPCM reset mask" "0,1"
newline
bitfld.long 0x14 23. "CMP,CMP reset mask" "0,1"
bitfld.long 0x14 17. "HSICMU,HSICMU reset mask" "0,1"
newline
bitfld.long 0x14 13. "UART1,UART1 reset mask" "0,1"
bitfld.long 0x14 12. "UART0,UART0 reset mask" "0,1"
newline
bitfld.long 0x14 6. "I2C2,I2C2 reset mask" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x14 27. "TSENSE,TSENSE reset mask" "0,1"
newline
endif
sif (cpuis("A31G32*"))
bitfld.long 0x14 23. "COMP,COMP reset mask" "0,1"
endif
bitfld.long 0x14 22. "DAC,DAC reset mask" "0,1"
newline
bitfld.long 0x14 20. "ADC,ADC reset mask" "0,1"
bitfld.long 0x14 16. "USB,USB reset mask" "0,1"
newline
bitfld.long 0x14 11. "USART13,USART13 reset mask" "0,1"
bitfld.long 0x14 10. "USART12,USART12 reset mask" "0,1"
newline
bitfld.long 0x14 9. "USART11,USART11 reset mask" "0,1"
bitfld.long 0x14 8. "USART10,USART10 reset mask" "0,1"
newline
bitfld.long 0x14 5. "I2C1,I2C1 reset mask" "0,1"
bitfld.long 0x14 4. "I2C0,I2C0 reset mask" "0,1"
newline
sif (cpuis("A31G32*"))
bitfld.long 0x14 3. "SPI21,SPI21 reset mask" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x14 2. "SPI20,SPI20 reset mask" "0,1"
endif
line.long 0x18 "PER1,Peripheral enable register 1"
bitfld.long 0x18 31. "WT,WT function enable" "0,1"
bitfld.long 0x18 26. "TIMER21,TIMER21 function enable" "0,1"
newline
bitfld.long 0x18 25. "TIMER20,TIMER20 function enable" "0,1"
bitfld.long 0x18 24. "TIMER30,TIMER30 function enable" "0,1"
newline
sif (cpuis("A31G31*"))
bitfld.long 0x18 22. "TIMER16,TIMER16 function enable" "0,1"
bitfld.long 0x18 21. "TIMER15,TIMER15 function enable" "0,1"
newline
bitfld.long 0x18 20. "TIMER14,TIMER14 function enable" "0,1"
bitfld.long 0x18 12. "GPIOE,GPIOE function enable" "0,1"
newline
bitfld.long 0x18 11. "GPIOD,GPIOD function enable" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x18 20. "TIMER40,TIMER40 function enable" "0,1"
newline
endif
bitfld.long 0x18 19. "TIMER13,TIMER13 function enable" "0,1"
bitfld.long 0x18 18. "TIMER12,TIMER12 function enable" "0,1"
newline
bitfld.long 0x18 17. "TIMER11,TIMER11 function enable" "0,1"
bitfld.long 0x18 16. "TIMER10,TIMER10 function enable" "0,1"
newline
bitfld.long 0x18 13. "GPIOF,GPIOF function enable" "0,1"
bitfld.long 0x18 10. "GPIOC,GPIOC function enable" "0,1"
newline
bitfld.long 0x18 9. "GPIOB,GPIOB function enable" "0,1"
bitfld.long 0x18 8. "GPIOA,GPIOA function enable" "0,1"
newline
sif (cpuis("A31G32*"))
bitfld.long 0x18 5. "EBI,EBI function enable" "0,1"
endif
bitfld.long 0x18 4. "DMA,DMA function enable" "0,1"
line.long 0x1C "PER2,Peripheral enable register 2"
bitfld.long 0x1C 31. "CRC,CRC function enable" "0,1"
sif (cpuis("A31G32*"))
bitfld.long 0x1C 29. "RTC,RTC function enable" "0,1"
newline
endif
sif (cpuis("A31G31*"))
bitfld.long 0x1C 29. "LED,LED function enable" "0,1"
bitfld.long 0x1C 28. "LCD,LCD function enable" "0,1"
newline
bitfld.long 0x1C 25. "TOUCH,TOUCH function enable" "0,1"
bitfld.long 0x1C 24. "ADPCM,ADPCM function enable" "0,1"
newline
bitfld.long 0x1C 23. "CMP,CMP function enable" "0,1"
bitfld.long 0x1C 17. "SOFCTMR,SOFCTMR function enable" "0,1"
newline
bitfld.long 0x1C 13. "UART1,UART1 function enable" "0,1"
bitfld.long 0x1C 12. "UART0,UART0 function enable" "0,1"
newline
bitfld.long 0x1C 6. "I2C2,I2C2 function enable" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x1C 27. "TSENSE,TSENSE function enable" "0,1"
newline
endif
sif (cpuis("A31G32*"))
bitfld.long 0x1C 23. "COMP,COMP function enable" "0,1"
endif
bitfld.long 0x1C 22. "DAC,DAC function enable" "0,1"
newline
bitfld.long 0x1C 20. "ADC,ADC function enable" "0,1"
bitfld.long 0x1C 16. "USB,USB function enable" "0,1"
newline
bitfld.long 0x1C 11. "USART13,USART13 function enable" "0,1"
bitfld.long 0x1C 10. "USART12,USART12 function enable" "0,1"
newline
bitfld.long 0x1C 9. "USART11,USART11 function enable" "0,1"
bitfld.long 0x1C 8. "USART10,USART10 function enable" "0,1"
newline
bitfld.long 0x1C 5. "I2C1,I2C1 function enable" "0,1"
bitfld.long 0x1C 4. "I2C0,I2C0 function enable" "0,1"
newline
sif (cpuis("A31G32*"))
bitfld.long 0x1C 3. "SPI21,SPI21 function enable" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x1C 2. "SPI20,SPI20 function enable" "0,1"
endif
line.long 0x20 "PCER1,Peripheral clock enable register 1"
bitfld.long 0x20 31. "WT,WT clock enable" "0,1"
bitfld.long 0x20 26. "TIMER21,TIMER21 clock enable" "0,1"
newline
bitfld.long 0x20 25. "TIMER20,TIMER20 clock enable" "0,1"
bitfld.long 0x20 24. "TIMER30,TIMER30 clock enable" "0,1"
newline
sif (cpuis("A31G31*"))
bitfld.long 0x20 22. "TIMER16,TIMER16 clock enable" "0,1"
bitfld.long 0x20 20. "TIMER14,TIMER14 clock enable" "0,1"
newline
bitfld.long 0x20 12. "GPIOE,GPIOE clock enable" "0,1"
bitfld.long 0x20 11. "GPIOD,GPIOD clock enable" "0,1"
newline
endif
sif (cpuis("A31G32*"))
bitfld.long 0x20 20. "TIMER40,TIMER40 clock enable" "0,1"
endif
bitfld.long 0x20 19. "TIMER13,TIMER13 clock enable" "0,1"
newline
bitfld.long 0x20 18. "TIMER12,TIMER12 clock enable" "0,1"
bitfld.long 0x20 17. "TIMER11,TIMER11 clock enable" "0,1"
newline
bitfld.long 0x20 16. "TIMER10,TIMER10 clock enable" "0,1"
bitfld.long 0x20 13. "GPIOF,GPIOF clock enable" "0,1"
newline
bitfld.long 0x20 10. "GPIOC,GPIOC clock enable" "0,1"
bitfld.long 0x20 9. "GPIOB,GPIOB clock enable" "0,1"
newline
bitfld.long 0x20 8. "GPIOA,GPIOA clock enable" "0,1"
sif (cpuis("A31G32*"))
bitfld.long 0x20 5. "EBI,EBI clock enable" "0,1"
newline
endif
bitfld.long 0x20 4. "DMA,DMA clock enable" "0,1"
line.long 0x24 "PCER2,Peripheral clock enable register 2"
bitfld.long 0x24 31. "CRC,CRC clock enable" "0,1"
sif (cpuis("A31G32*"))
bitfld.long 0x24 29. "RTC,RTC clock enable" "0,1"
newline
endif
sif (cpuis("A31G31*"))
bitfld.long 0x24 29. "LED,LED clock enable" "0,1"
bitfld.long 0x24 28. "LCD,LCD clock enable" "0,1"
newline
bitfld.long 0x24 25. "TOUCH,TOUCH clock enable" "0,1"
bitfld.long 0x24 24. "ADPCM,ADPCM clock enable" "0,1"
newline
bitfld.long 0x24 23. "CMP,CMP clock enable" "0,1"
bitfld.long 0x24 17. "HSICMU,HSICMU clock enable" "0,1"
newline
bitfld.long 0x24 13. "UART1,UART1 clock enable" "0,1"
bitfld.long 0x24 12. "UART0,UART0 clock enable" "0,1"
newline
bitfld.long 0x24 6. "I2C2,I2C2 clock enable" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x24 27. "TSENSE,TSENSE clock enable" "0,1"
newline
endif
sif (cpuis("A31G32*"))
bitfld.long 0x24 23. "COMP,COMP clock enable" "0,1"
endif
bitfld.long 0x24 22. "DAC,DAC clock enable" "0,1"
newline
bitfld.long 0x24 20. "ADC,ADC clock enable" "0,1"
bitfld.long 0x24 16. "USB,USB clock enable" "0,1"
newline
bitfld.long 0x24 11. "USART13,USART13 clock enable" "0,1"
bitfld.long 0x24 10. "USART12,USART12 clock enable" "0,1"
newline
bitfld.long 0x24 9. "USART11,USART11 clock enable" "0,1"
bitfld.long 0x24 8. "USART10,USART10 clock enable" "0,1"
newline
bitfld.long 0x24 5. "I2C1,I2C1 clock enable" "0,1"
bitfld.long 0x24 4. "I2C0,I2C0 clock enable" "0,1"
newline
sif (cpuis("A31G32*"))
bitfld.long 0x24 3. "SPI21,SPI21 clock enable" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x24 2. "SPI20,SPI20 clock enable" "0,1"
endif
line.long 0x28 "PPCLKSR,Peripheral clock selection register"
bitfld.long 0x28 22. "T1xCLK,Timer 1x Clock Selection bit" "0,1"
bitfld.long 0x28 20. "T20CLK,Timer 20 Clock Selection bit" "0,1"
newline
sif (cpuis("A31G32*"))
bitfld.long 0x28 19. "T21CLK,Timer21 Clock Selection bit" "0,1"
endif
bitfld.long 0x28 17. "T30CLK,Timer 30 Clock Selection bit" "0,1"
newline
sif (cpuis("A31G32*"))
bitfld.long 0x28 16. "T40CLK,Timer40 Clock Selection bit" "0,1"
endif
sif (cpuis("A31G31*"))
bitfld.long 0x28 10. "LEDCLK,LED Clock Selection bit" "0,1"
newline
bitfld.long 0x28 6.--7. "LCDCLK,LCD Driver Clock Selection bit" "0,1,2,3"
endif
bitfld.long 0x28 9. "USBCLK,USB Clock Selection bit" "0,1"
newline
sif (cpuis("A31G32*"))
bitfld.long 0x28 5. "RTCCLK,RTC Clock Selection bit" "0,1"
endif
bitfld.long 0x28 3.--4. "WTCLK,Watch Timer Clock Selection bit" "0,1,2,3"
newline
bitfld.long 0x28 0. "WDTCLK,Watch-dog Timer Clock Selection bit" "0,1"
group.long 0x40++0x13
line.long 0x0 "CSCR,Clock Source Control register"
hexmask.long.word 0x0 16.--31. 1. "WTIDKY,On writes write 0xA507 to these bits otherwise the write is ignored."
hexmask.long.byte 0x0 12.--15. 1. "SOSCCON,External crystal sub oscillator control"
newline
hexmask.long.byte 0x0 8.--11. 1. "LSICON,Low speed internal oscillator control"
hexmask.long.byte 0x0 4.--7. 1. "HSICON,High speed internal oscillator control"
newline
hexmask.long.byte 0x0 0.--3. 1. "MOSCCON,External crystal main oscillator control"
line.long 0x4 "SCCR,System Clock Control register"
hexmask.long.word 0x4 16.--31. 1. "WTIDKY,On writes write 0x570A to these bits otherwise the write is ignored."
sif (cpuis("A31G32*"))
bitfld.long 0x4 2. "PLLINCLKSEL,PLL input source select register" "0,1"
newline
endif
sif (cpuis("A31G31*"))
bitfld.long 0x4 2. "FINSEL,PLL input source FIN select register" "0,1"
endif
bitfld.long 0x4 0.--1. "MCLKSEL,System clock select register" "0,1,2,3"
line.long 0x8 "CMR,Clock Monitoring register"
bitfld.long 0x8 15. "MCLKREC,MCLK fail auto recovery" "0,1"
bitfld.long 0x8 11. "SOSCMNT,External sub oscillator monitoring enable" "0,1"
newline
bitfld.long 0x8 10. "SOSCIE,External sub oscillator fail interrupt enable" "0,1"
bitfld.long 0x8 9. "SOSCFAIL,External sub oscillator fail interrupt" "0,1"
newline
bitfld.long 0x8 8. "SOSCSTS,External sub oscillator status" "0,1"
bitfld.long 0x8 7. "MCLKMNT,MCLK monitoring enable" "0,1"
newline
bitfld.long 0x8 6. "MCLKIE,MCLK fail interrupt enable" "0,1"
bitfld.long 0x8 5. "MCLKFAIL,MCLK fail interrupt" "0,1"
newline
bitfld.long 0x8 4. "MCLKSTS,MCLK clock status" "0,1"
bitfld.long 0x8 3. "MOSCMNT,External main oscillator monitoring enable" "0,1"
newline
bitfld.long 0x8 2. "MOSCIE,External main oscillator fail interrupt enable" "0,1"
bitfld.long 0x8 1. "MOSCFAIL,External main oscillator fail interrupt" "0,1"
newline
bitfld.long 0x8 0. "MOSCSTS,External main oscillator status" "0,1"
line.long 0xC "NMIR,NMI control register"
hexmask.long.word 0xC 16.--31. 1. "ACCESSCODE,This field enables writing access to this register."
rbitfld.long 0xC 10. "WDTINTSTS,WDT Interrupt condition status bit" "0,1"
newline
rbitfld.long 0xC 9. "MCLKFAILSTS,MCLK Fail condition status bit" "0,1"
rbitfld.long 0xC 8. "LVDSTS,LVD condition status bit" "0,1"
newline
bitfld.long 0xC 2. "WDTINTEN,WDT Interrupt condition enable for NMI interrupt" "0,1"
bitfld.long 0xC 1. "MCLKFAILEN,MCLK Fail condition enable for NMI interrupt" "0,1"
newline
bitfld.long 0xC 0. "LVDEN,LVD Fail condition enable for NMI interrupt" "0,1"
line.long 0x10 "COR,Clock Output Control register"
bitfld.long 0x10 4. "CLKOEN,Clock output enable" "0,1"
hexmask.long.byte 0x10 0.--3. 1. "CLKODIV,Clock output divider value"
group.long 0x60++0x7
line.long 0x0 "PLLCON,PLL Control register"
sif (cpuis("A31G31*"))
bitfld.long 0x0 31. "LOCK,LOCK status" "0,1"
bitfld.long 0x0 20. "PLLMODE,PLL VCO mode" "0,1"
newline
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 31. "PLLLOCK,LOCK status" "0,1"
endif
bitfld.long 0x0 23. "PLLRSTB,PLL reset" "0,1"
newline
bitfld.long 0x0 22. "PLLEN,PLL enable" "0,1"
bitfld.long 0x0 21. "BYPASSB,FIN bypass" "0,1"
newline
bitfld.long 0x0 16.--18. "PREDIV,FIN predivider" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 8.--15. 1. "POSTDIV1,Feedback control 1 (N1)"
newline
hexmask.long.byte 0x0 4.--7. 1. "POSTDIV2,Feedback control 1 (N2)"
bitfld.long 0x0 0.--2. "OUTDIV,output divider control (P)" "0,1,2,3,4,5,6,7"
line.long 0x4 "VDCCON,VDC Control register"
hexmask.long.byte 0x4 28.--31. 1. "VDC33_WTIDKY,VDC33 Write Identification Key"
bitfld.long 0x4 27. "VDC33_PDBGR,VDC33 BGR Power Down Signal" "0,1"
newline
bitfld.long 0x4 26. "VDC33_STOP,VDC33 STOP Mode Enable Signal" "0,1"
bitfld.long 0x4 25. "VDC33_BYPASS,VDC33 Bypass Mode Enable Signal" "0,1"
newline
bitfld.long 0x4 24. "VDC33_LOCK,VDC33 VDC option write enable." "0,1"
hexmask.long.byte 0x4 20.--23. 1. "VDC15_WTIDKY,VDC15 Write Identification Key"
newline
sif (cpuis("A31G31*"))
bitfld.long 0x4 19. "VDC15_PDBGR,VDC15 1.2V BGR / 1.0V Buffer Power Down Signal" "0,1"
bitfld.long 0x4 17. "VDC15_STOP,VDC15 STOP Mode Control Signal" "0,1"
newline
bitfld.long 0x4 16. "VDC15_IDLE,VDC15 STOP1 Mode Control Signal" "0,1"
bitfld.long 0x4 15. "VDC15_LOCK,VDC15 VDCLOCK Control Signal for *BGR Stabilization" "0,1"
newline
endif
sif (cpuis("A31G32*"))
bitfld.long 0x4 18. "VDC15_STBY,Power down mode selection signal when cpu enters deepsleep mode" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x4 9. "VDC33_PD,VDC33 Power Down Signal" "0,1"
newline
endif
bitfld.long 0x4 8. "VDCWDLY_WEN,VDCWDLY value write enable. VDCWDLY value can be written with writing '1' to VDCWDLY_WEN bit simultaneously." "0,1"
hexmask.long.byte 0x4 0.--7. 1. "VDCWDLY,VDC warm-up delay count value."
sif (cpuis("A31G31*"))
group.long 0x6C++0x3
line.long 0x0 "ROSCCON,ROSC Control Register"
bitfld.long 0x0 1. "EN_LDO,Internal LDO On/Off" "0,1"
bitfld.long 0x0 0. "SKIP_LS,Internal Level Shifter control signal" "0,1"
endif
sif (cpuis("A31G32*"))
group.long 0x68++0x7
line.long 0x0 "PDRCON,PDR Control register"
hexmask.long.byte 0x0 8.--11. 1. "PDRCON_WTIDKY,PDRCON Write Identification Key On writes.write 0xA to these bits otherwise the write is ignored."
bitfld.long 0x0 7. "PDREN,PDR ENABLE" "0,1"
newline
bitfld.long 0x0 6. "PDR_SYNC_EN,PDR_SYNC_EN" "0,1"
bitfld.long 0x0 5. "BPMC_SYNC_EN,BPMC_SYNC_EN" "0,1"
newline
hexmask.long.byte 0x0 0.--3. 1. "PDR_DEBOUNCE,PDR_DEBOUNCE"
line.long 0x4 "LSICON,Low Speed Internal OSC Control Register"
bitfld.long 0x4 1. "EN_LDO,Internal LDO On/Off" "0,1"
bitfld.long 0x4 0. "SKIP_LS,Internal Level Shifter control signal" "0,1"
group.long 0x88++0x3
line.long 0x0 "RSTDBCR,Pin Reset Debounce Control register"
hexmask.long.word 0x0 16.--31. 1. "WTIDKY,Write Identification Key"
hexmask.long.byte 0x0 8.--13. 1. "CLKCNT,Noise Cancel delay Option for External MOSC"
newline
bitfld.long 0x0 0. "EN,Pin reset debounce enable bit" "0,1"
endif
group.long 0x80++0x3
line.long 0x0 "EOSCR,External Oscillator control register"
bitfld.long 0x0 15. "ESEN,Write enable for External SOSC" "0,1"
bitfld.long 0x0 12.--13. "ESISEL,Internal Level Shifter control signal" "0,1,2,3"
newline
sif (cpuis("A31G32*"))
bitfld.long 0x0 8. "ESSMT,Select Schmitt trigger" "0,1"
endif
sif (cpuis("A31G31*"))
bitfld.long 0x0 8. "ESNCBYPS,Noise Cancel Bypass enable for External SOSC" "0,1"
newline
endif
bitfld.long 0x0 7. "EMEN,Write enable for External MOSC" "0,1"
bitfld.long 0x0 4.--5. "ISE,Select current for External MOSC" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "NCOPT,Noise Cancel delay Option for External MOSC" "0,1,2,3"
bitfld.long 0x0 0. "NCSKIP,Noise Cancel Bypass enable for External SOSC" "0,1"
rgroup.long 0x84++0x3
line.long 0x0 "EMODR,External mode pin read register"
bitfld.long 0x0 2. "SCANMD,SCAN Mode level" "0,1"
bitfld.long 0x0 1. "TEST,TEST Mode level" "0,1"
newline
bitfld.long 0x0 0. "BOOT,BOOT pin level" "0,1"
group.long 0x90++0x17
line.long 0x0 "MCCR1,Miscellaneous Clock Control Register 1"
bitfld.long 0x0 24.--26. "TEXT1CSEL,TIMER1n EXT Clock source select bit" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 16.--23. 1. "TEXT1DIV,TIMER1n EXT Clock N divider"
newline
bitfld.long 0x0 8.--10. "STCSEL,systick clock source sel" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 0.--7. 1. "STDIV,SYSTICK Clock N divider"
line.long 0x4 "MCCR2,Miscellaneous Clock Control Register 2"
bitfld.long 0x4 24.--26. "TEXT3CSEL,TIMER 30 EXT Clock source select bit" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 16.--23. 1. "TEXT3DIV,TIMER 30 EXT Clock N divider"
newline
sif (cpuis("A31G32*"))
bitfld.long 0x4 8.--10. "TEXT20CSEL,TIMER20 EXT Clock source select bit" "0,1,2,3,4,5,6,7"
endif
sif (cpuis("A31G31*"))
bitfld.long 0x4 8.--10. "TEXT2CSEL,TEXT2CSEL" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 0.--7. 1. "TEXT2DIV,TIMER 20 EXT Clock N divider"
endif
sif (cpuis("A31G32*"))
hexmask.long.byte 0x4 0.--7. 1. "TEXT20DIV,TIMER20 EXT Clock N divider"
endif
line.long 0x8 "MCCR3,Miscellaneous Clock Control Register 3"
bitfld.long 0x8 24.--26. "WTEXTCSEL,WTEXTCSEL" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x8 16.--23. 1. "WTEXTCDIV,WT External Clock N divider"
newline
sif (cpuis("A31G32*"))
bitfld.long 0x8 11. "LSI40kHz,LSI40kHz Enable" "0,1"
endif
bitfld.long 0x8 8.--10. "WDTCSEL,WDT clock sel" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x8 0.--7. 1. "WDTDIV,WDT Clock N divider"
line.long 0xC "MCCR4,Miscellaneous Clock Control Register 4"
sif (cpuis("A31G31*"))
bitfld.long 0xC 24.--26. "PD1CSEL,Debounce Clock for PORT source select bit (PD PE PF)" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xC 16.--23. 1. "PD1DIV,PORT Debounce Clock N divider (PD PE PF)"
newline
endif
bitfld.long 0xC 8.--10. "PD0CSEL,Debounce Clock for PORT source select bit (PA PB PC)" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xC 0.--7. 1. "PD0DIV,PORT Debounce Clock N divider (PA PB PC)"
line.long 0x10 "MCCR5,Miscellaneous Clock Control Register 5"
sif (cpuis("A31G31*"))
bitfld.long 0x10 24.--26. "LCDCSEL,LCD Clock source select bit" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x10 16.--23. 1. "LCDDIV,LCD Clock N divider"
newline
bitfld.long 0x10 8.--10. "LEDCSEL,LED Clock source select bit" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x10 0.--7. 1. "LEDDIV,LED Clock N divider"
newline
endif
sif (cpuis("A31G32*"))
bitfld.long 0x10 24.--26. "USBCSEL,USB Clock source select bit" "0,1,2,3,4,5,6,7"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x10 16. "USBEXTCLKEN,USB External Clock Enable" "0,1"
newline
endif
sif (cpuis("A31G32*"))
bitfld.long 0x10 14.--15. "TSREFCLK_SEL,Temp Sensor Reference clock select bit" "0,1,2,3"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x10 12.--13. "TSSENSECLK_SEL,Temp Sensor Sense clock select bit" "0,1,2,3"
newline
endif
sif (cpuis("A31G32*"))
bitfld.long 0x10 11. "LSITS_EN,LSITS Enable" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x10 8.--10. "RTCCSEL,RTC Clock source select bit" "0,1,2,3,4,5,6,7"
newline
endif
sif (cpuis("A31G32*"))
hexmask.long.byte 0x10 0.--7. 1. "RTCDIV,RTC Clock N divider"
endif
line.long 0x14 "MCCR6,Miscellaneous Clock Control Register 6"
sif (cpuis("A31G31*"))
bitfld.long 0x14 24.--26. "USBCSEL,USB Clock source select bit" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x14 16.--23. 1. "USBCDIV,USB Clock N divider"
newline
endif
sif (cpuis("A31G32*"))
bitfld.long 0x14 24.--26. "TEXT21CSEL,TIMER21 EXT Clock source select bit" "0,1,2,3,4,5,6,7"
endif
sif (cpuis("A31G32*"))
hexmask.long.byte 0x14 16.--23. 1. "TEXT21DIV,TIMER21 EXT Clock N divider"
newline
endif
sif (cpuis("A31G32*"))
bitfld.long 0x14 8.--10. "TEXT4CSEL,TIMER40 EXT Clock source select bit" "0,1,2,3,4,5,6,7"
endif
sif (cpuis("A31G32*"))
hexmask.long.byte 0x14 0.--7. 1. "TEXT4DIV,TIMER40 EXT Clock N divider"
endif
tree.end
tree "SCUCC (Chip Configuration)"
base ad:0x4000F000
rgroup.long 0x0++0xB
line.long 0x0 "VENDORID,Vendor Identification Register"
hexmask.long 0x0 0.--31. 1. "VENDID,Vendor Identification bits"
line.long 0x4 "CHIPID,Chip Identification Register"
hexmask.long 0x4 0.--31. 1. "CHIPID,Chip Identification bits. 0x4D31F000: 32k bytes flash memory for program 0x4D31F001: 16k bytes flash memory for program"
line.long 0x8 "REVNR,Revision Number Register"
hexmask.long.byte 0x8 0.--7. 1. "REVNO,Chip Revision Number. These bits are fixed by manufacturer."
tree.end
tree "SCULV (LVI and LVR)"
base ad:0x40005100
group.long 0x0++0xB
line.long 0x0 "LVICR,Low Voltage Indicator Control Register"
bitfld.long 0x0 7. "LVIEN,LVI Enable bit" "0,1"
bitfld.long 0x0 5. "LVINTEN,LVI Interrupt Enable bit" "0,1"
bitfld.long 0x0 4. "LVIFLAG,LVI Interrupt Flag bit" "0,1"
hexmask.long.byte 0x0 0.--3. 1. "LVIVS,LVI Voltage Selection bits"
line.long 0x4 "LVRCR,Low Voltage Reset Control Register"
hexmask.long.byte 0x4 0.--7. 1. "LVREN,LVR Enable bits"
line.long 0x8 "LVRCNFIG,Configuration for Low Voltage Reset"
hexmask.long.word 0x8 16.--31. 1. "WTIDKY,Write Identification Key"
hexmask.long.byte 0x8 8.--15. 1. "LVRENM,LVR Reset Operation Control Master Configuration"
hexmask.long.byte 0x8 0.--7. 1. "LVRVS,LVR Voltage Selection bits"
tree.end
tree.end
tree "TC (Timer/Counter)"
base ad:0x0
tree "TIMER10"
base ad:0x40002100
group.long 0x0++0xB
line.long 0x0 "CR,Timer/Counter n Control Register"
bitfld.long 0x0 15. "TnEN,Timer n Operation Enable bit" "0,1"
bitfld.long 0x0 14. "TnCLK,Timer n Clock Selection bit (Note: This bit should be changed during TnEN bit is '0b'.)" "0,1"
bitfld.long 0x0 12.--13. "TnMS,Timer n Operation Mode Selection bits (Note: These bits should be changed during TnEN bit is '0b'.)" "0,1,2,3"
bitfld.long 0x0 11. "TnECE,Timer n External Clock Edge Selection bit" "0,1"
bitfld.long 0x0 8. "TnOPOL,TnOUT Polarity Selection bit" "0,1"
bitfld.long 0x0 6.--7. "TnCPOL,Timer n Capture Polarity Selection bits" "0,1,2,3"
bitfld.long 0x0 5. "TnMIEN,Timer n Match Interrupt Enable bit" "0,1"
bitfld.long 0x0 4. "TnCIEN,Timer n Capture Interrupt Enable bit" "0,1"
bitfld.long 0x0 3. "TnMIFLAG,Timer n Match Interrupt Flag bit" "0,1"
bitfld.long 0x0 2. "TnCIFLAG,Timer n Capture Interrupt Flag bit" "0,1"
bitfld.long 0x0 1. "TnPAU,Timer n Counter Temporary Pause Control bit" "0,1"
bitfld.long 0x0 0. "TnCLR,Timer n Counter and Prescaler Clear bit" "0,1"
line.long 0x4 "ADR,Timer/Counter n A Data Register"
hexmask.long.word 0x4 0.--15. 1. "ADATA,Timer/Counter n A Data bits. The range is 0x0000 to 0xFFFF. Note: Do not write '0000H' in the TnADR register when PPG mode."
line.long 0x8 "BDR,Timer/Counter n B Data Register"
hexmask.long.word 0x8 0.--15. 1. "BDATA,Timer/Counter n B Data bits. The range is 0x0000 to 0xFFFF."
rgroup.long 0xC++0x3
line.long 0x0 "CAPDR,Timer/Counter n Capture Data Register"
hexmask.long.word 0x0 0.--15. 1. "CAPD,Timer/Counter n Capture Data bits."
group.long 0x10++0x3
line.long 0x0 "PREDR,Timer/Counter n Prescaler Data Register"
hexmask.long.word 0x0 0.--11. 1. "PRED,Timer/Counter n Prescaler Data bits."
rgroup.long 0x14++0x3
line.long 0x0 "CNT,Timer/Counter n Counter Register"
hexmask.long.word 0x0 0.--15. 1. "CNT,Timer/Counter n Counter bits."
tree.end
tree "TIMER11"
base ad:0x40002200
group.long 0x0++0xB
line.long 0x0 "CR,Timer/Counter n Control Register"
bitfld.long 0x0 15. "TnEN,Timer n Operation Enable bit" "0,1"
bitfld.long 0x0 14. "TnCLK,Timer n Clock Selection bit (Note: This bit should be changed during TnEN bit is '0b'.)" "0,1"
bitfld.long 0x0 12.--13. "TnMS,Timer n Operation Mode Selection bits (Note: These bits should be changed during TnEN bit is '0b'.)" "0,1,2,3"
bitfld.long 0x0 11. "TnECE,Timer n External Clock Edge Selection bit" "0,1"
bitfld.long 0x0 8. "TnOPOL,TnOUT Polarity Selection bit" "0,1"
bitfld.long 0x0 6.--7. "TnCPOL,Timer n Capture Polarity Selection bits" "0,1,2,3"
bitfld.long 0x0 5. "TnMIEN,Timer n Match Interrupt Enable bit" "0,1"
bitfld.long 0x0 4. "TnCIEN,Timer n Capture Interrupt Enable bit" "0,1"
bitfld.long 0x0 3. "TnMIFLAG,Timer n Match Interrupt Flag bit" "0,1"
bitfld.long 0x0 2. "TnCIFLAG,Timer n Capture Interrupt Flag bit" "0,1"
bitfld.long 0x0 1. "TnPAU,Timer n Counter Temporary Pause Control bit" "0,1"
bitfld.long 0x0 0. "TnCLR,Timer n Counter and Prescaler Clear bit" "0,1"
line.long 0x4 "ADR,Timer/Counter n A Data Register"
hexmask.long.word 0x4 0.--15. 1. "ADATA,Timer/Counter n A Data bits. The range is 0x0000 to 0xFFFF. Note: Do not write '0000H' in the TnADR register when PPG mode."
line.long 0x8 "BDR,Timer/Counter n B Data Register"
hexmask.long.word 0x8 0.--15. 1. "BDATA,Timer/Counter n B Data bits. The range is 0x0000 to 0xFFFF."
rgroup.long 0xC++0x3
line.long 0x0 "CAPDR,Timer/Counter n Capture Data Register"
hexmask.long.word 0x0 0.--15. 1. "CAPD,Timer/Counter n Capture Data bits."
group.long 0x10++0x3
line.long 0x0 "PREDR,Timer/Counter n Prescaler Data Register"
hexmask.long.word 0x0 0.--11. 1. "PRED,Timer/Counter n Prescaler Data bits."
rgroup.long 0x14++0x3
line.long 0x0 "CNT,Timer/Counter n Counter Register"
hexmask.long.word 0x0 0.--15. 1. "CNT,Timer/Counter n Counter bits."
tree.end
tree "TIMER12"
base ad:0x40002300
group.long 0x0++0xB
line.long 0x0 "CR,Timer/Counter n Control Register"
bitfld.long 0x0 15. "TnEN,Timer n Operation Enable bit" "0,1"
bitfld.long 0x0 14. "TnCLK,Timer n Clock Selection bit (Note: This bit should be changed during TnEN bit is '0b'.)" "0,1"
bitfld.long 0x0 12.--13. "TnMS,Timer n Operation Mode Selection bits (Note: These bits should be changed during TnEN bit is '0b'.)" "0,1,2,3"
bitfld.long 0x0 11. "TnECE,Timer n External Clock Edge Selection bit" "0,1"
bitfld.long 0x0 8. "TnOPOL,TnOUT Polarity Selection bit" "0,1"
bitfld.long 0x0 6.--7. "TnCPOL,Timer n Capture Polarity Selection bits" "0,1,2,3"
bitfld.long 0x0 5. "TnMIEN,Timer n Match Interrupt Enable bit" "0,1"
bitfld.long 0x0 4. "TnCIEN,Timer n Capture Interrupt Enable bit" "0,1"
bitfld.long 0x0 3. "TnMIFLAG,Timer n Match Interrupt Flag bit" "0,1"
bitfld.long 0x0 2. "TnCIFLAG,Timer n Capture Interrupt Flag bit" "0,1"
bitfld.long 0x0 1. "TnPAU,Timer n Counter Temporary Pause Control bit" "0,1"
bitfld.long 0x0 0. "TnCLR,Timer n Counter and Prescaler Clear bit" "0,1"
line.long 0x4 "ADR,Timer/Counter n A Data Register"
hexmask.long.word 0x4 0.--15. 1. "ADATA,Timer/Counter n A Data bits. The range is 0x0000 to 0xFFFF. Note: Do not write '0000H' in the TnADR register when PPG mode."
line.long 0x8 "BDR,Timer/Counter n B Data Register"
hexmask.long.word 0x8 0.--15. 1. "BDATA,Timer/Counter n B Data bits. The range is 0x0000 to 0xFFFF."
rgroup.long 0xC++0x3
line.long 0x0 "CAPDR,Timer/Counter n Capture Data Register"
hexmask.long.word 0x0 0.--15. 1. "CAPD,Timer/Counter n Capture Data bits."
group.long 0x10++0x3
line.long 0x0 "PREDR,Timer/Counter n Prescaler Data Register"
hexmask.long.word 0x0 0.--11. 1. "PRED,Timer/Counter n Prescaler Data bits."
rgroup.long 0x14++0x3
line.long 0x0 "CNT,Timer/Counter n Counter Register"
hexmask.long.word 0x0 0.--15. 1. "CNT,Timer/Counter n Counter bits."
tree.end
tree "TIMER13"
base ad:0x40002700
group.long 0x0++0xB
line.long 0x0 "CR,Timer/Counter n Control Register"
bitfld.long 0x0 15. "TnEN,Timer n Operation Enable bit" "0,1"
bitfld.long 0x0 14. "TnCLK,Timer n Clock Selection bit (Note: This bit should be changed during TnEN bit is '0b'.)" "0,1"
bitfld.long 0x0 12.--13. "TnMS,Timer n Operation Mode Selection bits (Note: These bits should be changed during TnEN bit is '0b'.)" "0,1,2,3"
bitfld.long 0x0 11. "TnECE,Timer n External Clock Edge Selection bit" "0,1"
bitfld.long 0x0 8. "TnOPOL,TnOUT Polarity Selection bit" "0,1"
bitfld.long 0x0 6.--7. "TnCPOL,Timer n Capture Polarity Selection bits" "0,1,2,3"
bitfld.long 0x0 5. "TnMIEN,Timer n Match Interrupt Enable bit" "0,1"
bitfld.long 0x0 4. "TnCIEN,Timer n Capture Interrupt Enable bit" "0,1"
bitfld.long 0x0 3. "TnMIFLAG,Timer n Match Interrupt Flag bit" "0,1"
bitfld.long 0x0 2. "TnCIFLAG,Timer n Capture Interrupt Flag bit" "0,1"
bitfld.long 0x0 1. "TnPAU,Timer n Counter Temporary Pause Control bit" "0,1"
bitfld.long 0x0 0. "TnCLR,Timer n Counter and Prescaler Clear bit" "0,1"
line.long 0x4 "ADR,Timer/Counter n A Data Register"
hexmask.long.word 0x4 0.--15. 1. "ADATA,Timer/Counter n A Data bits. The range is 0x0000 to 0xFFFF. Note: Do not write '0000H' in the TnADR register when PPG mode."
line.long 0x8 "BDR,Timer/Counter n B Data Register"
hexmask.long.word 0x8 0.--15. 1. "BDATA,Timer/Counter n B Data bits. The range is 0x0000 to 0xFFFF."
rgroup.long 0xC++0x3
line.long 0x0 "CAPDR,Timer/Counter n Capture Data Register"
hexmask.long.word 0x0 0.--15. 1. "CAPD,Timer/Counter n Capture Data bits."
group.long 0x10++0x3
line.long 0x0 "PREDR,Timer/Counter n Prescaler Data Register"
hexmask.long.word 0x0 0.--11. 1. "PRED,Timer/Counter n Prescaler Data bits."
rgroup.long 0x14++0x3
line.long 0x0 "CNT,Timer/Counter n Counter Register"
hexmask.long.word 0x0 0.--15. 1. "CNT,Timer/Counter n Counter bits."
tree.end
sif (cpuis("A31G31*"))
tree "TIMER14"
base ad:0x40002800
group.long 0x0++0xB
line.long 0x0 "CR,Timer/Counter n Control Register"
bitfld.long 0x0 15. "TnEN,Timer n Operation Enable bit" "0,1"
bitfld.long 0x0 14. "TnCLK,Timer n Clock Selection bit (Note: This bit should be changed during TnEN bit is '0b'.)" "0,1"
bitfld.long 0x0 12.--13. "TnMS,Timer n Operation Mode Selection bits (Note: These bits should be changed during TnEN bit is '0b'.)" "0,1,2,3"
bitfld.long 0x0 11. "TnECE,Timer n External Clock Edge Selection bit" "0,1"
bitfld.long 0x0 8. "TnOPOL,TnOUT Polarity Selection bit" "0,1"
bitfld.long 0x0 6.--7. "TnCPOL,Timer n Capture Polarity Selection bits" "0,1,2,3"
bitfld.long 0x0 5. "TnMIEN,Timer n Match Interrupt Enable bit" "0,1"
bitfld.long 0x0 4. "TnCIEN,Timer n Capture Interrupt Enable bit" "0,1"
bitfld.long 0x0 3. "TnMIFLAG,Timer n Match Interrupt Flag bit" "0,1"
bitfld.long 0x0 2. "TnCIFLAG,Timer n Capture Interrupt Flag bit" "0,1"
bitfld.long 0x0 1. "TnPAU,Timer n Counter Temporary Pause Control bit" "0,1"
bitfld.long 0x0 0. "TnCLR,Timer n Counter and Prescaler Clear bit" "0,1"
line.long 0x4 "ADR,Timer/Counter n A Data Register"
hexmask.long.word 0x4 0.--15. 1. "ADATA,Timer/Counter n A Data bits. The range is 0x0000 to 0xFFFF. Note: Do not write '0000H' in the TnADR register when PPG mode."
line.long 0x8 "BDR,Timer/Counter n B Data Register"
hexmask.long.word 0x8 0.--15. 1. "BDATA,Timer/Counter n B Data bits. The range is 0x0000 to 0xFFFF."
rgroup.long 0xC++0x3
line.long 0x0 "CAPDR,Timer/Counter n Capture Data Register"
hexmask.long.word 0x0 0.--15. 1. "CAPD,Timer/Counter n Capture Data bits."
group.long 0x10++0x3
line.long 0x0 "PREDR,Timer/Counter n Prescaler Data Register"
hexmask.long.word 0x0 0.--11. 1. "PRED,Timer/Counter n Prescaler Data bits."
rgroup.long 0x14++0x3
line.long 0x0 "CNT,Timer/Counter n Counter Register"
hexmask.long.word 0x0 0.--15. 1. "CNT,Timer/Counter n Counter bits."
tree.end
tree "TIMER15"
base ad:0x40002900
group.long 0x0++0xB
line.long 0x0 "CR,Timer/Counter n Control Register"
bitfld.long 0x0 15. "TnEN,Timer n Operation Enable bit" "0,1"
bitfld.long 0x0 14. "TnCLK,Timer n Clock Selection bit (Note: This bit should be changed during TnEN bit is '0b'.)" "0,1"
bitfld.long 0x0 12.--13. "TnMS,Timer n Operation Mode Selection bits (Note: These bits should be changed during TnEN bit is '0b'.)" "0,1,2,3"
bitfld.long 0x0 11. "TnECE,Timer n External Clock Edge Selection bit" "0,1"
bitfld.long 0x0 8. "TnOPOL,TnOUT Polarity Selection bit" "0,1"
bitfld.long 0x0 6.--7. "TnCPOL,Timer n Capture Polarity Selection bits" "0,1,2,3"
bitfld.long 0x0 5. "TnMIEN,Timer n Match Interrupt Enable bit" "0,1"
bitfld.long 0x0 4. "TnCIEN,Timer n Capture Interrupt Enable bit" "0,1"
bitfld.long 0x0 3. "TnMIFLAG,Timer n Match Interrupt Flag bit" "0,1"
bitfld.long 0x0 2. "TnCIFLAG,Timer n Capture Interrupt Flag bit" "0,1"
bitfld.long 0x0 1. "TnPAU,Timer n Counter Temporary Pause Control bit" "0,1"
bitfld.long 0x0 0. "TnCLR,Timer n Counter and Prescaler Clear bit" "0,1"
line.long 0x4 "ADR,Timer/Counter n A Data Register"
hexmask.long.word 0x4 0.--15. 1. "ADATA,Timer/Counter n A Data bits. The range is 0x0000 to 0xFFFF. Note: Do not write '0000H' in the TnADR register when PPG mode."
line.long 0x8 "BDR,Timer/Counter n B Data Register"
hexmask.long.word 0x8 0.--15. 1. "BDATA,Timer/Counter n B Data bits. The range is 0x0000 to 0xFFFF."
rgroup.long 0xC++0x3
line.long 0x0 "CAPDR,Timer/Counter n Capture Data Register"
hexmask.long.word 0x0 0.--15. 1. "CAPD,Timer/Counter n Capture Data bits."
group.long 0x10++0x3
line.long 0x0 "PREDR,Timer/Counter n Prescaler Data Register"
hexmask.long.word 0x0 0.--11. 1. "PRED,Timer/Counter n Prescaler Data bits."
rgroup.long 0x14++0x3
line.long 0x0 "CNT,Timer/Counter n Counter Register"
hexmask.long.word 0x0 0.--15. 1. "CNT,Timer/Counter n Counter bits."
tree.end
tree "TIMER16"
base ad:0x40002A00
group.long 0x0++0xB
line.long 0x0 "CR,Timer/Counter n Control Register"
bitfld.long 0x0 15. "TnEN,Timer n Operation Enable bit" "0,1"
bitfld.long 0x0 14. "TnCLK,Timer n Clock Selection bit (Note: This bit should be changed during TnEN bit is '0b'.)" "0,1"
bitfld.long 0x0 12.--13. "TnMS,Timer n Operation Mode Selection bits (Note: These bits should be changed during TnEN bit is '0b'.)" "0,1,2,3"
bitfld.long 0x0 11. "TnECE,Timer n External Clock Edge Selection bit" "0,1"
bitfld.long 0x0 8. "TnOPOL,TnOUT Polarity Selection bit" "0,1"
bitfld.long 0x0 6.--7. "TnCPOL,Timer n Capture Polarity Selection bits" "0,1,2,3"
bitfld.long 0x0 5. "TnMIEN,Timer n Match Interrupt Enable bit" "0,1"
bitfld.long 0x0 4. "TnCIEN,Timer n Capture Interrupt Enable bit" "0,1"
bitfld.long 0x0 3. "TnMIFLAG,Timer n Match Interrupt Flag bit" "0,1"
bitfld.long 0x0 2. "TnCIFLAG,Timer n Capture Interrupt Flag bit" "0,1"
bitfld.long 0x0 1. "TnPAU,Timer n Counter Temporary Pause Control bit" "0,1"
bitfld.long 0x0 0. "TnCLR,Timer n Counter and Prescaler Clear bit" "0,1"
line.long 0x4 "ADR,Timer/Counter n A Data Register"
hexmask.long.word 0x4 0.--15. 1. "ADATA,Timer/Counter n A Data bits. The range is 0x0000 to 0xFFFF. Note: Do not write '0000H' in the TnADR register when PPG mode."
line.long 0x8 "BDR,Timer/Counter n B Data Register"
hexmask.long.word 0x8 0.--15. 1. "BDATA,Timer/Counter n B Data bits. The range is 0x0000 to 0xFFFF."
rgroup.long 0xC++0x3
line.long 0x0 "CAPDR,Timer/Counter n Capture Data Register"
hexmask.long.word 0x0 0.--15. 1. "CAPD,Timer/Counter n Capture Data bits."
group.long 0x10++0x3
line.long 0x0 "PREDR,Timer/Counter n Prescaler Data Register"
hexmask.long.word 0x0 0.--11. 1. "PRED,Timer/Counter n Prescaler Data bits."
rgroup.long 0x14++0x3
line.long 0x0 "CNT,Timer/Counter n Counter Register"
hexmask.long.word 0x0 0.--15. 1. "CNT,Timer/Counter n Counter bits."
tree.end
endif
tree "TIMER20"
base ad:0x40002500
group.long 0x0++0xB
line.long 0x0 "CR,Timer/Counter n Control Register"
sif (cpuis("A31G32*"))
bitfld.long 0x0 16. "CNCLR,Timer 2n counter clear after Capture" "0,1"
endif
sif (cpuis("A31G31*"))
bitfld.long 0x0 15. "TnEN,Timer n Operation Enable bit" "0,1"
bitfld.long 0x0 14. "TnCLK,Timer n Clock Selection bit (Note: This bit should be changed during TnEN bit is '0b'.)" "0,1"
bitfld.long 0x0 12.--13. "TnMS,Timer n Operation Mode Selection bits (Note: These bits should be changed during TnEN bit is '0b'.)" "0,1,2,3"
bitfld.long 0x0 11. "TnECE,Timer n External Clock Edge Selection bit" "0,1"
bitfld.long 0x0 8. "TnOPOL,TnOUT Polarity Selection bit" "0,1"
bitfld.long 0x0 6.--7. "TnCPOL,Timer n Capture Polarity Selection bits" "0,1,2,3"
bitfld.long 0x0 5. "TnMIEN,Timer n Match Interrupt Enable bit" "0,1"
bitfld.long 0x0 4. "TnCIEN,Timer n Capture Interrupt Enable bit" "0,1"
bitfld.long 0x0 3. "TnMIFLAG,Timer n Match Interrupt Flag bit" "0,1"
newline
bitfld.long 0x0 2. "TnCIFLAG,Timer n Capture Interrupt Flag bit" "0,1"
bitfld.long 0x0 1. "TnPAU,Timer n Counter Temporary Pause Control bit" "0,1"
bitfld.long 0x0 0. "TnCLR,Timer n Counter and Prescaler Clear bit" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 15. "EN,Timer n Operation Enable bit" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 14. "CLK,Timer n Clock Selection bit (Note: This bit should be changed during TnEN bit is '0b'.)" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 12.--13. "MS,Timer n Operation Mode Selection bits (Note: These bits should be changed during TnEN bit is '0b'.)" "0,1,2,3"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 11. "ECE,Timer n External Clock Edge Selection bit" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 8. "OPOL,TnOUT Polarity Selection bit" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 6.--7. "CPOL,Timer n Capture Polarity Selection bits" "0,1,2,3"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 5. "MIEN,Timer n Match Interrupt Enable bit" "0,1"
newline
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 4. "CIEN,Timer n Capture Interrupt Enable bit" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 3. "MIFLAG,Timer n Match Interrupt Flag bit" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 2. "CIFLAG,Timer n Capture Interrupt Flag bit" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 1. "PAU,Timer n Counter Temporary Pause Control bit" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 0. "CLR,Timer n Counter and Prescaler Clear bit" "0,1"
endif
line.long 0x4 "ADR,Timer/Counter n A Data Register"
hexmask.long 0x4 0.--31. 1. "ADATA,Timer/Counter n A Data bits. The range is 0x00000000 to 0xFFFFFFFF. Note: Do not write '00000000H' in the TnADR register when PPG mode."
line.long 0x8 "BDR,Timer/Counter n B Data Register"
hexmask.long 0x8 0.--31. 1. "BDATA,Timer/Counter n B Data bits. The range is 0x00000000 to 0xFFFFFFFF."
rgroup.long 0xC++0x3
line.long 0x0 "CAPDR,Timer/Counter n Capture Data Register"
hexmask.long 0x0 0.--31. 1. "CAPD,Timer/Counter n Capture Data bits."
group.long 0x10++0x3
line.long 0x0 "PREDR,Timer/Counter n Prescaler Data Register"
hexmask.long.word 0x0 0.--11. 1. "PRED,Timer/Counter n Prescaler Data bits.P"
rgroup.long 0x14++0x3
line.long 0x0 "CNT,Timer/Counter n Counter Register"
hexmask.long 0x0 0.--31. 1. "CNT,Timer/Counter n Counter bits."
tree.end
tree "TIMER21"
base ad:0x40002600
group.long 0x0++0xB
line.long 0x0 "CR,Timer/Counter n Control Register"
sif (cpuis("A31G32*"))
bitfld.long 0x0 16. "CNCLR,Timer 2n counter clear after Capture" "0,1"
endif
sif (cpuis("A31G31*"))
bitfld.long 0x0 15. "TnEN,Timer n Operation Enable bit" "0,1"
bitfld.long 0x0 14. "TnCLK,Timer n Clock Selection bit (Note: This bit should be changed during TnEN bit is '0b'.)" "0,1"
bitfld.long 0x0 12.--13. "TnMS,Timer n Operation Mode Selection bits (Note: These bits should be changed during TnEN bit is '0b'.)" "0,1,2,3"
bitfld.long 0x0 11. "TnECE,Timer n External Clock Edge Selection bit" "0,1"
bitfld.long 0x0 8. "TnOPOL,TnOUT Polarity Selection bit" "0,1"
bitfld.long 0x0 6.--7. "TnCPOL,Timer n Capture Polarity Selection bits" "0,1,2,3"
bitfld.long 0x0 5. "TnMIEN,Timer n Match Interrupt Enable bit" "0,1"
bitfld.long 0x0 4. "TnCIEN,Timer n Capture Interrupt Enable bit" "0,1"
bitfld.long 0x0 3. "TnMIFLAG,Timer n Match Interrupt Flag bit" "0,1"
newline
bitfld.long 0x0 2. "TnCIFLAG,Timer n Capture Interrupt Flag bit" "0,1"
bitfld.long 0x0 1. "TnPAU,Timer n Counter Temporary Pause Control bit" "0,1"
bitfld.long 0x0 0. "TnCLR,Timer n Counter and Prescaler Clear bit" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 15. "EN,Timer n Operation Enable bit" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 14. "CLK,Timer n Clock Selection bit (Note: This bit should be changed during TnEN bit is '0b'.)" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 12.--13. "MS,Timer n Operation Mode Selection bits (Note: These bits should be changed during TnEN bit is '0b'.)" "0,1,2,3"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 11. "ECE,Timer n External Clock Edge Selection bit" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 8. "OPOL,TnOUT Polarity Selection bit" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 6.--7. "CPOL,Timer n Capture Polarity Selection bits" "0,1,2,3"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 5. "MIEN,Timer n Match Interrupt Enable bit" "0,1"
newline
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 4. "CIEN,Timer n Capture Interrupt Enable bit" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 3. "MIFLAG,Timer n Match Interrupt Flag bit" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 2. "CIFLAG,Timer n Capture Interrupt Flag bit" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 1. "PAU,Timer n Counter Temporary Pause Control bit" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 0. "CLR,Timer n Counter and Prescaler Clear bit" "0,1"
endif
line.long 0x4 "ADR,Timer/Counter n A Data Register"
hexmask.long 0x4 0.--31. 1. "ADATA,Timer/Counter n A Data bits. The range is 0x00000000 to 0xFFFFFFFF. Note: Do not write '00000000H' in the TnADR register when PPG mode."
line.long 0x8 "BDR,Timer/Counter n B Data Register"
hexmask.long 0x8 0.--31. 1. "BDATA,Timer/Counter n B Data bits. The range is 0x00000000 to 0xFFFFFFFF."
rgroup.long 0xC++0x3
line.long 0x0 "CAPDR,Timer/Counter n Capture Data Register"
hexmask.long 0x0 0.--31. 1. "CAPD,Timer/Counter n Capture Data bits."
group.long 0x10++0x3
line.long 0x0 "PREDR,Timer/Counter n Prescaler Data Register"
hexmask.long.word 0x0 0.--11. 1. "PRED,Timer/Counter n Prescaler Data bits.P"
rgroup.long 0x14++0x3
line.long 0x0 "CNT,Timer/Counter n Counter Register"
hexmask.long 0x0 0.--31. 1. "CNT,Timer/Counter n Counter bits."
tree.end
tree "TIMER30"
base ad:0x40002400
group.long 0x0++0x13
line.long 0x0 "CR,Timer/Counter 30 Control Register"
bitfld.long 0x0 15. "T30EN,Timer 30 Operation Enable bit" "0: Disable timer 30 operation,1: Enable timer 30 operation (Counter clear and.."
bitfld.long 0x0 14. "T30CLK,Timer 30 Clock Selection bit (Note: This bit should be changed during T30EN bit is '0b'.)" "0: Select an internal prescaler clock,1: Select an external clock"
newline
bitfld.long 0x0 12.--13. "T30MS,Timer 30 Operation Mode Selection bits (Note: These bits should be changed during T30EN bit is '0b'.)" "0: Interval mode (All match interrupts can occur),1: Capture mode (The Period-match interrupt can..,2: Back-to-back mode (All interrupts can occur),?"
bitfld.long 0x0 11. "T30ECE,Timer 30 External Clock Edge Selection bit" "0,1"
newline
bitfld.long 0x0 10. "FORCA,Timer 30 Output Mode Selection bit. This bit should be changed when the T30EN is '0b'. Note: If this bit is changed on operation it shall apply from the next period." "0,1"
bitfld.long 0x0 9. "DLYEN,Delay Time Insertion Enable bit" "0,1"
newline
bitfld.long 0x0 8. "DLYPOS,Delay Time Insertion Position" "0,1"
bitfld.long 0x0 6.--7. "T30CPOL,Timer 30 Capture Polarity Selection bits" "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "UPDT,Data Reload Time Selection bits" "0,1,2,3"
bitfld.long 0x0 1.--3. "PMOC,Period Match Interrupt Occurrence Selection (Note: A period match counter is cleared as 0x00 when the T3nCLR bit is set or the PMOC[2:0] bits are changed.)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0. "T30CLR,Timer 30 Counter and Prescaler Clear bit" "0: No effect,1: Clear timer 30 counter and prescaler.."
line.long 0x4 "PDR,Timer/Counter 30 Period Data Register"
hexmask.long.word 0x4 0.--15. 1. "PDATA,Timer/Counter 30 Period Data bits. The range is 0x0002 to 0xFFFF."
line.long 0x8 "ADR,Timer/Counter 30 A Data Register"
hexmask.long.word 0x8 0.--15. 1. "ADATA,Timer/Counter 30 A Data bits. The range is 0x0000 to 0xFFFF."
line.long 0xC "BDR,Timer/Counter 30 B Data Register"
hexmask.long.word 0xC 0.--15. 1. "BDATA,Timer/Counter 30 B Data bits. The range is 0x0000 to 0xFFFF."
line.long 0x10 "CDR,Timer/Counter 30 C Data Register"
hexmask.long.word 0x10 0.--15. 1. "CDATA,Timer/Counter 30 C Data bits. The range is 0x0000 to 0xFFFF."
rgroup.long 0x14++0x3
line.long 0x0 "CAPDR,Timer/Counter 30 Capture Data Register"
hexmask.long.word 0x0 0.--15. 1. "CAPD,Timer/Counter 30 Capture Data bits."
group.long 0x18++0x3
line.long 0x0 "PREDR,Timer/Counter 30 Prescaler Data Register"
hexmask.long.word 0x0 0.--11. 1. "PRED,Timer/Counter 30 Prescaler Data bits."
rgroup.long 0x1C++0x3
line.long 0x0 "CNT,Timer/Counter 30 Counter Register"
hexmask.long.word 0x0 0.--15. 1. "CNT,Timer/Counter 30 Counter bits."
group.long 0x20++0x1B
line.long 0x0 "OUTCR,Timer/Counter 30 Output Control Register"
hexmask.long.word 0x0 16.--31. 1. "WTIDKY,Write Identification Key. On writes write 0xE06C to these bits otherwise the write is ignored."
bitfld.long 0x0 15. "POLB,PWM30xB Output Polarity Selection bit" "0,1"
newline
bitfld.long 0x0 14. "POLA,PWM30xA Output Polarity Selection bit" "0,1"
bitfld.long 0x0 13. "PABOE,PWM30AB Output Enable bit" "0,1"
newline
bitfld.long 0x0 12. "PBBOE,PWM30BB Output Enable bit" "0,1"
bitfld.long 0x0 11. "PCBOE,PWM30CB Output Enable bit" "0,1"
newline
bitfld.long 0x0 10. "PAAOE,PWM30AA Output Enable bit" "0,1"
bitfld.long 0x0 9. "PBAOE,PWM30BA Output Enable bit" "0,1"
newline
bitfld.long 0x0 8. "PCAOE,PWM30CA Output Enable bit" "0,1"
bitfld.long 0x0 6. "LVLAB,Configure PWM30AB output When Disable" "0,1"
newline
bitfld.long 0x0 5. "LVLBB,Configure PWM30BB output When Disable" "0,1"
bitfld.long 0x0 4. "LVLCB,Configure PWM30CB output When Disable" "0,1"
newline
bitfld.long 0x0 2. "LVLAA,Configure PWM30AA output When Disable" "0,1"
bitfld.long 0x0 1. "LVLBA,Configure PWM30BA output When Disable" "0,1"
newline
bitfld.long 0x0 0. "LVLCA,Configure PWM30CA output When Disable" "0,1"
line.long 0x4 "DLY,Timer/Counter 30 PWM Output Delay Data Register"
hexmask.long.word 0x4 0.--9. 1. "DLY,Timer/Counter 30 PWM Delay Data bits. Delay time: DLY[9:0]/fT30"
line.long 0x8 "INTCR,Timer/Counter 30 Interrupt Control Register"
bitfld.long 0x8 6. "HIZIEN,Timer 30 Output High-Impedance Interrupt Enable bit" "0,1"
bitfld.long 0x8 5. "T30CIEN,Timer 30 Capture Interrupt Enable bit" "0,1"
newline
bitfld.long 0x8 4. "T30BTIEN,Timer 30 Bottom Interrupt Enable bit" "0,1"
bitfld.long 0x8 3. "T30PMIEN,Timer 30 Period Match Interrupt Enable bit" "0,1"
newline
bitfld.long 0x8 2. "T30AMIEN,Timer 30 A-ch Match Interrupt Enable bit" "0,1"
bitfld.long 0x8 1. "T30BMIEN,Timer 30 B-ch Match Interrupt Enable bit" "0,1"
newline
bitfld.long 0x8 0. "T30CMIEN,Timer 30 C-ch Match Interrupt Enable bit" "0,1"
line.long 0xC "INTFLAG,Timer/Counter 30 Interrupt Flag Register"
bitfld.long 0xC 6. "HIZIFLAG,Timer 30 Output High-Impedance Interrupt Flag bit" "0,1"
bitfld.long 0xC 5. "T30CIFLAG,Timer 30 Capture Interrupt Flag bit" "0,1"
newline
bitfld.long 0xC 4. "T30BTIFLAG,Timer 30 Bottom Interrupt Flag bit" "0,1"
bitfld.long 0xC 3. "T30PMIFLAG,Timer 30 Period Match Interrupt Flag bit" "0,1"
newline
bitfld.long 0xC 2. "T30AMIFLAG,Timer 30 A-ch Match Interrupt Flag bit" "0,1"
bitfld.long 0xC 1. "T30BMIFLAG,Timer 30 B-ch Match Interrupt Flag bit" "0,1"
newline
bitfld.long 0xC 0. "T30CMIFLAG,Timer 30 C-ch Match Interrupt Flag bit" "0,1"
line.long 0x10 "HIZCR,Timer/Counter 30 High-Impedance Control Register"
sif (cpuis("A31G32*"))
bitfld.long 0x10 8. "HIZCSSEL,High-Impedance output control signal selection" "0,1"
endif
bitfld.long 0x10 7. "HIZEN,PWM30xA/PWM30xB Output High-Impedance Enable bit" "0,1"
newline
bitfld.long 0x10 4. "HIZSW,High-Impedance Output Software Setting" "0,1"
bitfld.long 0x10 2. "HEDGE,High-Impedance Edge Selection" "0,1"
newline
rbitfld.long 0x10 1. "HIZSTA,High-Impedance Status" "0,1"
bitfld.long 0x10 0. "HIZCLR,High-Impedance Output Clear bit" "0,1"
line.long 0x14 "ADTCR,Timer/Counter 30 A/DC Trigger Control Register"
bitfld.long 0x14 4. "T30BTTG,Select Timer 30 Bottom for A/DC Trigger Signal Generator" "0,1"
bitfld.long 0x14 3. "T30PMTG,Select Timer 30 Period Match for A/DC Trigger Signal Generator" "0,1"
newline
bitfld.long 0x14 2. "T30AMTG,Select Timer 30 A-ch Match for A/DC Trigger Signal Generator" "0,1"
bitfld.long 0x14 1. "T30BMTG,Select Timer 30 B-ch Match for A/DC Trigger Signal Generator" "0,1"
newline
bitfld.long 0x14 0. "T30CMTG,Select Timer 30 C-ch Match for A/DC Trigger Signal Generator" "0,1"
line.long 0x18 "ADTDR,Timer/Counter 30 A/DC Trigger Generator Data Register"
hexmask.long.word 0x18 0.--13. 1. "ADTDATA,Timer/Counter 30 A/DC Trigger Generation Data bits."
tree.end
sif (cpuis("A31G32*"))
tree "TIMER40"
base ad:0x40002800
group.long 0x0++0xB
line.long 0x0 "CR,Timer/Counter 40 Control Register"
bitfld.long 0x0 15. "T40EN,Timer 40 Operation Enable bit" "0: Disable timer 40 operation,1: Enable timer 40 operation (Counter clear and.."
bitfld.long 0x0 14. "T40CLK,Timer 40 Clock Selection bit (Note: This bit should be changed during T40EN bit is '0b'.)" "0: Select an internal prescaler clock,1: Select an external clock"
newline
bitfld.long 0x0 12.--13. "T40MS,Timer 40 Operation Mode Selection bits (Note: These bits should be changed during T40EN bit is '0b'.)" "0: Interval mode (All match interrupts can occur),1: Capture mode (The Period-match interrupt can..,2: Back-to-back mode (All interrupts can occur),?"
bitfld.long 0x0 11. "T40ECE,Timer 40 External Clock Edge Selection bit" "0,1"
newline
bitfld.long 0x0 9.--10. "T40CAPCHSEL,Timer 40 Capture Channel Selection bits." "0,1,2,3"
bitfld.long 0x0 8. "T40OPOL,T40O Polarity Selection bit." "0,1"
newline
bitfld.long 0x0 6.--7. "T40CPOL,Timer 40 Capture Polarity Selection bits." "0,1,2,3"
bitfld.long 0x0 5. "T40MIEN,Timer 40 Match Interrupt Enable bit." "0,1"
newline
bitfld.long 0x0 4. "T40CIEN,Timer 20 Capture Interrupt Enable bit." "0,1"
bitfld.long 0x0 3. "T40MIFLAG,Timer 40 Match Interrupt Flag bit." "0,1"
newline
bitfld.long 0x0 2. "T40CIFLAG,Timer 40 Capture Interrupt Flag bit." "0,1"
bitfld.long 0x0 1. "T40PAU,Timer 40 Counter Temporary Pause Control bit." "0,1"
newline
bitfld.long 0x0 0. "T40CLR,Timer 40 Counter and Prescaler Clear bit" "0: No effect,1: Clear timer 40 counter and prescaler.."
line.long 0x4 "ADR,Timer/Counter 40 A Data Register"
hexmask.long.word 0x4 0.--15. 1. "ADATA,Timer/Counter 20 A Data bits. The range is 0x0002 to 0xFFFFFFFF."
line.long 0x8 "BDR,Timer/Counter 40 B Data Register"
hexmask.long.word 0x8 0.--15. 1. "BDATA,Timer/Counter 40 B Data bits. The range is 0x0000 to 0xFFFFFFFF."
rgroup.long 0xC++0x3
line.long 0x0 "CAPDR,Timer/Counter 40 Capture Data Register"
hexmask.long.word 0x0 0.--15. 1. "CAPD,Timer/Counter 40 Capture Data bits."
group.long 0x10++0x7
line.long 0x0 "PREDR,Timer/Counter 40 Prescaler Data Register"
hexmask.long.word 0x0 0.--11. 1. "PRED,Timer/Counter 40 Prescaler Data bits."
line.long 0x4 "PREDR2,Timer/Counter 40 Prescaler Data Register 2"
hexmask.long.word 0x4 0.--11. 1. "PRED,Timer/Counter 40 Prescaler Data bits."
rgroup.long 0x18++0x3
line.long 0x0 "CNT,Timer/Counter 40 Counter Register"
hexmask.long 0x0 0.--31. 1. "CNT,Timer/Counter 40 Counter bits."
tree.end
endif
tree.end
tree "USART (Universal Synchronous/Asynchronous Receiver/Transmitter)"
base ad:0x0
tree "USART10"
base ad:0x40003800
group.long 0x0++0x7
line.long 0x0 "CR1,USARTn Control Register 1"
bitfld.long 0x0 14.--15. "USTnMS,USARTn Operation Mode Selection bits" "0: Asynchronous Mode (UART),1: Synchronous Mode,?,3: SPI mode"
bitfld.long 0x0 12.--13. "USTnP,Selects Parity Generation and Check method (only UART mode)" "0: No parity,?,2: Even parity,3: Odd parity"
bitfld.long 0x0 9.--11. "USTnS,Selects the length of data bit in a frame when Asynchronous or Synchronous mode" "0: 5 bit,1: 6 bit,2: 7 bit,3: 8 bit,?,?,?,7: 9 bit"
bitfld.long 0x0 8. "ORDn,Selects the first data bit to be transmitted (only SPI mode)" "0: LSB-first,1: MSB-first"
newline
bitfld.long 0x0 7. "CPOLn,Selects the clock polarity of ACK in synchronous or SPI mode" "0: TXD Change @Rising Edge RXD Change @Falling Edge,1: TXD Change @Falling Edge RXD Change @Rising Edge"
bitfld.long 0x0 6. "CPHAn,(null)The CPOLn and this bit determine if data are sampled on the leading or trailing edge of SCK (only SPI mode)" "0: Sample / Setup,1: Setup / Sample"
bitfld.long 0x0 5. "DRIEn,Transmit Data Register Empty Interrupt Enable bit" "0,1"
bitfld.long 0x0 4. "TXCIEn,Transmit Complete Interrupt Enable bit" "0,1"
newline
bitfld.long 0x0 3. "RXCIEn,Receive Complete Interrupt Enable bit" "0,1"
bitfld.long 0x0 2. "WAKEIEn,Asynchronous Wake-up Interrupt Enable bit in Deep Sleep Mode. When device is in deep sleep mode if RXD goes to low level an interrupt can be requested to wake-up system (only UART mode)" "0,1"
bitfld.long 0x0 1. "TXEn,Enables the Transmitter unit" "0,1"
bitfld.long 0x0 0. "RXEn,Enables the Receiver unit" "0,1"
line.long 0x4 "CR2,USARTn Control Register 2"
sif (cpuis("A31G32*"))
bitfld.long 0x4 14. "DMATXIE,DMA TX Interrupt bit" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x4 13. "DMARXIE,DMA RX Interrupt bit" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x4 12. "RTOIE,RTO Interrupt bit" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x4 11. "RTOEN,Activate RTO Block by supplying" "0,1"
newline
endif
sif (cpuis("A31G32*"))
bitfld.long 0x4 10. "FPCREN,Activate Floating Point Counter Register" "0,1"
endif
bitfld.long 0x4 9. "USTnEN,(nActivate USARTn Block by supplyingull)" "0,1"
bitfld.long 0x4 8. "DBLSn,Selects receiver sampling rate (only UART mode)" "0,1"
bitfld.long 0x4 7. "MASTERn,Selects master or slave in SPI or Synchronous mode and controls the direction of SCK pin" "0,1"
newline
bitfld.long 0x4 6. "LOOPSn,Control the Loop Back mode of USARTn for test mode" "0,1"
bitfld.long 0x4 5. "DISSCKn,In synchronous mode operation selects the waveform of SCK output" "0,1"
bitfld.long 0x4 4. "USTnSSEN,This bit controls the SS pin operation (only SPI mode)" "0,1"
bitfld.long 0x4 3. "FXCHn,SPI port function exchange control bit (only SPI mode)" "0,1"
newline
bitfld.long 0x4 2. "USTnSB,Selects the length of stop bit in Asynchronous or Synchronous mode" "0,1"
bitfld.long 0x4 1. "USTnTX8,The ninth bit of data frame in Asynchronous or Synchronous mode of operation. Write this bit first before loading the USTnDR register" "0,1"
bitfld.long 0x4 0. "USTnRX8,The ninth bit of data frame in Asynchronous or Synchronous mode of operation. Read this bit first before reading the receive buffer (only UART mode)" "0,1"
group.long 0xC++0xB
line.long 0x0 "ST,USARTn Status Register"
sif (cpuis("A31G32*"))
bitfld.long 0x0 9. "DMATXF,DMA Transmit Operation Complete flag. (DMA to USART)" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 8. "DMARXF,DMA Receive Operation Complete flag. (USART to DMA)" "0,1"
endif
bitfld.long 0x0 7. "DREn,Transmit Data Register Empty Interrupt Flag" "0,1"
bitfld.long 0x0 6. "TXCn,Transmit Complete Interrupt Flag" "0,1"
newline
rbitfld.long 0x0 5. "RXCn,Receive Complete Interrupt Flag" "0,1"
bitfld.long 0x0 4. "WAKEn,Asynchronous Wake-up Interrupt Flag" "0,1"
sif (cpuis("A31G32*"))
bitfld.long 0x0 3. "RTOF,Receive Time Out Interrupt flag. This bit is cleared to '0' when write '1'." "0,1"
endif
rbitfld.long 0x0 2. "DORn,This bit is set if data OverRun occurs" "0,1"
newline
bitfld.long 0x0 1. "FEn,This bit is set if the first stop bit of next character in the receive buffer is detected as '0'. This bit is valid until the receive buffer is read (only UART mode)" "0,1"
bitfld.long 0x0 0. "PEn,This bit is set if the next character in the receive buffer has a Parity Error while parity is checked. This bit is valid until the receive buffer is read (only UART mode)" "0,1"
line.long 0x4 "BDR,USARTn Baud Rate Generation Register"
hexmask.long.word 0x4 0.--11. 1. "BDATA,The value in this register is used to generate internal baud rate in UART mode or to generate SCK clock in SPI mode. To prevent malfunction do not write '0' in UART mode and do not write '0' or '1' in synchronous or SPI mode."
line.long 0x8 "DR,USARTn Data Register"
hexmask.long.byte 0x8 0.--7. 1. "DATA,The USART Transmit buffer and Receive buffer share the same I/O address with this DATA register. The Transmit Data Buffer is the destination for data written to the USTnDR register. Reading the USTnDR register returns the contents of the Receive.."
sif (cpuis("A31G32*"))
group.long 0x18++0x7
line.long 0x0 "FPCR,USART1n Floating Point Count Register"
hexmask.long.byte 0x0 0.--7. 1. "FPCR,USART Floating Point Counter"
line.long 0x4 "RTO,USART1n RTO Register"
hexmask.long.tbyte 0x4 0.--23. 1. "RTO,USART receive time out register"
endif
tree.end
tree "USART11"
base ad:0x40003900
group.long 0x0++0x7
line.long 0x0 "CR1,USARTn Control Register 1"
bitfld.long 0x0 14.--15. "USTnMS,USARTn Operation Mode Selection bits" "0: Asynchronous Mode (UART),1: Synchronous Mode,?,3: SPI mode"
bitfld.long 0x0 12.--13. "USTnP,Selects Parity Generation and Check method (only UART mode)" "0: No parity,?,2: Even parity,3: Odd parity"
bitfld.long 0x0 9.--11. "USTnS,Selects the length of data bit in a frame when Asynchronous or Synchronous mode" "0: 5 bit,1: 6 bit,2: 7 bit,3: 8 bit,?,?,?,7: 9 bit"
bitfld.long 0x0 8. "ORDn,Selects the first data bit to be transmitted (only SPI mode)" "0: LSB-first,1: MSB-first"
newline
bitfld.long 0x0 7. "CPOLn,Selects the clock polarity of ACK in synchronous or SPI mode" "0: TXD Change @Rising Edge RXD Change @Falling Edge,1: TXD Change @Falling Edge RXD Change @Rising Edge"
bitfld.long 0x0 6. "CPHAn,(null)The CPOLn and this bit determine if data are sampled on the leading or trailing edge of SCK (only SPI mode)" "0: Sample / Setup,1: Setup / Sample"
bitfld.long 0x0 5. "DRIEn,Transmit Data Register Empty Interrupt Enable bit" "0,1"
bitfld.long 0x0 4. "TXCIEn,Transmit Complete Interrupt Enable bit" "0,1"
newline
bitfld.long 0x0 3. "RXCIEn,Receive Complete Interrupt Enable bit" "0,1"
bitfld.long 0x0 2. "WAKEIEn,Asynchronous Wake-up Interrupt Enable bit in Deep Sleep Mode. When device is in deep sleep mode if RXD goes to low level an interrupt can be requested to wake-up system (only UART mode)" "0,1"
bitfld.long 0x0 1. "TXEn,Enables the Transmitter unit" "0,1"
bitfld.long 0x0 0. "RXEn,Enables the Receiver unit" "0,1"
line.long 0x4 "CR2,USARTn Control Register 2"
sif (cpuis("A31G32*"))
bitfld.long 0x4 14. "DMATXIE,DMA TX Interrupt bit" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x4 13. "DMARXIE,DMA RX Interrupt bit" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x4 12. "RTOIE,RTO Interrupt bit" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x4 11. "RTOEN,Activate RTO Block by supplying" "0,1"
newline
endif
sif (cpuis("A31G32*"))
bitfld.long 0x4 10. "FPCREN,Activate Floating Point Counter Register" "0,1"
endif
bitfld.long 0x4 9. "USTnEN,(nActivate USARTn Block by supplyingull)" "0,1"
bitfld.long 0x4 8. "DBLSn,Selects receiver sampling rate (only UART mode)" "0,1"
bitfld.long 0x4 7. "MASTERn,Selects master or slave in SPI or Synchronous mode and controls the direction of SCK pin" "0,1"
newline
bitfld.long 0x4 6. "LOOPSn,Control the Loop Back mode of USARTn for test mode" "0,1"
bitfld.long 0x4 5. "DISSCKn,In synchronous mode operation selects the waveform of SCK output" "0,1"
bitfld.long 0x4 4. "USTnSSEN,This bit controls the SS pin operation (only SPI mode)" "0,1"
bitfld.long 0x4 3. "FXCHn,SPI port function exchange control bit (only SPI mode)" "0,1"
newline
bitfld.long 0x4 2. "USTnSB,Selects the length of stop bit in Asynchronous or Synchronous mode" "0,1"
bitfld.long 0x4 1. "USTnTX8,The ninth bit of data frame in Asynchronous or Synchronous mode of operation. Write this bit first before loading the USTnDR register" "0,1"
bitfld.long 0x4 0. "USTnRX8,The ninth bit of data frame in Asynchronous or Synchronous mode of operation. Read this bit first before reading the receive buffer (only UART mode)" "0,1"
group.long 0xC++0xB
line.long 0x0 "ST,USARTn Status Register"
sif (cpuis("A31G32*"))
bitfld.long 0x0 9. "DMATXF,DMA Transmit Operation Complete flag. (DMA to USART)" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 8. "DMARXF,DMA Receive Operation Complete flag. (USART to DMA)" "0,1"
endif
bitfld.long 0x0 7. "DREn,Transmit Data Register Empty Interrupt Flag" "0,1"
bitfld.long 0x0 6. "TXCn,Transmit Complete Interrupt Flag" "0,1"
newline
rbitfld.long 0x0 5. "RXCn,Receive Complete Interrupt Flag" "0,1"
bitfld.long 0x0 4. "WAKEn,Asynchronous Wake-up Interrupt Flag" "0,1"
sif (cpuis("A31G32*"))
bitfld.long 0x0 3. "RTOF,Receive Time Out Interrupt flag. This bit is cleared to '0' when write '1'." "0,1"
endif
rbitfld.long 0x0 2. "DORn,This bit is set if data OverRun occurs" "0,1"
newline
bitfld.long 0x0 1. "FEn,This bit is set if the first stop bit of next character in the receive buffer is detected as '0'. This bit is valid until the receive buffer is read (only UART mode)" "0,1"
bitfld.long 0x0 0. "PEn,This bit is set if the next character in the receive buffer has a Parity Error while parity is checked. This bit is valid until the receive buffer is read (only UART mode)" "0,1"
line.long 0x4 "BDR,USARTn Baud Rate Generation Register"
hexmask.long.word 0x4 0.--11. 1. "BDATA,The value in this register is used to generate internal baud rate in UART mode or to generate SCK clock in SPI mode. To prevent malfunction do not write '0' in UART mode and do not write '0' or '1' in synchronous or SPI mode."
line.long 0x8 "DR,USARTn Data Register"
hexmask.long.byte 0x8 0.--7. 1. "DATA,The USART Transmit buffer and Receive buffer share the same I/O address with this DATA register. The Transmit Data Buffer is the destination for data written to the USTnDR register. Reading the USTnDR register returns the contents of the Receive.."
sif (cpuis("A31G32*"))
group.long 0x18++0x7
line.long 0x0 "FPCR,USART1n Floating Point Count Register"
hexmask.long.byte 0x0 0.--7. 1. "FPCR,USART Floating Point Counter"
line.long 0x4 "RTO,USART1n RTO Register"
hexmask.long.tbyte 0x4 0.--23. 1. "RTO,USART receive time out register"
endif
tree.end
tree "USART12"
base ad:0x40003A00
group.long 0x0++0x7
line.long 0x0 "CR1,USARTn Control Register 1"
bitfld.long 0x0 14.--15. "USTnMS,USARTn Operation Mode Selection bits" "0: Asynchronous Mode (UART),1: Synchronous Mode,?,3: SPI mode"
bitfld.long 0x0 12.--13. "USTnP,Selects Parity Generation and Check method (only UART mode)" "0: No parity,?,2: Even parity,3: Odd parity"
bitfld.long 0x0 9.--11. "USTnS,Selects the length of data bit in a frame when Asynchronous or Synchronous mode" "0: 5 bit,1: 6 bit,2: 7 bit,3: 8 bit,?,?,?,7: 9 bit"
bitfld.long 0x0 8. "ORDn,Selects the first data bit to be transmitted (only SPI mode)" "0: LSB-first,1: MSB-first"
newline
bitfld.long 0x0 7. "CPOLn,Selects the clock polarity of ACK in synchronous or SPI mode" "0: TXD Change @Rising Edge RXD Change @Falling Edge,1: TXD Change @Falling Edge RXD Change @Rising Edge"
bitfld.long 0x0 6. "CPHAn,(null)The CPOLn and this bit determine if data are sampled on the leading or trailing edge of SCK (only SPI mode)" "0: Sample / Setup,1: Setup / Sample"
bitfld.long 0x0 5. "DRIEn,Transmit Data Register Empty Interrupt Enable bit" "0,1"
bitfld.long 0x0 4. "TXCIEn,Transmit Complete Interrupt Enable bit" "0,1"
newline
bitfld.long 0x0 3. "RXCIEn,Receive Complete Interrupt Enable bit" "0,1"
bitfld.long 0x0 2. "WAKEIEn,Asynchronous Wake-up Interrupt Enable bit in Deep Sleep Mode. When device is in deep sleep mode if RXD goes to low level an interrupt can be requested to wake-up system (only UART mode)" "0,1"
bitfld.long 0x0 1. "TXEn,Enables the Transmitter unit" "0,1"
bitfld.long 0x0 0. "RXEn,Enables the Receiver unit" "0,1"
line.long 0x4 "CR2,USARTn Control Register 2"
sif (cpuis("A31G32*"))
bitfld.long 0x4 14. "DMATXIE,DMA TX Interrupt bit" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x4 13. "DMARXIE,DMA RX Interrupt bit" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x4 12. "RTOIE,RTO Interrupt bit" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x4 11. "RTOEN,Activate RTO Block by supplying" "0,1"
newline
endif
sif (cpuis("A31G32*"))
bitfld.long 0x4 10. "FPCREN,Activate Floating Point Counter Register" "0,1"
endif
bitfld.long 0x4 9. "USTnEN,(nActivate USARTn Block by supplyingull)" "0,1"
bitfld.long 0x4 8. "DBLSn,Selects receiver sampling rate (only UART mode)" "0,1"
bitfld.long 0x4 7. "MASTERn,Selects master or slave in SPI or Synchronous mode and controls the direction of SCK pin" "0,1"
newline
bitfld.long 0x4 6. "LOOPSn,Control the Loop Back mode of USARTn for test mode" "0,1"
bitfld.long 0x4 5. "DISSCKn,In synchronous mode operation selects the waveform of SCK output" "0,1"
bitfld.long 0x4 4. "USTnSSEN,This bit controls the SS pin operation (only SPI mode)" "0,1"
bitfld.long 0x4 3. "FXCHn,SPI port function exchange control bit (only SPI mode)" "0,1"
newline
bitfld.long 0x4 2. "USTnSB,Selects the length of stop bit in Asynchronous or Synchronous mode" "0,1"
bitfld.long 0x4 1. "USTnTX8,The ninth bit of data frame in Asynchronous or Synchronous mode of operation. Write this bit first before loading the USTnDR register" "0,1"
bitfld.long 0x4 0. "USTnRX8,The ninth bit of data frame in Asynchronous or Synchronous mode of operation. Read this bit first before reading the receive buffer (only UART mode)" "0,1"
group.long 0xC++0xB
line.long 0x0 "ST,USARTn Status Register"
sif (cpuis("A31G32*"))
bitfld.long 0x0 9. "DMATXF,DMA Transmit Operation Complete flag. (DMA to USART)" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 8. "DMARXF,DMA Receive Operation Complete flag. (USART to DMA)" "0,1"
endif
bitfld.long 0x0 7. "DREn,Transmit Data Register Empty Interrupt Flag" "0,1"
bitfld.long 0x0 6. "TXCn,Transmit Complete Interrupt Flag" "0,1"
newline
rbitfld.long 0x0 5. "RXCn,Receive Complete Interrupt Flag" "0,1"
bitfld.long 0x0 4. "WAKEn,Asynchronous Wake-up Interrupt Flag" "0,1"
sif (cpuis("A31G32*"))
bitfld.long 0x0 3. "RTOF,Receive Time Out Interrupt flag. This bit is cleared to '0' when write '1'." "0,1"
endif
rbitfld.long 0x0 2. "DORn,This bit is set if data OverRun occurs" "0,1"
newline
bitfld.long 0x0 1. "FEn,This bit is set if the first stop bit of next character in the receive buffer is detected as '0'. This bit is valid until the receive buffer is read (only UART mode)" "0,1"
bitfld.long 0x0 0. "PEn,This bit is set if the next character in the receive buffer has a Parity Error while parity is checked. This bit is valid until the receive buffer is read (only UART mode)" "0,1"
line.long 0x4 "BDR,USARTn Baud Rate Generation Register"
hexmask.long.word 0x4 0.--11. 1. "BDATA,The value in this register is used to generate internal baud rate in UART mode or to generate SCK clock in SPI mode. To prevent malfunction do not write '0' in UART mode and do not write '0' or '1' in synchronous or SPI mode."
line.long 0x8 "DR,USARTn Data Register"
hexmask.long.byte 0x8 0.--7. 1. "DATA,The USART Transmit buffer and Receive buffer share the same I/O address with this DATA register. The Transmit Data Buffer is the destination for data written to the USTnDR register. Reading the USTnDR register returns the contents of the Receive.."
sif (cpuis("A31G32*"))
group.long 0x18++0x7
line.long 0x0 "FPCR,USART1n Floating Point Count Register"
hexmask.long.byte 0x0 0.--7. 1. "FPCR,USART Floating Point Counter"
line.long 0x4 "RTO,USART1n RTO Register"
hexmask.long.tbyte 0x4 0.--23. 1. "RTO,USART receive time out register"
endif
tree.end
tree "USART13"
base ad:0x40003B00
group.long 0x0++0x7
line.long 0x0 "CR1,USARTn Control Register 1"
bitfld.long 0x0 14.--15. "USTnMS,USARTn Operation Mode Selection bits" "0: Asynchronous Mode (UART),1: Synchronous Mode,?,3: SPI mode"
bitfld.long 0x0 12.--13. "USTnP,Selects Parity Generation and Check method (only UART mode)" "0: No parity,?,2: Even parity,3: Odd parity"
bitfld.long 0x0 9.--11. "USTnS,Selects the length of data bit in a frame when Asynchronous or Synchronous mode" "0: 5 bit,1: 6 bit,2: 7 bit,3: 8 bit,?,?,?,7: 9 bit"
bitfld.long 0x0 8. "ORDn,Selects the first data bit to be transmitted (only SPI mode)" "0: LSB-first,1: MSB-first"
newline
bitfld.long 0x0 7. "CPOLn,Selects the clock polarity of ACK in synchronous or SPI mode" "0: TXD Change @Rising Edge RXD Change @Falling Edge,1: TXD Change @Falling Edge RXD Change @Rising Edge"
bitfld.long 0x0 6. "CPHAn,(null)The CPOLn and this bit determine if data are sampled on the leading or trailing edge of SCK (only SPI mode)" "0: Sample / Setup,1: Setup / Sample"
bitfld.long 0x0 5. "DRIEn,Transmit Data Register Empty Interrupt Enable bit" "0,1"
bitfld.long 0x0 4. "TXCIEn,Transmit Complete Interrupt Enable bit" "0,1"
newline
bitfld.long 0x0 3. "RXCIEn,Receive Complete Interrupt Enable bit" "0,1"
bitfld.long 0x0 2. "WAKEIEn,Asynchronous Wake-up Interrupt Enable bit in Deep Sleep Mode. When device is in deep sleep mode if RXD goes to low level an interrupt can be requested to wake-up system (only UART mode)" "0,1"
bitfld.long 0x0 1. "TXEn,Enables the Transmitter unit" "0,1"
bitfld.long 0x0 0. "RXEn,Enables the Receiver unit" "0,1"
line.long 0x4 "CR2,USARTn Control Register 2"
sif (cpuis("A31G32*"))
bitfld.long 0x4 14. "DMATXIE,DMA TX Interrupt bit" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x4 13. "DMARXIE,DMA RX Interrupt bit" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x4 12. "RTOIE,RTO Interrupt bit" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x4 11. "RTOEN,Activate RTO Block by supplying" "0,1"
newline
endif
sif (cpuis("A31G32*"))
bitfld.long 0x4 10. "FPCREN,Activate Floating Point Counter Register" "0,1"
endif
bitfld.long 0x4 9. "USTnEN,(nActivate USARTn Block by supplyingull)" "0,1"
bitfld.long 0x4 8. "DBLSn,Selects receiver sampling rate (only UART mode)" "0,1"
bitfld.long 0x4 7. "MASTERn,Selects master or slave in SPI or Synchronous mode and controls the direction of SCK pin" "0,1"
newline
bitfld.long 0x4 6. "LOOPSn,Control the Loop Back mode of USARTn for test mode" "0,1"
bitfld.long 0x4 5. "DISSCKn,In synchronous mode operation selects the waveform of SCK output" "0,1"
bitfld.long 0x4 4. "USTnSSEN,This bit controls the SS pin operation (only SPI mode)" "0,1"
bitfld.long 0x4 3. "FXCHn,SPI port function exchange control bit (only SPI mode)" "0,1"
newline
bitfld.long 0x4 2. "USTnSB,Selects the length of stop bit in Asynchronous or Synchronous mode" "0,1"
bitfld.long 0x4 1. "USTnTX8,The ninth bit of data frame in Asynchronous or Synchronous mode of operation. Write this bit first before loading the USTnDR register" "0,1"
bitfld.long 0x4 0. "USTnRX8,The ninth bit of data frame in Asynchronous or Synchronous mode of operation. Read this bit first before reading the receive buffer (only UART mode)" "0,1"
group.long 0xC++0xB
line.long 0x0 "ST,USARTn Status Register"
sif (cpuis("A31G32*"))
bitfld.long 0x0 9. "DMATXF,DMA Transmit Operation Complete flag. (DMA to USART)" "0,1"
endif
sif (cpuis("A31G32*"))
bitfld.long 0x0 8. "DMARXF,DMA Receive Operation Complete flag. (USART to DMA)" "0,1"
endif
bitfld.long 0x0 7. "DREn,Transmit Data Register Empty Interrupt Flag" "0,1"
bitfld.long 0x0 6. "TXCn,Transmit Complete Interrupt Flag" "0,1"
newline
rbitfld.long 0x0 5. "RXCn,Receive Complete Interrupt Flag" "0,1"
bitfld.long 0x0 4. "WAKEn,Asynchronous Wake-up Interrupt Flag" "0,1"
sif (cpuis("A31G32*"))
bitfld.long 0x0 3. "RTOF,Receive Time Out Interrupt flag. This bit is cleared to '0' when write '1'." "0,1"
endif
rbitfld.long 0x0 2. "DORn,This bit is set if data OverRun occurs" "0,1"
newline
bitfld.long 0x0 1. "FEn,This bit is set if the first stop bit of next character in the receive buffer is detected as '0'. This bit is valid until the receive buffer is read (only UART mode)" "0,1"
bitfld.long 0x0 0. "PEn,This bit is set if the next character in the receive buffer has a Parity Error while parity is checked. This bit is valid until the receive buffer is read (only UART mode)" "0,1"
line.long 0x4 "BDR,USARTn Baud Rate Generation Register"
hexmask.long.word 0x4 0.--11. 1. "BDATA,The value in this register is used to generate internal baud rate in UART mode or to generate SCK clock in SPI mode. To prevent malfunction do not write '0' in UART mode and do not write '0' or '1' in synchronous or SPI mode."
line.long 0x8 "DR,USARTn Data Register"
hexmask.long.byte 0x8 0.--7. 1. "DATA,The USART Transmit buffer and Receive buffer share the same I/O address with this DATA register. The Transmit Data Buffer is the destination for data written to the USTnDR register. Reading the USTnDR register returns the contents of the Receive.."
sif (cpuis("A31G32*"))
group.long 0x18++0x7
line.long 0x0 "FPCR,USART1n Floating Point Count Register"
hexmask.long.byte 0x0 0.--7. 1. "FPCR,USART Floating Point Counter"
line.long 0x4 "RTO,USART1n RTO Register"
hexmask.long.tbyte 0x4 0.--23. 1. "RTO,USART receive time out register"
endif
tree.end
tree.end
tree "USB (Universal Serial Bus)"
base ad:0x50000000
rgroup.long 0x0++0x3
line.long 0x0 "GOTGCTL,Interrupt Source Mask Register"
hexmask.long.byte 0x0 22.--26. 1. "MultValIdBC,Multi Valued ID pin (MultValIdBC)"
group.long 0x4++0x17
line.long 0x0 "GOTGINT,Interrupt Register"
bitfld.long 0x0 20. "MultValIpChng,This bit when set indicates that there is a change in the value of at least one ACA pin value." "0,1"
line.long 0x4 "GAHBCFG,AHB Configuration Register"
bitfld.long 0x4 24. "InvDescEndianes,Invert Descriptor Endianess (InvDescEndianess)" "0,1"
newline
bitfld.long 0x4 23. "AHBSingle,AHB Single Support (AHBSingle)" "0,1"
newline
bitfld.long 0x4 22. "NotiAllDmaWrit,Notify All Dma Write Transactions (NotiAllDmaWrit)" "0,1"
newline
bitfld.long 0x4 21. "RemMemSupp,Remote Memory Support (RemMemSupp)" "0,1"
newline
bitfld.long 0x4 5. "DMAEn,DMA Enable (DMAEn)" "0,1"
newline
hexmask.long.byte 0x4 1.--4. 1. "HbstLen,Burst Length/Type (HbstLen)"
newline
bitfld.long 0x4 0. "GlblIntrMsk,Global Interrupt Mask (GlblIntrMsk)" "0,1"
line.long 0x8 "GUSBCFG,USB Configuration Register"
bitfld.long 0x8 31. "CorruptTxPkt,Corrupt Tx packet (CorruptTxPkt)" "0,1"
newline
bitfld.long 0x8 6. "PHYSel,USB 1.1 Full-Speed Serial Transceiver Select (PHYSel)" "0,1"
newline
bitfld.long 0x8 5. "FSIntf,Full-Speed Serial Interface Select (FSIntf)" "0,1"
newline
bitfld.long 0x8 0.--2. "ToutCal,FS Timeout Calibration (ToutCal)" "0,1,2,3,4,5,6,7"
line.long 0xC "GRSTCTL,Reset Register"
bitfld.long 0xC 31. "AHBIdle,AHB Master Idle (AHBIdle)" "0,1"
newline
bitfld.long 0xC 30. "DMAReq,DMA Request Signal (DMAReq)" "0,1"
newline
hexmask.long.byte 0xC 6.--10. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0xC 5. "TxFFlsh,TxFIFO Flush (TxFFlsh)" "0,1"
newline
bitfld.long 0xC 4. "RxFFlsh,RxFIFO Flush (RxFFlsh)" "0,1"
newline
bitfld.long 0xC 1. "PIUFSSftRst,PIU FS Dedicated Controller Soft Reset (PIUFSSftRst)" "0,1"
newline
bitfld.long 0xC 0. "CSftRst,Core Soft Reset (CSftRst)" "0,1"
line.long 0x10 "GINTSTS,Interrupt Register"
bitfld.long 0x10 31. "WkUpInt,Resume/Remote Wakeup Detected Interrupt (WkUpInt)" "0,1"
newline
bitfld.long 0x10 27. "LPM_Int,LPM Transaction Received Interrupt (LPM_Int). This interrupt is asserted when the device receives an LPM transaction and responds with a non-ERRORed response. Has completed LPM transactions for the programmed number of times (GLPMCFG.RetryCnt)." "0,1"
newline
bitfld.long 0x10 23. "ResetDet,Reset detected Interrupt (ResetDet)" "0,1"
newline
bitfld.long 0x10 22. "FetSusp,Data Fetch Suspended (FetSusp)" "0,1"
newline
bitfld.long 0x10 19. "OEPInt,OUT Endpoints Interrupt (OEPInt)" "0,1"
newline
bitfld.long 0x10 18. "IEPInt,IN Endpoints Interrupt (IEPInt)" "0,1"
newline
bitfld.long 0x10 17. "EPMis,Endpoint Mismatch Interrupt (EPMis)" "0,1"
newline
bitfld.long 0x10 16. "RstrDoneInt,Restore Done Interrupt (RstrDoneInt)" "0,1"
newline
bitfld.long 0x10 15. "EOPF,End of Periodic Frame Interrupt (EOPF)" "0,1"
newline
bitfld.long 0x10 14. "ISOOutDrop,Isochronous OUT Packet Dropped Interrupt (ISOOutDrop)" "0,1"
newline
bitfld.long 0x10 13. "EnumDone,Mode: Device only" "0,1"
newline
bitfld.long 0x10 12. "USBRst,USB Reset (USBRst)" "0,1"
newline
bitfld.long 0x10 11. "USBSusp,USB Suspend (USBSusp)" "0,1"
newline
bitfld.long 0x10 10. "ErlySusp,Early Suspend (ErlySusp)" "0,1"
newline
bitfld.long 0x10 7. "GOUTNakEff,Global OUT NAK Effective (GOUTNakEff)" "0,1"
newline
bitfld.long 0x10 6. "GINNakEff,Global IN Non-periodic NAK Effective (GINNakEff)" "0,1"
newline
bitfld.long 0x10 4. "RxFLvl,RxFIFO Non-Empty (RxFLvl)" "0,1"
newline
bitfld.long 0x10 3. "Sof,Start of (micro)Frame (Sof)" "0,1"
line.long 0x14 "GINTMSK,Interrupt Mask Register"
bitfld.long 0x14 31. "WkUpIntMsk,Resume/Remote Wakeup Detected Interrupt Mask (WkUpIntMsk)" "0,1"
newline
bitfld.long 0x14 27. "LPM_IntMsk,LPM Transaction Received Interrupt (LPM_Int)" "0,1"
newline
bitfld.long 0x14 22. "FetSuspMsk,Data Fetch Suspended Mask (FetSuspMsk)" "0,1"
newline
bitfld.long 0x14 19. "OEPIntMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x14 18. "IEPIntMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x14 17. "EPMisMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x14 16. "RstrDoneIntMsk,Restore Done Interrupt Mask (RstrDoneIntMsk)" "0,1"
newline
bitfld.long 0x14 15. "EOPFMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x14 14. "ISOOutDropMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x14 13. "EnumDoneMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x14 12. "USBRstMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x14 11. "USBSuspMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x14 10. "ErlySuspMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x14 7. "GOUTNakEffMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x14 6. "GINNakEffMsk,Mode: Device only " "0,1"
newline
bitfld.long 0x14 4. "RxFLvlMsk,Receive FIFO Non-Empty Mask (RxFLvlMsk)" "0,1"
newline
bitfld.long 0x14 3. "SofMsk,Start of (micro)Frame Mask (SofMsk)" "0,1"
newline
bitfld.long 0x14 2. "OTGIntMsk,OTG Interrupt Mask (OTGIntMsk)" "0,1"
rgroup.long 0x1C++0x7
line.long 0x0 "GRXSTSR,Receive Status Debug Read Register"
hexmask.long.byte 0x0 21.--24. 1. "FN,Mode: Device only"
newline
hexmask.long.byte 0x0 17.--20. 1. "PktSts,Packet Status (PktSts)"
newline
bitfld.long 0x0 15.--16. "DPID,Data PID (DPID)" "0,1,2,3"
newline
hexmask.long.word 0x0 4.--14. 1. "BCnt,Byte Count (BCnt)"
newline
hexmask.long.byte 0x0 0.--3. 1. "EPNum,Endpoint Number (EPNum)"
line.long 0x4 "GRXSTSP,Receive Status Read/Pop Register"
hexmask.long.byte 0x4 21.--24. 1. "FN,Mode: Device only"
newline
hexmask.long.byte 0x4 17.--20. 1. "PktSts,Packet Status (PktSts)"
newline
bitfld.long 0x4 15.--16. "DPID,Data PID (DPID)" "0,1,2,3"
newline
hexmask.long.word 0x4 4.--14. 1. "BCnt,Byte Count (BCnt)"
newline
hexmask.long.byte 0x4 0.--3. 1. "EPNum,Endpoint Number (EPNum)"
group.long 0x24++0x7
line.long 0x0 "GRXFSIZ,Receive FIFO Size Register"
hexmask.long.word 0x0 0.--10. 1. "RxFDep,RxFIFO Depth (RxFDep)"
line.long 0x4 "GNPTXFSIZ,Non-periodic Transmit FIFO Size Register"
hexmask.long.word 0x4 16.--31. 1. "INEPTxF0Dep,IN Endpoint TxFIFO 0 Depth (INEPTxF0Dep)"
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hexmask.long.word 0x4 0.--15. 1. "INEPTxF0StAddr,IN Endpoint FIFO0 Transmit RAM Start Address(INEPTxF0StAddr)"
rgroup.long 0x40++0x13
line.long 0x0 "GSNPSID,Synopsys ID Register"
hexmask.long 0x0 0.--31. 1. "SynopsysID,Release number of the controller being used currently."
line.long 0x4 "GHWCFG1,User HW Config1 Register"
hexmask.long 0x4 0.--31. 1. "EpDir,This 32-bit field uses two bits per endpoint to determine the endpoint direction."
line.long 0x8 "GHWCFG2,User HW Config2 Register"
bitfld.long 0x8 19. "DynFifoSizing,Dynamic FIFO Sizing Enabled (DynFifoSizing)" "0,1"
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hexmask.long.byte 0x8 10.--13. 1. "NumDevEps,Number of Device Endpoints (NumDevEps)"
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bitfld.long 0x8 8.--9. "FSPhyType,Full-Speed PHY Interface Type (FSPhyType)" "0,1,2,3"
line.long 0xC "GHWCFG3,User HW Config3 Register"
hexmask.long.word 0xC 16.--31. 1. "DfifoDepth,DFIFO Depth (DfifoDepth - EP_LOC_CNT)"
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bitfld.long 0xC 15. "LPMMode,LPM mode specified for Mode of Operation." "0,1"
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bitfld.long 0xC 14. "BCSupport,This bit indicates the controller support for Battery Charger." "0,1"
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bitfld.long 0xC 11. "RstType,Reset Style for Clocked always Blocks in RTL (RstType)" "0,1"
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bitfld.long 0xC 4.--6. "PktSizeWidth,Width of Packet Size Counters (PktSizeWidth)" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0xC 0.--3. 1. "XferSizeWidth,Width of Transfer Size Counters (XferSizeWidth)"
line.long 0x10 "GHWCFG4,User HW Config4 Register"
bitfld.long 0x10 31. "DescDMA,Scatter/Gather DMA configuration" "0: Non Dynamic configuration,1: Dynamic configuration"
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bitfld.long 0x10 30. "DescDMAEnable,Scatter/Gather DMA configuration" "0: Non-Scatter/Gather DMA configuration,1: Scatter/Gather DMA configuration"
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hexmask.long.byte 0x10 26.--29. 1. "INEps,Number of Device Mode IN Endpoints Including Control Endpoints (INEps)"
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hexmask.long.byte 0x10 16.--19. 1. "NumCtlEps,Number of Device Mode Control Endpoints in Addition to Endpoint 0 (NumCtlEps)"
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bitfld.long 0x10 6. "Hibernation,Enable Hibernation (Hibernation)" "0,1"
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bitfld.long 0x10 5. "AhbFreq,Minimum AHB Frequency Less Than 60 MHz (AhbFreq)" "0,1"
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bitfld.long 0x10 4. "PartialPwrDn,Enable Partial Power Down (PartialPwrDn)" "0,1"
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hexmask.long.byte 0x10 0.--3. 1. "NumDevPerioEps,Number of Device Mode Periodic IN Endpoints (NumDevPerioEps)"
group.long 0x54++0xB
line.long 0x0 "GLPMCFG,LPM Config Register"
bitfld.long 0x0 29. "RestoreSlpSts,LPM Restore Sleep Status (LPM_RestoreSlpSts)" "0,1"
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bitfld.long 0x0 28. "LPM_EnBESL,LPM Enable BESL (LPM_EnBESL)" "0,1"
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bitfld.long 0x0 25.--27. "LPM_RetryCnt_Sts,LPM Retry Count Status (LPM_RetryCnt_Sts)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 21.--23. "LPM_Retry_Cnt,LPM Retry Count (LPM_Retry_Cnt)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 16. "L1ResumeOK,Sleep State Resume OK (L1ResumeOK)" "0,1"
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bitfld.long 0x0 15. "SlpSts,Port Sleep Status (SlpSts)" "0,1"
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bitfld.long 0x0 13.--14. "CoreL1Res,LPM response (CoreL1Res)" "0,1,2,3"
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hexmask.long.byte 0x0 8.--12. 1. "HIRD_Thres,BESL/HIRD Threshold (HIRD_Thres)"
newline
bitfld.long 0x0 7. "EnblSlpM,Enable utmi_sleep_n (EnblSlpM)" "0,1"
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bitfld.long 0x0 6. "bRemoteWake,RemoteWakeEnable (bRemoteWake)" "0,1"
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hexmask.long.byte 0x0 2.--5. 1. "HIRD,Host-Initiated Resume Duration (HIRD)"
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bitfld.long 0x0 1. "AppL1Res,LPM response programmed by application (AppL1Res)" "0,1"
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bitfld.long 0x0 0. "LPMCap,The application uses this bit to control the controller LPM capabilities. If the core operates as a non-LPM-capable host it cannot request the connected device/hub to activate LPM mode. If the core operates as a non-LPM-capable device it cannot.." "0,1"
line.long 0x4 "GPWRDN,Global Power Down register"
hexmask.long.byte 0x4 24.--28. 1. "MultValIdBC,MultValIdBC"
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rbitfld.long 0x4 22. "BsessVld,B Session Valid (BsessVld)" "0,1"
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rbitfld.long 0x4 19.--20. "LineState,LineState" "0,1,2,3"
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bitfld.long 0x4 18. "StsChngIntMsk,StsChngIntMsk" "0,1"
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bitfld.long 0x4 17. "StsChngInt,Status Change Interrupt (StsChngInt)" "0,1"
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bitfld.long 0x4 14. "ConnDetMsk,ConnDetMsk" "0,1"
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bitfld.long 0x4 13. "ConnectDet,ConnectDet" "0,1"
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bitfld.long 0x4 12. "DisconnectDetectMsk,DisconnectDetectMsk" "0,1"
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bitfld.long 0x4 11. "DisconnectDetect,DisconnectDetect" "0,1"
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bitfld.long 0x4 10. "ResetDetMsk,ResetDetMsk" "0,1"
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bitfld.long 0x4 9. "ResetDetected,ResetDetected" "0,1"
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bitfld.long 0x4 8. "LineStageChangeMsk,LineStageChangeMsk" "0,1"
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bitfld.long 0x4 7. "LnStsChng,Line State Change (LnStsChng)" "0,1"
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bitfld.long 0x4 5. "PwrDnSwtch,Power Down Switch (PwrDnSwtch)" "0,1"
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bitfld.long 0x4 4. "PwrDnRst_n,Power Down ResetN (PwrDnRst_n)" "0,1"
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bitfld.long 0x4 3. "PwrDnClmp,Power Down Clamp (PwrDnClmp)" "0,1"
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bitfld.long 0x4 2. "Restore,Restore" "0,1"
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bitfld.long 0x4 1. "PMUActv,PMU Active (PMUActv)" "0,1"
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bitfld.long 0x4 0. "PMUIntSel,PMU Interrupt Select (PMUIntSel)" "0,1"
line.long 0x8 "GDFIFOCFG,Global DFIFO Configuration Register"
hexmask.long.word 0x8 16.--31. 1. "EPInfoBaseAddr,EPInfoBaseAddr"
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hexmask.long.word 0x8 0.--15. 1. "GDFIFOCfg,GDFIFOCfg"
group.long 0x13C++0xF
line.long 0x0 "DIEPTXF1,Device IN Endpoint Transmit FIFO Size Register i"
hexmask.long.word 0x0 16.--27. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
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hexmask.long.word 0x0 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr)"
line.long 0x4 "DIEPTXF2,Device IN Endpoint Transmit FIFO Size Register i"
hexmask.long.word 0x4 16.--27. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
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hexmask.long.word 0x4 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr)"
line.long 0x8 "DIEPTXF3,Device IN Endpoint Transmit FIFO Size Register i"
hexmask.long.word 0x8 16.--27. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
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hexmask.long.word 0x8 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr)"
line.long 0xC "DIEPTXF4,Device IN Endpoint Transmit FIFO Size Register i"
hexmask.long.word 0xC 16.--27. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
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hexmask.long.word 0xC 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr)"
group.long 0x800++0x7
line.long 0x0 "DCFG,Device Configuration Register"
hexmask.long.byte 0x0 26.--31. 1. "ResValid,Resume Validation Period (ResValid)"
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bitfld.long 0x0 24.--25. "PerSchIntvl,Periodic Scheduling Interval (PerSchIntvl)" "0,1,2,3"
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bitfld.long 0x0 23. "DescDMA,Enable Scatter/gather DMA in device mode (DescDMA)." "0,1"
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bitfld.long 0x0 15. "ErraticIntMsk,Erratic Error Interrupt Mask" "0,1"
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bitfld.long 0x0 13. "EnDevOutNak,Enable Device OUT NAK (EnDevOutNak)" "0,1"
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bitfld.long 0x0 11.--12. "PerFrInt,Periodic Frame Interval (PerFrInt)" "0,1,2,3"
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hexmask.long.byte 0x0 4.--10. 1. "DevAddr,Device Address (DevAddr)"
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bitfld.long 0x0 3. "Ena32KhzSusp,Enable 32 KHz Suspend mode (Ena32KhzSusp)" "0,1"
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bitfld.long 0x0 2. "NZStsOUTHShk,Non-Zero-Length Status OUT Handshake (NZStsOUTHShk)" "0,1"
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bitfld.long 0x0 0.--1. "DevSpd,Device Speed (DevSpd)" "0,1,2,3"
line.long 0x4 "DCTL,Device Control Register"
bitfld.long 0x4 18. "DeepSleepBESLReject,DeepSleepBESLReject" "0,1"
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bitfld.long 0x4 17. "EnContOnBNA,Enable Continue on BNA (EnContOnBNA)" "0,1"
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bitfld.long 0x4 16. "NakOnBble,NAK on Babble Error (NakOnBble)" "0,1"
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bitfld.long 0x4 15. "IgnrFrmNum,Ignore Frame number for Isochronous End points (IgnrFrmNum)" "0,1"
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bitfld.long 0x4 13.--14. "GMC,Global Multi Count (GMC)" "0,1,2,3"
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bitfld.long 0x4 11. "PWROnPrgDone,Power-On Programming Done (PWROnPrgDone)" "0,1"
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bitfld.long 0x4 10. "CGOUTNak,Clear Global OUT NAK (CGOUTNak)" "0,1"
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bitfld.long 0x4 9. "SGOUTNak,Set Global OUT NAK (SGOUTNak)" "0,1"
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bitfld.long 0x4 8. "CGNPInNak,Clear Global Non-periodic IN NAK (CGNPInNak)" "0,1"
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bitfld.long 0x4 7. "SGNPInNak,Set Global Non-periodic IN NAK (SGNPInNak)" "0,1"
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bitfld.long 0x4 4.--6. "TstCtl,Test Control (TstCtl)" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x4 3. "GOUTNakSts,Global OUT NAK Status (GOUTNakSts)" "0,1"
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rbitfld.long 0x4 2. "GNPINNakSts,Global Non-periodic IN NAK Status (GNPINNakSts)" "0,1"
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bitfld.long 0x4 1. "SftDiscon,Soft Disconnect (SftDiscon)" "0,1"
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bitfld.long 0x4 0. "RmtWkUpSig,Remote Wakeup Signaling (RmtWkUpSig)" "0,1"
rgroup.long 0x808++0x3
line.long 0x0 "DSTS,Device Status Register"
bitfld.long 0x0 22.--23. "DevLnSts,Device Line Status (DevLnSts)" "0,1,2,3"
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hexmask.long.word 0x0 8.--21. 1. "SOFFN,Number of the Received SOF (SOFFN)"
newline
bitfld.long 0x0 3. "ErrticErr,Erratic Error (ErrticErr)" "0,1"
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bitfld.long 0x0 1.--2. "EnumSpd,Enumerated Speed (EnumSpd)" "0,1,2,3"
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bitfld.long 0x0 0. "SuspSts,Suspend Status (SuspSts)" "0,1"
group.long 0x810++0x7
line.long 0x0 "DIEPMSK,Device IN Endpoint Common Interrupt Mask Register"
bitfld.long 0x0 13. "NAKMsk,NAK interrupt Mask (NAKMsk)" "0,1"
newline
bitfld.long 0x0 9. "BNAInIntrMsk,BNA interrupt Mask (BNAInIntrMsk)" "0,1"
newline
bitfld.long 0x0 8. "TxfifoUndrnMsk,Fifo Underrun Mask (TxfifoUndrnMsk)" "0,1"
newline
bitfld.long 0x0 6. "INEPNakEffMsk,IN Endpoint NAK Effective Mask (INEPNakEffMsk)" "0,1"
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bitfld.long 0x0 5. "INTknEPMisMsk,IN Token received with EP Mismatch Mask (INTknEPMisMsk)" "0,1"
newline
bitfld.long 0x0 4. "INTknTXFEmpMsk,IN Token Received When TxFIFO Empty Mask (INTknTXFEmpMsk)" "0,1"
newline
bitfld.long 0x0 3. "TimeOUTMsk,Timeout Condition Mask (TimeOUTMsk) (Non-isochronous endpoints)" "0,1"
newline
bitfld.long 0x0 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
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bitfld.long 0x0 1. "EPDisbldMsk,Endpoint Disabled Interrupt Mask (EPDisbldMsk)" "0,1"
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bitfld.long 0x0 0. "XferComplMsk,Transfer Completed Interrupt Mask (XferComplMsk)" "0,1"
line.long 0x4 "DOEPMSK,Device OUT Endpoint Common Interrupt Mask Register"
bitfld.long 0x4 14. "NYETMsk,NYET interrupt Mask (NYETMsk)" "0,1"
newline
bitfld.long 0x4 13. "NAKMsk,NAK interrupt Mask (NAKMsk)" "0,1"
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bitfld.long 0x4 12. "BbleErrMsk,Babble Error interrupt Mask (BbleErrMsk)" "0,1"
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bitfld.long 0x4 9. "BnaOutIntrMsk,BNA interrupt Mask (BnaOutIntrMsk)" "0,1"
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bitfld.long 0x4 8. "OutPktErrMsk,OUT Packet Error Mask (OutPktErrMsk)" "0,1"
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bitfld.long 0x4 6. "Back2BackSETup,Back-to-Back SETUP Packets Received Mask (Back2BackSETup)" "0,1"
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bitfld.long 0x4 5. "StsPhseRcvdMsk,Status Phase Received Mask (StsPhseRcvdMsk)" "0,1"
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bitfld.long 0x4 4. "OUTTknEPdisMsk,OUT Token Received when Endpoint Disabled Mask (OUTTknEPdisMsk)" "0,1"
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bitfld.long 0x4 3. "SetUPMsk,SETUP Phase Done Mask (SetUPMsk)" "0,1"
newline
bitfld.long 0x4 2. "AHBErrMsk,AHB Error (AHBErrMsk)" "0,1"
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bitfld.long 0x4 1. "EPDisbldMsk,Endpoint Disabled Interrupt Mask (EPDisbldMsk)" "0,1"
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bitfld.long 0x4 0. "XferComplMsk,Transfer Completed Interrupt Mask (XferComplMsk)" "0,1"
rgroup.long 0x818++0x3
line.long 0x0 "DAINT,Device All Endpoints Interrupt Register"
bitfld.long 0x0 20. "OutEPInt4,OUT Endpoint 4 Interrupt Bit" "0,1"
newline
bitfld.long 0x0 19. "OutEPInt3,OUT Endpoint 3 Interrupt Bit" "0,1"
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bitfld.long 0x0 18. "OutEPInt2,OUT Endpoint 2 Interrupt Bit" "0,1"
newline
bitfld.long 0x0 17. "OutEPInt1,OUT Endpoint 1 Interrupt Bit" "0,1"
newline
bitfld.long 0x0 16. "OutEPInt0,OUT Endpoint 0 Interrupt Bit" "0,1"
newline
bitfld.long 0x0 4. "InEpInt4,IN Endpoint 4 Interrupt Bit" "0,1"
newline
bitfld.long 0x0 3. "InEpInt3,IN Endpoint 3 Interrupt Bit" "0,1"
newline
bitfld.long 0x0 2. "InEpInt2,IN Endpoint 2 Interrupt Bit" "0,1"
newline
bitfld.long 0x0 1. "InEpInt1,IN Endpoint 1 Interrupt Bit" "0,1"
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bitfld.long 0x0 0. "InEpInt0,IN Endpoint 0 Interrupt Bit" "0,1"
group.long 0x81C++0x3
line.long 0x0 "DAINTMSK,Device All Endpoints Interrupt Mask Register"
bitfld.long 0x0 20. "OutEPMak4,OUT Endpoint 4 Interrupt mask Bit" "0,1"
newline
bitfld.long 0x0 19. "OutEPMak3,OUT Endpoint 3 Interrupt mask Bit" "0,1"
newline
bitfld.long 0x0 18. "OutEPMak2,OUT Endpoint 2 Interrupt mask Bit" "0,1"
newline
bitfld.long 0x0 17. "OutEPMak1,OUT Endpoint 1 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 16. "OutEPMak0,OUT Endpoint 0 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 4. "InEpMsk4,IN Endpoint 4 Interrupt mask Bit" "0,1"
newline
bitfld.long 0x0 3. "InEpMsk3,IN Endpoint 3 Interrupt mask Bit" "0,1"
newline
bitfld.long 0x0 2. "InEpMsk2,IN Endpoint 2 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 1. "InEpMsk1,IN Endpoint 1 Interrupt mask Bit" "0,1"
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bitfld.long 0x0 0. "InEpMsk0,IN Endpoint 0 Interrupt mask Bit" "0,1"
group.long 0x830++0x7
line.long 0x0 "DTHRCTL,Device Threshold Control Register"
bitfld.long 0x0 27. "ArbPrkEn,Arbiter Parking Enable (ArbPrkEn)" "0,1"
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hexmask.long.word 0x0 17.--25. 1. "RxThrLen,Receive Threshold Length (RxThrLen)"
newline
bitfld.long 0x0 16. "RxThrEn,Receive Threshold Enable (RxThrEn)" "0,1"
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bitfld.long 0x0 11.--12. "AHBThrRatio,AHB Threshold Ratio (AHBThrRatio)" "0,1,2,3"
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hexmask.long.word 0x0 2.--10. 1. "TxThrLen,Transmit Threshold Length (TxThrLen)"
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bitfld.long 0x0 1. "ISOThrEn,ISO IN Endpoints Threshold Enable. (ISOThrEn) When this bit is Set the core enables thresholding for isochronous IN endpoints." "0,1"
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bitfld.long 0x0 0. "NonISOThrEn,Non-ISO IN Endpoints Threshold Enable. (NonISOThrEn)" "0,1"
line.long 0x4 "DIEPEMPMSK,Device IN Endpoint FIFO Empty Interrupt Mask Register"
hexmask.long.word 0x4 0.--15. 1. "InEpTxfEmpMsk,IN EP Tx FIFO Empty Interrupt Mask Bits (InEpTxfEmpMsk)"
group.long 0x900++0x3
line.long 0x0 "DIEPCTL0,Device Control IN Endpoint 0 Control Register"
bitfld.long 0x0 31. "EPEna,When Scatter/Gather DMA mode is enabled for IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup." "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
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bitfld.long 0x0 27. "SNAK,Set NAK (SNAK) A write to this bit sets the NAK bit for the endpoint. Using this bit the application can control the transmission of NAK handshakes on an endpoint. The core can also set this bit for an endpoint after a SETUP packet is received on.." "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK) A write to this bit clears the NAK bit for the endpoint." "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,TxFIFO Number (TxFNum)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0,1,2,3"
newline
bitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0,1"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
bitfld.long 0x0 0.--1. "MPS,Maximum Packet Size (MPS)" "0,1,2,3"
group.long 0x908++0x3
line.long 0x0 "DIEPINT0,Device IN Endpoint 0 Interrupt Register"
bitfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
bitfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
bitfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
bitfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
bitfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
bitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
bitfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
bitfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
bitfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
bitfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
bitfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
bitfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0x914++0x3
line.long 0x0 "DIEPDMA0,Device IN Endpoint 0 DMA Address Register"
hexmask.long 0x0 0.--31. 1. "DMAAddr,DMAAddr"
rgroup.long 0x918++0x3
line.long 0x0 "DTXFSTS0,Device IN Endpoint Transmit FIFO Status Register 0"
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
group.long 0x91C++0x7
line.long 0x0 "DIEPDMAB0,Device IN Endpoint 16 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data transfer for the corresponding end point is in progress."
line.long 0x4 "DIEPCTL1,Device Control IN Endpoint 1 Control Register"
bitfld.long 0x4 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x4 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x4 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x4 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x4 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x4 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
rbitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType) This is the transfer type supported by this logical endpoint." "0,1,2,3"
newline
rbitfld.long 0x4 17. "NAKSts,NAK Status (NAKSts)" "0,1"
newline
rbitfld.long 0x4 16. "DPID,Endpoint Data PID (DPID)" "0,1"
newline
rbitfld.long 0x4 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0x928++0x3
line.long 0x0 "DIEPINT1,Device IN Endpoint 1 Interrupt Register"
bitfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
bitfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
bitfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
bitfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
bitfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
bitfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
bitfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
bitfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
bitfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
bitfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
bitfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0x934++0x3
line.long 0x0 "DIEPDMA1,Device IN Endpoint 1 DMA Address Register"
hexmask.long 0x0 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint data."
rgroup.long 0x938++0x3
line.long 0x0 "DTXFSTS1,Device IN Endpoint Transmit FIFO Status Register 1"
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
group.long 0x93C++0x7
line.long 0x0 "DIEPDMAB1,Device IN Endpoint 16 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address. This register is updated as and when the data transfer for the corresponding end point is in progress."
line.long 0x4 "DIEPCTL2,Device Control IN Endpoint 1 Control Register"
bitfld.long 0x4 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x4 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x4 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x4 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x4 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x4 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
rbitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType) This is the transfer type supported by this logical endpoint." "0,1,2,3"
newline
rbitfld.long 0x4 17. "NAKSts,NAK Status (NAKSts)" "0,1"
newline
rbitfld.long 0x4 16. "DPID,Endpoint Data PID (DPID)" "0,1"
newline
rbitfld.long 0x4 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0x948++0x3
line.long 0x0 "DIEPINT2,Device IN Endpoint 1 Interrupt Register"
bitfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
bitfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
bitfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
bitfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
bitfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
bitfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
bitfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
bitfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
bitfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
bitfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
bitfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0x954++0x3
line.long 0x0 "DIEPDMA2,Device IN Endpoint 1 DMA Address Register"
hexmask.long 0x0 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint data."
rgroup.long 0x958++0x3
line.long 0x0 "DTXFSTS2,Device IN Endpoint Transmit FIFO Status Register 1"
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
group.long 0x95C++0x7
line.long 0x0 "DIEPDMAB2,Device IN Endpoint 16 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address. This register is updated as and when the data transfer for the corresponding end point is in progress."
line.long 0x4 "DIEPCTL3,Device Control IN Endpoint 1 Control Register"
bitfld.long 0x4 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x4 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x4 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x4 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x4 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x4 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
rbitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType) This is the transfer type supported by this logical endpoint." "0,1,2,3"
newline
rbitfld.long 0x4 17. "NAKSts,NAK Status (NAKSts)" "0,1"
newline
rbitfld.long 0x4 16. "DPID,Endpoint Data PID (DPID)" "0,1"
newline
rbitfld.long 0x4 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0x968++0x3
line.long 0x0 "DIEPINT3,Device IN Endpoint 1 Interrupt Register"
bitfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
bitfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
bitfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
bitfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
bitfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
bitfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
bitfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
bitfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
bitfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
bitfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
bitfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0x974++0x3
line.long 0x0 "DIEPDMA3,Device IN Endpoint 1 DMA Address Register"
hexmask.long 0x0 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint data."
rgroup.long 0x978++0x3
line.long 0x0 "DTXFSTS3,Device IN Endpoint Transmit FIFO Status Register 1"
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
group.long 0x97C++0x7
line.long 0x0 "DIEPDMAB3,Device IN Endpoint 16 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address. This register is updated as and when the data transfer for the corresponding end point is in progress."
line.long 0x4 "DIEPCTL4,Device Control IN Endpoint 4 Control Register"
bitfld.long 0x4 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x4 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x4 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x4 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x4 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x4 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
rbitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType) This is the transfer type supported by this logical endpoint." "0,1,2,3"
newline
rbitfld.long 0x4 17. "NAKSts,NAK Status (NAKSts)" "0,1"
newline
rbitfld.long 0x4 16. "DPID,Endpoint Data PID (DPID)" "0,1"
newline
rbitfld.long 0x4 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0x988++0x3
line.long 0x0 "DIEPINT4,Device IN Endpoint 4 Interrupt Register"
bitfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
bitfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
bitfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
bitfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
bitfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
bitfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
bitfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
bitfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
bitfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
bitfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
bitfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0x994++0x3
line.long 0x0 "DIEPDMA4,Device IN Endpoint 4 DMA Address Register"
hexmask.long 0x0 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint data."
rgroup.long 0x998++0x3
line.long 0x0 "DTXFSTS4,Device IN Endpoint Transmit FIFO Status Register 4"
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
group.long 0x99C++0x3
line.long 0x0 "DIEPDMAB4,Device IN Endpoint 16 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address. This register is updated as and when the data transfer for the corresponding end point is in progress."
group.long 0xB00++0x3
line.long 0x0 "DOEPCTL0,Device Control OUT Endpoint 0 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
rbitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0,1,2,3"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
bitfld.long 0x0 0.--1. "MPS,Maximum Packet Size (MPS)" "0,1,2,3"
group.long 0xB08++0x3
line.long 0x0 "DOEPINT0,Device OUT Endpoint 0 Interrupt Register"
bitfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
bitfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
bitfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
bitfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
bitfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
bitfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
bitfld.long 0x0 5. "StsPhseRcvd,Status Phase Received for Control Write (StsPhseRcvd)" "0,1"
newline
bitfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
bitfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
bitfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
bitfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
bitfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xB14++0x3
line.long 0x0 "DOEPDMA0,Device OUT Endpoint 0 DMA Address Register"
hexmask.long 0x0 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint data."
rgroup.long 0xB1C++0x3
line.long 0x0 "DOEPDMAB0,Device OUT Endpoint 16 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address. This register is updated as and when the data transfer for the corresponding end point is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved."
group.long 0xB20++0x3
line.long 0x0 "DOEPCTL1,Device Control OUT Endpoint 1 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK) A write to this bit clears the NAK bit for the endpoint." "0,1"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
rbitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0,1"
newline
rbitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xB28++0x3
line.long 0x0 "DOEPINT1,Device OUT Endpoint 1 Interrupt Register"
bitfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
bitfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
bitfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
bitfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
bitfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
bitfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
bitfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
bitfld.long 0x0 5. "StsPhseRcvd,Status Phase Received for Control Write (StsPhseRcvd)" "0,1"
newline
bitfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
bitfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
bitfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
bitfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
bitfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xB34++0x3
line.long 0x0 "DOEPDMA1,Device OUT Endpoint 1 DMA Address Register"
hexmask.long 0x0 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint data."
rgroup.long 0xB3C++0x3
line.long 0x0 "DOEPDMAB1,Device OUT Endpoint 16 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data transfer for the corresponding end point is in progress."
group.long 0xB40++0x3
line.long 0x0 "DOEPCTL2,Device Control OUT Endpoint 2 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK) A write to this bit clears the NAK bit for the endpoint." "0,1"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
rbitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0,1"
newline
rbitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xB48++0x3
line.long 0x0 "DOEPINT2,Device OUT Endpoint 2 Interrupt Register"
bitfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
bitfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
bitfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
bitfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
bitfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
bitfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
bitfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
bitfld.long 0x0 5. "StsPhseRcvd,Status Phase Received for Control Write (StsPhseRcvd)" "0,1"
newline
bitfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
bitfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
bitfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
bitfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
bitfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xB54++0x3
line.long 0x0 "DOEPDMA2,Device OUT Endpoint 2 DMA Address Register"
hexmask.long 0x0 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint data."
rgroup.long 0xB5C++0x3
line.long 0x0 "DOEPDMAB2,Device OUT Endpoint 16 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data transfer for the corresponding end point is in progress."
group.long 0xB60++0x3
line.long 0x0 "DOEPCTL3,Device Control OUT Endpoint 3 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK) A write to this bit clears the NAK bit for the endpoint." "0,1"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
rbitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0,1"
newline
rbitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xB68++0x3
line.long 0x0 "DOEPINT3,Device OUT Endpoint 3 Interrupt Register"
bitfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
bitfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
bitfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
bitfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
bitfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
bitfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
bitfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
bitfld.long 0x0 5. "StsPhseRcvd,Status Phase Received for Control Write (StsPhseRcvd)" "0,1"
newline
bitfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
bitfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
bitfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
bitfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
bitfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xB74++0x3
line.long 0x0 "DOEPDMA3,Device OUT Endpoint 3 DMA Address Register"
hexmask.long 0x0 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint data."
rgroup.long 0xB7C++0x3
line.long 0x0 "DOEPDMAB3,Device OUT Endpoint 16 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data transfer for the corresponding end point is in progress."
group.long 0xB80++0x3
line.long 0x0 "DOEPCTL4,Device Control OUT Endpoint 4 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK) A write to this bit clears the NAK bit for the endpoint." "0,1"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
rbitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0,1"
newline
rbitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xB88++0x3
line.long 0x0 "DOEPINT4,Device OUT Endpoint 4 Interrupt Register"
bitfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
bitfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
bitfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
bitfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
bitfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
bitfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
bitfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
bitfld.long 0x0 5. "StsPhseRcvd,Status Phase Received for Control Write (StsPhseRcvd)" "0,1"
newline
bitfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
bitfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
bitfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
bitfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
bitfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xB94++0x3
line.long 0x0 "DOEPDMA4,Device OUT Endpoint 4 DMA Address Register"
hexmask.long 0x0 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint data."
rgroup.long 0xB9C++0x3
line.long 0x0 "DOEPDMAB4,Device OUT Endpoint 16 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data transfer for the corresponding end point is in progress."
group.long 0xE00++0x3
line.long 0x0 "PCGCCTL,Power and Clock Gating Control Register"
hexmask.long.tbyte 0x0 14.--31. 1. "RestoreValue,Restore Value (RestoreValue)"
newline
bitfld.long 0x0 13. "EssRegRestored,Essential Register Values Restored (EssRegRestored)" "0,1"
newline
bitfld.long 0x0 9. "RestoreMode,Restore Mode (RestoreMode)" "0,1"
newline
bitfld.long 0x0 7. "L1Suspended,L1 Deep Sleep" "0,1"
newline
bitfld.long 0x0 6. "PhySleep,PHY In Sleep" "0,1"
newline
bitfld.long 0x0 5. "Enbl_L1Gating,Enable Sleep Clock Gating" "0,1"
newline
bitfld.long 0x0 3. "RstPdwnModule,Reset Power-Down Modules (RstPdwnModule)" "0,1"
newline
bitfld.long 0x0 2. "PwrClmp,Power Clamp (PwrClmp)" "0,1"
newline
bitfld.long 0x0 1. "GateHclk,Gate Hclk (GateHclk)" "0,1"
newline
bitfld.long 0x0 0. "StopPclk,Stop Pclk (StopPclk)" "0,1"
tree.end
tree "WDT (Watchdog Timer)"
base ad:0x40001A00
group.long 0x0++0xB
line.long 0x0 "CR,Watch-dog Timer Control Register"
hexmask.long.word 0x0 16.--31. 1. "WTIDKY,Write Identification Key. On writes write 0x5A69 to these bits otherwise the write is ignored."
hexmask.long.byte 0x0 10.--15. 1. "RSTEN,Watch-dog Timer Reset Enable bits"
newline
hexmask.long.byte 0x0 4.--9. 1. "CNTEN,Watch-dog Timer Counter Enable bits"
bitfld.long 0x0 3. "WINMIEN,Watch-dog Timer Window Match Interrupt Enable bit" "0,1"
newline
bitfld.long 0x0 2. "UNFIEN,Watch-dog Timer Underflow Interrupt Enable bit" "0,1"
bitfld.long 0x0 0.--1. "CLKDIV,Watch-dog Timer Clock Divider bits The clock which is selected by PPCLKSR[0]" "0,1,2,3"
line.long 0x4 "SR,Watch-dog Timer Status Register"
bitfld.long 0x4 7. "DBGCNTEN,Watch-dog Timer Counter Enable bit. When the core is halted in the debug mode. Note: This bit is cleared to '0b' only by POR reset." "0: The watch-dog timer counter continues even if..,1: The watch-dog timer counter is stopped when the.."
bitfld.long 0x4 1. "WINMIFLAG,Watch-dog Timer Window Match Interrupt Flag bit" "0: No request occurred,1: Request occurred This bit is cleared to '0' when.."
newline
bitfld.long 0x4 0. "UNFIFLAG,Watch-dog Timer Underflow Interrupt Flag bit" "0: No request occurred,1: Request occurred This bit is cleared to '0' when.."
line.long 0x8 "DR,Watch-dog Timer Data Register"
hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Watch-dog Timer Data bits. The range is 0x000000 to 0xFFFFFF."
rgroup.long 0xC++0x3
line.long 0x0 "CNT,Watch-dog Timer Counter Register"
hexmask.long.tbyte 0x0 0.--23. 1. "CNT,Watch-dog Timer Counter bits."
group.long 0x10++0x3
line.long 0x0 "WINDR,Watch-dog Timer Window Data Register (Note: Once any value is written to this window data register. the register can't be changed until a system reset.)"
hexmask.long.tbyte 0x0 0.--23. 1. "WDATA,Watch-dog Timer Window Data bits. The range is 0x000000 to 0xFFFFFF."
wgroup.long 0x14++0x3
line.long 0x0 "CNTR,Watch-dog Timer Counter Reload Register"
hexmask.long.byte 0x0 0.--7. 1. "CNTR,Watch-dog Timer Counter Reload bits."
tree.end
tree "WT (Watch Timer)"
base ad:0x40002000
group.long 0x0++0x7
line.long 0x0 "CR,Watch Timer Control Register"
bitfld.long 0x0 7. "WTEN,Watch Timer Operation Enable bit" "0: Disable watch timer operation,1: Enable watch timer operation"
bitfld.long 0x0 4.--5. "WTINTV,Watch Timer Interval Selection bits." "0: fWT/2^7,1: fWT/2^13,2: fWT/2^14,3: fWT/(2^14x(WTDR value + 1))"
newline
bitfld.long 0x0 3. "WTIEN,Watch Timer Interrupt Enable bit" "0: Disable watch timer interrupt,1: Enable watch timer interrupt"
bitfld.long 0x0 1. "WTIFLAG,Watch Timer Interrupt Flag bit" "0: No request occurred,1: Request occurred This bit is cleared to '0' when.."
newline
bitfld.long 0x0 0. "WTCLR,Watch Timer Counter and Divider Clear bit" "0: No effect,1: Clear the counter and divider (Automatically.."
line.long 0x4 "DR,Watch Timer Data Register"
hexmask.long.word 0x4 0.--11. 1. "WTDATA,Watch Timer Data bits. The range is 0x001 to 0xFFF."
rgroup.long 0x8++0x3
line.long 0x0 "CNT,Watch Timer Counter Register"
hexmask.long.word 0x0 0.--11. 1. "CNT,Watch Timer Counter bits."
tree.end
AUTOINDENT.OFF
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