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Gen4_R-Car_Trace32/2_Trunk/pera31g1xx.per
woody d411edd9b4 add Trace32 File
2025-10-14 09:52:32 +09:00

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; --------------------------------------------------------------------------------
; @Title: A31G1xx On-Chip Peripherals
; @Props: Released
; @Author: JDU, NEJ
; @Changelog: 2023-02-06 JDU
; 2023-11-02 NEJ
; @Manufacturer: ABOV - ABOV Semiconductor Co., Ltd.
; @Doc: Generated (TRACE32, build: 164232.), based on:
; A31G11x.svd (Ver. 1.0), A31G12x_fixed.svd (Ver. 1.0)
; @Core: Cortex-M0+
; @Chip: A31G111GR, A31G111KN, A31G111KU, A31G111LU, A31G112CL, A31G112GR,
; A31G112KN, A31G112KU, A31G112KY, A31G112LU, A31G112SQ, A31G122CL,
; A31G122GR, A31G122KN, A31G122SQ, A31G123CL, A31G123GR, A31G123KN,
; A31G123SQ
; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: pera31g1xx.per 16938 2023-11-07 18:43:11Z kwisniewski $
AUTOINDENT.ON CENTER TREE
ENUMDELIMITER ","
base ad:0x0
tree.close "Core Registers (Cortex-M0+)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0x8
if (CORENAME()=="CORTEXM1")
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
else
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
endif
if (CORENAME()=="CORTEXM1")
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
else
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
endif
rgroup.long 0xd00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
textline " "
hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
group.long 0xd04++0x03
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
textline " "
bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
textline " "
bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
textline " "
bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
textline " "
hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
if (CORENAME()=="CORTEXM0+")
group.long 0xd08++0x03
line.long 0x00 "VTOR,Vector Table Offset Register"
hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
else
textline " "
endif
group.long 0xd0c++0x03
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
textline " "
bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
group.long 0xd10++0x03
line.long 0x00 "SCR,System Control Register"
bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline " "
bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
rgroup.long 0xd14++0x03
line.long 0x00 "CCR,Configuration and Control Register"
bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
group.long 0xd1c++0x0b
line.long 0x00 "SHPR2,System Handler Priority Register 2"
bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
line.long 0x04 "SHPR3,System Handler Priority Register 3"
bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
line.long 0x08 "SHCSR,System Handler Control and State Register"
bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
if (CORENAME()=="CORTEXM0+")
hgroup.long 0x08++0x03
hide.long 0x00 "ACTLR,Auxiliary Control Register"
else
textline " "
endif
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Memory Protection Unit (MPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
rgroup.long 0xD90++0x03
line.long 0x00 "MPU_TYPE,MPU Type Register"
bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..."
group.long 0xD94++0x03
line.long 0x00 "MPU_CTRL,MPU Control Register"
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
group.long 0xD98++0x03
line.long 0x00 "MPU_RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
tree.close "MPU regions"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
group.long 0xD9C++0x03 "Region 0"
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
group.long 0xD9C++0x03 "Region 1"
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
group.long 0xD9C++0x03 "Region 2"
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
group.long 0xD9C++0x03 "Region 3"
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
group.long 0xD9C++0x03 "Region 4"
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
group.long 0xD9C++0x03 "Region 5"
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
group.long 0xD9C++0x03 "Region 6"
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
group.long 0xD9C++0x03 "Region 7"
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
textline " "
textline " "
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
tree "Interrupt Enable Registers"
group.long 0x100++0x03
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
tree.end
tree "Interrupt Pending Registers"
group.long 0x200++0x03
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
tree.end
width 6.
tree "Interrupt Priority Registers"
group.long 0x400++0x1F
line.long 0x00 "INT0,Interrupt Priority Register"
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
line.long 0x04 "INT1,Interrupt Priority Register"
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
line.long 0x08 "INT2,Interrupt Priority Register"
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
line.long 0x0C "INT3,Interrupt Priority Register"
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
line.long 0x10 "INT4,Interrupt Priority Register"
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
line.long 0x14 "INT5,Interrupt Priority Register"
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
line.long 0x18 "INT6,Interrupt Priority Register"
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
line.long 0x1C "INT7,Interrupt Priority Register"
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0xA
group.long 0xD30++0x03
line.long 0x00 "DFSR,Data Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
textline " "
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
textline " "
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
if (CORENAME()=="CORTEXM1")
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
else
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
endif
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Selector Register"
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
group.long 0xDF8++0x07
line.long 0x00 "DCRDR,Debug Core Register Data Register"
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
textline " "
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Breakpoint Unit (BPU)"
sif COMPonent.AVAILABLE("BPU")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
width 8.
group.long 0x00++0x03
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
group.long 0x8++0x03
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
group.long 0xC++0x03
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
group.long 0x10++0x03
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
group.long 0x14++0x03
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
else
newline
textline "BPU component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 14.
rgroup.long 0x00++0x03
line.long 0x00 "DW_CTRL,DW Control Register "
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x1c++0x03
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
group.long 0x20++0x0b
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
line.long 0x04 "DW_MASK0,DW Mask Register 0"
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
group.long 0x30++0x0b
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
tree "ADC (12-bit A/D Converter)"
base ad:0x40003000
group.long 0x0++0x3
line.long 0x0 "CR,A/D Converter Control Register"
bitfld.long 0x0 15. "ADCEN,ADC Module Enable" "0: Disable ADC module operation.,1: Enable ADC module operation."
bitfld.long 0x0 11.--13. "TRIG,ADC Trigger Signal Selection" "0: Select ADST.,1: Select TIMER10 A-Match Signal.,2: Select TIMER11 A-Match Signal.,3: Select TIMER12 A-Match Signal.,4: Select ADC Trigger Signal from TIMER30.,?,?,?"
newline
bitfld.long 0x0 10. "REFSEL,ADC Reference Selection" "0: Select analog power (VDD).,1: Select external reference (AVREF)."
bitfld.long 0x0 8. "ADST,ADC Conversion Start" "0: No effect.,1: Trigger signal generation for conversion start."
newline
bitfld.long 0x0 5. "ADCIEN,ADC Interrupt Enable" "0: Disable ADC interrupt.,1: Enable ADC interrupt."
bitfld.long 0x0 4. "ADCIFLAG,ADC Interrupt Flag" "0: No request occurred.,1: Request occurred."
newline
sif (cpuis("A31G12?*"))
hexmask.long.byte 0x0 0.--3. 1. "ADSEL,A/D Converter Channel Selection"
endif
sif (cpuis("A31G11?*"))
hexmask.long.byte 0x0 0.--3. 1. "ADSEL,A/D Converter Channel Selection"
endif
rgroup.long 0x4++0x3
line.long 0x0 "DR,A/D Converter Data Register"
hexmask.long.word 0x0 0.--11. 1. "ADDATA,A/D Converter Result Data"
group.long 0x8++0x3
line.long 0x0 "PREDR,A/D Converter Prescaler Data Register"
hexmask.long.byte 0x0 0.--4. 1. "PRED,A/D Converter Prescaler Data"
tree.end
tree "COA (Configuration Option Area)"
base ad:0x0
tree "COA0 (System Related Trimming Value)"
base ad:0x1FFFF000
rgroup.long 0x0++0x7F
line.long 0x0 "TRIM00,System Related Trim Value 00"
line.long 0x4 "TRIM01,System Related Trim Value 01"
line.long 0x8 "TRIM02,System Related Trim Value 02"
line.long 0xC "TRIM03,System Related Trim Value 03"
line.long 0x10 "TRIM04,System Related Trim Value 04"
line.long 0x14 "TRIM05,System Related Trim Value 05"
line.long 0x18 "TRIM06,System Related Trim Value 06"
line.long 0x1C "TRIM07,System Related Trim Value 07"
line.long 0x20 "TRIM08,System Related Trim Value 08"
line.long 0x24 "TRIM09,System Related Trim Value 09"
line.long 0x28 "TRIM10,System Related Trim Value 10"
line.long 0x2C "TRIM11,System Related Trim Value 11"
line.long 0x30 "TRIM12,System Related Trim Value 12"
line.long 0x34 "TRIM13,System Related Trim Value 13"
line.long 0x38 "TRIM14,System Related Trim Value 14"
line.long 0x3C "TRIM15,System Related Trim Value 15"
line.long 0x40 "TRIM16,System Related Trim Value 16"
line.long 0x44 "TRIM17,System Related Trim Value 17"
line.long 0x48 "TRIM18,System Related Trim Value 18"
line.long 0x4C "TRIM19,System Related Trim Value 19"
line.long 0x50 "CONF_MF1CNFIG,Manufacture Information 1"
hexmask.long 0x50 0.--31. 1. "XYCDN,X and Y Coordinates"
line.long 0x54 "CONF_MF2CNFIG,Manufacture Information 2"
hexmask.long.tbyte 0x54 8.--31. 1. "LOTNO,Lot Number [23:0]"
hexmask.long.byte 0x54 0.--7. 1. "WAFNO,Wafer Number"
line.long 0x58 "CONF_MF3CNFIG,Manufacture Information 3"
hexmask.long 0x58 0.--31. 1. "LOTNO,Lot Number [55:24]"
line.long 0x5C "CONF_MF4CNFIG,Manufacture Information 4"
hexmask.long 0x5C 0.--31. 1. "LOTNO,Lot Number [87:56]"
line.long 0x60 "TRIM24,System Related Trim Value 24"
line.long 0x64 "TRIM25,System Related Trim Value 25"
line.long 0x68 "TRIM26,System Related Trim Value 26"
line.long 0x6C "TRIM27,System Related Trim Value 27"
line.long 0x70 "TRIM28,System Related Trim Value 28"
line.long 0x74 "TRIM29,System Related Trim Value 29"
line.long 0x78 "TRIM30,System Related Trim Value 30"
line.long 0x7C "TRIM31,System Related Trim Value 31"
tree.end
tree "COA1 (User Option)"
base ad:0x1FFFF200
rgroup.long 0x0++0x3
line.long 0x0 "RPCNFIG,Configuration for Read Protection"
hexmask.long 0x0 4.--31. 1. "WTIDKY,Write Identification Key (0x69c8a27)"
bitfld.long 0x0 0.--1. "READP,Read Protection for Flash Memory Area" "0: 1. Not readable/erasable/writable by 'Debug' /..,?,2: 1. Not readable/erasable/writable by 'Debug' 2.,3: No restriction for read/erase/write."
rgroup.long 0xC++0xB
line.long 0x0 "WDTCNFIG,Configuration for Watch-Dog Timer"
hexmask.long.word 0x0 4.--15. 1. "WRCMF,Watch-Dog Timer RC Oscillator Master Configuration"
bitfld.long 0x0 2. "WCLKMF,Watch-Dog Timer Clock Selection Master Configuration" "0: By S/W (PPCLKSR Register),1: Always WDTRC"
newline
bitfld.long 0x0 1. "WRSTMF,Watch-Dog Timer Reset Enable Master Configuration" "0: Always Enable,1: By S/W (WDTCR Register)"
bitfld.long 0x0 0. "WCNTMF,Watch-Dog Timer Counter Enable Master Configuration" "0: Always Enable,1: By S/W (WDTCR Register)"
line.long 0x4 "LVRCNFIG,Configuration for Low Voltage Reset"
hexmask.long.byte 0x4 8.--15. 1. "LVRENM,LVR Reset Operation Control Master Configuration"
hexmask.long.byte 0x4 0.--3. 1. "LVRVS,LVR Voltage Selection"
line.long 0x8 "CNFIGWTP1,Erase/Write Protection for Configure Option Page 1/2/3"
bitfld.long 0x8 2. "CP3WP,Configure Option Page 3 Erase/Write Protection" "0: Enable protection. (Not erasable/writable by..,1: Disable protection. (Erasable/writable by.."
bitfld.long 0x8 1. "CP2WP,Configure Option Page 2 Erase/Write Protection" "0: Enable protection. (Not erasable/writable by..,1: Disable protection. (Erasable/writable by.."
newline
bitfld.long 0x8 0. "CP1WP,Configure Option Page 1 Erase/Write Protection" "0: Enable protection. (Not erasable/writable by..,1: Disable protection. (Erasable/writable by.."
rgroup.long 0x40++0x3
line.long 0x0 "FMWTP1,Erase/Write Protection for Flash Memory"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 31. "SWTP31,Flash Memory Erase/Write Protection 31" "0: Protect 'flash memory sector n erase/write',1: Permit 'flash memory sector n erase/write'"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 30. "SWTP30,Flash Memory Erase/Write Protection 30" "0: Protect 'flash memory sector n erase/write',1: Permit 'flash memory sector n erase/write'"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 29. "SWTP29,Flash Memory Erase/Write Protection 29" "0: Protect 'flash memory sector n erase/write',1: Permit 'flash memory sector n erase/write'"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 28. "SWTP28,Flash Memory Erase/Write Protection 28" "0: Protect 'flash memory sector n erase/write',1: Permit 'flash memory sector n erase/write'"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 27. "SWTP27,Flash Memory Erase/Write Protection 27" "0: Protect 'flash memory sector n erase/write',1: Permit 'flash memory sector n erase/write'"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 26. "SWTP26,Flash Memory Erase/Write Protection 26" "0: Protect 'flash memory sector n erase/write',1: Permit 'flash memory sector n erase/write'"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 25. "SWTP25,Flash Memory Erase/Write Protection 25" "0: Protect 'flash memory sector n erase/write',1: Permit 'flash memory sector n erase/write'"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 24. "SWTP24,Flash Memory Erase/Write Protection 24" "0: Protect 'flash memory sector n erase/write',1: Permit 'flash memory sector n erase/write'"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 23. "SWTP23,Flash Memory Erase/Write Protection 23" "0: Protect 'flash memory sector n erase/write',1: Permit 'flash memory sector n erase/write'"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 22. "SWTP22,Flash Memory Erase/Write Protection 22" "0: Protect 'flash memory sector n erase/write',1: Permit 'flash memory sector n erase/write'"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 21. "SWTP21,Flash Memory Erase/Write Protection 21" "0: Protect 'flash memory sector n erase/write',1: Permit 'flash memory sector n erase/write'"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 20. "SWTP20,Flash Memory Erase/Write Protection 20" "0: Protect 'flash memory sector n erase/write',1: Permit 'flash memory sector n erase/write'"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 19. "SWTP19,Flash Memory Erase/Write Protection 19" "0: Protect 'flash memory sector n erase/write',1: Permit 'flash memory sector n erase/write'"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 18. "SWTP18,Flash Memory Erase/Write Protection 18" "0: Protect 'flash memory sector n erase/write',1: Permit 'flash memory sector n erase/write'"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 17. "SWTP17,Flash Memory Erase/Write Protection 17" "0: Protect 'flash memory sector n erase/write',1: Permit 'flash memory sector n erase/write'"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 16. "SWTP16,Flash Memory Erase/Write Protection 16" "0: Protect 'flash memory sector n erase/write',1: Permit 'flash memory sector n erase/write'"
newline
endif
bitfld.long 0x0 15. "SWTP15,Flash Memory Erase/Write Protection 15" "0: Protect 'flash memory sector n erase/write',1: Permit 'flash memory sector n erase/write'"
bitfld.long 0x0 14. "SWTP14,Flash Memory Erase/Write Protection 14" "0: Protect 'flash memory sector n erase/write',1: Permit 'flash memory sector n erase/write'"
newline
bitfld.long 0x0 13. "SWTP13,Flash Memory Erase/Write Protection 13" "0: Protect 'flash memory sector n erase/write',1: Permit 'flash memory sector n erase/write'"
bitfld.long 0x0 12. "SWTP12,Flash Memory Erase/Write Protection 12" "0: Protect 'flash memory sector n erase/write',1: Permit 'flash memory sector n erase/write'"
newline
bitfld.long 0x0 11. "SWTP11,Flash Memory Erase/Write Protection 11" "0: Protect 'flash memory sector n erase/write',1: Permit 'flash memory sector n erase/write'"
bitfld.long 0x0 10. "SWTP10,Flash Memory Erase/Write Protection 10" "0: Protect 'flash memory sector n erase/write',1: Permit 'flash memory sector n erase/write'"
newline
bitfld.long 0x0 9. "SWTP9,Flash Memory Erase/Write Protection 9" "0: Protect 'flash memory sector n erase/write',1: Permit 'flash memory sector n erase/write'"
bitfld.long 0x0 8. "SWTP8,Flash Memory Erase/Write Protection 8" "0: Protect 'flash memory sector n erase/write',1: Permit 'flash memory sector n erase/write'"
newline
bitfld.long 0x0 7. "SWTP7,Flash Memory Erase/Write Protection 7" "0: Protect 'flash memory sector n erase/write',1: Permit 'flash memory sector n erase/write'"
bitfld.long 0x0 6. "SWTP6,Flash Memory Erase/Write Protection 6" "0: Protect 'flash memory sector n erase/write',1: Permit 'flash memory sector n erase/write'"
newline
bitfld.long 0x0 5. "SWTP5,Flash Memory Erase/Write Protection 5" "0: Protect 'flash memory sector n erase/write',1: Permit 'flash memory sector n erase/write'"
bitfld.long 0x0 4. "SWTP4,Flash Memory Erase/Write Protection 4" "0: Protect 'flash memory sector n erase/write',1: Permit 'flash memory sector n erase/write'"
newline
bitfld.long 0x0 3. "SWTP3,Flash Memory Erase/Write Protection 3" "0: Protect 'flash memory sector n erase/write',1: Permit 'flash memory sector n erase/write'"
bitfld.long 0x0 2. "SWTP2,Flash Memory Erase/Write Protection 2" "0: Protect 'flash memory sector n erase/write',1: Permit 'flash memory sector n erase/write'"
newline
bitfld.long 0x0 1. "SWTP1,Flash Memory Erase/Write Protection 1" "0: Protect 'flash memory sector n erase/write',1: Permit 'flash memory sector n erase/write'"
bitfld.long 0x0 0. "SWTP0,Flash Memory Erase/Write Protection 0" "0: Protect 'flash memory sector n erase/write',1: Permit 'flash memory sector n erase/write'"
tree.end
tree "COA2 (User Data Area 0)"
base ad:0x1FFFF400
rgroup.long 0x0++0x7F
line.long 0x0 "UDATA00,User Data 00"
line.long 0x4 "UDATA01,User Data 01"
line.long 0x8 "UDATA02,User Data 02"
line.long 0xC "UDATA03,User Data 03"
line.long 0x10 "UDATA04,User Data 04"
line.long 0x14 "UDATA05,User Data 05"
line.long 0x18 "UDATA06,User Data 06"
line.long 0x1C "UDATA07,User Data 07"
line.long 0x20 "UDATA08,User Data 08"
line.long 0x24 "UDATA09,User Data 09"
line.long 0x28 "UDATA10,User Data 10"
line.long 0x2C "UDATA11,User Data 11"
line.long 0x30 "UDATA12,User Data 12"
line.long 0x34 "UDATA13,User Data 13"
line.long 0x38 "UDATA14,User Data 14"
line.long 0x3C "UDATA15,User Data 15"
line.long 0x40 "UDATA16,User Data 16"
line.long 0x44 "UDATA17,User Data 17"
line.long 0x48 "UDATA18,User Data 18"
line.long 0x4C "UDATA19,User Data 19"
line.long 0x50 "UDATA20,User Data 20"
line.long 0x54 "UDATA21,User Data 21"
line.long 0x58 "UDATA22,User Data 22"
line.long 0x5C "UDATA23,User Data 23"
line.long 0x60 "UDATA24,User Data 24"
line.long 0x64 "UDATA25,User Data 25"
line.long 0x68 "UDATA26,User Data 26"
line.long 0x6C "UDATA27,User Data 27"
line.long 0x70 "UDATA28,User Data 28"
line.long 0x74 "UDATA29,User Data 29"
line.long 0x78 "UDATA30,User Data 30"
line.long 0x7C "UDATA31,User Data 31"
tree.end
tree "COA3 (User Data Area 1)"
base ad:0x1FFFF600
rgroup.long 0x0++0x7F
line.long 0x0 "UDATA00,User Data 00"
line.long 0x4 "UDATA01,User Data 01"
line.long 0x8 "UDATA02,User Data 02"
line.long 0xC "UDATA03,User Data 03"
line.long 0x10 "UDATA04,User Data 04"
line.long 0x14 "UDATA05,User Data 05"
line.long 0x18 "UDATA06,User Data 06"
line.long 0x1C "UDATA07,User Data 07"
line.long 0x20 "UDATA08,User Data 08"
line.long 0x24 "UDATA09,User Data 09"
line.long 0x28 "UDATA10,User Data 10"
line.long 0x2C "UDATA11,User Data 11"
line.long 0x30 "UDATA12,User Data 12"
line.long 0x34 "UDATA13,User Data 13"
line.long 0x38 "UDATA14,User Data 14"
line.long 0x3C "UDATA15,User Data 15"
line.long 0x40 "UDATA16,User Data 16"
line.long 0x44 "UDATA17,User Data 17"
line.long 0x48 "UDATA18,User Data 18"
line.long 0x4C "UDATA19,User Data 19"
line.long 0x50 "UDATA20,User Data 20"
line.long 0x54 "UDATA21,User Data 21"
line.long 0x58 "UDATA22,User Data 22"
line.long 0x5C "UDATA23,User Data 23"
line.long 0x60 "UDATA24,User Data 24"
line.long 0x64 "UDATA25,User Data 25"
line.long 0x68 "UDATA26,User Data 26"
line.long 0x6C "UDATA27,User Data 27"
line.long 0x70 "UDATA28,User Data 28"
line.long 0x74 "UDATA29,User Data 29"
line.long 0x78 "UDATA30,User Data 30"
line.long 0x7C "UDATA31,User Data 31"
tree.end
tree.end
tree "CRC (Cyclic Redundancy Check and Checksum)"
base ad:0x30001000
group.long 0x0++0x7
line.long 0x0 "CR,CRC/Checksum Control Register"
bitfld.long 0x0 7. "MODS,User/Auto Mode Selection" "0: User Mode (Calculate every data written to the..,1: Auto Mode (Calculate till CRC_SADR == CRC_EADR)"
bitfld.long 0x0 6. "RLTCLR,CRC/Checksum Result Data Register (CRCRLT) Initialization" "0: No effect.,1: Initialize the CRC_RLT register with the value.."
newline
bitfld.long 0x0 5. "MDSEL,CRC/Checksum Selection" "0: Select CRC.,1: Select Checksum."
bitfld.long 0x0 4. "POLYS,Polynomial Selection (CRC only)" "0: CRC16-CCITT (G1(x) = x16 + x12 + x5 + 1),1: CRC16 (G2(x) = x16 + x15 + x2 + 1)"
newline
bitfld.long 0x0 3. "SARINC,CRC/Checksum Start Address Auto Increment Control (User mode only)" "0: No effect.,1: The CRC/Checksum start address register is.."
bitfld.long 0x0 1. "FIRSTBS,First Shifted-in Selection (CRC only)" "0: msb first,1: lsb first"
newline
bitfld.long 0x0 0. "CRCRUN,CRC/Checksum Start Control and Busy" "0: Not busy. The CRC operation can be finished by..,1: Start CRC operation. This bit is automatically.."
line.long 0x4 "IN,CRC/Checksum Input Data Register"
hexmask.long 0x4 0.--31. 1. "INDATA,CRC Input Data"
rgroup.long 0x8++0x3
line.long 0x0 "RLT,CRC/Checksum Result Data Register"
hexmask.long.word 0x0 0.--15. 1. "RLTDATA,CRC Result Data"
group.long 0xC++0xB
line.long 0x0 "INIT,CRC/Checksum Initial Data Register"
hexmask.long.word 0x0 0.--15. 1. "INIDATA,CRC Initial Data"
line.long 0x4 "SADR,CRC/Checksum Start Address Register"
hexmask.long 0x4 2.--31. 1. "SADR,CRC Start Address"
line.long 0x8 "EADR,CRC/Checksum End Address Register"
hexmask.long 0x8 2.--31. 1. "EADR,CRC End Address"
tree.end
tree "FMC (Flash Memory Controller)"
base ad:0x40001B00
group.long 0x0++0x17
line.long 0x0 "ADR,Flash Memory Address Register"
hexmask.long 0x0 0.--31. 1. "ADDR,Flash Memory Address Pointer"
line.long 0x4 "IDR1,Flash Memory Identification Register 1"
hexmask.long 0x4 0.--31. 1. "ID1,Flash Memory Identification 1"
line.long 0x8 "IDR2,Flash Memory Identification Register 2"
hexmask.long 0x8 0.--31. 1. "ID2,Flash Memory Identification 2"
line.long 0xC "CR,Flash Memory Control Register"
hexmask.long.word 0xC 16.--31. 1. "WTIDKY,Write Identification Key (0x6c93)"
hexmask.long.byte 0xC 8.--15. 1. "FMKEY,Flash Memory Operation Area Selection"
rbitfld.long 0xC 7. "FMBUSY,Flash Memory Operation Mode Busy" "0,1"
hexmask.long.byte 0xC 0.--3. 1. "FMOD,Flash Memory Operation Mode Selection"
line.long 0x10 "BCR,Flash Memory Configure Area Bulk Erase Control Register"
hexmask.long.word 0x10 16.--31. 1. "WTIDKY,Write Identification Key (0xc1be)"
hexmask.long.byte 0x10 8.--11. 1. "CNF3BEN,Configure Option Page 3 Bulk Erase Enable"
hexmask.long.byte 0x10 4.--7. 1. "CNF2BEN,Configure Option Page 2 Bulk Erase Enable"
hexmask.long.byte 0x10 0.--3. 1. "CNF1BEN,Configure Option Page 1 Bulk Erase Enable"
line.long 0x14 "ERFLAG,Flash Memory Error Flag"
bitfld.long 0x14 1. "INSTFLAG,Don't care" "0,1"
bitfld.long 0x14 0. "FMOPFLAG,Error bit of Flash Memory Operation Procedure" "0,1"
wgroup.long 0x100++0x3
line.long 0x0 "PAGEBUF,Flash Memory Page Buffer Area (128bytes/Accessed by 32bit Word Only)"
tree.end
tree "I2C (Inter-Integrated Circuit)"
base ad:0x0
sif (cpuis("A31G12?*"))
tree "I2C2"
base ad:0x40004A00
group.long 0x0++0x1F
line.long 0x0 "CR,I2Cn Control Register"
bitfld.long 0x0 7. "I2CnEN,Activate I2Cn Block by supplying" "0,1"
bitfld.long 0x0 6. "TXDLYENBn,SDHR Register Control" "0,1"
bitfld.long 0x0 5. "I2CnIEN,I2Cn Interrupt Enable" "0,1"
bitfld.long 0x0 4. "I2CnIFLAG,I2Cn Interrupt Flag" "0,1"
bitfld.long 0x0 3. "ACKnEN,Controls ACK signal generation at ninth SCL period" "0,1"
rbitfld.long 0x0 2. "IMASTERn,Represent Operation Mode of I2Cn" "0,1"
bitfld.long 0x0 1. "STOPCn,STOP Condition Generation when I2Cn is master" "0,1"
newline
bitfld.long 0x0 0. "STARTCn,START Condition Generation when I2Cn is master" "0,1"
line.long 0x4 "ST,I2Cn Status Register"
bitfld.long 0x4 7. "GCALLn,This bit has different meaning depending on whether I2C is master or slave." "0,1"
bitfld.long 0x4 6. "TENDn,This bit is set when 1-byte of data is transferred completely" "?,1: byte of data is transferred completely"
bitfld.long 0x4 5. "STOPDn,This bit is set when a STOP condition is detected" "0,1"
bitfld.long 0x4 4. "SSELn,This bit is set when I2C is addressed by other master" "0,1"
bitfld.long 0x4 3. "MLOSTn,This bit represents the result of bus arbitration in master mode" "0,1"
bitfld.long 0x4 2. "BUSYn,This bit reflects bus status" "0,1"
rbitfld.long 0x4 1. "TMODEn,This bit is used to indicate whether I2C is transmitter or receiver" "0,1"
newline
bitfld.long 0x4 0. "RXACKn,This bit shows the state of ACK signal" "0,1"
line.long 0x8 "SAR1,I2Cn Slave Address Register 1"
hexmask.long.byte 0x8 1.--7. 1. "SLAn,These bits configure the slave address 1 in slave mode"
bitfld.long 0x8 0. "GCALLnEN,This bit decides whether I2Cn allows general call address 1 or not in I2Cn slave mode" "0,1"
line.long 0xC "SAR2,I2Cn Slave Address Register 2"
hexmask.long.byte 0xC 1.--7. 1. "SLAn,These bits configure the slave address 2 in slave mode"
bitfld.long 0xC 0. "GCALLnEN,This bit decides whether I2Cn allows general call address 2 or not in I2Cn slave mode" "0,1"
line.long 0x10 "DR,I2Cn Data Register"
hexmask.long.byte 0x10 0.--7. 1. "DATA,The DR Transmit buffer and Receive buffer share the same I/O address with this DATA register"
line.long 0x14 "SDHR,I2Cn SDA Hold Time Register"
hexmask.long.word 0x14 0.--11. 1. "HLDT,This register is used to control SDA output timing from the falling edge of SCL"
line.long 0x18 "SCLR,I2Cn SCL Low Period Register"
hexmask.long.word 0x18 0.--11. 1. "SCLL,This register defines the low period of SCL in master mode"
line.long 0x1C "SCHR,I2Cn SCL High Period Register"
hexmask.long.word 0x1C 0.--11. 1. "SCLH,This register defines the high period of SCL in master mode"
tree.end
endif
tree "I2C0"
base ad:0x40004800
group.long 0x0++0x1F
line.long 0x0 "CR,I2Cn Control Register"
bitfld.long 0x0 7. "I2CnEN,Activate I2Cn Block" "0,1"
bitfld.long 0x0 6. "TXDLYENBn,SDHR Register Control" "0,1"
bitfld.long 0x0 5. "I2CnIEN,I2Cn Interrupt Enable" "0,1"
bitfld.long 0x0 4. "I2CnIFLAG,I2Cn Interrupt Flag" "0,1"
bitfld.long 0x0 3. "ACKnEN,Controls ACK signal generation at ninth SCL period" "0,1"
rbitfld.long 0x0 2. "IMASTERn,Represent Operation Mode of I2Cn" "0,1"
bitfld.long 0x0 1. "STOPCn,STOP Condition Generation when I2Cn is master" "0,1"
newline
bitfld.long 0x0 0. "STARTCn,START Condition Generation when I2Cn is master" "0,1"
line.long 0x4 "ST,I2Cn Status Register"
bitfld.long 0x4 7. "GCALLn,This bit has different meaning depending on whether I2C is master or slave." "0,1"
bitfld.long 0x4 6. "TENDn,This bit is set when 1-byte of data is transferred completely" "?,1: byte of data is transferred completely"
bitfld.long 0x4 5. "STOPDn,This bit is set when a STOP condition is detected" "0,1"
bitfld.long 0x4 4. "SSELn,This bit is set when I2C is addressed by other master" "0,1"
bitfld.long 0x4 3. "MLOSTn,This bit represents the result of bus arbitration in master mode" "0,1"
bitfld.long 0x4 2. "BUSYn,This bit reflects bus status" "0,1"
rbitfld.long 0x4 1. "TMODEn,This bit is used to indicate whether I2C is transmitter or receiver" "0,1"
newline
bitfld.long 0x4 0. "RXACKn,This bit shows the state of ACK signal" "0,1"
line.long 0x8 "SAR1,I2Cn Slave Address Register 1"
hexmask.long.byte 0x8 1.--7. 1. "SLAn,These bits configure the slave address 1 in slave mode"
bitfld.long 0x8 0. "GCALLnEN,This bit decides whether I2Cn allows general call address 1 or not in I2Cn slave mode" "0,1"
line.long 0xC "SAR2,I2Cn Slave Address Register 2"
hexmask.long.byte 0xC 1.--7. 1. "SLAn,These bits configure the slave address 2 in slave mode"
bitfld.long 0xC 0. "GCALLnEN,This bit decides whether I2Cn allows general call address 2 or not in I2Cn slave mode" "0,1"
line.long 0x10 "DR,I2Cn Data Register"
hexmask.long.byte 0x10 0.--7. 1. "DATA,The DR Transmit buffer and Receive buffer share the same I/O address with this DATA register"
line.long 0x14 "SDHR,I2Cn SDA Hold Time Register"
hexmask.long.word 0x14 0.--11. 1. "HLDT,This register is used to control SDA output timing from the falling edge of SCL"
line.long 0x18 "SCLR,I2Cn SCL Low Period Register"
hexmask.long.word 0x18 0.--11. 1. "SCLL,This register defines the low period of SCL in master mode"
line.long 0x1C "SCHR,I2Cn SCL High Period Register"
hexmask.long.word 0x1C 0.--11. 1. "SCLH,This register defines the high period of SCL in master mode"
tree.end
tree "I2C1"
base ad:0x40004900
group.long 0x0++0x1F
line.long 0x0 "CR,I2Cn Control Register"
bitfld.long 0x0 7. "I2CnEN,Activate I2Cn Block" "0,1"
bitfld.long 0x0 6. "TXDLYENBn,SDHR Register Control" "0,1"
bitfld.long 0x0 5. "I2CnIEN,I2Cn Interrupt Enable" "0,1"
bitfld.long 0x0 4. "I2CnIFLAG,I2Cn Interrupt Flag" "0,1"
bitfld.long 0x0 3. "ACKnEN,Controls ACK signal generation at ninth SCL period" "0,1"
rbitfld.long 0x0 2. "IMASTERn,Represent Operation Mode of I2Cn" "0,1"
bitfld.long 0x0 1. "STOPCn,STOP Condition Generation when I2Cn is master" "0,1"
newline
bitfld.long 0x0 0. "STARTCn,START Condition Generation when I2Cn is master" "0,1"
line.long 0x4 "ST,I2Cn Status Register"
bitfld.long 0x4 7. "GCALLn,This bit has different meaning depending on whether I2C is master or slave." "0,1"
bitfld.long 0x4 6. "TENDn,This bit is set when 1-byte of data is transferred completely" "?,1: byte of data is transferred completely"
bitfld.long 0x4 5. "STOPDn,This bit is set when a STOP condition is detected" "0,1"
bitfld.long 0x4 4. "SSELn,This bit is set when I2C is addressed by other master" "0,1"
bitfld.long 0x4 3. "MLOSTn,This bit represents the result of bus arbitration in master mode" "0,1"
bitfld.long 0x4 2. "BUSYn,This bit reflects bus status" "0,1"
rbitfld.long 0x4 1. "TMODEn,This bit is used to indicate whether I2C is transmitter or receiver" "0,1"
newline
bitfld.long 0x4 0. "RXACKn,This bit shows the state of ACK signal" "0,1"
line.long 0x8 "SAR1,I2Cn Slave Address Register 1"
hexmask.long.byte 0x8 1.--7. 1. "SLAn,These bits configure the slave address 1 in slave mode"
bitfld.long 0x8 0. "GCALLnEN,This bit decides whether I2Cn allows general call address 1 or not in I2Cn slave mode" "0,1"
line.long 0xC "SAR2,I2Cn Slave Address Register 2"
hexmask.long.byte 0xC 1.--7. 1. "SLAn,These bits configure the slave address 2 in slave mode"
bitfld.long 0xC 0. "GCALLnEN,This bit decides whether I2Cn allows general call address 2 or not in I2Cn slave mode" "0,1"
line.long 0x10 "DR,I2Cn Data Register"
hexmask.long.byte 0x10 0.--7. 1. "DATA,The DR Transmit buffer and Receive buffer share the same I/O address with this DATA register"
line.long 0x14 "SDHR,I2Cn SDA Hold Time Register"
hexmask.long.word 0x14 0.--11. 1. "HLDT,This register is used to control SDA output timing from the falling edge of SCL"
line.long 0x18 "SCLR,I2Cn SCL Low Period Register"
hexmask.long.word 0x18 0.--11. 1. "SCLL,This register defines the low period of SCL in master mode"
line.long 0x1C "SCHR,I2Cn SCL High Period Register"
hexmask.long.word 0x1C 0.--11. 1. "SCLH,This register defines the high period of SCL in master mode"
tree.end
tree "I2Cn"
base ad:0x56000000
group.long 0x0++0x1F
line.long 0x0 "CR,I2Cn Control Register"
bitfld.long 0x0 7. "I2CnEN,Activate I2Cn Block" "0,1"
bitfld.long 0x0 6. "TXDLYENBn,SDHR Register Control" "0,1"
bitfld.long 0x0 5. "I2CnIEN,I2Cn Interrupt Enable" "0,1"
bitfld.long 0x0 4. "I2CnIFLAG,I2Cn Interrupt Flag" "0,1"
bitfld.long 0x0 3. "ACKnEN,Controls ACK signal generation at ninth SCL period" "0,1"
rbitfld.long 0x0 2. "IMASTERn,Represent Operation Mode of I2Cn" "0,1"
bitfld.long 0x0 1. "STOPCn,STOP Condition Generation when I2Cn is master" "0,1"
newline
bitfld.long 0x0 0. "STARTCn,START Condition Generation when I2Cn is master" "0,1"
line.long 0x4 "ST,I2Cn Status Register"
bitfld.long 0x4 7. "GCALLn,This bit has different meaning depending on whether I2C is master or slave." "0,1"
bitfld.long 0x4 6. "TENDn,This bit is set when 1-byte of data is transferred completely" "?,1: byte of data is transferred completely"
bitfld.long 0x4 5. "STOPDn,This bit is set when a STOP condition is detected" "0,1"
bitfld.long 0x4 4. "SSELn,This bit is set when I2C is addressed by other master" "0,1"
bitfld.long 0x4 3. "MLOSTn,This bit represents the result of bus arbitration in master mode" "0,1"
bitfld.long 0x4 2. "BUSYn,This bit reflects bus status" "0,1"
rbitfld.long 0x4 1. "TMODEn,This bit is used to indicate whether I2C is transmitter or receiver" "0,1"
newline
bitfld.long 0x4 0. "RXACKn,This bit shows the state of ACK signal" "0,1"
line.long 0x8 "SAR1,I2Cn Slave Address Register 1"
hexmask.long.byte 0x8 1.--7. 1. "SLAn,These bits configure the slave address 1 in slave mode"
bitfld.long 0x8 0. "GCALLnEN,This bit decides whether I2Cn allows general call address 1 or not in I2Cn slave mode" "0,1"
line.long 0xC "SAR2,I2Cn Slave Address Register 2"
hexmask.long.byte 0xC 1.--7. 1. "SLAn,These bits configure the slave address 2 in slave mode"
bitfld.long 0xC 0. "GCALLnEN,This bit decides whether I2Cn allows general call address 2 or not in I2Cn slave mode" "0,1"
line.long 0x10 "DR,I2Cn Data Register"
hexmask.long.byte 0x10 0.--7. 1. "DATA,The DR Transmit buffer and Receive buffer share the same I/O address with this DATA register"
line.long 0x14 "SDHR,I2Cn SDA Hold Time Register"
hexmask.long.word 0x14 0.--11. 1. "HLDT,This register is used to control SDA output timing from the falling edge of SCL"
line.long 0x18 "SCLR,I2Cn SCL Low Period Register"
hexmask.long.word 0x18 0.--11. 1. "SCLL,This register defines the low period of SCL in master mode"
line.long 0x1C "SCHR,I2Cn SCL High Period Register"
hexmask.long.word 0x1C 0.--11. 1. "SCLH,This register defines the high period of SCL in master mode"
tree.end
tree.end
tree "INTC (Interrupt Controller)"
base ad:0x40001000
group.long 0x4++0x7
line.long 0x0 "PBTRIG,Port B Interrupt Trigger Selection Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "ITRIG11,Port B Interrupt Trigger Selection 11" "0: Edge trigger interrupt,1: Level trigger interrupt"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "ITRIG10,Port B Interrupt Trigger Selection 10" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "ITRIG9,Port B Interrupt Trigger Selection 9" "0: Edge trigger interrupt,1: Level trigger interrupt"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "ITRIG8,Port B Interrupt Trigger Selection 8" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
endif
bitfld.long 0x0 7. "ITRIG7,Port B Interrupt Trigger Selection 7" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x0 6. "ITRIG6,Port B Interrupt Trigger Selection 6" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x0 5. "ITRIG5,Port B Interrupt Trigger Selection 5" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x0 4. "ITRIG4,Port B Interrupt Trigger Selection 4" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x0 3. "ITRIG3,Port B Interrupt Trigger Selection 3" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x0 2. "ITRIG2,Port B Interrupt Trigger Selection 2" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x0 1. "ITRIG1,Port B Interrupt Trigger Selection 1" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x0 0. "ITRIG0,Port B Interrupt Trigger Selection 0" "0: Edge trigger interrupt,1: Level trigger interrupt"
line.long 0x4 "PCTRIG,Port C Interrupt Trigger Selection Register"
bitfld.long 0x4 3. "ITRIG3,Port C Interrupt Trigger Selection 3" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 2. "ITRIG2,Port C Interrupt Trigger Selection 2" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x4 1. "ITRIG1,Port C Interrupt Trigger Selection 1" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 0. "ITRIG0,Port C Interrupt Trigger Selection 0" "0: Edge trigger interrupt,1: Level trigger interrupt"
group.long 0x10++0x3
line.long 0x0 "PETRIG,Port E Interrupt Trigger Selection Register"
bitfld.long 0x0 3. "ITRIG3,Port E Interrupt Trigger Selection 3" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x0 2. "ITRIG2,Port E Interrupt Trigger Selection 2" "0: Edge trigger interrupt,1: Level trigger interrupt"
newline
bitfld.long 0x0 1. "ITRIG1,Port E Interrupt Trigger Selection 1" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x0 0. "ITRIG0,Port E Interrupt Trigger Selection 0" "0: Edge trigger interrupt,1: Level trigger interrupt"
group.long 0x104++0x7
line.long 0x0 "PBCR,Port B Interrupt Control Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 22.--23. "INTCTL11,Port B Interrupt Control 11" "0: Disable external interrupt.,1: Interrupt on falling edge or on low level,2: Interrupt on rising edge or on high level,3: Interrupt on both falling and rising edge No.."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 20.--21. "INTCTL10,Port B Interrupt Control 10" "0: Disable external interrupt.,1: Interrupt on falling edge or on low level,2: Interrupt on rising edge or on high level,3: Interrupt on both falling and rising edge No.."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 18.--19. "INTCTL9,Port B Interrupt Control 9" "0: Disable external interrupt.,1: Interrupt on falling edge or on low level,2: Interrupt on rising edge or on high level,3: Interrupt on both falling and rising edge No.."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 16.--17. "INTCTL8,Port B Interrupt Control 8" "0: Disable external interrupt.,1: Interrupt on falling edge or on low level,2: Interrupt on rising edge or on high level,3: Interrupt on both falling and rising edge No.."
newline
endif
bitfld.long 0x0 14.--15. "INTCTL7,Port B Interrupt Control 7" "0: Disable external interrupt.,1: Interrupt on falling edge or on low level,2: Interrupt on rising edge or on high level,3: Interrupt on both falling and rising edge No.."
bitfld.long 0x0 12.--13. "INTCTL6,Port B Interrupt Control 6" "0: Disable external interrupt.,1: Interrupt on falling edge or on low level,2: Interrupt on rising edge or on high level,3: Interrupt on both falling and rising edge No.."
newline
bitfld.long 0x0 10.--11. "INTCTL5,Port B Interrupt Control 5" "0: Disable external interrupt.,1: Interrupt on falling edge or on low level,2: Interrupt on rising edge or on high level,3: Interrupt on both falling and rising edge No.."
bitfld.long 0x0 8.--9. "INTCTL4,Port B Interrupt Control 4" "0: Disable external interrupt.,1: Interrupt on falling edge or on low level,2: Interrupt on rising edge or on high level,3: Interrupt on both falling and rising edge No.."
newline
bitfld.long 0x0 6.--7. "INTCTL3,Port B Interrupt Control 3" "0: Disable external interrupt.,1: Interrupt on falling edge or on low level,2: Interrupt on rising edge or on high level,3: Interrupt on both falling and rising edge No.."
bitfld.long 0x0 4.--5. "INTCTL2,Port B Interrupt Control 2" "0: Disable external interrupt.,1: Interrupt on falling edge or on low level,2: Interrupt on rising edge or on high level,3: Interrupt on both falling and rising edge No.."
newline
bitfld.long 0x0 2.--3. "INTCTL1,Port B Interrupt Control 1" "0: Disable external interrupt.,1: Interrupt on falling edge or on low level,2: Interrupt on rising edge or on high level,3: Interrupt on both falling and rising edge No.."
bitfld.long 0x0 0.--1. "INTCTL0,Port B Interrupt Control 0" "0: Disable external interrupt.,1: Interrupt on falling edge or on low level,2: Interrupt on rising edge or on high level,3: Interrupt on both falling and rising edge No.."
line.long 0x4 "PCCR,Port C Interrupt Control Register"
bitfld.long 0x4 6.--7. "INTCTL3,Port C Interrupt Control 3" "0: Disable external interrupt.,1: Interrupt on falling edge or on low level,2: Interrupt on rising edge or on high level,3: Interrupt on both falling and rising edge No.."
bitfld.long 0x4 4.--5. "INTCTL2,Port C Interrupt Control 2" "0: Disable external interrupt.,1: Interrupt on falling edge or on low level,2: Interrupt on rising edge or on high level,3: Interrupt on both falling and rising edge No.."
newline
bitfld.long 0x4 2.--3. "INTCTL1,Port C Interrupt Control 1" "0: Disable external interrupt.,1: Interrupt on falling edge or on low level,2: Interrupt on rising edge or on high level,3: Interrupt on both falling and rising edge No.."
bitfld.long 0x4 0.--1. "INTCTL0,Port C Interrupt Control 0" "0: Disable external interrupt.,1: Interrupt on falling edge or on low level,2: Interrupt on rising edge or on high level,3: Interrupt on both falling and rising edge No.."
group.long 0x110++0x3
line.long 0x0 "PECR,Port E Interrupt Control Register"
bitfld.long 0x0 6.--7. "INTCTL3,Port E Interrupt Control 3" "0: Disable external interrupt.,1: Interrupt on falling edge or on low level,2: Interrupt on rising edge or on high level,3: Interrupt on both falling and rising edge No.."
bitfld.long 0x0 4.--5. "INTCTL2,Port E Interrupt Control 2" "0: Disable external interrupt.,1: Interrupt on falling edge or on low level,2: Interrupt on rising edge or on high level,3: Interrupt on both falling and rising edge No.."
newline
bitfld.long 0x0 2.--3. "INTCTL1,Port E Interrupt Control 1" "0: Disable external interrupt.,1: Interrupt on falling edge or on low level,2: Interrupt on rising edge or on high level,3: Interrupt on both falling and rising edge No.."
bitfld.long 0x0 0.--1. "INTCTL0,Port E Interrupt Control 0" "0: Disable external interrupt.,1: Interrupt on falling edge or on low level,2: Interrupt on rising edge or on high level,3: Interrupt on both falling and rising edge No.."
group.long 0x204++0x7
line.long 0x0 "PBFLAG,Port B Interrupt Flag Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "FLAG11,Port B Interrupt Flag 11" "0: No request occurred.,1: Request occurred."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "FLAG10,Port B Interrupt Flag 10" "0: No request occurred.,1: Request occurred."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "FLAG9,Port B Interrupt Flag 9" "0: No request occurred.,1: Request occurred."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "FLAG8,Port B Interrupt Flag 8" "0: No request occurred.,1: Request occurred."
newline
endif
bitfld.long 0x0 7. "FLAG7,Port B Interrupt Flag 7" "0: No request occurred.,1: Request occurred."
bitfld.long 0x0 6. "FLAG6,Port B Interrupt Flag 6" "0: No request occurred.,1: Request occurred."
newline
bitfld.long 0x0 5. "FLAG5,Port B Interrupt Flag 5" "0: No request occurred.,1: Request occurred."
bitfld.long 0x0 4. "FLAG4,Port B Interrupt Flag 4" "0: No request occurred.,1: Request occurred."
newline
bitfld.long 0x0 3. "FLAG3,Port B Interrupt Flag 3" "0: No request occurred.,1: Request occurred."
bitfld.long 0x0 2. "FLAG2,Port B Interrupt Flag 2" "0: No request occurred.,1: Request occurred."
newline
bitfld.long 0x0 1. "FLAG1,Port B Interrupt Flag 1" "0: No request occurred.,1: Request occurred."
bitfld.long 0x0 0. "FLAG0,Port B Interrupt Flag 0" "0: No request occurred.,1: Request occurred."
line.long 0x4 "PCFLAG,Port C Interrupt Flag Register"
bitfld.long 0x4 3. "FLAG3,Port C Interrupt Flag 3" "0: No request occurred.,1: Request occurred."
bitfld.long 0x4 2. "FLAG2,Port C Interrupt Flag 2" "0: No request occurred.,1: Request occurred."
newline
bitfld.long 0x4 1. "FLAG1,Port C Interrupt Flag 1" "0: No request occurred.,1: Request occurred."
bitfld.long 0x4 0. "FLAG0,Port C Interrupt Flag 0" "0: No request occurred.,1: Request occurred."
group.long 0x210++0x3
line.long 0x0 "PEFLAG,Port E Interrupt Flag Register"
bitfld.long 0x0 3. "FLAG3,Port E Interrupt Flag 3" "0: No request occurred.,1: Request occurred."
bitfld.long 0x0 2. "FLAG2,Port E Interrupt Flag 2" "0: No request occurred.,1: Request occurred."
newline
bitfld.long 0x0 1. "FLAG1,Port E Interrupt Flag 1" "0: No request occurred.,1: Request occurred."
bitfld.long 0x0 0. "FLAG0,Port E Interrupt Flag 0" "0: No request occurred.,1: Request occurred."
group.long 0x300++0xF
line.long 0x0 "EINT0CONF1,External Interrupt 0 Configuration Register 1"
hexmask.long.byte 0x0 28.--31. 1. "CONF7,External Interrupt 0 Configuration 7"
hexmask.long.byte 0x0 24.--27. 1. "CONF6,External Interrupt 0 Configuration 6"
newline
hexmask.long.byte 0x0 20.--23. 1. "CONF5,External Interrupt 0 Configuration 5"
hexmask.long.byte 0x0 16.--19. 1. "CONF4,External Interrupt 0 Configuration 4"
newline
hexmask.long.byte 0x0 12.--15. 1. "CONF3,External Interrupt 0 Configuration 3"
hexmask.long.byte 0x0 8.--11. 1. "CONF2,External Interrupt 0 Configuration 2"
newline
hexmask.long.byte 0x0 4.--7. 1. "CONF1,External Interrupt 0 Configuration 1"
hexmask.long.byte 0x0 0.--3. 1. "CONF0,External Interrupt 0 Configuration 0"
line.long 0x4 "EINT1CONF1,External Interrupt 1 Configuration Register 1"
hexmask.long.byte 0x4 28.--31. 1. "CONF7,External Interrupt 1 Configuration 7"
hexmask.long.byte 0x4 24.--27. 1. "CONF6,External Interrupt 1 Configuration 6"
newline
hexmask.long.byte 0x4 20.--23. 1. "CONF5,External Interrupt 1 Configuration 5"
hexmask.long.byte 0x4 16.--19. 1. "CONF4,External Interrupt 1 Configuration 4"
newline
hexmask.long.byte 0x4 12.--15. 1. "CONF3,External Interrupt 1 Configuration 3"
hexmask.long.byte 0x4 8.--11. 1. "CONF2,External Interrupt 1 Configuration 2"
newline
hexmask.long.byte 0x4 4.--7. 1. "CONF1,External Interrupt 1 Configuration 1"
hexmask.long.byte 0x4 0.--3. 1. "CONF0,External Interrupt 1 Configuration 0"
line.long 0x8 "EINT2CONF1,External Interrupt 2 Configuration Register 1"
hexmask.long.byte 0x8 28.--31. 1. "CONF7,External Interrupt 2 Configuration 7"
hexmask.long.byte 0x8 24.--27. 1. "CONF6,External Interrupt 2 Configuration 6"
newline
hexmask.long.byte 0x8 20.--23. 1. "CONF5,External Interrupt 2 Configuration 5"
hexmask.long.byte 0x8 16.--19. 1. "CONF4,External Interrupt 2 Configuration 4"
newline
hexmask.long.byte 0x8 12.--15. 1. "CONF3,External Interrupt 2 Configuration 3"
hexmask.long.byte 0x8 8.--11. 1. "CONF2,External Interrupt 2 Configuration 2"
newline
hexmask.long.byte 0x8 4.--7. 1. "CONF1,External Interrupt 2 Configuration 1"
hexmask.long.byte 0x8 0.--3. 1. "CONF0,External Interrupt 2 Configuration 0"
line.long 0xC "EINT3CONF1,External Interrupt 3 Configuration Register 1"
hexmask.long.byte 0xC 28.--31. 1. "CONF7,External Interrupt 3 Configuration 7"
hexmask.long.byte 0xC 24.--27. 1. "CONF6,External Interrupt 3 Configuration 6"
newline
hexmask.long.byte 0xC 20.--23. 1. "CONF5,External Interrupt 3 Configuration 5"
hexmask.long.byte 0xC 16.--19. 1. "CONF4,External Interrupt 3 Configuration 4"
newline
hexmask.long.byte 0xC 12.--15. 1. "CONF3,External Interrupt 3 Configuration 3"
hexmask.long.byte 0xC 8.--11. 1. "CONF2,External Interrupt 3 Configuration 2"
newline
hexmask.long.byte 0xC 4.--7. 1. "CONF1,External Interrupt 3 Configuration 1"
hexmask.long.byte 0xC 0.--3. 1. "CONF0,External Interrupt 3 Configuration 0"
sif (cpuis("A31G12?*"))
group.long 0x310++0xF
line.long 0x0 "EINT0CONF2,External Interrupt 0 Configuration Register 2"
hexmask.long.byte 0x0 12.--15. 1. "CONF11,External Interrupt 0 Configuration 11"
hexmask.long.byte 0x0 8.--11. 1. "CONF10,External Interrupt 0 Configuration 10"
newline
hexmask.long.byte 0x0 4.--7. 1. "CONF9,External Interrupt 0 Configuration 9"
hexmask.long.byte 0x0 0.--3. 1. "CONF8,External Interrupt 0 Configuration 8"
line.long 0x4 "EINT1CONF2,External Interrupt 1 Configuration Register 2"
hexmask.long.byte 0x4 12.--15. 1. "CONF11,External Interrupt 1 Configuration 11"
hexmask.long.byte 0x4 8.--11. 1. "CONF10,External Interrupt 1 Configuration 10"
newline
hexmask.long.byte 0x4 4.--7. 1. "CONF9,External Interrupt 1 Configuration 9"
hexmask.long.byte 0x4 0.--3. 1. "CONF8,External Interrupt 1 Configuration 8"
line.long 0x8 "EINT2CONF2,External Interrupt 2 Configuration Register 2"
hexmask.long.byte 0x8 12.--15. 1. "CONF11,External Interrupt 2 Configuration 11"
hexmask.long.byte 0x8 8.--11. 1. "CONF10,External Interrupt 2 Configuration 10"
newline
hexmask.long.byte 0x8 4.--7. 1. "CONF9,External Interrupt 2 Configuration 9"
hexmask.long.byte 0x8 0.--3. 1. "CONF8,External Interrupt 2 Configuration 8"
line.long 0xC "EINT3CONF2,External Interrupt 3 Configuration Register 2"
hexmask.long.byte 0xC 12.--15. 1. "CONF11,External Interrupt 3 Configuration 11"
hexmask.long.byte 0xC 8.--11. 1. "CONF10,External Interrupt 3 Configuration 10"
newline
hexmask.long.byte 0xC 4.--7. 1. "CONF9,External Interrupt 3 Configuration 9"
hexmask.long.byte 0xC 0.--3. 1. "CONF8,External Interrupt 3 Configuration 8"
endif
group.long 0x400++0x3
line.long 0x0 "MSK,Interrupt Source Mask Register"
bitfld.long 0x0 31. "IMSK31_NULL,Interrupt Source Mask 31 (RSVD)" "0: Mask Interrupt Source,1: Unmask Interrupt Source"
bitfld.long 0x0 30. "IMSK30_NULL,Interrupt Source Mask 30 (RSVD)" "0: Mask Interrupt Source,1: Unmask Interrupt Source"
newline
bitfld.long 0x0 29. "IMSK29_NULL,Interrupt Source Mask 29 (RSVD)" "0: Mask Interrupt Source,1: Unmask Interrupt Source"
bitfld.long 0x0 28. "IMSK28_NULL,Interrupt Source Mask 28 (RSVD)" "0: Mask Interrupt Source,1: Unmask Interrupt Source"
newline
sif (cpuis("A31G12?*"))
bitfld.long 0x0 27. "IMSK27_USART13,Interrupt Source Mask 27 (USART13)" "0: Mask Interrupt Source,1: Unmask Interrupt Source"
endif
sif (cpuis("A31G11?*"))
bitfld.long 0x0 27. "IMSK27_NULL,Interrupt Source Mask 27 (RSVD)" "0: Mask Interrupt Source,1: Unmask Interrupt Source"
newline
bitfld.long 0x0 26. "IMSK26_NULL,Interrupt Source Mask 26 (RSVD)" "0: Mask Interrupt Source,1: Unmask Interrupt Source"
bitfld.long 0x0 25. "IMSK25_NULL,Interrupt Source Mask 25 (RSVD)" "0: Mask Interrupt Source,1: Unmask Interrupt Source"
newline
bitfld.long 0x0 24. "IMSK24_NULL,Interrupt Source Mask 24 (RSVD)" "0: Mask Interrupt Source,1: Unmask Interrupt Source"
bitfld.long 0x0 23. "IMSK23_NULL,Interrupt Source Mask 23 (RSVD)" "0: Mask Interrupt Source,1: Unmask Interrupt Source"
newline
bitfld.long 0x0 22. "IMSK22_NULL,Interrupt Source Mask 22 (RSVD)" "0: Mask Interrupt Source,1: Unmask Interrupt Source"
bitfld.long 0x0 21. "IMSK21_NULL,Interrupt Source Mask 21 (RSVD)" "0: Mask Interrupt Source,1: Unmask Interrupt Source"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 26. "IMSK26_USART12,Interrupt Source Mask 26 (USART12)" "0: Mask Interrupt Source,1: Unmask Interrupt Source"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 25. "IMSK25_I2C2,Interrupt Source Mask 25 (I2C2)" "0: Mask Interrupt Source,1: Unmask Interrupt Source"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 24. "IMSK24_TIMER16,Interrupt Source Mask 24 (TIMER16)" "0: Mask Interrupt Source,1: Unmask Interrupt Source"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 23. "IMSK23_TIMER15,Interrupt Source Mask 23 (TIMER15)" "0: Mask Interrupt Source,1: Unmask Interrupt Source"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 22. "IMSK22_TIMER14,Interrupt Source Mask 22 (TIMER14)" "0: Mask Interrupt Source,1: Unmask Interrupt Source"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 21. "IMSK21_TIMER13,Interrupt Source Mask 21 (TIMER13)" "0: Mask Interrupt Source,1: Unmask Interrupt Source"
newline
endif
bitfld.long 0x0 20. "IMSK20_UART1,Interrupt Source Mask 20 (UART1)" "0: Mask Interrupt Source,1: Unmask Interrupt Source"
bitfld.long 0x0 19. "IMSK19_UART0,Interrupt Source Mask 19 (UART0)" "0: Mask Interrupt Source,1: Unmask Interrupt Source"
newline
bitfld.long 0x0 18. "IMSK18_ADC,Interrupt Source Mask 18 (ADC)" "0: Mask Interrupt Source,1: Unmask Interrupt Source"
bitfld.long 0x0 17. "IMSK17_USART11,Interrupt Source Mask 17 (USART11)" "0: Mask Interrupt Source,1: Unmask Interrupt Source"
newline
bitfld.long 0x0 16. "IMSK16_TIMER21,Interrupt Source Mask 16 (TIMER21)" "0: Mask Interrupt Source,1: Unmask Interrupt Source"
bitfld.long 0x0 15. "IMSK15_TIMER20,Interrupt Source Mask 15 (TIMER20)" "0: Mask Interrupt Source,1: Unmask Interrupt Source"
newline
bitfld.long 0x0 14. "IMSK14_I2C1,Interrupt Source Mask 14 (I2C1)" "0: Mask Interrupt Source,1: Unmask Interrupt Source"
bitfld.long 0x0 13. "IMSK13_TIMER30,Interrupt Source Mask 13 (TIMER30)" "0: Mask Interrupt Source,1: Unmask Interrupt Source"
newline
bitfld.long 0x0 12. "IMSK12_WT,Interrupt Source Mask 12 (WT)" "0: Mask Interrupt Source,1: Unmask Interrupt Source"
bitfld.long 0x0 11. "IMSK11_USART10,Interrupt Source Mask 11 (USART10)" "0: Mask Interrupt Source,1: Unmask Interrupt Source"
newline
bitfld.long 0x0 10. "IMSK10_I2C0,Interrupt Source Mask 10 (I2C0)" "0: Mask Interrupt Source,1: Unmask Interrupt Source"
bitfld.long 0x0 9. "IMSK9_TIMER12,Interrupt Source Mask 9 (TIMER12)" "0: Mask Interrupt Source,1: Unmask Interrupt Source"
newline
bitfld.long 0x0 8. "IMSK8_TIMER11,Interrupt Source Mask 8 (TIMER11)" "0: Mask Interrupt Source,1: Unmask Interrupt Source"
bitfld.long 0x0 7. "IMSK7_TIMER10,Interrupt Source Mask 7 (TIMER10)" "0: Mask Interrupt Source,1: Unmask Interrupt Source"
newline
bitfld.long 0x0 6. "IMSK6_EINT3,Interrupt Source Mask 6 (EINT3)" "0: Mask Interrupt Source,1: Unmask Interrupt Source"
bitfld.long 0x0 5. "IMSK5_EINT2,Interrupt Source Mask 5 (EINT2)" "0: Mask Interrupt Source,1: Unmask Interrupt Source"
newline
bitfld.long 0x0 4. "IMSK4_EINT1,Interrupt Source Mask 4 (EINT1)" "0: Mask Interrupt Source,1: Unmask Interrupt Source"
bitfld.long 0x0 3. "IMSK3_EINT0,Interrupt Source Mask 3 (EINT0)" "0: Mask Interrupt Source,1: Unmask Interrupt Source"
newline
bitfld.long 0x0 2. "IMSK2_WDT,Interrupt Source Mask 2 (WDT)" "0: Mask Interrupt Source,1: Unmask Interrupt Source"
bitfld.long 0x0 1. "IMSK1_WUT,Interrupt Source Mask 1 (WUT)" "0: Mask Interrupt Source,1: Unmask Interrupt Source"
newline
bitfld.long 0x0 0. "IMSK0_LVI,Interrupt Source Mask 0 (LVI)" "0: Mask Interrupt Source,1: Unmask Interrupt Source"
tree.end
tree "LCD (LCD Driver)"
base ad:0x40005000
group.long 0x0++0x7
line.long 0x0 "CR,LCD Driver Control Register"
bitfld.long 0x0 6.--7. "IRSEL,Internal LCD Bias Dividing Resistor Selection" "0: RLCD3: 105/105/80[kohm] @(1/2)/(1/3)/(1/4) bias,1: RLCD1: 10/10/10[kohm] @(1/2)/(1/3)/(1/4) bias,2: RLCD2: 66/66/50[kohm] @(1/2)/(1/3)/(1/4) bias,3: RLCD4: 320/320/240[kohm] @(1/2)/(1/3)/(1/4) bias"
bitfld.long 0x0 3.--5. "DBS,LCD Duty and Bias Selection" "0: 1/8 duty 1/4 bias,1: 1/6 duty 1/4 bias,2: 1/5 duty 1/3 bias,3: 1/4 duty 1/3 bias,4: 1/3 duty 1/3 bias,5: 1/3 duty 1/2 bias,?,?"
bitfld.long 0x0 1.--2. "LCLK,LCD Clock Selection (When fLCD = 32.768kHz)" "0: 128Hz,1: 256Hz,2: 512Hz,3: 1024Hz"
newline
bitfld.long 0x0 0. "DISP,LCD Display Control" "0: Display off,1: Normal display on"
line.long 0x4 "BCCR,LCD Automatic Bias and Contrast Control Register"
bitfld.long 0x4 12. "LCDABC,LCD Automatic Bias Control" "0: LCD automatic bias is off,1: LCD automatic bias is on"
bitfld.long 0x4 8.--10. "BMSEL,'Bias Mode A' Time Selection" "0: 'Bias Mode A' for 1-clock of fLCD,1: 'Bias Mode A' for 2-clock of fLCD,2: 'Bias Mode A' for 3-clock of fLCD,3: 'Bias Mode A' for 4-clock of fLCD,4: 'Bias Mode A' for 5-clock of fLCD,5: 'Bias Mode A' for 6-clock of fLCD,6: 'Bias Mode A' for 7-clock of fLCD,7: 'Bias Mode A' for 8-clock of fLCD"
bitfld.long 0x4 5. "LCTEN,LCD Driver Contrast Control" "0: Disable LCD driver contrast.,1: Enable LCD driver contrast."
newline
hexmask.long.byte 0x4 0.--3. 1. "VLCD,VLC0 Voltage Control when the contrast is enabled"
group.byte 0x10++0x1B
line.byte 0x0 "DR0,LCD Display Data Register 0"
line.byte 0x1 "DR1,LCD Display Data Register 1"
line.byte 0x2 "DR2,LCD Display Data Register 2"
line.byte 0x3 "DR3,LCD Display Data Register 3"
line.byte 0x4 "DR4,LCD Display Data Register 4"
line.byte 0x5 "DR5,LCD Display Data Register 5"
line.byte 0x6 "DR6,LCD Display Data Register 6"
line.byte 0x7 "DR7,LCD Display Data Register 7"
line.byte 0x8 "DR8,LCD Display Data Register 8"
line.byte 0x9 "DR9,LCD Display Data Register 9"
line.byte 0xA "DR10,LCD Display Data Register 10"
line.byte 0xB "DR11,LCD Display Data Register 11"
line.byte 0xC "DR12,LCD Display Data Register 12"
line.byte 0xD "DR13,LCD Display Data Register 13"
line.byte 0xE "DR14,LCD Display Data Register 14"
line.byte 0xF "DR15,LCD Display Data Register 15"
line.byte 0x10 "DR16,LCD Display Data Register 16"
line.byte 0x11 "DR17,LCD Display Data Register 17"
line.byte 0x12 "DR18,LCD Display Data Register 18"
line.byte 0x13 "DR19,LCD Display Data Register 19"
line.byte 0x14 "DR20,LCD Display Data Register 20"
line.byte 0x15 "DR21,LCD Display Data Register 21"
line.byte 0x16 "DR22,LCD Display Data Register 22"
line.byte 0x17 "DR23,LCD Display Data Register 23"
line.byte 0x18 "DR24,LCD Display Data Register 24"
line.byte 0x19 "DR25,LCD Display Data Register 25"
line.byte 0x1A "DR26,LCD Display Data Register 26"
line.byte 0x1B "DR27,LCD Display Data Register 27"
sif (cpuis("A31G12?*"))
group.byte 0x2C++0xF
line.byte 0x0 "DR28,LCD Display Data Register 28"
line.byte 0x1 "DR29,LCD Display Data Register 29"
line.byte 0x2 "DR30,LCD Display Data Register 30"
line.byte 0x3 "DR31,LCD Display Data Register 31"
line.byte 0x4 "DR32,LCD Display Data Register 32"
line.byte 0x5 "DR33,LCD Display Data Register 33"
line.byte 0x6 "DR34,LCD Display Data Register 34"
line.byte 0x7 "DR35,LCD Display Data Register 35"
line.byte 0x8 "DR36,LCD Display Data Register 36"
line.byte 0x9 "DR37,LCD Display Data Register 37"
line.byte 0xA "DR38,LCD Display Data Register 38"
line.byte 0xB "DR39,LCD Display Data Register 39"
line.byte 0xC "DR40,LCD Display Data Register 40"
line.byte 0xD "DR41,LCD Display Data Register 41"
line.byte 0xE "DR42,LCD Display Data Register 42"
line.byte 0xF "DR43,LCD Display Data Register 43"
endif
tree.end
tree "PCU&GPIO (Port Control Unit & General Purpose I/O)"
base ad:0x0
tree "PA"
base ad:0x30000000
group.long 0x0++0xB
line.long 0x0 "MOD,Port n Mode Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 30.--31. "MODE15,Port n Mode Selection 15" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 28.--29. "MODE14,Port n Mode Selection 14" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 26.--27. "MODE13,Port n Mode Selection 13" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 24.--25. "MODE12,Port n Mode Selection 12" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 22.--23. "MODE11,Port n Mode Selection 11" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 20.--21. "MODE10,Port n Mode Selection 10" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 18.--19. "MODE9,Port n Mode Selection 9" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 16.--17. "MODE8,Port n Mode Selection 8" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
endif
bitfld.long 0x0 14.--15. "MODE7,Port n Mode Selection 7" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
bitfld.long 0x0 12.--13. "MODE6,Port n Mode Selection 6" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
bitfld.long 0x0 10.--11. "MODE5,Port n Mode Selection 5" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
bitfld.long 0x0 8.--9. "MODE4,Port n Mode Selection 4" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
bitfld.long 0x0 6.--7. "MODE3,Port n Mode Selection 3" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
bitfld.long 0x0 4.--5. "MODE2,Port n Mode Selection 2" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
bitfld.long 0x0 2.--3. "MODE1,Port n Mode Selection 1" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
bitfld.long 0x0 0.--1. "MODE0,Port n Mode Selection 0" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
line.long 0x4 "TYP,Port n Output Type Selection Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x4 15. "TYP15,Port n Output Type Selection 15" "0: Push-Pull Output,1: Open-Drain Output"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 14. "TYP14,Port n Output Type Selection 14" "0: Push-Pull Output,1: Open-Drain Output"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 13. "TYP13,Port n Output Type Selection 13" "0: Push-Pull Output,1: Open-Drain Output"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 12. "TYP12,Port n Output Type Selection 12" "0: Push-Pull Output,1: Open-Drain Output"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 11. "TYP11,Port n Output Type Selection 11" "0: Push-Pull Output,1: Open-Drain Output"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 10. "TYP10,Port n Output Type Selection 10" "0: Push-Pull Output,1: Open-Drain Output"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 9. "TYP9,Port n Output Type Selection 9" "0: Push-Pull Output,1: Open-Drain Output"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 8. "TYP8,Port n Output Type Selection 8" "0: Push-Pull Output,1: Open-Drain Output"
newline
endif
bitfld.long 0x4 7. "TYP7,Port n Output Type Selection 7" "0: Push-Pull Output,1: Open-Drain Output"
bitfld.long 0x4 6. "TYP6,Port n Output Type Selection 6" "0: Push-Pull Output,1: Open-Drain Output"
newline
bitfld.long 0x4 5. "TYP5,Port n Output Type Selection 5" "0: Push-Pull Output,1: Open-Drain Output"
bitfld.long 0x4 4. "TYP4,Port n Output Type Selection 4" "0: Push-Pull Output,1: Open-Drain Output"
newline
bitfld.long 0x4 3. "TYP3,Port n Output Type Selection 3" "0: Push-Pull Output,1: Open-Drain Output"
bitfld.long 0x4 2. "TYP2,Port n Output Type Selection 2" "0: Push-Pull Output,1: Open-Drain Output"
newline
bitfld.long 0x4 1. "TYP1,Port n Output Type Selection 1" "0: Push-Pull Output,1: Open-Drain Output"
bitfld.long 0x4 0. "TYP0,Port n Output Type Selection 0" "0: Push-Pull Output,1: Open-Drain Output"
line.long 0x8 "AFSR1,Port n Alternative Function Selection Register 1"
hexmask.long.byte 0x8 28.--31. 1. "AFSR7,Port n Alternative Function Selection 7"
hexmask.long.byte 0x8 24.--27. 1. "AFSR6,Port n Alternative Function Selection 6"
newline
hexmask.long.byte 0x8 20.--23. 1. "AFSR5,Port n Alternative Function Selection 5"
hexmask.long.byte 0x8 16.--19. 1. "AFSR4,Port n Alternative Function Selection 4"
newline
hexmask.long.byte 0x8 12.--15. 1. "AFSR3,Port n Alternative Function Selection 3"
hexmask.long.byte 0x8 8.--11. 1. "AFSR2,Port n Alternative Function Selection 2"
newline
hexmask.long.byte 0x8 4.--7. 1. "AFSR1,Port n Alternative Function Selection 1"
hexmask.long.byte 0x8 0.--3. 1. "AFSR0,Port n Alternative Function Selection 0"
sif (cpuis("A31G12?*"))
group.long 0xC++0x3
line.long 0x0 "AFSR2,Port n Alternative Function Selection Register 2"
hexmask.long.byte 0x0 28.--31. 1. "AFSR15,Port n Alternative Function Selection 15"
hexmask.long.byte 0x0 24.--27. 1. "AFSR14,Port n Alternative Function Selection 14"
newline
hexmask.long.byte 0x0 20.--23. 1. "AFSR13,Port n Alternative Function Selection 13"
hexmask.long.byte 0x0 16.--19. 1. "AFSR12,Port n Alternative Function Selection 12"
newline
hexmask.long.byte 0x0 12.--15. 1. "AFSR11,Port n Alternative Function Selection 11"
hexmask.long.byte 0x0 8.--11. 1. "AFSR10,Port n Alternative Function Selection 10"
newline
hexmask.long.byte 0x0 4.--7. 1. "AFSR9,Port n Alternative Function Selection 9"
hexmask.long.byte 0x0 0.--3. 1. "AFSR8,Port n Alternative Function Selection 8"
endif
sif (cpuis("A31G12?*"))
group.long 0xC++0x3
line.long 0x0 "PA_AFSR2,Port n Alternative Function Selection Register 2"
hexmask.long.byte 0x0 12.--15. 1. "AFSR11,Port n Alternative Function Selection 11"
hexmask.long.byte 0x0 8.--11. 1. "AFSR10,Port n Alternative Function Selection 10"
newline
hexmask.long.byte 0x0 4.--7. 1. "AFSR9,Port n Alternative Function Selection 9"
hexmask.long.byte 0x0 0.--3. 1. "AFSR8,Port n Alternative Function Selection 8"
endif
group.long 0x10++0x3
line.long 0x0 "PUPD,Port n Pull-Up/Down Selection Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 30.--31. "PUPD15,Port n Pull-Up/Down Resistor Selection 15" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 28.--29. "PUPD14,Port n Pull-Up/Down Resistor Selection 14" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 26.--27. "PUPD13,Port n Pull-Up/Down Resistor Selection 13" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 24.--25. "PUPD12,Port n Pull-Up/Down Resistor Selection 12" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 22.--23. "PUPD11,Port n Pull-Up/Down Resistor Selection 11" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 20.--21. "PUPD10,Port n Pull-Up/Down Resistor Selection 10" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 18.--19. "PUPD9,Port n Pull-Up/Down Resistor Selection 9" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 16.--17. "PUPD8,Port n Pull-Up/Down Resistor Selection 8" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
endif
bitfld.long 0x0 14.--15. "PUPD7,Port n Pull-Up/Down Resistor Selection 7" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
bitfld.long 0x0 12.--13. "PUPD6,Port n Pull-Up/Down Resistor Selection 6" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
bitfld.long 0x0 10.--11. "PUPD5,Port n Pull-Up/Down Resistor Selection 5" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
bitfld.long 0x0 8.--9. "PUPD4,Port n Pull-Up/Down Resistor Selection 4" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
bitfld.long 0x0 6.--7. "PUPD3,Port n Pull-Up/Down Resistor Selection 3" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
bitfld.long 0x0 4.--5. "PUPD2,Port n Pull-Up/Down Resistor Selection 2" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
bitfld.long 0x0 2.--3. "PUPD1,Port n Pull-Up/Down Resistor Selection 1" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
bitfld.long 0x0 0.--1. "PUPD0,Port n Pull-Up/Down Resistor Selection 0" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
rgroup.long 0x14++0x3
line.long 0x0 "INDR,Port n Input Data Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 15. "INDR15,Port n Input Data 15" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 14. "INDR14,Port n Input Data 14" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 13. "INDR13,Port n Input Data 13" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12. "INDR12,Port n Input Data 12" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "INDR11,Port n Input Data 11" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "INDR10,Port n Input Data 10" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "INDR9,Port n Input Data 9" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "INDR8,Port n Input Data 8" "0,1"
newline
endif
bitfld.long 0x0 7. "INDR7,Port n Input Data 7" "0,1"
bitfld.long 0x0 6. "INDR6,Port n Input Data 6" "0,1"
newline
bitfld.long 0x0 5. "INDR5,Port n Input Data 5" "0,1"
bitfld.long 0x0 4. "INDR4,Port n Input Data 4" "0,1"
newline
bitfld.long 0x0 3. "INDR3,Port n Input Data 3" "0,1"
bitfld.long 0x0 2. "INDR2,Port n Input Data 2" "0,1"
newline
bitfld.long 0x0 1. "INDR1,Port n Input Data 1" "0,1"
bitfld.long 0x0 0. "INDR0,Port n Input Data 0" "0,1"
group.long 0x18++0x3
line.long 0x0 "OUTDR,Port n Output Data Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 15. "OUTDR15,Port n Output Data 15" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 14. "OUTDR14,Port n Output Data 14" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 13. "OUTDR13,Port n Output Data 13" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12. "OUTDR12,Port n Output Data 12" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "OUTDR11,Port n Output Data 11" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "OUTDR10,Port n Output Data 10" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "OUTDR9,Port n Output Data 9" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "OUTDR8,Port n Output Data 8" "0,1"
newline
endif
bitfld.long 0x0 7. "OUTDR7,Port n Output Data 7" "0,1"
bitfld.long 0x0 6. "OUTDR6,Port n Output Data 6" "0,1"
newline
bitfld.long 0x0 5. "OUTDR5,Port n Output Data 5" "0,1"
bitfld.long 0x0 4. "OUTDR4,Port n Output Data 4" "0,1"
newline
bitfld.long 0x0 3. "OUTDR3,Port n Output Data 3" "0,1"
bitfld.long 0x0 2. "OUTDR2,Port n Output Data 2" "0,1"
newline
bitfld.long 0x0 1. "OUTDR1,Port n Output Data 1" "0,1"
bitfld.long 0x0 0. "OUTDR0,Port n Output Data 0" "0,1"
wgroup.long 0x1C++0x7
line.long 0x0 "BSR,Port n Output Bit Set Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 15. "BSR15,Port n Output Bit Set 15" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 14. "BSR14,Port n Output Bit Set 14" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 13. "BSR13,Port n Output Bit Set 13" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12. "BSR12,Port n Output Bit Set 12" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "BSR11,Port n Output Bit Set 11" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "BSR10,Port n Output Bit Set 10" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "BSR9,Port n Output Bit Set 9" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "BSR8,Port n Output Bit Set 8" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
endif
bitfld.long 0x0 7. "BSR7,Port n Output Bit Set 7" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
bitfld.long 0x0 6. "BSR6,Port n Output Bit Set 6" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
bitfld.long 0x0 5. "BSR5,Port n Output Bit Set 5" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
bitfld.long 0x0 4. "BSR4,Port n Output Bit Set 4" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
bitfld.long 0x0 3. "BSR3,Port n Output Bit Set 3" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
bitfld.long 0x0 2. "BSR2,Port n Output Bit Set 2" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
bitfld.long 0x0 1. "BSR1,Port n Output Bit Set 1" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
bitfld.long 0x0 0. "BSR0,Port n Output Bit Set 0" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
line.long 0x4 "BCR,Port n Output Bit Clear Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x4 15. "BCR15,Port n Output Bit Clear 15" "0: No effect.,1: Clear the corresponding OUTDRx bit."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 14. "BCR14,Port n Output Bit Clear 14" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 13. "BCR13,Port n Output Bit Clear 13" "0: No effect.,1: Clear the corresponding OUTDRx bit."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 12. "BCR12,Port n Output Bit Clear 12" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 11. "BCR11,Port n Output Bit Clear 11" "0: No effect.,1: Clear the corresponding OUTDRx bit."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 10. "BCR10,Port n Output Bit Clear 10" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 9. "BCR9,Port n Output Bit Clear 9" "0: No effect.,1: Clear the corresponding OUTDRx bit."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 8. "BCR8,Port n Output Bit Clear 8" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
endif
bitfld.long 0x4 7. "BCR7,Port n Output Bit Clear 7" "0: No effect.,1: Clear the corresponding OUTDRx bit."
bitfld.long 0x4 6. "BCR6,Port n Output Bit Clear 6" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
bitfld.long 0x4 5. "BCR5,Port n Output Bit Clear 5" "0: No effect.,1: Clear the corresponding OUTDRx bit."
bitfld.long 0x4 4. "BCR4,Port n Output Bit Clear 4" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
bitfld.long 0x4 3. "BCR3,Port n Output Bit Clear 3" "0: No effect.,1: Clear the corresponding OUTDRx bit."
bitfld.long 0x4 2. "BCR2,Port n Output Bit Clear 2" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
bitfld.long 0x4 1. "BCR1,Port n Output Bit Clear 1" "0: No effect.,1: Clear the corresponding OUTDRx bit."
bitfld.long 0x4 0. "BCR0,Port n Output Bit Clear 0" "0: No effect.,1: Clear the corresponding OUTDRx bit."
group.long 0x24++0x7
line.long 0x0 "OUTDMSK,Port n Output Data Mask Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 15. "OUTDMSK15,Port n Output Data Mask 15" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 14. "OUTDMSK14,Port n Output Data Mask 14" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 13. "OUTDMSK13,Port n Output Data Mask 13" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12. "OUTDMSK12,Port n Output Data Mask 12" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "OUTDMSK11,Port n Output Data Mask 11" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "OUTDMSK10,Port n Output Data Mask 10" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "OUTDMSK9,Port n Output Data Mask 9" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "OUTDMSK8,Port n Output Data Mask 8" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
endif
bitfld.long 0x0 7. "OUTDMSK7,Port n Output Data Mask 7" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
bitfld.long 0x0 6. "OUTDMSK6,Port n Output Data Mask 6" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
bitfld.long 0x0 5. "OUTDMSK5,Port n Output Data Mask 5" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
bitfld.long 0x0 4. "OUTDMSK4,Port n Output Data Mask 4" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
bitfld.long 0x0 3. "OUTDMSK3,Port n Output Data Mask 3" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
bitfld.long 0x0 2. "OUTDMSK2,Port n Output Data Mask 2" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
bitfld.long 0x0 1. "OUTDMSK1,Port n Output Data Mask 1" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
bitfld.long 0x0 0. "OUTDMSK0,Port n Output Data Mask 0" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
line.long 0x4 "DBCR,Port n Debounce Control Register"
bitfld.long 0x4 16.--18. "DBCLK,Port n Debounce Filter Sampling Clock Selection" "0: HCLK/1,1: HCLK/4,2: HCLK/16,3: HCLK/64,4: HCLK/256,5: HCLK/1024,?,?"
sif (cpuis("A31G12?*"))
bitfld.long 0x4 11. "DBEN11,Port n Debounce Enable 11" "0: Disable debounce filter.,1: Enable debounce filter."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 10. "DBEN10,Port n Debounce Enable 10" "0: Disable debounce filter.,1: Enable debounce filter."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 9. "DBEN9,Port n Debounce Enable 9" "0: Disable debounce filter.,1: Enable debounce filter."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 8. "DBEN8,Port n Debounce Enable 8" "0: Disable debounce filter.,1: Enable debounce filter."
endif
bitfld.long 0x4 7. "DBEN7,Port n Debounce Enable 7" "0: Disable debounce filter.,1: Enable debounce filter."
newline
bitfld.long 0x4 6. "DBEN6,Port n Debounce Enable 6" "0: Disable debounce filter.,1: Enable debounce filter."
bitfld.long 0x4 5. "DBEN5,Port n Debounce Enable 5" "0: Disable debounce filter.,1: Enable debounce filter."
newline
bitfld.long 0x4 4. "DBEN4,Port n Debounce Enable 4" "0: Disable debounce filter.,1: Enable debounce filter."
bitfld.long 0x4 3. "DBEN3,Port n Debounce Enable 3" "0: Disable debounce filter.,1: Enable debounce filter."
newline
bitfld.long 0x4 2. "DBEN2,Port n Debounce Enable 2" "0: Disable debounce filter.,1: Enable debounce filter."
bitfld.long 0x4 1. "DBEN1,Port n Debounce Enable 1" "0: Disable debounce filter.,1: Enable debounce filter."
newline
bitfld.long 0x4 0. "DBEN0,Port n Debounce Enable 0" "0: Disable debounce filter.,1: Enable debounce filter."
group.long 0x0++0xB
line.long 0x0 "PA_MOD,Port n Mode Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 22.--23. "MODE11,Port n Mode Selection 11" "0,1,2,3"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 20.--21. "MODE10,Port n Mode Selection 10" "0,1,2,3"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 18.--19. "MODE9,Port n Mode Selection 9" "0,1,2,3"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 16.--17. "MODE8,Port n Mode Selection 8" "0,1,2,3"
newline
endif
bitfld.long 0x0 14.--15. "MODE7,Port n Mode Selection 7" "0,1,2,3"
bitfld.long 0x0 12.--13. "MODE6,Port n Mode Selection 6" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "MODE5,Port n Mode Selection 5" "0,1,2,3"
bitfld.long 0x0 8.--9. "MODE4,Port n Mode Selection 4" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "MODE3,Port n Mode Selection 3" "0,1,2,3"
bitfld.long 0x0 4.--5. "MODE2,Port n Mode Selection 2" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "MODE1,Port n Mode Selection 1" "0,1,2,3"
bitfld.long 0x0 0.--1. "MODE0,Port n Mode Selection 0" "0,1,2,3"
line.long 0x4 "PA_TYP,Port n Output Type Selection Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x4 11. "TYP11,Port n Output Type Selection 11" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 10. "TYP10,Port n Output Type Selection 10" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 9. "TYP9,Port n Output Type Selection 9" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 8. "TYP8,Port n Output Type Selection 8" "0,1"
newline
endif
bitfld.long 0x4 7. "TYP7,Port n Output Type Selection 7" "0,1"
bitfld.long 0x4 6. "TYP6,Port n Output Type Selection 6" "0,1"
newline
bitfld.long 0x4 5. "TYP5,Port n Output Type Selection 5" "0,1"
bitfld.long 0x4 4. "TYP4,Port n Output Type Selection 4" "0,1"
newline
bitfld.long 0x4 3. "TYP3,Port n Output Type Selection 3" "0,1"
bitfld.long 0x4 2. "TYP2,Port n Output Type Selection 2" "0,1"
newline
bitfld.long 0x4 1. "TYP1,Port n Output Type Selection 1" "0,1"
bitfld.long 0x4 0. "TYP0,Port n Output Type Selection 0" "0,1"
line.long 0x8 "PA_AFSR1,Port n Alternative Function Selection Register 1"
hexmask.long.byte 0x8 28.--31. 1. "AFSR7,Port n Alternative Function Selection 7"
hexmask.long.byte 0x8 24.--27. 1. "AFSR6,Port n Alternative Function Selection 6"
newline
hexmask.long.byte 0x8 20.--23. 1. "AFSR5,Port n Alternative Function Selection 5"
hexmask.long.byte 0x8 16.--19. 1. "AFSR4,Port n Alternative Function Selection 4"
newline
hexmask.long.byte 0x8 12.--15. 1. "AFSR3,Port n Alternative Function Selection 3"
hexmask.long.byte 0x8 8.--11. 1. "AFSR2,Port n Alternative Function Selection 2"
newline
hexmask.long.byte 0x8 4.--7. 1. "AFSR1,Port n Alternative Function Selection 1"
hexmask.long.byte 0x8 0.--3. 1. "AFSR0,Port n Alternative Function Selection 0"
group.long 0x10++0x3
line.long 0x0 "PA_PUPD,Port n Pull-Up/Down Selection Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 22.--23. "PUPD11,Port n Pull-Up/Down Resistor Selection 11" "0,1,2,3"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 20.--21. "PUPD10,Port n Pull-Up/Down Resistor Selection 10" "0,1,2,3"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 18.--19. "PUPD9,Port n Pull-Up/Down Resistor Selection 9" "0,1,2,3"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 16.--17. "PUPD8,Port n Pull-Up/Down Resistor Selection 8" "0,1,2,3"
newline
endif
bitfld.long 0x0 14.--15. "PUPD7,Port n Pull-Up/Down Resistor Selection 7" "0,1,2,3"
bitfld.long 0x0 12.--13. "PUPD6,Port n Pull-Up/Down Resistor Selection 6" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "PUPD5,Port n Pull-Up/Down Resistor Selection 5" "0,1,2,3"
bitfld.long 0x0 8.--9. "PUPD4,Port n Pull-Up/Down Resistor Selection 4" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "PUPD3,Port n Pull-Up/Down Resistor Selection 3" "0,1,2,3"
bitfld.long 0x0 4.--5. "PUPD2,Port n Pull-Up/Down Resistor Selection 2" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "PUPD1,Port n Pull-Up/Down Resistor Selection 1" "0,1,2,3"
bitfld.long 0x0 0.--1. "PUPD0,Port n Pull-Up/Down Resistor Selection 0" "0,1,2,3"
rgroup.long 0x14++0x3
line.long 0x0 "PA_INDR,Port n Input Data Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "INDR11,Port n Input Data 11" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "INDR10,Port n Input Data 10" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "INDR9,Port n Input Data 9" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "INDR8,Port n Input Data 8" "0,1"
newline
endif
bitfld.long 0x0 7. "INDR7,Port n Input Data 7" "0,1"
bitfld.long 0x0 6. "INDR6,Port n Input Data 6" "0,1"
newline
bitfld.long 0x0 5. "INDR5,Port n Input Data 5" "0,1"
bitfld.long 0x0 4. "INDR4,Port n Input Data 4" "0,1"
newline
bitfld.long 0x0 3. "INDR3,Port n Input Data 3" "0,1"
bitfld.long 0x0 2. "INDR2,Port n Input Data 2" "0,1"
newline
bitfld.long 0x0 1. "INDR1,Port n Input Data 1" "0,1"
bitfld.long 0x0 0. "INDR0,Port n Input Data 0" "0,1"
group.long 0x18++0x3
line.long 0x0 "PA_OUTDR,Port n Output Data Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "OUTDR11,Port n Output Data 11" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "OUTDR10,Port n Output Data 10" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "OUTDR9,Port n Output Data 9" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "OUTDR8,Port n Output Data 8" "0,1"
newline
endif
bitfld.long 0x0 7. "OUTDR7,Port n Output Data 7" "0,1"
bitfld.long 0x0 6. "OUTDR6,Port n Output Data 6" "0,1"
newline
bitfld.long 0x0 5. "OUTDR5,Port n Output Data 5" "0,1"
bitfld.long 0x0 4. "OUTDR4,Port n Output Data 4" "0,1"
newline
bitfld.long 0x0 3. "OUTDR3,Port n Output Data 3" "0,1"
bitfld.long 0x0 2. "OUTDR2,Port n Output Data 2" "0,1"
newline
bitfld.long 0x0 1. "OUTDR1,Port n Output Data 1" "0,1"
bitfld.long 0x0 0. "OUTDR0,Port n Output Data 0" "0,1"
wgroup.long 0x1C++0x7
line.long 0x0 "PA_BSR,Port n Output Bit Set Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "BSR11,Port n Output Bit Set 11" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "BSR10,Port n Output Bit Set 10" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "BSR9,Port n Output Bit Set 9" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "BSR8,Port n Output Bit Set 8" "0,1"
newline
endif
bitfld.long 0x0 7. "BSR7,Port n Output Bit Set 7" "0,1"
bitfld.long 0x0 6. "BSR6,Port n Output Bit Set 6" "0,1"
newline
bitfld.long 0x0 5. "BSR5,Port n Output Bit Set 5" "0,1"
bitfld.long 0x0 4. "BSR4,Port n Output Bit Set 4" "0,1"
newline
bitfld.long 0x0 3. "BSR3,Port n Output Bit Set 3" "0,1"
bitfld.long 0x0 2. "BSR2,Port n Output Bit Set 2" "0,1"
newline
bitfld.long 0x0 1. "BSR1,Port n Output Bit Set 1" "0,1"
bitfld.long 0x0 0. "BSR0,Port n Output Bit Set 0" "0,1"
line.long 0x4 "PA_BCR,Port n Output Bit Clear Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x4 11. "BCR11,Port n Output Bit Clear 11" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 10. "BCR10,Port n Output Bit Clear 10" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 9. "BCR9,Port n Output Bit Clear 9" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 8. "BCR8,Port n Output Bit Clear 8" "0,1"
newline
endif
bitfld.long 0x4 7. "BCR7,Port n Output Bit Clear 7" "0,1"
bitfld.long 0x4 6. "BCR6,Port n Output Bit Clear 6" "0,1"
newline
bitfld.long 0x4 5. "BCR5,Port n Output Bit Clear 5" "0,1"
bitfld.long 0x4 4. "BCR4,Port n Output Bit Clear 4" "0,1"
newline
bitfld.long 0x4 3. "BCR3,Port n Output Bit Clear 3" "0,1"
bitfld.long 0x4 2. "BCR2,Port n Output Bit Clear 2" "0,1"
newline
bitfld.long 0x4 1. "BCR1,Port n Output Bit Clear 1" "0,1"
bitfld.long 0x4 0. "BCR0,Port n Output Bit Clear 0" "0,1"
group.long 0x24++0x3
line.long 0x0 "PA_OUTDMSK,Port n Output Data Mask Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "OUTDMSK11,Port n Output Data Mask 11" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "OUTDMSK10,Port n Output Data Mask 10" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "OUTDMSK9,Port n Output Data Mask 9" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "OUTDMSK8,Port n Output Data Mask 8" "0,1"
newline
endif
bitfld.long 0x0 7. "OUTDMSK7,Port n Output Data Mask 7" "0,1"
bitfld.long 0x0 6. "OUTDMSK6,Port n Output Data Mask 6" "0,1"
newline
bitfld.long 0x0 5. "OUTDMSK5,Port n Output Data Mask 5" "0,1"
bitfld.long 0x0 4. "OUTDMSK4,Port n Output Data Mask 4" "0,1"
newline
bitfld.long 0x0 3. "OUTDMSK3,Port n Output Data Mask 3" "0,1"
bitfld.long 0x0 2. "OUTDMSK2,Port n Output Data Mask 2" "0,1"
newline
bitfld.long 0x0 1. "OUTDMSK1,Port n Output Data Mask 1" "0,1"
bitfld.long 0x0 0. "OUTDMSK0,Port n Output Data Mask 0" "0,1"
tree.end
tree "PB"
base ad:0x30000100
group.long 0x0++0xB
line.long 0x0 "MOD,Port n Mode Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 30.--31. "MODE15,Port n Mode Selection 15" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 28.--29. "MODE14,Port n Mode Selection 14" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 26.--27. "MODE13,Port n Mode Selection 13" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 24.--25. "MODE12,Port n Mode Selection 12" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 22.--23. "MODE11,Port n Mode Selection 11" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 20.--21. "MODE10,Port n Mode Selection 10" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 18.--19. "MODE9,Port n Mode Selection 9" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 16.--17. "MODE8,Port n Mode Selection 8" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
endif
bitfld.long 0x0 14.--15. "MODE7,Port n Mode Selection 7" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
bitfld.long 0x0 12.--13. "MODE6,Port n Mode Selection 6" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
bitfld.long 0x0 10.--11. "MODE5,Port n Mode Selection 5" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
bitfld.long 0x0 8.--9. "MODE4,Port n Mode Selection 4" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
bitfld.long 0x0 6.--7. "MODE3,Port n Mode Selection 3" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
bitfld.long 0x0 4.--5. "MODE2,Port n Mode Selection 2" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
bitfld.long 0x0 2.--3. "MODE1,Port n Mode Selection 1" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
bitfld.long 0x0 0.--1. "MODE0,Port n Mode Selection 0" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
line.long 0x4 "TYP,Port n Output Type Selection Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x4 15. "TYP15,Port n Output Type Selection 15" "0: Push-Pull Output,1: Open-Drain Output"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 14. "TYP14,Port n Output Type Selection 14" "0: Push-Pull Output,1: Open-Drain Output"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 13. "TYP13,Port n Output Type Selection 13" "0: Push-Pull Output,1: Open-Drain Output"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 12. "TYP12,Port n Output Type Selection 12" "0: Push-Pull Output,1: Open-Drain Output"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 11. "TYP11,Port n Output Type Selection 11" "0: Push-Pull Output,1: Open-Drain Output"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 10. "TYP10,Port n Output Type Selection 10" "0: Push-Pull Output,1: Open-Drain Output"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 9. "TYP9,Port n Output Type Selection 9" "0: Push-Pull Output,1: Open-Drain Output"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 8. "TYP8,Port n Output Type Selection 8" "0: Push-Pull Output,1: Open-Drain Output"
newline
endif
bitfld.long 0x4 7. "TYP7,Port n Output Type Selection 7" "0: Push-Pull Output,1: Open-Drain Output"
bitfld.long 0x4 6. "TYP6,Port n Output Type Selection 6" "0: Push-Pull Output,1: Open-Drain Output"
newline
bitfld.long 0x4 5. "TYP5,Port n Output Type Selection 5" "0: Push-Pull Output,1: Open-Drain Output"
bitfld.long 0x4 4. "TYP4,Port n Output Type Selection 4" "0: Push-Pull Output,1: Open-Drain Output"
newline
bitfld.long 0x4 3. "TYP3,Port n Output Type Selection 3" "0: Push-Pull Output,1: Open-Drain Output"
bitfld.long 0x4 2. "TYP2,Port n Output Type Selection 2" "0: Push-Pull Output,1: Open-Drain Output"
newline
bitfld.long 0x4 1. "TYP1,Port n Output Type Selection 1" "0: Push-Pull Output,1: Open-Drain Output"
bitfld.long 0x4 0. "TYP0,Port n Output Type Selection 0" "0: Push-Pull Output,1: Open-Drain Output"
line.long 0x8 "AFSR1,Port n Alternative Function Selection Register 1"
hexmask.long.byte 0x8 28.--31. 1. "AFSR7,Port n Alternative Function Selection 7"
hexmask.long.byte 0x8 24.--27. 1. "AFSR6,Port n Alternative Function Selection 6"
newline
hexmask.long.byte 0x8 20.--23. 1. "AFSR5,Port n Alternative Function Selection 5"
hexmask.long.byte 0x8 16.--19. 1. "AFSR4,Port n Alternative Function Selection 4"
newline
hexmask.long.byte 0x8 12.--15. 1. "AFSR3,Port n Alternative Function Selection 3"
hexmask.long.byte 0x8 8.--11. 1. "AFSR2,Port n Alternative Function Selection 2"
newline
hexmask.long.byte 0x8 4.--7. 1. "AFSR1,Port n Alternative Function Selection 1"
hexmask.long.byte 0x8 0.--3. 1. "AFSR0,Port n Alternative Function Selection 0"
sif (cpuis("A31G12?*"))
group.long 0xC++0x3
line.long 0x0 "AFSR2,Port n Alternative Function Selection Register 2"
hexmask.long.byte 0x0 28.--31. 1. "AFSR15,Port n Alternative Function Selection 15"
hexmask.long.byte 0x0 24.--27. 1. "AFSR14,Port n Alternative Function Selection 14"
newline
hexmask.long.byte 0x0 20.--23. 1. "AFSR13,Port n Alternative Function Selection 13"
hexmask.long.byte 0x0 16.--19. 1. "AFSR12,Port n Alternative Function Selection 12"
newline
hexmask.long.byte 0x0 12.--15. 1. "AFSR11,Port n Alternative Function Selection 11"
hexmask.long.byte 0x0 8.--11. 1. "AFSR10,Port n Alternative Function Selection 10"
newline
hexmask.long.byte 0x0 4.--7. 1. "AFSR9,Port n Alternative Function Selection 9"
hexmask.long.byte 0x0 0.--3. 1. "AFSR8,Port n Alternative Function Selection 8"
endif
sif (cpuis("A31G12?*"))
group.long 0xC++0x3
line.long 0x0 "PB_AFSR2,Port n Alternative Function Selection Register 2"
hexmask.long.byte 0x0 28.--31. 1. "AFSR15,Port n Alternative Function Selection 15"
hexmask.long.byte 0x0 24.--27. 1. "AFSR14,Port n Alternative Function Selection 14"
newline
hexmask.long.byte 0x0 20.--23. 1. "AFSR13,Port n Alternative Function Selection 13"
hexmask.long.byte 0x0 16.--19. 1. "AFSR12,Port n Alternative Function Selection 12"
newline
hexmask.long.byte 0x0 12.--15. 1. "AFSR11,Port n Alternative Function Selection 11"
hexmask.long.byte 0x0 8.--11. 1. "AFSR10,Port n Alternative Function Selection 10"
newline
hexmask.long.byte 0x0 4.--7. 1. "AFSR9,Port n Alternative Function Selection 9"
hexmask.long.byte 0x0 0.--3. 1. "AFSR8,Port n Alternative Function Selection 8"
endif
group.long 0x10++0x3
line.long 0x0 "PUPD,Port n Pull-Up/Down Selection Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 30.--31. "PUPD15,Port n Pull-Up/Down Resistor Selection 15" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 28.--29. "PUPD14,Port n Pull-Up/Down Resistor Selection 14" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 26.--27. "PUPD13,Port n Pull-Up/Down Resistor Selection 13" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 24.--25. "PUPD12,Port n Pull-Up/Down Resistor Selection 12" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 22.--23. "PUPD11,Port n Pull-Up/Down Resistor Selection 11" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 20.--21. "PUPD10,Port n Pull-Up/Down Resistor Selection 10" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 18.--19. "PUPD9,Port n Pull-Up/Down Resistor Selection 9" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 16.--17. "PUPD8,Port n Pull-Up/Down Resistor Selection 8" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
endif
bitfld.long 0x0 14.--15. "PUPD7,Port n Pull-Up/Down Resistor Selection 7" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
bitfld.long 0x0 12.--13. "PUPD6,Port n Pull-Up/Down Resistor Selection 6" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
bitfld.long 0x0 10.--11. "PUPD5,Port n Pull-Up/Down Resistor Selection 5" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
bitfld.long 0x0 8.--9. "PUPD4,Port n Pull-Up/Down Resistor Selection 4" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
bitfld.long 0x0 6.--7. "PUPD3,Port n Pull-Up/Down Resistor Selection 3" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
bitfld.long 0x0 4.--5. "PUPD2,Port n Pull-Up/Down Resistor Selection 2" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
bitfld.long 0x0 2.--3. "PUPD1,Port n Pull-Up/Down Resistor Selection 1" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
bitfld.long 0x0 0.--1. "PUPD0,Port n Pull-Up/Down Resistor Selection 0" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
rgroup.long 0x14++0x3
line.long 0x0 "INDR,Port n Input Data Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 15. "INDR15,Port n Input Data 15" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 14. "INDR14,Port n Input Data 14" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 13. "INDR13,Port n Input Data 13" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12. "INDR12,Port n Input Data 12" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "INDR11,Port n Input Data 11" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "INDR10,Port n Input Data 10" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "INDR9,Port n Input Data 9" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "INDR8,Port n Input Data 8" "0,1"
newline
endif
bitfld.long 0x0 7. "INDR7,Port n Input Data 7" "0,1"
bitfld.long 0x0 6. "INDR6,Port n Input Data 6" "0,1"
newline
bitfld.long 0x0 5. "INDR5,Port n Input Data 5" "0,1"
bitfld.long 0x0 4. "INDR4,Port n Input Data 4" "0,1"
newline
bitfld.long 0x0 3. "INDR3,Port n Input Data 3" "0,1"
bitfld.long 0x0 2. "INDR2,Port n Input Data 2" "0,1"
newline
bitfld.long 0x0 1. "INDR1,Port n Input Data 1" "0,1"
bitfld.long 0x0 0. "INDR0,Port n Input Data 0" "0,1"
group.long 0x18++0x3
line.long 0x0 "OUTDR,Port n Output Data Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 15. "OUTDR15,Port n Output Data 15" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 14. "OUTDR14,Port n Output Data 14" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 13. "OUTDR13,Port n Output Data 13" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12. "OUTDR12,Port n Output Data 12" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "OUTDR11,Port n Output Data 11" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "OUTDR10,Port n Output Data 10" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "OUTDR9,Port n Output Data 9" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "OUTDR8,Port n Output Data 8" "0,1"
newline
endif
bitfld.long 0x0 7. "OUTDR7,Port n Output Data 7" "0,1"
bitfld.long 0x0 6. "OUTDR6,Port n Output Data 6" "0,1"
newline
bitfld.long 0x0 5. "OUTDR5,Port n Output Data 5" "0,1"
bitfld.long 0x0 4. "OUTDR4,Port n Output Data 4" "0,1"
newline
bitfld.long 0x0 3. "OUTDR3,Port n Output Data 3" "0,1"
bitfld.long 0x0 2. "OUTDR2,Port n Output Data 2" "0,1"
newline
bitfld.long 0x0 1. "OUTDR1,Port n Output Data 1" "0,1"
bitfld.long 0x0 0. "OUTDR0,Port n Output Data 0" "0,1"
wgroup.long 0x1C++0x7
line.long 0x0 "BSR,Port n Output Bit Set Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 15. "BSR15,Port n Output Bit Set 15" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 14. "BSR14,Port n Output Bit Set 14" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 13. "BSR13,Port n Output Bit Set 13" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12. "BSR12,Port n Output Bit Set 12" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "BSR11,Port n Output Bit Set 11" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "BSR10,Port n Output Bit Set 10" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "BSR9,Port n Output Bit Set 9" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "BSR8,Port n Output Bit Set 8" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
endif
bitfld.long 0x0 7. "BSR7,Port n Output Bit Set 7" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
bitfld.long 0x0 6. "BSR6,Port n Output Bit Set 6" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
bitfld.long 0x0 5. "BSR5,Port n Output Bit Set 5" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
bitfld.long 0x0 4. "BSR4,Port n Output Bit Set 4" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
bitfld.long 0x0 3. "BSR3,Port n Output Bit Set 3" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
bitfld.long 0x0 2. "BSR2,Port n Output Bit Set 2" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
bitfld.long 0x0 1. "BSR1,Port n Output Bit Set 1" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
bitfld.long 0x0 0. "BSR0,Port n Output Bit Set 0" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
line.long 0x4 "BCR,Port n Output Bit Clear Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x4 15. "BCR15,Port n Output Bit Clear 15" "0: No effect.,1: Clear the corresponding OUTDRx bit."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 14. "BCR14,Port n Output Bit Clear 14" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 13. "BCR13,Port n Output Bit Clear 13" "0: No effect.,1: Clear the corresponding OUTDRx bit."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 12. "BCR12,Port n Output Bit Clear 12" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 11. "BCR11,Port n Output Bit Clear 11" "0: No effect.,1: Clear the corresponding OUTDRx bit."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 10. "BCR10,Port n Output Bit Clear 10" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 9. "BCR9,Port n Output Bit Clear 9" "0: No effect.,1: Clear the corresponding OUTDRx bit."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 8. "BCR8,Port n Output Bit Clear 8" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
endif
bitfld.long 0x4 7. "BCR7,Port n Output Bit Clear 7" "0: No effect.,1: Clear the corresponding OUTDRx bit."
bitfld.long 0x4 6. "BCR6,Port n Output Bit Clear 6" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
bitfld.long 0x4 5. "BCR5,Port n Output Bit Clear 5" "0: No effect.,1: Clear the corresponding OUTDRx bit."
bitfld.long 0x4 4. "BCR4,Port n Output Bit Clear 4" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
bitfld.long 0x4 3. "BCR3,Port n Output Bit Clear 3" "0: No effect.,1: Clear the corresponding OUTDRx bit."
bitfld.long 0x4 2. "BCR2,Port n Output Bit Clear 2" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
bitfld.long 0x4 1. "BCR1,Port n Output Bit Clear 1" "0: No effect.,1: Clear the corresponding OUTDRx bit."
bitfld.long 0x4 0. "BCR0,Port n Output Bit Clear 0" "0: No effect.,1: Clear the corresponding OUTDRx bit."
group.long 0x24++0x7
line.long 0x0 "OUTDMSK,Port n Output Data Mask Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 15. "OUTDMSK15,Port n Output Data Mask 15" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 14. "OUTDMSK14,Port n Output Data Mask 14" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 13. "OUTDMSK13,Port n Output Data Mask 13" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12. "OUTDMSK12,Port n Output Data Mask 12" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "OUTDMSK11,Port n Output Data Mask 11" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "OUTDMSK10,Port n Output Data Mask 10" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "OUTDMSK9,Port n Output Data Mask 9" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "OUTDMSK8,Port n Output Data Mask 8" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
endif
bitfld.long 0x0 7. "OUTDMSK7,Port n Output Data Mask 7" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
bitfld.long 0x0 6. "OUTDMSK6,Port n Output Data Mask 6" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
bitfld.long 0x0 5. "OUTDMSK5,Port n Output Data Mask 5" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
bitfld.long 0x0 4. "OUTDMSK4,Port n Output Data Mask 4" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
bitfld.long 0x0 3. "OUTDMSK3,Port n Output Data Mask 3" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
bitfld.long 0x0 2. "OUTDMSK2,Port n Output Data Mask 2" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
bitfld.long 0x0 1. "OUTDMSK1,Port n Output Data Mask 1" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
bitfld.long 0x0 0. "OUTDMSK0,Port n Output Data Mask 0" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
line.long 0x4 "DBCR,Port n Debounce Control Register"
bitfld.long 0x4 16.--18. "DBCLK,Port n Debounce Filter Sampling Clock Selection" "0: HCLK/1,1: HCLK/4,2: HCLK/16,3: HCLK/64,4: HCLK/256,5: HCLK/1024,?,?"
sif (cpuis("A31G12?*"))
bitfld.long 0x4 11. "DBEN11,Port n Debounce Enable 11" "0: Disable debounce filter.,1: Enable debounce filter."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 10. "DBEN10,Port n Debounce Enable 10" "0: Disable debounce filter.,1: Enable debounce filter."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 9. "DBEN9,Port n Debounce Enable 9" "0: Disable debounce filter.,1: Enable debounce filter."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 8. "DBEN8,Port n Debounce Enable 8" "0: Disable debounce filter.,1: Enable debounce filter."
endif
bitfld.long 0x4 7. "DBEN7,Port n Debounce Enable 7" "0: Disable debounce filter.,1: Enable debounce filter."
newline
bitfld.long 0x4 6. "DBEN6,Port n Debounce Enable 6" "0: Disable debounce filter.,1: Enable debounce filter."
bitfld.long 0x4 5. "DBEN5,Port n Debounce Enable 5" "0: Disable debounce filter.,1: Enable debounce filter."
newline
bitfld.long 0x4 4. "DBEN4,Port n Debounce Enable 4" "0: Disable debounce filter.,1: Enable debounce filter."
bitfld.long 0x4 3. "DBEN3,Port n Debounce Enable 3" "0: Disable debounce filter.,1: Enable debounce filter."
newline
bitfld.long 0x4 2. "DBEN2,Port n Debounce Enable 2" "0: Disable debounce filter.,1: Enable debounce filter."
bitfld.long 0x4 1. "DBEN1,Port n Debounce Enable 1" "0: Disable debounce filter.,1: Enable debounce filter."
newline
bitfld.long 0x4 0. "DBEN0,Port n Debounce Enable 0" "0: Disable debounce filter.,1: Enable debounce filter."
group.long 0x0++0xB
line.long 0x0 "PB_MOD,Port n Mode Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 30.--31. "MODE15,Port n Mode Selection 15" "0,1,2,3"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 28.--29. "MODE14,Port n Mode Selection 14" "0,1,2,3"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 26.--27. "MODE13,Port n Mode Selection 13" "0,1,2,3"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 24.--25. "MODE12,Port n Mode Selection 12" "0,1,2,3"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 22.--23. "MODE11,Port n Mode Selection 11" "0,1,2,3"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 20.--21. "MODE10,Port n Mode Selection 10" "0,1,2,3"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 18.--19. "MODE9,Port n Mode Selection 9" "0,1,2,3"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 16.--17. "MODE8,Port n Mode Selection 8" "0,1,2,3"
newline
endif
bitfld.long 0x0 14.--15. "MODE7,Port n Mode Selection 7" "0,1,2,3"
bitfld.long 0x0 12.--13. "MODE6,Port n Mode Selection 6" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "MODE5,Port n Mode Selection 5" "0,1,2,3"
bitfld.long 0x0 8.--9. "MODE4,Port n Mode Selection 4" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "MODE3,Port n Mode Selection 3" "0,1,2,3"
bitfld.long 0x0 4.--5. "MODE2,Port n Mode Selection 2" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "MODE1,Port n Mode Selection 1" "0,1,2,3"
bitfld.long 0x0 0.--1. "MODE0,Port n Mode Selection 0" "0,1,2,3"
line.long 0x4 "PB_TYP,Port n Output Type Selection Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x4 15. "TYP15,Port n Output Type Selection 15" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 14. "TYP14,Port n Output Type Selection 14" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 13. "TYP13,Port n Output Type Selection 13" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 12. "TYP12,Port n Output Type Selection 12" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 11. "TYP11,Port n Output Type Selection 11" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 10. "TYP10,Port n Output Type Selection 10" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 9. "TYP9,Port n Output Type Selection 9" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 8. "TYP8,Port n Output Type Selection 8" "0,1"
newline
endif
bitfld.long 0x4 7. "TYP7,Port n Output Type Selection 7" "0,1"
bitfld.long 0x4 6. "TYP6,Port n Output Type Selection 6" "0,1"
newline
bitfld.long 0x4 5. "TYP5,Port n Output Type Selection 5" "0,1"
bitfld.long 0x4 4. "TYP4,Port n Output Type Selection 4" "0,1"
newline
bitfld.long 0x4 3. "TYP3,Port n Output Type Selection 3" "0,1"
bitfld.long 0x4 2. "TYP2,Port n Output Type Selection 2" "0,1"
newline
bitfld.long 0x4 1. "TYP1,Port n Output Type Selection 1" "0,1"
bitfld.long 0x4 0. "TYP0,Port n Output Type Selection 0" "0,1"
line.long 0x8 "PB_AFSR1,Port n Alternative Function Selection Register 1"
hexmask.long.byte 0x8 28.--31. 1. "AFSR7,Port n Alternative Function Selection 7"
hexmask.long.byte 0x8 24.--27. 1. "AFSR6,Port n Alternative Function Selection 6"
newline
hexmask.long.byte 0x8 20.--23. 1. "AFSR5,Port n Alternative Function Selection 5"
hexmask.long.byte 0x8 16.--19. 1. "AFSR4,Port n Alternative Function Selection 4"
newline
hexmask.long.byte 0x8 12.--15. 1. "AFSR3,Port n Alternative Function Selection 3"
hexmask.long.byte 0x8 8.--11. 1. "AFSR2,Port n Alternative Function Selection 2"
newline
hexmask.long.byte 0x8 4.--7. 1. "AFSR1,Port n Alternative Function Selection 1"
hexmask.long.byte 0x8 0.--3. 1. "AFSR0,Port n Alternative Function Selection 0"
group.long 0x10++0x3
line.long 0x0 "PB_PUPD,Port n Pull-Up/Down Selection Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 30.--31. "PUPD15,Port n Pull-Up/Down Resistor Selection 15" "0,1,2,3"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 28.--29. "PUPD14,Port n Pull-Up/Down Resistor Selection 14" "0,1,2,3"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 26.--27. "PUPD13,Port n Pull-Up/Down Resistor Selection 13" "0,1,2,3"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 24.--25. "PUPD12,Port n Pull-Up/Down Resistor Selection 12" "0,1,2,3"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 22.--23. "PUPD11,Port n Pull-Up/Down Resistor Selection 11" "0,1,2,3"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 20.--21. "PUPD10,Port n Pull-Up/Down Resistor Selection 10" "0,1,2,3"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 18.--19. "PUPD9,Port n Pull-Up/Down Resistor Selection 9" "0,1,2,3"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 16.--17. "PUPD8,Port n Pull-Up/Down Resistor Selection 8" "0,1,2,3"
newline
endif
bitfld.long 0x0 14.--15. "PUPD7,Port n Pull-Up/Down Resistor Selection 7" "0,1,2,3"
bitfld.long 0x0 12.--13. "PUPD6,Port n Pull-Up/Down Resistor Selection 6" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "PUPD5,Port n Pull-Up/Down Resistor Selection 5" "0,1,2,3"
bitfld.long 0x0 8.--9. "PUPD4,Port n Pull-Up/Down Resistor Selection 4" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "PUPD3,Port n Pull-Up/Down Resistor Selection 3" "0,1,2,3"
bitfld.long 0x0 4.--5. "PUPD2,Port n Pull-Up/Down Resistor Selection 2" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "PUPD1,Port n Pull-Up/Down Resistor Selection 1" "0,1,2,3"
bitfld.long 0x0 0.--1. "PUPD0,Port n Pull-Up/Down Resistor Selection 0" "0,1,2,3"
rgroup.long 0x14++0x3
line.long 0x0 "PB_INDR,Port n Input Data Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 15. "INDR15,Port n Input Data 15" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 14. "INDR14,Port n Input Data 14" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 13. "INDR13,Port n Input Data 13" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12. "INDR12,Port n Input Data 12" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "INDR11,Port n Input Data 11" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "INDR10,Port n Input Data 10" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "INDR9,Port n Input Data 9" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "INDR8,Port n Input Data 8" "0,1"
newline
endif
bitfld.long 0x0 7. "INDR7,Port n Input Data 7" "0,1"
bitfld.long 0x0 6. "INDR6,Port n Input Data 6" "0,1"
newline
bitfld.long 0x0 5. "INDR5,Port n Input Data 5" "0,1"
bitfld.long 0x0 4. "INDR4,Port n Input Data 4" "0,1"
newline
bitfld.long 0x0 3. "INDR3,Port n Input Data 3" "0,1"
bitfld.long 0x0 2. "INDR2,Port n Input Data 2" "0,1"
newline
bitfld.long 0x0 1. "INDR1,Port n Input Data 1" "0,1"
bitfld.long 0x0 0. "INDR0,Port n Input Data 0" "0,1"
group.long 0x18++0x3
line.long 0x0 "PB_OUTDR,Port n Output Data Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 15. "OUTDR15,Port n Output Data 15" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 14. "OUTDR14,Port n Output Data 14" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 13. "OUTDR13,Port n Output Data 13" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12. "OUTDR12,Port n Output Data 12" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "OUTDR11,Port n Output Data 11" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "OUTDR10,Port n Output Data 10" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "OUTDR9,Port n Output Data 9" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "OUTDR8,Port n Output Data 8" "0,1"
newline
endif
bitfld.long 0x0 7. "OUTDR7,Port n Output Data 7" "0,1"
bitfld.long 0x0 6. "OUTDR6,Port n Output Data 6" "0,1"
newline
bitfld.long 0x0 5. "OUTDR5,Port n Output Data 5" "0,1"
bitfld.long 0x0 4. "OUTDR4,Port n Output Data 4" "0,1"
newline
bitfld.long 0x0 3. "OUTDR3,Port n Output Data 3" "0,1"
bitfld.long 0x0 2. "OUTDR2,Port n Output Data 2" "0,1"
newline
bitfld.long 0x0 1. "OUTDR1,Port n Output Data 1" "0,1"
bitfld.long 0x0 0. "OUTDR0,Port n Output Data 0" "0,1"
wgroup.long 0x1C++0x7
line.long 0x0 "PB_BSR,Port n Output Bit Set Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 15. "BSR15,Port n Output Bit Set 15" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 14. "BSR14,Port n Output Bit Set 14" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 13. "BSR13,Port n Output Bit Set 13" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12. "BSR12,Port n Output Bit Set 12" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "BSR11,Port n Output Bit Set 11" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "BSR10,Port n Output Bit Set 10" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "BSR9,Port n Output Bit Set 9" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "BSR8,Port n Output Bit Set 8" "0,1"
newline
endif
bitfld.long 0x0 7. "BSR7,Port n Output Bit Set 7" "0,1"
bitfld.long 0x0 6. "BSR6,Port n Output Bit Set 6" "0,1"
newline
bitfld.long 0x0 5. "BSR5,Port n Output Bit Set 5" "0,1"
bitfld.long 0x0 4. "BSR4,Port n Output Bit Set 4" "0,1"
newline
bitfld.long 0x0 3. "BSR3,Port n Output Bit Set 3" "0,1"
bitfld.long 0x0 2. "BSR2,Port n Output Bit Set 2" "0,1"
newline
bitfld.long 0x0 1. "BSR1,Port n Output Bit Set 1" "0,1"
bitfld.long 0x0 0. "BSR0,Port n Output Bit Set 0" "0,1"
line.long 0x4 "PB_BCR,Port n Output Bit Clear Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x4 15. "BCR15,Port n Output Bit Clear 15" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 14. "BCR14,Port n Output Bit Clear 14" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 13. "BCR13,Port n Output Bit Clear 13" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 12. "BCR12,Port n Output Bit Clear 12" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 11. "BCR11,Port n Output Bit Clear 11" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 10. "BCR10,Port n Output Bit Clear 10" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 9. "BCR9,Port n Output Bit Clear 9" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 8. "BCR8,Port n Output Bit Clear 8" "0,1"
newline
endif
bitfld.long 0x4 7. "BCR7,Port n Output Bit Clear 7" "0,1"
bitfld.long 0x4 6. "BCR6,Port n Output Bit Clear 6" "0,1"
newline
bitfld.long 0x4 5. "BCR5,Port n Output Bit Clear 5" "0,1"
bitfld.long 0x4 4. "BCR4,Port n Output Bit Clear 4" "0,1"
newline
bitfld.long 0x4 3. "BCR3,Port n Output Bit Clear 3" "0,1"
bitfld.long 0x4 2. "BCR2,Port n Output Bit Clear 2" "0,1"
newline
bitfld.long 0x4 1. "BCR1,Port n Output Bit Clear 1" "0,1"
bitfld.long 0x4 0. "BCR0,Port n Output Bit Clear 0" "0,1"
group.long 0x24++0x7
line.long 0x0 "PB_OUTDMSK,Port n Output Data Mask Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 15. "OUTDMSK15,Port n Output Data Mask 15" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 14. "OUTDMSK14,Port n Output Data Mask 14" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 13. "OUTDMSK13,Port n Output Data Mask 13" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12. "OUTDMSK12,Port n Output Data Mask 12" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "OUTDMSK11,Port n Output Data Mask 11" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "OUTDMSK10,Port n Output Data Mask 10" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "OUTDMSK9,Port n Output Data Mask 9" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "OUTDMSK8,Port n Output Data Mask 8" "0,1"
newline
endif
bitfld.long 0x0 7. "OUTDMSK7,Port n Output Data Mask 7" "0,1"
bitfld.long 0x0 6. "OUTDMSK6,Port n Output Data Mask 6" "0,1"
newline
bitfld.long 0x0 5. "OUTDMSK5,Port n Output Data Mask 5" "0,1"
bitfld.long 0x0 4. "OUTDMSK4,Port n Output Data Mask 4" "0,1"
newline
bitfld.long 0x0 3. "OUTDMSK3,Port n Output Data Mask 3" "0,1"
bitfld.long 0x0 2. "OUTDMSK2,Port n Output Data Mask 2" "0,1"
newline
bitfld.long 0x0 1. "OUTDMSK1,Port n Output Data Mask 1" "0,1"
bitfld.long 0x0 0. "OUTDMSK0,Port n Output Data Mask 0" "0,1"
line.long 0x4 "PB_DBCR,Port n Debounce Control Register"
bitfld.long 0x4 16.--18. "DBCLK,Port n Debounce Filter Sampling Clock Selection" "0,1,2,3,4,5,6,7"
sif (cpuis("A31G12?*"))
bitfld.long 0x4 11. "DBEN11,Port n Debounce Enable 11" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 10. "DBEN10,Port n Debounce Enable 10" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 9. "DBEN9,Port n Debounce Enable 9" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 8. "DBEN8,Port n Debounce Enable 8" "0,1"
endif
bitfld.long 0x4 7. "DBEN7,Port n Debounce Enable 7" "0,1"
newline
bitfld.long 0x4 6. "DBEN6,Port n Debounce Enable 6" "0,1"
bitfld.long 0x4 5. "DBEN5,Port n Debounce Enable 5" "0,1"
newline
bitfld.long 0x4 4. "DBEN4,Port n Debounce Enable 4" "0,1"
bitfld.long 0x4 3. "DBEN3,Port n Debounce Enable 3" "0,1"
newline
bitfld.long 0x4 2. "DBEN2,Port n Debounce Enable 2" "0,1"
bitfld.long 0x4 1. "DBEN1,Port n Debounce Enable 1" "0,1"
newline
bitfld.long 0x4 0. "DBEN0,Port n Debounce Enable 0" "0,1"
tree.end
tree "PC"
base ad:0x30000200
group.long 0x0++0xB
line.long 0x0 "MOD,Port n Mode Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 30.--31. "MODE15,Port n Mode Selection 15" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 28.--29. "MODE14,Port n Mode Selection 14" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 26.--27. "MODE13,Port n Mode Selection 13" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 24.--25. "MODE12,Port n Mode Selection 12" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 22.--23. "MODE11,Port n Mode Selection 11" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 20.--21. "MODE10,Port n Mode Selection 10" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 18.--19. "MODE9,Port n Mode Selection 9" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 16.--17. "MODE8,Port n Mode Selection 8" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
endif
bitfld.long 0x0 14.--15. "MODE7,Port n Mode Selection 7" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
bitfld.long 0x0 12.--13. "MODE6,Port n Mode Selection 6" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
bitfld.long 0x0 10.--11. "MODE5,Port n Mode Selection 5" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
bitfld.long 0x0 8.--9. "MODE4,Port n Mode Selection 4" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
bitfld.long 0x0 6.--7. "MODE3,Port n Mode Selection 3" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
bitfld.long 0x0 4.--5. "MODE2,Port n Mode Selection 2" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
bitfld.long 0x0 2.--3. "MODE1,Port n Mode Selection 1" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
bitfld.long 0x0 0.--1. "MODE0,Port n Mode Selection 0" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
line.long 0x4 "TYP,Port n Output Type Selection Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x4 15. "TYP15,Port n Output Type Selection 15" "0: Push-Pull Output,1: Open-Drain Output"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 14. "TYP14,Port n Output Type Selection 14" "0: Push-Pull Output,1: Open-Drain Output"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 13. "TYP13,Port n Output Type Selection 13" "0: Push-Pull Output,1: Open-Drain Output"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 12. "TYP12,Port n Output Type Selection 12" "0: Push-Pull Output,1: Open-Drain Output"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 11. "TYP11,Port n Output Type Selection 11" "0: Push-Pull Output,1: Open-Drain Output"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 10. "TYP10,Port n Output Type Selection 10" "0: Push-Pull Output,1: Open-Drain Output"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 9. "TYP9,Port n Output Type Selection 9" "0: Push-Pull Output,1: Open-Drain Output"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 8. "TYP8,Port n Output Type Selection 8" "0: Push-Pull Output,1: Open-Drain Output"
newline
endif
bitfld.long 0x4 7. "TYP7,Port n Output Type Selection 7" "0: Push-Pull Output,1: Open-Drain Output"
bitfld.long 0x4 6. "TYP6,Port n Output Type Selection 6" "0: Push-Pull Output,1: Open-Drain Output"
newline
bitfld.long 0x4 5. "TYP5,Port n Output Type Selection 5" "0: Push-Pull Output,1: Open-Drain Output"
bitfld.long 0x4 4. "TYP4,Port n Output Type Selection 4" "0: Push-Pull Output,1: Open-Drain Output"
newline
bitfld.long 0x4 3. "TYP3,Port n Output Type Selection 3" "0: Push-Pull Output,1: Open-Drain Output"
bitfld.long 0x4 2. "TYP2,Port n Output Type Selection 2" "0: Push-Pull Output,1: Open-Drain Output"
newline
bitfld.long 0x4 1. "TYP1,Port n Output Type Selection 1" "0: Push-Pull Output,1: Open-Drain Output"
bitfld.long 0x4 0. "TYP0,Port n Output Type Selection 0" "0: Push-Pull Output,1: Open-Drain Output"
line.long 0x8 "AFSR1,Port n Alternative Function Selection Register 1"
hexmask.long.byte 0x8 28.--31. 1. "AFSR7,Port n Alternative Function Selection 7"
hexmask.long.byte 0x8 24.--27. 1. "AFSR6,Port n Alternative Function Selection 6"
newline
hexmask.long.byte 0x8 20.--23. 1. "AFSR5,Port n Alternative Function Selection 5"
hexmask.long.byte 0x8 16.--19. 1. "AFSR4,Port n Alternative Function Selection 4"
newline
hexmask.long.byte 0x8 12.--15. 1. "AFSR3,Port n Alternative Function Selection 3"
hexmask.long.byte 0x8 8.--11. 1. "AFSR2,Port n Alternative Function Selection 2"
newline
hexmask.long.byte 0x8 4.--7. 1. "AFSR1,Port n Alternative Function Selection 1"
hexmask.long.byte 0x8 0.--3. 1. "AFSR0,Port n Alternative Function Selection 0"
sif (cpuis("A31G12?*"))
group.long 0xC++0x3
line.long 0x0 "AFSR2,Port n Alternative Function Selection Register 2"
hexmask.long.byte 0x0 28.--31. 1. "AFSR15,Port n Alternative Function Selection 15"
hexmask.long.byte 0x0 24.--27. 1. "AFSR14,Port n Alternative Function Selection 14"
newline
hexmask.long.byte 0x0 20.--23. 1. "AFSR13,Port n Alternative Function Selection 13"
hexmask.long.byte 0x0 16.--19. 1. "AFSR12,Port n Alternative Function Selection 12"
newline
hexmask.long.byte 0x0 12.--15. 1. "AFSR11,Port n Alternative Function Selection 11"
hexmask.long.byte 0x0 8.--11. 1. "AFSR10,Port n Alternative Function Selection 10"
newline
hexmask.long.byte 0x0 4.--7. 1. "AFSR9,Port n Alternative Function Selection 9"
hexmask.long.byte 0x0 0.--3. 1. "AFSR8,Port n Alternative Function Selection 8"
endif
sif (cpuis("A31G12?*"))
group.long 0xC++0x3
line.long 0x0 "PC_AFSR2,Port n Alternative Function Selection Register 2"
hexmask.long.byte 0x0 16.--19. 1. "AFSR12,Port n Alternative Function Selection 12"
hexmask.long.byte 0x0 12.--15. 1. "AFSR11,Port n Alternative Function Selection 11"
newline
hexmask.long.byte 0x0 8.--11. 1. "AFSR10,Port n Alternative Function Selection 10"
hexmask.long.byte 0x0 4.--7. 1. "AFSR9,Port n Alternative Function Selection 9"
newline
hexmask.long.byte 0x0 0.--3. 1. "AFSR8,Port n Alternative Function Selection 8"
endif
group.long 0x10++0x3
line.long 0x0 "PUPD,Port n Pull-Up/Down Selection Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 30.--31. "PUPD15,Port n Pull-Up/Down Resistor Selection 15" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 28.--29. "PUPD14,Port n Pull-Up/Down Resistor Selection 14" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 26.--27. "PUPD13,Port n Pull-Up/Down Resistor Selection 13" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 24.--25. "PUPD12,Port n Pull-Up/Down Resistor Selection 12" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 22.--23. "PUPD11,Port n Pull-Up/Down Resistor Selection 11" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 20.--21. "PUPD10,Port n Pull-Up/Down Resistor Selection 10" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 18.--19. "PUPD9,Port n Pull-Up/Down Resistor Selection 9" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 16.--17. "PUPD8,Port n Pull-Up/Down Resistor Selection 8" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
endif
bitfld.long 0x0 14.--15. "PUPD7,Port n Pull-Up/Down Resistor Selection 7" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
bitfld.long 0x0 12.--13. "PUPD6,Port n Pull-Up/Down Resistor Selection 6" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
bitfld.long 0x0 10.--11. "PUPD5,Port n Pull-Up/Down Resistor Selection 5" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
bitfld.long 0x0 8.--9. "PUPD4,Port n Pull-Up/Down Resistor Selection 4" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
bitfld.long 0x0 6.--7. "PUPD3,Port n Pull-Up/Down Resistor Selection 3" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
bitfld.long 0x0 4.--5. "PUPD2,Port n Pull-Up/Down Resistor Selection 2" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
bitfld.long 0x0 2.--3. "PUPD1,Port n Pull-Up/Down Resistor Selection 1" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
bitfld.long 0x0 0.--1. "PUPD0,Port n Pull-Up/Down Resistor Selection 0" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
rgroup.long 0x14++0x3
line.long 0x0 "INDR,Port n Input Data Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 15. "INDR15,Port n Input Data 15" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 14. "INDR14,Port n Input Data 14" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 13. "INDR13,Port n Input Data 13" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12. "INDR12,Port n Input Data 12" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "INDR11,Port n Input Data 11" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "INDR10,Port n Input Data 10" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "INDR9,Port n Input Data 9" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "INDR8,Port n Input Data 8" "0,1"
newline
endif
bitfld.long 0x0 7. "INDR7,Port n Input Data 7" "0,1"
bitfld.long 0x0 6. "INDR6,Port n Input Data 6" "0,1"
newline
bitfld.long 0x0 5. "INDR5,Port n Input Data 5" "0,1"
bitfld.long 0x0 4. "INDR4,Port n Input Data 4" "0,1"
newline
bitfld.long 0x0 3. "INDR3,Port n Input Data 3" "0,1"
bitfld.long 0x0 2. "INDR2,Port n Input Data 2" "0,1"
newline
bitfld.long 0x0 1. "INDR1,Port n Input Data 1" "0,1"
bitfld.long 0x0 0. "INDR0,Port n Input Data 0" "0,1"
group.long 0x18++0x3
line.long 0x0 "OUTDR,Port n Output Data Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 15. "OUTDR15,Port n Output Data 15" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 14. "OUTDR14,Port n Output Data 14" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 13. "OUTDR13,Port n Output Data 13" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12. "OUTDR12,Port n Output Data 12" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "OUTDR11,Port n Output Data 11" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "OUTDR10,Port n Output Data 10" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "OUTDR9,Port n Output Data 9" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "OUTDR8,Port n Output Data 8" "0,1"
newline
endif
bitfld.long 0x0 7. "OUTDR7,Port n Output Data 7" "0,1"
bitfld.long 0x0 6. "OUTDR6,Port n Output Data 6" "0,1"
newline
bitfld.long 0x0 5. "OUTDR5,Port n Output Data 5" "0,1"
bitfld.long 0x0 4. "OUTDR4,Port n Output Data 4" "0,1"
newline
bitfld.long 0x0 3. "OUTDR3,Port n Output Data 3" "0,1"
bitfld.long 0x0 2. "OUTDR2,Port n Output Data 2" "0,1"
newline
bitfld.long 0x0 1. "OUTDR1,Port n Output Data 1" "0,1"
bitfld.long 0x0 0. "OUTDR0,Port n Output Data 0" "0,1"
wgroup.long 0x1C++0x7
line.long 0x0 "BSR,Port n Output Bit Set Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 15. "BSR15,Port n Output Bit Set 15" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 14. "BSR14,Port n Output Bit Set 14" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 13. "BSR13,Port n Output Bit Set 13" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12. "BSR12,Port n Output Bit Set 12" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "BSR11,Port n Output Bit Set 11" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "BSR10,Port n Output Bit Set 10" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "BSR9,Port n Output Bit Set 9" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "BSR8,Port n Output Bit Set 8" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
endif
bitfld.long 0x0 7. "BSR7,Port n Output Bit Set 7" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
bitfld.long 0x0 6. "BSR6,Port n Output Bit Set 6" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
bitfld.long 0x0 5. "BSR5,Port n Output Bit Set 5" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
bitfld.long 0x0 4. "BSR4,Port n Output Bit Set 4" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
bitfld.long 0x0 3. "BSR3,Port n Output Bit Set 3" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
bitfld.long 0x0 2. "BSR2,Port n Output Bit Set 2" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
bitfld.long 0x0 1. "BSR1,Port n Output Bit Set 1" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
bitfld.long 0x0 0. "BSR0,Port n Output Bit Set 0" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
line.long 0x4 "BCR,Port n Output Bit Clear Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x4 15. "BCR15,Port n Output Bit Clear 15" "0: No effect.,1: Clear the corresponding OUTDRx bit."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 14. "BCR14,Port n Output Bit Clear 14" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 13. "BCR13,Port n Output Bit Clear 13" "0: No effect.,1: Clear the corresponding OUTDRx bit."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 12. "BCR12,Port n Output Bit Clear 12" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 11. "BCR11,Port n Output Bit Clear 11" "0: No effect.,1: Clear the corresponding OUTDRx bit."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 10. "BCR10,Port n Output Bit Clear 10" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 9. "BCR9,Port n Output Bit Clear 9" "0: No effect.,1: Clear the corresponding OUTDRx bit."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 8. "BCR8,Port n Output Bit Clear 8" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
endif
bitfld.long 0x4 7. "BCR7,Port n Output Bit Clear 7" "0: No effect.,1: Clear the corresponding OUTDRx bit."
bitfld.long 0x4 6. "BCR6,Port n Output Bit Clear 6" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
bitfld.long 0x4 5. "BCR5,Port n Output Bit Clear 5" "0: No effect.,1: Clear the corresponding OUTDRx bit."
bitfld.long 0x4 4. "BCR4,Port n Output Bit Clear 4" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
bitfld.long 0x4 3. "BCR3,Port n Output Bit Clear 3" "0: No effect.,1: Clear the corresponding OUTDRx bit."
bitfld.long 0x4 2. "BCR2,Port n Output Bit Clear 2" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
bitfld.long 0x4 1. "BCR1,Port n Output Bit Clear 1" "0: No effect.,1: Clear the corresponding OUTDRx bit."
bitfld.long 0x4 0. "BCR0,Port n Output Bit Clear 0" "0: No effect.,1: Clear the corresponding OUTDRx bit."
group.long 0x24++0x7
line.long 0x0 "OUTDMSK,Port n Output Data Mask Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 15. "OUTDMSK15,Port n Output Data Mask 15" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 14. "OUTDMSK14,Port n Output Data Mask 14" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 13. "OUTDMSK13,Port n Output Data Mask 13" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12. "OUTDMSK12,Port n Output Data Mask 12" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "OUTDMSK11,Port n Output Data Mask 11" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "OUTDMSK10,Port n Output Data Mask 10" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "OUTDMSK9,Port n Output Data Mask 9" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "OUTDMSK8,Port n Output Data Mask 8" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
endif
bitfld.long 0x0 7. "OUTDMSK7,Port n Output Data Mask 7" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
bitfld.long 0x0 6. "OUTDMSK6,Port n Output Data Mask 6" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
bitfld.long 0x0 5. "OUTDMSK5,Port n Output Data Mask 5" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
bitfld.long 0x0 4. "OUTDMSK4,Port n Output Data Mask 4" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
bitfld.long 0x0 3. "OUTDMSK3,Port n Output Data Mask 3" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
bitfld.long 0x0 2. "OUTDMSK2,Port n Output Data Mask 2" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
bitfld.long 0x0 1. "OUTDMSK1,Port n Output Data Mask 1" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
bitfld.long 0x0 0. "OUTDMSK0,Port n Output Data Mask 0" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
line.long 0x4 "DBCR,Port n Debounce Control Register"
bitfld.long 0x4 16.--18. "DBCLK,Port n Debounce Filter Sampling Clock Selection" "0: HCLK/1,1: HCLK/4,2: HCLK/16,3: HCLK/64,4: HCLK/256,5: HCLK/1024,?,?"
sif (cpuis("A31G12?*"))
bitfld.long 0x4 11. "DBEN11,Port n Debounce Enable 11" "0: Disable debounce filter.,1: Enable debounce filter."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 10. "DBEN10,Port n Debounce Enable 10" "0: Disable debounce filter.,1: Enable debounce filter."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 9. "DBEN9,Port n Debounce Enable 9" "0: Disable debounce filter.,1: Enable debounce filter."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 8. "DBEN8,Port n Debounce Enable 8" "0: Disable debounce filter.,1: Enable debounce filter."
endif
bitfld.long 0x4 7. "DBEN7,Port n Debounce Enable 7" "0: Disable debounce filter.,1: Enable debounce filter."
newline
bitfld.long 0x4 6. "DBEN6,Port n Debounce Enable 6" "0: Disable debounce filter.,1: Enable debounce filter."
bitfld.long 0x4 5. "DBEN5,Port n Debounce Enable 5" "0: Disable debounce filter.,1: Enable debounce filter."
newline
bitfld.long 0x4 4. "DBEN4,Port n Debounce Enable 4" "0: Disable debounce filter.,1: Enable debounce filter."
bitfld.long 0x4 3. "DBEN3,Port n Debounce Enable 3" "0: Disable debounce filter.,1: Enable debounce filter."
newline
bitfld.long 0x4 2. "DBEN2,Port n Debounce Enable 2" "0: Disable debounce filter.,1: Enable debounce filter."
bitfld.long 0x4 1. "DBEN1,Port n Debounce Enable 1" "0: Disable debounce filter.,1: Enable debounce filter."
newline
bitfld.long 0x4 0. "DBEN0,Port n Debounce Enable 0" "0: Disable debounce filter.,1: Enable debounce filter."
group.long 0x0++0xB
line.long 0x0 "PC_MOD,Port n Mode Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 24.--25. "MODE12,Port n Mode Selection 12" "0,1,2,3"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 22.--23. "MODE11,Port n Mode Selection 11" "0,1,2,3"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 20.--21. "MODE10,Port n Mode Selection 10" "0,1,2,3"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 18.--19. "MODE9,Port n Mode Selection 9" "0,1,2,3"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 16.--17. "MODE8,Port n Mode Selection 8" "0,1,2,3"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 14.--15. "MODE7,Port n Mode Selection 7" "0,1,2,3"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12.--13. "MODE6,Port n Mode Selection 6" "0,1,2,3"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10.--11. "MODE5,Port n Mode Selection 5" "0,1,2,3"
newline
endif
bitfld.long 0x0 8.--9. "MODE4,Port n Mode Selection 4" "0,1,2,3"
bitfld.long 0x0 6.--7. "MODE3,Port n Mode Selection 3" "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "MODE2,Port n Mode Selection 2" "0,1,2,3"
bitfld.long 0x0 2.--3. "MODE1,Port n Mode Selection 1" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "MODE0,Port n Mode Selection 0" "0,1,2,3"
line.long 0x4 "PC_TYP,Port n Output Type Selection Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x4 12. "TYP12,Port n Output Type Selection 12" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 11. "TYP11,Port n Output Type Selection 11" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 10. "TYP10,Port n Output Type Selection 10" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 9. "TYP9,Port n Output Type Selection 9" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 8. "TYP8,Port n Output Type Selection 8" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 7. "TYP7,Port n Output Type Selection 7" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 6. "TYP6,Port n Output Type Selection 6" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 5. "TYP5,Port n Output Type Selection 5" "0,1"
newline
endif
bitfld.long 0x4 4. "TYP4,Port n Output Type Selection 4" "0,1"
bitfld.long 0x4 3. "TYP3,Port n Output Type Selection 3" "0,1"
newline
bitfld.long 0x4 2. "TYP2,Port n Output Type Selection 2" "0,1"
bitfld.long 0x4 1. "TYP1,Port n Output Type Selection 1" "0,1"
newline
bitfld.long 0x4 0. "TYP0,Port n Output Type Selection 0" "0,1"
line.long 0x8 "PC_AFSR1,Port n Alternative Function Selection Register 1"
sif (cpuis("A31G12?*"))
hexmask.long.byte 0x8 28.--31. 1. "AFSR7,Port n Alternative Function Selection 7"
endif
sif (cpuis("A31G12?*"))
hexmask.long.byte 0x8 24.--27. 1. "AFSR6,Port n Alternative Function Selection 6"
newline
endif
sif (cpuis("A31G12?*"))
hexmask.long.byte 0x8 20.--23. 1. "AFSR5,Port n Alternative Function Selection 5"
endif
hexmask.long.byte 0x8 16.--19. 1. "AFSR4,Port n Alternative Function Selection 4"
newline
hexmask.long.byte 0x8 12.--15. 1. "AFSR3,Port n Alternative Function Selection 3"
hexmask.long.byte 0x8 8.--11. 1. "AFSR2,Port n Alternative Function Selection 2"
newline
hexmask.long.byte 0x8 4.--7. 1. "AFSR1,Port n Alternative Function Selection 1"
hexmask.long.byte 0x8 0.--3. 1. "AFSR0,Port n Alternative Function Selection 0"
group.long 0x10++0x3
line.long 0x0 "PC_PUPD,Port n Pull-Up/Down Selection Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 24.--25. "PUPD12,Port n Pull-Up/Down Resistor Selection 12" "0,1,2,3"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 22.--23. "PUPD11,Port n Pull-Up/Down Resistor Selection 11" "0,1,2,3"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 20.--21. "PUPD10,Port n Pull-Up/Down Resistor Selection 10" "0,1,2,3"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 18.--19. "PUPD9,Port n Pull-Up/Down Resistor Selection 9" "0,1,2,3"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 16.--17. "PUPD8,Port n Pull-Up/Down Resistor Selection 8" "0,1,2,3"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 14.--15. "PUPD7,Port n Pull-Up/Down Resistor Selection 7" "0,1,2,3"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12.--13. "PUPD6,Port n Pull-Up/Down Resistor Selection 6" "0,1,2,3"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10.--11. "PUPD5,Port n Pull-Up/Down Resistor Selection 5" "0,1,2,3"
newline
endif
bitfld.long 0x0 8.--9. "PUPD4,Port n Pull-Up/Down Resistor Selection 4" "0,1,2,3"
bitfld.long 0x0 6.--7. "PUPD3,Port n Pull-Up/Down Resistor Selection 3" "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "PUPD2,Port n Pull-Up/Down Resistor Selection 2" "0,1,2,3"
bitfld.long 0x0 2.--3. "PUPD1,Port n Pull-Up/Down Resistor Selection 1" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "PUPD0,Port n Pull-Up/Down Resistor Selection 0" "0,1,2,3"
rgroup.long 0x14++0x3
line.long 0x0 "PC_INDR,Port n Input Data Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12. "INDR12,Port n Input Data 12" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "INDR11,Port n Input Data 11" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "INDR10,Port n Input Data 10" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "INDR9,Port n Input Data 9" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "INDR8,Port n Input Data 8" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 7. "INDR7,Port n Input Data 7" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 6. "INDR6,Port n Input Data 6" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 5. "INDR5,Port n Input Data 5" "0,1"
newline
endif
bitfld.long 0x0 4. "INDR4,Port n Input Data 4" "0,1"
bitfld.long 0x0 3. "INDR3,Port n Input Data 3" "0,1"
newline
bitfld.long 0x0 2. "INDR2,Port n Input Data 2" "0,1"
bitfld.long 0x0 1. "INDR1,Port n Input Data 1" "0,1"
newline
bitfld.long 0x0 0. "INDR0,Port n Input Data 0" "0,1"
group.long 0x18++0x3
line.long 0x0 "PC_OUTDR,Port n Output Data Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12. "OUTDR12,Port n Output Data 12" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "OUTDR11,Port n Output Data 11" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "OUTDR10,Port n Output Data 10" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "OUTDR9,Port n Output Data 9" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "OUTDR8,Port n Output Data 8" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 7. "OUTDR7,Port n Output Data 7" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 6. "OUTDR6,Port n Output Data 6" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 5. "OUTDR5,Port n Output Data 5" "0,1"
newline
endif
bitfld.long 0x0 4. "OUTDR4,Port n Output Data 4" "0,1"
bitfld.long 0x0 3. "OUTDR3,Port n Output Data 3" "0,1"
newline
bitfld.long 0x0 2. "OUTDR2,Port n Output Data 2" "0,1"
bitfld.long 0x0 1. "OUTDR1,Port n Output Data 1" "0,1"
newline
bitfld.long 0x0 0. "OUTDR0,Port n Output Data 0" "0,1"
wgroup.long 0x1C++0x7
line.long 0x0 "PC_BSR,Port n Output Bit Set Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12. "BSR12,Port n Output Bit Set 12" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "BSR11,Port n Output Bit Set 11" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "BSR10,Port n Output Bit Set 10" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "BSR9,Port n Output Bit Set 9" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "BSR8,Port n Output Bit Set 8" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 7. "BSR7,Port n Output Bit Set 7" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 6. "BSR6,Port n Output Bit Set 6" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 5. "BSR5,Port n Output Bit Set 5" "0,1"
newline
endif
bitfld.long 0x0 4. "BSR4,Port n Output Bit Set 4" "0,1"
bitfld.long 0x0 3. "BSR3,Port n Output Bit Set 3" "0,1"
newline
bitfld.long 0x0 2. "BSR2,Port n Output Bit Set 2" "0,1"
bitfld.long 0x0 1. "BSR1,Port n Output Bit Set 1" "0,1"
newline
bitfld.long 0x0 0. "BSR0,Port n Output Bit Set 0" "0,1"
line.long 0x4 "PC_BCR,Port n Output Bit Clear Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x4 12. "BCR12,Port n Output Bit Clear 12" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 11. "BCR11,Port n Output Bit Clear 11" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 10. "BCR10,Port n Output Bit Clear 10" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 9. "BCR9,Port n Output Bit Clear 9" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 8. "BCR8,Port n Output Bit Clear 8" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 7. "BCR7,Port n Output Bit Clear 7" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 6. "BCR6,Port n Output Bit Clear 6" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 5. "BCR5,Port n Output Bit Clear 5" "0,1"
newline
endif
bitfld.long 0x4 4. "BCR4,Port n Output Bit Clear 4" "0,1"
bitfld.long 0x4 3. "BCR3,Port n Output Bit Clear 3" "0,1"
newline
bitfld.long 0x4 2. "BCR2,Port n Output Bit Clear 2" "0,1"
bitfld.long 0x4 1. "BCR1,Port n Output Bit Clear 1" "0,1"
newline
bitfld.long 0x4 0. "BCR0,Port n Output Bit Clear 0" "0,1"
group.long 0x24++0x7
line.long 0x0 "PC_OUTDMSK,Port n Output Data Mask Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12. "OUTDMSK12,Port n Output Data Mask 12" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "OUTDMSK11,Port n Output Data Mask 11" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "OUTDMSK10,Port n Output Data Mask 10" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "OUTDMSK9,Port n Output Data Mask 9" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "OUTDMSK8,Port n Output Data Mask 8" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 7. "OUTDMSK7,Port n Output Data Mask 7" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 6. "OUTDMSK6,Port n Output Data Mask 6" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 5. "OUTDMSK5,Port n Output Data Mask 5" "0,1"
newline
endif
bitfld.long 0x0 4. "OUTDMSK4,Port n Output Data Mask 4" "0,1"
bitfld.long 0x0 3. "OUTDMSK3,Port n Output Data Mask 3" "0,1"
newline
bitfld.long 0x0 2. "OUTDMSK2,Port n Output Data Mask 2" "0,1"
bitfld.long 0x0 1. "OUTDMSK1,Port n Output Data Mask 1" "0,1"
newline
bitfld.long 0x0 0. "OUTDMSK0,Port n Output Data Mask 0" "0,1"
line.long 0x4 "PC_DBCR,Port n Debounce Control Register"
bitfld.long 0x4 16.--18. "DBCLK,Port n Debounce Filter Sampling Clock Selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 3. "DBEN3,Port n Debounce Enable 3" "0,1"
newline
bitfld.long 0x4 2. "DBEN2,Port n Debounce Enable 2" "0,1"
bitfld.long 0x4 1. "DBEN1,Port n Debounce Enable 1" "0,1"
newline
bitfld.long 0x4 0. "DBEN0,Port n Debounce Enable 0" "0,1"
tree.end
tree "PD"
base ad:0x30000300
group.long 0x0++0xB
line.long 0x0 "MOD,Port n Mode Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 30.--31. "MODE15,Port n Mode Selection 15" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 28.--29. "MODE14,Port n Mode Selection 14" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 26.--27. "MODE13,Port n Mode Selection 13" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 24.--25. "MODE12,Port n Mode Selection 12" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 22.--23. "MODE11,Port n Mode Selection 11" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 20.--21. "MODE10,Port n Mode Selection 10" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 18.--19. "MODE9,Port n Mode Selection 9" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 16.--17. "MODE8,Port n Mode Selection 8" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
endif
bitfld.long 0x0 14.--15. "MODE7,Port n Mode Selection 7" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
bitfld.long 0x0 12.--13. "MODE6,Port n Mode Selection 6" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
bitfld.long 0x0 10.--11. "MODE5,Port n Mode Selection 5" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
bitfld.long 0x0 8.--9. "MODE4,Port n Mode Selection 4" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
bitfld.long 0x0 6.--7. "MODE3,Port n Mode Selection 3" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
bitfld.long 0x0 4.--5. "MODE2,Port n Mode Selection 2" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
bitfld.long 0x0 2.--3. "MODE1,Port n Mode Selection 1" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
bitfld.long 0x0 0.--1. "MODE0,Port n Mode Selection 0" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
line.long 0x4 "TYP,Port n Output Type Selection Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x4 15. "TYP15,Port n Output Type Selection 15" "0: Push-Pull Output,1: Open-Drain Output"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 14. "TYP14,Port n Output Type Selection 14" "0: Push-Pull Output,1: Open-Drain Output"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 13. "TYP13,Port n Output Type Selection 13" "0: Push-Pull Output,1: Open-Drain Output"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 12. "TYP12,Port n Output Type Selection 12" "0: Push-Pull Output,1: Open-Drain Output"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 11. "TYP11,Port n Output Type Selection 11" "0: Push-Pull Output,1: Open-Drain Output"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 10. "TYP10,Port n Output Type Selection 10" "0: Push-Pull Output,1: Open-Drain Output"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 9. "TYP9,Port n Output Type Selection 9" "0: Push-Pull Output,1: Open-Drain Output"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 8. "TYP8,Port n Output Type Selection 8" "0: Push-Pull Output,1: Open-Drain Output"
newline
endif
bitfld.long 0x4 7. "TYP7,Port n Output Type Selection 7" "0: Push-Pull Output,1: Open-Drain Output"
bitfld.long 0x4 6. "TYP6,Port n Output Type Selection 6" "0: Push-Pull Output,1: Open-Drain Output"
newline
bitfld.long 0x4 5. "TYP5,Port n Output Type Selection 5" "0: Push-Pull Output,1: Open-Drain Output"
bitfld.long 0x4 4. "TYP4,Port n Output Type Selection 4" "0: Push-Pull Output,1: Open-Drain Output"
newline
bitfld.long 0x4 3. "TYP3,Port n Output Type Selection 3" "0: Push-Pull Output,1: Open-Drain Output"
bitfld.long 0x4 2. "TYP2,Port n Output Type Selection 2" "0: Push-Pull Output,1: Open-Drain Output"
newline
bitfld.long 0x4 1. "TYP1,Port n Output Type Selection 1" "0: Push-Pull Output,1: Open-Drain Output"
bitfld.long 0x4 0. "TYP0,Port n Output Type Selection 0" "0: Push-Pull Output,1: Open-Drain Output"
line.long 0x8 "AFSR1,Port n Alternative Function Selection Register 1"
hexmask.long.byte 0x8 28.--31. 1. "AFSR7,Port n Alternative Function Selection 7"
hexmask.long.byte 0x8 24.--27. 1. "AFSR6,Port n Alternative Function Selection 6"
newline
hexmask.long.byte 0x8 20.--23. 1. "AFSR5,Port n Alternative Function Selection 5"
hexmask.long.byte 0x8 16.--19. 1. "AFSR4,Port n Alternative Function Selection 4"
newline
hexmask.long.byte 0x8 12.--15. 1. "AFSR3,Port n Alternative Function Selection 3"
hexmask.long.byte 0x8 8.--11. 1. "AFSR2,Port n Alternative Function Selection 2"
newline
hexmask.long.byte 0x8 4.--7. 1. "AFSR1,Port n Alternative Function Selection 1"
hexmask.long.byte 0x8 0.--3. 1. "AFSR0,Port n Alternative Function Selection 0"
sif (cpuis("A31G12?*"))
group.long 0xC++0x3
line.long 0x0 "AFSR2,Port n Alternative Function Selection Register 2"
hexmask.long.byte 0x0 28.--31. 1. "AFSR15,Port n Alternative Function Selection 15"
hexmask.long.byte 0x0 24.--27. 1. "AFSR14,Port n Alternative Function Selection 14"
newline
hexmask.long.byte 0x0 20.--23. 1. "AFSR13,Port n Alternative Function Selection 13"
hexmask.long.byte 0x0 16.--19. 1. "AFSR12,Port n Alternative Function Selection 12"
newline
hexmask.long.byte 0x0 12.--15. 1. "AFSR11,Port n Alternative Function Selection 11"
hexmask.long.byte 0x0 8.--11. 1. "AFSR10,Port n Alternative Function Selection 10"
newline
hexmask.long.byte 0x0 4.--7. 1. "AFSR9,Port n Alternative Function Selection 9"
hexmask.long.byte 0x0 0.--3. 1. "AFSR8,Port n Alternative Function Selection 8"
endif
sif (cpuis("A31G12?*"))
group.long 0xC++0x3
line.long 0x0 "PD_AFSR2,Port n Alternative Function Selection Register 2"
endif
group.long 0x10++0x3
line.long 0x0 "PUPD,Port n Pull-Up/Down Selection Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 30.--31. "PUPD15,Port n Pull-Up/Down Resistor Selection 15" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 28.--29. "PUPD14,Port n Pull-Up/Down Resistor Selection 14" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 26.--27. "PUPD13,Port n Pull-Up/Down Resistor Selection 13" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 24.--25. "PUPD12,Port n Pull-Up/Down Resistor Selection 12" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 22.--23. "PUPD11,Port n Pull-Up/Down Resistor Selection 11" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 20.--21. "PUPD10,Port n Pull-Up/Down Resistor Selection 10" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 18.--19. "PUPD9,Port n Pull-Up/Down Resistor Selection 9" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 16.--17. "PUPD8,Port n Pull-Up/Down Resistor Selection 8" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
endif
bitfld.long 0x0 14.--15. "PUPD7,Port n Pull-Up/Down Resistor Selection 7" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
bitfld.long 0x0 12.--13. "PUPD6,Port n Pull-Up/Down Resistor Selection 6" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
bitfld.long 0x0 10.--11. "PUPD5,Port n Pull-Up/Down Resistor Selection 5" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
bitfld.long 0x0 8.--9. "PUPD4,Port n Pull-Up/Down Resistor Selection 4" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
bitfld.long 0x0 6.--7. "PUPD3,Port n Pull-Up/Down Resistor Selection 3" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
bitfld.long 0x0 4.--5. "PUPD2,Port n Pull-Up/Down Resistor Selection 2" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
bitfld.long 0x0 2.--3. "PUPD1,Port n Pull-Up/Down Resistor Selection 1" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
bitfld.long 0x0 0.--1. "PUPD0,Port n Pull-Up/Down Resistor Selection 0" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
rgroup.long 0x14++0x3
line.long 0x0 "INDR,Port n Input Data Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 15. "INDR15,Port n Input Data 15" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 14. "INDR14,Port n Input Data 14" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 13. "INDR13,Port n Input Data 13" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12. "INDR12,Port n Input Data 12" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "INDR11,Port n Input Data 11" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "INDR10,Port n Input Data 10" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "INDR9,Port n Input Data 9" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "INDR8,Port n Input Data 8" "0,1"
newline
endif
bitfld.long 0x0 7. "INDR7,Port n Input Data 7" "0,1"
bitfld.long 0x0 6. "INDR6,Port n Input Data 6" "0,1"
newline
bitfld.long 0x0 5. "INDR5,Port n Input Data 5" "0,1"
bitfld.long 0x0 4. "INDR4,Port n Input Data 4" "0,1"
newline
bitfld.long 0x0 3. "INDR3,Port n Input Data 3" "0,1"
bitfld.long 0x0 2. "INDR2,Port n Input Data 2" "0,1"
newline
bitfld.long 0x0 1. "INDR1,Port n Input Data 1" "0,1"
bitfld.long 0x0 0. "INDR0,Port n Input Data 0" "0,1"
group.long 0x18++0x3
line.long 0x0 "OUTDR,Port n Output Data Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 15. "OUTDR15,Port n Output Data 15" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 14. "OUTDR14,Port n Output Data 14" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 13. "OUTDR13,Port n Output Data 13" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12. "OUTDR12,Port n Output Data 12" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "OUTDR11,Port n Output Data 11" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "OUTDR10,Port n Output Data 10" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "OUTDR9,Port n Output Data 9" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "OUTDR8,Port n Output Data 8" "0,1"
newline
endif
bitfld.long 0x0 7. "OUTDR7,Port n Output Data 7" "0,1"
bitfld.long 0x0 6. "OUTDR6,Port n Output Data 6" "0,1"
newline
bitfld.long 0x0 5. "OUTDR5,Port n Output Data 5" "0,1"
bitfld.long 0x0 4. "OUTDR4,Port n Output Data 4" "0,1"
newline
bitfld.long 0x0 3. "OUTDR3,Port n Output Data 3" "0,1"
bitfld.long 0x0 2. "OUTDR2,Port n Output Data 2" "0,1"
newline
bitfld.long 0x0 1. "OUTDR1,Port n Output Data 1" "0,1"
bitfld.long 0x0 0. "OUTDR0,Port n Output Data 0" "0,1"
wgroup.long 0x1C++0x7
line.long 0x0 "BSR,Port n Output Bit Set Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 15. "BSR15,Port n Output Bit Set 15" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 14. "BSR14,Port n Output Bit Set 14" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 13. "BSR13,Port n Output Bit Set 13" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12. "BSR12,Port n Output Bit Set 12" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "BSR11,Port n Output Bit Set 11" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "BSR10,Port n Output Bit Set 10" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "BSR9,Port n Output Bit Set 9" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "BSR8,Port n Output Bit Set 8" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
endif
bitfld.long 0x0 7. "BSR7,Port n Output Bit Set 7" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
bitfld.long 0x0 6. "BSR6,Port n Output Bit Set 6" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
bitfld.long 0x0 5. "BSR5,Port n Output Bit Set 5" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
bitfld.long 0x0 4. "BSR4,Port n Output Bit Set 4" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
bitfld.long 0x0 3. "BSR3,Port n Output Bit Set 3" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
bitfld.long 0x0 2. "BSR2,Port n Output Bit Set 2" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
bitfld.long 0x0 1. "BSR1,Port n Output Bit Set 1" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
bitfld.long 0x0 0. "BSR0,Port n Output Bit Set 0" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
line.long 0x4 "BCR,Port n Output Bit Clear Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x4 15. "BCR15,Port n Output Bit Clear 15" "0: No effect.,1: Clear the corresponding OUTDRx bit."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 14. "BCR14,Port n Output Bit Clear 14" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 13. "BCR13,Port n Output Bit Clear 13" "0: No effect.,1: Clear the corresponding OUTDRx bit."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 12. "BCR12,Port n Output Bit Clear 12" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 11. "BCR11,Port n Output Bit Clear 11" "0: No effect.,1: Clear the corresponding OUTDRx bit."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 10. "BCR10,Port n Output Bit Clear 10" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 9. "BCR9,Port n Output Bit Clear 9" "0: No effect.,1: Clear the corresponding OUTDRx bit."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 8. "BCR8,Port n Output Bit Clear 8" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
endif
bitfld.long 0x4 7. "BCR7,Port n Output Bit Clear 7" "0: No effect.,1: Clear the corresponding OUTDRx bit."
bitfld.long 0x4 6. "BCR6,Port n Output Bit Clear 6" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
bitfld.long 0x4 5. "BCR5,Port n Output Bit Clear 5" "0: No effect.,1: Clear the corresponding OUTDRx bit."
bitfld.long 0x4 4. "BCR4,Port n Output Bit Clear 4" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
bitfld.long 0x4 3. "BCR3,Port n Output Bit Clear 3" "0: No effect.,1: Clear the corresponding OUTDRx bit."
bitfld.long 0x4 2. "BCR2,Port n Output Bit Clear 2" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
bitfld.long 0x4 1. "BCR1,Port n Output Bit Clear 1" "0: No effect.,1: Clear the corresponding OUTDRx bit."
bitfld.long 0x4 0. "BCR0,Port n Output Bit Clear 0" "0: No effect.,1: Clear the corresponding OUTDRx bit."
group.long 0x24++0x7
line.long 0x0 "OUTDMSK,Port n Output Data Mask Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 15. "OUTDMSK15,Port n Output Data Mask 15" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 14. "OUTDMSK14,Port n Output Data Mask 14" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 13. "OUTDMSK13,Port n Output Data Mask 13" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12. "OUTDMSK12,Port n Output Data Mask 12" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "OUTDMSK11,Port n Output Data Mask 11" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "OUTDMSK10,Port n Output Data Mask 10" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "OUTDMSK9,Port n Output Data Mask 9" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "OUTDMSK8,Port n Output Data Mask 8" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
endif
bitfld.long 0x0 7. "OUTDMSK7,Port n Output Data Mask 7" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
bitfld.long 0x0 6. "OUTDMSK6,Port n Output Data Mask 6" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
bitfld.long 0x0 5. "OUTDMSK5,Port n Output Data Mask 5" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
bitfld.long 0x0 4. "OUTDMSK4,Port n Output Data Mask 4" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
bitfld.long 0x0 3. "OUTDMSK3,Port n Output Data Mask 3" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
bitfld.long 0x0 2. "OUTDMSK2,Port n Output Data Mask 2" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
bitfld.long 0x0 1. "OUTDMSK1,Port n Output Data Mask 1" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
bitfld.long 0x0 0. "OUTDMSK0,Port n Output Data Mask 0" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
line.long 0x4 "DBCR,Port n Debounce Control Register"
bitfld.long 0x4 16.--18. "DBCLK,Port n Debounce Filter Sampling Clock Selection" "0: HCLK/1,1: HCLK/4,2: HCLK/16,3: HCLK/64,4: HCLK/256,5: HCLK/1024,?,?"
sif (cpuis("A31G12?*"))
bitfld.long 0x4 11. "DBEN11,Port n Debounce Enable 11" "0: Disable debounce filter.,1: Enable debounce filter."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 10. "DBEN10,Port n Debounce Enable 10" "0: Disable debounce filter.,1: Enable debounce filter."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 9. "DBEN9,Port n Debounce Enable 9" "0: Disable debounce filter.,1: Enable debounce filter."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 8. "DBEN8,Port n Debounce Enable 8" "0: Disable debounce filter.,1: Enable debounce filter."
endif
bitfld.long 0x4 7. "DBEN7,Port n Debounce Enable 7" "0: Disable debounce filter.,1: Enable debounce filter."
newline
bitfld.long 0x4 6. "DBEN6,Port n Debounce Enable 6" "0: Disable debounce filter.,1: Enable debounce filter."
bitfld.long 0x4 5. "DBEN5,Port n Debounce Enable 5" "0: Disable debounce filter.,1: Enable debounce filter."
newline
bitfld.long 0x4 4. "DBEN4,Port n Debounce Enable 4" "0: Disable debounce filter.,1: Enable debounce filter."
bitfld.long 0x4 3. "DBEN3,Port n Debounce Enable 3" "0: Disable debounce filter.,1: Enable debounce filter."
newline
bitfld.long 0x4 2. "DBEN2,Port n Debounce Enable 2" "0: Disable debounce filter.,1: Enable debounce filter."
bitfld.long 0x4 1. "DBEN1,Port n Debounce Enable 1" "0: Disable debounce filter.,1: Enable debounce filter."
newline
bitfld.long 0x4 0. "DBEN0,Port n Debounce Enable 0" "0: Disable debounce filter.,1: Enable debounce filter."
group.long 0x0++0xB
line.long 0x0 "PD_MOD,Port n Mode Register"
bitfld.long 0x0 14.--15. "MODE7,Port n Mode Selection 7" "0,1,2,3"
bitfld.long 0x0 12.--13. "MODE6,Port n Mode Selection 6" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "MODE5,Port n Mode Selection 5" "0,1,2,3"
bitfld.long 0x0 8.--9. "MODE4,Port n Mode Selection 4" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "MODE3,Port n Mode Selection 3" "0,1,2,3"
bitfld.long 0x0 4.--5. "MODE2,Port n Mode Selection 2" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "MODE1,Port n Mode Selection 1" "0,1,2,3"
bitfld.long 0x0 0.--1. "MODE0,Port n Mode Selection 0" "0,1,2,3"
line.long 0x4 "PD_TYP,Port n Output Type Selection Register"
bitfld.long 0x4 7. "TYP7,Port n Output Type Selection 7" "0,1"
bitfld.long 0x4 6. "TYP6,Port n Output Type Selection 6" "0,1"
newline
bitfld.long 0x4 5. "TYP5,Port n Output Type Selection 5" "0,1"
bitfld.long 0x4 4. "TYP4,Port n Output Type Selection 4" "0,1"
newline
bitfld.long 0x4 3. "TYP3,Port n Output Type Selection 3" "0,1"
bitfld.long 0x4 2. "TYP2,Port n Output Type Selection 2" "0,1"
newline
bitfld.long 0x4 1. "TYP1,Port n Output Type Selection 1" "0,1"
bitfld.long 0x4 0. "TYP0,Port n Output Type Selection 0" "0,1"
line.long 0x8 "PD_AFSR1,Port n Alternative Function Selection Register 1"
hexmask.long.byte 0x8 28.--31. 1. "AFSR7,Port n Alternative Function Selection 7"
hexmask.long.byte 0x8 24.--27. 1. "AFSR6,Port n Alternative Function Selection 6"
newline
hexmask.long.byte 0x8 20.--23. 1. "AFSR5,Port n Alternative Function Selection 5"
hexmask.long.byte 0x8 16.--19. 1. "AFSR4,Port n Alternative Function Selection 4"
newline
hexmask.long.byte 0x8 12.--15. 1. "AFSR3,Port n Alternative Function Selection 3"
hexmask.long.byte 0x8 8.--11. 1. "AFSR2,Port n Alternative Function Selection 2"
newline
hexmask.long.byte 0x8 4.--7. 1. "AFSR1,Port n Alternative Function Selection 1"
hexmask.long.byte 0x8 0.--3. 1. "AFSR0,Port n Alternative Function Selection 0"
group.long 0x10++0x3
line.long 0x0 "PD_PUPD,Port n Pull-Up/Down Selection Register"
bitfld.long 0x0 14.--15. "PUPD7,Port n Pull-Up/Down Resistor Selection 7" "0,1,2,3"
bitfld.long 0x0 12.--13. "PUPD6,Port n Pull-Up/Down Resistor Selection 6" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "PUPD5,Port n Pull-Up/Down Resistor Selection 5" "0,1,2,3"
bitfld.long 0x0 8.--9. "PUPD4,Port n Pull-Up/Down Resistor Selection 4" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "PUPD3,Port n Pull-Up/Down Resistor Selection 3" "0,1,2,3"
bitfld.long 0x0 4.--5. "PUPD2,Port n Pull-Up/Down Resistor Selection 2" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "PUPD1,Port n Pull-Up/Down Resistor Selection 1" "0,1,2,3"
bitfld.long 0x0 0.--1. "PUPD0,Port n Pull-Up/Down Resistor Selection 0" "0,1,2,3"
rgroup.long 0x14++0x3
line.long 0x0 "PD_INDR,Port n Input Data Register"
bitfld.long 0x0 7. "INDR7,Port n Input Data 7" "0,1"
bitfld.long 0x0 6. "INDR6,Port n Input Data 6" "0,1"
newline
bitfld.long 0x0 5. "INDR5,Port n Input Data 5" "0,1"
bitfld.long 0x0 4. "INDR4,Port n Input Data 4" "0,1"
newline
bitfld.long 0x0 3. "INDR3,Port n Input Data 3" "0,1"
bitfld.long 0x0 2. "INDR2,Port n Input Data 2" "0,1"
newline
bitfld.long 0x0 1. "INDR1,Port n Input Data 1" "0,1"
bitfld.long 0x0 0. "INDR0,Port n Input Data 0" "0,1"
group.long 0x18++0x3
line.long 0x0 "PD_OUTDR,Port n Output Data Register"
bitfld.long 0x0 7. "OUTDR7,Port n Output Data 7" "0,1"
bitfld.long 0x0 6. "OUTDR6,Port n Output Data 6" "0,1"
newline
bitfld.long 0x0 5. "OUTDR5,Port n Output Data 5" "0,1"
bitfld.long 0x0 4. "OUTDR4,Port n Output Data 4" "0,1"
newline
bitfld.long 0x0 3. "OUTDR3,Port n Output Data 3" "0,1"
bitfld.long 0x0 2. "OUTDR2,Port n Output Data 2" "0,1"
newline
bitfld.long 0x0 1. "OUTDR1,Port n Output Data 1" "0,1"
bitfld.long 0x0 0. "OUTDR0,Port n Output Data 0" "0,1"
wgroup.long 0x1C++0x7
line.long 0x0 "PD_BSR,Port n Output Bit Set Register"
bitfld.long 0x0 7. "BSR7,Port n Output Bit Set 7" "0,1"
bitfld.long 0x0 6. "BSR6,Port n Output Bit Set 6" "0,1"
newline
bitfld.long 0x0 5. "BSR5,Port n Output Bit Set 5" "0,1"
bitfld.long 0x0 4. "BSR4,Port n Output Bit Set 4" "0,1"
newline
bitfld.long 0x0 3. "BSR3,Port n Output Bit Set 3" "0,1"
bitfld.long 0x0 2. "BSR2,Port n Output Bit Set 2" "0,1"
newline
bitfld.long 0x0 1. "BSR1,Port n Output Bit Set 1" "0,1"
bitfld.long 0x0 0. "BSR0,Port n Output Bit Set 0" "0,1"
line.long 0x4 "PD_BCR,Port n Output Bit Clear Register"
bitfld.long 0x4 7. "BCR7,Port n Output Bit Clear 7" "0,1"
bitfld.long 0x4 6. "BCR6,Port n Output Bit Clear 6" "0,1"
newline
bitfld.long 0x4 5. "BCR5,Port n Output Bit Clear 5" "0,1"
bitfld.long 0x4 4. "BCR4,Port n Output Bit Clear 4" "0,1"
newline
bitfld.long 0x4 3. "BCR3,Port n Output Bit Clear 3" "0,1"
bitfld.long 0x4 2. "BCR2,Port n Output Bit Clear 2" "0,1"
newline
bitfld.long 0x4 1. "BCR1,Port n Output Bit Clear 1" "0,1"
bitfld.long 0x4 0. "BCR0,Port n Output Bit Clear 0" "0,1"
group.long 0x24++0x3
line.long 0x0 "PD_OUTDMSK,Port n Output Data Mask Register"
bitfld.long 0x0 7. "OUTDMSK7,Port n Output Data Mask 7" "0,1"
bitfld.long 0x0 6. "OUTDMSK6,Port n Output Data Mask 6" "0,1"
newline
bitfld.long 0x0 5. "OUTDMSK5,Port n Output Data Mask 5" "0,1"
bitfld.long 0x0 4. "OUTDMSK4,Port n Output Data Mask 4" "0,1"
newline
bitfld.long 0x0 3. "OUTDMSK3,Port n Output Data Mask 3" "0,1"
bitfld.long 0x0 2. "OUTDMSK2,Port n Output Data Mask 2" "0,1"
newline
bitfld.long 0x0 1. "OUTDMSK1,Port n Output Data Mask 1" "0,1"
bitfld.long 0x0 0. "OUTDMSK0,Port n Output Data Mask 0" "0,1"
tree.end
tree "PE"
base ad:0x30000400
group.long 0x0++0xB
line.long 0x0 "MOD,Port n Mode Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 30.--31. "MODE15,Port n Mode Selection 15" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 28.--29. "MODE14,Port n Mode Selection 14" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 26.--27. "MODE13,Port n Mode Selection 13" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 24.--25. "MODE12,Port n Mode Selection 12" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 22.--23. "MODE11,Port n Mode Selection 11" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 20.--21. "MODE10,Port n Mode Selection 10" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 18.--19. "MODE9,Port n Mode Selection 9" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 16.--17. "MODE8,Port n Mode Selection 8" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
endif
bitfld.long 0x0 14.--15. "MODE7,Port n Mode Selection 7" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
bitfld.long 0x0 12.--13. "MODE6,Port n Mode Selection 6" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
bitfld.long 0x0 10.--11. "MODE5,Port n Mode Selection 5" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
bitfld.long 0x0 8.--9. "MODE4,Port n Mode Selection 4" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
bitfld.long 0x0 6.--7. "MODE3,Port n Mode Selection 3" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
bitfld.long 0x0 4.--5. "MODE2,Port n Mode Selection 2" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
bitfld.long 0x0 2.--3. "MODE1,Port n Mode Selection 1" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
bitfld.long 0x0 0.--1. "MODE0,Port n Mode Selection 0" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
line.long 0x4 "TYP,Port n Output Type Selection Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x4 15. "TYP15,Port n Output Type Selection 15" "0: Push-Pull Output,1: Open-Drain Output"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 14. "TYP14,Port n Output Type Selection 14" "0: Push-Pull Output,1: Open-Drain Output"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 13. "TYP13,Port n Output Type Selection 13" "0: Push-Pull Output,1: Open-Drain Output"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 12. "TYP12,Port n Output Type Selection 12" "0: Push-Pull Output,1: Open-Drain Output"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 11. "TYP11,Port n Output Type Selection 11" "0: Push-Pull Output,1: Open-Drain Output"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 10. "TYP10,Port n Output Type Selection 10" "0: Push-Pull Output,1: Open-Drain Output"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 9. "TYP9,Port n Output Type Selection 9" "0: Push-Pull Output,1: Open-Drain Output"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 8. "TYP8,Port n Output Type Selection 8" "0: Push-Pull Output,1: Open-Drain Output"
newline
endif
bitfld.long 0x4 7. "TYP7,Port n Output Type Selection 7" "0: Push-Pull Output,1: Open-Drain Output"
bitfld.long 0x4 6. "TYP6,Port n Output Type Selection 6" "0: Push-Pull Output,1: Open-Drain Output"
newline
bitfld.long 0x4 5. "TYP5,Port n Output Type Selection 5" "0: Push-Pull Output,1: Open-Drain Output"
bitfld.long 0x4 4. "TYP4,Port n Output Type Selection 4" "0: Push-Pull Output,1: Open-Drain Output"
newline
bitfld.long 0x4 3. "TYP3,Port n Output Type Selection 3" "0: Push-Pull Output,1: Open-Drain Output"
bitfld.long 0x4 2. "TYP2,Port n Output Type Selection 2" "0: Push-Pull Output,1: Open-Drain Output"
newline
bitfld.long 0x4 1. "TYP1,Port n Output Type Selection 1" "0: Push-Pull Output,1: Open-Drain Output"
bitfld.long 0x4 0. "TYP0,Port n Output Type Selection 0" "0: Push-Pull Output,1: Open-Drain Output"
line.long 0x8 "AFSR1,Port n Alternative Function Selection Register 1"
hexmask.long.byte 0x8 28.--31. 1. "AFSR7,Port n Alternative Function Selection 7"
hexmask.long.byte 0x8 24.--27. 1. "AFSR6,Port n Alternative Function Selection 6"
newline
hexmask.long.byte 0x8 20.--23. 1. "AFSR5,Port n Alternative Function Selection 5"
hexmask.long.byte 0x8 16.--19. 1. "AFSR4,Port n Alternative Function Selection 4"
newline
hexmask.long.byte 0x8 12.--15. 1. "AFSR3,Port n Alternative Function Selection 3"
hexmask.long.byte 0x8 8.--11. 1. "AFSR2,Port n Alternative Function Selection 2"
newline
hexmask.long.byte 0x8 4.--7. 1. "AFSR1,Port n Alternative Function Selection 1"
hexmask.long.byte 0x8 0.--3. 1. "AFSR0,Port n Alternative Function Selection 0"
sif (cpuis("A31G12?*"))
group.long 0xC++0x3
line.long 0x0 "AFSR2,Port n Alternative Function Selection Register 2"
hexmask.long.byte 0x0 28.--31. 1. "AFSR15,Port n Alternative Function Selection 15"
hexmask.long.byte 0x0 24.--27. 1. "AFSR14,Port n Alternative Function Selection 14"
newline
hexmask.long.byte 0x0 20.--23. 1. "AFSR13,Port n Alternative Function Selection 13"
hexmask.long.byte 0x0 16.--19. 1. "AFSR12,Port n Alternative Function Selection 12"
newline
hexmask.long.byte 0x0 12.--15. 1. "AFSR11,Port n Alternative Function Selection 11"
hexmask.long.byte 0x0 8.--11. 1. "AFSR10,Port n Alternative Function Selection 10"
newline
hexmask.long.byte 0x0 4.--7. 1. "AFSR9,Port n Alternative Function Selection 9"
hexmask.long.byte 0x0 0.--3. 1. "AFSR8,Port n Alternative Function Selection 8"
endif
sif (cpuis("A31G12?*"))
group.long 0xC++0x3
line.long 0x0 "PE_AFSR2,Port n Alternative Function Selection Register 2"
hexmask.long.byte 0x0 28.--31. 1. "AFSR15,Port n Alternative Function Selection 15"
hexmask.long.byte 0x0 24.--27. 1. "AFSR14,Port n Alternative Function Selection 14"
newline
hexmask.long.byte 0x0 20.--23. 1. "AFSR13,Port n Alternative Function Selection 13"
hexmask.long.byte 0x0 16.--19. 1. "AFSR12,Port n Alternative Function Selection 12"
newline
hexmask.long.byte 0x0 12.--15. 1. "AFSR11,Port n Alternative Function Selection 11"
hexmask.long.byte 0x0 8.--11. 1. "AFSR10,Port n Alternative Function Selection 10"
newline
hexmask.long.byte 0x0 4.--7. 1. "AFSR9,Port n Alternative Function Selection 9"
hexmask.long.byte 0x0 0.--3. 1. "AFSR8,Port n Alternative Function Selection 8"
endif
group.long 0x10++0x3
line.long 0x0 "PUPD,Port n Pull-Up/Down Selection Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 30.--31. "PUPD15,Port n Pull-Up/Down Resistor Selection 15" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 28.--29. "PUPD14,Port n Pull-Up/Down Resistor Selection 14" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 26.--27. "PUPD13,Port n Pull-Up/Down Resistor Selection 13" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 24.--25. "PUPD12,Port n Pull-Up/Down Resistor Selection 12" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 22.--23. "PUPD11,Port n Pull-Up/Down Resistor Selection 11" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 20.--21. "PUPD10,Port n Pull-Up/Down Resistor Selection 10" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 18.--19. "PUPD9,Port n Pull-Up/Down Resistor Selection 9" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 16.--17. "PUPD8,Port n Pull-Up/Down Resistor Selection 8" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
endif
bitfld.long 0x0 14.--15. "PUPD7,Port n Pull-Up/Down Resistor Selection 7" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
bitfld.long 0x0 12.--13. "PUPD6,Port n Pull-Up/Down Resistor Selection 6" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
bitfld.long 0x0 10.--11. "PUPD5,Port n Pull-Up/Down Resistor Selection 5" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
bitfld.long 0x0 8.--9. "PUPD4,Port n Pull-Up/Down Resistor Selection 4" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
bitfld.long 0x0 6.--7. "PUPD3,Port n Pull-Up/Down Resistor Selection 3" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
bitfld.long 0x0 4.--5. "PUPD2,Port n Pull-Up/Down Resistor Selection 2" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
bitfld.long 0x0 2.--3. "PUPD1,Port n Pull-Up/Down Resistor Selection 1" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
bitfld.long 0x0 0.--1. "PUPD0,Port n Pull-Up/Down Resistor Selection 0" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
rgroup.long 0x14++0x3
line.long 0x0 "INDR,Port n Input Data Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 15. "INDR15,Port n Input Data 15" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 14. "INDR14,Port n Input Data 14" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 13. "INDR13,Port n Input Data 13" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12. "INDR12,Port n Input Data 12" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "INDR11,Port n Input Data 11" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "INDR10,Port n Input Data 10" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "INDR9,Port n Input Data 9" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "INDR8,Port n Input Data 8" "0,1"
newline
endif
bitfld.long 0x0 7. "INDR7,Port n Input Data 7" "0,1"
bitfld.long 0x0 6. "INDR6,Port n Input Data 6" "0,1"
newline
bitfld.long 0x0 5. "INDR5,Port n Input Data 5" "0,1"
bitfld.long 0x0 4. "INDR4,Port n Input Data 4" "0,1"
newline
bitfld.long 0x0 3. "INDR3,Port n Input Data 3" "0,1"
bitfld.long 0x0 2. "INDR2,Port n Input Data 2" "0,1"
newline
bitfld.long 0x0 1. "INDR1,Port n Input Data 1" "0,1"
bitfld.long 0x0 0. "INDR0,Port n Input Data 0" "0,1"
group.long 0x18++0x3
line.long 0x0 "OUTDR,Port n Output Data Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 15. "OUTDR15,Port n Output Data 15" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 14. "OUTDR14,Port n Output Data 14" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 13. "OUTDR13,Port n Output Data 13" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12. "OUTDR12,Port n Output Data 12" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "OUTDR11,Port n Output Data 11" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "OUTDR10,Port n Output Data 10" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "OUTDR9,Port n Output Data 9" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "OUTDR8,Port n Output Data 8" "0,1"
newline
endif
bitfld.long 0x0 7. "OUTDR7,Port n Output Data 7" "0,1"
bitfld.long 0x0 6. "OUTDR6,Port n Output Data 6" "0,1"
newline
bitfld.long 0x0 5. "OUTDR5,Port n Output Data 5" "0,1"
bitfld.long 0x0 4. "OUTDR4,Port n Output Data 4" "0,1"
newline
bitfld.long 0x0 3. "OUTDR3,Port n Output Data 3" "0,1"
bitfld.long 0x0 2. "OUTDR2,Port n Output Data 2" "0,1"
newline
bitfld.long 0x0 1. "OUTDR1,Port n Output Data 1" "0,1"
bitfld.long 0x0 0. "OUTDR0,Port n Output Data 0" "0,1"
wgroup.long 0x1C++0x7
line.long 0x0 "BSR,Port n Output Bit Set Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 15. "BSR15,Port n Output Bit Set 15" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 14. "BSR14,Port n Output Bit Set 14" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 13. "BSR13,Port n Output Bit Set 13" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12. "BSR12,Port n Output Bit Set 12" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "BSR11,Port n Output Bit Set 11" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "BSR10,Port n Output Bit Set 10" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "BSR9,Port n Output Bit Set 9" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "BSR8,Port n Output Bit Set 8" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
endif
bitfld.long 0x0 7. "BSR7,Port n Output Bit Set 7" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
bitfld.long 0x0 6. "BSR6,Port n Output Bit Set 6" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
bitfld.long 0x0 5. "BSR5,Port n Output Bit Set 5" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
bitfld.long 0x0 4. "BSR4,Port n Output Bit Set 4" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
bitfld.long 0x0 3. "BSR3,Port n Output Bit Set 3" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
bitfld.long 0x0 2. "BSR2,Port n Output Bit Set 2" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
bitfld.long 0x0 1. "BSR1,Port n Output Bit Set 1" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
bitfld.long 0x0 0. "BSR0,Port n Output Bit Set 0" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
line.long 0x4 "BCR,Port n Output Bit Clear Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x4 15. "BCR15,Port n Output Bit Clear 15" "0: No effect.,1: Clear the corresponding OUTDRx bit."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 14. "BCR14,Port n Output Bit Clear 14" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 13. "BCR13,Port n Output Bit Clear 13" "0: No effect.,1: Clear the corresponding OUTDRx bit."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 12. "BCR12,Port n Output Bit Clear 12" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 11. "BCR11,Port n Output Bit Clear 11" "0: No effect.,1: Clear the corresponding OUTDRx bit."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 10. "BCR10,Port n Output Bit Clear 10" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 9. "BCR9,Port n Output Bit Clear 9" "0: No effect.,1: Clear the corresponding OUTDRx bit."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 8. "BCR8,Port n Output Bit Clear 8" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
endif
bitfld.long 0x4 7. "BCR7,Port n Output Bit Clear 7" "0: No effect.,1: Clear the corresponding OUTDRx bit."
bitfld.long 0x4 6. "BCR6,Port n Output Bit Clear 6" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
bitfld.long 0x4 5. "BCR5,Port n Output Bit Clear 5" "0: No effect.,1: Clear the corresponding OUTDRx bit."
bitfld.long 0x4 4. "BCR4,Port n Output Bit Clear 4" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
bitfld.long 0x4 3. "BCR3,Port n Output Bit Clear 3" "0: No effect.,1: Clear the corresponding OUTDRx bit."
bitfld.long 0x4 2. "BCR2,Port n Output Bit Clear 2" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
bitfld.long 0x4 1. "BCR1,Port n Output Bit Clear 1" "0: No effect.,1: Clear the corresponding OUTDRx bit."
bitfld.long 0x4 0. "BCR0,Port n Output Bit Clear 0" "0: No effect.,1: Clear the corresponding OUTDRx bit."
group.long 0x24++0x7
line.long 0x0 "OUTDMSK,Port n Output Data Mask Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 15. "OUTDMSK15,Port n Output Data Mask 15" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 14. "OUTDMSK14,Port n Output Data Mask 14" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 13. "OUTDMSK13,Port n Output Data Mask 13" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12. "OUTDMSK12,Port n Output Data Mask 12" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "OUTDMSK11,Port n Output Data Mask 11" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "OUTDMSK10,Port n Output Data Mask 10" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "OUTDMSK9,Port n Output Data Mask 9" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "OUTDMSK8,Port n Output Data Mask 8" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
endif
bitfld.long 0x0 7. "OUTDMSK7,Port n Output Data Mask 7" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
bitfld.long 0x0 6. "OUTDMSK6,Port n Output Data Mask 6" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
bitfld.long 0x0 5. "OUTDMSK5,Port n Output Data Mask 5" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
bitfld.long 0x0 4. "OUTDMSK4,Port n Output Data Mask 4" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
bitfld.long 0x0 3. "OUTDMSK3,Port n Output Data Mask 3" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
bitfld.long 0x0 2. "OUTDMSK2,Port n Output Data Mask 2" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
bitfld.long 0x0 1. "OUTDMSK1,Port n Output Data Mask 1" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
bitfld.long 0x0 0. "OUTDMSK0,Port n Output Data Mask 0" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
line.long 0x4 "DBCR,Port n Debounce Control Register"
bitfld.long 0x4 16.--18. "DBCLK,Port n Debounce Filter Sampling Clock Selection" "0: HCLK/1,1: HCLK/4,2: HCLK/16,3: HCLK/64,4: HCLK/256,5: HCLK/1024,?,?"
sif (cpuis("A31G12?*"))
bitfld.long 0x4 11. "DBEN11,Port n Debounce Enable 11" "0: Disable debounce filter.,1: Enable debounce filter."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 10. "DBEN10,Port n Debounce Enable 10" "0: Disable debounce filter.,1: Enable debounce filter."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 9. "DBEN9,Port n Debounce Enable 9" "0: Disable debounce filter.,1: Enable debounce filter."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 8. "DBEN8,Port n Debounce Enable 8" "0: Disable debounce filter.,1: Enable debounce filter."
endif
bitfld.long 0x4 7. "DBEN7,Port n Debounce Enable 7" "0: Disable debounce filter.,1: Enable debounce filter."
newline
bitfld.long 0x4 6. "DBEN6,Port n Debounce Enable 6" "0: Disable debounce filter.,1: Enable debounce filter."
bitfld.long 0x4 5. "DBEN5,Port n Debounce Enable 5" "0: Disable debounce filter.,1: Enable debounce filter."
newline
bitfld.long 0x4 4. "DBEN4,Port n Debounce Enable 4" "0: Disable debounce filter.,1: Enable debounce filter."
bitfld.long 0x4 3. "DBEN3,Port n Debounce Enable 3" "0: Disable debounce filter.,1: Enable debounce filter."
newline
bitfld.long 0x4 2. "DBEN2,Port n Debounce Enable 2" "0: Disable debounce filter.,1: Enable debounce filter."
bitfld.long 0x4 1. "DBEN1,Port n Debounce Enable 1" "0: Disable debounce filter.,1: Enable debounce filter."
newline
bitfld.long 0x4 0. "DBEN0,Port n Debounce Enable 0" "0: Disable debounce filter.,1: Enable debounce filter."
group.long 0x0++0xB
line.long 0x0 "PE_MOD,Port n Mode Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 30.--31. "MODE15,Port n Mode Selection 15" "0,1,2,3"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 28.--29. "MODE14,Port n Mode Selection 14" "0,1,2,3"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 26.--27. "MODE13,Port n Mode Selection 13" "0,1,2,3"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 24.--25. "MODE12,Port n Mode Selection 12" "0,1,2,3"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 22.--23. "MODE11,Port n Mode Selection 11" "0,1,2,3"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 20.--21. "MODE10,Port n Mode Selection 10" "0,1,2,3"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 18.--19. "MODE9,Port n Mode Selection 9" "0,1,2,3"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 16.--17. "MODE8,Port n Mode Selection 8" "0,1,2,3"
newline
endif
bitfld.long 0x0 14.--15. "MODE7,Port n Mode Selection 7" "0,1,2,3"
bitfld.long 0x0 12.--13. "MODE6,Port n Mode Selection 6" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "MODE5,Port n Mode Selection 5" "0,1,2,3"
bitfld.long 0x0 8.--9. "MODE4,Port n Mode Selection 4" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "MODE3,Port n Mode Selection 3" "0,1,2,3"
bitfld.long 0x0 4.--5. "MODE2,Port n Mode Selection 2" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "MODE1,Port n Mode Selection 1" "0,1,2,3"
bitfld.long 0x0 0.--1. "MODE0,Port n Mode Selection 0" "0,1,2,3"
line.long 0x4 "PE_TYP,Port n Output Type Selection Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x4 15. "TYP15,Port n Output Type Selection 15" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 14. "TYP14,Port n Output Type Selection 14" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 13. "TYP13,Port n Output Type Selection 13" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 12. "TYP12,Port n Output Type Selection 12" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 11. "TYP11,Port n Output Type Selection 11" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 10. "TYP10,Port n Output Type Selection 10" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 9. "TYP9,Port n Output Type Selection 9" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 8. "TYP8,Port n Output Type Selection 8" "0,1"
newline
endif
bitfld.long 0x4 7. "TYP7,Port n Output Type Selection 7" "0,1"
bitfld.long 0x4 6. "TYP6,Port n Output Type Selection 6" "0,1"
newline
bitfld.long 0x4 5. "TYP5,Port n Output Type Selection 5" "0,1"
bitfld.long 0x4 4. "TYP4,Port n Output Type Selection 4" "0,1"
newline
bitfld.long 0x4 3. "TYP3,Port n Output Type Selection 3" "0,1"
bitfld.long 0x4 2. "TYP2,Port n Output Type Selection 2" "0,1"
newline
bitfld.long 0x4 1. "TYP1,Port n Output Type Selection 1" "0,1"
bitfld.long 0x4 0. "TYP0,Port n Output Type Selection 0" "0,1"
line.long 0x8 "PE_AFSR1,Port n Alternative Function Selection Register 1"
hexmask.long.byte 0x8 28.--31. 1. "AFSR7,Port n Alternative Function Selection 7"
hexmask.long.byte 0x8 24.--27. 1. "AFSR6,Port n Alternative Function Selection 6"
newline
hexmask.long.byte 0x8 20.--23. 1. "AFSR5,Port n Alternative Function Selection 5"
hexmask.long.byte 0x8 16.--19. 1. "AFSR4,Port n Alternative Function Selection 4"
newline
hexmask.long.byte 0x8 12.--15. 1. "AFSR3,Port n Alternative Function Selection 3"
hexmask.long.byte 0x8 8.--11. 1. "AFSR2,Port n Alternative Function Selection 2"
newline
hexmask.long.byte 0x8 4.--7. 1. "AFSR1,Port n Alternative Function Selection 1"
hexmask.long.byte 0x8 0.--3. 1. "AFSR0,Port n Alternative Function Selection 0"
group.long 0x10++0x3
line.long 0x0 "PE_PUPD,Port n Pull-Up/Down Selection Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 30.--31. "PUPD15,Port n Pull-Up/Down Resistor Selection 15" "0,1,2,3"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 28.--29. "PUPD14,Port n Pull-Up/Down Resistor Selection 14" "0,1,2,3"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 26.--27. "PUPD13,Port n Pull-Up/Down Resistor Selection 13" "0,1,2,3"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 24.--25. "PUPD12,Port n Pull-Up/Down Resistor Selection 12" "0,1,2,3"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 22.--23. "PUPD11,Port n Pull-Up/Down Resistor Selection 11" "0,1,2,3"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 20.--21. "PUPD10,Port n Pull-Up/Down Resistor Selection 10" "0,1,2,3"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 18.--19. "PUPD9,Port n Pull-Up/Down Resistor Selection 9" "0,1,2,3"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 16.--17. "PUPD8,Port n Pull-Up/Down Resistor Selection 8" "0,1,2,3"
newline
endif
bitfld.long 0x0 14.--15. "PUPD7,Port n Pull-Up/Down Resistor Selection 7" "0,1,2,3"
bitfld.long 0x0 12.--13. "PUPD6,Port n Pull-Up/Down Resistor Selection 6" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "PUPD5,Port n Pull-Up/Down Resistor Selection 5" "0,1,2,3"
bitfld.long 0x0 8.--9. "PUPD4,Port n Pull-Up/Down Resistor Selection 4" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "PUPD3,Port n Pull-Up/Down Resistor Selection 3" "0,1,2,3"
bitfld.long 0x0 4.--5. "PUPD2,Port n Pull-Up/Down Resistor Selection 2" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "PUPD1,Port n Pull-Up/Down Resistor Selection 1" "0,1,2,3"
bitfld.long 0x0 0.--1. "PUPD0,Port n Pull-Up/Down Resistor Selection 0" "0,1,2,3"
rgroup.long 0x14++0x3
line.long 0x0 "PE_INDR,Port n Input Data Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 15. "INDR15,Port n Input Data 15" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 14. "INDR14,Port n Input Data 14" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 13. "INDR13,Port n Input Data 13" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12. "INDR12,Port n Input Data 12" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "INDR11,Port n Input Data 11" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "INDR10,Port n Input Data 10" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "INDR9,Port n Input Data 9" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "INDR8,Port n Input Data 8" "0,1"
newline
endif
bitfld.long 0x0 7. "INDR7,Port n Input Data 7" "0,1"
bitfld.long 0x0 6. "INDR6,Port n Input Data 6" "0,1"
newline
bitfld.long 0x0 5. "INDR5,Port n Input Data 5" "0,1"
bitfld.long 0x0 4. "INDR4,Port n Input Data 4" "0,1"
newline
bitfld.long 0x0 3. "INDR3,Port n Input Data 3" "0,1"
bitfld.long 0x0 2. "INDR2,Port n Input Data 2" "0,1"
newline
bitfld.long 0x0 1. "INDR1,Port n Input Data 1" "0,1"
bitfld.long 0x0 0. "INDR0,Port n Input Data 0" "0,1"
group.long 0x18++0x3
line.long 0x0 "PE_OUTDR,Port n Output Data Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 15. "OUTDR15,Port n Output Data 15" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 14. "OUTDR14,Port n Output Data 14" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 13. "OUTDR13,Port n Output Data 13" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12. "OUTDR12,Port n Output Data 12" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "OUTDR11,Port n Output Data 11" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "OUTDR10,Port n Output Data 10" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "OUTDR9,Port n Output Data 9" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "OUTDR8,Port n Output Data 8" "0,1"
newline
endif
bitfld.long 0x0 7. "OUTDR7,Port n Output Data 7" "0,1"
bitfld.long 0x0 6. "OUTDR6,Port n Output Data 6" "0,1"
newline
bitfld.long 0x0 5. "OUTDR5,Port n Output Data 5" "0,1"
bitfld.long 0x0 4. "OUTDR4,Port n Output Data 4" "0,1"
newline
bitfld.long 0x0 3. "OUTDR3,Port n Output Data 3" "0,1"
bitfld.long 0x0 2. "OUTDR2,Port n Output Data 2" "0,1"
newline
bitfld.long 0x0 1. "OUTDR1,Port n Output Data 1" "0,1"
bitfld.long 0x0 0. "OUTDR0,Port n Output Data 0" "0,1"
wgroup.long 0x1C++0x7
line.long 0x0 "PE_BSR,Port n Output Bit Set Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 15. "BSR15,Port n Output Bit Set 15" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 14. "BSR14,Port n Output Bit Set 14" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 13. "BSR13,Port n Output Bit Set 13" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12. "BSR12,Port n Output Bit Set 12" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "BSR11,Port n Output Bit Set 11" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "BSR10,Port n Output Bit Set 10" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "BSR9,Port n Output Bit Set 9" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "BSR8,Port n Output Bit Set 8" "0,1"
newline
endif
bitfld.long 0x0 7. "BSR7,Port n Output Bit Set 7" "0,1"
bitfld.long 0x0 6. "BSR6,Port n Output Bit Set 6" "0,1"
newline
bitfld.long 0x0 5. "BSR5,Port n Output Bit Set 5" "0,1"
bitfld.long 0x0 4. "BSR4,Port n Output Bit Set 4" "0,1"
newline
bitfld.long 0x0 3. "BSR3,Port n Output Bit Set 3" "0,1"
bitfld.long 0x0 2. "BSR2,Port n Output Bit Set 2" "0,1"
newline
bitfld.long 0x0 1. "BSR1,Port n Output Bit Set 1" "0,1"
bitfld.long 0x0 0. "BSR0,Port n Output Bit Set 0" "0,1"
line.long 0x4 "PE_BCR,Port n Output Bit Clear Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x4 15. "BCR15,Port n Output Bit Clear 15" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 14. "BCR14,Port n Output Bit Clear 14" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 13. "BCR13,Port n Output Bit Clear 13" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 12. "BCR12,Port n Output Bit Clear 12" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 11. "BCR11,Port n Output Bit Clear 11" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 10. "BCR10,Port n Output Bit Clear 10" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 9. "BCR9,Port n Output Bit Clear 9" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 8. "BCR8,Port n Output Bit Clear 8" "0,1"
newline
endif
bitfld.long 0x4 7. "BCR7,Port n Output Bit Clear 7" "0,1"
bitfld.long 0x4 6. "BCR6,Port n Output Bit Clear 6" "0,1"
newline
bitfld.long 0x4 5. "BCR5,Port n Output Bit Clear 5" "0,1"
bitfld.long 0x4 4. "BCR4,Port n Output Bit Clear 4" "0,1"
newline
bitfld.long 0x4 3. "BCR3,Port n Output Bit Clear 3" "0,1"
bitfld.long 0x4 2. "BCR2,Port n Output Bit Clear 2" "0,1"
newline
bitfld.long 0x4 1. "BCR1,Port n Output Bit Clear 1" "0,1"
bitfld.long 0x4 0. "BCR0,Port n Output Bit Clear 0" "0,1"
group.long 0x24++0x7
line.long 0x0 "PE_OUTDMSK,Port n Output Data Mask Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 15. "OUTDMSK15,Port n Output Data Mask 15" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 14. "OUTDMSK14,Port n Output Data Mask 14" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 13. "OUTDMSK13,Port n Output Data Mask 13" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12. "OUTDMSK12,Port n Output Data Mask 12" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "OUTDMSK11,Port n Output Data Mask 11" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "OUTDMSK10,Port n Output Data Mask 10" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "OUTDMSK9,Port n Output Data Mask 9" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "OUTDMSK8,Port n Output Data Mask 8" "0,1"
newline
endif
bitfld.long 0x0 7. "OUTDMSK7,Port n Output Data Mask 7" "0,1"
bitfld.long 0x0 6. "OUTDMSK6,Port n Output Data Mask 6" "0,1"
newline
bitfld.long 0x0 5. "OUTDMSK5,Port n Output Data Mask 5" "0,1"
bitfld.long 0x0 4. "OUTDMSK4,Port n Output Data Mask 4" "0,1"
newline
bitfld.long 0x0 3. "OUTDMSK3,Port n Output Data Mask 3" "0,1"
bitfld.long 0x0 2. "OUTDMSK2,Port n Output Data Mask 2" "0,1"
newline
bitfld.long 0x0 1. "OUTDMSK1,Port n Output Data Mask 1" "0,1"
bitfld.long 0x0 0. "OUTDMSK0,Port n Output Data Mask 0" "0,1"
line.long 0x4 "PE_DBCR,Port n Debounce Control Register"
bitfld.long 0x4 16.--18. "DBCLK,Port n Debounce Filter Sampling Clock Selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 3. "DBEN3,Port n Debounce Enable 3" "0,1"
newline
bitfld.long 0x4 2. "DBEN2,Port n Debounce Enable 2" "0,1"
bitfld.long 0x4 1. "DBEN1,Port n Debounce Enable 1" "0,1"
newline
bitfld.long 0x4 0. "DBEN0,Port n Debounce Enable 0" "0,1"
tree.end
tree "PF"
base ad:0x30000500
group.long 0x0++0xB
line.long 0x0 "MOD,Port n Mode Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 30.--31. "MODE15,Port n Mode Selection 15" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 28.--29. "MODE14,Port n Mode Selection 14" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 26.--27. "MODE13,Port n Mode Selection 13" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 24.--25. "MODE12,Port n Mode Selection 12" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 22.--23. "MODE11,Port n Mode Selection 11" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 20.--21. "MODE10,Port n Mode Selection 10" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 18.--19. "MODE9,Port n Mode Selection 9" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 16.--17. "MODE8,Port n Mode Selection 8" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
endif
bitfld.long 0x0 14.--15. "MODE7,Port n Mode Selection 7" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
bitfld.long 0x0 12.--13. "MODE6,Port n Mode Selection 6" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
bitfld.long 0x0 10.--11. "MODE5,Port n Mode Selection 5" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
bitfld.long 0x0 8.--9. "MODE4,Port n Mode Selection 4" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
bitfld.long 0x0 6.--7. "MODE3,Port n Mode Selection 3" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
bitfld.long 0x0 4.--5. "MODE2,Port n Mode Selection 2" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
bitfld.long 0x0 2.--3. "MODE1,Port n Mode Selection 1" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
bitfld.long 0x0 0.--1. "MODE0,Port n Mode Selection 0" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
line.long 0x4 "TYP,Port n Output Type Selection Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x4 15. "TYP15,Port n Output Type Selection 15" "0: Push-Pull Output,1: Open-Drain Output"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 14. "TYP14,Port n Output Type Selection 14" "0: Push-Pull Output,1: Open-Drain Output"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 13. "TYP13,Port n Output Type Selection 13" "0: Push-Pull Output,1: Open-Drain Output"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 12. "TYP12,Port n Output Type Selection 12" "0: Push-Pull Output,1: Open-Drain Output"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 11. "TYP11,Port n Output Type Selection 11" "0: Push-Pull Output,1: Open-Drain Output"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 10. "TYP10,Port n Output Type Selection 10" "0: Push-Pull Output,1: Open-Drain Output"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 9. "TYP9,Port n Output Type Selection 9" "0: Push-Pull Output,1: Open-Drain Output"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 8. "TYP8,Port n Output Type Selection 8" "0: Push-Pull Output,1: Open-Drain Output"
newline
endif
bitfld.long 0x4 7. "TYP7,Port n Output Type Selection 7" "0: Push-Pull Output,1: Open-Drain Output"
bitfld.long 0x4 6. "TYP6,Port n Output Type Selection 6" "0: Push-Pull Output,1: Open-Drain Output"
newline
bitfld.long 0x4 5. "TYP5,Port n Output Type Selection 5" "0: Push-Pull Output,1: Open-Drain Output"
bitfld.long 0x4 4. "TYP4,Port n Output Type Selection 4" "0: Push-Pull Output,1: Open-Drain Output"
newline
bitfld.long 0x4 3. "TYP3,Port n Output Type Selection 3" "0: Push-Pull Output,1: Open-Drain Output"
bitfld.long 0x4 2. "TYP2,Port n Output Type Selection 2" "0: Push-Pull Output,1: Open-Drain Output"
newline
bitfld.long 0x4 1. "TYP1,Port n Output Type Selection 1" "0: Push-Pull Output,1: Open-Drain Output"
bitfld.long 0x4 0. "TYP0,Port n Output Type Selection 0" "0: Push-Pull Output,1: Open-Drain Output"
line.long 0x8 "AFSR1,Port n Alternative Function Selection Register 1"
hexmask.long.byte 0x8 28.--31. 1. "AFSR7,Port n Alternative Function Selection 7"
hexmask.long.byte 0x8 24.--27. 1. "AFSR6,Port n Alternative Function Selection 6"
newline
hexmask.long.byte 0x8 20.--23. 1. "AFSR5,Port n Alternative Function Selection 5"
hexmask.long.byte 0x8 16.--19. 1. "AFSR4,Port n Alternative Function Selection 4"
newline
hexmask.long.byte 0x8 12.--15. 1. "AFSR3,Port n Alternative Function Selection 3"
hexmask.long.byte 0x8 8.--11. 1. "AFSR2,Port n Alternative Function Selection 2"
newline
hexmask.long.byte 0x8 4.--7. 1. "AFSR1,Port n Alternative Function Selection 1"
hexmask.long.byte 0x8 0.--3. 1. "AFSR0,Port n Alternative Function Selection 0"
sif (cpuis("A31G12?*"))
group.long 0xC++0x3
line.long 0x0 "AFSR2,Port n Alternative Function Selection Register 2"
hexmask.long.byte 0x0 28.--31. 1. "AFSR15,Port n Alternative Function Selection 15"
hexmask.long.byte 0x0 24.--27. 1. "AFSR14,Port n Alternative Function Selection 14"
newline
hexmask.long.byte 0x0 20.--23. 1. "AFSR13,Port n Alternative Function Selection 13"
hexmask.long.byte 0x0 16.--19. 1. "AFSR12,Port n Alternative Function Selection 12"
newline
hexmask.long.byte 0x0 12.--15. 1. "AFSR11,Port n Alternative Function Selection 11"
hexmask.long.byte 0x0 8.--11. 1. "AFSR10,Port n Alternative Function Selection 10"
newline
hexmask.long.byte 0x0 4.--7. 1. "AFSR9,Port n Alternative Function Selection 9"
hexmask.long.byte 0x0 0.--3. 1. "AFSR8,Port n Alternative Function Selection 8"
endif
sif (cpuis("A31G12?*"))
group.long 0xC++0x3
line.long 0x0 "PF_AFSR2,Port n Alternative Function Selection Register 2"
hexmask.long.byte 0x0 12.--15. 1. "AFSR11,Port n Alternative Function Selection 11"
hexmask.long.byte 0x0 8.--11. 1. "AFSR10,Port n Alternative Function Selection 10"
newline
hexmask.long.byte 0x0 4.--7. 1. "AFSR9,Port n Alternative Function Selection 9"
hexmask.long.byte 0x0 0.--3. 1. "AFSR8,Port n Alternative Function Selection 8"
endif
group.long 0x10++0x3
line.long 0x0 "PUPD,Port n Pull-Up/Down Selection Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 30.--31. "PUPD15,Port n Pull-Up/Down Resistor Selection 15" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 28.--29. "PUPD14,Port n Pull-Up/Down Resistor Selection 14" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 26.--27. "PUPD13,Port n Pull-Up/Down Resistor Selection 13" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 24.--25. "PUPD12,Port n Pull-Up/Down Resistor Selection 12" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 22.--23. "PUPD11,Port n Pull-Up/Down Resistor Selection 11" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 20.--21. "PUPD10,Port n Pull-Up/Down Resistor Selection 10" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 18.--19. "PUPD9,Port n Pull-Up/Down Resistor Selection 9" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 16.--17. "PUPD8,Port n Pull-Up/Down Resistor Selection 8" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
endif
bitfld.long 0x0 14.--15. "PUPD7,Port n Pull-Up/Down Resistor Selection 7" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
bitfld.long 0x0 12.--13. "PUPD6,Port n Pull-Up/Down Resistor Selection 6" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
bitfld.long 0x0 10.--11. "PUPD5,Port n Pull-Up/Down Resistor Selection 5" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
bitfld.long 0x0 8.--9. "PUPD4,Port n Pull-Up/Down Resistor Selection 4" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
bitfld.long 0x0 6.--7. "PUPD3,Port n Pull-Up/Down Resistor Selection 3" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
bitfld.long 0x0 4.--5. "PUPD2,Port n Pull-Up/Down Resistor Selection 2" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
bitfld.long 0x0 2.--3. "PUPD1,Port n Pull-Up/Down Resistor Selection 1" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
bitfld.long 0x0 0.--1. "PUPD0,Port n Pull-Up/Down Resistor Selection 0" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
rgroup.long 0x14++0x3
line.long 0x0 "INDR,Port n Input Data Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 15. "INDR15,Port n Input Data 15" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 14. "INDR14,Port n Input Data 14" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 13. "INDR13,Port n Input Data 13" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12. "INDR12,Port n Input Data 12" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "INDR11,Port n Input Data 11" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "INDR10,Port n Input Data 10" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "INDR9,Port n Input Data 9" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "INDR8,Port n Input Data 8" "0,1"
newline
endif
bitfld.long 0x0 7. "INDR7,Port n Input Data 7" "0,1"
bitfld.long 0x0 6. "INDR6,Port n Input Data 6" "0,1"
newline
bitfld.long 0x0 5. "INDR5,Port n Input Data 5" "0,1"
bitfld.long 0x0 4. "INDR4,Port n Input Data 4" "0,1"
newline
bitfld.long 0x0 3. "INDR3,Port n Input Data 3" "0,1"
bitfld.long 0x0 2. "INDR2,Port n Input Data 2" "0,1"
newline
bitfld.long 0x0 1. "INDR1,Port n Input Data 1" "0,1"
bitfld.long 0x0 0. "INDR0,Port n Input Data 0" "0,1"
group.long 0x18++0x3
line.long 0x0 "OUTDR,Port n Output Data Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 15. "OUTDR15,Port n Output Data 15" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 14. "OUTDR14,Port n Output Data 14" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 13. "OUTDR13,Port n Output Data 13" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12. "OUTDR12,Port n Output Data 12" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "OUTDR11,Port n Output Data 11" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "OUTDR10,Port n Output Data 10" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "OUTDR9,Port n Output Data 9" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "OUTDR8,Port n Output Data 8" "0,1"
newline
endif
bitfld.long 0x0 7. "OUTDR7,Port n Output Data 7" "0,1"
bitfld.long 0x0 6. "OUTDR6,Port n Output Data 6" "0,1"
newline
bitfld.long 0x0 5. "OUTDR5,Port n Output Data 5" "0,1"
bitfld.long 0x0 4. "OUTDR4,Port n Output Data 4" "0,1"
newline
bitfld.long 0x0 3. "OUTDR3,Port n Output Data 3" "0,1"
bitfld.long 0x0 2. "OUTDR2,Port n Output Data 2" "0,1"
newline
bitfld.long 0x0 1. "OUTDR1,Port n Output Data 1" "0,1"
bitfld.long 0x0 0. "OUTDR0,Port n Output Data 0" "0,1"
wgroup.long 0x1C++0x7
line.long 0x0 "BSR,Port n Output Bit Set Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 15. "BSR15,Port n Output Bit Set 15" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 14. "BSR14,Port n Output Bit Set 14" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 13. "BSR13,Port n Output Bit Set 13" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12. "BSR12,Port n Output Bit Set 12" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "BSR11,Port n Output Bit Set 11" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "BSR10,Port n Output Bit Set 10" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "BSR9,Port n Output Bit Set 9" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "BSR8,Port n Output Bit Set 8" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
endif
bitfld.long 0x0 7. "BSR7,Port n Output Bit Set 7" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
bitfld.long 0x0 6. "BSR6,Port n Output Bit Set 6" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
bitfld.long 0x0 5. "BSR5,Port n Output Bit Set 5" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
bitfld.long 0x0 4. "BSR4,Port n Output Bit Set 4" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
bitfld.long 0x0 3. "BSR3,Port n Output Bit Set 3" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
bitfld.long 0x0 2. "BSR2,Port n Output Bit Set 2" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
bitfld.long 0x0 1. "BSR1,Port n Output Bit Set 1" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
bitfld.long 0x0 0. "BSR0,Port n Output Bit Set 0" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
line.long 0x4 "BCR,Port n Output Bit Clear Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x4 15. "BCR15,Port n Output Bit Clear 15" "0: No effect.,1: Clear the corresponding OUTDRx bit."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 14. "BCR14,Port n Output Bit Clear 14" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 13. "BCR13,Port n Output Bit Clear 13" "0: No effect.,1: Clear the corresponding OUTDRx bit."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 12. "BCR12,Port n Output Bit Clear 12" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 11. "BCR11,Port n Output Bit Clear 11" "0: No effect.,1: Clear the corresponding OUTDRx bit."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 10. "BCR10,Port n Output Bit Clear 10" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 9. "BCR9,Port n Output Bit Clear 9" "0: No effect.,1: Clear the corresponding OUTDRx bit."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 8. "BCR8,Port n Output Bit Clear 8" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
endif
bitfld.long 0x4 7. "BCR7,Port n Output Bit Clear 7" "0: No effect.,1: Clear the corresponding OUTDRx bit."
bitfld.long 0x4 6. "BCR6,Port n Output Bit Clear 6" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
bitfld.long 0x4 5. "BCR5,Port n Output Bit Clear 5" "0: No effect.,1: Clear the corresponding OUTDRx bit."
bitfld.long 0x4 4. "BCR4,Port n Output Bit Clear 4" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
bitfld.long 0x4 3. "BCR3,Port n Output Bit Clear 3" "0: No effect.,1: Clear the corresponding OUTDRx bit."
bitfld.long 0x4 2. "BCR2,Port n Output Bit Clear 2" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
bitfld.long 0x4 1. "BCR1,Port n Output Bit Clear 1" "0: No effect.,1: Clear the corresponding OUTDRx bit."
bitfld.long 0x4 0. "BCR0,Port n Output Bit Clear 0" "0: No effect.,1: Clear the corresponding OUTDRx bit."
group.long 0x24++0x7
line.long 0x0 "OUTDMSK,Port n Output Data Mask Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 15. "OUTDMSK15,Port n Output Data Mask 15" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 14. "OUTDMSK14,Port n Output Data Mask 14" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 13. "OUTDMSK13,Port n Output Data Mask 13" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12. "OUTDMSK12,Port n Output Data Mask 12" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "OUTDMSK11,Port n Output Data Mask 11" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "OUTDMSK10,Port n Output Data Mask 10" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "OUTDMSK9,Port n Output Data Mask 9" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "OUTDMSK8,Port n Output Data Mask 8" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
endif
bitfld.long 0x0 7. "OUTDMSK7,Port n Output Data Mask 7" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
bitfld.long 0x0 6. "OUTDMSK6,Port n Output Data Mask 6" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
bitfld.long 0x0 5. "OUTDMSK5,Port n Output Data Mask 5" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
bitfld.long 0x0 4. "OUTDMSK4,Port n Output Data Mask 4" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
bitfld.long 0x0 3. "OUTDMSK3,Port n Output Data Mask 3" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
bitfld.long 0x0 2. "OUTDMSK2,Port n Output Data Mask 2" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
bitfld.long 0x0 1. "OUTDMSK1,Port n Output Data Mask 1" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
bitfld.long 0x0 0. "OUTDMSK0,Port n Output Data Mask 0" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
line.long 0x4 "DBCR,Port n Debounce Control Register"
bitfld.long 0x4 16.--18. "DBCLK,Port n Debounce Filter Sampling Clock Selection" "0: HCLK/1,1: HCLK/4,2: HCLK/16,3: HCLK/64,4: HCLK/256,5: HCLK/1024,?,?"
sif (cpuis("A31G12?*"))
bitfld.long 0x4 11. "DBEN11,Port n Debounce Enable 11" "0: Disable debounce filter.,1: Enable debounce filter."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 10. "DBEN10,Port n Debounce Enable 10" "0: Disable debounce filter.,1: Enable debounce filter."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 9. "DBEN9,Port n Debounce Enable 9" "0: Disable debounce filter.,1: Enable debounce filter."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 8. "DBEN8,Port n Debounce Enable 8" "0: Disable debounce filter.,1: Enable debounce filter."
endif
bitfld.long 0x4 7. "DBEN7,Port n Debounce Enable 7" "0: Disable debounce filter.,1: Enable debounce filter."
newline
bitfld.long 0x4 6. "DBEN6,Port n Debounce Enable 6" "0: Disable debounce filter.,1: Enable debounce filter."
bitfld.long 0x4 5. "DBEN5,Port n Debounce Enable 5" "0: Disable debounce filter.,1: Enable debounce filter."
newline
bitfld.long 0x4 4. "DBEN4,Port n Debounce Enable 4" "0: Disable debounce filter.,1: Enable debounce filter."
bitfld.long 0x4 3. "DBEN3,Port n Debounce Enable 3" "0: Disable debounce filter.,1: Enable debounce filter."
newline
bitfld.long 0x4 2. "DBEN2,Port n Debounce Enable 2" "0: Disable debounce filter.,1: Enable debounce filter."
bitfld.long 0x4 1. "DBEN1,Port n Debounce Enable 1" "0: Disable debounce filter.,1: Enable debounce filter."
newline
bitfld.long 0x4 0. "DBEN0,Port n Debounce Enable 0" "0: Disable debounce filter.,1: Enable debounce filter."
group.long 0x0++0xB
line.long 0x0 "PF_MOD,Port n Mode Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 22.--23. "MODE11,Port n Mode Selection 11" "0,1,2,3"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 20.--21. "MODE10,Port n Mode Selection 10" "0,1,2,3"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 18.--19. "MODE9,Port n Mode Selection 9" "0,1,2,3"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 16.--17. "MODE8,Port n Mode Selection 8" "0,1,2,3"
newline
endif
bitfld.long 0x0 14.--15. "MODE7,Port n Mode Selection 7" "0,1,2,3"
bitfld.long 0x0 12.--13. "MODE6,Port n Mode Selection 6" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "MODE5,Port n Mode Selection 5" "0,1,2,3"
bitfld.long 0x0 8.--9. "MODE4,Port n Mode Selection 4" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "MODE3,Port n Mode Selection 3" "0,1,2,3"
bitfld.long 0x0 4.--5. "MODE2,Port n Mode Selection 2" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "MODE1,Port n Mode Selection 1" "0,1,2,3"
bitfld.long 0x0 0.--1. "MODE0,Port n Mode Selection 0" "0,1,2,3"
line.long 0x4 "PF_TYP,Port n Output Type Selection Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x4 11. "TYP11,Port n Output Type Selection 11" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 10. "TYP10,Port n Output Type Selection 10" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 9. "TYP9,Port n Output Type Selection 9" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 8. "TYP8,Port n Output Type Selection 8" "0,1"
newline
endif
bitfld.long 0x4 7. "TYP7,Port n Output Type Selection 7" "0,1"
bitfld.long 0x4 6. "TYP6,Port n Output Type Selection 6" "0,1"
newline
bitfld.long 0x4 5. "TYP5,Port n Output Type Selection 5" "0,1"
bitfld.long 0x4 4. "TYP4,Port n Output Type Selection 4" "0,1"
newline
bitfld.long 0x4 3. "TYP3,Port n Output Type Selection 3" "0,1"
bitfld.long 0x4 2. "TYP2,Port n Output Type Selection 2" "0,1"
newline
bitfld.long 0x4 1. "TYP1,Port n Output Type Selection 1" "0,1"
bitfld.long 0x4 0. "TYP0,Port n Output Type Selection 0" "0,1"
line.long 0x8 "PF_AFSR1,Port n Alternative Function Selection Register 1"
hexmask.long.byte 0x8 28.--31. 1. "AFSR7,Port n Alternative Function Selection 7"
hexmask.long.byte 0x8 24.--27. 1. "AFSR6,Port n Alternative Function Selection 6"
newline
hexmask.long.byte 0x8 20.--23. 1. "AFSR5,Port n Alternative Function Selection 5"
hexmask.long.byte 0x8 16.--19. 1. "AFSR4,Port n Alternative Function Selection 4"
newline
hexmask.long.byte 0x8 12.--15. 1. "AFSR3,Port n Alternative Function Selection 3"
hexmask.long.byte 0x8 8.--11. 1. "AFSR2,Port n Alternative Function Selection 2"
newline
hexmask.long.byte 0x8 4.--7. 1. "AFSR1,Port n Alternative Function Selection 1"
hexmask.long.byte 0x8 0.--3. 1. "AFSR0,Port n Alternative Function Selection 0"
group.long 0x10++0x3
line.long 0x0 "PF_PUPD,Port n Pull-Up/Down Selection Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 22.--23. "PUPD11,Port n Pull-Up/Down Resistor Selection 11" "0,1,2,3"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 20.--21. "PUPD10,Port n Pull-Up/Down Resistor Selection 10" "0,1,2,3"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 18.--19. "PUPD9,Port n Pull-Up/Down Resistor Selection 9" "0,1,2,3"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 16.--17. "PUPD8,Port n Pull-Up/Down Resistor Selection 8" "0,1,2,3"
newline
endif
bitfld.long 0x0 14.--15. "PUPD7,Port n Pull-Up/Down Resistor Selection 7" "0,1,2,3"
bitfld.long 0x0 12.--13. "PUPD6,Port n Pull-Up/Down Resistor Selection 6" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "PUPD5,Port n Pull-Up/Down Resistor Selection 5" "0,1,2,3"
bitfld.long 0x0 8.--9. "PUPD4,Port n Pull-Up/Down Resistor Selection 4" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "PUPD3,Port n Pull-Up/Down Resistor Selection 3" "0,1,2,3"
bitfld.long 0x0 4.--5. "PUPD2,Port n Pull-Up/Down Resistor Selection 2" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "PUPD1,Port n Pull-Up/Down Resistor Selection 1" "0,1,2,3"
bitfld.long 0x0 0.--1. "PUPD0,Port n Pull-Up/Down Resistor Selection 0" "0,1,2,3"
rgroup.long 0x14++0x3
line.long 0x0 "PF_INDR,Port n Input Data Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "INDR11,Port n Input Data 11" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "INDR10,Port n Input Data 10" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "INDR9,Port n Input Data 9" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "INDR8,Port n Input Data 8" "0,1"
newline
endif
bitfld.long 0x0 7. "INDR7,Port n Input Data 7" "0,1"
bitfld.long 0x0 6. "INDR6,Port n Input Data 6" "0,1"
newline
bitfld.long 0x0 5. "INDR5,Port n Input Data 5" "0,1"
bitfld.long 0x0 4. "INDR4,Port n Input Data 4" "0,1"
newline
bitfld.long 0x0 3. "INDR3,Port n Input Data 3" "0,1"
bitfld.long 0x0 2. "INDR2,Port n Input Data 2" "0,1"
newline
bitfld.long 0x0 1. "INDR1,Port n Input Data 1" "0,1"
bitfld.long 0x0 0. "INDR0,Port n Input Data 0" "0,1"
group.long 0x18++0x3
line.long 0x0 "PF_OUTDR,Port n Output Data Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "OUTDR11,Port n Output Data 11" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "OUTDR10,Port n Output Data 10" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "OUTDR9,Port n Output Data 9" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "OUTDR8,Port n Output Data 8" "0,1"
newline
endif
bitfld.long 0x0 7. "OUTDR7,Port n Output Data 7" "0,1"
bitfld.long 0x0 6. "OUTDR6,Port n Output Data 6" "0,1"
newline
bitfld.long 0x0 5. "OUTDR5,Port n Output Data 5" "0,1"
bitfld.long 0x0 4. "OUTDR4,Port n Output Data 4" "0,1"
newline
bitfld.long 0x0 3. "OUTDR3,Port n Output Data 3" "0,1"
bitfld.long 0x0 2. "OUTDR2,Port n Output Data 2" "0,1"
newline
bitfld.long 0x0 1. "OUTDR1,Port n Output Data 1" "0,1"
bitfld.long 0x0 0. "OUTDR0,Port n Output Data 0" "0,1"
wgroup.long 0x1C++0x7
line.long 0x0 "PF_BSR,Port n Output Bit Set Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "BSR11,Port n Output Bit Set 11" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "BSR10,Port n Output Bit Set 10" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "BSR9,Port n Output Bit Set 9" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "BSR8,Port n Output Bit Set 8" "0,1"
newline
endif
bitfld.long 0x0 7. "BSR7,Port n Output Bit Set 7" "0,1"
bitfld.long 0x0 6. "BSR6,Port n Output Bit Set 6" "0,1"
newline
bitfld.long 0x0 5. "BSR5,Port n Output Bit Set 5" "0,1"
bitfld.long 0x0 4. "BSR4,Port n Output Bit Set 4" "0,1"
newline
bitfld.long 0x0 3. "BSR3,Port n Output Bit Set 3" "0,1"
bitfld.long 0x0 2. "BSR2,Port n Output Bit Set 2" "0,1"
newline
bitfld.long 0x0 1. "BSR1,Port n Output Bit Set 1" "0,1"
bitfld.long 0x0 0. "BSR0,Port n Output Bit Set 0" "0,1"
line.long 0x4 "PF_BCR,Port n Output Bit Clear Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x4 11. "BCR11,Port n Output Bit Clear 11" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 10. "BCR10,Port n Output Bit Clear 10" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 9. "BCR9,Port n Output Bit Clear 9" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 8. "BCR8,Port n Output Bit Clear 8" "0,1"
newline
endif
bitfld.long 0x4 7. "BCR7,Port n Output Bit Clear 7" "0,1"
bitfld.long 0x4 6. "BCR6,Port n Output Bit Clear 6" "0,1"
newline
bitfld.long 0x4 5. "BCR5,Port n Output Bit Clear 5" "0,1"
bitfld.long 0x4 4. "BCR4,Port n Output Bit Clear 4" "0,1"
newline
bitfld.long 0x4 3. "BCR3,Port n Output Bit Clear 3" "0,1"
bitfld.long 0x4 2. "BCR2,Port n Output Bit Clear 2" "0,1"
newline
bitfld.long 0x4 1. "BCR1,Port n Output Bit Clear 1" "0,1"
bitfld.long 0x4 0. "BCR0,Port n Output Bit Clear 0" "0,1"
group.long 0x24++0x3
line.long 0x0 "PF_OUTDMSK,Port n Output Data Mask Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "OUTDMSK11,Port n Output Data Mask 11" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "OUTDMSK10,Port n Output Data Mask 10" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "OUTDMSK9,Port n Output Data Mask 9" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "OUTDMSK8,Port n Output Data Mask 8" "0,1"
newline
endif
bitfld.long 0x0 7. "OUTDMSK7,Port n Output Data Mask 7" "0,1"
bitfld.long 0x0 6. "OUTDMSK6,Port n Output Data Mask 6" "0,1"
newline
bitfld.long 0x0 5. "OUTDMSK5,Port n Output Data Mask 5" "0,1"
bitfld.long 0x0 4. "OUTDMSK4,Port n Output Data Mask 4" "0,1"
newline
bitfld.long 0x0 3. "OUTDMSK3,Port n Output Data Mask 3" "0,1"
bitfld.long 0x0 2. "OUTDMSK2,Port n Output Data Mask 2" "0,1"
newline
bitfld.long 0x0 1. "OUTDMSK1,Port n Output Data Mask 1" "0,1"
bitfld.long 0x0 0. "OUTDMSK0,Port n Output Data Mask 0" "0,1"
tree.end
tree "Pn"
base ad:0x50000000
group.long 0x0++0xB
line.long 0x0 "MOD,Port n Mode Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 30.--31. "MODE15,Port n Mode Selection 15" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 28.--29. "MODE14,Port n Mode Selection 14" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 26.--27. "MODE13,Port n Mode Selection 13" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 24.--25. "MODE12,Port n Mode Selection 12" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 22.--23. "MODE11,Port n Mode Selection 11" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 20.--21. "MODE10,Port n Mode Selection 10" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 18.--19. "MODE9,Port n Mode Selection 9" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 16.--17. "MODE8,Port n Mode Selection 8" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
endif
bitfld.long 0x0 14.--15. "MODE7,Port n Mode Selection 7" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
bitfld.long 0x0 12.--13. "MODE6,Port n Mode Selection 6" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
bitfld.long 0x0 10.--11. "MODE5,Port n Mode Selection 5" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
bitfld.long 0x0 8.--9. "MODE4,Port n Mode Selection 4" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
bitfld.long 0x0 6.--7. "MODE3,Port n Mode Selection 3" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
bitfld.long 0x0 4.--5. "MODE2,Port n Mode Selection 2" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
newline
bitfld.long 0x0 2.--3. "MODE1,Port n Mode Selection 1" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
bitfld.long 0x0 0.--1. "MODE0,Port n Mode Selection 0" "0: Input Mode,1: Output Mode,2: Alternative Function Mode,?"
line.long 0x4 "TYP,Port n Output Type Selection Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x4 15. "TYP15,Port n Output Type Selection 15" "0: Push-Pull Output,1: Open-Drain Output"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 14. "TYP14,Port n Output Type Selection 14" "0: Push-Pull Output,1: Open-Drain Output"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 13. "TYP13,Port n Output Type Selection 13" "0: Push-Pull Output,1: Open-Drain Output"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 12. "TYP12,Port n Output Type Selection 12" "0: Push-Pull Output,1: Open-Drain Output"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 11. "TYP11,Port n Output Type Selection 11" "0: Push-Pull Output,1: Open-Drain Output"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 10. "TYP10,Port n Output Type Selection 10" "0: Push-Pull Output,1: Open-Drain Output"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 9. "TYP9,Port n Output Type Selection 9" "0: Push-Pull Output,1: Open-Drain Output"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 8. "TYP8,Port n Output Type Selection 8" "0: Push-Pull Output,1: Open-Drain Output"
newline
endif
bitfld.long 0x4 7. "TYP7,Port n Output Type Selection 7" "0: Push-Pull Output,1: Open-Drain Output"
bitfld.long 0x4 6. "TYP6,Port n Output Type Selection 6" "0: Push-Pull Output,1: Open-Drain Output"
newline
bitfld.long 0x4 5. "TYP5,Port n Output Type Selection 5" "0: Push-Pull Output,1: Open-Drain Output"
bitfld.long 0x4 4. "TYP4,Port n Output Type Selection 4" "0: Push-Pull Output,1: Open-Drain Output"
newline
bitfld.long 0x4 3. "TYP3,Port n Output Type Selection 3" "0: Push-Pull Output,1: Open-Drain Output"
bitfld.long 0x4 2. "TYP2,Port n Output Type Selection 2" "0: Push-Pull Output,1: Open-Drain Output"
newline
bitfld.long 0x4 1. "TYP1,Port n Output Type Selection 1" "0: Push-Pull Output,1: Open-Drain Output"
bitfld.long 0x4 0. "TYP0,Port n Output Type Selection 0" "0: Push-Pull Output,1: Open-Drain Output"
line.long 0x8 "AFSR1,Port n Alternative Function Selection Register 1"
hexmask.long.byte 0x8 28.--31. 1. "AFSR7,Port n Alternative Function Selection 7"
hexmask.long.byte 0x8 24.--27. 1. "AFSR6,Port n Alternative Function Selection 6"
newline
hexmask.long.byte 0x8 20.--23. 1. "AFSR5,Port n Alternative Function Selection 5"
hexmask.long.byte 0x8 16.--19. 1. "AFSR4,Port n Alternative Function Selection 4"
newline
hexmask.long.byte 0x8 12.--15. 1. "AFSR3,Port n Alternative Function Selection 3"
hexmask.long.byte 0x8 8.--11. 1. "AFSR2,Port n Alternative Function Selection 2"
newline
hexmask.long.byte 0x8 4.--7. 1. "AFSR1,Port n Alternative Function Selection 1"
hexmask.long.byte 0x8 0.--3. 1. "AFSR0,Port n Alternative Function Selection 0"
sif (cpuis("A31G12?*"))
group.long 0xC++0x3
line.long 0x0 "AFSR2,Port n Alternative Function Selection Register 2"
hexmask.long.byte 0x0 28.--31. 1. "AFSR15,Port n Alternative Function Selection 15"
hexmask.long.byte 0x0 24.--27. 1. "AFSR14,Port n Alternative Function Selection 14"
newline
hexmask.long.byte 0x0 20.--23. 1. "AFSR13,Port n Alternative Function Selection 13"
hexmask.long.byte 0x0 16.--19. 1. "AFSR12,Port n Alternative Function Selection 12"
newline
hexmask.long.byte 0x0 12.--15. 1. "AFSR11,Port n Alternative Function Selection 11"
hexmask.long.byte 0x0 8.--11. 1. "AFSR10,Port n Alternative Function Selection 10"
newline
hexmask.long.byte 0x0 4.--7. 1. "AFSR9,Port n Alternative Function Selection 9"
hexmask.long.byte 0x0 0.--3. 1. "AFSR8,Port n Alternative Function Selection 8"
endif
group.long 0x10++0x3
line.long 0x0 "PUPD,Port n Pull-Up/Down Selection Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 30.--31. "PUPD15,Port n Pull-Up/Down Resistor Selection 15" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 28.--29. "PUPD14,Port n Pull-Up/Down Resistor Selection 14" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 26.--27. "PUPD13,Port n Pull-Up/Down Resistor Selection 13" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 24.--25. "PUPD12,Port n Pull-Up/Down Resistor Selection 12" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 22.--23. "PUPD11,Port n Pull-Up/Down Resistor Selection 11" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 20.--21. "PUPD10,Port n Pull-Up/Down Resistor Selection 10" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 18.--19. "PUPD9,Port n Pull-Up/Down Resistor Selection 9" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 16.--17. "PUPD8,Port n Pull-Up/Down Resistor Selection 8" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
endif
bitfld.long 0x0 14.--15. "PUPD7,Port n Pull-Up/Down Resistor Selection 7" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
bitfld.long 0x0 12.--13. "PUPD6,Port n Pull-Up/Down Resistor Selection 6" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
bitfld.long 0x0 10.--11. "PUPD5,Port n Pull-Up/Down Resistor Selection 5" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
bitfld.long 0x0 8.--9. "PUPD4,Port n Pull-Up/Down Resistor Selection 4" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
bitfld.long 0x0 6.--7. "PUPD3,Port n Pull-Up/Down Resistor Selection 3" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
bitfld.long 0x0 4.--5. "PUPD2,Port n Pull-Up/Down Resistor Selection 2" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
newline
bitfld.long 0x0 2.--3. "PUPD1,Port n Pull-Up/Down Resistor Selection 1" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
bitfld.long 0x0 0.--1. "PUPD0,Port n Pull-Up/Down Resistor Selection 0" "0: Disable pull-up/down resistor.,1: Enable pull-up resistor.,2: Enable pull-down resistor.,?"
rgroup.long 0x14++0x3
line.long 0x0 "INDR,Port n Input Data Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 15. "INDR15,Port n Input Data 15" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 14. "INDR14,Port n Input Data 14" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 13. "INDR13,Port n Input Data 13" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12. "INDR12,Port n Input Data 12" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "INDR11,Port n Input Data 11" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "INDR10,Port n Input Data 10" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "INDR9,Port n Input Data 9" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "INDR8,Port n Input Data 8" "0,1"
newline
endif
bitfld.long 0x0 7. "INDR7,Port n Input Data 7" "0,1"
bitfld.long 0x0 6. "INDR6,Port n Input Data 6" "0,1"
newline
bitfld.long 0x0 5. "INDR5,Port n Input Data 5" "0,1"
bitfld.long 0x0 4. "INDR4,Port n Input Data 4" "0,1"
newline
bitfld.long 0x0 3. "INDR3,Port n Input Data 3" "0,1"
bitfld.long 0x0 2. "INDR2,Port n Input Data 2" "0,1"
newline
bitfld.long 0x0 1. "INDR1,Port n Input Data 1" "0,1"
bitfld.long 0x0 0. "INDR0,Port n Input Data 0" "0,1"
group.long 0x18++0x3
line.long 0x0 "OUTDR,Port n Output Data Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 15. "OUTDR15,Port n Output Data 15" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 14. "OUTDR14,Port n Output Data 14" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 13. "OUTDR13,Port n Output Data 13" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12. "OUTDR12,Port n Output Data 12" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "OUTDR11,Port n Output Data 11" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "OUTDR10,Port n Output Data 10" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "OUTDR9,Port n Output Data 9" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "OUTDR8,Port n Output Data 8" "0,1"
newline
endif
bitfld.long 0x0 7. "OUTDR7,Port n Output Data 7" "0,1"
bitfld.long 0x0 6. "OUTDR6,Port n Output Data 6" "0,1"
newline
bitfld.long 0x0 5. "OUTDR5,Port n Output Data 5" "0,1"
bitfld.long 0x0 4. "OUTDR4,Port n Output Data 4" "0,1"
newline
bitfld.long 0x0 3. "OUTDR3,Port n Output Data 3" "0,1"
bitfld.long 0x0 2. "OUTDR2,Port n Output Data 2" "0,1"
newline
bitfld.long 0x0 1. "OUTDR1,Port n Output Data 1" "0,1"
bitfld.long 0x0 0. "OUTDR0,Port n Output Data 0" "0,1"
wgroup.long 0x1C++0x7
line.long 0x0 "BSR,Port n Output Bit Set Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 15. "BSR15,Port n Output Bit Set 15" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 14. "BSR14,Port n Output Bit Set 14" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 13. "BSR13,Port n Output Bit Set 13" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12. "BSR12,Port n Output Bit Set 12" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "BSR11,Port n Output Bit Set 11" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "BSR10,Port n Output Bit Set 10" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "BSR9,Port n Output Bit Set 9" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "BSR8,Port n Output Bit Set 8" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
endif
bitfld.long 0x0 7. "BSR7,Port n Output Bit Set 7" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
bitfld.long 0x0 6. "BSR6,Port n Output Bit Set 6" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
bitfld.long 0x0 5. "BSR5,Port n Output Bit Set 5" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
bitfld.long 0x0 4. "BSR4,Port n Output Bit Set 4" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
bitfld.long 0x0 3. "BSR3,Port n Output Bit Set 3" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
bitfld.long 0x0 2. "BSR2,Port n Output Bit Set 2" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
newline
bitfld.long 0x0 1. "BSR1,Port n Output Bit Set 1" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
bitfld.long 0x0 0. "BSR0,Port n Output Bit Set 0" "0: No effect.,1: Set the corresponding OUTDRx bit (Automatically.."
line.long 0x4 "BCR,Port n Output Bit Clear Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x4 15. "BCR15,Port n Output Bit Clear 15" "0: No effect.,1: Clear the corresponding OUTDRx bit."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 14. "BCR14,Port n Output Bit Clear 14" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 13. "BCR13,Port n Output Bit Clear 13" "0: No effect.,1: Clear the corresponding OUTDRx bit."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 12. "BCR12,Port n Output Bit Clear 12" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 11. "BCR11,Port n Output Bit Clear 11" "0: No effect.,1: Clear the corresponding OUTDRx bit."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 10. "BCR10,Port n Output Bit Clear 10" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 9. "BCR9,Port n Output Bit Clear 9" "0: No effect.,1: Clear the corresponding OUTDRx bit."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 8. "BCR8,Port n Output Bit Clear 8" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
endif
bitfld.long 0x4 7. "BCR7,Port n Output Bit Clear 7" "0: No effect.,1: Clear the corresponding OUTDRx bit."
bitfld.long 0x4 6. "BCR6,Port n Output Bit Clear 6" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
bitfld.long 0x4 5. "BCR5,Port n Output Bit Clear 5" "0: No effect.,1: Clear the corresponding OUTDRx bit."
bitfld.long 0x4 4. "BCR4,Port n Output Bit Clear 4" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
bitfld.long 0x4 3. "BCR3,Port n Output Bit Clear 3" "0: No effect.,1: Clear the corresponding OUTDRx bit."
bitfld.long 0x4 2. "BCR2,Port n Output Bit Clear 2" "0: No effect.,1: Clear the corresponding OUTDRx bit."
newline
bitfld.long 0x4 1. "BCR1,Port n Output Bit Clear 1" "0: No effect.,1: Clear the corresponding OUTDRx bit."
bitfld.long 0x4 0. "BCR0,Port n Output Bit Clear 0" "0: No effect.,1: Clear the corresponding OUTDRx bit."
group.long 0x24++0x7
line.long 0x0 "OUTDMSK,Port n Output Data Mask Register"
sif (cpuis("A31G12?*"))
bitfld.long 0x0 15. "OUTDMSK15,Port n Output Data Mask 15" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 14. "OUTDMSK14,Port n Output Data Mask 14" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 13. "OUTDMSK13,Port n Output Data Mask 13" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 12. "OUTDMSK12,Port n Output Data Mask 12" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "OUTDMSK11,Port n Output Data Mask 11" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "OUTDMSK10,Port n Output Data Mask 10" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "OUTDMSK9,Port n Output Data Mask 9" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "OUTDMSK8,Port n Output Data Mask 8" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
endif
bitfld.long 0x0 7. "OUTDMSK7,Port n Output Data Mask 7" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
bitfld.long 0x0 6. "OUTDMSK6,Port n Output Data Mask 6" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
bitfld.long 0x0 5. "OUTDMSK5,Port n Output Data Mask 5" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
bitfld.long 0x0 4. "OUTDMSK4,Port n Output Data Mask 4" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
bitfld.long 0x0 3. "OUTDMSK3,Port n Output Data Mask 3" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
bitfld.long 0x0 2. "OUTDMSK2,Port n Output Data Mask 2" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
newline
bitfld.long 0x0 1. "OUTDMSK1,Port n Output Data Mask 1" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
bitfld.long 0x0 0. "OUTDMSK0,Port n Output Data Mask 0" "0: Unmask. The corresponding OUTDRx bit can be..,1: Mask. The corresponding OUTDRx bit is protected."
line.long 0x4 "DBCR,Port n Debounce Control Register"
bitfld.long 0x4 16.--18. "DBCLK,Port n Debounce Filter Sampling Clock Selection" "0: HCLK/1,1: HCLK/4,2: HCLK/16,3: HCLK/64,4: HCLK/256,5: HCLK/1024,?,?"
sif (cpuis("A31G12?*"))
bitfld.long 0x4 11. "DBEN11,Port n Debounce Enable 11" "0: Disable debounce filter.,1: Enable debounce filter."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 10. "DBEN10,Port n Debounce Enable 10" "0: Disable debounce filter.,1: Enable debounce filter."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 9. "DBEN9,Port n Debounce Enable 9" "0: Disable debounce filter.,1: Enable debounce filter."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 8. "DBEN8,Port n Debounce Enable 8" "0: Disable debounce filter.,1: Enable debounce filter."
endif
bitfld.long 0x4 7. "DBEN7,Port n Debounce Enable 7" "0: Disable debounce filter.,1: Enable debounce filter."
newline
bitfld.long 0x4 6. "DBEN6,Port n Debounce Enable 6" "0: Disable debounce filter.,1: Enable debounce filter."
bitfld.long 0x4 5. "DBEN5,Port n Debounce Enable 5" "0: Disable debounce filter.,1: Enable debounce filter."
newline
bitfld.long 0x4 4. "DBEN4,Port n Debounce Enable 4" "0: Disable debounce filter.,1: Enable debounce filter."
bitfld.long 0x4 3. "DBEN3,Port n Debounce Enable 3" "0: Disable debounce filter.,1: Enable debounce filter."
newline
bitfld.long 0x4 2. "DBEN2,Port n Debounce Enable 2" "0: Disable debounce filter.,1: Enable debounce filter."
bitfld.long 0x4 1. "DBEN1,Port n Debounce Enable 1" "0: Disable debounce filter.,1: Enable debounce filter."
newline
bitfld.long 0x4 0. "DBEN0,Port n Debounce Enable 0" "0: Disable debounce filter.,1: Enable debounce filter."
tree.end
tree.end
tree "SCU (System Control Unit)"
base ad:0x0
tree "SCUCC (Chip Configuration)"
base ad:0x4000F000
rgroup.long 0x0++0xB
line.long 0x0 "VENDORID,Vendor Identification Register"
hexmask.long 0x0 0.--31. 1. "VENDID,Vendor Identification"
line.long 0x4 "CHIPID,Chip Identification Register"
hexmask.long 0x4 0.--31. 1. "CHIPID,Chip Identification"
line.long 0x8 "REVNR,Revision Number Register"
hexmask.long.byte 0x8 0.--7. 1. "REVNO,Chip Revision Number"
group.long 0x14++0xF
line.long 0x0 "PMREMAP,Program Memory Remap Register"
hexmask.long.word 0x0 16.--31. 1. "WTIDKY,Write Identification Key (0xe2f1)"
hexmask.long.byte 0x0 8.--15. 1. "nPMREM,Write Complement Key"
newline
hexmask.long.byte 0x0 0.--7. 1. "PMREM,Program Memory Remap"
line.long 0x4 "BTPSCR,Boot Pin Status and Control Register"
bitfld.long 0x4 5.--6. "BFIND,BOOT Pin Function Indicator" "?,?,2: Check the BOOT pin when a system reset occurs by..,3: Check the BOOT pin when a system reset occurs.."
rbitfld.long 0x4 0. "BTPSTA,BOOT Pin Status" "0: The BOOT pin is low level.,1: The BOOT pin is high level."
line.long 0x8 "RSTSSR,Reset Source Status Register"
bitfld.long 0x8 5. "MONSTA,Clock Monitoring Reset Status" "0: Not detected.,1: CMR was detected."
bitfld.long 0x8 4. "SWSTA,Software Reset Status" "0: Not detected.,1: SWR was detected."
newline
bitfld.long 0x8 3. "EXTSTA,External Pin Reset Status" "0: Not detected.,1: EXTR was detected."
bitfld.long 0x8 2. "WDTSTA,Watch-Dog Timer Reset Status" "0: Not detected.,1: WDTR was detected."
newline
bitfld.long 0x8 1. "LVRSTA,LVR Reset Status" "0: Not detected.,1: LVR was detected."
bitfld.long 0x8 0. "PORSTA,POR Reset Status" "0: Not detected.,1: POR was detected."
line.long 0xC "NMISRCR,NMI Source Selection Register"
bitfld.long 0xC 7. "NMICON,Non-Maskable Interrupt (NMI) Control" "0: Disable NMI.,1: Enable NMI."
bitfld.long 0xC 6. "MONINT,Clock Monitoring Interrupt Selection" "0: Non-select clock monitoring interrupt for NMI..,1: Select clock monitoring interrupt for NMI source."
newline
hexmask.long.byte 0xC 0.--4. 1. "NMISRC,Non-Maskable Interrupt Source Selection"
wgroup.long 0x24++0x3
line.long 0x0 "SWRSTR,Software Reset Register"
hexmask.long.word 0x0 16.--31. 1. "WTIDKY,Write Identification Key (0x9eb3)"
hexmask.long.byte 0x0 0.--7. 1. "SWRST,Software Reset (System Reset)"
rgroup.long 0x28++0x3
line.long 0x0 "SRSTVR,System Reset Validation Register"
hexmask.long.byte 0x0 0.--7. 1. "VALID,System Reset Validation"
group.long 0x2C++0x7
line.long 0x0 "WUTCR,Wake-Up Timer Control Register"
bitfld.long 0x0 7. "WUTIEN,Wake-Up Timer Interrupt Enable" "0: Disable Wake-Up Timer interrupt.,1: Enable Wake-Up Timer interrupt."
bitfld.long 0x0 1. "CNTRLD,Counter Reload" "0: No effect.,1: Reload data to counter."
newline
bitfld.long 0x0 0. "WUTIFLAG,Wake-Up Timer Interrupt Flag" "0: No request occurred.,1: Request occurred."
line.long 0x4 "WUTDR,Wake-Up Timer Data Register"
hexmask.long.word 0x4 0.--15. 1. "WUTDATA,Wake-Up Timer Data"
group.long 0xA8++0x7
line.long 0x0 "HIRCTRM,High Frequency Internal RC Trim Register (HIRCNFIG)"
hexmask.long.word 0x0 16.--31. 1. "WTIDKY,Write Identification Key (0xa6b5)"
hexmask.long.byte 0x0 8.--15. 1. "nTRMH,Write Complement Key"
newline
rbitfld.long 0x0 5.--7. "CTRMH,Factory HIRC Coarse Trim" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 0.--4. 1. "FTRMH,Factory HIRC Fine Trim"
line.long 0x4 "WDTRCTRM,Watch-Dog Timer RC Trim Register (WDTRCNFIG)"
hexmask.long.word 0x4 16.--31. 1. "WTIDKY,Write Identification Key (0x4c3d)"
hexmask.long.byte 0x4 8.--15. 1. "nTRMW,Write Complement Key"
newline
hexmask.long.byte 0x4 4.--7. 1. "CTRMW,Factory WDTRC Coarse Trim"
bitfld.long 0x4 0.--2. "FTRMW,Factory WDTRC Fine Trim" "0,1,2,3,4,5,6,7"
tree.end
tree "SCUCG (Clock Generation)"
base ad:0x40001800
group.long 0x0++0x17
line.long 0x0 "SCCR,System Clock Control Register"
hexmask.long.word 0x0 16.--31. 1. "WTIDKY,Write Identification Key (0x570a)"
bitfld.long 0x0 0.--1. "MCLKSEL,Main Clock Selection MCLK" "0: High Frequency Internal RC Oscillator (40MHz) HIRC,1: External Main Oscillator (2 - 40MHz) XMOSC,2: External Sub Oscillator (32.768kHz) XSOSC,3: Internal Watch-Dog Timer RC Oscillator (40kHz).."
line.long 0x4 "CLKSRCR,Clock Source Control Register"
hexmask.long.word 0x4 16.--31. 1. "WTIDKY,Write Identification Key (0xa507)"
bitfld.long 0x4 12.--13. "HIRCSEL,HIRC Frequency Selection" "0: 40MHz HIRC,1: 20MHz HIRC,2: 10MHz HIRC,3: 5MHz HIRC"
newline
bitfld.long 0x4 8. "XMFRNG,Main Oscillator Type and Frequency Range Selection" "0: X-tal for XMOSC 2 to 16MHz,1: External Clock for XMOSC 2MHz to 40MHz"
bitfld.long 0x4 3. "WDTRCEN,WDTRC Enable" "0: Disable WDTRC.,1: Enable WDTRC."
newline
bitfld.long 0x4 2. "HIRCEN,HIRC Enable" "0: Disable HIRC.,1: Enable HIRC."
bitfld.long 0x4 1. "XMOSCEN,XMOSC Enable" "0: Disable XMOSC.,1: Enable XMOSC."
newline
bitfld.long 0x4 0. "XSOSCEN,XSOSC Enable" "0: Disable XSOSC.,1: Enable XSOSC."
line.long 0x8 "SCDIVR1,System Clock Divide Register 1"
bitfld.long 0x8 4.--6. "WLDIV,Clock Divide for Watch Timer and LCD Driver Divider 2" "0: MCLK/64,1: MCLK/128,2: MCLK/256,3: MCLK/512,4: MCLK/1024,?,?,?"
bitfld.long 0x8 0.--2. "HDIV,Clock Divide for HCLK Divider 0" "0: MCLK/16,1: MCLK/8,2: MCLK/4,3: MCLK/2,4: MCLK/1,?,?,?"
line.long 0xC "SCDIVR2,System Clock Divide Register 2"
bitfld.long 0xC 4.--5. "SYSTDIV,Clock Divide for SysTick Timer Divider 3" "0: HCLK/1,1: HCLK/2,2: HCLK/4,3: HCLK/8"
bitfld.long 0xC 0.--1. "PDIV,Clock Divide for PCLK Divider 1" "0: HCLK/1,1: HCLK/2,2: HCLK/4,3: HCLK/8"
line.long 0x10 "CLKOCR,Clock Output Control Register"
bitfld.long 0x10 7. "CLKOEN,Clock Output Enable" "0: Disable clock output.,1: Enable clock output."
bitfld.long 0x10 6. "POLSEL,Clock Output Polarity Selection when Disable" "0: Low level during disable,1: High level during disable"
newline
bitfld.long 0x10 3.--5. "CLKODIV,Output Clock Divide Divider 4" "0: Selected Clock/1,1: Selected Clock/2,2: Selected Clock/4,3: Selected Clock/8,4: Selected Clock/16,5: Selected Clock/32,6: Selected Clock/64,7: Selected Clock/128"
bitfld.long 0x10 0.--2. "CLKOS,Clock Output Selection" "0: Select MCLK.,1: Select WDTRC.,2: Select HIRC.,3: Select HCLK.,4: Select PCLK.,?,?,?"
line.long 0x14 "CMONCR,Clock Monitoring Control Register"
bitfld.long 0x14 7. "MONEN,Clock Monitoring Enable" "0: Disable clock monitoring.,1: Enable clock monitoring."
bitfld.long 0x14 5.--6. "MACTS,Clock Monitoring Action Selection" "0: No action by clock monitoring but flags will be..,1: Reset generation by clock monitoring,2: The system clock will be changed to the WDTRC..,?"
newline
bitfld.long 0x14 3. "MONFLAG,Clock Monitoring Result Flag" "0: The clock to be monitored is not ready,1: The clock to be monitored is ready"
bitfld.long 0x14 2. "NMINTFG,Clock Monitoring Interrupt Flag" "0: No request occurred.,1: Request occurred."
newline
bitfld.long 0x14 0.--1. "MONCS,Monitored Clock Selection" "0: Select MCLK.,1: Select HIRC.,2: Select XMOSC.,3: Select XSOSC."
group.long 0x20++0x7
line.long 0x0 "PPCLKEN1,Peripheral Clock Enable Register 1"
bitfld.long 0x0 21. "T21CLKE,TIMER21 Clock Enable" "0: Disable clock.,1: Enable clock."
bitfld.long 0x0 20. "T20CLKE,TIMER20 Clock Enable" "0: Disable clock.,1: Enable clock."
newline
bitfld.long 0x0 19. "T30CLKE,TIMER30 Clock Enable" "0: Disable clock.,1: Enable clock."
bitfld.long 0x0 18. "T12CLKE,TIMER12 Clock Enable" "0: Disable clock.,1: Enable clock."
newline
bitfld.long 0x0 17. "T11CLKE,TIMER11 Clock Enable" "0: Disable clock.,1: Enable clock."
bitfld.long 0x0 16. "T10CLKE,TIMER10 Clock Enable" "0: Disable clock.,1: Enable clock."
newline
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "T16CLKE,TIMER16 Clock Enable" "0: Disable clock.,1: Enable clock."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "T15CLKE,TIMER15 Clock Enable" "0: Disable clock.,1: Enable clock."
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "T14CLKE,TIMER14 Clock Enable" "0: Disable clock.,1: Enable clock."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "T13CLKE,TIMER13 Clock Enable" "0: Disable clock.,1: Enable clock."
newline
endif
bitfld.long 0x0 5. "PFCLKE,Port F Clock Enable" "0: Disable clock.,1: Enable clock."
bitfld.long 0x0 4. "PECLKE,Port E Clock Enable" "0: Disable clock.,1: Enable clock."
newline
bitfld.long 0x0 3. "PDCLKE,Port D Clock Enable" "0: Disable clock.,1: Enable clock."
bitfld.long 0x0 2. "PCCLKE,Port C Clock Enable" "0: Disable clock.,1: Enable clock."
newline
bitfld.long 0x0 1. "PBCLKE,Port B Clock Enable" "0: Disable clock.,1: Enable clock."
bitfld.long 0x0 0. "PACLKE,Port A Clock Enable" "0: Disable clock.,1: Enable clock."
line.long 0x4 "PPCLKEN2,Peripheral Clock Enable Register 2"
bitfld.long 0x4 19. "FMCLKE,FMC (Flash Memory Controller) Clock Enable" "0: Disable clock.,1: Enable clock."
bitfld.long 0x4 18. "LVICLKE,LVI (Low Voltage Indicator) Clock Enable" "0: Disable clock.,1: Enable clock."
newline
bitfld.long 0x4 17. "WDTCLKE,WDT (Watch-Dog Timer) Clock Enable" "0: Disable clock.,1: Enable clock."
bitfld.long 0x4 16. "WTCLKE,WT (Watch Timer) Clock Enable" "0: Disable clock.,1: Enable clock."
newline
bitfld.long 0x4 13. "LCDCLKE,LCD (LCD Driver) Clock Enable" "0: Disable clock.,1: Enable clock."
bitfld.long 0x4 12. "CRCLKE,CRC (Cyclic Redundancy Check) Clock Enable" "0: Disable clock.,1: Enable clock."
newline
bitfld.long 0x4 10. "ADCLKE,ADC (Analog to Digital Converter) Clock Enable" "0: Disable clock.,1: Enable clock."
newline
sif (cpuis("A31G12?*"))
bitfld.long 0x4 8. "I2C2CLKE,I2C2 (Inter-IC) Clock Enable" "0: Disable clock.,1: Enable clock."
newline
endif
bitfld.long 0x4 7. "I2C1CLKE,I2C1 (Inter-IC) Clock Enable" "0: Disable clock.,1: Enable clock."
bitfld.long 0x4 6. "I2C0CLKE,I2C0 (Inter-IC) Clock Enable" "0: Disable clock.,1: Enable clock."
newline
sif (cpuis("A31G12?*"))
bitfld.long 0x4 5. "UST13CLKE,USART13 Clock Enable" "0: Disable clock.,1: Enable clock."
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 4. "UST12CLKE,USART12 Clock Enable" "0: Disable clock.,1: Enable clock."
newline
endif
bitfld.long 0x4 3. "UT1CLKE,UART1 Clock Enable" "0: Disable clock.,1: Enable clock."
bitfld.long 0x4 2. "UT0CLKE,UART0 Clock Enable" "0: Disable clock.,1: Enable clock."
newline
bitfld.long 0x4 1. "UST11CLKE,USART11 Clock Enable" "0: Disable clock.,1: Enable clock."
bitfld.long 0x4 0. "UST10CLKE,USART10 Clock Enable" "0: Disable clock.,1: Enable clock."
group.long 0x40++0x3
line.long 0x0 "PPCLKSR,Peripheral Clock Selection Register"
bitfld.long 0x0 20. "T20CLK,TIMER20 Clock Selection" "0: XSOSC clock,1: PCLK clock"
bitfld.long 0x0 17. "T30CLK,TIMER30 Clock Selection" "0: MCLK clock,1: PCLK clock"
newline
bitfld.long 0x0 6.--7. "LCDCLK,LCD (LCD Driver) Clock Selection" "0: A clock of the MCLK which is divided by divider 2,1: XSOSC clock,2: WDTRC clock,?"
bitfld.long 0x0 3.--4. "WTCLK,WT (Watch Timer) Clock Selection" "0: A clock of the MCLK which is divided by divider 2,1: XSOSC clock,2: WDTRC clock,?"
newline
bitfld.long 0x0 0. "WDTCLK,WDT (Watch-Dog Timer) Clock Selection" "0: WDTRC clock,1: PCLK clock"
group.long 0x60++0x7
line.long 0x0 "PPRST1,Peripheral Reset Register 1"
bitfld.long 0x0 21. "T21RST,TIMER21 Reset" "0,1"
bitfld.long 0x0 20. "T20RST,TIMER20 Reset" "0,1"
newline
bitfld.long 0x0 19. "T30RST,TIMER30 Reset" "0,1"
bitfld.long 0x0 18. "T12RST,TIMER12 Reset" "0,1"
newline
bitfld.long 0x0 17. "T11RST,TIMER11 Reset" "0,1"
bitfld.long 0x0 16. "T10RST,TIMER10 Reset" "0,1"
newline
sif (cpuis("A31G12?*"))
bitfld.long 0x0 11. "T16RST,TIMER16 Reset" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 10. "T15RST,TIMER15 Reset" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 9. "T14RST,TIMER14 Reset" "0,1"
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x0 8. "T13RST,TIMER13 Reset" "0,1"
newline
endif
bitfld.long 0x0 5. "PFRST,Port F Reset" "0,1"
bitfld.long 0x0 4. "PERST,Port E Reset" "0,1"
newline
bitfld.long 0x0 3. "PDRST,Port D Reset" "0,1"
bitfld.long 0x0 2. "PCRST,Port C Reset" "0,1"
newline
bitfld.long 0x0 1. "PBRST,Port B Reset" "0,1"
bitfld.long 0x0 0. "PARST,Port A Reset" "0,1"
line.long 0x4 "PPRST2,Peripheral Reset Register 2"
bitfld.long 0x4 19. "FMCRST,FMC (Flash Memory Controller) Reset" "0,1"
bitfld.long 0x4 18. "LVIRST,LVI (Low Voltage Indicator) Reset" "0,1"
newline
bitfld.long 0x4 16. "WTRST,WT (Watch Timer) Reset" "0,1"
bitfld.long 0x4 13. "LCDRST,LCD (LCD Driver) Reset" "0,1"
newline
bitfld.long 0x4 12. "CRRST,CRC (Cyclic Redundancy Check) Reset" "0,1"
bitfld.long 0x4 10. "ADRST,ADC (Analog to Digital Converter) Reset" "0,1"
newline
sif (cpuis("A31G12?*"))
bitfld.long 0x4 8. "I2C2RST,I2C2 (Inter-IC) Reset" "0,1"
endif
bitfld.long 0x4 7. "I2C1RST,I2C1 (Inter-IC) Reset" "0,1"
newline
bitfld.long 0x4 6. "I2C0RST,I2C0 (Inter-IC) Reset" "0,1"
sif (cpuis("A31G12?*"))
bitfld.long 0x4 5. "UST13RST,USART13 Reset" "0,1"
newline
endif
sif (cpuis("A31G12?*"))
bitfld.long 0x4 4. "UST12RST,USART12 Reset" "0,1"
endif
bitfld.long 0x4 3. "UT1RST,UART1 Reset" "0,1"
newline
bitfld.long 0x4 2. "UT0RST,UART0 Reset" "0,1"
bitfld.long 0x4 1. "UST11RST,USART11 Reset" "0,1"
newline
bitfld.long 0x4 0. "UST10RST,USART10 Reset" "0,1"
group.long 0x80++0x3
line.long 0x0 "XTFLSR,X-tal Filter Selection Register"
hexmask.long.word 0x0 16.--31. 1. "WTIDKY,Write Identification Key (0x9b37)"
bitfld.long 0x0 0.--2. "XRNS,External Main Oscillator Filter Selection" "0: x-tal LE 4.5MHz,1: 4.5MHz GT x-tal LE 6.5MHz,2: 6.5MHz GT x-tal LE 8.5MHz,3: 8.5MHz GT x-tal LE 10.5MHz,4: 10.5MHz GT x-tal LE 12.5MHz,5: 12.5MHz GT x-tal LE 16.5MHz,?,?"
tree.end
tree "SCULV (LVI and LVR)"
base ad:0x40005100
group.long 0x0++0x7
line.long 0x0 "LVICR,Low Voltage Indicator Control Register"
bitfld.long 0x0 7. "LVIEN,LVI Enable" "0: Disable low voltage indicator.,1: Enable low voltage indicator."
bitfld.long 0x0 5. "LVINTEN,LVI Interrupt Enable" "0: Disable low voltage indicator interrupt.,1: Enable low voltage indicator interrupt."
bitfld.long 0x0 4. "LVIFLAG,LVI Interrupt Flag" "0: No request occurred.,1: Request occurred."
hexmask.long.byte 0x0 0.--3. 1. "LVIVS,LVI Voltage Selection"
line.long 0x4 "LVRCR,Low Voltage Reset Control Register"
hexmask.long.byte 0x4 0.--7. 1. "LVREN,LVR Enable"
tree.end
tree.end
tree "TC (Timer/Counter)"
base ad:0x0
sif (cpuis("A31G12?*"))
tree "TIMER13"
base ad:0x40002700
group.long 0x0++0xB
line.long 0x0 "CR,TIMER1n Control Register"
bitfld.long 0x0 15. "T1nEN,TIMER1n Operation Enable" "0,1"
bitfld.long 0x0 14. "T1nCLK,TIMER1n Clock Selection" "0,1"
bitfld.long 0x0 12.--13. "T1nMS,TIMER1n Operation Mode Selection" "0,1,2,3"
bitfld.long 0x0 11. "T1nECE,TIMER1n External Clock Edge Selection" "0,1"
bitfld.long 0x0 8. "T1nOPOL,TIMER1n Output Polarity Selection" "0,1"
bitfld.long 0x0 6.--7. "T1nCPOL,TIMER1n Capture Polarity Selection" "0,1,2,3"
bitfld.long 0x0 5. "T1nMIEN,TIMER1n Match Interrupt Enable" "0,1"
bitfld.long 0x0 4. "T1nCIEN,TIMER1n Capture Interrupt Enable" "0,1"
bitfld.long 0x0 3. "T1nMIFLAG,TIMER1n Match Interrupt Flag" "0,1"
bitfld.long 0x0 2. "T1nCIFLAG,TIMER1n Capture Interrupt Flag" "0,1"
bitfld.long 0x0 1. "T1nPAU,TIMER1n Counter Temporary Pause Control" "0,1"
newline
bitfld.long 0x0 0. "T1nCLR,TIMER1n Counter and Prescaler Clear" "0,1"
line.long 0x4 "ADR,TIMER1n A Data Register"
hexmask.long.word 0x4 0.--15. 1. "ADATA,TIMER1n A Data"
line.long 0x8 "BDR,TIMER1n B Data Register"
hexmask.long.word 0x8 0.--15. 1. "BDATA,TIMER1n B Data"
rgroup.long 0xC++0x3
line.long 0x0 "CAPDR,TIMER1n Capture Data Register"
hexmask.long.word 0x0 0.--15. 1. "CAPD,TIMER1n Capture Data"
group.long 0x10++0x3
line.long 0x0 "PREDR,TIMER1n Prescaler Data Register"
hexmask.long.word 0x0 0.--11. 1. "PRED,TIMER1n Prescaler Data"
rgroup.long 0x14++0x3
line.long 0x0 "CNT,TIMER1n Counter Register"
hexmask.long.word 0x0 0.--15. 1. "CNT,TIMER1n Counter"
tree.end
endif
sif (cpuis("A31G12?*"))
tree "TIMER14"
base ad:0x40002800
group.long 0x0++0xB
line.long 0x0 "CR,TIMER1n Control Register"
bitfld.long 0x0 15. "T1nEN,TIMER1n Operation Enable" "0,1"
bitfld.long 0x0 14. "T1nCLK,TIMER1n Clock Selection" "0,1"
bitfld.long 0x0 12.--13. "T1nMS,TIMER1n Operation Mode Selection" "0,1,2,3"
bitfld.long 0x0 11. "T1nECE,TIMER1n External Clock Edge Selection" "0,1"
bitfld.long 0x0 8. "T1nOPOL,TIMER1n Output Polarity Selection" "0,1"
bitfld.long 0x0 6.--7. "T1nCPOL,TIMER1n Capture Polarity Selection" "0,1,2,3"
bitfld.long 0x0 5. "T1nMIEN,TIMER1n Match Interrupt Enable" "0,1"
bitfld.long 0x0 4. "T1nCIEN,TIMER1n Capture Interrupt Enable" "0,1"
bitfld.long 0x0 3. "T1nMIFLAG,TIMER1n Match Interrupt Flag" "0,1"
bitfld.long 0x0 2. "T1nCIFLAG,TIMER1n Capture Interrupt Flag" "0,1"
bitfld.long 0x0 1. "T1nPAU,TIMER1n Counter Temporary Pause Control" "0,1"
newline
bitfld.long 0x0 0. "T1nCLR,TIMER1n Counter and Prescaler Clear" "0,1"
line.long 0x4 "ADR,TIMER1n A Data Register"
hexmask.long.word 0x4 0.--15. 1. "ADATA,TIMER1n A Data"
line.long 0x8 "BDR,TIMER1n B Data Register"
hexmask.long.word 0x8 0.--15. 1. "BDATA,TIMER1n B Data"
rgroup.long 0xC++0x3
line.long 0x0 "CAPDR,TIMER1n Capture Data Register"
hexmask.long.word 0x0 0.--15. 1. "CAPD,TIMER1n Capture Data"
group.long 0x10++0x3
line.long 0x0 "PREDR,TIMER1n Prescaler Data Register"
hexmask.long.word 0x0 0.--11. 1. "PRED,TIMER1n Prescaler Data"
rgroup.long 0x14++0x3
line.long 0x0 "CNT,TIMER1n Counter Register"
hexmask.long.word 0x0 0.--15. 1. "CNT,TIMER1n Counter"
tree.end
endif
sif (cpuis("A31G12?*"))
tree "TIMER15"
base ad:0x40002900
group.long 0x0++0xB
line.long 0x0 "CR,TIMER1n Control Register"
bitfld.long 0x0 15. "T1nEN,TIMER1n Operation Enable" "0,1"
bitfld.long 0x0 14. "T1nCLK,TIMER1n Clock Selection" "0,1"
bitfld.long 0x0 12.--13. "T1nMS,TIMER1n Operation Mode Selection" "0,1,2,3"
bitfld.long 0x0 11. "T1nECE,TIMER1n External Clock Edge Selection" "0,1"
bitfld.long 0x0 8. "T1nOPOL,TIMER1n Output Polarity Selection" "0,1"
bitfld.long 0x0 6.--7. "T1nCPOL,TIMER1n Capture Polarity Selection" "0,1,2,3"
bitfld.long 0x0 5. "T1nMIEN,TIMER1n Match Interrupt Enable" "0,1"
bitfld.long 0x0 4. "T1nCIEN,TIMER1n Capture Interrupt Enable" "0,1"
bitfld.long 0x0 3. "T1nMIFLAG,TIMER1n Match Interrupt Flag" "0,1"
bitfld.long 0x0 2. "T1nCIFLAG,TIMER1n Capture Interrupt Flag" "0,1"
bitfld.long 0x0 1. "T1nPAU,TIMER1n Counter Temporary Pause Control" "0,1"
newline
bitfld.long 0x0 0. "T1nCLR,TIMER1n Counter and Prescaler Clear" "0,1"
line.long 0x4 "ADR,TIMER1n A Data Register"
hexmask.long.word 0x4 0.--15. 1. "ADATA,TIMER1n A Data"
line.long 0x8 "BDR,TIMER1n B Data Register"
hexmask.long.word 0x8 0.--15. 1. "BDATA,TIMER1n B Data"
rgroup.long 0xC++0x3
line.long 0x0 "CAPDR,TIMER1n Capture Data Register"
hexmask.long.word 0x0 0.--15. 1. "CAPD,TIMER1n Capture Data"
group.long 0x10++0x3
line.long 0x0 "PREDR,TIMER1n Prescaler Data Register"
hexmask.long.word 0x0 0.--11. 1. "PRED,TIMER1n Prescaler Data"
rgroup.long 0x14++0x3
line.long 0x0 "CNT,TIMER1n Counter Register"
hexmask.long.word 0x0 0.--15. 1. "CNT,TIMER1n Counter"
tree.end
endif
sif (cpuis("A31G12?*"))
tree "TIMER16"
base ad:0x40002A00
group.long 0x0++0xB
line.long 0x0 "CR,TIMER1n Control Register"
bitfld.long 0x0 15. "T1nEN,TIMER1n Operation Enable" "0,1"
bitfld.long 0x0 14. "T1nCLK,TIMER1n Clock Selection" "0,1"
bitfld.long 0x0 12.--13. "T1nMS,TIMER1n Operation Mode Selection" "0,1,2,3"
bitfld.long 0x0 11. "T1nECE,TIMER1n External Clock Edge Selection" "0,1"
bitfld.long 0x0 8. "T1nOPOL,TIMER1n Output Polarity Selection" "0,1"
bitfld.long 0x0 6.--7. "T1nCPOL,TIMER1n Capture Polarity Selection" "0,1,2,3"
bitfld.long 0x0 5. "T1nMIEN,TIMER1n Match Interrupt Enable" "0,1"
bitfld.long 0x0 4. "T1nCIEN,TIMER1n Capture Interrupt Enable" "0,1"
bitfld.long 0x0 3. "T1nMIFLAG,TIMER1n Match Interrupt Flag" "0,1"
bitfld.long 0x0 2. "T1nCIFLAG,TIMER1n Capture Interrupt Flag" "0,1"
bitfld.long 0x0 1. "T1nPAU,TIMER1n Counter Temporary Pause Control" "0,1"
newline
bitfld.long 0x0 0. "T1nCLR,TIMER1n Counter and Prescaler Clear" "0,1"
line.long 0x4 "ADR,TIMER1n A Data Register"
hexmask.long.word 0x4 0.--15. 1. "ADATA,TIMER1n A Data"
line.long 0x8 "BDR,TIMER1n B Data Register"
hexmask.long.word 0x8 0.--15. 1. "BDATA,TIMER1n B Data"
rgroup.long 0xC++0x3
line.long 0x0 "CAPDR,TIMER1n Capture Data Register"
hexmask.long.word 0x0 0.--15. 1. "CAPD,TIMER1n Capture Data"
group.long 0x10++0x3
line.long 0x0 "PREDR,TIMER1n Prescaler Data Register"
hexmask.long.word 0x0 0.--11. 1. "PRED,TIMER1n Prescaler Data"
rgroup.long 0x14++0x3
line.long 0x0 "CNT,TIMER1n Counter Register"
hexmask.long.word 0x0 0.--15. 1. "CNT,TIMER1n Counter"
tree.end
endif
tree "TIMER1n"
base ad:0x51000000
group.long 0x0++0xB
line.long 0x0 "CR,TIMER1n Control Register"
bitfld.long 0x0 15. "T1nEN,TIMER1n Operation Enable" "0,1"
bitfld.long 0x0 14. "T1nCLK,TIMER1n Clock Selection" "0,1"
bitfld.long 0x0 12.--13. "T1nMS,TIMER1n Operation Mode Selection" "0,1,2,3"
bitfld.long 0x0 11. "T1nECE,TIMER1n External Clock Edge Selection" "0,1"
bitfld.long 0x0 8. "T1nOPOL,TIMER1n Output Polarity Selection" "0,1"
bitfld.long 0x0 6.--7. "T1nCPOL,TIMER1n Capture Polarity Selection" "0,1,2,3"
bitfld.long 0x0 5. "T1nMIEN,TIMER1n Match Interrupt Enable" "0,1"
bitfld.long 0x0 4. "T1nCIEN,TIMER1n Capture Interrupt Enable" "0,1"
bitfld.long 0x0 3. "T1nMIFLAG,TIMER1n Match Interrupt Flag" "0,1"
bitfld.long 0x0 2. "T1nCIFLAG,TIMER1n Capture Interrupt Flag" "0,1"
bitfld.long 0x0 1. "T1nPAU,TIMER1n Counter Temporary Pause Control" "0,1"
newline
bitfld.long 0x0 0. "T1nCLR,TIMER1n Counter and Prescaler Clear" "0,1"
line.long 0x4 "ADR,TIMER1n A Data Register"
hexmask.long.word 0x4 0.--15. 1. "ADATA,TIMER1n A Data"
line.long 0x8 "BDR,TIMER1n B Data Register"
hexmask.long.word 0x8 0.--15. 1. "BDATA,TIMER1n B Data"
rgroup.long 0xC++0x3
line.long 0x0 "CAPDR,TIMER1n Capture Data Register"
hexmask.long.word 0x0 0.--15. 1. "CAPD,TIMER1n Capture Data"
group.long 0x10++0x3
line.long 0x0 "PREDR,TIMER1n Prescaler Data Register"
hexmask.long.word 0x0 0.--11. 1. "PRED,TIMER1n Prescaler Data"
rgroup.long 0x14++0x3
line.long 0x0 "CNT,TIMER1n Counter Register"
hexmask.long.word 0x0 0.--15. 1. "CNT,TIMER1n Counter"
tree.end
tree "TIMER2n"
base ad:0x52000000
group.long 0x0++0xB
line.long 0x0 "CR,TIMER2n Control Register"
bitfld.long 0x0 15. "T2nEN,TIMER2n Operation Enable" "0,1"
bitfld.long 0x0 14. "T2nCLK,TIMER2n Clock Selection" "0,1"
bitfld.long 0x0 12.--13. "T2nMS,TIMER2n Operation Mode Selection" "0,1,2,3"
bitfld.long 0x0 11. "T2nECE,TIMER2n External Clock Edge Selection" "0,1"
bitfld.long 0x0 9.--10. "CAPSEL,TIMER2n Capture Signal Selection" "0,1,2,3"
bitfld.long 0x0 8. "T2nOPOL,TIMER2n Output Polarity Selection" "0,1"
bitfld.long 0x0 6.--7. "T2nCPOL,TIMER2n Capture Polarity Selection" "0,1,2,3"
bitfld.long 0x0 5. "T2nMIEN,TIMER2n Match Interrupt Enable" "0,1"
bitfld.long 0x0 4. "T2nCIEN,TIMER2n Capture Interrupt Enable" "0,1"
bitfld.long 0x0 3. "T2nMIFLAG,TIMER2n Match Interrupt Flag" "0,1"
bitfld.long 0x0 2. "T2nCIFLAG,TIMER2n Capture Interrupt Flag" "0,1"
newline
bitfld.long 0x0 1. "T2nPAU,TIMER2n Counter Temporary Pause Control" "0,1"
bitfld.long 0x0 0. "T2nCLR,TIMER2n Counter and Prescaler Clear" "0,1"
line.long 0x4 "ADR,TIMER2n A Data Register"
hexmask.long 0x4 0.--31. 1. "ADATA,TIMER2n A Data"
line.long 0x8 "BDR,TIMER2n B Data Register"
hexmask.long 0x8 0.--31. 1. "BDATA,TIMER2n B Data"
rgroup.long 0xC++0x3
line.long 0x0 "CAPDR,TIMER2n Capture Data Register"
hexmask.long 0x0 0.--31. 1. "CAPD,TIMER2n Capture Data"
group.long 0x10++0x3
line.long 0x0 "PREDR,TIMER2n Prescaler Data Register"
hexmask.long.word 0x0 0.--11. 1. "PRED,TIMER2n Prescaler Data"
rgroup.long 0x14++0x3
line.long 0x0 "CNT,TIMER2n Counter Register"
hexmask.long 0x0 0.--31. 1. "CNT,TIMER2n Counter"
tree.end
tree "TIMER3n"
base ad:0x53000000
group.long 0x0++0x13
line.long 0x0 "CR,TIMER3n Control Register"
bitfld.long 0x0 15. "T3nEN,TIMER3n Operation Enable" "0: Disable TIMER3n Operation.,1: Enable TIMER3n Operation. (Counter Clear and.."
bitfld.long 0x0 14. "T3nCLK,TIMER3n Clock Selection" "0: Select an Internal Prescaler Clock.,1: Select an External Clock."
newline
bitfld.long 0x0 12.--13. "T3nMS,TIMER3n Operation Mode Selection" "0: Interval mode. (All match interrupts can occur),1: Capture mode. (The Period-match interrupt can..,2: Back-to-back mode. (All interrupts can occur),?"
bitfld.long 0x0 11. "T3nECE,TIMER3n External Clock Edge Selection" "0: Select falling edge of external clock.,1: Select rising edge of external clock."
newline
bitfld.long 0x0 10. "FORCA,TIMER3n Output Mode SelectionSelection. This bit should be changed while T3nEN is '0'." "0: 6-Channel mode. (The PWM3nxA/PWM3nxB pins are..,1: Force A-Channel mode. (All PWM3nxA/PWM3nxB pins.."
bitfld.long 0x0 9. "DLYEN,Delay Time Insertion Enable" "0: Disable delay time insertion to the..,1: Enable delay time insertion to the.."
newline
bitfld.long 0x0 8. "DLYPOS,Delay Time Insertion Position" "0: Insert in front of PWM3nxA and behind PWM3nxB..,1: Insert behind PWM3nxA and in front of PWM3nxB.."
bitfld.long 0x0 6.--7. "T3nCPOL,TIMER3n Capture Polarity Selection" "0: Capture on falling edge.,1: Capture on rising edge.,2: Capture on both falling and rising edge.,?"
newline
bitfld.long 0x0 4.--5. "UPDT,Data Reload Time Selection" "0: Update data to buffer at the time of writing.,1: Update data to buffer at period match.,2: Update data to buffer at bottom.,?"
bitfld.long 0x0 1.--3. "PMOC,Period Match Interrupt Occurrence Selection" "0: Once every 1 period match.,1: Once every 2 period match.,2: Once every 3 period match.,3: Once every 4 period match.,4: Once every 5 period match.,5: Once every 6 period match.,6: Once every 7 period match.,7: Once every 8 period match."
newline
bitfld.long 0x0 0. "T3nCLR,TIMER3n Counter and Prescaler Clear" "0: No effect.,1: Clear TIMER3n counter and prescaler."
line.long 0x4 "PDR,TIMER3n Period Data Register"
hexmask.long.word 0x4 0.--15. 1. "PDATA,TIMER3n Period Data"
line.long 0x8 "ADR,TIMER3n A Data Register"
hexmask.long.word 0x8 0.--15. 1. "ADATA,TIMER3n A Data"
line.long 0xC "BDR,TIMER3n B Data Register"
hexmask.long.word 0xC 0.--15. 1. "BDATA,TIMER3n B Data"
line.long 0x10 "CDR,TIMER3n C Data Register"
hexmask.long.word 0x10 0.--15. 1. "CDATA,TIMER3n C Data"
rgroup.long 0x14++0x3
line.long 0x0 "CAPDR,TIMER3n Capture Data Register"
hexmask.long.word 0x0 0.--15. 1. "CAPD,TIMER3n Capture Data"
group.long 0x18++0x3
line.long 0x0 "PREDR,TIMER3n Prescaler Data Register"
hexmask.long.word 0x0 0.--11. 1. "PRED,TIMER3n Prescaler Data"
rgroup.long 0x1C++0x3
line.long 0x0 "CNT,TIMER3n Counter Register"
hexmask.long.word 0x0 0.--15. 1. "CNT,TIMER3n Counter"
group.long 0x20++0x1B
line.long 0x0 "OUTCR,TIMER3n Output Control Register"
hexmask.long.word 0x0 16.--31. 1. "WTIDKY,Write Identification Key"
bitfld.long 0x0 15. "POLB,PWM3nxB Output Polarity Selection" "0: Low level start. (The PWM3nxB pins are started..,1: High level start. (The PWM3nxB pins are started.."
newline
bitfld.long 0x0 14. "POLA,PWM3nxA Output Polarity Selection" "0: Low level start. (The PWM3nxA pins are started..,1: High level start. (The PWM3nxA pins are started.."
bitfld.long 0x0 13. "PABOE,PWM3nAB Output Enable" "0: Disable output.,1: Enable output."
newline
bitfld.long 0x0 12. "PBBOE,PWM3nBB Output Enable" "0: Disable output.,1: Enable output."
bitfld.long 0x0 11. "PCBOE,PWM3nCB Output Enable" "0: Disable output.,1: Enable output."
newline
bitfld.long 0x0 10. "PAAOE,PWM3nAA Output Enable" "0: Disable output.,1: Enable output."
bitfld.long 0x0 9. "PBAOE,PWM3nBA Output Enable" "0: Disable output.,1: Enable output."
newline
bitfld.long 0x0 8. "PCAOE,PWM3nCA Output Enable" "0: Disable output.,1: Enable output."
bitfld.long 0x0 6. "LVLAB,Configure PWM3nAB Output when Disable" "0: Low level.,1: High level."
newline
bitfld.long 0x0 5. "LVLBB,Configure PWM3nBB Output when Disable" "0: Low level.,1: High level."
bitfld.long 0x0 4. "LVLCB,Configure PWM3nCB Output when Disable" "0: Low level.,1: High level."
newline
bitfld.long 0x0 2. "LVLAA,Configure PWM3nAA Output when Disable" "0: Low level.,1: High level."
bitfld.long 0x0 1. "LVLBA,Configure PWM3nBA Output when Disable" "0: Low level.,1: High level."
newline
bitfld.long 0x0 0. "LVLCA,Configure PWM3nCA Output when Disable" "0: Low level.,1: High level."
line.long 0x4 "DLY,TIMER3n PWM Output Delay Data Register"
hexmask.long.word 0x4 0.--9. 1. "DLY,TIMER3n PWM Delay Data"
line.long 0x8 "INTCR,TIMER3n Interrupt Control Register"
bitfld.long 0x8 6. "HIZIEN,TIMER3n Output High-Impedance Interrupt Enable" "0: Disable TIMER3n output high-impedance interrupt.,1: Enable TIMER3n output high-impedance interrupt."
bitfld.long 0x8 5. "T3nCIEN,TIMER3n Capture Interrupt Enable" "0: Disable TIMER3n capture interrupt.,1: Enable TIMER3n capture interrupt."
newline
bitfld.long 0x8 4. "T3nBTIEN,TIMER3n Bottom Interrupt Enable" "0: Disable TIMER3n bottom interrupt.,1: Enable TIMER3n bottom interrupt."
bitfld.long 0x8 3. "T3nPMIEN,TIMER3n Period Match Interrupt Enable" "0: Disable TIMER3n period interrupt.,1: Enable TIMER3n period interrupt."
newline
bitfld.long 0x8 2. "T3nAMIEN,TIMER3n A-ch Match Interrupt Enable" "0: Disable TIMER3n A-ch match interrupt.,1: Enable TIMER3n A-ch match interrupt."
bitfld.long 0x8 1. "T3nBMIEN,TIMER3n B-ch Match Interrupt Enable" "0: Disable TIMER3n B-ch match interrupt.,1: Enable TIMER3n B-ch match interrupt."
newline
bitfld.long 0x8 0. "T3nCMIEN,TIMER3n C-ch Match Interrupt Enable" "0: Disable TIMER3n C-ch match interrupt.,1: Enable TIMER3n C-ch match interrupt."
line.long 0xC "INTFLAG,TIMER3n Interrupt Flag Register"
bitfld.long 0xC 6. "HIZIFLAG,TIMER3n Output High-Impedance Interrupt Flag" "0: No request occurred.,1: Request occurred. The bit will be cleared to '0'.."
bitfld.long 0xC 5. "T3nCIFLAG,TIMER3n Capture Interrupt Flag" "0: No request occurred.,1: Request occurred. The bit will be cleared to '0'.."
newline
bitfld.long 0xC 4. "T3nBTIFLAG,TIMER3n Bottom Interrupt Flag" "0: No request occurred.,1: Request occurred. The bit will be cleared to '0'.."
bitfld.long 0xC 3. "T3nPMIFLAG,TIMER3n Period Match Interrupt Flag" "0: No request occurred.,1: Request occurred. The bit will be cleared to '0'.."
newline
bitfld.long 0xC 2. "T3nAMIFLAG,TIMER3n A-ch Match Interrupt Flag" "0: No request occurred.,1: Request occurred. The bit will be cleared to '0'.."
bitfld.long 0xC 1. "T3nBMIFLAG,TIMER3n B-ch Match Interrupt Flag" "0: No request occurred.,1: Request occurred. The bit will be cleared to '0'.."
newline
bitfld.long 0xC 0. "T3nCMIFLAG,TIMER3n C-ch Match Interrupt Flag" "0: No request occurred.,1: Request occurred. The bit will be cleared to '0'.."
line.long 0x10 "HIZCR,TIMER3n High-Impedance Control Register"
bitfld.long 0x10 7. "HIZEN,PWM3nxA/PWM3nxB Output High-Impedance Enable" "0: Disable to control the output high-impedance.,1: Enable to control the output high-impedance."
bitfld.long 0x10 4. "HIZSW,High-Impedance Output Software Setting" "0: No effect.,1: PWM3nxA/PWM3nxB pins go into high impedance."
newline
bitfld.long 0x10 2. "HEDGE,High-Impedance Edge Selection" "0: Falling edge of the BLNK pin.,1: Rising edge of the BLNK pin."
rbitfld.long 0x10 1. "HIZSTA,High-Impedance Status" "0: Indicates that the pins are not under a Hi-Z..,1: Indicates that the pins are under a Hi-Z state."
newline
bitfld.long 0x10 0. "HIZCLR,High-Impedance Output Clear" "0: No effect.,1: Clear high-impedance output. (The.."
line.long 0x14 "ADTCR,TIMER3n ADC Trigger Control Register"
bitfld.long 0x14 4. "T3nBTTG,Select TIMER3n Bottom for ADC Trigger Signal Generator." "0: Disable ADC trigger signal generator by bottom.,1: Enable ADC trigger signal generator by bottom."
bitfld.long 0x14 3. "T3nPMTG,Select TIMER3n Period Match for ADC Trigger Signal Generator." "0: Disable ADC trigger signal generator by period..,1: Enable ADC trigger signal generator by period.."
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bitfld.long 0x14 2. "T3nAMTG,Select TIMER3n A-ch Match for ADC Trigger Signal Generator." "0: Disable ADC trigger signal generator by A-ch..,1: Enable ADC trigger signal generator by A-ch match."
bitfld.long 0x14 1. "T3nBMTG,Select TIMER3n B-ch Match for ADC Trigger Signal Generator." "0: Disable ADC trigger signal generator by B-ch..,1: Enable ADC trigger signal generator by B-ch match."
newline
bitfld.long 0x14 0. "T3nCMTG,Select TIMER3n C-ch Match for ADC Trigger Signal Generator." "0: Disable ADC trigger signal generator by C-ch..,1: Enable ADC trigger signal generator by C-ch match."
line.long 0x18 "ADTDR,TIMER3n ADC Trigger Generator Data Register"
hexmask.long.word 0x18 0.--13. 1. "ADTDATA,TIMER3n ADC Trigger Generation Data"
tree.end
tree "TIMER10"
base ad:0x40002100
group.long 0x0++0xB
line.long 0x0 "CR,TIMER1n Control Register"
bitfld.long 0x0 15. "T1nEN,TIMER1n Operation Enable" "0,1"
bitfld.long 0x0 14. "T1nCLK,TIMER1n Clock Selection" "0,1"
bitfld.long 0x0 12.--13. "T1nMS,TIMER1n Operation Mode Selection" "0,1,2,3"
bitfld.long 0x0 11. "T1nECE,TIMER1n External Clock Edge Selection" "0,1"
bitfld.long 0x0 8. "T1nOPOL,TIMER1n Output Polarity Selection" "0,1"
bitfld.long 0x0 6.--7. "T1nCPOL,TIMER1n Capture Polarity Selection" "0,1,2,3"
bitfld.long 0x0 5. "T1nMIEN,TIMER1n Match Interrupt Enable" "0,1"
bitfld.long 0x0 4. "T1nCIEN,TIMER1n Capture Interrupt Enable" "0,1"
bitfld.long 0x0 3. "T1nMIFLAG,TIMER1n Match Interrupt Flag" "0,1"
bitfld.long 0x0 2. "T1nCIFLAG,TIMER1n Capture Interrupt Flag" "0,1"
bitfld.long 0x0 1. "T1nPAU,TIMER1n Counter Temporary Pause Control" "0,1"
newline
bitfld.long 0x0 0. "T1nCLR,TIMER1n Counter and Prescaler Clear" "0,1"
line.long 0x4 "ADR,TIMER1n A Data Register"
hexmask.long.word 0x4 0.--15. 1. "ADATA,TIMER1n A Data"
line.long 0x8 "BDR,TIMER1n B Data Register"
hexmask.long.word 0x8 0.--15. 1. "BDATA,TIMER1n B Data"
rgroup.long 0xC++0x3
line.long 0x0 "CAPDR,TIMER1n Capture Data Register"
hexmask.long.word 0x0 0.--15. 1. "CAPD,TIMER1n Capture Data"
group.long 0x10++0x3
line.long 0x0 "PREDR,TIMER1n Prescaler Data Register"
hexmask.long.word 0x0 0.--11. 1. "PRED,TIMER1n Prescaler Data"
rgroup.long 0x14++0x3
line.long 0x0 "CNT,TIMER1n Counter Register"
hexmask.long.word 0x0 0.--15. 1. "CNT,TIMER1n Counter"
tree.end
tree "TIMER11"
base ad:0x40002200
group.long 0x0++0xB
line.long 0x0 "CR,TIMER1n Control Register"
bitfld.long 0x0 15. "T1nEN,TIMER1n Operation Enable" "0,1"
bitfld.long 0x0 14. "T1nCLK,TIMER1n Clock Selection" "0,1"
bitfld.long 0x0 12.--13. "T1nMS,TIMER1n Operation Mode Selection" "0,1,2,3"
bitfld.long 0x0 11. "T1nECE,TIMER1n External Clock Edge Selection" "0,1"
bitfld.long 0x0 8. "T1nOPOL,TIMER1n Output Polarity Selection" "0,1"
bitfld.long 0x0 6.--7. "T1nCPOL,TIMER1n Capture Polarity Selection" "0,1,2,3"
bitfld.long 0x0 5. "T1nMIEN,TIMER1n Match Interrupt Enable" "0,1"
bitfld.long 0x0 4. "T1nCIEN,TIMER1n Capture Interrupt Enable" "0,1"
bitfld.long 0x0 3. "T1nMIFLAG,TIMER1n Match Interrupt Flag" "0,1"
bitfld.long 0x0 2. "T1nCIFLAG,TIMER1n Capture Interrupt Flag" "0,1"
bitfld.long 0x0 1. "T1nPAU,TIMER1n Counter Temporary Pause Control" "0,1"
newline
bitfld.long 0x0 0. "T1nCLR,TIMER1n Counter and Prescaler Clear" "0,1"
line.long 0x4 "ADR,TIMER1n A Data Register"
hexmask.long.word 0x4 0.--15. 1. "ADATA,TIMER1n A Data"
line.long 0x8 "BDR,TIMER1n B Data Register"
hexmask.long.word 0x8 0.--15. 1. "BDATA,TIMER1n B Data"
rgroup.long 0xC++0x3
line.long 0x0 "CAPDR,TIMER1n Capture Data Register"
hexmask.long.word 0x0 0.--15. 1. "CAPD,TIMER1n Capture Data"
group.long 0x10++0x3
line.long 0x0 "PREDR,TIMER1n Prescaler Data Register"
hexmask.long.word 0x0 0.--11. 1. "PRED,TIMER1n Prescaler Data"
rgroup.long 0x14++0x3
line.long 0x0 "CNT,TIMER1n Counter Register"
hexmask.long.word 0x0 0.--15. 1. "CNT,TIMER1n Counter"
tree.end
tree "TIMER12"
base ad:0x40002300
group.long 0x0++0xB
line.long 0x0 "CR,TIMER1n Control Register"
bitfld.long 0x0 15. "T1nEN,TIMER1n Operation Enable" "0,1"
bitfld.long 0x0 14. "T1nCLK,TIMER1n Clock Selection" "0,1"
bitfld.long 0x0 12.--13. "T1nMS,TIMER1n Operation Mode Selection" "0,1,2,3"
bitfld.long 0x0 11. "T1nECE,TIMER1n External Clock Edge Selection" "0,1"
bitfld.long 0x0 8. "T1nOPOL,TIMER1n Output Polarity Selection" "0,1"
bitfld.long 0x0 6.--7. "T1nCPOL,TIMER1n Capture Polarity Selection" "0,1,2,3"
bitfld.long 0x0 5. "T1nMIEN,TIMER1n Match Interrupt Enable" "0,1"
bitfld.long 0x0 4. "T1nCIEN,TIMER1n Capture Interrupt Enable" "0,1"
bitfld.long 0x0 3. "T1nMIFLAG,TIMER1n Match Interrupt Flag" "0,1"
bitfld.long 0x0 2. "T1nCIFLAG,TIMER1n Capture Interrupt Flag" "0,1"
bitfld.long 0x0 1. "T1nPAU,TIMER1n Counter Temporary Pause Control" "0,1"
newline
bitfld.long 0x0 0. "T1nCLR,TIMER1n Counter and Prescaler Clear" "0,1"
line.long 0x4 "ADR,TIMER1n A Data Register"
hexmask.long.word 0x4 0.--15. 1. "ADATA,TIMER1n A Data"
line.long 0x8 "BDR,TIMER1n B Data Register"
hexmask.long.word 0x8 0.--15. 1. "BDATA,TIMER1n B Data"
rgroup.long 0xC++0x3
line.long 0x0 "CAPDR,TIMER1n Capture Data Register"
hexmask.long.word 0x0 0.--15. 1. "CAPD,TIMER1n Capture Data"
group.long 0x10++0x3
line.long 0x0 "PREDR,TIMER1n Prescaler Data Register"
hexmask.long.word 0x0 0.--11. 1. "PRED,TIMER1n Prescaler Data"
rgroup.long 0x14++0x3
line.long 0x0 "CNT,TIMER1n Counter Register"
hexmask.long.word 0x0 0.--15. 1. "CNT,TIMER1n Counter"
tree.end
tree "TIMER20"
base ad:0x40002500
group.long 0x0++0xB
line.long 0x0 "CR,TIMER2n Control Register"
bitfld.long 0x0 15. "T2nEN,TIMER2n Operation Enable" "0,1"
bitfld.long 0x0 14. "T2nCLK,TIMER2n Clock Selection" "0,1"
bitfld.long 0x0 12.--13. "T2nMS,TIMER2n Operation Mode Selection" "0,1,2,3"
bitfld.long 0x0 11. "T2nECE,TIMER2n External Clock Edge Selection" "0,1"
bitfld.long 0x0 9.--10. "CAPSEL,TIMER2n Capture Signal Selection" "0,1,2,3"
bitfld.long 0x0 8. "T2nOPOL,TIMER2n Output Polarity Selection" "0,1"
bitfld.long 0x0 6.--7. "T2nCPOL,TIMER2n Capture Polarity Selection" "0,1,2,3"
bitfld.long 0x0 5. "T2nMIEN,TIMER2n Match Interrupt Enable" "0,1"
bitfld.long 0x0 4. "T2nCIEN,TIMER2n Capture Interrupt Enable" "0,1"
bitfld.long 0x0 3. "T2nMIFLAG,TIMER2n Match Interrupt Flag" "0,1"
newline
bitfld.long 0x0 2. "T2nCIFLAG,TIMER2n Capture Interrupt Flag" "0,1"
bitfld.long 0x0 1. "T2nPAU,TIMER2n Counter Temporary Pause Control" "0,1"
bitfld.long 0x0 0. "T2nCLR,TIMER2n Counter and Prescaler Clear" "0,1"
line.long 0x4 "ADR,TIMER2n A Data Register"
hexmask.long 0x4 0.--31. 1. "ADATA,TIMER2n A Data"
line.long 0x8 "BDR,TIMER2n B Data Register"
hexmask.long 0x8 0.--31. 1. "BDATA,TIMER2n B Data"
rgroup.long 0xC++0x3
line.long 0x0 "CAPDR,TIMER2n Capture Data Register"
hexmask.long 0x0 0.--31. 1. "CAPD,TIMER2n Capture Data"
group.long 0x10++0x3
line.long 0x0 "PREDR,TIMER2n Prescaler Data Register"
hexmask.long.word 0x0 0.--11. 1. "PRED,TIMER2n Prescaler Data"
rgroup.long 0x14++0x3
line.long 0x0 "CNT,TIMER2n Counter Register"
hexmask.long 0x0 0.--31. 1. "CNT,TIMER2n Counter"
group.long 0x0++0x3
line.long 0x0 "TIMER20_CR,TIMER2n Control Register"
bitfld.long 0x0 15. "T2nEN,TIMER2n Operation Enable" "0,1"
bitfld.long 0x0 14. "T2nCLK,TIMER2n Clock Selection" "0,1"
bitfld.long 0x0 12.--13. "T2nMS,TIMER2n Operation Mode Selection" "0,1,2,3"
bitfld.long 0x0 11. "T2nECE,TIMER2n External Clock Edge Selection" "0,1"
bitfld.long 0x0 9.--10. "CAPSEL,TIMER2n Capture Signal Selection" "0,1,2,3"
bitfld.long 0x0 8. "T2nOPOL,TIMER2n Output Polarity Selection" "0,1"
bitfld.long 0x0 6.--7. "T2nCPOL,TIMER2n Capture Polarity Selection" "0,1,2,3"
bitfld.long 0x0 5. "T2nMIEN,TIMER2n Match Interrupt Enable" "0,1"
bitfld.long 0x0 4. "T2nCIEN,TIMER2n Capture Interrupt Enable" "0,1"
bitfld.long 0x0 3. "T2nMIFLAG,TIMER2n Match Interrupt Flag" "0,1"
newline
bitfld.long 0x0 2. "T2nCIFLAG,TIMER2n Capture Interrupt Flag" "0,1"
bitfld.long 0x0 1. "T2nPAU,TIMER2n Counter Temporary Pause Control" "0,1"
bitfld.long 0x0 0. "T2nCLR,TIMER2n Counter and Prescaler Clear" "0,1"
tree.end
tree "TIMER21"
base ad:0x40002600
group.long 0x0++0xB
line.long 0x0 "CR,TIMER2n Control Register"
bitfld.long 0x0 15. "T2nEN,TIMER2n Operation Enable" "0,1"
bitfld.long 0x0 14. "T2nCLK,TIMER2n Clock Selection" "0,1"
bitfld.long 0x0 12.--13. "T2nMS,TIMER2n Operation Mode Selection" "0,1,2,3"
bitfld.long 0x0 11. "T2nECE,TIMER2n External Clock Edge Selection" "0,1"
bitfld.long 0x0 9.--10. "CAPSEL,TIMER2n Capture Signal Selection" "0,1,2,3"
bitfld.long 0x0 8. "T2nOPOL,TIMER2n Output Polarity Selection" "0,1"
bitfld.long 0x0 6.--7. "T2nCPOL,TIMER2n Capture Polarity Selection" "0,1,2,3"
bitfld.long 0x0 5. "T2nMIEN,TIMER2n Match Interrupt Enable" "0,1"
bitfld.long 0x0 4. "T2nCIEN,TIMER2n Capture Interrupt Enable" "0,1"
bitfld.long 0x0 3. "T2nMIFLAG,TIMER2n Match Interrupt Flag" "0,1"
newline
bitfld.long 0x0 2. "T2nCIFLAG,TIMER2n Capture Interrupt Flag" "0,1"
bitfld.long 0x0 1. "T2nPAU,TIMER2n Counter Temporary Pause Control" "0,1"
bitfld.long 0x0 0. "T2nCLR,TIMER2n Counter and Prescaler Clear" "0,1"
line.long 0x4 "ADR,TIMER2n A Data Register"
hexmask.long 0x4 0.--31. 1. "ADATA,TIMER2n A Data"
line.long 0x8 "BDR,TIMER2n B Data Register"
hexmask.long 0x8 0.--31. 1. "BDATA,TIMER2n B Data"
rgroup.long 0xC++0x3
line.long 0x0 "CAPDR,TIMER2n Capture Data Register"
hexmask.long 0x0 0.--31. 1. "CAPD,TIMER2n Capture Data"
group.long 0x10++0x3
line.long 0x0 "PREDR,TIMER2n Prescaler Data Register"
hexmask.long.word 0x0 0.--11. 1. "PRED,TIMER2n Prescaler Data"
rgroup.long 0x14++0x3
line.long 0x0 "CNT,TIMER2n Counter Register"
hexmask.long 0x0 0.--31. 1. "CNT,TIMER2n Counter"
group.long 0x0++0x3
line.long 0x0 "TIMER21_CR,TIMER2n Control Register"
bitfld.long 0x0 15. "T2nEN,TIMER2n Operation Enable" "0,1"
bitfld.long 0x0 14. "T2nCLK,TIMER2n Clock Selection" "0,1"
bitfld.long 0x0 12.--13. "T2nMS,TIMER2n Operation Mode Selection" "0,1,2,3"
bitfld.long 0x0 11. "T2nECE,TIMER2n External Clock Edge Selection" "0,1"
bitfld.long 0x0 8. "T2nOPOL,TIMER2n Output Polarity Selection" "0,1"
bitfld.long 0x0 6.--7. "T2nCPOL,TIMER2n Capture Polarity Selection" "0,1,2,3"
bitfld.long 0x0 5. "T2nMIEN,TIMER2n Match Interrupt Enable" "0,1"
bitfld.long 0x0 4. "T2nCIEN,TIMER2n Capture Interrupt Enable" "0,1"
bitfld.long 0x0 3. "T2nMIFLAG,TIMER2n Match Interrupt Flag" "0,1"
bitfld.long 0x0 2. "T2nCIFLAG,TIMER2n Capture Interrupt Flag" "0,1"
newline
bitfld.long 0x0 1. "T2nPAU,TIMER2n Counter Temporary Pause Control" "0,1"
bitfld.long 0x0 0. "T2nCLR,TIMER2n Counter and Prescaler Clear" "0,1"
tree.end
tree "TIMER30"
base ad:0x40002400
group.long 0x0++0x13
line.long 0x0 "CR,TIMER3n Control Register"
bitfld.long 0x0 15. "T3nEN,TIMER3n Operation Enable" "0: Disable TIMER3n Operation.,1: Enable TIMER3n Operation. (Counter Clear and.."
bitfld.long 0x0 14. "T3nCLK,TIMER3n Clock Selection" "0: Select an Internal Prescaler Clock.,1: Select an External Clock."
newline
bitfld.long 0x0 12.--13. "T3nMS,TIMER3n Operation Mode Selection" "0: Interval mode. (All match interrupts can occur),1: Capture mode. (The Period-match interrupt can..,2: Back-to-back mode. (All interrupts can occur),?"
bitfld.long 0x0 11. "T3nECE,TIMER3n External Clock Edge Selection" "0: Select falling edge of external clock.,1: Select rising edge of external clock."
newline
bitfld.long 0x0 10. "FORCA,TIMER3n Output Mode SelectionSelection. This bit should be changed while T3nEN is '0'." "0: 6-Channel mode. (The PWM3nxA/PWM3nxB pins are..,1: Force A-Channel mode. (All PWM3nxA/PWM3nxB pins.."
bitfld.long 0x0 9. "DLYEN,Delay Time Insertion Enable" "0: Disable delay time insertion to the..,1: Enable delay time insertion to the.."
newline
bitfld.long 0x0 8. "DLYPOS,Delay Time Insertion Position" "0: Insert in front of PWM3nxA and behind PWM3nxB..,1: Insert behind PWM3nxA and in front of PWM3nxB.."
bitfld.long 0x0 6.--7. "T3nCPOL,TIMER3n Capture Polarity Selection" "0: Capture on falling edge.,1: Capture on rising edge.,2: Capture on both falling and rising edge.,?"
newline
bitfld.long 0x0 4.--5. "UPDT,Data Reload Time Selection" "0: Update data to buffer at the time of writing.,1: Update data to buffer at period match.,2: Update data to buffer at bottom.,?"
bitfld.long 0x0 1.--3. "PMOC,Period Match Interrupt Occurrence Selection" "0: Once every 1 period match.,1: Once every 2 period match.,2: Once every 3 period match.,3: Once every 4 period match.,4: Once every 5 period match.,5: Once every 6 period match.,6: Once every 7 period match.,7: Once every 8 period match."
newline
bitfld.long 0x0 0. "T3nCLR,TIMER3n Counter and Prescaler Clear" "0: No effect.,1: Clear TIMER3n counter and prescaler."
line.long 0x4 "PDR,TIMER3n Period Data Register"
hexmask.long.word 0x4 0.--15. 1. "PDATA,TIMER3n Period Data"
line.long 0x8 "ADR,TIMER3n A Data Register"
hexmask.long.word 0x8 0.--15. 1. "ADATA,TIMER3n A Data"
line.long 0xC "BDR,TIMER3n B Data Register"
hexmask.long.word 0xC 0.--15. 1. "BDATA,TIMER3n B Data"
line.long 0x10 "CDR,TIMER3n C Data Register"
hexmask.long.word 0x10 0.--15. 1. "CDATA,TIMER3n C Data"
rgroup.long 0x14++0x3
line.long 0x0 "CAPDR,TIMER3n Capture Data Register"
hexmask.long.word 0x0 0.--15. 1. "CAPD,TIMER3n Capture Data"
group.long 0x18++0x3
line.long 0x0 "PREDR,TIMER3n Prescaler Data Register"
hexmask.long.word 0x0 0.--11. 1. "PRED,TIMER3n Prescaler Data"
rgroup.long 0x1C++0x3
line.long 0x0 "CNT,TIMER3n Counter Register"
hexmask.long.word 0x0 0.--15. 1. "CNT,TIMER3n Counter"
group.long 0x20++0x1B
line.long 0x0 "OUTCR,TIMER3n Output Control Register"
hexmask.long.word 0x0 16.--31. 1. "WTIDKY,Write Identification Key"
bitfld.long 0x0 15. "POLB,PWM3nxB Output Polarity Selection" "0: Low level start. (The PWM3nxB pins are started..,1: High level start. (The PWM3nxB pins are started.."
newline
bitfld.long 0x0 14. "POLA,PWM3nxA Output Polarity Selection" "0: Low level start. (The PWM3nxA pins are started..,1: High level start. (The PWM3nxA pins are started.."
bitfld.long 0x0 13. "PABOE,PWM3nAB Output Enable" "0: Disable output.,1: Enable output."
newline
bitfld.long 0x0 12. "PBBOE,PWM3nBB Output Enable" "0: Disable output.,1: Enable output."
bitfld.long 0x0 11. "PCBOE,PWM3nCB Output Enable" "0: Disable output.,1: Enable output."
newline
bitfld.long 0x0 10. "PAAOE,PWM3nAA Output Enable" "0: Disable output.,1: Enable output."
bitfld.long 0x0 9. "PBAOE,PWM3nBA Output Enable" "0: Disable output.,1: Enable output."
newline
bitfld.long 0x0 8. "PCAOE,PWM3nCA Output Enable" "0: Disable output.,1: Enable output."
bitfld.long 0x0 6. "LVLAB,Configure PWM3nAB Output when Disable" "0: Low level.,1: High level."
newline
bitfld.long 0x0 5. "LVLBB,Configure PWM3nBB Output when Disable" "0: Low level.,1: High level."
bitfld.long 0x0 4. "LVLCB,Configure PWM3nCB Output when Disable" "0: Low level.,1: High level."
newline
bitfld.long 0x0 2. "LVLAA,Configure PWM3nAA Output when Disable" "0: Low level.,1: High level."
bitfld.long 0x0 1. "LVLBA,Configure PWM3nBA Output when Disable" "0: Low level.,1: High level."
newline
bitfld.long 0x0 0. "LVLCA,Configure PWM3nCA Output when Disable" "0: Low level.,1: High level."
line.long 0x4 "DLY,TIMER3n PWM Output Delay Data Register"
hexmask.long.word 0x4 0.--9. 1. "DLY,TIMER3n PWM Delay Data"
line.long 0x8 "INTCR,TIMER3n Interrupt Control Register"
bitfld.long 0x8 6. "HIZIEN,TIMER3n Output High-Impedance Interrupt Enable" "0: Disable TIMER3n output high-impedance interrupt.,1: Enable TIMER3n output high-impedance interrupt."
bitfld.long 0x8 5. "T3nCIEN,TIMER3n Capture Interrupt Enable" "0: Disable TIMER3n capture interrupt.,1: Enable TIMER3n capture interrupt."
newline
bitfld.long 0x8 4. "T3nBTIEN,TIMER3n Bottom Interrupt Enable" "0: Disable TIMER3n bottom interrupt.,1: Enable TIMER3n bottom interrupt."
bitfld.long 0x8 3. "T3nPMIEN,TIMER3n Period Match Interrupt Enable" "0: Disable TIMER3n period interrupt.,1: Enable TIMER3n period interrupt."
newline
bitfld.long 0x8 2. "T3nAMIEN,TIMER3n A-ch Match Interrupt Enable" "0: Disable TIMER3n A-ch match interrupt.,1: Enable TIMER3n A-ch match interrupt."
bitfld.long 0x8 1. "T3nBMIEN,TIMER3n B-ch Match Interrupt Enable" "0: Disable TIMER3n B-ch match interrupt.,1: Enable TIMER3n B-ch match interrupt."
newline
bitfld.long 0x8 0. "T3nCMIEN,TIMER3n C-ch Match Interrupt Enable" "0: Disable TIMER3n C-ch match interrupt.,1: Enable TIMER3n C-ch match interrupt."
line.long 0xC "INTFLAG,TIMER3n Interrupt Flag Register"
bitfld.long 0xC 6. "HIZIFLAG,TIMER3n Output High-Impedance Interrupt Flag" "0: No request occurred.,1: Request occurred. The bit will be cleared to '0'.."
bitfld.long 0xC 5. "T3nCIFLAG,TIMER3n Capture Interrupt Flag" "0: No request occurred.,1: Request occurred. The bit will be cleared to '0'.."
newline
bitfld.long 0xC 4. "T3nBTIFLAG,TIMER3n Bottom Interrupt Flag" "0: No request occurred.,1: Request occurred. The bit will be cleared to '0'.."
bitfld.long 0xC 3. "T3nPMIFLAG,TIMER3n Period Match Interrupt Flag" "0: No request occurred.,1: Request occurred. The bit will be cleared to '0'.."
newline
bitfld.long 0xC 2. "T3nAMIFLAG,TIMER3n A-ch Match Interrupt Flag" "0: No request occurred.,1: Request occurred. The bit will be cleared to '0'.."
bitfld.long 0xC 1. "T3nBMIFLAG,TIMER3n B-ch Match Interrupt Flag" "0: No request occurred.,1: Request occurred. The bit will be cleared to '0'.."
newline
bitfld.long 0xC 0. "T3nCMIFLAG,TIMER3n C-ch Match Interrupt Flag" "0: No request occurred.,1: Request occurred. The bit will be cleared to '0'.."
line.long 0x10 "HIZCR,TIMER3n High-Impedance Control Register"
bitfld.long 0x10 7. "HIZEN,PWM3nxA/PWM3nxB Output High-Impedance Enable" "0: Disable to control the output high-impedance.,1: Enable to control the output high-impedance."
bitfld.long 0x10 4. "HIZSW,High-Impedance Output Software Setting" "0: No effect.,1: PWM3nxA/PWM3nxB pins go into high impedance."
newline
bitfld.long 0x10 2. "HEDGE,High-Impedance Edge Selection" "0: Falling edge of the BLNK pin.,1: Rising edge of the BLNK pin."
rbitfld.long 0x10 1. "HIZSTA,High-Impedance Status" "0: Indicates that the pins are not under a Hi-Z..,1: Indicates that the pins are under a Hi-Z state."
newline
bitfld.long 0x10 0. "HIZCLR,High-Impedance Output Clear" "0: No effect.,1: Clear high-impedance output. (The.."
line.long 0x14 "ADTCR,TIMER3n ADC Trigger Control Register"
bitfld.long 0x14 4. "T3nBTTG,Select TIMER3n Bottom for ADC Trigger Signal Generator." "0: Disable ADC trigger signal generator by bottom.,1: Enable ADC trigger signal generator by bottom."
bitfld.long 0x14 3. "T3nPMTG,Select TIMER3n Period Match for ADC Trigger Signal Generator." "0: Disable ADC trigger signal generator by period..,1: Enable ADC trigger signal generator by period.."
newline
bitfld.long 0x14 2. "T3nAMTG,Select TIMER3n A-ch Match for ADC Trigger Signal Generator." "0: Disable ADC trigger signal generator by A-ch..,1: Enable ADC trigger signal generator by A-ch match."
bitfld.long 0x14 1. "T3nBMTG,Select TIMER3n B-ch Match for ADC Trigger Signal Generator." "0: Disable ADC trigger signal generator by B-ch..,1: Enable ADC trigger signal generator by B-ch match."
newline
bitfld.long 0x14 0. "T3nCMTG,Select TIMER3n C-ch Match for ADC Trigger Signal Generator." "0: Disable ADC trigger signal generator by C-ch..,1: Enable ADC trigger signal generator by C-ch match."
line.long 0x18 "ADTDR,TIMER3n ADC Trigger Generator Data Register"
hexmask.long.word 0x18 0.--13. 1. "ADTDATA,TIMER3n ADC Trigger Generation Data"
group.long 0x20++0x3
line.long 0x0 "T30_OUTCR,TIMER3n Output Control Register"
hexmask.long.word 0x0 16.--31. 1. "WTIDKY,Write Identification Key (0xe06c)"
bitfld.long 0x0 15. "POLB,PWM3nxB Output Polarity Selection" "0,1"
newline
bitfld.long 0x0 14. "POLA,PWM3nxA Output Polarity Selection" "0,1"
bitfld.long 0x0 13. "PABOE,PWM3nAB Output Enable" "0,1"
newline
bitfld.long 0x0 12. "PBBOE,PWM3nBB Output Enable" "0,1"
bitfld.long 0x0 11. "PCBOE,PWM3nCB Output Enable" "0,1"
newline
bitfld.long 0x0 10. "PAAOE,PWM3nAA Output Enable" "0,1"
bitfld.long 0x0 9. "PBAOE,PWM3nBA Output Enable" "0,1"
newline
bitfld.long 0x0 8. "PCAOE,PWM3nCA Output Enable" "0,1"
bitfld.long 0x0 6. "LVLAB,Configure PWM3nAB Output when Disable" "0,1"
newline
bitfld.long 0x0 5. "LVLBB,Configure PWM3nBB Output when Disable" "0,1"
bitfld.long 0x0 4. "LVLCB,Configure PWM3nCB Output when Disable" "0,1"
newline
bitfld.long 0x0 2. "LVLAA,Configure PWM3nAA Output when Disable" "0,1"
bitfld.long 0x0 1. "LVLBA,Configure PWM3nBA Output when Disable" "0,1"
newline
bitfld.long 0x0 0. "LVLCA,Configure PWM3nCA Output when Disable" "0,1"
tree.end
tree.end
tree "UART (Universal Asynchronous Receiver/Transmitter)"
base ad:0x0
tree "UART0"
base ad:0x40004000
rgroup.long 0x0++0x3
line.long 0x0 "RBR,UARTn Receive Data Buffer Register"
hexmask.long.byte 0x0 0.--7. 1. "RBR,UARTn Receive Data Buffer"
wgroup.long 0x0++0x3
line.long 0x0 "THR,UARTn Transmit Data Hold Register"
hexmask.long.byte 0x0 0.--7. 1. "THR,UARTn Transmit Data Hold"
group.long 0x4++0x3
line.long 0x0 "IER,UARTn Interrupt Enable Register"
bitfld.long 0x0 3. "TXEIE,Transmit Register Empty Interrupt Enable" "0,1"
bitfld.long 0x0 2. "RLSIE,Receiver Line Status Interrupt Enable" "0,1"
bitfld.long 0x0 1. "THREIE,Transmit Holding Register Empty Interrupt Enable" "0,1"
bitfld.long 0x0 0. "DRIE,Data Receive Interrupt Enable" "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "IIR,UARTn Interrupt ID Register"
bitfld.long 0x0 4. "TXE,Transmit Complete Interrupt Source ID" "0,1"
bitfld.long 0x0 1.--2. "IID,UARTn Interrupt ID" "0,1,2,3"
bitfld.long 0x0 0. "IPEN,Interrupt Pending" "0,1"
group.long 0xC++0x7
line.long 0x0 "LCR,UARTn Line Control Register"
bitfld.long 0x0 6. "BREAK,Transfer Break Control" "0,1"
bitfld.long 0x0 5. "STICKP,Force Parity" "0,1"
bitfld.long 0x0 4. "PARITY,Parity Mode and Parity Stuck Selection" "0,1"
bitfld.long 0x0 3. "PEN,Parity Bit Transfer Enable" "0,1"
bitfld.long 0x0 2. "STOPBIT,Stop Bit Length Selection" "0,1"
bitfld.long 0x0 0.--1. "DLEN,Data Length Selection" "0,1,2,3"
line.long 0x4 "DCR,UARTn Data Control Register"
bitfld.long 0x4 4. "LBON,Local Loopback Test Mode Enable" "0,1"
bitfld.long 0x4 3. "RXINV,Receive Data Inversion Selection" "0,1"
bitfld.long 0x4 2. "TXINV,Transmit Data Inversion Selection" "0,1"
rgroup.long 0x14++0x3
line.long 0x0 "LSR,UARTn Line Status Register"
bitfld.long 0x0 6. "TEMT,Transmit Register Empty" "0,1"
bitfld.long 0x0 5. "THRE,Transmit Hold Register Empty" "0,1"
bitfld.long 0x0 4. "BI,Break Condition Indication" "0,1"
bitfld.long 0x0 3. "FE,Frame Error Indicator" "0,1"
bitfld.long 0x0 2. "PE,Parity Error Indicator" "0,1"
bitfld.long 0x0 1. "OE,Overrun Error Indicator" "0,1"
bitfld.long 0x0 0. "DR,Data Receive Indicator" "0,1"
group.long 0x20++0x7
line.long 0x0 "BDR,UARTn Baud Rate Divisor Latch Register"
hexmask.long.word 0x0 0.--15. 1. "BDR,Baud Rate Divider Latch Value"
line.long 0x4 "BFR,UARTn Baud Rate Fractional Counter Value"
hexmask.long.byte 0x4 0.--7. 1. "BFR,Fraction Counter value"
group.long 0x30++0x3
line.long 0x0 "IDTR,UARTn Inter-frame Delay Time Register"
bitfld.long 0x0 7. "SMS,Start Bit Multi Sampling Enable" "0,1"
bitfld.long 0x0 6. "DMS,Data Bit Multi Sampling Enable" "0,1"
bitfld.long 0x0 0.--2. "WAITVAL,Wait Time Value" "0,1,2,3,4,5,6,7"
tree.end
tree "UART1"
base ad:0x40004100
rgroup.long 0x0++0x3
line.long 0x0 "RBR,UARTn Receive Data Buffer Register"
hexmask.long.byte 0x0 0.--7. 1. "RBR,UARTn Receive Data Buffer"
wgroup.long 0x0++0x3
line.long 0x0 "THR,UARTn Transmit Data Hold Register"
hexmask.long.byte 0x0 0.--7. 1. "THR,UARTn Transmit Data Hold"
group.long 0x4++0x3
line.long 0x0 "IER,UARTn Interrupt Enable Register"
bitfld.long 0x0 3. "TXEIE,Transmit Register Empty Interrupt Enable" "0,1"
bitfld.long 0x0 2. "RLSIE,Receiver Line Status Interrupt Enable" "0,1"
bitfld.long 0x0 1. "THREIE,Transmit Holding Register Empty Interrupt Enable" "0,1"
bitfld.long 0x0 0. "DRIE,Data Receive Interrupt Enable" "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "IIR,UARTn Interrupt ID Register"
bitfld.long 0x0 4. "TXE,Transmit Complete Interrupt Source ID" "0,1"
bitfld.long 0x0 1.--2. "IID,UARTn Interrupt ID" "0,1,2,3"
bitfld.long 0x0 0. "IPEN,Interrupt Pending" "0,1"
group.long 0xC++0x7
line.long 0x0 "LCR,UARTn Line Control Register"
bitfld.long 0x0 6. "BREAK,Transfer Break Control" "0,1"
bitfld.long 0x0 5. "STICKP,Force Parity" "0,1"
bitfld.long 0x0 4. "PARITY,Parity Mode and Parity Stuck Selection" "0,1"
bitfld.long 0x0 3. "PEN,Parity Bit Transfer Enable" "0,1"
bitfld.long 0x0 2. "STOPBIT,Stop Bit Length Selection" "0,1"
bitfld.long 0x0 0.--1. "DLEN,Data Length Selection" "0,1,2,3"
line.long 0x4 "DCR,UARTn Data Control Register"
bitfld.long 0x4 4. "LBON,Local Loopback Test Mode Enable" "0,1"
bitfld.long 0x4 3. "RXINV,Receive Data Inversion Selection" "0,1"
bitfld.long 0x4 2. "TXINV,Transmit Data Inversion Selection" "0,1"
rgroup.long 0x14++0x3
line.long 0x0 "LSR,UARTn Line Status Register"
bitfld.long 0x0 6. "TEMT,Transmit Register Empty" "0,1"
bitfld.long 0x0 5. "THRE,Transmit Hold Register Empty" "0,1"
bitfld.long 0x0 4. "BI,Break Condition Indication" "0,1"
bitfld.long 0x0 3. "FE,Frame Error Indicator" "0,1"
bitfld.long 0x0 2. "PE,Parity Error Indicator" "0,1"
bitfld.long 0x0 1. "OE,Overrun Error Indicator" "0,1"
bitfld.long 0x0 0. "DR,Data Receive Indicator" "0,1"
group.long 0x20++0x7
line.long 0x0 "BDR,UARTn Baud Rate Divisor Latch Register"
hexmask.long.word 0x0 0.--15. 1. "BDR,Baud Rate Divider Latch Value"
line.long 0x4 "BFR,UARTn Baud Rate Fractional Counter Value"
hexmask.long.byte 0x4 0.--7. 1. "BFR,Fraction Counter value"
group.long 0x30++0x3
line.long 0x0 "IDTR,UARTn Inter-frame Delay Time Register"
bitfld.long 0x0 7. "SMS,Start Bit Multi Sampling Enable" "0,1"
bitfld.long 0x0 6. "DMS,Data Bit Multi Sampling Enable" "0,1"
bitfld.long 0x0 0.--2. "WAITVAL,Wait Time Value" "0,1,2,3,4,5,6,7"
tree.end
tree "UARTn"
base ad:0x55000000
rgroup.long 0x0++0x3
line.long 0x0 "RBR,UARTn Receive Data Buffer Register"
hexmask.long.byte 0x0 0.--7. 1. "RBR,UARTn Receive Data Buffer"
wgroup.long 0x0++0x3
line.long 0x0 "THR,UARTn Transmit Data Hold Register"
hexmask.long.byte 0x0 0.--7. 1. "THR,UARTn Transmit Data Hold"
group.long 0x4++0x3
line.long 0x0 "IER,UARTn Interrupt Enable Register"
bitfld.long 0x0 3. "TXEIE,Transmit Register Empty Interrupt Enable" "0,1"
bitfld.long 0x0 2. "RLSIE,Receiver Line Status Interrupt Enable" "0,1"
bitfld.long 0x0 1. "THREIE,Transmit Holding Register Empty Interrupt Enable" "0,1"
bitfld.long 0x0 0. "DRIE,Data Receive Interrupt Enable" "0,1"
rgroup.long 0x8++0x3
line.long 0x0 "IIR,UARTn Interrupt ID Register"
bitfld.long 0x0 4. "TXE,Transmit Complete Interrupt Source ID" "0,1"
bitfld.long 0x0 1.--2. "IID,UARTn Interrupt ID" "0,1,2,3"
bitfld.long 0x0 0. "IPEN,Interrupt Pending" "0,1"
group.long 0xC++0x7
line.long 0x0 "LCR,UARTn Line Control Register"
bitfld.long 0x0 6. "BREAK,Transfer Break Control" "0,1"
bitfld.long 0x0 5. "STICKP,Force Parity" "0,1"
bitfld.long 0x0 4. "PARITY,Parity Mode and Parity Stuck Selection" "0,1"
bitfld.long 0x0 3. "PEN,Parity Bit Transfer Enable" "0,1"
bitfld.long 0x0 2. "STOPBIT,Stop Bit Length Selection" "0,1"
bitfld.long 0x0 0.--1. "DLEN,Data Length Selection" "0,1,2,3"
line.long 0x4 "DCR,UARTn Data Control Register"
bitfld.long 0x4 4. "LBON,Local Loopback Test Mode Enable" "0,1"
bitfld.long 0x4 3. "RXINV,Receive Data Inversion Selection" "0,1"
bitfld.long 0x4 2. "TXINV,Transmit Data Inversion Selection" "0,1"
rgroup.long 0x14++0x3
line.long 0x0 "LSR,UARTn Line Status Register"
bitfld.long 0x0 6. "TEMT,Transmit Register Empty" "0,1"
bitfld.long 0x0 5. "THRE,Transmit Hold Register Empty" "0,1"
bitfld.long 0x0 4. "BI,Break Condition Indication" "0,1"
bitfld.long 0x0 3. "FE,Frame Error Indicator" "0,1"
bitfld.long 0x0 2. "PE,Parity Error Indicator" "0,1"
bitfld.long 0x0 1. "OE,Overrun Error Indicator" "0,1"
bitfld.long 0x0 0. "DR,Data Receive Indicator" "0,1"
group.long 0x20++0x7
line.long 0x0 "BDR,UARTn Baud Rate Divisor Latch Register"
hexmask.long.word 0x0 0.--15. 1. "BDR,Baud Rate Divider Latch Value"
line.long 0x4 "BFR,UARTn Baud Rate Fractional Counter Value"
hexmask.long.byte 0x4 0.--7. 1. "BFR,Fraction Counter value"
group.long 0x30++0x3
line.long 0x0 "IDTR,UARTn Inter-frame Delay Time Register"
bitfld.long 0x0 7. "SMS,Start Bit Multi Sampling Enable" "0,1"
bitfld.long 0x0 6. "DMS,Data Bit Multi Sampling Enable" "0,1"
bitfld.long 0x0 0.--2. "WAITVAL,Wait Time Value" "0,1,2,3,4,5,6,7"
tree.end
tree.end
tree "USART&SPI (Universal Synchronous/Asynchronous Receiver/Transmitter + Serial Peripheral Interface)"
base ad:0x0
sif (cpuis("A31G12?*"))
tree "USART12"
base ad:0x40003A00
group.long 0x0++0x7
line.long 0x0 "CR1,USART1n Control Register 1"
bitfld.long 0x0 14.--15. "USTnMS,USART1n Operation Mode Selection" "0: Asynchronous Mode (UART),1: Synchronous Mode (USRT),?,3: SPI Mode"
bitfld.long 0x0 12.--13. "USTnP,Selects Parity Generation and Check method (only UART mode)" "0: No Parity,?,2: Even Parity,3: Odd Parity"
bitfld.long 0x0 9.--11. "USTnS,Selects the length of data bit in a frame when Asynchronous or Synchronous mode" "0: 5 bit,1: 6 bit,2: 7 bit,3: 8 bit,?,?,?,7: 9 bit"
newline
bitfld.long 0x0 8. "ORDn,Selects the first data bit to be transmitted (only SPI mode)" "0: LSB First,1: MSB First"
bitfld.long 0x0 7. "CPOLn,Selects the Clock Polarity of ACK in Synchronous or SPI mode" "0: TXD Change @Rising Edge RXD Change @Falling Edge,1: TXD Change @Falling Edge RXD Change @Rising Edge"
bitfld.long 0x0 6. "CPHAn,The CPOLn and this bit determine if data are sampled on the leading or trailing edge of SCK (only SPI mode)" "0: Start with idle state.,1: Start with inverted idle state."
newline
bitfld.long 0x0 5. "DRIEn,Transmit Data Register Empty Interrupt Enable" "0,1"
bitfld.long 0x0 4. "TXCIEn,Transmit Complete Interrupt Enable" "0,1"
bitfld.long 0x0 3. "RXCIEn,Receive Complete Interrupt Enable" "0,1"
newline
bitfld.long 0x0 2. "WAKEIEn,Asynchronous Wake-Up Interrupt Enable in Deep Sleep Mode" "0,1"
bitfld.long 0x0 1. "TXEn,Enable the transmitter unit." "0,1"
bitfld.long 0x0 0. "RXEn,Enable the receiver unit." "0,1"
line.long 0x4 "CR2,USART1n Control Register 2"
bitfld.long 0x4 9. "USTnEN,Activate USART1n Block" "0,1"
bitfld.long 0x4 8. "DBLSn,Selects receiver sampling rate (only UART mode)" "0,1"
bitfld.long 0x4 7. "MASTERn,Selects master or slave in SPI1n or Synchronous mode and controls the direction of SCK1n pin" "0,1"
newline
bitfld.long 0x4 6. "LOOPSn,Control the Loop Back mode of USART1n for test mode" "0,1"
bitfld.long 0x4 5. "DISSCKn,In synchronous mode operation selects the waveform of SCK1n output" "0,1"
bitfld.long 0x4 4. "USTnSSEN,This bit controls the SS1n pin operation (only SPI mode)" "0,1"
newline
bitfld.long 0x4 3. "FXCHn,SPI1n port function exchange control (only SPI mode)" "0,1"
bitfld.long 0x4 2. "USTnSB,Selects the length of stop bit in Asynchronous or Synchronous mode" "0,1"
bitfld.long 0x4 1. "USTnTX8,The ninth bit of data frame in Asynchronous or Synchronous mode of operation" "0,1"
newline
bitfld.long 0x4 0. "USTnRX8,The ninth bit of data frame in Asynchronous or Synchronous mode of operation" "0,1"
group.long 0xC++0xB
line.long 0x0 "ST,USART1n Status Register"
bitfld.long 0x0 7. "DREn,Transmit Data Register Empty Interrupt Flag" "0,1"
bitfld.long 0x0 6. "TXCn,Transmit Complete Interrupt Flag" "0,1"
rbitfld.long 0x0 5. "RXCn,Receive Complete Interrupt Flag" "0,1"
newline
bitfld.long 0x0 4. "WAKEn,Asynchronous Wake-Up Interrupt Flag" "0,1"
rbitfld.long 0x0 2. "DORn,This bit is set if data OverRun takes place" "0,1"
bitfld.long 0x0 1. "FEn,This bit is set if the first stop bit of next character in the receive buffer is detected as '0'" "0,1"
newline
bitfld.long 0x0 0. "PEn,This bit is set if the next character in the receive buffer has a Parity Error while parity is checked" "0,1"
line.long 0x4 "BDR,USART1n Baud Rate Generation Register"
hexmask.long.word 0x4 0.--11. 1. "BDATA,The value in this register is used to generate internal baud rate in UART mode or to generate SCK clock in SPI mode"
line.long 0x8 "DR,USART1n Data Register"
hexmask.long.byte 0x8 0.--7. 1. "DATA,The USART Transmit buffer and Receive buffer share the same I/O address with this DATA register"
tree.end
endif
sif (cpuis("A31G12?*"))
tree "USART13"
base ad:0x40003B00
group.long 0x0++0x7
line.long 0x0 "CR1,USART1n Control Register 1"
bitfld.long 0x0 14.--15. "USTnMS,USART1n Operation Mode Selection" "0: Asynchronous Mode (UART),1: Synchronous Mode (USRT),?,3: SPI Mode"
bitfld.long 0x0 12.--13. "USTnP,Selects Parity Generation and Check method (only UART mode)" "0: No Parity,?,2: Even Parity,3: Odd Parity"
bitfld.long 0x0 9.--11. "USTnS,Selects the length of data bit in a frame when Asynchronous or Synchronous mode" "0: 5 bit,1: 6 bit,2: 7 bit,3: 8 bit,?,?,?,7: 9 bit"
newline
bitfld.long 0x0 8. "ORDn,Selects the first data bit to be transmitted (only SPI mode)" "0: LSB First,1: MSB First"
bitfld.long 0x0 7. "CPOLn,Selects the Clock Polarity of ACK in Synchronous or SPI mode" "0: TXD Change @Rising Edge RXD Change @Falling Edge,1: TXD Change @Falling Edge RXD Change @Rising Edge"
bitfld.long 0x0 6. "CPHAn,The CPOLn and this bit determine if data are sampled on the leading or trailing edge of SCK (only SPI mode)" "0: Start with idle state.,1: Start with inverted idle state."
newline
bitfld.long 0x0 5. "DRIEn,Transmit Data Register Empty Interrupt Enable" "0,1"
bitfld.long 0x0 4. "TXCIEn,Transmit Complete Interrupt Enable" "0,1"
bitfld.long 0x0 3. "RXCIEn,Receive Complete Interrupt Enable" "0,1"
newline
bitfld.long 0x0 2. "WAKEIEn,Asynchronous Wake-Up Interrupt Enable in Deep Sleep Mode" "0,1"
bitfld.long 0x0 1. "TXEn,Enable the transmitter unit." "0,1"
bitfld.long 0x0 0. "RXEn,Enable the receiver unit." "0,1"
line.long 0x4 "CR2,USART1n Control Register 2"
bitfld.long 0x4 9. "USTnEN,Activate USART1n Block" "0,1"
bitfld.long 0x4 8. "DBLSn,Selects receiver sampling rate (only UART mode)" "0,1"
bitfld.long 0x4 7. "MASTERn,Selects master or slave in SPI1n or Synchronous mode and controls the direction of SCK1n pin" "0,1"
newline
bitfld.long 0x4 6. "LOOPSn,Control the Loop Back mode of USART1n for test mode" "0,1"
bitfld.long 0x4 5. "DISSCKn,In synchronous mode operation selects the waveform of SCK1n output" "0,1"
bitfld.long 0x4 4. "USTnSSEN,This bit controls the SS1n pin operation (only SPI mode)" "0,1"
newline
bitfld.long 0x4 3. "FXCHn,SPI1n port function exchange control (only SPI mode)" "0,1"
bitfld.long 0x4 2. "USTnSB,Selects the length of stop bit in Asynchronous or Synchronous mode" "0,1"
bitfld.long 0x4 1. "USTnTX8,The ninth bit of data frame in Asynchronous or Synchronous mode of operation" "0,1"
newline
bitfld.long 0x4 0. "USTnRX8,The ninth bit of data frame in Asynchronous or Synchronous mode of operation" "0,1"
group.long 0xC++0xB
line.long 0x0 "ST,USART1n Status Register"
bitfld.long 0x0 7. "DREn,Transmit Data Register Empty Interrupt Flag" "0,1"
bitfld.long 0x0 6. "TXCn,Transmit Complete Interrupt Flag" "0,1"
rbitfld.long 0x0 5. "RXCn,Receive Complete Interrupt Flag" "0,1"
newline
bitfld.long 0x0 4. "WAKEn,Asynchronous Wake-Up Interrupt Flag" "0,1"
rbitfld.long 0x0 2. "DORn,This bit is set if data OverRun takes place" "0,1"
bitfld.long 0x0 1. "FEn,This bit is set if the first stop bit of next character in the receive buffer is detected as '0'" "0,1"
newline
bitfld.long 0x0 0. "PEn,This bit is set if the next character in the receive buffer has a Parity Error while parity is checked" "0,1"
line.long 0x4 "BDR,USART1n Baud Rate Generation Register"
hexmask.long.word 0x4 0.--11. 1. "BDATA,The value in this register is used to generate internal baud rate in UART mode or to generate SCK clock in SPI mode"
line.long 0x8 "DR,USART1n Data Register"
hexmask.long.byte 0x8 0.--7. 1. "DATA,The USART Transmit buffer and Receive buffer share the same I/O address with this DATA register"
tree.end
endif
tree "USART1n"
base ad:0x54000000
group.long 0x0++0x7
line.long 0x0 "CR1,USART1n Control Register 1"
bitfld.long 0x0 14.--15. "USTnMS,USART1n Operation Mode Selection" "0: Asynchronous Mode (UART),1: Synchronous Mode (USRT),?,3: SPI Mode"
bitfld.long 0x0 12.--13. "USTnP,Selects Parity Generation and Check method (only UART mode)" "0: No Parity,?,2: Even Parity,3: Odd Parity"
bitfld.long 0x0 9.--11. "USTnS,Selects the length of data bit in a frame when Asynchronous or Synchronous mode" "0: 5 bit,1: 6 bit,2: 7 bit,3: 8 bit,?,?,?,7: 9 bit"
newline
bitfld.long 0x0 8. "ORDn,Selects the first data bit to be transmitted (only SPI mode)" "0: LSB First,1: MSB First"
bitfld.long 0x0 7. "CPOLn,Selects the Clock Polarity of ACK in Synchronous or SPI mode" "0: TXD Change @Rising Edge RXD Change @Falling Edge,1: TXD Change @Falling Edge RXD Change @Rising Edge"
bitfld.long 0x0 6. "CPHAn,The CPOLn and this bit determine if data are sampled on the leading or trailing edge of SCK (only SPI mode)" "0: Start with idle state.,1: Start with inverted idle state."
newline
bitfld.long 0x0 5. "DRIEn,Transmit Data Register Empty Interrupt Enable" "0,1"
bitfld.long 0x0 4. "TXCIEn,Transmit Complete Interrupt Enable" "0,1"
bitfld.long 0x0 3. "RXCIEn,Receive Complete Interrupt Enable" "0,1"
newline
bitfld.long 0x0 2. "WAKEIEn,Asynchronous Wake-Up Interrupt Enable in Deep Sleep Mode" "0,1"
bitfld.long 0x0 1. "TXEn,Enable the transmitter unit." "0,1"
bitfld.long 0x0 0. "RXEn,Enable the receiver unit." "0,1"
line.long 0x4 "CR2,USART1n Control Register 2"
bitfld.long 0x4 9. "USTnEN,Activate USART1n Block" "0,1"
bitfld.long 0x4 8. "DBLSn,Selects receiver sampling rate (only UART mode)" "0,1"
bitfld.long 0x4 7. "MASTERn,Selects master or slave in SPI1n or Synchronous mode and controls the direction of SCK1n pin" "0,1"
newline
bitfld.long 0x4 6. "LOOPSn,Control the Loop Back mode of USART1n for test mode" "0,1"
bitfld.long 0x4 5. "DISSCKn,In synchronous mode operation selects the waveform of SCK1n output" "0,1"
bitfld.long 0x4 4. "USTnSSEN,This bit controls the SS1n pin operation (only SPI mode)" "0,1"
newline
bitfld.long 0x4 3. "FXCHn,SPI1n port function exchange control (only SPI mode)" "0,1"
bitfld.long 0x4 2. "USTnSB,Selects the length of stop bit in Asynchronous or Synchronous mode" "0,1"
bitfld.long 0x4 1. "USTnTX8,The ninth bit of data frame in Asynchronous or Synchronous mode of operation" "0,1"
newline
bitfld.long 0x4 0. "USTnRX8,The ninth bit of data frame in Asynchronous or Synchronous mode of operation" "0,1"
group.long 0xC++0xB
line.long 0x0 "ST,USART1n Status Register"
bitfld.long 0x0 7. "DREn,Transmit Data Register Empty Interrupt Flag" "0,1"
bitfld.long 0x0 6. "TXCn,Transmit Complete Interrupt Flag" "0,1"
rbitfld.long 0x0 5. "RXCn,Receive Complete Interrupt Flag" "0,1"
newline
bitfld.long 0x0 4. "WAKEn,Asynchronous Wake-Up Interrupt Flag" "0,1"
rbitfld.long 0x0 2. "DORn,This bit is set if data OverRun takes place" "0,1"
bitfld.long 0x0 1. "FEn,This bit is set if the first stop bit of next character in the receive buffer is detected as '0'" "0,1"
newline
bitfld.long 0x0 0. "PEn,This bit is set if the next character in the receive buffer has a Parity Error while parity is checked" "0,1"
line.long 0x4 "BDR,USART1n Baud Rate Generation Register"
hexmask.long.word 0x4 0.--11. 1. "BDATA,The value in this register is used to generate internal baud rate in UART mode or to generate SCK clock in SPI mode"
line.long 0x8 "DR,USART1n Data Register"
hexmask.long.byte 0x8 0.--7. 1. "DATA,The USART Transmit buffer and Receive buffer share the same I/O address with this DATA register"
tree.end
tree "USART10"
base ad:0x40003800
group.long 0x0++0x7
line.long 0x0 "CR1,USART1n Control Register 1"
bitfld.long 0x0 14.--15. "USTnMS,USART1n Operation Mode Selection" "0: Asynchronous Mode (UART),1: Synchronous Mode (USRT),?,3: SPI Mode"
bitfld.long 0x0 12.--13. "USTnP,Selects Parity Generation and Check method (only UART mode)" "0: No Parity,?,2: Even Parity,3: Odd Parity"
bitfld.long 0x0 9.--11. "USTnS,Selects the length of data bit in a frame when Asynchronous or Synchronous mode" "0: 5 bit,1: 6 bit,2: 7 bit,3: 8 bit,?,?,?,7: 9 bit"
newline
bitfld.long 0x0 8. "ORDn,Selects the first data bit to be transmitted (only SPI mode)" "0: LSB First,1: MSB First"
bitfld.long 0x0 7. "CPOLn,Selects the Clock Polarity of ACK in Synchronous or SPI mode" "0: TXD Change @Rising Edge RXD Change @Falling Edge,1: TXD Change @Falling Edge RXD Change @Rising Edge"
bitfld.long 0x0 6. "CPHAn,The CPOLn and this bit determine if data are sampled on the leading or trailing edge of SCK (only SPI mode)" "0: Start with idle state.,1: Start with inverted idle state."
newline
bitfld.long 0x0 5. "DRIEn,Transmit Data Register Empty Interrupt Enable" "0,1"
bitfld.long 0x0 4. "TXCIEn,Transmit Complete Interrupt Enable" "0,1"
bitfld.long 0x0 3. "RXCIEn,Receive Complete Interrupt Enable" "0,1"
newline
bitfld.long 0x0 2. "WAKEIEn,Asynchronous Wake-Up Interrupt Enable in Deep Sleep Mode" "0,1"
bitfld.long 0x0 1. "TXEn,Enable the transmitter unit." "0,1"
bitfld.long 0x0 0. "RXEn,Enable the receiver unit." "0,1"
line.long 0x4 "CR2,USART1n Control Register 2"
bitfld.long 0x4 9. "USTnEN,Activate USART1n Block" "0,1"
bitfld.long 0x4 8. "DBLSn,Selects receiver sampling rate (only UART mode)" "0,1"
bitfld.long 0x4 7. "MASTERn,Selects master or slave in SPI1n or Synchronous mode and controls the direction of SCK1n pin" "0,1"
newline
bitfld.long 0x4 6. "LOOPSn,Control the Loop Back mode of USART1n for test mode" "0,1"
bitfld.long 0x4 5. "DISSCKn,In synchronous mode operation selects the waveform of SCK1n output" "0,1"
bitfld.long 0x4 4. "USTnSSEN,This bit controls the SS1n pin operation (only SPI mode)" "0,1"
newline
bitfld.long 0x4 3. "FXCHn,SPI1n port function exchange control (only SPI mode)" "0,1"
bitfld.long 0x4 2. "USTnSB,Selects the length of stop bit in Asynchronous or Synchronous mode" "0,1"
bitfld.long 0x4 1. "USTnTX8,The ninth bit of data frame in Asynchronous or Synchronous mode of operation" "0,1"
newline
bitfld.long 0x4 0. "USTnRX8,The ninth bit of data frame in Asynchronous or Synchronous mode of operation" "0,1"
group.long 0xC++0xB
line.long 0x0 "ST,USART1n Status Register"
bitfld.long 0x0 7. "DREn,Transmit Data Register Empty Interrupt Flag" "0,1"
bitfld.long 0x0 6. "TXCn,Transmit Complete Interrupt Flag" "0,1"
rbitfld.long 0x0 5. "RXCn,Receive Complete Interrupt Flag" "0,1"
newline
bitfld.long 0x0 4. "WAKEn,Asynchronous Wake-Up Interrupt Flag" "0,1"
rbitfld.long 0x0 2. "DORn,This bit is set if data OverRun takes place" "0,1"
bitfld.long 0x0 1. "FEn,This bit is set if the first stop bit of next character in the receive buffer is detected as '0'" "0,1"
newline
bitfld.long 0x0 0. "PEn,This bit is set if the next character in the receive buffer has a Parity Error while parity is checked" "0,1"
line.long 0x4 "BDR,USART1n Baud Rate Generation Register"
hexmask.long.word 0x4 0.--11. 1. "BDATA,The value in this register is used to generate internal baud rate in UART mode or to generate SCK clock in SPI mode"
line.long 0x8 "DR,USART1n Data Register"
hexmask.long.byte 0x8 0.--7. 1. "DATA,The USART Transmit buffer and Receive buffer share the same I/O address with this DATA register"
tree.end
tree "USART11"
base ad:0x40003900
group.long 0x0++0x7
line.long 0x0 "CR1,USART1n Control Register 1"
bitfld.long 0x0 14.--15. "USTnMS,USART1n Operation Mode Selection" "0: Asynchronous Mode (UART),1: Synchronous Mode (USRT),?,3: SPI Mode"
bitfld.long 0x0 12.--13. "USTnP,Selects Parity Generation and Check method (only UART mode)" "0: No Parity,?,2: Even Parity,3: Odd Parity"
bitfld.long 0x0 9.--11. "USTnS,Selects the length of data bit in a frame when Asynchronous or Synchronous mode" "0: 5 bit,1: 6 bit,2: 7 bit,3: 8 bit,?,?,?,7: 9 bit"
newline
bitfld.long 0x0 8. "ORDn,Selects the first data bit to be transmitted (only SPI mode)" "0: LSB First,1: MSB First"
bitfld.long 0x0 7. "CPOLn,Selects the Clock Polarity of ACK in Synchronous or SPI mode" "0: TXD Change @Rising Edge RXD Change @Falling Edge,1: TXD Change @Falling Edge RXD Change @Rising Edge"
bitfld.long 0x0 6. "CPHAn,The CPOLn and this bit determine if data are sampled on the leading or trailing edge of SCK (only SPI mode)" "0: Start with idle state.,1: Start with inverted idle state."
newline
bitfld.long 0x0 5. "DRIEn,Transmit Data Register Empty Interrupt Enable" "0,1"
bitfld.long 0x0 4. "TXCIEn,Transmit Complete Interrupt Enable" "0,1"
bitfld.long 0x0 3. "RXCIEn,Receive Complete Interrupt Enable" "0,1"
newline
bitfld.long 0x0 2. "WAKEIEn,Asynchronous Wake-Up Interrupt Enable in Deep Sleep Mode" "0,1"
bitfld.long 0x0 1. "TXEn,Enable the transmitter unit." "0,1"
bitfld.long 0x0 0. "RXEn,Enable the receiver unit." "0,1"
line.long 0x4 "CR2,USART1n Control Register 2"
bitfld.long 0x4 9. "USTnEN,Activate USART1n Block" "0,1"
bitfld.long 0x4 8. "DBLSn,Selects receiver sampling rate (only UART mode)" "0,1"
bitfld.long 0x4 7. "MASTERn,Selects master or slave in SPI1n or Synchronous mode and controls the direction of SCK1n pin" "0,1"
newline
bitfld.long 0x4 6. "LOOPSn,Control the Loop Back mode of USART1n for test mode" "0,1"
bitfld.long 0x4 5. "DISSCKn,In synchronous mode operation selects the waveform of SCK1n output" "0,1"
bitfld.long 0x4 4. "USTnSSEN,This bit controls the SS1n pin operation (only SPI mode)" "0,1"
newline
bitfld.long 0x4 3. "FXCHn,SPI1n port function exchange control (only SPI mode)" "0,1"
bitfld.long 0x4 2. "USTnSB,Selects the length of stop bit in Asynchronous or Synchronous mode" "0,1"
bitfld.long 0x4 1. "USTnTX8,The ninth bit of data frame in Asynchronous or Synchronous mode of operation" "0,1"
newline
bitfld.long 0x4 0. "USTnRX8,The ninth bit of data frame in Asynchronous or Synchronous mode of operation" "0,1"
group.long 0xC++0xB
line.long 0x0 "ST,USART1n Status Register"
bitfld.long 0x0 7. "DREn,Transmit Data Register Empty Interrupt Flag" "0,1"
bitfld.long 0x0 6. "TXCn,Transmit Complete Interrupt Flag" "0,1"
rbitfld.long 0x0 5. "RXCn,Receive Complete Interrupt Flag" "0,1"
newline
bitfld.long 0x0 4. "WAKEn,Asynchronous Wake-Up Interrupt Flag" "0,1"
rbitfld.long 0x0 2. "DORn,This bit is set if data OverRun takes place" "0,1"
bitfld.long 0x0 1. "FEn,This bit is set if the first stop bit of next character in the receive buffer is detected as '0'" "0,1"
newline
bitfld.long 0x0 0. "PEn,This bit is set if the next character in the receive buffer has a Parity Error while parity is checked" "0,1"
line.long 0x4 "BDR,USART1n Baud Rate Generation Register"
hexmask.long.word 0x4 0.--11. 1. "BDATA,The value in this register is used to generate internal baud rate in UART mode or to generate SCK clock in SPI mode"
line.long 0x8 "DR,USART1n Data Register"
hexmask.long.byte 0x8 0.--7. 1. "DATA,The USART Transmit buffer and Receive buffer share the same I/O address with this DATA register"
tree.end
tree.end
tree "WDT (Watchdog Timer)"
base ad:0x40001A00
group.long 0x0++0xB
line.long 0x0 "CR,Watch-Dog Timer Control Register"
hexmask.long.word 0x0 16.--31. 1. "WTIDKY,Write Identification Key (0x5a69)"
hexmask.long.byte 0x0 10.--15. 1. "RSTEN,Watch-Dog Timer Reset Enable"
newline
hexmask.long.byte 0x0 4.--9. 1. "CNTEN,Watch-Dog Timer Counter Enable"
bitfld.long 0x0 3. "WINMIEN,Watch-Dog Timer Window Match Interrupt Enable" "0: Disable window data match interrupt.,1: Enable window data match interrupt."
newline
bitfld.long 0x0 2. "UNFIEN,Watch-Dog Timer Underflow Interrupt Enable" "0: Disable Watch-Dog Timer underflow interrupt.,1: Enable Watch-Dog Timer underflow interrupt."
bitfld.long 0x0 0.--1. "CLKDIV,Watch-Dog Timer Clock Divider" "0: fWDT/4,1: fWDT/16,2: fWDT/64,3: fWDT/256"
line.long 0x4 "SR,Watch-Dog Timer Status Register"
bitfld.long 0x4 7. "DBGCNTEN,Watch-Dog Timer Counter Enable when the core is halted in debug mode" "0: The Watch-Dog Timer counter continues even if..,1: The Watch-Dog Timer counter is stopped when the.."
bitfld.long 0x4 1. "WINMIFLAG,Watch-Dog Timer Window Match Interrupt Flag" "0: No request occurred.,1: Request occurred."
newline
bitfld.long 0x4 0. "UNFIFLAG,Watch-Dog Timer Underflow Interrupt Flag" "0: No request occurred.,1: Request occurred."
line.long 0x8 "DR,Watch-Dog Timer Data Register"
hexmask.long.tbyte 0x8 0.--23. 1. "DATA,Watch-Dog Timer Data"
rgroup.long 0xC++0x3
line.long 0x0 "CNT,Watch-Dog Timer Counter Register"
hexmask.long.tbyte 0x0 0.--23. 1. "CNT,Watch-Dog Timer Counter"
group.long 0x10++0x3
line.long 0x0 "WINDR,Watch-Dog Timer Window Data Register"
hexmask.long.tbyte 0x0 0.--23. 1. "WDATA,Watch-Dog Timer Window Data"
wgroup.long 0x14++0x3
line.long 0x0 "CNTR,Watch-Dog Timer Counter Reload Register"
hexmask.long.byte 0x0 0.--7. 1. "CNTR,Watch-Dog Timer Counter Reload"
tree.end
tree "WT (Watch Timer)"
base ad:0x40002000
group.long 0x0++0x7
line.long 0x0 "CR,Watch Timer Control Register"
bitfld.long 0x0 7. "WTEN,Watch Timer Operation Enable" "0: Disable watch timer operation.,1: Enable watch timer operation."
bitfld.long 0x0 4.--5. "WTINTV,Watch Timer Interval Selection" "0: fWT/2^7,1: fWT/2^13,2: fWT/2^14,3: fWT/(2^14x(WTDR value + 1))"
bitfld.long 0x0 3. "WTIEN,Watch Timer Interrupt Enable" "0: Disable watch timer interrupt.,1: Enable watch timer interrupt."
newline
bitfld.long 0x0 1. "WTIFLAG,Watch Timer Interrupt Flag" "0: No request occurred.,1: Request occurred."
bitfld.long 0x0 0. "WTCLR,Watch Timer Counter and Divider Clear" "0: No effect.,1: Clear the counter and divider. (Automatically.."
line.long 0x4 "DR,Watch Timer Data Register"
hexmask.long.word 0x4 0.--11. 1. "WTDATA,Watch Timer Data"
rgroup.long 0x8++0x3
line.long 0x0 "CNT,Watch Timer Counter Register"
hexmask.long.word 0x0 0.--11. 1. "CNT,Watch Timer Counter"
tree.end
AUTOINDENT.OFF
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