6441 lines
371 KiB
Plaintext
6441 lines
371 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: 81341, 81342, 81348 On-Chip Peripherals
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; @Props: Released
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; @Author: LUK, ZEN
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; @Changelog: 2007-07-05
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; @Manufacturer: INTEL - Intel Corporation
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; @Doc: DevMan-31503701.pdf (315037-001US 2006-09)
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; DS-315039.pdf (315039-001US 2006-10)
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; SpecUpd-31504204.pdf (315042-004US 2007-03)
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; @Core: Xscale
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; @Chip: 81341, 81342, 81348
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; @Chiplist: I81341, I81342, I81348
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; @Copyright: (C) 1989-2014 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: per8134x.per 6547 2015-11-26 09:19:35Z askoncej $
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config 16. 8.
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width 8.
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tree "PMMRBAR (Peripheral Memory-Mapped Register Base Address Register)"
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base asd:0x0f:0xFFD80000
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width 0xb
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group.long 0x0++0x3
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line.long 0x0 "PMMRBAR,Peripheral Memory-Mapped Base Address Register"
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bitfld.long 0x0 28.--31. " PMMRBAR ,PMMR Base Address bits [35:32]" "00,01,02,03,04,05,06,07,08,09,0a,0b,0c,0d,0e,0f"
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hexmask.long 0x0 15.--27. 0x80000 ":,PMMR Base Address bits [31:0]"
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width 0xb
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tree.end
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tree "PCI-X"
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; if (((data.long(asd:(0x0:0xFFD80000+0x2188)))&0x8000)==0x8000)
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; ESSTSR0 -> INTERFACE_SEL_PCIX == 1
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base asd:(0x0:0xFFD80000+0x4C000)
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; else
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; base asd:(0x0:0xFFD80000+0x48000)
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; endif
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width 0xd
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rgroup.word 0x0++0x3
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line.word 0x00 "ATUVID,ATU Vendor ID Register"
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line.word 0x02 "ATUDID,ATU Device ID Register"
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group.word 0x4++0x3
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line.word 0x0 "ATUCMD,ATU Command Register"
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bitfld.word 0x0 10. " INTDIS ,Interrupt Disable" "Enabled,Disabled"
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bitfld.word 0x0 9. " FBTBE ,Fast Back to Back Enable" "Disabled,Enabled"
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bitfld.word 0x0 8. " SERR ,SERR Enable" "Not asserted,Asserted"
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textline " "
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bitfld.word 0x0 6. " PER ,Parity Error Response" "Disabled,Enabled"
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bitfld.word 0x0 5. " VGA ,VGA Palette Snoop Enable" "Disabled,Enabled"
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bitfld.word 0x0 4. " MWI ,Memory Write and Invalidate Enable" "Disabled,Enabled"
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textline " "
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bitfld.word 0x0 2. " BME ,Bus Master Enable" "Disabled,Enabled"
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bitfld.word 0x0 1. " MEMORY ,Memory Enable" "Disabled,Enabled"
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bitfld.word 0x0 0. " IOSPACE ,I/O Space Enable" "Disabled,Enabled"
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line.word 0x02 "ATUSR,ATU Status Register"
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eventfld.word 0x2 15. " PARERR ,Detected Parity Error" "No error,Error"
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eventfld.word 0x2 14. " SERR ,SERR asserted" "Not asserted,Asserted"
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eventfld.word 0x2 13. " MA ,Master Abort" "Disabled,Enabled"
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textline " "
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eventfld.word 0x2 12. " TAM ,Target Abort (master)" "Disabled,Enabled"
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eventfld.word 0x2 11. " TAT ,Target Abort (target)" "Disabled,Enabled"
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bitfld.word 0x2 9.--10. " DEVTIM ,DEVSEL# Timing" "Fast,Medium,Slow,Reserved"
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textline " "
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eventfld.word 0x2 8. " MPERR ,Master Parity Error" "No error,Error"
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bitfld.word 0x2 7. " FB2B ,Fast Back-to-Back" "Disabled,Enabled"
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bitfld.word 0x2 5. " 66MHZ ,66 MHz Supported" "Not supported,Supported"
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textline " "
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bitfld.word 0x2 4. " CAP ,Capabilities" "Normal,Extended"
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bitfld.word 0x2 3. " INTERRUPT ,Interrupt Status" "No interrupt,Interrupt"
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rgroup.byte 0x08++0x00
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line.byte 0x00 "ATURID,ATU Revision ID Register"
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rgroup.byte 0x09++0x03
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line.tbyte 0x00 "ATUCCR,ATU Class Code Register"
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hexmask.tbyte.byte 0x0 16.--23. 1. " BC ,Base Class - Memory Controller"
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hexmask.tbyte.byte 0x0 08.--15. 1. " SC ,Sub Class - Other Memory Controller"
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hexmask.tbyte.byte 0x0 00.--07. 1. " PI ,Programming Interface - None defined"
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group.byte 0x0c++0x01
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line.byte 0x00 "ATUCLSR,ATU Cacheline Size Register"
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line.byte 0x01 "ATULT,ATU Latency Timer Register"
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hexmask.byte 0x01 3.--7. 1. " PLT ,Programmable Latency Timer"
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bitfld.byte 0x01 0.--2. " LTG ,Latency Timer Granularity" "0,1,2,3,4,5,6,7"
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group.byte 0x0e++0x01
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line.byte 0x00 "ATUHTR,ATU Header Type Register"
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bitfld.byte 0x00 7. " SF/MF ,Single Function/Multi-Function Device" "Single,Multi"
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hexmask.byte 0x00 00.--06. 1. " HTYP ,PCI Header Type"
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line.byte 0x01 "ATUBISTR,ATU BIST Register"
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bitfld.byte 0x1 7. " BIST ,BIST Capable" "Not capable,Capable"
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bitfld.byte 0x1 6. " START ,Start BIST" "No effect,Started"
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bitfld.byte 0x1 0.--3. " CCODE ,BIST Completion Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x10++0x7
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line.long 0x0 "IABAR0,Inbound ATU Base Address Register 0"
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hexmask.long 0x00 12.--31. 0x1000 " TBA ,Translation Base Address 0"
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bitfld.long 0x00 3. " PREFETCH ,Prefetchable Indicator" "Not prefetchable,Prefetchable"
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bitfld.long 0x00 1.--2. " TYPE ,Type Indicator" "32-bit,Reserved,64-bit,Reserved"
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textline " "
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bitfld.long 0x00 0. " MEMSPACE ,Memory Space Indicator" "0,1"
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line.long 0x4 "IAUBAR0,Inbound ATU Upper Base Address Register 0"
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group.long 0x18++0x7
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line.long 0x0 "IABAR1,Inbound ATU Base Address Register 1"
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hexmask.long 0x00 12.--31. 0x1000 " TBA ,Translation Base Address 1"
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bitfld.long 0x00 3. " PREFETCH ,Prefetchable Indicator" "Not prefetchable,Prefetchable"
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bitfld.long 0x00 1.--2. " TYPE ,Type Indicator" "32-bit,Reserved,64-bit,Reserved"
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textline " "
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bitfld.long 0x00 0. " MEMSPACE ,Memory Space Indicator" "0,1"
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line.long 0x4 "IAUBAR1,Inbound ATU Upper Base Address Register 1"
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group.long 0x20++0x7
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line.long 0x0 "IABAR2,Inbound ATU Base Address Register 2"
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hexmask.long 0x00 12.--31. 0x1000 " TBA ,Translation Base Address 2"
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bitfld.long 0x00 3. " PREFETCH ,Prefetchable Indicator" "Not prefetchable,Prefetchable"
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bitfld.long 0x00 1.--2. " TYPE ,Type Indicator" "32-bit,Reserved,64-bit,Reserved"
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textline " "
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bitfld.long 0x00 0. " MEMSPACE ,Memory Space Indicator" "0,1"
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line.long 0x4 "IAUBAR2,Inbound ATU Upper Base Address Register 2"
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rgroup.word 0x2c++0x3
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line.word 0x0 "ASVIR,ATU Subsystem Vendor ID Register"
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line.word 0x2 "ASIR,ATU Subsystem ID Register"
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group.long 0x30++0x3
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line.long 0x0 "ERBAR,Expansion ROM Base Address Register"
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hexmask.long 0x00 12.--31. 0x1000 " ERBA ,Expansion ROM Base Address"
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bitfld.long 0x00 0. " ADE ,Address Decode Enable" "Disabled,Enabled"
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rgroup.byte 0x34++0x00
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line.byte 0x00 "ATU_Cap_Ptr,ATU Capability Pointer Register"
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group.byte 0x3c++0x0
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line.byte 0x00 "ATUILR,ATU Interrupt Line Register"
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rgroup.byte 0x3d++0x2
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line.byte 0x00 "ATUIPR,ATU Interrupt Pin Register"
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line.byte 0x01 "ATUMGNT,ATU Minimum Grant Register"
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line.byte 0x02 "ATUMLAT,ATU Maximum Latency Register"
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group.long 0x40++0x0b
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line.long 0x00 "IALR0,Inbound ATU Limit Register 0"
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hexmask.long 0x00 12.--31. 0x1000 " LIM0 ,Inbound Translation Limit 0"
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bitfld.long 0x00 0. " MEMWIN0 ,Memory Window 0 Claim Disable" "Enabled,Disabled"
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line.long 0x04 "IATVR0,Inbound ATU Translate Value Register 0"
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hexmask.long 0x04 12.--31. 0x1000 " VAL0 ,Inbound ATU Translation Value 0"
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bitfld.long 0x04 0. " BIGEND ,Big Endian Byte Swap enable" "Disabled,Enabled"
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line.long 0x8 "IAUTVR0,Inbound ATU Upper Translate Value Register 0"
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bitfld.long 0x08 0.--3. " VALU0 ,Inbound Upper ATU Translation Value 0" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F"
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group.long 0x4C++0x0b
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line.long 0x00 "IALR1,Inbound ATU Limit Register 1"
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hexmask.long 0x00 12.--31. 0x1000 " LIM1 ,Inbound Translation Limit 1"
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bitfld.long 0x00 0. " MEMWIN1 ,Memory Window 1 Claim Disable" "Enabled,Disabled"
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line.long 0x04 "IATVR1,Inbound ATU Translate Value Register 1"
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hexmask.long 0x04 12.--31. 0x1000 " VAL1 ,Inbound ATU Translation Value 1"
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bitfld.long 0x04 0. " BIGEND ,Big Endian Byte Swap enable" "Disabled,Enabled"
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line.long 0x8 "IAUTVR1,Inbound ATU Upper Translate Value Register 1"
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bitfld.long 0x08 0.--3. " VALU1 ,Inbound Upper ATU Translation Value 1" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F"
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group.long 0x58++0x0b
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line.long 0x00 "IALR2,Inbound ATU Limit Register 2"
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hexmask.long 0x00 12.--31. 0x1000 " LIM2 ,Inbound Translation Limit 2"
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bitfld.long 0x00 0. " MEMWIN2 ,Memory Window 2 Claim Disable" "Enabled,Disabled"
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line.long 0x04 "IATVR2,Inbound ATU Translate Value Register 2"
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hexmask.long 0x04 12.--31. 0x1000 " VAL2 ,Inbound ATU Translation Value 2"
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bitfld.long 0x04 0. " BIGEND ,Big Endian Byte Swap enable" "Disabled,Enabled"
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line.long 0x8 "IAUTVR2,Inbound ATU Upper Translate Value Register 2"
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bitfld.long 0x08 0.--3. " VALU2 ,Inbound Upper ATU Translation Value 2" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F"
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width 0xd
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group.long 0x64++0x0b
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line.long 0x00 "ERLR,Expansion ROM Limit Register"
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hexmask.long 0x00 12.--31. 0x1000 " LIM ,Expansion ROM Limit"
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line.long 0x04 "ERTVR,Expansion ROM Translate Value Register"
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hexmask.long 0x04 12.--31. 0x1000 " VAL ,Expansion ROM Translation Value"
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bitfld.long 0x04 0. " BIGEND ,Big Endian Byte Swap enable" "Disabled,Enabled"
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line.long 0x8 "ERUTVR,Expansion ROM Upper Translate Value Register"
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bitfld.long 0x08 0.--3. " VALU ,Expansion ROM Upper Translation Value" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F"
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group.long 0x70++0x0f
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line.long 0x00 "ATUCR,ATU Configuration Register"
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bitfld.long 0x00 19. " ADA ,ATU DRC Alias" "Disabled,Enabled"
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bitfld.long 0x00 16. " SMA ,P_SERR# Manual Assertion" "Not asserted,Asserted"
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bitfld.long 0x00 15. " ADTS ,ATU Discard Timer Status" "Not expired,Expired"
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textline " "
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bitfld.long 0x00 09. " SDIE ,SERR# Detected Interrupt Enable" "Disabled,Enabled"
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bitfld.long 0x00 08. " HAE ,Halt ATU On Error Enable" "Disabled,Enabled"
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bitfld.long 0x00 03. " ABIE ,ATU BIST Interrupt Enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 01. " OAE ,Outbound ATU Enable" "Disabled,Enabled"
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line.long 0x04 "PCSR,PCI Configuration and Status Register"
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sif (cpu()=="I81342")||(cpu()=="I81348")
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bitfld.long 0x04 30.--31. " ICPR ,Initiate Core Processor Reset" "No reset,Core0 reset,Core1 reset,Reset"
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else
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bitfld.long 0x04 30.--31. " ICPR ,Initiate Core Processor Reset" "No reset,Core0 reset,Reserved,Reset"
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endif
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bitfld.long 0x04 29. " HS_LSTAT ,Hot-Swap Latch Status" "Low,High"
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bitfld.long 0x04 28. " HS_SM ,Hot-Swap Start up Mode" "Disabled,Enabled"
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textline " "
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bitfld.long 0x04 26.--27. " HS_FREQ ,Hot-Swap Frequency selection" "33/66MHz,66MHz,100MHz,133MHz"
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bitfld.long 0x04 25. " PCIX_EP ,PCIX End Point Strap" "End point,Central resource"
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textline " "
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bitfld.long 0x04 24. " PCIXM1_100 ,PCIX Mode1 - 100MHz limit" "100 MHz,130 MHz"
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bitfld.long 0x04 23. " PCIXM2_100 ,PCIX Mode2 - 100MHz limit (200MHz data rate)" "100 MHz,130 MHz"
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bitfld.long 0x04 22. " EXTARB ,External Arbiter" "Enabled,Disabled"
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textline " "
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bitfld.long 0x04 21. " PBRES ,Central Resource PCI Bus Reset" "No reset,Reset"
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eventfld.long 0x04 20. " UAAER ,Uncorrectable Address or Attribute Error Detected" "No error,Error"
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bitfld.long 0x04 16.--19. " Cap ,PCI-X capability" "Reserved,Reserved,Reserved,Reserved,PCI-X 266 (133),PCI-X 266 (100),PCI-X 266 (66),Reserved,Reserved,Reserved,Reserved,Reserved,PCI-X 133,PCI-X 100,PCI-X 66,PCI"
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textline " "
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bitfld.long 0x04 15. " OTQB ,Outbound Transaction Queue Busy" "Empty,Busy"
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bitfld.long 0x04 14. " ITQB ,Inbound Transaction Queue Busy" "Empty,Busy"
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bitfld.long 0x04 12. " VAL ,Discard Timer Value" "2^15clk,2^10clk"
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textline " "
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bitfld.long 0x04 10. " 66Mhz ,Bus Operating at 66 MHz" "33MHz,66MHz"
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bitfld.long 0x04 09. " PMODE2 ,PCI Bus Mode 2" "Not capable,Capable"
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bitfld.long 0x04 08. " 64B ,PCI Bus 64-Bit Capable" "64bit,32bit"
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textline " "
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eventfld.long 0x04 07. " FTD ,Firmware Timer Disable" "Disabled,Enabled"
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bitfld.long 0x04 02. " CCR ,Configuration Cycle Retry" "Disabled,Enabled"
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sif (cpu()=="I81342")||(cpu()=="I81348")
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bitfld.long 0x04 0.--1. " CPR ,Core Processor Reset" "No reset,Core0 reset,Core1 reset,Reset"
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else
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bitfld.long 0x04 0.--1. " CPR ,Core Processor Reset" "No reset,Core0 reset,Reserved,Reset"
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endif
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line.long 0x08 "ATUISR ,ATU Interrupt Status Register"
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eventfld.long 0x08 18. " PCIER ,PCI Interface Error" "No error,Error"
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eventfld.long 0x08 17. " VPDUPD ,VPD Address Register Updated" "Not updated,Updated"
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eventfld.long 0x08 16. " IBPARERR ,Internal Bus Parity Error Detected" "No error,Error"
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textline " "
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eventfld.long 0x08 15. " ATUWR ,ATU Configuration Write" "Not occurred,Occurred"
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eventfld.long 0x08 14. " CORERR ,Detected Correctable Error" "No error,Error"
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eventfld.long 0x08 13. " ISCEM ,Initiated Split Completion Error Message" "Not occurred,Occurred"
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textline " "
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eventfld.long 0x08 12. " RSCEM ,Received Split Completion Error Message" "Not occurred,Occurred"
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eventfld.long 0x08 11. " PST ,Power State Transition" "Not occurred,Occurred"
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eventfld.long 0x08 10. " PA ,P_SERR# Asserted" "Not asserted,Asserted"
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textline " "
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eventfld.long 0x08 09. " DPE ,Detected Parity Error" "No error,Error"
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eventfld.long 0x08 08. " ABINT ,ATU BIST Interrupt" "No interrupt,Interrupt"
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eventfld.long 0x08 07. " IBMA ,Internal Bus Master Abort" "Not occurred,Occurred"
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textline " "
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eventfld.long 0x08 04. " PD ,P_SERR# Detected" "Not detected,Detected"
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eventfld.long 0x08 03. " PMA ,PCI Master Abort" "Not occurred,Occurred"
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eventfld.long 0x08 02. " PTAM ,PCI Target Abort (master)" "Not occurred,Occurred"
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textline " "
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eventfld.long 0x08 01. " PTAT ,PCI Target Abort (target)" "Not occurred,Occurred"
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eventfld.long 0x08 00. " PMPE ,PCI Master Parity Error" "No error,Error"
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line.long 0x0c "ATUIMR,ATU Interrupt Mask Register"
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bitfld.long 0x0c 15. " PIEM ,PCI Interface Error Mask" "Not masked,Masked"
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bitfld.long 0x0c 14. " VARUM ,VPD Address Register Updated Mask" "Not masked,Masked"
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bitfld.long 0x0c 13. " IBPEDM ,Internal Bus Parity Error Detected Mask" "Not masked,Masked"
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textline " "
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bitfld.long 0x0c 12. " CRWM ,Configuration Register Write Mask" "Not masked,Masked"
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bitfld.long 0x0c 11. " DCEM ,Detected Correctable Error Mask" "Not masked,Masked"
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bitfld.long 0x0c 10. " ISCEMIM ,Initiated Split Completion Error Message Interrupt Mask" "Not masked,Masked"
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textline " "
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bitfld.long 0x0c 09. " RSCEMIM ,Received Split Completion Error Message Interrupt Mask" "Not masked,Masked"
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bitfld.long 0x0c 08. " PSTIM ,Power State Transition Interrupt Mask" "Not masked,Masked"
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bitfld.long 0x0c 07. " ADPEIM ,ATU Detected Parity Error Interrupt Mask" "Not masked,Masked"
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textline " "
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bitfld.long 0x0c 06. " ASAIM ,ATU SERR# Asserted Interrupt Mask" "Not masked,Masked"
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bitfld.long 0x0c 05. " APMAIM ,ATU PCI Master Abort Interrupt Mask" "Not masked,Masked"
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bitfld.long 0x0c 04. " APTAMIM ,ATU PCI Target Abort (Master) Interrupt Mask" "Not masked,Masked"
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textline " "
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bitfld.long 0x0c 03. " APTATIM ,ATU PCI Target Abort (Target) Interrupt Mask" "Not masked,Masked"
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bitfld.long 0x0c 02. " APMPEIM ,ATU PCI Master Parity Error Interrupt Mask" "Not masked,Masked"
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bitfld.long 0x0c 01. " AIESE ,ATU Inbound Error SERR# Enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x0c 00. " AETAE ,ATU ECC Target Abort Enable" "Disabled,Enabled"
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width 0x14
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rgroup.byte 0x90++0x01
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line.byte 0x0 "VPD_Cap_ID,VPD Capability Identifier Register"
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line.byte 0x1 "VPD_Next_Item_Ptr,VPD Next Item Pointer Register"
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group.word 0x92++0x1
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line.word 0x0 "VPDAR,VPD Address Register"
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bitfld.word 0x0 15. " FLAG ,Transfer between VPD Data Register and the storage component flag" "Not completed,Completed"
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hexmask.word 0x0 0.--14. 1. " VA ,VPD Address"
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group.long 0x94++0x3
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line.long 0x0 "VPDDR,VPD Data Register"
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rgroup.byte 0x98++0x0
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line.byte 0x00 "PM_Cap_ID,PM_Capability Identifier Register"
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group.byte 0x99++0x0
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line.byte 0x00 "PPM_Next_Item_Ptr,PM Next Item Pointer Register"
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rgroup.word 0x9a++0x3
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line.word 0x0 "APMCR,ATU Power Management Capabilities Register"
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hexmask.word.byte 0x00 11.--15. 0x1 " PME ,PME_Support"
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bitfld.word 0x00 10. " D2 ,D2_Support" "Not supported,Supported"
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bitfld.word 0x00 9. " D1 ,D1_Support" "Not supported,Supported"
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textline " "
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bitfld.word 0x00 6.--8. " AUXC ,Aux_Current" "000,001,010,011,100,101,110,111"
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bitfld.word 0x00 5. " DSI ,Device Specific Initialization" "Not required,Required"
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bitfld.word 0x00 3. " PMEC ,PME Clock" "Not supported,Supported"
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textline " "
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bitfld.word 0x00 0.--2. " Ver ,Version" "000,001,010,011,100,101,110,111"
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line.word 0x02 "APMCSR,ATU Power Management Control/Status Register"
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bitfld.word 0x02 15. " PMES ,PME_Status" "0,1"
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bitfld.word 0x02 8. " PMEE ,PME_En" "0,1"
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bitfld.word 0x02 0.--1. " PS ,Power State" "D0,Reserved,Reserved,D3hot"
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group.long 0xcc++0x3
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line.long 0x0 "ATUSPR,Scratch Pad Register"
|
|
rgroup.byte 0xd0++0x1
|
|
line.byte 0x0 "PCI-X_Cap_ID,PCI-X_Capability Identifier Register"
|
|
line.byte 0x1 "PCI-X_Next_Item_Ptr,PCI-X Next Item Pointer Register"
|
|
group.word 0xd2++0x1
|
|
line.word 0x0 "PCIXCMD,PCI-X Command Register"
|
|
bitfld.word 0x00 12.--13. " PCLIV ,PCI-X Capabilities List Item Version" "0,1,2,3"
|
|
bitfld.word 0x00 4.--6. " MOST ,Maximum Outstanding Split Transactions" "1,2,3,4,8,12,16,32"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " MMRBC ,Maximum Memory Read Byte Count" "512,1024,2048,4096"
|
|
bitfld.word 0x00 1. " ERO ,Enable Relaxed Ordering" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " UDERE ,Uncorrectable Data Error Recovery Enable" "Disabled,Enabled"
|
|
group.long 0xd4++0x07
|
|
line.long 0x00 "PCIXSR,PCI-X Status Register"
|
|
eventfld.long 0x00 29. " Split-Err ,Received Split Completion Error Message" "Not occurred,Occurred"
|
|
bitfld.long 0x00 26.--28. " DMCRS ,Designed Maximum Cumulative Read Size" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 23.--25. " Max-Split ,Designed Maximum Outstanding Split Transactions" "1,2,3,4,8,12,16,32"
|
|
bitfld.long 0x00 21.--22. " Max-Byte ,Designed Maximum Memory Read Byte Count" "512,1024,2048,4096"
|
|
textline " "
|
|
bitfld.long 0x00 20. " Complex ,Complex Device" "Not complex,Complex"
|
|
eventfld.long 0x00 19. " Unexp-Split ,Unexpected Split Completion" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 18. " Split-Disc ,Split Completion Discarded" "Not occurred,Occurred"
|
|
bitfld.long 0x00 17. " 133MHz ,133 MHz Device" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 16. " 32BITPCI# ,Add-in card configuration" "32-Bit,64-Bit"
|
|
hexmask.long 0x00 8.--15. 0x01 " Bus ,Bus Number"
|
|
textline " "
|
|
bitfld.long 0x00 3.--7. " Dev ,Device Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " Func ,Function Number" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "ECCCSR,ECC Control and Status Register"
|
|
bitfld.long 0x04 31. " ECC ,ECC Mode" "Parity,ECC"
|
|
bitfld.long 0x04 30. " SBEC ,Disable Single-Bit-Error Correction" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 28. " CUE ,ECC Control Update Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24.--27. " UPATER ,Error Upper Attributes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 20.--23. " SECOER ,Error Second Command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. " FICOER ,Error First (or only) Command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 15. " SYN_E0 ,Syndrome E0 Error" "No error,Error"
|
|
bitfld.long 0x04 14. " SYN_E1 ,Syndrome E1 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 13. " SYN_E2 ,Syndrome E2 Error" "No error,Error"
|
|
bitfld.long 0x04 12. " SYN_E3 ,Syndrome E3 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 11. " SYN_E4 ,Syndrome E4 Error" "No error,Error"
|
|
bitfld.long 0x04 10. " SYN_E5 ,Syndrome E5 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 9. " SYN_E6 ,Syndrome E6 Error" "No error,Error"
|
|
bitfld.long 0x04 8. " SYN_E7 ,Syndrome E7 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ERCOR ,ECC Error Corrected" "Not corrected,Corrected"
|
|
bitfld.long 0x04 4.--6. " PHASE ,ECC Error Phase" "No Error,F addr 32 bits,S addr 32 bits,Attribute phase,32-bit data phase,64-bit data phase,Reserved,Reserved"
|
|
textline " "
|
|
bitfld.long 0x04 3. " ADUNER ,Additional Uncorrectable ECC Error" "No error,Error"
|
|
bitfld.long 0x04 2. " ADCOER ,Additional Correctable ECC Error" "No error,Error"
|
|
rgroup.long 0xdc++0xb
|
|
line.long 0x0 "ECCFAR,ECC First Address Register"
|
|
line.long 0x4 "ECCSAR,ECC Second Address Register"
|
|
line.long 0x8 "ECCAR,ECC Attribute Register"
|
|
rgroup.byte 0xe8++0x0
|
|
line.byte 0x0 "HS_CAPID,Hot-Swap Cap ID"
|
|
group.byte 0xe9++0x1
|
|
line.byte 0x0 "HS_NXTP,Next Item Pointer"
|
|
line.byte 0x1 "HS_CNTRL,Hot-Swap Control/Status Register"
|
|
eventfld.byte 0x1 7. " INS ,Freshly INSerted board" "Not inserted,Inserted"
|
|
eventfld.byte 0x1 6. " EXT ,Pending EXTraction of board" "Not pending,Pending"
|
|
bitfld.byte 0x1 4.--5. " PI ,Programming Interface" "0,1,2,3"
|
|
textline " "
|
|
bitfld.byte 0x1 3. " LOO ,LED On/Off (LOO) Control" "Off,On"
|
|
bitfld.byte 0x1 2. " PIE ,Pending Insertion/Extraction" "Not pending,Pending"
|
|
bitfld.byte 0x1 1. " EIM ,ENUM# Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x1 0. " DHA ,Device Hiding Armed" "Not armed,Armed"
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IABAR3,Inbound ATU Base Address Register 3"
|
|
hexmask.long 0x00 12.--31. 0x1000 " Addr ,Translation Base Address 0"
|
|
bitfld.long 0x00 3. " Preft ,Prefetchable Indicator" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x00 1.--2. " Type ,Type Indicator" "32-bit,Reserved,64-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 0. " Mem ,Memory Space Indicator" "Memory,I/O space"
|
|
line.long 0x04 "IAUBAR3,Inbound ATU Upper Base Address Register 3"
|
|
line.long 0x08 "IALR3,Inbound ATU Limit Register 3"
|
|
hexmask.long 0x08 12.--31. 0x1000 " LIM3 ,Inbound Translation Limit 3"
|
|
line.long 0x0c "IATVR3,Inbound ATU Translate Value Register 3"
|
|
hexmask.long 0x0c 12.--31. 0x1000 " VAL3 ,Inbound ATU Translation Value 3"
|
|
bitfld.long 0x0c 0. " BIGEND ,Big Endian Byte Swap enable" "Disabled,Enabled"
|
|
line.long 0x10 "IAUTVR3,Inbound ATU Upper Translate Value Register 3"
|
|
bitfld.long 0x10 0.--3. " VALU3 ,Inbound Upper ATU Translation Value 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x300++0x27
|
|
line.long 0x0 "OIOBAR,Outbound I/O Base Address Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " Addr ,Outbound I/O Base Address"
|
|
bitfld.long 0x00 0.--2. " OIOFNM ,Outbound I/O Function Number Mapping" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "OIOWTVR,Outbound I/O Window Translate Value Register"
|
|
hexmask.long 0x04 16.--31. 0x10000 " OIOWTV ,Outbound I/O Window Translate Value"
|
|
bitfld.long 0x04 0. " BIGEND ,Big Endian Byte Swap enable" "Disabled,Enabled"
|
|
line.long 0x8 "OUMBAR0,Outbound Upper Memory Window Base Address Register 0"
|
|
bitfld.long 0x8 31. " OW0E ,Outbound Window 0 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 28.--30. " OW0FNM ,Outbound Window 0 Function Number Mapping" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 27. " BEBS ,Big Endian Byte Swap enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 0.--3. " OUMWBA0 ,Outbound Upper Memory Window Base Address 0" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F"
|
|
line.long 0xC "OUMWTVR0,Outbound Upper 32-bit Memory Window Translate Value Register 0"
|
|
line.long 0x10 "OUMBAR1,Outbound Upper Memory Window Base Address Register 1"
|
|
bitfld.long 0x10 31. " OW1E ,Outbound Window 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 28.--30. " OW1FNM ,Outbound Window 1 Function Number Mapping" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 27. " BEBS ,Big Endian Byte Swap enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0.--3. " OUMWBA1 ,Outbound Upper Memory Window Base Address 1" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F"
|
|
line.long 0x14 "OUMWTVR1,Outbound Upper 32-bit Memory Window Translate Value Register 1"
|
|
line.long 0x18 "OUMBAR2,Outbound Upper Memory Window Base Address Register 2"
|
|
bitfld.long 0x18 31. " OW2E ,Outbound Window 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 28.--30. " OW2FNM ,Outbound Window 2 Function Number Mapping" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 27. " BEBS ,Big Endian Byte Swap enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 0.--3. " OUMWBA2 ,Outbound Upper Memory Window Base Address 2" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F"
|
|
line.long 0x1C "OUMWTVR2,Outbound Upper 32-bit Memory Window Translate Value Register 2"
|
|
line.long 0x20 "OUMBAR3,Outbound Upper Memory Window Base Address Register 3"
|
|
bitfld.long 0x20 31. " OW3E ,Outbound Window 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 28.--30. " OW3FNM ,Outbound Window 3 Function Number Mapping" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x20 27. " BEBS ,Big Endian Byte Swap enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 0.--3. " OUMWBA3 ,Outbound Upper Memory Window Base Address 3" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F"
|
|
line.long 0x24 "OUMWTVR3,Outbound Upper 32-bit Memory Window Translate Value Register 3"
|
|
rgroup.long 0x330++0x7
|
|
line.long 0x0 "OCCAR,Outbound Configuration Cycle Address Register"
|
|
line.long 0x4 "OCCDR,Outbound Configuration Cycle Data Register"
|
|
group.long 0x338++0x3
|
|
line.long 0x0 "OCCFN,Outbound Configuration Cycle Function Number Register"
|
|
bitfld.long 0x00 0.--2. " CCFN ,Configuration Cycle Function Number" "0,1,2,3,4,5,6,7"
|
|
group.long 0x380++0x3
|
|
line.long 0x0 "PIECSR,PCI Interface Error Control and Status Register"
|
|
bitfld.long 0x0 13.--16. " ERRCOM ,Error Command" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F"
|
|
bitfld.long 0x00 9.--12. " ERRTYPE ,Error Type" "Address Parity,Data Parity,Master Abort,Target Abort,Split Completion,Unexp. Split Completion,Split Completion Disc.,Internal Bus Data Parity,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " IID ,Initiator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--4. " PFN ,PCI Function Number" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
eventfld.long 0x00 1. " MPIED ,Multiple PCI Interface Errors Detected" "No error,Error"
|
|
eventfld.long 0x00 0. " PIED ,PCI Interface Error Detected" "No error,Error"
|
|
rgroup.long 0x384++0xb
|
|
line.long 0x0 "PCIEAR,PCI Interface Error Address Register"
|
|
line.long 0x4 "PCIEUAR,PCI Interface Error Upper Address Register"
|
|
line.long 0x8 "PCIECAR,PCI Interface Error Context Address Register"
|
|
bitfld.long 0x08 29.--30. " DMACH ,DMA Channel Number" "0,1,2,3"
|
|
hexmask.long 0x08 0.--28. 1. " ADA ,ADMA Descriptor Address Bits 30:5"
|
|
group.word 0x394++0x3
|
|
line.word 0x0 "IACR,Internal Arbiter Control Register"
|
|
sif (cpu()=="I81342")||(cpu()=="I81341")
|
|
bitfld.word 0x0 8. " BPC ,Bus Parking Control" "Last PCI,81341/81342"
|
|
elif (cpu()=="I81348")
|
|
bitfld.word 0x0 8. " BPC ,Bus Parking Control" "Last PCI,81348"
|
|
endif
|
|
bitfld.word 0x0 6. " ARA ,ATU Ring Allocation" "Low,High"
|
|
bitfld.word 0x0 3. " PMPRA3 ,PCI Master Priority Ring Allocation REQ#[3]" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x0 2. " PMPRA2 ,PCI Master Priority Ring Allocation REQ#[2]" "Low,High"
|
|
bitfld.word 0x0 1. " PMPRA1 ,PCI Master Priority Ring Allocation REQ#[1]" "Low,High"
|
|
bitfld.word 0x0 0. " PMPRA0 ,PCI Master Priority Ring Allocation REQ#[0]" "Low,High"
|
|
rgroup.byte 0x398++0x0
|
|
line.byte 0x0 "MTT,Multi-Transaction Timer"
|
|
bitfld.byte 0x0 3.--7. " MTC ,Timer Count Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x2100++0xf
|
|
line.long 0x0 "PRCR,PCIX RCOMP Control Register"
|
|
bitfld.long 0x00 11. " SLEW ,Slew rate manual override values" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--10. " PCIX ,Reference select for PCIX CAP pad" "Nominal,-5%,+5%,Reserved"
|
|
bitfld.long 0x00 7.--8. " ORDRVSTR ,Drive strength select for ODT RCOMP pad" "103 Ohms,110 Ohms,120 Ohms,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " RDRVSTR33 ,Drive strength select for RCOMP pad dedicated 3.3V supply voltage" "18 Ohms,20.1 Ohms,22 Ohms,24.1 Ohms,26.1 Ohms,Reserved,Reserved,Reserved"
|
|
bitfld.long 0x00 1.--3. " RDRVSTR15 ,Drive strength select for RCOMP pad dedicated 1.5V supply voltage" "18 Ohms,20.1 Ohms,22 Ohms,24.1 Ohms,26.1 Ohms,Reserved,Reserved,Reserved"
|
|
bitfld.long 0x00 0. " RCOMPEN ,RCOMP pads enable" "Disabled,Enabled"
|
|
line.long 0x4 "PPODSMOVR,PCIX Pad ODT Drive Strength Manual Override Values Registers"
|
|
hexmask.long.byte 0x04 8.--13. 1. " NODTDRVSTR ,N-ODT drive strength manual override values for PCIX pad"
|
|
hexmask.long.byte 0x04 0.--5. 1. " PODTDRVSTR ,P-ODT drive strength manual override values for PCIX pad"
|
|
line.long 0x8 "PPDSMOVR3.3_1.5,PCIX PAD DRIVE STRENGTH Manual Override Values Register (3.3V/1.5V Switch Supply Voltage)"
|
|
bitfld.long 0x08 24.--27. " NSLEW ,N-slew rate manual override values for PCIX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 16.--19. " PSLEW ,P-slew rate manual override values for PCIX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x08 8.--13. 1. " DRVSTRN ,N-drive strength manual override values for PCIX pad"
|
|
hexmask.long.byte 0x08 0.--5. 1. " DRVSTRP ,P-drive strength manual override values for PCIX pad"
|
|
line.long 0xc "PPDSMOVR3.3,PCIX PAD DRIVE STRENGTH Manual Override Values Register (3.3 V Dedicated Supply Voltage)"
|
|
bitfld.long 0x0c 24.--27. " NSLEW ,N-slew rate manual override values for PCIX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0c 16.--19. " PSLEW ,P-slew rate manual override values for PCIX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x0c 8.--13. 1. " DRVSTRN ,N-drive strength manual override values for PCIX pad"
|
|
hexmask.long.byte 0x0c 0.--5. 1. " DRVSTRP ,P-drive strength manual override values for PCIX pad"
|
|
width 0xb
|
|
tree.end
|
|
tree "PCI-Express"
|
|
; if (((data.long(asd:(0x0:0xFFD80000+0x2188)))&0x8000)==0x8000)
|
|
; ESSTSR0 -> INTERFACE_SEL_PCIX == 1
|
|
base asd:(0x0:0xFFD80000+0x48000)
|
|
; else
|
|
; base asd:(0x0:0xFFD80000+0x4D000)
|
|
; endif
|
|
width 0xd
|
|
rgroup.word 0x0++0x3
|
|
line.word 0x00 "ATUVID,ATU Vendor ID Register"
|
|
line.word 0x02 "ATUDID,ATU Device ID Register"
|
|
group.word 0x4++0x3
|
|
line.word 0x0 "ATUCMD,ATU Command Register"
|
|
bitfld.word 0x0 10. " INTDIS ,Interrupt Disable" "Enabled,Disabled"
|
|
bitfld.word 0x0 9. " FBTBE ,Fast Back to Back Enable" "Disabled,Enabled"
|
|
bitfld.word 0x0 8. " SERR ,SERR Enable" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.word 0x0 6. " PER ,Parity Error Response" "Disabled,Enabled"
|
|
bitfld.word 0x0 5. " VGA ,VGA Palette Snoop Enable" "Disabled,Enabled"
|
|
bitfld.word 0x0 4. " MWI ,Memory Write and Invalidate Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x0 2. " BME ,Bus Master Enable" "Disabled,Enabled"
|
|
bitfld.word 0x0 1. " MEMORY ,Memory Enable" "Disabled,Enabled"
|
|
bitfld.word 0x0 0. " IOSPACE ,I/O Space Enable" "Disabled,Enabled"
|
|
line.word 0x02 "ATUSR,ATU Status Register"
|
|
eventfld.word 0x2 15. " PARERR ,Detected Parity Error" "No error,Error"
|
|
eventfld.word 0x2 14. " SERR ,SERR asserted" "Not asserted,Asserted"
|
|
eventfld.word 0x2 13. " MA ,Master Abort" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.word 0x2 12. " TAM ,Target Abort (master)" "Disabled,Enabled"
|
|
eventfld.word 0x2 11. " TAT ,Target Abort (target)" "Disabled,Enabled"
|
|
bitfld.word 0x2 9.--10. " DEVTIM ,DEVSEL# Timing" "Fast,Medium,Slow,Reserved"
|
|
textline " "
|
|
eventfld.word 0x2 8. " MPERR ,Master Parity Error" "No error,Error"
|
|
bitfld.word 0x2 7. " FB2B ,Fast Back-to-Back" "Disabled,Enabled"
|
|
bitfld.word 0x2 5. " 66MHZ ,66 MHz Supported" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.word 0x2 4. " CAP ,Capabilities" "Normal,Extended"
|
|
bitfld.word 0x2 3. " INTERRUPT ,Interrupt Status" "No interrupt,Interrupt"
|
|
rgroup.byte 0x08++0x00
|
|
line.byte 0x00 "ATURID,ATU Revision ID Register"
|
|
rgroup.byte 0x09++0x03
|
|
line.tbyte 0x00 "ATUCCR,ATU Class Code Register"
|
|
hexmask.tbyte.byte 0x0 16.--23. 1. " BC ,Base Class - Memory Controller"
|
|
hexmask.tbyte.byte 0x0 08.--15. 1. " SC ,Sub Class - Other Memory Controller"
|
|
hexmask.tbyte.byte 0x0 00.--07. 1. " PI ,Programming Interface - None defined"
|
|
group.byte 0x0c++0x01
|
|
line.byte 0x00 "ATUCLSR,ATU Cacheline Size Register"
|
|
line.byte 0x01 "ATULT,ATU Latency Timer Register"
|
|
hexmask.byte 0x01 3.--7. 1. " PLT ,Programmable Latency Timer"
|
|
bitfld.byte 0x01 0.--2. " LTG ,Latency Timer Granularity" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x0e++0x01
|
|
line.byte 0x00 "ATUHTR,ATU Header Type Register"
|
|
bitfld.byte 0x00 7. " SF/MF ,Single Function/Multi-Function Device" "Single,Multi"
|
|
hexmask.byte 0x00 00.--06. 1. " HTYP ,PCI Header Type"
|
|
line.byte 0x01 "ATUBISTR,ATU BIST Register"
|
|
bitfld.byte 0x1 7. " BIST ,BIST Capable" "Not capable,Capable"
|
|
bitfld.byte 0x1 6. " START ,Start BIST" "No effect,Started"
|
|
bitfld.byte 0x1 0.--3. " CCODE ,BIST Completion Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "IABAR0,Inbound ATU Base Address Register 0"
|
|
hexmask.long 0x00 12.--31. 0x1000 " TBA ,Translation Base Address 0"
|
|
bitfld.long 0x00 3. " PREFETCH ,Prefetchable Indicator" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x00 1.--2. " TYPE ,Type Indicator" "32-bit,Reserved,64-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MEMSPACE ,Memory Space Indicator" "0,1"
|
|
line.long 0x4 "IAUBAR0,Inbound ATU Upper Base Address Register 0"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "IABAR1,Inbound ATU Base Address Register 1"
|
|
hexmask.long 0x00 12.--31. 0x1000 " TBA ,Translation Base Address 1"
|
|
bitfld.long 0x00 3. " PREFETCH ,Prefetchable Indicator" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x00 1.--2. " TYPE ,Type Indicator" "32-bit,Reserved,64-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MEMSPACE ,Memory Space Indicator" "0,1"
|
|
line.long 0x4 "IAUBAR1,Inbound ATU Upper Base Address Register 1"
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "IABAR2,Inbound ATU Base Address Register 2"
|
|
hexmask.long 0x00 12.--31. 0x1000 " TBA ,Translation Base Address 2"
|
|
bitfld.long 0x00 3. " PREFETCH ,Prefetchable Indicator" "Not prefetchable,Prefetchable"
|
|
bitfld.long 0x00 1.--2. " TYPE ,Type Indicator" "32-bit,Reserved,64-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MEMSPACE ,Memory Space Indicator" "0,1"
|
|
line.long 0x4 "IAUBAR2,Inbound ATU Upper Base Address Register 2"
|
|
rgroup.word 0x2c++0x3
|
|
line.word 0x0 "ASVIR,ATU Subsystem Vendor ID Register"
|
|
line.word 0x2 "ASIR,ATU Subsystem ID Register"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "ERBAR,Expansion ROM Base Address Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " ERBA ,Expansion ROM Base Address"
|
|
bitfld.long 0x00 0. " ADE ,Address Decode Enable" "Disabled,Enabled"
|
|
rgroup.byte 0x34++0x00
|
|
line.byte 0x00 "ATU_Cap_Ptr,ATU Capability Pointer Register"
|
|
group.byte 0x3c++0x0
|
|
line.byte 0x00 "ATUILR,ATU Interrupt Line Register"
|
|
rgroup.byte 0x3d++0x2
|
|
line.byte 0x00 "ATUIPR,ATU Interrupt Pin Register"
|
|
line.byte 0x01 "ATUMGNT,ATU Minimum Grant Register"
|
|
line.byte 0x02 "ATUMLAT,ATU Maximum Latency Register"
|
|
group.long 0x40++0x0b
|
|
line.long 0x00 "IALR0,Inbound ATU Limit Register 0"
|
|
hexmask.long 0x00 12.--31. 0x1000 " LIM0 ,Inbound Translation Limit 0"
|
|
bitfld.long 0x00 0. " MEMWIN0 ,Memory Window 0 Claim Disable" "Enabled,Disabled"
|
|
line.long 0x04 "IATVR0,Inbound ATU Translate Value Register 0"
|
|
hexmask.long 0x04 12.--31. 0x1000 " VAL0 ,Inbound ATU Translation Value 0"
|
|
bitfld.long 0x04 0. " BIGEND ,Big Endian Byte Swap enable" "Disabled,Enabled"
|
|
line.long 0x8 "IAUTVR0,Inbound ATU Upper Translate Value Register 0"
|
|
bitfld.long 0x08 0.--3. " VALU0 ,Inbound Upper ATU Translation Value 0" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F"
|
|
group.long 0x4C++0x0b
|
|
line.long 0x00 "IALR1,Inbound ATU Limit Register 1"
|
|
hexmask.long 0x00 12.--31. 0x1000 " LIM1 ,Inbound Translation Limit 1"
|
|
bitfld.long 0x00 0. " MEMWIN1 ,Memory Window 1 Claim Disable" "Enabled,Disabled"
|
|
line.long 0x04 "IATVR1,Inbound ATU Translate Value Register 1"
|
|
hexmask.long 0x04 12.--31. 0x1000 " VAL1 ,Inbound ATU Translation Value 1"
|
|
bitfld.long 0x04 0. " BIGEND ,Big Endian Byte Swap enable" "Disabled,Enabled"
|
|
line.long 0x8 "IAUTVR1,Inbound ATU Upper Translate Value Register 1"
|
|
bitfld.long 0x08 0.--3. " VALU1 ,Inbound Upper ATU Translation Value 1" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F"
|
|
group.long 0x58++0x0b
|
|
line.long 0x00 "IALR2,Inbound ATU Limit Register 2"
|
|
hexmask.long 0x00 12.--31. 0x1000 " LIM2 ,Inbound Translation Limit 2"
|
|
bitfld.long 0x00 0. " MEMWIN2 ,Memory Window 2 Claim Disable" "Enabled,Disabled"
|
|
line.long 0x04 "IATVR2,Inbound ATU Translate Value Register 2"
|
|
hexmask.long 0x04 12.--31. 0x1000 " VAL2 ,Inbound ATU Translation Value 2"
|
|
bitfld.long 0x04 0. " BIGEND ,Big Endian Byte Swap enable" "Disabled,Enabled"
|
|
line.long 0x8 "IAUTVR2,Inbound ATU Upper Translate Value Register 2"
|
|
bitfld.long 0x08 0.--3. " VALU2 ,Inbound Upper ATU Translation Value 2" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F"
|
|
width 0xd
|
|
group.long 0x64++0x0b
|
|
line.long 0x00 "ERLR,Expansion ROM Limit Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " LIM ,Expansion ROM Limit"
|
|
line.long 0x04 "ERTVR,Expansion ROM Translate Value Register"
|
|
hexmask.long 0x04 12.--31. 0x1000 " VAL ,Expansion ROM Translation Value"
|
|
bitfld.long 0x04 0. " BIGEND ,Big Endian Byte Swap enable" "Disabled,Enabled"
|
|
line.long 0x8 "ERUTVR,Expansion ROM Upper Translate Value Register"
|
|
bitfld.long 0x08 0.--3. " VALU ,Expansion ROM Upper Translation Value" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F"
|
|
group.long 0x70++0x17
|
|
line.long 0x00 "ATUCR,ATU Configuration Register"
|
|
bitfld.long 0x00 30. " CTD ,Completion Timeout Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 08. " HAE ,Halt On Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 06. " IVM ,Drop Subsequent Inbound Vendor Defined Messages" "Not dropped,Dropped"
|
|
textline " "
|
|
bitfld.long 0x00 05. " OCS ,Outbound Completion Size" "Max,128 Bytes"
|
|
bitfld.long 0x00 04. " IMCS ,Inbound Minimum Completion Size" "64 Bytes,Entire"
|
|
bitfld.long 0x00 03. " ABIE ,ATU BIST Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 01. " OAE ,Outbound ATU Enable" "Disabled,Enabled"
|
|
line.long 0x04 "PCSR,PCI Configuration and Status Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " PEBN ,PCI Express Bus Number"
|
|
bitfld.long 0x04 19.--23. " PEDN ,PCI Express Device Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 16.--18. " PEFN ,PCI Express Function Number" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 15. " OTQB ,Outbound Transaction Queue Busy" "Empty,Busy"
|
|
bitfld.long 0x04 14. " ITQB ,Inbound Transaction Queue Busy" "Empty,Busy"
|
|
bitfld.long 0x04 13. " RC ,PCI Express Root Complex mode" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " LLRB ,Link Layer Retry Buffer Busy" "Empty,Busy"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.long 0x04 08.--9. " CORES ,Core reset" "No reset,Core0 reset,Core1 reset,Reset"
|
|
else
|
|
bitfld.long 0x04 08.--9. " CORES ,Core reset" "No reset,Core0 reset,Reserved,Reset"
|
|
endif
|
|
eventfld.long 0x04 07. " FTD ,Firmware Timer Disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 02. " CRR ,Configuration Request Retry" "Disabled,Enabled"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.long 0x04 0.--1. " CPR ,Core Processor Reset" "No reset,Core0 reset,Core1 reset,Reset"
|
|
else
|
|
bitfld.long 0x04 0.--1. " CPR ,Core Processor Reset" "No reset,Core0 reset,Reserved,Reset"
|
|
endif
|
|
line.long 0x08 "ATUISR ,ATU Interrupt Status Register"
|
|
eventfld.long 0x08 28. " SPMR ,Slot Power Message Received Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 27. " PMEINT ,PME Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 26. " HPMR ,Hot-Plug Message Received Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 25. " IVM ,Inbound Vendor Message Received Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 24. " ATUBI ,ATU BIST Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 18. " ACW ,ATU Configuration Write Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 17. " VPDUPD ,VPD Address Register Updated Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 16. " PST ,Power State Transition Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 13. " HOEI ,Halt on Error Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 12. " RSE ,Root System Error Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 11. " REM ,Root Error Message Received Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 10. " PIE ,PCI Interface Error Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 09. " CEMT ,Correctable Error Message Transmitted Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 08. " UEMT ,Uncorrectable Error Message Transmitted Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 07. " CRS ,Received Configuration Retry Status Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 06. " LD ,Link Down Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 05. " PD ,Internal Bus Master Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 04. " PMA ,Parity Error Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 03. " RMA ,Received Master Abort Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 02. " STA ,Signaled Target Abort Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 01. " RTA ,Received Target Abort Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 00. " MDPE ,Master Data Parity Error Interrupt" "No interrupt,Interrupt"
|
|
line.long 0x0c "ATUIMR,ATU Interrupt Mask Register"
|
|
bitfld.long 0x0c 28. " SPMR ,Slot Power Message Received Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x0c 26. " HPMR ,Hot-Plug Message Received Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x0c 25. " IVM ,Inbound Vendor Message Received Interrupt Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0c 18. " ACW ,ATU Configuration Write Mask" "Not masked,Masked"
|
|
bitfld.long 0x0c 17. " VPDUPD ,VPD Address Register Updated Mask" "Not masked,Masked"
|
|
bitfld.long 0x0c 16. " PST ,Power State Transition Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " HOEI ,Halt on Error Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x0c 12. " RSE ,Root System Error Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x0c 09. " CEMT ,Correctable Error Logged Interrupt Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0c 08. " UEMT ,Uncorrectable Error Logged Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x0c 07. " CRS ,Received Configuration Retry Status Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x0c 06. " LD ,Link Down Interrupt Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0c 05. " PD ,Internal Bus Master Abort Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x0c 04. " PMA ,Data Parity Error Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x0c 03. " RMA ,Received Master Abort Interrupt Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0c 02. " STA ,Signaled Target Abort Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x0c 01. " RTA ,Received Target Abort Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x0c 00. " MDPE ,Master Data Parity Error Interrupt Mask" "Not masked,Masked"
|
|
line.long 0x10 "PEMCSR,PCI Express Message Control and Status Register"
|
|
bitfld.long 0x10 30.--31. " AIS ,Attention Indicator Status" "Reserved,On,Blink,Off"
|
|
bitfld.long 0x10 28.--29. " PIS ,Power Indicator Status" "Reserved,On,Blink,Off"
|
|
textline " "
|
|
bitfld.long 0x10 15. " ABPS ,Attention Button Pressed Control message generation" "Not generated,Generated"
|
|
bitfld.long 0x10 14. " IVDT0UR ,Inbound Vendor_Defined Type 0 Unsupported Request response" "Not generated,Generated"
|
|
line.long 0x14 "PELCSR,PCI Express Link Control and Status Register"
|
|
bitfld.long 0x14 5. " SDS ,Scrambling Disabled Status" "Active,Disabled"
|
|
bitfld.long 0x14 4. " LS ,Loopback Status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 3. " DS ,Disable Scrambling" "Active,Disabled"
|
|
bitfld.long 0x14 2. " LB ,Loopback" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 0. " HRES ,Hot Reset" "Disabled,Enabled"
|
|
width 0x14
|
|
rgroup.byte 0x90++0x01
|
|
line.byte 0x0 "VPD_Cap_ID,VPD Capability Identifier Register"
|
|
line.byte 0x1 "VPD_Next_Item_Ptr,VPD Next Item Pointer Register"
|
|
group.word 0x92++0x1
|
|
line.word 0x0 "VPDAR,VPD Address Register"
|
|
bitfld.word 0x0 15. " FLAG ,Transfer between VPD Data Register and the storage component flag" "Not completed,Completed"
|
|
hexmask.word 0x0 0.--14. 1. " VA ,VPD Address"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "VPDDR,VPD Data Register"
|
|
rgroup.byte 0x98++0x0
|
|
line.byte 0x00 "PM_Cap_ID,PM_Capability Identifier Register"
|
|
group.byte 0x99++0x0
|
|
line.byte 0x00 "PPM_Next_Item_Ptr,PM Next Item Pointer Register"
|
|
width 14.
|
|
rgroup.word 0x9a++0x3
|
|
line.word 0x0 "APMCR,ATU Power Management Capabilities Register"
|
|
hexmask.word.byte 0x00 11.--15. 0x1 " PME ,PME_Support"
|
|
bitfld.word 0x00 10. " D2 ,D2_Support" "Not supported,Supported"
|
|
bitfld.word 0x00 9. " D1 ,D1_Support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.word 0x00 6.--8. " AUXC ,Aux_Current" "000,001,010,011,100,101,110,111"
|
|
bitfld.word 0x00 5. " DSI ,Device Specific Initialization" "Not required,Required"
|
|
bitfld.word 0x00 3. " PMEC ,PME Clock" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " Ver ,Version" "000,001,010,011,100,101,110,111"
|
|
line.word 0x02 "APMCSR,ATU Power Management Control/Status Register"
|
|
bitfld.word 0x02 15. " PMES ,PME_Status" "0,1"
|
|
bitfld.word 0x02 8. " PMEE ,PME_En" "0,1"
|
|
sif (cpu()=="I81341"||cpu()=="I81342"||cpu()=="I81348")
|
|
bitfld.word 0x02 0.--1. " PS ,Power State" "D0,D1,Reserved,D3hot"
|
|
else
|
|
bitfld.word 0x02 0.--1. " PS ,Power State" "D0,Reserved,Reserved,D3hot"
|
|
endif
|
|
group.long 0xcc++0x3
|
|
line.long 0x0 "ATUSPR,Scratch Pad Register"
|
|
rgroup.byte 0xd0++0x1
|
|
line.byte 0x0 "PCIE_CAPID,PCI-X_Capability Identifier Register"
|
|
line.byte 0x1 "PCIE_NXTP,PCI-X Next Item Pointer Register"
|
|
rgroup.word 0xd2++0x1
|
|
line.word 0x0 "PCIE_CAP,PCI Express Capabilities Register"
|
|
bitfld.word 0x00 9.--13. " IMN ,Interrupt Message Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 8. " SLOT ,Slot Implemented" "Disconnected,Connected"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " DEVPORT ,Device/Port Type" "Endpoint,Reserved,Reserved,Reserved,Root Complex,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
|
|
bitfld.word 0x00 0.--3. " CAP ,Capability Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xd4++0x03
|
|
line.long 0x00 "PCIE_DCAP,PCI Express Device Capabilities Register"
|
|
bitfld.long 0x00 26.--27. " SPLS ,Captured Slot Power Limit Scale" "0,1,2,3"
|
|
hexmask.long.byte 0x00 18.--25. 1. " SPLV ,Captured Slot Power Limit Value"
|
|
bitfld.long 0x00 15. " RBER ,Role-Based Error Reporting" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 14. " PIPD ,Power Indicator Present on Device" "Not implemented,Implemented"
|
|
bitfld.long 0x00 13. " AIPD ,Attention Indicator Preset on Device" "Not implemented,Implemented"
|
|
bitfld.long 0x00 12. " ABPD ,Attention Button Present on Device" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " EL1AL ,Endpoint L1 Acceptable Latency" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--8. " EL0AL ,Endpoint L0 Acceptable Latency" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5. " ETFS ,Extended Tag Field Supported" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " PHF ,Phantom Functions Supported" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. " MPS ,Max Payload Size Supported" "000,001,512 Bytes,011,100,101,110,111"
|
|
group.word 0xd8++0x3
|
|
line.word 0x00 "PE_DCTL,PCI Express Device Control Register"
|
|
bitfld.word 0x00 12.--14. " MAXRRS ,Max_Read_Request_Size" "128 Bytes,256 Bytes,512 Bytes,1024 Bytes,2048 Bytes,4096 Bytes,Reserved/4096,Reserved/4096"
|
|
bitfld.word 0x00 11. " NS ,Enable No Snoop" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " APPM ,Aux Power PM Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " PHF ,Phantom Functions Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " ETF ,Extended Tag Field Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5.--7. " MAXPS ,Max_Payload_Size" "128 Bytes,256 Bytes,512 Bytes,1024 Bytes,2048 Bytes,4096 Bytes,Reserved/128,Reserved/128"
|
|
textline " "
|
|
bitfld.word 0x00 4. " RO ,Enable Relaxed Ordering" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " URR ,Unsupported Request Reporting Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " FER ,Fatal Error Reporting Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " NFER ,Non-Fatal Error Reporting Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CER ,Correctable Error Reporting Enable" "Disabled,Enabled"
|
|
line.word 0x2 "PE_DSTS,PCI Express Device Status Register"
|
|
bitfld.word 0x2 5. " TP ,Transactions Pending" "Not pending,Pending"
|
|
bitfld.word 0x2 4. " AP ,AUX Power Detected" "Not detected,Detected"
|
|
eventfld.word 0x2 3. " UR ,Unsupported Request Detected" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.word 0x2 2. " FE ,Fatal Error Detected" "Not detected,Detected"
|
|
eventfld.word 0x2 1. " NFE ,Non-Fatal Error Detected" "Not detected,Detected"
|
|
eventfld.word 0x2 0. " CE ,Correctable Error Detected" "Not detected,Detected"
|
|
group.long 0xdc++0x3
|
|
line.long 0x0 "PE_LCAP,PCI Express Link Capabilities Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PORT ,Port # - PCI Express port number"
|
|
bitfld.long 0x00 15.--17. " L1EL ,L1 Exit Latency" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " L0EL ,L0 Exit Latency" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " ASLPM ,Active State Link PM Support" "0,1,2,3"
|
|
bitfld.long 0x00 4.--9. " MAXLW ,Maximum Link Width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
bitfld.long 0x00 0.--3. " MAXLS ,Maximum Link Speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xe0++0x3
|
|
line.word 0x0 "PE_LCTL,PCI Express Link Control Register"
|
|
bitfld.word 0x00 7. " EXS ,Extended Synch" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CCC ,Common Clock Configuration" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " RL ,Retrain Link" "No effect,Initiated"
|
|
textline " "
|
|
bitfld.word 0x00 4. " LD ,Link Disable" "No effect,Disabled"
|
|
bitfld.word 0x00 3. " RCB ,Read Completion Boundary Control" "0,128 Byte"
|
|
bitfld.word 0x00 0.--1. " ASPM ,Active State PM Control" "0,1,2,3"
|
|
line.word 0x02 "PE_LSTS,PCI Express Link Status Register"
|
|
bitfld.word 0x2 12. " SCLK ,Slot Clock Configuration" "Common,Independent"
|
|
bitfld.word 0x2 11. " LT ,Link Training" "Inactive,Active"
|
|
bitfld.word 0x2 10. " LTE ,Link Training Error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x2 4.--9. " NLW ,Negotiated Link Width" "Reserved,1x,2x,Reserved,4x,Reserved,Reserved,Reserved,8x,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,x16,Reserved,x12,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,x32,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
|
|
bitfld.word 0x2 0.--3. " LS ,Link Speed" "Reserved,2.5Gb/s,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
|
|
group.long 0xe4++0x3
|
|
line.long 0x0 "PE_SCAP,PCI Express Slot Capabilities Register"
|
|
hexmask.long.word 0x00 19.--31. 1. " PSN ,Physical Slot Number"
|
|
bitfld.long 0x00 15.--16. " SPLS ,Slot Power Limit Scale" "0,1,2,3"
|
|
hexmask.long.byte 0x00 7.--14. 1. " SPLV ,Slot Power Limit Value"
|
|
textline " "
|
|
bitfld.long 0x00 6. " HPC ,Hot-Plug Capable" "Not capable,Capable"
|
|
bitfld.long 0x00 5. " HPS ,Hot-Plug Surprise" "Not surprised,Surprised"
|
|
bitfld.long 0x00 4. " PIP ,Power Indicator Present" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AIP ,Attention Indicator Present" "Not present,Present"
|
|
bitfld.long 0x00 2. " MSP ,MRL Sensor Present" "Not present,Present"
|
|
bitfld.long 0x00 1. " PCP ,Power Controller Present" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ABP ,Attention Button Present" "Not present,Present"
|
|
group.word 0xe8++0x5
|
|
line.word 0x0 "PE_SCR,PCI Express Slot Control Register"
|
|
bitfld.word 0x00 10. " PCC ,Power Controller Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " PIC ,Power Indicator Control" "0,1,2,3"
|
|
bitfld.word 0x00 6.--7. " AIC ,Attention Indicator Control" "0,1,2,3"
|
|
textline " "
|
|
bitfld.word 0x00 5. " HPI ,Hot-Plug Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CCI ,Command Completed Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " PDC ,Presence Detect Changed Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MSC ,MRL Sensor Changed Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " PFD ,Power Fault Detected Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " ABP ,Attention Button Power Enable" "Disabled,Enabled"
|
|
line.word 0x2 "PE_SSTS,PCI Express Slot Status Register"
|
|
bitfld.word 0x2 6. " PDS ,Presence Detect State" "0,1"
|
|
bitfld.word 0x2 5. " MSS ,MRL Sensor State" "0,1"
|
|
eventfld.word 0x2 4. " CC ,Command Completed" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.word 0x2 3. " PDC ,Presence Detect Changed" "Not changed,Changed"
|
|
eventfld.word 0x2 2. " MSC ,MRL Sensor Changed" "Not changed,Changed"
|
|
eventfld.word 0x2 1. " PFD ,Power Fault Detected" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.word 0x2 0. " ABP ,Attention Button Pressed" "Not pressed,Pressed"
|
|
line.word 0x04 "PE_RCR,PCI Express Root Control Register"
|
|
bitfld.word 0x04 3. " PI ,PME Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 2. " SEFE ,System Error on Fatal Error Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x04 1. " SENFE ,System Error on Non-Fatal Error Enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 0. " ECE ,System Error on Correctable Error Enable" "Disabled,Enabled"
|
|
group.long 0xf0++0x3
|
|
line.long 0x0 "PE_RSR,PCI Express Root Status Register"
|
|
bitfld.long 0x0 17. " PP ,PME Pending" "Not pending,Pending"
|
|
eventfld.long 0x0 16. " PS ,PME Status" "Not asserted,Asserted"
|
|
hexmask.long.word 0x0 0.--15. 1. " RID ,PME Requestor ID"
|
|
group.long 0x100++0x1B
|
|
line.long 0x0 "ADVERR_CAPID,PCI Express Advanced Error Capability Identifier"
|
|
hexmask.long.word 0x0 20.--31. 1. " PEECPTR ,Next PCI Express Extended Capability Pointer"
|
|
bitfld.long 0x0 16.--19. " AECVN ,Advanced Error Capability Version Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x0 0.--15. 1. " AECID ,Advanced Error Capability ID"
|
|
line.long 0x4 "ERRUNC_STS,PCI Express Uncorrectable Error Status"
|
|
eventfld.long 0x04 20. " URES ,Unsupported Request Error Status" "Not detected,Detected"
|
|
eventfld.long 0x04 19. " ECRCC ,ECRC Check" "Normal,Failed"
|
|
eventfld.long 0x04 18. " MTLP ,Malformed TLP" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x04 17. " RO ,Receiver Overflow" "No overflow,Overflow"
|
|
eventfld.long 0x04 16. " UC ,Unexpected Completion" "Not detected,Detected"
|
|
eventfld.long 0x04 15. " CA ,Completer Abort" "No abort,Abort"
|
|
textline " "
|
|
eventfld.long 0x04 14. " CT ,Completion Timeout" "No timeout,Timeout"
|
|
eventfld.long 0x04 13. " FCPE ,Flow Control Protocol Error Status" "Not detected,Detected"
|
|
eventfld.long 0x04 12. " PTLPR ,Poisoned TLP Received" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x04 4. " DLPE ,Data Link Protocol Error" "No error,Error"
|
|
eventfld.long 0x04 0. " TE ,Training Error" "No error,Error"
|
|
line.long 0x8 "ERRUNC_MSK,PCI Express Uncorrectable Error Mask"
|
|
bitfld.long 0x8 20. " URES ,Unsupported Request Error Status Mask" "Not masked,Masked"
|
|
bitfld.long 0x8 19. " ECRCC ,ECRC Check Mask" "Not masked,Masked"
|
|
bitfld.long 0x8 18. " MTLP ,Malformed TLP Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x8 17. " RO ,Receiver Overflow Mask" "Not masked,Masked"
|
|
bitfld.long 0x8 16. " UC ,Unexpected Completion Mask" "Not masked,Masked"
|
|
bitfld.long 0x8 15. " CA ,Completer Abort Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x8 14. " CT ,Completion Timeout Mask" "Not masked,Masked"
|
|
bitfld.long 0x8 13. " FCPE ,Flow Control Protocol Error Status Mask" "Not masked,Masked"
|
|
bitfld.long 0x8 12. " PTLPR ,Poisoned TLP Received Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x8 4. " DLPE ,Data Link Protocol Error Mask" "Not masked,Masked"
|
|
bitfld.long 0x8 0. " TE ,Training Error Mask" "Not masked,Masked"
|
|
line.long 0xc "ERRUNC_SEV,PCI Express Uncorrectable Error Severity"
|
|
bitfld.long 0x0c 20. " URES ,Unsupported Request Error Status Severity" "Non-fatal,Fatal"
|
|
bitfld.long 0x0c 19. " ECRCC ,ECRC Check Severity" "Non-fatal,Fatal"
|
|
bitfld.long 0x0c 18. " MTLP ,Malformed TLP Severity" "Non-fatal,Fatal"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " RO ,Receiver Overflow Severity" "Non-fatal,Fatal"
|
|
bitfld.long 0x0c 16. " UC ,Unexpected Completion Severity" "Non-fatal,Fatal"
|
|
bitfld.long 0x0c 15. " CA ,Completer Abort Severity" "Non-fatal,Fatal"
|
|
textline " "
|
|
bitfld.long 0x0c 14. " CT ,Completion Timeout Severity" "Non-fatal,Fatal"
|
|
bitfld.long 0x0c 13. " FCPE ,Flow Control Protocol Error Status Severity" "Non-fatal,Fatal"
|
|
bitfld.long 0x0c 12. " PTLPR ,Poisoned TLP Received Severity" "Non-fatal,Fatal"
|
|
textline " "
|
|
bitfld.long 0x0c 4. " DLPE ,Data Link Protocol Error Severity" "Non-fatal,Fatal"
|
|
bitfld.long 0x0c 0. " TE ,Training Error Severity" "Non-fatal,Fatal"
|
|
line.long 0x10 "ERRCOR_STS,PCI Express Correctable Error Status"
|
|
eventfld.long 0x10 13. " ANFE ,Advisory Non-Fatal Error Status" "No error,Error"
|
|
eventfld.long 0x10 12. " RTT ,Replay Timer Timeout Status" "No timeout,Timeout"
|
|
eventfld.long 0x10 8. " RNR ,REPLAY_NUM Rollover Status" "No rollover,Rollover"
|
|
textline " "
|
|
eventfld.long 0x10 7. " BDLLP ,Bad DLLP Status" "Not occurred,Occurred"
|
|
eventfld.long 0x10 6. " BTLP ,Bad TLP Status" "Not occurred,Occurred"
|
|
eventfld.long 0x10 0. " RXE ,Receiver Error Status" "No error,Error"
|
|
line.long 0x14 "ERRCOR_MSK,PCI Express Correctable Error Mask"
|
|
bitfld.long 0x14 13. " ANFE ,Advisory Non-Fatal Error Mask" "Not masked,Masked"
|
|
bitfld.long 0x14 12. " RTT ,Replay Timer Timeout Mask" "Not masked,Masked"
|
|
bitfld.long 0x14 8. " RNR ,REPLAY_NUM Rollover Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x14 7. " BDLLP ,Bad DLLP Mask" "Not masked,Masked"
|
|
bitfld.long 0x14 6. " BTLP ,Bad TLP Mask" "Not masked,Masked"
|
|
bitfld.long 0x14 0. " RXE ,Receiver Error Mask" "Not masked,Masked"
|
|
line.long 0x18 "ADVERR_CTL,Advanced Error Control and Capability Register"
|
|
bitfld.long 0x18 8. " ECE ,ECRC Check Enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 7. " ECC ,ECRC Check Capable" "Not capable,Capable"
|
|
bitfld.long 0x18 6. " EGE ,ECRC Generation Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 5. " EGC ,ECRC Generation Capable" "Not capable,Capable"
|
|
bitfld.long 0x18 0.--4. " FEP ,The First Error Pointer" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F,10,11,12,13,14,15,16,17,18,19,1A,1B,1C,1D,1E,1F"
|
|
rgroup.long 0x11c++0xf
|
|
line.long 0x0 "ADVERR_LOG0,PCI Express Advanced Error Header Log 0"
|
|
line.long 0x4 "ADVERR_LOG1,PCI Express Advanced Error Header Log 1"
|
|
line.long 0x8 "ADVERR_LOG2,PCI Express Advanced Error Header Log 2"
|
|
line.long 0xC "ADVERR_LOG3,PCI Express Advanced Error Header Log 3"
|
|
group.long 0x12c++0xb
|
|
line.long 0x0 "RERR_CMD,Root Error Command Register"
|
|
bitfld.long 0x0 2. " FER ,Fatal Error Reporting Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " NFER ,Non-Fatal Error Reporting Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " CER ,Correctable Error Reporting Enable" "Disabled,Enabled"
|
|
line.long 0x4 "RERR_SR,Root Error Status Register"
|
|
bitfld.long 0x04 27.--31. " AEIMN ,Advanced Error Interrupt Message Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 6. " FEM ,Fatal Error Message Received" "Not received,Received"
|
|
bitfld.long 0x04 5. " NFEM ,Non-Fatal Error Messages Received" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x04 4. " FUF ,First Uncorrectable Fatal" "Nonfatal,Fatal"
|
|
bitfld.long 0x04 3. " MEFNF ,Multiple ERR_FATAL/NONFATAL Received" "Not received,Received"
|
|
bitfld.long 0x04 2. " EFNF ,ERR_FATAL/NONFATAL Received" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x04 1. " MEC ,Multiple ERR_COR Received" "Not received,Received"
|
|
bitfld.long 0x04 0. " EC ,ERR_COR Received" "Not received,Received"
|
|
line.long 0x08 "RERR_ID,Error Source Identification Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " EFNFSI ,ERR_FATAL/NONFATAL Source Identification"
|
|
hexmask.long.word 0x08 0.--15. 1. " ECSI ,ERR_COR Source Identification"
|
|
rgroup.long 0x1e0++0x3
|
|
line.long 0x0 "DSN_CAP,Device Serial Number Capability"
|
|
hexmask.long.word 0x00 20.--31. 1. " NCO ,Next Capability Offset"
|
|
bitfld.long 0x00 16.--19. " CVER ,Capability Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " ECID ,PCI Express Extended Capability ID"
|
|
group.long 0x1e4++0xb
|
|
line.long 0x00 "DSN_LDW,Device Serial Number Lower DW Register"
|
|
line.long 0x04 "DSN_UDW,Device Serial Number Upper DW Register"
|
|
line.long 0x08 "PIE_AEC,PCI Express Advisory Error Control Register"
|
|
bitfld.long 0x08 6. " AECT ,Advisory Error Enable for Completion Timeout" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " AEPPT ,Advisory Error Enable for Poisoned Posted TLPs" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " AEPC ,Advisory Error Enable for Poisoned Completions" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " GENEN ,Generate ERR_NONFATAL" "Not generated,Generated"
|
|
rgroup.long 0x1f0++0x3
|
|
line.long 0x00 "PWRBGT_CAPID,Power Budgeting Enhanced Capability Header"
|
|
hexmask.long.word 0x00 20.--31. 1. " NPECP ,Next PCI Express Extended Capability Pointer"
|
|
bitfld.long 0x00 16.--19. " PBCV ,Power Budgeting Capability Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " PBCID ,Power Budgeting Capability ID"
|
|
group.long 0x1f4++0x3
|
|
line.long 0x00 "PWRBGT_DSEL,Power Budgeting Data Select Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATASEL ,Data Select"
|
|
rgroup.long 0x1f8++0x3
|
|
line.long 0x0 "PWRBGT_DATA,Power Budgeting Data Register"
|
|
bitfld.long 0x00 18.--20. " PRAIL ,Power Rail" "12V,3.3V,1.8V,Reserved,Reserved,Reserved,Reserved,Thermal"
|
|
bitfld.long 0x00 15.--17. " TYPE ,Type" "PME Aux,Auxiliary,Idle,Sustained,Reserved,Reserved,Reserved,Maximum"
|
|
bitfld.long 0x00 13.--14. " PM ,PM State" "D0,D1,D2,D3"
|
|
textline " "
|
|
bitfld.long 0x00 10.--12. " PMS ,PM Sub State" "Default,State 1,State 2,State 3,State 4,State 5,State 6,State 7"
|
|
bitfld.long 0x00 8.--9. " DATAS ,Data Scale" "1.0x,0.1x,0.01x,0.001x"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BASEP ,Base Power"
|
|
group.long 0x1fc++0x3
|
|
line.long 0x0 "PWRBGT_CAP,Power Budgeting Capability Register"
|
|
bitfld.long 0x00 0. " SAL ,System Allocated" "Software,System"
|
|
tree "Power Budgeting Information Registers"
|
|
group.long 0x200++0x5f
|
|
textline " "
|
|
line.long 0x0 "PWRBGT_INFO0,Power Budgeting Information Register 0"
|
|
bitfld.long 0x0 18.--20. " PRAIL ,Power Rail" "12V,3.3V,1.8V,Reserved,Reserved,Reserved,Reserved,Thermal"
|
|
bitfld.long 0x0 15.--17. " TYPE ,Type" "PME Aux,Auxiliary,Idle,Sustained,Reserved,Reserved,Reserved,Maximum"
|
|
bitfld.long 0x0 13.--14. " PM ,PM State" "D0,D1,D2,D3"
|
|
textline " "
|
|
bitfld.long 0x0 10.--12. " PMS ,PM Sub State" "Default,State 1,State 2,State 3,State 4,State 5,State 6,State 7"
|
|
bitfld.long 0x0 8.--9. " DATAS ,Data Scale" "1.0x,0.1x,0.01x,0.001x"
|
|
hexmask.long.byte 0x0 0.--7. 1. " BASEP ,Base Power"
|
|
line.long 0x4 "PWRBGT_INFO1,Power Budgeting Information Register 1"
|
|
bitfld.long 0x4 18.--20. " PRAIL ,Power Rail" "12V,3.3V,1.8V,Reserved,Reserved,Reserved,Reserved,Thermal"
|
|
bitfld.long 0x4 15.--17. " TYPE ,Type" "PME Aux,Auxiliary,Idle,Sustained,Reserved,Reserved,Reserved,Maximum"
|
|
bitfld.long 0x4 13.--14. " PM ,PM State" "D0,D1,D2,D3"
|
|
textline " "
|
|
bitfld.long 0x4 10.--12. " PMS ,PM Sub State" "Default,State 1,State 2,State 3,State 4,State 5,State 6,State 7"
|
|
bitfld.long 0x4 8.--9. " DATAS ,Data Scale" "1.0x,0.1x,0.01x,0.001x"
|
|
hexmask.long.byte 0x4 0.--7. 1. " BASEP ,Base Power"
|
|
line.long 0x8 "PWRBGT_INFO2,Power Budgeting Information Register 2"
|
|
bitfld.long 0x8 18.--20. " PRAIL ,Power Rail" "12V,3.3V,1.8V,Reserved,Reserved,Reserved,Reserved,Thermal"
|
|
bitfld.long 0x8 15.--17. " TYPE ,Type" "PME Aux,Auxiliary,Idle,Sustained,Reserved,Reserved,Reserved,Maximum"
|
|
bitfld.long 0x8 13.--14. " PM ,PM State" "D0,D1,D2,D3"
|
|
textline " "
|
|
bitfld.long 0x8 10.--12. " PMS ,PM Sub State" "Default,State 1,State 2,State 3,State 4,State 5,State 6,State 7"
|
|
bitfld.long 0x8 8.--9. " DATAS ,Data Scale" "1.0x,0.1x,0.01x,0.001x"
|
|
hexmask.long.byte 0x8 0.--7. 1. " BASEP ,Base Power"
|
|
line.long 0xC "PWRBGT_INFO3,Power Budgeting Information Register 3"
|
|
bitfld.long 0xC 18.--20. " PRAIL ,Power Rail" "12V,3.3V,1.8V,Reserved,Reserved,Reserved,Reserved,Thermal"
|
|
bitfld.long 0xC 15.--17. " TYPE ,Type" "PME Aux,Auxiliary,Idle,Sustained,Reserved,Reserved,Reserved,Maximum"
|
|
bitfld.long 0xC 13.--14. " PM ,PM State" "D0,D1,D2,D3"
|
|
textline " "
|
|
bitfld.long 0xC 10.--12. " PMS ,PM Sub State" "Default,State 1,State 2,State 3,State 4,State 5,State 6,State 7"
|
|
bitfld.long 0xC 8.--9. " DATAS ,Data Scale" "1.0x,0.1x,0.01x,0.001x"
|
|
hexmask.long.byte 0xC 0.--7. 1. " BASEP ,Base Power"
|
|
line.long 0x10 "PWRBGT_INFO4,Power Budgeting Information Register 4"
|
|
bitfld.long 0x10 18.--20. " PRAIL ,Power Rail" "12V,3.3V,1.8V,Reserved,Reserved,Reserved,Reserved,Thermal"
|
|
bitfld.long 0x10 15.--17. " TYPE ,Type" "PME Aux,Auxiliary,Idle,Sustained,Reserved,Reserved,Reserved,Maximum"
|
|
bitfld.long 0x10 13.--14. " PM ,PM State" "D0,D1,D2,D3"
|
|
textline " "
|
|
bitfld.long 0x10 10.--12. " PMS ,PM Sub State" "Default,State 1,State 2,State 3,State 4,State 5,State 6,State 7"
|
|
bitfld.long 0x10 8.--9. " DATAS ,Data Scale" "1.0x,0.1x,0.01x,0.001x"
|
|
hexmask.long.byte 0x10 0.--7. 1. " BASEP ,Base Power"
|
|
line.long 0x14 "PWRBGT_INFO5,Power Budgeting Information Register 5"
|
|
bitfld.long 0x14 18.--20. " PRAIL ,Power Rail" "12V,3.3V,1.8V,Reserved,Reserved,Reserved,Reserved,Thermal"
|
|
bitfld.long 0x14 15.--17. " TYPE ,Type" "PME Aux,Auxiliary,Idle,Sustained,Reserved,Reserved,Reserved,Maximum"
|
|
bitfld.long 0x14 13.--14. " PM ,PM State" "D0,D1,D2,D3"
|
|
textline " "
|
|
bitfld.long 0x14 10.--12. " PMS ,PM Sub State" "Default,State 1,State 2,State 3,State 4,State 5,State 6,State 7"
|
|
bitfld.long 0x14 8.--9. " DATAS ,Data Scale" "1.0x,0.1x,0.01x,0.001x"
|
|
hexmask.long.byte 0x14 0.--7. 1. " BASEP ,Base Power"
|
|
line.long 0x18 "PWRBGT_INFO6,Power Budgeting Information Register 6"
|
|
bitfld.long 0x18 18.--20. " PRAIL ,Power Rail" "12V,3.3V,1.8V,Reserved,Reserved,Reserved,Reserved,Thermal"
|
|
bitfld.long 0x18 15.--17. " TYPE ,Type" "PME Aux,Auxiliary,Idle,Sustained,Reserved,Reserved,Reserved,Maximum"
|
|
bitfld.long 0x18 13.--14. " PM ,PM State" "D0,D1,D2,D3"
|
|
textline " "
|
|
bitfld.long 0x18 10.--12. " PMS ,PM Sub State" "Default,State 1,State 2,State 3,State 4,State 5,State 6,State 7"
|
|
bitfld.long 0x18 8.--9. " DATAS ,Data Scale" "1.0x,0.1x,0.01x,0.001x"
|
|
hexmask.long.byte 0x18 0.--7. 1. " BASEP ,Base Power"
|
|
line.long 0x1C "PWRBGT_INFO7,Power Budgeting Information Register 7"
|
|
bitfld.long 0x1C 18.--20. " PRAIL ,Power Rail" "12V,3.3V,1.8V,Reserved,Reserved,Reserved,Reserved,Thermal"
|
|
bitfld.long 0x1C 15.--17. " TYPE ,Type" "PME Aux,Auxiliary,Idle,Sustained,Reserved,Reserved,Reserved,Maximum"
|
|
bitfld.long 0x1C 13.--14. " PM ,PM State" "D0,D1,D2,D3"
|
|
textline " "
|
|
bitfld.long 0x1C 10.--12. " PMS ,PM Sub State" "Default,State 1,State 2,State 3,State 4,State 5,State 6,State 7"
|
|
bitfld.long 0x1C 8.--9. " DATAS ,Data Scale" "1.0x,0.1x,0.01x,0.001x"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " BASEP ,Base Power"
|
|
line.long 0x20 "PWRBGT_INFO8,Power Budgeting Information Register 8"
|
|
bitfld.long 0x20 18.--20. " PRAIL ,Power Rail" "12V,3.3V,1.8V,Reserved,Reserved,Reserved,Reserved,Thermal"
|
|
bitfld.long 0x20 15.--17. " TYPE ,Type" "PME Aux,Auxiliary,Idle,Sustained,Reserved,Reserved,Reserved,Maximum"
|
|
bitfld.long 0x20 13.--14. " PM ,PM State" "D0,D1,D2,D3"
|
|
textline " "
|
|
bitfld.long 0x20 10.--12. " PMS ,PM Sub State" "Default,State 1,State 2,State 3,State 4,State 5,State 6,State 7"
|
|
bitfld.long 0x20 8.--9. " DATAS ,Data Scale" "1.0x,0.1x,0.01x,0.001x"
|
|
hexmask.long.byte 0x20 0.--7. 1. " BASEP ,Base Power"
|
|
line.long 0x24 "PWRBGT_INFO9,Power Budgeting Information Register 9"
|
|
bitfld.long 0x24 18.--20. " PRAIL ,Power Rail" "12V,3.3V,1.8V,Reserved,Reserved,Reserved,Reserved,Thermal"
|
|
bitfld.long 0x24 15.--17. " TYPE ,Type" "PME Aux,Auxiliary,Idle,Sustained,Reserved,Reserved,Reserved,Maximum"
|
|
bitfld.long 0x24 13.--14. " PM ,PM State" "D0,D1,D2,D3"
|
|
textline " "
|
|
bitfld.long 0x24 10.--12. " PMS ,PM Sub State" "Default,State 1,State 2,State 3,State 4,State 5,State 6,State 7"
|
|
bitfld.long 0x24 8.--9. " DATAS ,Data Scale" "1.0x,0.1x,0.01x,0.001x"
|
|
hexmask.long.byte 0x24 0.--7. 1. " BASEP ,Base Power"
|
|
line.long 0x28 "PWRBGT_INFO10,Power Budgeting Information Register 10"
|
|
bitfld.long 0x28 18.--20. " PRAIL ,Power Rail" "12V,3.3V,1.8V,Reserved,Reserved,Reserved,Reserved,Thermal"
|
|
bitfld.long 0x28 15.--17. " TYPE ,Type" "PME Aux,Auxiliary,Idle,Sustained,Reserved,Reserved,Reserved,Maximum"
|
|
bitfld.long 0x28 13.--14. " PM ,PM State" "D0,D1,D2,D3"
|
|
textline " "
|
|
bitfld.long 0x28 10.--12. " PMS ,PM Sub State" "Default,State 1,State 2,State 3,State 4,State 5,State 6,State 7"
|
|
bitfld.long 0x28 8.--9. " DATAS ,Data Scale" "1.0x,0.1x,0.01x,0.001x"
|
|
hexmask.long.byte 0x28 0.--7. 1. " BASEP ,Base Power"
|
|
line.long 0x2C "PWRBGT_INFO11,Power Budgeting Information Register 11"
|
|
bitfld.long 0x2C 18.--20. " PRAIL ,Power Rail" "12V,3.3V,1.8V,Reserved,Reserved,Reserved,Reserved,Thermal"
|
|
bitfld.long 0x2C 15.--17. " TYPE ,Type" "PME Aux,Auxiliary,Idle,Sustained,Reserved,Reserved,Reserved,Maximum"
|
|
bitfld.long 0x2C 13.--14. " PM ,PM State" "D0,D1,D2,D3"
|
|
textline " "
|
|
bitfld.long 0x2C 10.--12. " PMS ,PM Sub State" "Default,State 1,State 2,State 3,State 4,State 5,State 6,State 7"
|
|
bitfld.long 0x2C 8.--9. " DATAS ,Data Scale" "1.0x,0.1x,0.01x,0.001x"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " BASEP ,Base Power"
|
|
line.long 0x30 "PWRBGT_INFO12,Power Budgeting Information Register 12"
|
|
bitfld.long 0x30 18.--20. " PRAIL ,Power Rail" "12V,3.3V,1.8V,Reserved,Reserved,Reserved,Reserved,Thermal"
|
|
bitfld.long 0x30 15.--17. " TYPE ,Type" "PME Aux,Auxiliary,Idle,Sustained,Reserved,Reserved,Reserved,Maximum"
|
|
bitfld.long 0x30 13.--14. " PM ,PM State" "D0,D1,D2,D3"
|
|
textline " "
|
|
bitfld.long 0x30 10.--12. " PMS ,PM Sub State" "Default,State 1,State 2,State 3,State 4,State 5,State 6,State 7"
|
|
bitfld.long 0x30 8.--9. " DATAS ,Data Scale" "1.0x,0.1x,0.01x,0.001x"
|
|
hexmask.long.byte 0x30 0.--7. 1. " BASEP ,Base Power"
|
|
line.long 0x34 "PWRBGT_INFO13,Power Budgeting Information Register 13"
|
|
bitfld.long 0x34 18.--20. " PRAIL ,Power Rail" "12V,3.3V,1.8V,Reserved,Reserved,Reserved,Reserved,Thermal"
|
|
bitfld.long 0x34 15.--17. " TYPE ,Type" "PME Aux,Auxiliary,Idle,Sustained,Reserved,Reserved,Reserved,Maximum"
|
|
bitfld.long 0x34 13.--14. " PM ,PM State" "D0,D1,D2,D3"
|
|
textline " "
|
|
bitfld.long 0x34 10.--12. " PMS ,PM Sub State" "Default,State 1,State 2,State 3,State 4,State 5,State 6,State 7"
|
|
bitfld.long 0x34 8.--9. " DATAS ,Data Scale" "1.0x,0.1x,0.01x,0.001x"
|
|
hexmask.long.byte 0x34 0.--7. 1. " BASEP ,Base Power"
|
|
line.long 0x38 "PWRBGT_INFO14,Power Budgeting Information Register 14"
|
|
bitfld.long 0x38 18.--20. " PRAIL ,Power Rail" "12V,3.3V,1.8V,Reserved,Reserved,Reserved,Reserved,Thermal"
|
|
bitfld.long 0x38 15.--17. " TYPE ,Type" "PME Aux,Auxiliary,Idle,Sustained,Reserved,Reserved,Reserved,Maximum"
|
|
bitfld.long 0x38 13.--14. " PM ,PM State" "D0,D1,D2,D3"
|
|
textline " "
|
|
bitfld.long 0x38 10.--12. " PMS ,PM Sub State" "Default,State 1,State 2,State 3,State 4,State 5,State 6,State 7"
|
|
bitfld.long 0x38 8.--9. " DATAS ,Data Scale" "1.0x,0.1x,0.01x,0.001x"
|
|
hexmask.long.byte 0x38 0.--7. 1. " BASEP ,Base Power"
|
|
line.long 0x3C "PWRBGT_INFO15,Power Budgeting Information Register 15"
|
|
bitfld.long 0x3C 18.--20. " PRAIL ,Power Rail" "12V,3.3V,1.8V,Reserved,Reserved,Reserved,Reserved,Thermal"
|
|
bitfld.long 0x3C 15.--17. " TYPE ,Type" "PME Aux,Auxiliary,Idle,Sustained,Reserved,Reserved,Reserved,Maximum"
|
|
bitfld.long 0x3C 13.--14. " PM ,PM State" "D0,D1,D2,D3"
|
|
textline " "
|
|
bitfld.long 0x3C 10.--12. " PMS ,PM Sub State" "Default,State 1,State 2,State 3,State 4,State 5,State 6,State 7"
|
|
bitfld.long 0x3C 8.--9. " DATAS ,Data Scale" "1.0x,0.1x,0.01x,0.001x"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " BASEP ,Base Power"
|
|
line.long 0x40 "PWRBGT_INFO16,Power Budgeting Information Register 16"
|
|
bitfld.long 0x40 18.--20. " PRAIL ,Power Rail" "12V,3.3V,1.8V,Reserved,Reserved,Reserved,Reserved,Thermal"
|
|
bitfld.long 0x40 15.--17. " TYPE ,Type" "PME Aux,Auxiliary,Idle,Sustained,Reserved,Reserved,Reserved,Maximum"
|
|
bitfld.long 0x40 13.--14. " PM ,PM State" "D0,D1,D2,D3"
|
|
textline " "
|
|
bitfld.long 0x40 10.--12. " PMS ,PM Sub State" "Default,State 1,State 2,State 3,State 4,State 5,State 6,State 7"
|
|
bitfld.long 0x40 8.--9. " DATAS ,Data Scale" "1.0x,0.1x,0.01x,0.001x"
|
|
hexmask.long.byte 0x40 0.--7. 1. " BASEP ,Base Power"
|
|
line.long 0x44 "PWRBGT_INFO17,Power Budgeting Information Register 17"
|
|
bitfld.long 0x44 18.--20. " PRAIL ,Power Rail" "12V,3.3V,1.8V,Reserved,Reserved,Reserved,Reserved,Thermal"
|
|
bitfld.long 0x44 15.--17. " TYPE ,Type" "PME Aux,Auxiliary,Idle,Sustained,Reserved,Reserved,Reserved,Maximum"
|
|
bitfld.long 0x44 13.--14. " PM ,PM State" "D0,D1,D2,D3"
|
|
textline " "
|
|
bitfld.long 0x44 10.--12. " PMS ,PM Sub State" "Default,State 1,State 2,State 3,State 4,State 5,State 6,State 7"
|
|
bitfld.long 0x44 8.--9. " DATAS ,Data Scale" "1.0x,0.1x,0.01x,0.001x"
|
|
hexmask.long.byte 0x44 0.--7. 1. " BASEP ,Base Power"
|
|
line.long 0x48 "PWRBGT_INFO18,Power Budgeting Information Register 18"
|
|
bitfld.long 0x48 18.--20. " PRAIL ,Power Rail" "12V,3.3V,1.8V,Reserved,Reserved,Reserved,Reserved,Thermal"
|
|
bitfld.long 0x48 15.--17. " TYPE ,Type" "PME Aux,Auxiliary,Idle,Sustained,Reserved,Reserved,Reserved,Maximum"
|
|
bitfld.long 0x48 13.--14. " PM ,PM State" "D0,D1,D2,D3"
|
|
textline " "
|
|
bitfld.long 0x48 10.--12. " PMS ,PM Sub State" "Default,State 1,State 2,State 3,State 4,State 5,State 6,State 7"
|
|
bitfld.long 0x48 8.--9. " DATAS ,Data Scale" "1.0x,0.1x,0.01x,0.001x"
|
|
hexmask.long.byte 0x48 0.--7. 1. " BASEP ,Base Power"
|
|
line.long 0x4C "PWRBGT_INFO19,Power Budgeting Information Register 19"
|
|
bitfld.long 0x4C 18.--20. " PRAIL ,Power Rail" "12V,3.3V,1.8V,Reserved,Reserved,Reserved,Reserved,Thermal"
|
|
bitfld.long 0x4C 15.--17. " TYPE ,Type" "PME Aux,Auxiliary,Idle,Sustained,Reserved,Reserved,Reserved,Maximum"
|
|
bitfld.long 0x4C 13.--14. " PM ,PM State" "D0,D1,D2,D3"
|
|
textline " "
|
|
bitfld.long 0x4C 10.--12. " PMS ,PM Sub State" "Default,State 1,State 2,State 3,State 4,State 5,State 6,State 7"
|
|
bitfld.long 0x4C 8.--9. " DATAS ,Data Scale" "1.0x,0.1x,0.01x,0.001x"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " BASEP ,Base Power"
|
|
line.long 0x50 "PWRBGT_INFO20,Power Budgeting Information Register 20"
|
|
bitfld.long 0x50 18.--20. " PRAIL ,Power Rail" "12V,3.3V,1.8V,Reserved,Reserved,Reserved,Reserved,Thermal"
|
|
bitfld.long 0x50 15.--17. " TYPE ,Type" "PME Aux,Auxiliary,Idle,Sustained,Reserved,Reserved,Reserved,Maximum"
|
|
bitfld.long 0x50 13.--14. " PM ,PM State" "D0,D1,D2,D3"
|
|
textline " "
|
|
bitfld.long 0x50 10.--12. " PMS ,PM Sub State" "Default,State 1,State 2,State 3,State 4,State 5,State 6,State 7"
|
|
bitfld.long 0x50 8.--9. " DATAS ,Data Scale" "1.0x,0.1x,0.01x,0.001x"
|
|
hexmask.long.byte 0x50 0.--7. 1. " BASEP ,Base Power"
|
|
line.long 0x54 "PWRBGT_INFO21,Power Budgeting Information Register 21"
|
|
bitfld.long 0x54 18.--20. " PRAIL ,Power Rail" "12V,3.3V,1.8V,Reserved,Reserved,Reserved,Reserved,Thermal"
|
|
bitfld.long 0x54 15.--17. " TYPE ,Type" "PME Aux,Auxiliary,Idle,Sustained,Reserved,Reserved,Reserved,Maximum"
|
|
bitfld.long 0x54 13.--14. " PM ,PM State" "D0,D1,D2,D3"
|
|
textline " "
|
|
bitfld.long 0x54 10.--12. " PMS ,PM Sub State" "Default,State 1,State 2,State 3,State 4,State 5,State 6,State 7"
|
|
bitfld.long 0x54 8.--9. " DATAS ,Data Scale" "1.0x,0.1x,0.01x,0.001x"
|
|
hexmask.long.byte 0x54 0.--7. 1. " BASEP ,Base Power"
|
|
line.long 0x58 "PWRBGT_INFO22,Power Budgeting Information Register 22"
|
|
bitfld.long 0x58 18.--20. " PRAIL ,Power Rail" "12V,3.3V,1.8V,Reserved,Reserved,Reserved,Reserved,Thermal"
|
|
bitfld.long 0x58 15.--17. " TYPE ,Type" "PME Aux,Auxiliary,Idle,Sustained,Reserved,Reserved,Reserved,Maximum"
|
|
bitfld.long 0x58 13.--14. " PM ,PM State" "D0,D1,D2,D3"
|
|
textline " "
|
|
bitfld.long 0x58 10.--12. " PMS ,PM Sub State" "Default,State 1,State 2,State 3,State 4,State 5,State 6,State 7"
|
|
bitfld.long 0x58 8.--9. " DATAS ,Data Scale" "1.0x,0.1x,0.01x,0.001x"
|
|
hexmask.long.byte 0x58 0.--7. 1. " BASEP ,Base Power"
|
|
line.long 0x5C "PWRBGT_INFO23,Power Budgeting Information Register 23"
|
|
bitfld.long 0x5C 18.--20. " PRAIL ,Power Rail" "12V,3.3V,1.8V,Reserved,Reserved,Reserved,Reserved,Thermal"
|
|
bitfld.long 0x5C 15.--17. " TYPE ,Type" "PME Aux,Auxiliary,Idle,Sustained,Reserved,Reserved,Reserved,Maximum"
|
|
bitfld.long 0x5C 13.--14. " PM ,PM State" "D0,D1,D2,D3"
|
|
textline " "
|
|
bitfld.long 0x5C 10.--12. " PMS ,PM Sub State" "Default,State 1,State 2,State 3,State 4,State 5,State 6,State 7"
|
|
bitfld.long 0x5C 8.--9. " DATAS ,Data Scale" "1.0x,0.1x,0.01x,0.001x"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " BASEP ,Base Power"
|
|
tree.end
|
|
textline " "
|
|
group.long 0x300++0x27
|
|
line.long 0x0 "OIOBAR,Outbound I/O Base Address Register"
|
|
hexmask.long 0x0 12.--31. 0x1000 " OIOBA ,Outbound I/O Base Address"
|
|
bitfld.long 0x0 0.--2. " OIOFNM ,Outbound I/O Function Number Mapping" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "OIOWTVR,Outbound I/O Window Translate Value Register"
|
|
hexmask.long 0x04 16.--31. 0x10000 " OIOWTV ,Outbound I/O Window Translate Value"
|
|
bitfld.long 0x04 0. " BEBS ,Big Endian Byte Swap enable" "Disabled,Enabled"
|
|
line.long 0x8 "OUMBAR0,Outbound Upper Memory Window Base Address Register 0"
|
|
bitfld.long 0x8 31. " OW0 ,Outbound Window 0 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 28.--30. " OW0FNM ,Outbound Window 0 Function Number Mapping" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x8 27. " BEBS ,Big Endian Byte Swap enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 0.--3. " OUMWBA0 ,Outbound Upper Memory Window Base Address 0" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F"
|
|
line.long 0xC "OUMWTVR0,Outbound Upper Memory Window Translate Value Register 0"
|
|
line.long 0x10 "OUMBAR1,Outbound Upper Memory Window Base Address Register 1"
|
|
bitfld.long 0x10 31. " OW1 ,Outbound Window 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 28.--30. " OW1FNM ,Outbound Window 1 Function Number Mapping" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x10 27. " BEBS ,Big Endian Byte Swap enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0.--3. " OUMWBA1 ,Outbound Upper Memory Window Base Address 1" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F"
|
|
line.long 0x14 "OUMWTVR1,Outbound Upper Memory Window Translate Value Register 1"
|
|
line.long 0x18 "OUMBAR2,Outbound Upper Memory Window Base Address Register 2"
|
|
bitfld.long 0x18 31. " OW2 ,Outbound Window 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 28.--30. " OW2FNM ,Outbound Window 2 Function Number Mapping" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x18 27. " BEBS ,Big Endian Byte Swap enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 0.--3. " OUMWBA2 ,Outbound Upper Memory Window Base Address 2" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F"
|
|
line.long 0x1C "OUMWTVR2,Outbound Upper Memory Window Translate Value Register 2"
|
|
line.long 0x20 "OUMBAR3,Outbound Upper Memory Window Base Address Register 3"
|
|
bitfld.long 0x20 31. " OW3 ,Outbound Window 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 28.--30. " OW3FNM ,Outbound Window 3 Function Number Mapping" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x20 27. " BEBS ,Big Endian Byte Swap enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 0.--3. " OUMWBA3 ,Outbound Upper Memory Window Base Address 3" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F"
|
|
line.long 0x24 "OUMWTVR3,Outbound Upper Memory Window Translate Value Register 3"
|
|
group.long 0x32c++0xb
|
|
line.long 0x0 "OCCAR,Outbound Configuration Cycle Address Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BUSNO ,Bus Number"
|
|
bitfld.long 0x00 19.--23. " DEVNO ,Device Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--18. " FUNO ,Function Number" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " EREGNO ,Extended Register Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2.--7. " REGNO ,Register Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0. " CONF ,Configuration Type" "Type 0,Type 1"
|
|
line.long 0x4 "OCCDR,Outbound Configuration Cycle Data Register"
|
|
line.long 0x8 "OCCFN,Outbound Configuration Cycle Function Number"
|
|
bitfld.long 0x08 0.--02. " CCFNO ,Configuration Cycle Function Number" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x340++0x13
|
|
line.long 0x0 "IVMHR0,Inbound Vendor Defined Message Header Register 0"
|
|
hexmask.long.byte 0x0 24.--31. 1. " HEAD0 ,Header Byte 0"
|
|
hexmask.long.byte 0x0 16.--23. 1. " HEAD1 ,Header Byte 1"
|
|
hexmask.long.byte 0x0 8.--15. 1. " HEAD2 ,Header Byte 2"
|
|
hexmask.long.byte 0x0 0.--7. 1. " HEAD3 ,Header Byte 3"
|
|
line.long 0x04 "IVMHR1,Inbound Vendor Defined Message Header Register 1"
|
|
hexmask.long.byte 0x04 24.--31. 1. " HEAD4 ,Header Byte 4"
|
|
hexmask.long.byte 0x04 16.--23. 1. " HEAD5 ,Header Byte 5"
|
|
hexmask.long.byte 0x04 8.--15. 1. " HEAD6 ,Header Byte 6"
|
|
hexmask.long.byte 0x04 0.--7. 1. " HEAD7 ,Header Byte 7"
|
|
line.long 0x08 "IVMHR2,Inbound Vendor Defined Message Header Register 2"
|
|
hexmask.long.byte 0x08 24.--31. 1. " HEAD8 ,Header Byte 8"
|
|
hexmask.long.byte 0x08 16.--23. 1. " HEAD9 ,Header Byte 9"
|
|
hexmask.long.byte 0x08 8.--15. 1. " HEAD10 ,Header Byte 10"
|
|
hexmask.long.byte 0x08 0.--7. 1. " HEAD11 ,Header Byte 11"
|
|
line.long 0x0c "IVMHR3,Inbound Vendor Defined Message Header Register 3"
|
|
hexmask.long.byte 0x0c 24.--31. 1. " HEAD12 ,Header Byte 12"
|
|
hexmask.long.byte 0x0c 16.--23. 1. " HEAD13 ,Header Byte 13"
|
|
hexmask.long.byte 0x0c 8.--15. 1. " HEAD14 ,Header Byte 14"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " HEAD15 ,Header Byte 15"
|
|
line.long 0x10 "IVMPR,Inbound Vendor Defined Message Payload Register"
|
|
group.long 0x360++0xf
|
|
line.long 0x0 "OVMHR0,Outbound Vendor Defined Message Header Register0"
|
|
bitfld.long 0x00 29.--30. " FMT ,Format of TLP" "Reserved,4DW/no data,Reserved,4DW/with data"
|
|
bitfld.long 0x00 27.--28. " TYPE[4:3] ,Type [4:3]" "Reserved,Reserved,vendor_def,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " TYPE[2:0] ,Type [2:0]" "to Root Complex,by Address,by ID,from Root Complex,Local,Gathered,Reserved/terminate at Rx,Reserved/terminate at Rx"
|
|
textline " "
|
|
sif (cpu()=="I81341"||cpu()=="I81342"||cpu()=="I81348")
|
|
bitfld.long 0x00 20.--22. " TC[2:0] ,Traffic Class" "TC0,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
|
|
else
|
|
bitfld.long 0x00 20.--22. " TC[2:0] ,Traffic Class" "TC0,TC1,TC2,TC3,TC4,TC5,TC6,TC7"
|
|
endif
|
|
bitfld.long 0x00 15. " TD ,TLP Digest present" "Not present,Present"
|
|
bitfld.long 0x00 12.--13. " ATTR ,Attributes" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14. " EP ,TLP is poisoned" "Not poisoned,Poisoned"
|
|
hexmask.long.word 0x00 1.--9. 1. " LNG[9:1] ,Length [9:1]"
|
|
bitfld.long 0x00 0. " LNG[0] ,Length [0]" "0,1"
|
|
line.long 0x04 "OVMHR1,Outbound Vendor Defined Message Header Register 1"
|
|
hexmask.long.byte 0x04 24.--31. 1. " BUSNO ,Requester ID - Bus number"
|
|
bitfld.long 0x04 19.--23. " DEVNO ,Requester ID - Device Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 16.--18. " FUNO ,Requester ID - Function Number" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " TAG ,Tag - The tag field is undefined for posted requests"
|
|
hexmask.long.byte 0x04 0.--7. 1. " MCODE[7:0] ,Message Code[7:0]"
|
|
line.long 0x08 "OVMHR2,Outbound Vendor Defined Message Header Register 2"
|
|
hexmask.long.word 0x08 16.--31. 1. " DESTID ,Destination ID"
|
|
hexmask.long.word 0x08 0.--15. 1. " VENDID ,Vendor ID"
|
|
line.long 0x0c "OVMHR3,Outbound Vendor Defined Message Header Register 3"
|
|
wgroup.long 0x370++0x3
|
|
line.long 0x0 "OVMPR,Outbound Vendor Defined Message Payload Register"
|
|
group.long 0x380++0xb
|
|
line.long 0x0 "PIE_CSR,PCI Interface Error Control and Status Register"
|
|
bitfld.long 0x00 28.--31. " INID ,Initiator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " GDE ,General Device Error" "No error,Error"
|
|
bitfld.long 0x00 24.--26. " PFN ,PCI Function Number" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " PIEFEP ,PCI Interface Error First Error Pointer" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F,10,11,12,13,14,15,16,17,18,19,1A,1B,1C,1D,1E,1F"
|
|
line.long 0x4 "PIE_STS,PCI Interface Error Status"
|
|
eventfld.long 0x04 31. " RCUR ,Received Completion with Unsupported Request Status" "Not occurred,Occurred"
|
|
eventfld.long 0x04 30. " CWCA ,Received Completion with Completer Abort Status" "Not occurred,Occurred"
|
|
eventfld.long 0x04 29. " PTT ,Poisoned TLP Transmitted Status" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x04 28. " HPE ,Transmit: Header Parity Error detected" "No error,Error"
|
|
eventfld.long 0x04 20. " URE ,Unsupported Request Error Status" "No error,Error"
|
|
eventfld.long 0x04 19. " EC ,ECRC Check Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x04 18. " MT ,Malformed TLP Error" "No error,Error"
|
|
eventfld.long 0x04 17. " RO ,Receiver Overflow" "No error,Error"
|
|
eventfld.long 0x04 16. " UC ,Unexpected Completion Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x04 15. " CA ,Completer Abort Error" "No error,Error"
|
|
eventfld.long 0x04 14. " CT ,Completion Timeout Error" "No error,Error"
|
|
eventfld.long 0x04 13. " FCPE ,Flow Control Protocol Error Status" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x04 12. " PTR ,Poisoned TLP Received" "No error,Error"
|
|
eventfld.long 0x04 4. " DLPE ,Data Link Protocol Error" "No error,Error"
|
|
eventfld.long 0x04 0. " TE ,Training Error" "No error,Error"
|
|
line.long 0x8 "PIE_MSK,PCI Interface Error Mask"
|
|
bitfld.long 0x08 31. " RCUR ,Received Completion with Unsupported Request Mask" "Not occurred,Occurred"
|
|
bitfld.long 0x08 30. " CWCA ,Received Completion with Completer Abort Mask" "Not occurred,Occurred"
|
|
bitfld.long 0x08 29. " PTT ,Poisoned TLP Transmitted Mask" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x08 28. " HPE ,Transmit: Header Parity Error Mask" "No error,Error"
|
|
bitfld.long 0x08 20. " URE ,Unsupported Request Error Status Error Mask" "No error,Error"
|
|
bitfld.long 0x08 19. " EC ,ECRC Check Error Mask" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x08 18. " MT ,Malformed TLP Error Mask" "Not occurred,Occurred"
|
|
bitfld.long 0x08 17. " RO ,Receiver Overflow Error Mask" "No overflow,Overflow"
|
|
bitfld.long 0x08 16. " UC ,Unexpected Completion Error Mask" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x08 15. " CA ,Completer Abort Error Mask" "No abort,Abort"
|
|
bitfld.long 0x08 14. " CT ,Completion Timeout Error Mask" "No timeout,Timeout"
|
|
bitfld.long 0x08 13. " FCPE ,Flow Control Protocol Error Status Error Mask" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x08 12. " PTR ,Poisoned TLP Received Error Mask" "Not occurred,Occurred"
|
|
bitfld.long 0x08 4. " DLPE ,Data Link Protocol Error Mask" "No error,Error"
|
|
bitfld.long 0x08 0. " TE ,Training Error Mask" "No error,Error"
|
|
rgroup.long 0x38c++0x13
|
|
line.long 0x00 "PIE_LOG0,PCI Interface Error Header Log 0"
|
|
line.long 0x04 "PIE_LOG1,PCI Interface Error Header Log 1"
|
|
line.long 0x08 "PIE_LOG2,PCI Interface Error Header Log 2"
|
|
line.long 0x0c "PIE_LOG3,PCI Interface Error Header Log 3"
|
|
line.long 0x10 "PIE_DLOG,PCI Interface Error Descriptor Log"
|
|
bitfld.long 0x10 29.--30. " DMACN ,DMA Channel Number" "0,1,2,3"
|
|
hexmask.long 0x10 0.--28. 1. "ADMA Descriptor Address"
|
|
group.long 0x3B0++0x3
|
|
line.long 0x0 "ATURCR,ATU Reset Control Register"
|
|
bitfld.long 0x00 0. " LDRB ,Link Down Reset Bypass override" "Asserted,Deasserted"
|
|
width 0xb
|
|
tree.end
|
|
tree "Messaging Unit"
|
|
base asd:(0x0:0xFFD80000+0x4000)
|
|
width 0xa
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "IMR0,Inbound Message Register"
|
|
line.long 0x04 "IMR1,Inbound Message Register"
|
|
group.long 0x18++0x07
|
|
line.long 0x00 "OMR0,Outbound Message Register"
|
|
line.long 0x04 "OMR1,Outbound Message Register"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "IDR,Inbound Doorbell Register"
|
|
eventfld.long 0x00 31. " ErrInt ,Error Interrupt" "Disabled,Enabled"
|
|
hexmask.long 0x00 0.--30. 0x01 " NorInt ,Normal Interrupt"
|
|
line.long 0x04 "IISR,Inbound Interrupt Status Register"
|
|
bitfld.long 0x04 31. " CRes ,Coordinated Reset Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 30. " SRes ,Selective Reset Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 29. " MUMTW ,MU MSI-X Table Write Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 6. " IdxReg ,Index Register Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 5. " OFull ,Outbound Free Queue Full Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 4. " IPost ,Inbound Post Queue Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " EDoor ,Error Doorbell Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " IDoor ,Inbound Doorbell Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 1. " Msg1 ,Inbound Message 1 Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 0. " Msg0 ,Inbound Message 0 Interrupt" "No interrupt,Interrupt"
|
|
line.long 0x08 "IIMR,Inbound Interrupt Mask Register"
|
|
bitfld.long 0x08 31. " CRes ,Coordinated Reset Interrupt Mask" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " SRes ,Selective Reset Interrupt Mask" "Disabled,Enabled"
|
|
eventfld.long 0x08 29. " MUMTW ,MU MSI-X Table Write Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 6. " IdxReg ,Index Register Interrupt Mask" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " OFull ,Outbound Free Queue Full Interrupt Mask" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " IPost ,Inbound Post Queue Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " EDoor ,Error Doorbell Interrupt Mask" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " IDoor ,Inbound Doorbell Interrupt Mask" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " Msg1 ,Inbound Message 1 Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " Msg0 ,Inbound Message 0 Interrupt Mask" "Disabled,Enabled"
|
|
group.long 0x2c++0x0b
|
|
line.long 0x00 "ODR,Outbound Doorbell Register"
|
|
eventfld.long 0x00 31. " PINTD ,PCI Interrupt D" "Asserted,Deasserted"
|
|
eventfld.long 0x00 30. " PINTC ,PCI Interrupt C" "Asserted,Deasserted"
|
|
eventfld.long 0x00 29. " PINTB ,PCI Interrupt B" "Asserted,Deasserted"
|
|
textline " "
|
|
eventfld.long 0x00 28. " PINTA ,PCI Interrupt A" "Asserted,Deasserted"
|
|
eventfld.long 0x00 27. " SW[27] ,Software Interrupt 27" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 26. " SW[26] ,Software Interrupt 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 25. " SW[25] ,Software Interrupt 25" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " SW[24] ,Software Interrupt 24" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 23. " SW[23] ,Software Interrupt 23" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 22. " SW[22] ,Software Interrupt 22" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " SW[21] ,Software Interrupt 21" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " SW[20] ,Software Interrupt 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " SW[19] ,Software Interrupt 19" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " SW[18] ,Software Interrupt 18" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " SW[17] ,Software Interrupt 17" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 16. " SW[16] ,Software Interrupt 16" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 15. " SW[15] ,Software Interrupt 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " SW[14] ,Software Interrupt 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 13. " SW[13] ,Software Interrupt 13" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " SW[12] ,Software Interrupt 12" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " SW[11] ,Software Interrupt 11" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SW[10] ,Software Interrupt 10" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " SW[9] ,Software Interrupt 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " SW[8] ,Software Interrupt 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " SW[7] ,Software Interrupt 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " SW[6] ,Software Interrupt 6" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " SW[5] ,Software Interrupt 5" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " SW[4] ,Software Interrupt 4" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " SW[3] ,Software Interrupt 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " SW[2] ,Software Interrupt 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " SW[1] ,Software Interrupt 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " SW[0] ,Software Interrupt 0" "No interrupt,Interrupt"
|
|
line.long 0x04 "OISR,Outbound Interrupt Status Register"
|
|
bitfld.long 0x04 31. " FIntP ,Firmware Interrupt Pending" "Not pending,Pending"
|
|
bitfld.long 0x04 7. " PCI-D ,PCI Interrupt D" "Not pending,Pending"
|
|
bitfld.long 0x04 6. " PCI-C ,PCI Interrupt C" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 5. " PCI-B ,PCI Interrupt B" "Not pending,Pending"
|
|
bitfld.long 0x04 4. " PCI-A ,PCI Interrupt A" "Not pending,Pending"
|
|
bitfld.long 0x04 3. " OPost ,Outbound Post Queue Interrupt" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 2. " ODoor ,Outbound Doorbell Interrupt" "Not pending,Pending"
|
|
eventfld.long 0x04 1. " Msg1 ,Outbound Message 1 Interrupt" "Not pending,Pending"
|
|
eventfld.long 0x04 0. " Msg0 ,Outbound Message 0 Interrupt" "Not pending,Pending"
|
|
line.long 0x08 "OIMR,Outbound Interrupt Mask Register"
|
|
bitfld.long 0x08 31. " FIntP ,Firmware Interrupt Pending Mask" "Not masked,Masked"
|
|
bitfld.long 0x08 7. " PCI-D ,PCI Interrupt D Mask" "Not masked,Masked"
|
|
bitfld.long 0x08 6. " PCI-C ,PCI Interrupt C Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 5. " PCI-B ,PCI Interrupt B Mask" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " PCI-A ,PCI Interrupt A Mask" "Not masked,Masked"
|
|
bitfld.long 0x08 3. " OPost ,Outbound Post Queue Interrupt Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 2. " ODoor ,Outbound Doorbell Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x08 1. " Msg1 ,Outbound Message 1 Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " Msg0 ,Outbound Message 0 Interrupt Mask" "Not masked,Masked"
|
|
group.long 0x38++0x7
|
|
line.long 0x0 "IRCSR,Inbound Reset Control and Status Register"
|
|
bitfld.long 0x0 0. " SR ,Selective Reset" "No reset,Reset"
|
|
bitfld.long 0x0 1. " CR ,Coordinated Reset" "No reset,Reset"
|
|
line.long 0x4 "ORCSR,Outbound Reset Control and Status Register"
|
|
bitfld.long 0x04 31. " FI ,Firmware Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " MF ,Multi-Function" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " GRO ,Global Reset Outstanding" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 2. " RCC ,Reset Coordination Complete" "Not completed,Completed"
|
|
bitfld.long 0x04 0. " RM ,Reset Master" "No reset,Reset"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "MIMR,MSI Inbound Message Register"
|
|
hexmask.long.byte 0x0 0.--6. 1. " INTVEC ,Interrupt Vector"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.long 0x0 15. " CSB ,Core Select Bit" "CoreID0,CoreID1"
|
|
else
|
|
bitfld.long 0x0 15. " CSB ,Core Select Bit" "CoreID0,Reserved"
|
|
endif
|
|
group.long 0x50++0x7
|
|
line.long 0x0 "MUCR,MU Configuration Register"
|
|
bitfld.long 0x0 16.--19. " UQBA ,Upper Queue Base Address" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F"
|
|
bitfld.long 0x0 1.--5. " CQS ,Circular Queue Size" "Reserved,4K entries,8K entries,Reserved,16K entries,Reserved,Reserved,Reserved,32K entries,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64K entries,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
|
|
bitfld.long 0x0 0. " CQEN ,Circular Queue Enable" "Disabled,Enabled"
|
|
line.long 0x4 "QBAR,Queue Base Address Register"
|
|
hexmask.long 0x4 20.--31. 0x100000 " QBA ,Queue Base Address"
|
|
group.long 0x60++0x1f
|
|
line.long 0x0 "IFHPR,Inbound Free Head Pointer Register"
|
|
hexmask.long 0x0 20.--31. 0x100000 " QBA ,Queue Base Address"
|
|
hexmask.long.tbyte 0x0 2.--19. 1. " IFHP ,Inbound Free Head Pointer"
|
|
line.long 0x04 "IFTPR,Inbound Free Tail Pointer Register"
|
|
hexmask.long 0x04 20.--31. 0x100000 " QBA ,Queue Base Address"
|
|
hexmask.long.tbyte 0x04 2.--19. 1. " IFTP ,Inbound Free Tail Pointer"
|
|
line.long 0x08 "IPHPR,Inbound Post Head Pointer Register"
|
|
hexmask.long. 0x8 20.--31. 0x100000 " QBA ,Queue Base Address"
|
|
hexmask.long.tbyte 0x8 2.--19. 1. " IFHP ,Inbound Post Head Pointer"
|
|
line.long 0x0c "IPTPR,Inbound Post Tail Pointer Register"
|
|
hexmask.long 0x0c 20.--31. 0x100000 " QBA ,Queue Base Address"
|
|
hexmask.long.tbyte 0x0c 2.--19. 1. " IFTP ,Inbound Post Tail Pointer"
|
|
line.long 0x10 "OFHPR,Outbound Free Head Pointer Register"
|
|
hexmask.long 0x10 20.--31. 0x100000 " QBA ,Queue Base Address"
|
|
hexmask.long.tbyte 0x10 2.--19. 1. " IFHP ,Outbound Free Head Pointer"
|
|
line.long 0x14 "OFTPR,Outbound Free Tail Pointer Register"
|
|
hexmask.long 0x14 20.--31. 0x100000 " QBA ,Queue Base Address"
|
|
hexmask.long.tbyte 0x14 2.--19. 1. " IFTP ,Outbound Free Tail Pointer"
|
|
line.long 0x18 "OPHPR,Outbound Post Head Pointer Register"
|
|
hexmask.long 0x18 20.--31. 0x100000 " QBA ,Queue Base Address"
|
|
hexmask.long.tbyte 0x18 2.--19. 1. " IFHP ,Outbound Post Head Pointer"
|
|
line.long 0x1c "OPTPR,Outbound Post Tail Pointer Register"
|
|
hexmask.long 0x1c 20.--31. 0x100000 " QBA ,Queue Base Address"
|
|
hexmask.long.tbyte 0x1c 2.--19. 1. " IFTP ,Outbound Post Tail Pointer"
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x0 "IAR,Index Address Register"
|
|
hexmask.long.word 0x0 2.--11. 0x4 " IDXADR ,Index Address"
|
|
group.long 0x84++0x7
|
|
line.long 0x0 "MUBAR,MU Base Address Register"
|
|
hexmask.long 0x0 13.--31. 0x2000 " MUBA ,MU Base Address"
|
|
line.long 0x04 "MUUBAR,MU Upper Base Address Register"
|
|
bitfld.long 0x4 0.--3. " MUUBA ,MU Upper Base Address" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F"
|
|
tree "MU MSI-X Table Message"
|
|
textline " "
|
|
group.long 0x1000++0xF
|
|
line.long 0x0 "M_MT_MAR0,MU MSI-X Table Message Address Register 0"
|
|
hexmask.long 0x0 2.--31. 0x4 " MLA ,Message Lower Address"
|
|
line.long 0x4 "M_MT_MUAR0,MU MSI-X Table Message Upper Address Register 0"
|
|
line.long 0x8 "M_MT_MDR0,MU MSI-X Table Message Data Register 0"
|
|
line.long 0xc "M_MT_MVCR0,MU MSI-X Table Message Vector Control Register 0"
|
|
bitfld.long 0xc 0. " MVC ,Message Vector Control" "Enabled,Disabled"
|
|
group.long 0x1010++0xF
|
|
line.long 0x0 "M_MT_MAR1,MU MSI-X Table Message Address Register 1"
|
|
hexmask.long 0x0 2.--31. 0x4 " MLA ,Message Lower Address"
|
|
line.long 0x4 "M_MT_MUAR1,MU MSI-X Table Message Upper Address Register 1"
|
|
line.long 0x8 "M_MT_MDR1,MU MSI-X Table Message Data Register 1"
|
|
line.long 0xc "M_MT_MVCR1,MU MSI-X Table Message Vector Control Register 1"
|
|
bitfld.long 0xc 0. " MVC ,Message Vector Control" "Enabled,Disabled"
|
|
group.long 0x1020++0xF
|
|
line.long 0x0 "M_MT_MAR2,MU MSI-X Table Message Address Register 2"
|
|
hexmask.long 0x0 2.--31. 0x4 " MLA ,Message Lower Address"
|
|
line.long 0x4 "M_MT_MUAR2,MU MSI-X Table Message Upper Address Register 2"
|
|
line.long 0x8 "M_MT_MDR2,MU MSI-X Table Message Data Register 2"
|
|
line.long 0xc "M_MT_MVCR2,MU MSI-X Table Message Vector Control Register 2"
|
|
bitfld.long 0xc 0. " MVC ,Message Vector Control" "Enabled,Disabled"
|
|
group.long 0x1030++0xF
|
|
line.long 0x0 "M_MT_MAR3,MU MSI-X Table Message Address Register 3"
|
|
hexmask.long 0x0 2.--31. 0x4 " MLA ,Message Lower Address"
|
|
line.long 0x4 "M_MT_MUAR3,MU MSI-X Table Message Upper Address Register 3"
|
|
line.long 0x8 "M_MT_MDR3,MU MSI-X Table Message Data Register 3"
|
|
line.long 0xc "M_MT_MVCR3,MU MSI-X Table Message Vector Control Register 3"
|
|
bitfld.long 0xc 0. " MVC ,Message Vector Control" "Enabled,Disabled"
|
|
group.long 0x1040++0xF
|
|
line.long 0x0 "M_MT_MAR4,MU MSI-X Table Message Address Register 4"
|
|
hexmask.long 0x0 2.--31. 0x4 " MLA ,Message Lower Address"
|
|
line.long 0x4 "M_MT_MUAR4,MU MSI-X Table Message Upper Address Register 4"
|
|
line.long 0x8 "M_MT_MDR4,MU MSI-X Table Message Data Register 4"
|
|
line.long 0xc "M_MT_MVCR4,MU MSI-X Table Message Vector Control Register 4"
|
|
bitfld.long 0xc 0. " MVC ,Message Vector Control" "Enabled,Disabled"
|
|
group.long 0x1050++0xF
|
|
line.long 0x0 "M_MT_MAR5,MU MSI-X Table Message Address Register 5"
|
|
hexmask.long 0x0 2.--31. 0x4 " MLA ,Message Lower Address"
|
|
line.long 0x4 "M_MT_MUAR5,MU MSI-X Table Message Upper Address Register 5"
|
|
line.long 0x8 "M_MT_MDR5,MU MSI-X Table Message Data Register 5"
|
|
line.long 0xc "M_MT_MVCR5,MU MSI-X Table Message Vector Control Register 5"
|
|
bitfld.long 0xc 0. " MVC ,Message Vector Control" "Enabled,Disabled"
|
|
group.long 0x1060++0xF
|
|
line.long 0x0 "M_MT_MAR6,MU MSI-X Table Message Address Register 6"
|
|
hexmask.long 0x0 2.--31. 0x4 " MLA ,Message Lower Address"
|
|
line.long 0x4 "M_MT_MUAR6,MU MSI-X Table Message Upper Address Register 6"
|
|
line.long 0x8 "M_MT_MDR6,MU MSI-X Table Message Data Register 6"
|
|
line.long 0xc "M_MT_MVCR6,MU MSI-X Table Message Vector Control Register 6"
|
|
bitfld.long 0xc 0. " MVC ,Message Vector Control" "Enabled,Disabled"
|
|
group.long 0x1070++0xF
|
|
line.long 0x0 "M_MT_MAR7,MU MSI-X Table Message Address Register 7"
|
|
hexmask.long 0x0 2.--31. 0x4 " MLA ,Message Lower Address"
|
|
line.long 0x4 "M_MT_MUAR7,MU MSI-X Table Message Upper Address Register 7"
|
|
line.long 0x8 "M_MT_MDR7,MU MSI-X Table Message Data Register 7"
|
|
line.long 0xc "M_MT_MVCR7,MU MSI-X Table Message Vector Control Register 7"
|
|
bitfld.long 0xc 0. " MVC ,Message Vector Control" "Enabled,Disabled"
|
|
tree.end
|
|
textline " "
|
|
width 23.
|
|
rgroup.long 0x1800++0x3
|
|
line.long 0x0 "M_MPBAR,MU MSI-X Pending Bits Array Register"
|
|
bitfld.long 0x0 7. " PBA7 ,Pending Bit 7" "Not pending,Pending"
|
|
bitfld.long 0x0 6. " PBA6 ,Pending Bit 6" "Not pending,Pending"
|
|
bitfld.long 0x0 5. " PBA5 ,Pending Bit 5" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0 4. " PBA4 ,Pending Bit 4" "Not pending,Pending"
|
|
bitfld.long 0x0 3. " PBA3 ,Pending Bit 3" "Not pending,Pending"
|
|
bitfld.long 0x0 2. " PBA2 ,Pending Bit 2" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0 1. " PBA1 ,Pending Bit 1" "Not pending,Pending"
|
|
bitfld.long 0x0 0. " PBA0 ,Pending Bit 0" "Not pending,Pending"
|
|
rgroup.byte 0xa0++0x1
|
|
line.byte 0x0 "MSI_Cap_ID,MSI Capability Identifier Register"
|
|
line.byte 0x1 "MSI_Next_Ptr,MSI Next Item Pointer Register"
|
|
group.word 0xa2++0x1
|
|
line.word 0x0 "Message_Control,Message Control Register"
|
|
bitfld.word 0x00 7. " S64A ,64-bit Address Support" "Not supported,Supported"
|
|
bitfld.word 0x00 4.--6. " MME ,Multiple Message Enable" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x00 1.--3. " MMC ,Multiple Message Capable" "Not capable,Capable,Not capable,Not capable,Not capable,Not capable,Not capable,Not capable"
|
|
textline " "
|
|
bitfld.word 0x00 0. " MSIE ,MSI Enable" "Disabled,Enabled"
|
|
group.long 0xa4++0x7
|
|
line.long 0x0 "Message_Address,Message Address Register"
|
|
hexmask.long 0x0 2.--31. 0x4 " MESADR ,Message Address"
|
|
line.long 0x4 "Message_Upper_Address,Message Upper Address Register"
|
|
group.word 0xac++0x1
|
|
line.word 0x0 "Message_Data,Message Data Register"
|
|
group.byte 0xb0++0x1
|
|
line.byte 0x0 "MSI-X_Cap_ID,MSI-X_Capability Identifier Register"
|
|
line.byte 0x1 "MSI-X_Next_Item_Ptr,MSI-X Next Item Pointer Register"
|
|
group.word 0xb2++0x1
|
|
line.word 0x0 "MSI-X_MCR,MSI-X Message Control Register"
|
|
bitfld.word 0x0 15. " MSIXEN ,MSI-X Enable" "Disabled,Enabled"
|
|
bitfld.word 0x0 14. " FUNMASK ,Function Mask" "Not masked,Masked"
|
|
hexmask.word 0x0 0.--10. 1. " MSIXTS ,MSI-X Table Size"
|
|
group.long 0xb4++0xb
|
|
line.long 0x0 "MSI-X_Table_Offset,MSI-X Table Offset Register"
|
|
hexmask.long.tbyte 0x0 13.--31. 0x1 " MSIXTO1 ,MSI-X Table Offset1"
|
|
hexmask.long.word 0x0 3.--12. 0x1 " MSIXTO2 ,MSI-X Table Offset2"
|
|
bitfld.long 0x0 0.--2. " BIR ,MSI-X Table BAR Indication Register" "0x10,0x14,0x18,0x1c,0x20,0x24,Reserved,Reserved"
|
|
line.long 0x4 "MSI-X_PBA_Offset,MSI-X Pending Bit Array Offset Register"
|
|
hexmask.long.tbyte 0x04 13.--31. 0x1 " MSIXTO1 ,MSI-X Table Offset1"
|
|
hexmask.long.word 0x04 3.--12. 0x1 " MSIXTO2 ,MSI-X Table Offset2"
|
|
bitfld.long 0x04 0.--2. " BIR ,MSI-X Table BAR Indication Register" "0x10,0x14,0x18,0x1c,0x20,0x24,Reserved,Reserved"
|
|
line.long 0x8 "MMCRx,MU MSI-X Control Register X"
|
|
bitfld.long 0x08 0. " MMSMV ,MU MSI-X Single Message Vector" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree.open "ADMA (Application DMA)"
|
|
tree "ADMA 0"
|
|
base asd:(0x0:0xFFD80000+0x000)
|
|
width 0x9
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "ACCR0,ADMA Channel Control Register 0"
|
|
bitfld.long 0x00 29. " IOSEL ,I/O Interface Select:" "PCI-X,PCI Express"
|
|
bitfld.long 0x00 24.--27. " UCRCADDR ,Upper CRC Address" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " UNDADDR ,Upper Next Descriptor Address" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F"
|
|
bitfld.long 0x00 19. " ENDIAN ,Endian Mode Selector (Host | Local)" "Little | Big,Big | Little"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CR ,Chain Resume" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ADMAEN ,ADMA Enable Transfers" "Disabled,Enabled"
|
|
line.long 0x4 "ACSR0,ADMA Channel Status Register 0"
|
|
bitfld.long 0x04 13. " ADMAAF ,ADMA Active Flag" "Active,Idle"
|
|
eventfld.long 0x04 12. " EOT ,End of Transfer Interrupt Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x04 11. " EOC ,End of Chain Interrupt Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x04 9. " INTMA ,Internal Interface Parity Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x04 5. " MA ,MCU Port Abort Flag" "No error,Error"
|
|
eventfld.long 0x04 4. " TA ,Internal Bus Target Abort Flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x04 3. " INBUSMASTA ,Internal Bus Master Abort Flag" "No error,Error"
|
|
eventfld.long 0x04 2. " ZERORESERR ,Zero Result Buffer Error Detected" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x04 1. " PQZERORESERR ,P+Q Zero Result Buffer Error Detected" "No error,Error"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "ADAR0,ADMA Descriptor Address Register 0"
|
|
hexmask.long 0x0 5.--31. 0x20 " CDESADDR ,Current Descriptor Address"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "IIPCR0,Internal Interface Parity Control Register 0"
|
|
bitfld.long 0x0 0. " IIPARITY ,Internal Interface Parity Enabled" "Disabled,Enabled"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "ANDAR0 ,ADMA Next Descriptor Address Register 0"
|
|
hexmask.long 0x0 5.--31. 0x20 " NDESADDR ,Next Descriptor Address"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x0 "ADCR0,ADMA Descriptor Control Register 0"
|
|
bitfld.long 0x00 31. " NOSNOOP ,No Snoop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RELAXORD ,Relaxed Ordering Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PTRANSDIS ,P Transfer Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 18. " PQTRANS ,P+Q Transfer Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DUALXOR ,Dual XOR Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PQUPDATX ,P+Q Update Transfer Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ENDIANSWAP ,Endian Swap Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " STATWRBK ,Status Write Back Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CRCSEEDF ,CRC Seed Fetch Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " CRCTXDIS ,CRC Transfer Disable" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CRCGEN ,CRC Generation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MEMBLKFILL ,Memory Block Fill Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ZERORES ,Zero Result Buffer Check Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--6. " SOURCE ,Source Selection" "SAR1:0,SAR:0,SAR2:0,SAR3:0,SAR4:0,SAR5:0,SAR6:0,SAR7:0,SAR8:0,SAR9:0,SAR10:0,SAR11:0,SAR12:0,SAR13:0,SAR14:0,SAR15:0"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " TXDIR ,Transfer Direction" "Host -> Memory,Memory -> Host,Bus -> Memory,Memory -> Bus"
|
|
textline " "
|
|
bitfld.long 0x00 0. " INTEN ,Interrupt Enable" "Disabled,Enabled"
|
|
rgroup.long 0x2c++0xf
|
|
line.long 0x0 "CARMDQ0,CRC Address/Memory Block Fill Data Register 0"
|
|
line.long 0x4 "ABCR0,ADMA Byte Count Register 0"
|
|
bitfld.long 0x04 31. " TXDONE ,Transfer Complete" "Not completed,Completed"
|
|
bitfld.long 0x04 30. " ZERORESERR ,Zero Result Buffer Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 29. " ZERORESERRQ ,Zero Result Buffer Error Q" "No error,Error"
|
|
bitfld.long 0x04 24.--26. " HOSTINTFUN ,Host I/O Interface Function Number" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " BYTE_COUNT ,Byte Count"
|
|
line.long 0x8 "DLADR,Destination Lower Address Register"
|
|
line.long 0xc "DUADR,Destination Upper Address Register"
|
|
rgroup.long 0x3c++0x7f
|
|
line.long 0x0 "SLAR0,Source Lower Address Register 0"
|
|
line.long 0x8 "SLAR1,Source Lower Address Register 1"
|
|
line.long 0x10 "SLAR2,Source Lower Address Register 2"
|
|
line.long 0x18 "SLAR3,Source Lower Address Register 3"
|
|
line.long 0x20 "SLAR4,Source Lower Address Register 4"
|
|
line.long 0x28 "SLAR5,Source Lower Address Register 5"
|
|
line.long 0x30 "SLAR6,Source Lower Address Register 6"
|
|
line.long 0x38 "SLAR7,Source Lower Address Register 7"
|
|
line.long 0x40 "SLAR8,Source Lower Address Register 8"
|
|
line.long 0x48 "SLAR9,Source Lower Address Register 9"
|
|
line.long 0x50 "SLAR10,Source Lower Address Register 10"
|
|
line.long 0x58 "SLAR11,Source Lower Address Register 11"
|
|
line.long 0x60 "SLAR12,Source Lower Address Register 12"
|
|
line.long 0x68 "SLAR13,Source Lower Address Register 13"
|
|
line.long 0x70 "SLAR14,Source Lower Address Register 14"
|
|
line.long 0x78 "SLAR15,Source Lower Address Register 15"
|
|
line.long 0x4 "SUAR0,Source Upper Address Register 0"
|
|
hexmask.long.byte 0x4 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0xC "SUAR1,Source Upper Address Register 1"
|
|
hexmask.long.byte 0xC 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0xC 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x14 "SUAR2,Source Upper Address Register 2"
|
|
hexmask.long.byte 0x14 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x1C "SUAR3,Source Upper Address Register 3"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x1C 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x24 "SUAR4,Source Upper Address Register 4"
|
|
hexmask.long.byte 0x24 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x24 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x2C "SUAR5,Source Upper Address Register 5"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x2C 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x34 "SUAR6,Source Upper Address Register 6"
|
|
hexmask.long.byte 0x34 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x34 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x3C "SUAR7,Source Upper Address Register 7"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x3C 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x44 "SUAR8,Source Upper Address Register 8"
|
|
hexmask.long.byte 0x44 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x44 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x4C "SUAR9,Source Upper Address Register 9"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x4C 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x54 "SUAR10,Source Upper Address Register 10"
|
|
hexmask.long.byte 0x54 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x54 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x5C "SUAR11,Source Upper Address Register 11"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x5C 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x64 "SUAR12,Source Upper Address Register 12"
|
|
hexmask.long.byte 0x64 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x64 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x6C "SUAR13,Source Upper Address Register 13"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x6C 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x74 "SUAR14,Source Upper Address Register 14"
|
|
hexmask.long.byte 0x74 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x74 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x7C "SUAR15,Source Upper Address Register 15"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x7C 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
width 0xb
|
|
tree.end
|
|
tree "ADMA 1"
|
|
base asd:(0x0:0xFFD80000+0x200)
|
|
width 0x9
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "ACCR1,ADMA Channel Control Register 1"
|
|
bitfld.long 0x00 29. " IOSEL ,I/O Interface Select:" "PCI-X,PCI Express"
|
|
bitfld.long 0x00 24.--27. " UCRCADDR ,Upper CRC Address" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " UNDADDR ,Upper Next Descriptor Address" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F"
|
|
bitfld.long 0x00 19. " ENDIAN ,Endian Mode Selector (Host | Local)" "Little | Big,Big | Little"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CR ,Chain Resume" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ADMAEN ,ADMA Enable Transfers" "Disabled,Enabled"
|
|
line.long 0x4 "ACSR1,ADMA Channel Status Register 1"
|
|
bitfld.long 0x04 13. " ADMAAF ,ADMA Active Flag" "Active,Idle"
|
|
eventfld.long 0x04 12. " EOT ,End of Transfer Interrupt Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x04 11. " EOC ,End of Chain Interrupt Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x04 9. " INTMA ,Internal Interface Parity Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x04 5. " MA ,MCU Port Abort Flag" "No error,Error"
|
|
eventfld.long 0x04 4. " TA ,Internal Bus Target Abort Flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x04 3. " INBUSMASTA ,Internal Bus Master Abort Flag" "No error,Error"
|
|
eventfld.long 0x04 2. " ZERORESERR ,Zero Result Buffer Error Detected" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x04 1. " PQZERORESERR ,P+Q Zero Result Buffer Error Detected" "No error,Error"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "ADAR1,ADMA Descriptor Address Register 1"
|
|
hexmask.long 0x0 5.--31. 0x20 " CDESADDR ,Current Descriptor Address"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "IIPCR1,Internal Interface Parity Control Register 1"
|
|
bitfld.long 0x0 0. " IIPARITY ,Internal Interface Parity Enabled" "Disabled,Enabled"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "ANDAR1 ,ADMA Next Descriptor Address Register 1"
|
|
hexmask.long 0x0 5.--31. 0x20 " NDESADDR ,Next Descriptor Address"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x0 "ADCR1,ADMA Descriptor Control Register 1"
|
|
bitfld.long 0x00 31. " NOSNOOP ,No Snoop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RELAXORD ,Relaxed Ordering Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PTRANSDIS ,P Transfer Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 18. " PQTRANS ,P+Q Transfer Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DUALXOR ,Dual XOR Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PQUPDATX ,P+Q Update Transfer Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ENDIANSWAP ,Endian Swap Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " STATWRBK ,Status Write Back Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CRCSEEDF ,CRC Seed Fetch Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " CRCTXDIS ,CRC Transfer Disable" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CRCGEN ,CRC Generation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MEMBLKFILL ,Memory Block Fill Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ZERORES ,Zero Result Buffer Check Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--6. " SOURCE ,Source Selection" "SAR1:0,SAR:0,SAR2:0,SAR3:0,SAR4:0,SAR5:0,SAR6:0,SAR7:0,SAR8:0,SAR9:0,SAR10:0,SAR11:0,SAR12:0,SAR13:0,SAR14:0,SAR15:0"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " TXDIR ,Transfer Direction" "Host -> Memory,Memory -> Host,Bus -> Memory,Memory -> Bus"
|
|
textline " "
|
|
bitfld.long 0x00 0. " INTEN ,Interrupt Enable" "Disabled,Enabled"
|
|
rgroup.long 0x2c++0xf
|
|
line.long 0x0 "CARMDQ1,CRC Address/Memory Block Fill Data Register 1"
|
|
line.long 0x4 "ABCR1,ADMA Byte Count Register 1"
|
|
bitfld.long 0x04 31. " TXDONE ,Transfer Complete" "Not completed,Completed"
|
|
bitfld.long 0x04 30. " ZERORESERR ,Zero Result Buffer Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 29. " ZERORESERRQ ,Zero Result Buffer Error Q" "No error,Error"
|
|
bitfld.long 0x04 24.--26. " HOSTINTFUN ,Host I/O Interface Function Number" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " BYTE_COUNT ,Byte Count"
|
|
line.long 0x8 "DLADR,Destination Lower Address Register"
|
|
line.long 0xc "DUADR,Destination Upper Address Register"
|
|
rgroup.long 0x3c++0x7f
|
|
line.long 0x0 "SLAR0,Source Lower Address Register 0"
|
|
line.long 0x8 "SLAR1,Source Lower Address Register 1"
|
|
line.long 0x10 "SLAR2,Source Lower Address Register 2"
|
|
line.long 0x18 "SLAR3,Source Lower Address Register 3"
|
|
line.long 0x20 "SLAR4,Source Lower Address Register 4"
|
|
line.long 0x28 "SLAR5,Source Lower Address Register 5"
|
|
line.long 0x30 "SLAR6,Source Lower Address Register 6"
|
|
line.long 0x38 "SLAR7,Source Lower Address Register 7"
|
|
line.long 0x40 "SLAR8,Source Lower Address Register 8"
|
|
line.long 0x48 "SLAR9,Source Lower Address Register 9"
|
|
line.long 0x50 "SLAR10,Source Lower Address Register 10"
|
|
line.long 0x58 "SLAR11,Source Lower Address Register 11"
|
|
line.long 0x60 "SLAR12,Source Lower Address Register 12"
|
|
line.long 0x68 "SLAR13,Source Lower Address Register 13"
|
|
line.long 0x70 "SLAR14,Source Lower Address Register 14"
|
|
line.long 0x78 "SLAR15,Source Lower Address Register 15"
|
|
line.long 0x4 "SUAR0,Source Upper Address Register 0"
|
|
hexmask.long.byte 0x4 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0xC "SUAR1,Source Upper Address Register 1"
|
|
hexmask.long.byte 0xC 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0xC 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x14 "SUAR2,Source Upper Address Register 2"
|
|
hexmask.long.byte 0x14 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x1C "SUAR3,Source Upper Address Register 3"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x1C 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x24 "SUAR4,Source Upper Address Register 4"
|
|
hexmask.long.byte 0x24 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x24 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x2C "SUAR5,Source Upper Address Register 5"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x2C 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x34 "SUAR6,Source Upper Address Register 6"
|
|
hexmask.long.byte 0x34 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x34 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x3C "SUAR7,Source Upper Address Register 7"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x3C 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x44 "SUAR8,Source Upper Address Register 8"
|
|
hexmask.long.byte 0x44 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x44 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x4C "SUAR9,Source Upper Address Register 9"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x4C 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x54 "SUAR10,Source Upper Address Register 10"
|
|
hexmask.long.byte 0x54 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x54 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x5C "SUAR11,Source Upper Address Register 11"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x5C 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x64 "SUAR12,Source Upper Address Register 12"
|
|
hexmask.long.byte 0x64 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x64 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x6C "SUAR13,Source Upper Address Register 13"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x6C 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x74 "SUAR14,Source Upper Address Register 14"
|
|
hexmask.long.byte 0x74 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x74 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x7C "SUAR15,Source Upper Address Register 15"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x7C 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
width 0xb
|
|
tree.end
|
|
tree "ADMA 2"
|
|
base asd:(0x0:0xFFD80000+0x400)
|
|
width 0x9
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "ACCR2,ADMA Channel Control Register 2"
|
|
bitfld.long 0x00 29. " IOSEL ,I/O Interface Select:" "PCI-X,PCI Express"
|
|
bitfld.long 0x00 24.--27. " UCRCADDR ,Upper CRC Address" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " UNDADDR ,Upper Next Descriptor Address" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F"
|
|
bitfld.long 0x00 19. " ENDIAN ,Endian Mode Selector (Host | Local)" "Little | Big,Big | Little"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CR ,Chain Resume" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ADMAEN ,ADMA Enable Transfers" "Disabled,Enabled"
|
|
line.long 0x4 "ACSR2,ADMA Channel Status Register 2"
|
|
bitfld.long 0x04 13. " ADMAAF ,ADMA Active Flag" "Active,Idle"
|
|
eventfld.long 0x04 12. " EOT ,End of Transfer Interrupt Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x04 11. " EOC ,End of Chain Interrupt Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x04 9. " INTMA ,Internal Interface Parity Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x04 5. " MA ,MCU Port Abort Flag" "No error,Error"
|
|
eventfld.long 0x04 4. " TA ,Internal Bus Target Abort Flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x04 3. " INBUSMASTA ,Internal Bus Master Abort Flag" "No error,Error"
|
|
eventfld.long 0x04 2. " ZERORESERR ,Zero Result Buffer Error Detected" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x04 1. " PQZERORESERR ,P+Q Zero Result Buffer Error Detected" "No error,Error"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "ADAR2,ADMA Descriptor Address Register 2"
|
|
hexmask.long 0x0 5.--31. 0x20 " CDESADDR ,Current Descriptor Address"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "IIPCR2,Internal Interface Parity Control Register 2"
|
|
bitfld.long 0x0 0. " IIPARITY ,Internal Interface Parity Enabled" "Disabled,Enabled"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "ANDAR2 ,ADMA Next Descriptor Address Register 2"
|
|
hexmask.long 0x0 5.--31. 0x20 " NDESADDR ,Next Descriptor Address"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x0 "ADCR2,ADMA Descriptor Control Register 2"
|
|
bitfld.long 0x00 31. " NOSNOOP ,No Snoop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RELAXORD ,Relaxed Ordering Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PTRANSDIS ,P Transfer Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 18. " PQTRANS ,P+Q Transfer Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DUALXOR ,Dual XOR Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PQUPDATX ,P+Q Update Transfer Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ENDIANSWAP ,Endian Swap Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " STATWRBK ,Status Write Back Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CRCSEEDF ,CRC Seed Fetch Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " CRCTXDIS ,CRC Transfer Disable" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CRCGEN ,CRC Generation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MEMBLKFILL ,Memory Block Fill Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ZERORES ,Zero Result Buffer Check Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--6. " SOURCE ,Source Selection" "SAR1:0,SAR:0,SAR2:0,SAR3:0,SAR4:0,SAR5:0,SAR6:0,SAR7:0,SAR8:0,SAR9:0,SAR10:0,SAR11:0,SAR12:0,SAR13:0,SAR14:0,SAR15:0"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " TXDIR ,Transfer Direction" "Host -> Memory,Memory -> Host,Bus -> Memory,Memory -> Bus"
|
|
textline " "
|
|
bitfld.long 0x00 0. " INTEN ,Interrupt Enable" "Disabled,Enabled"
|
|
rgroup.long 0x2c++0xf
|
|
line.long 0x0 "CARMDQ2,CRC Address/Memory Block Fill Data Register 2"
|
|
line.long 0x4 "ABCR2,ADMA Byte Count Register 2"
|
|
bitfld.long 0x04 31. " TXDONE ,Transfer Complete" "Not completed,Completed"
|
|
bitfld.long 0x04 30. " ZERORESERR ,Zero Result Buffer Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 29. " ZERORESERRQ ,Zero Result Buffer Error Q" "No error,Error"
|
|
bitfld.long 0x04 24.--26. " HOSTINTFUN ,Host I/O Interface Function Number" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " BYTE_COUNT ,Byte Count"
|
|
line.long 0x8 "DLADR,Destination Lower Address Register"
|
|
line.long 0xc "DUADR,Destination Upper Address Register"
|
|
rgroup.long 0x3c++0x7f
|
|
line.long 0x0 "SLAR0,Source Lower Address Register 0"
|
|
line.long 0x8 "SLAR1,Source Lower Address Register 1"
|
|
line.long 0x10 "SLAR2,Source Lower Address Register 2"
|
|
line.long 0x18 "SLAR3,Source Lower Address Register 3"
|
|
line.long 0x20 "SLAR4,Source Lower Address Register 4"
|
|
line.long 0x28 "SLAR5,Source Lower Address Register 5"
|
|
line.long 0x30 "SLAR6,Source Lower Address Register 6"
|
|
line.long 0x38 "SLAR7,Source Lower Address Register 7"
|
|
line.long 0x40 "SLAR8,Source Lower Address Register 8"
|
|
line.long 0x48 "SLAR9,Source Lower Address Register 9"
|
|
line.long 0x50 "SLAR10,Source Lower Address Register 10"
|
|
line.long 0x58 "SLAR11,Source Lower Address Register 11"
|
|
line.long 0x60 "SLAR12,Source Lower Address Register 12"
|
|
line.long 0x68 "SLAR13,Source Lower Address Register 13"
|
|
line.long 0x70 "SLAR14,Source Lower Address Register 14"
|
|
line.long 0x78 "SLAR15,Source Lower Address Register 15"
|
|
line.long 0x4 "SUAR0,Source Upper Address Register 0"
|
|
hexmask.long.byte 0x4 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0xC "SUAR1,Source Upper Address Register 1"
|
|
hexmask.long.byte 0xC 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0xC 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x14 "SUAR2,Source Upper Address Register 2"
|
|
hexmask.long.byte 0x14 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x1C "SUAR3,Source Upper Address Register 3"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x1C 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x24 "SUAR4,Source Upper Address Register 4"
|
|
hexmask.long.byte 0x24 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x24 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x2C "SUAR5,Source Upper Address Register 5"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x2C 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x34 "SUAR6,Source Upper Address Register 6"
|
|
hexmask.long.byte 0x34 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x34 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x3C "SUAR7,Source Upper Address Register 7"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x3C 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x44 "SUAR8,Source Upper Address Register 8"
|
|
hexmask.long.byte 0x44 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x44 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x4C "SUAR9,Source Upper Address Register 9"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x4C 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x54 "SUAR10,Source Upper Address Register 10"
|
|
hexmask.long.byte 0x54 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x54 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x5C "SUAR11,Source Upper Address Register 11"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x5C 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x64 "SUAR12,Source Upper Address Register 12"
|
|
hexmask.long.byte 0x64 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x64 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x6C "SUAR13,Source Upper Address Register 13"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x6C 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x74 "SUAR14,Source Upper Address Register 14"
|
|
hexmask.long.byte 0x74 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x74 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
line.long 0x7C "SUAR15,Source Upper Address Register 15"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " DATAMUL ,Data multiplier"
|
|
hexmask.long.tbyte 0x7C 0.--23. 1. " SUA ,Source Upper Memory Address"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
sif (cpu()=="I81348")
|
|
tree.open "SGPIO (Serial General Purpose Input Output)"
|
|
tree "SGPIO Unit 0"
|
|
base asd:(0x0:0xFFD80000+0x2600)
|
|
width 0xD
|
|
group.long 0x00++0x0f
|
|
line.long 0x00 "SGICR0,SGPIO Interface Control Register 0"
|
|
bitfld.long 0x00 0. " SGPIOFE ,SGPIO 0 Functionality Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SGPBR0,SGPIO Programmable Blink Register 0"
|
|
bitfld.long 0x04 12.--15. " PPBHDT ,Programmable Pattern B High Duration Time" "125,250,375,500,625,750,875,1000,1125,1250,1375,1500,1625,1750,1875,2000"
|
|
bitfld.long 0x04 08.--11. " PPBLDT ,Programmable Pattern B Low Duration Time" "125,250,375,500,625,750,875,1000,1125,1250,1375,1500,1625,1750,1875,2000"
|
|
bitfld.long 0x04 4.--7. " PPAHDT ,Programmable Pattern A High Duration Time" "125,250,375,500,625,750,875,1000,1125,1250,1375,1500,1625,1750,1875,2000"
|
|
bitfld.long 0x04 0.--3. " PPALDT ,Programmable Pattern A Low Duration Time" "125,250,375,500,625,750,875,1000,1125,1250,1375,1500,1625,1750,1875,2000"
|
|
line.long 0x08 "SGSDLR0,SGPIO Start Drive Lower Register 0"
|
|
bitfld.long 0x08 12.--14. " O3SB ,Output 3 Select Bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 8.--10. " O2SB ,Output 2 Select Bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 4.--6. " O1SB ,Output 1 Select Bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 0.--2. " O0SB ,Output 0 Select Bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0c "SGSDUR0,SGPIO Start Drive Upper Register 0"
|
|
bitfld.long 0x0c 12.--14. " O7SB ,Output 7 Select Bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0c 8.--10. " O6SB ,Output 6 Select Bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0c 4.--6. " O5SB ,Output 5 Select Bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0c 0.--2. " O4SB ,Output 4 Select Bits" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x10++0x07
|
|
line.long 0x00 "SGSIDLR0,SGPIO Serial Input Data Lower Register 0"
|
|
bitfld.long 0x00 12.--14. " D3ID ,Drive 3 input data" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " D2ID ,Drive 2 input data" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " D1ID ,Drive 1 input data" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " D0ID ,Drive 0 input data" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "SGSIDUR0,SGPIO Serial Input Data Upper Register 0"
|
|
bitfld.long 0x04 12.--14. " D7ID ,Drive 7 input data" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 8.--10. " D6ID ,Drive 6 input data" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 4.--6. " D5ID ,Drive 5 input data" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. " D4ID ,Drive 4 input data" "0,1,2,3,4,5,6,7"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SGVSCR0,SGPIO Vendor Specific Code Register 0"
|
|
bitfld.long 0x00 0.--3. " VSD ,Vendor Specific data" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F"
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "SGODSR00,SGPIO Output Data Select Register0 0"
|
|
bitfld.long 0x00 11. " OD2JE ,OD2 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " IOD2SI ,Invert OD2 Selected Input" "No effect,Inverted"
|
|
bitfld.long 0x00 8.--9. " OD2IS ,OD2 Input Select" "High,Prog Pattern A,Prog Pattern B,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OD1JE ,OD1 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " IOD1SI ,Invert OD1 Selected Input" "No effect,Invetred"
|
|
bitfld.long 0x00 4.--5. " OD1IS ,OD1 Input Select" "High,Prog Pattern A,Prog Pattern B,Prot Engine Status"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OD0JE ,OD0 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " IOD0SI ,Invert OD0 Selected Input" "No effect,Inverted"
|
|
bitfld.long 0x00 0.--1. " OD0IS ,OD0 Input Select" "High,Prog Pattern A,Prog Pattern B,Prot Engine Activity"
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "SGODSR10,SGPIO Output Data Select Register1 0"
|
|
bitfld.long 0x00 11. " OD2JE ,OD2 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " IOD2SI ,Invert OD2 Selected Input" "No effect,Inverted"
|
|
bitfld.long 0x00 8.--9. " OD2IS ,OD2 Input Select" "High,Prog Pattern A,Prog Pattern B,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OD1JE ,OD1 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " IOD1SI ,Invert OD1 Selected Input" "No effect,Invetred"
|
|
bitfld.long 0x00 4.--5. " OD1IS ,OD1 Input Select" "High,Prog Pattern A,Prog Pattern B,Prot Engine Status"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OD0JE ,OD0 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " IOD0SI ,Invert OD0 Selected Input" "No effect,Inverted"
|
|
bitfld.long 0x00 0.--1. " OD0IS ,OD0 Input Select" "High,Prog Pattern A,Prog Pattern B,Prot Engine Activity"
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "SGODSR20,SGPIO Output Data Select Register2 0"
|
|
bitfld.long 0x00 11. " OD2JE ,OD2 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " IOD2SI ,Invert OD2 Selected Input" "No effect,Inverted"
|
|
bitfld.long 0x00 8.--9. " OD2IS ,OD2 Input Select" "High,Prog Pattern A,Prog Pattern B,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OD1JE ,OD1 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " IOD1SI ,Invert OD1 Selected Input" "No effect,Invetred"
|
|
bitfld.long 0x00 4.--5. " OD1IS ,OD1 Input Select" "High,Prog Pattern A,Prog Pattern B,Prot Engine Status"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OD0JE ,OD0 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " IOD0SI ,Invert OD0 Selected Input" "No effect,Inverted"
|
|
bitfld.long 0x00 0.--1. " OD0IS ,OD0 Input Select" "High,Prog Pattern A,Prog Pattern B,Prot Engine Activity"
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "SGODSR30,SGPIO Output Data Select Register3 0"
|
|
bitfld.long 0x00 11. " OD2JE ,OD2 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " IOD2SI ,Invert OD2 Selected Input" "No effect,Inverted"
|
|
bitfld.long 0x00 8.--9. " OD2IS ,OD2 Input Select" "High,Prog Pattern A,Prog Pattern B,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OD1JE ,OD1 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " IOD1SI ,Invert OD1 Selected Input" "No effect,Invetred"
|
|
bitfld.long 0x00 4.--5. " OD1IS ,OD1 Input Select" "High,Prog Pattern A,Prog Pattern B,Prot Engine Status"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OD0JE ,OD0 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " IOD0SI ,Invert OD0 Selected Input" "No effect,Inverted"
|
|
bitfld.long 0x00 0.--1. " OD0IS ,OD0 Input Select" "High,Prog Pattern A,Prog Pattern B,Prot Engine Activity"
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "SGODSR40,SGPIO Output Data Select Register4 0"
|
|
bitfld.long 0x00 11. " OD2JE ,OD2 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " IOD2SI ,Invert OD2 Selected Input" "No effect,Inverted"
|
|
bitfld.long 0x00 8.--9. " OD2IS ,OD2 Input Select" "High,Prog Pattern A,Prog Pattern B,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OD1JE ,OD1 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " IOD1SI ,Invert OD1 Selected Input" "No effect,Invetred"
|
|
bitfld.long 0x00 4.--5. " OD1IS ,OD1 Input Select" "High,Prog Pattern A,Prog Pattern B,Prot Engine Status"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OD0JE ,OD0 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " IOD0SI ,Invert OD0 Selected Input" "No effect,Inverted"
|
|
bitfld.long 0x00 0.--1. " OD0IS ,OD0 Input Select" "High,Prog Pattern A,Prog Pattern B,Prot Engine Activity"
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "SGODSR50,SGPIO Output Data Select Register5 0"
|
|
bitfld.long 0x00 11. " OD2JE ,OD2 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " IOD2SI ,Invert OD2 Selected Input" "No effect,Inverted"
|
|
bitfld.long 0x00 8.--9. " OD2IS ,OD2 Input Select" "High,Prog Pattern A,Prog Pattern B,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OD1JE ,OD1 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " IOD1SI ,Invert OD1 Selected Input" "No effect,Invetred"
|
|
bitfld.long 0x00 4.--5. " OD1IS ,OD1 Input Select" "High,Prog Pattern A,Prog Pattern B,Prot Engine Status"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OD0JE ,OD0 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " IOD0SI ,Invert OD0 Selected Input" "No effect,Inverted"
|
|
bitfld.long 0x00 0.--1. " OD0IS ,OD0 Input Select" "High,Prog Pattern A,Prog Pattern B,Prot Engine Activity"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "SGODSR60,SGPIO Output Data Select Register6 0"
|
|
bitfld.long 0x00 11. " OD2JE ,OD2 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " IOD2SI ,Invert OD2 Selected Input" "No effect,Inverted"
|
|
bitfld.long 0x00 8.--9. " OD2IS ,OD2 Input Select" "High,Prog Pattern A,Prog Pattern B,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OD1JE ,OD1 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " IOD1SI ,Invert OD1 Selected Input" "No effect,Invetred"
|
|
bitfld.long 0x00 4.--5. " OD1IS ,OD1 Input Select" "High,Prog Pattern A,Prog Pattern B,Prot Engine Status"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OD0JE ,OD0 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " IOD0SI ,Invert OD0 Selected Input" "No effect,Inverted"
|
|
bitfld.long 0x00 0.--1. " OD0IS ,OD0 Input Select" "High,Prog Pattern A,Prog Pattern B,Prot Engine Activity"
|
|
group.long 0x3C++0x3
|
|
line.long 0x00 "SGODSR70,SGPIO Output Data Select Register7 0"
|
|
bitfld.long 0x00 11. " OD2JE ,OD2 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " IOD2SI ,Invert OD2 Selected Input" "No effect,Inverted"
|
|
bitfld.long 0x00 8.--9. " OD2IS ,OD2 Input Select" "High,Prog Pattern A,Prog Pattern B,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OD1JE ,OD1 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " IOD1SI ,Invert OD1 Selected Input" "No effect,Invetred"
|
|
bitfld.long 0x00 4.--5. " OD1IS ,OD1 Input Select" "High,Prog Pattern A,Prog Pattern B,Prot Engine Status"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OD0JE ,OD0 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " IOD0SI ,Invert OD0 Selected Input" "No effect,Inverted"
|
|
bitfld.long 0x00 0.--1. " OD0IS ,OD0 Input Select" "High,Prog Pattern A,Prog Pattern B,Prot Engine Activity"
|
|
width 0xB
|
|
tree.end
|
|
tree "SGPIO Unit 1"
|
|
base asd:(0x0:0xFFD80000+0x2680)
|
|
width 0xD
|
|
group.long 0x00++0x0f
|
|
line.long 0x00 "SGICR1,SGPIO Interface Control Register 1"
|
|
bitfld.long 0x00 0. " SGPIOFE ,SGPIO 1 Functionality Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SGPBR1,SGPIO Programmable Blink Register 1"
|
|
bitfld.long 0x04 12.--15. " PPBHDT ,Programmable Pattern B High Duration Time" "125,250,375,500,625,750,875,1000,1125,1250,1375,1500,1625,1750,1875,2000"
|
|
bitfld.long 0x04 08.--11. " PPBLDT ,Programmable Pattern B Low Duration Time" "125,250,375,500,625,750,875,1000,1125,1250,1375,1500,1625,1750,1875,2000"
|
|
bitfld.long 0x04 4.--7. " PPAHDT ,Programmable Pattern A High Duration Time" "125,250,375,500,625,750,875,1000,1125,1250,1375,1500,1625,1750,1875,2000"
|
|
bitfld.long 0x04 0.--3. " PPALDT ,Programmable Pattern A Low Duration Time" "125,250,375,500,625,750,875,1000,1125,1250,1375,1500,1625,1750,1875,2000"
|
|
line.long 0x08 "SGSDLR1,SGPIO Start Drive Lower Register 1"
|
|
bitfld.long 0x08 12.--14. " O3SB ,Output 3 Select Bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 8.--10. " O2SB ,Output 2 Select Bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 4.--6. " O1SB ,Output 1 Select Bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 0.--2. " O0SB ,Output 0 Select Bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0c "SGSDUR1,SGPIO Start Drive Upper Register 1"
|
|
bitfld.long 0x0c 12.--14. " O7SB ,Output 7 Select Bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0c 8.--10. " O6SB ,Output 6 Select Bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0c 4.--6. " O5SB ,Output 5 Select Bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0c 0.--2. " O4SB ,Output 4 Select Bits" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x10++0x07
|
|
line.long 0x00 "SGSIDLR1,SGPIO Serial Input Data Lower Register 1"
|
|
bitfld.long 0x00 12.--14. " D3ID ,Drive 3 input data" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " D2ID ,Drive 2 input data" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " D1ID ,Drive 1 input data" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " D0ID ,Drive 0 input data" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "SGSIDUR1,SGPIO Serial Input Data Upper Register 1"
|
|
bitfld.long 0x04 12.--14. " D7ID ,Drive 7 input data" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 8.--10. " D6ID ,Drive 6 input data" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 4.--6. " D5ID ,Drive 5 input data" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. " D4ID ,Drive 4 input data" "0,1,2,3,4,5,6,7"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SGVSCR1,SGPIO Vendor Specific Code Register 1"
|
|
bitfld.long 0x00 0.--3. " VSD ,Vendor Specific data" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F"
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "SGODSR01,SGPIO Output Data Select Register0 1"
|
|
bitfld.long 0x00 11. " OD2JE ,OD2 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " IOD2SI ,Invert OD2 Selected Input" "No effect,Inverted"
|
|
bitfld.long 0x00 8.--9. " OD2IS ,OD2 Input Select" "High,Prog Pattern A,Prog Pattern B,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OD1JE ,OD1 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " IOD1SI ,Invert OD1 Selected Input" "No effect,Invetred"
|
|
bitfld.long 0x00 4.--5. " OD1IS ,OD1 Input Select" "High,Prog Pattern A,Prog Pattern B,Prot Engine Status"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OD0JE ,OD0 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " IOD0SI ,Invert OD0 Selected Input" "No effect,Inverted"
|
|
bitfld.long 0x00 0.--1. " OD0IS ,OD0 Input Select" "High,Prog Pattern A,Prog Pattern B,Prot Engine Activity"
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "SGODSR11,SGPIO Output Data Select Register1 1"
|
|
bitfld.long 0x00 11. " OD2JE ,OD2 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " IOD2SI ,Invert OD2 Selected Input" "No effect,Inverted"
|
|
bitfld.long 0x00 8.--9. " OD2IS ,OD2 Input Select" "High,Prog Pattern A,Prog Pattern B,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OD1JE ,OD1 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " IOD1SI ,Invert OD1 Selected Input" "No effect,Invetred"
|
|
bitfld.long 0x00 4.--5. " OD1IS ,OD1 Input Select" "High,Prog Pattern A,Prog Pattern B,Prot Engine Status"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OD0JE ,OD0 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " IOD0SI ,Invert OD0 Selected Input" "No effect,Inverted"
|
|
bitfld.long 0x00 0.--1. " OD0IS ,OD0 Input Select" "High,Prog Pattern A,Prog Pattern B,Prot Engine Activity"
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "SGODSR21,SGPIO Output Data Select Register2 1"
|
|
bitfld.long 0x00 11. " OD2JE ,OD2 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " IOD2SI ,Invert OD2 Selected Input" "No effect,Inverted"
|
|
bitfld.long 0x00 8.--9. " OD2IS ,OD2 Input Select" "High,Prog Pattern A,Prog Pattern B,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OD1JE ,OD1 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " IOD1SI ,Invert OD1 Selected Input" "No effect,Invetred"
|
|
bitfld.long 0x00 4.--5. " OD1IS ,OD1 Input Select" "High,Prog Pattern A,Prog Pattern B,Prot Engine Status"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OD0JE ,OD0 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " IOD0SI ,Invert OD0 Selected Input" "No effect,Inverted"
|
|
bitfld.long 0x00 0.--1. " OD0IS ,OD0 Input Select" "High,Prog Pattern A,Prog Pattern B,Prot Engine Activity"
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "SGODSR31,SGPIO Output Data Select Register3 1"
|
|
bitfld.long 0x00 11. " OD2JE ,OD2 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " IOD2SI ,Invert OD2 Selected Input" "No effect,Inverted"
|
|
bitfld.long 0x00 8.--9. " OD2IS ,OD2 Input Select" "High,Prog Pattern A,Prog Pattern B,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OD1JE ,OD1 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " IOD1SI ,Invert OD1 Selected Input" "No effect,Invetred"
|
|
bitfld.long 0x00 4.--5. " OD1IS ,OD1 Input Select" "High,Prog Pattern A,Prog Pattern B,Prot Engine Status"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OD0JE ,OD0 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " IOD0SI ,Invert OD0 Selected Input" "No effect,Inverted"
|
|
bitfld.long 0x00 0.--1. " OD0IS ,OD0 Input Select" "High,Prog Pattern A,Prog Pattern B,Prot Engine Activity"
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "SGODSR41,SGPIO Output Data Select Register4 1"
|
|
bitfld.long 0x00 11. " OD2JE ,OD2 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " IOD2SI ,Invert OD2 Selected Input" "No effect,Inverted"
|
|
bitfld.long 0x00 8.--9. " OD2IS ,OD2 Input Select" "High,Prog Pattern A,Prog Pattern B,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OD1JE ,OD1 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " IOD1SI ,Invert OD1 Selected Input" "No effect,Invetred"
|
|
bitfld.long 0x00 4.--5. " OD1IS ,OD1 Input Select" "High,Prog Pattern A,Prog Pattern B,Prot Engine Status"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OD0JE ,OD0 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " IOD0SI ,Invert OD0 Selected Input" "No effect,Inverted"
|
|
bitfld.long 0x00 0.--1. " OD0IS ,OD0 Input Select" "High,Prog Pattern A,Prog Pattern B,Prot Engine Activity"
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "SGODSR51,SGPIO Output Data Select Register5 1"
|
|
bitfld.long 0x00 11. " OD2JE ,OD2 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " IOD2SI ,Invert OD2 Selected Input" "No effect,Inverted"
|
|
bitfld.long 0x00 8.--9. " OD2IS ,OD2 Input Select" "High,Prog Pattern A,Prog Pattern B,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OD1JE ,OD1 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " IOD1SI ,Invert OD1 Selected Input" "No effect,Invetred"
|
|
bitfld.long 0x00 4.--5. " OD1IS ,OD1 Input Select" "High,Prog Pattern A,Prog Pattern B,Prot Engine Status"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OD0JE ,OD0 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " IOD0SI ,Invert OD0 Selected Input" "No effect,Inverted"
|
|
bitfld.long 0x00 0.--1. " OD0IS ,OD0 Input Select" "High,Prog Pattern A,Prog Pattern B,Prot Engine Activity"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "SGODSR61,SGPIO Output Data Select Register6 1"
|
|
bitfld.long 0x00 11. " OD2JE ,OD2 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " IOD2SI ,Invert OD2 Selected Input" "No effect,Inverted"
|
|
bitfld.long 0x00 8.--9. " OD2IS ,OD2 Input Select" "High,Prog Pattern A,Prog Pattern B,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OD1JE ,OD1 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " IOD1SI ,Invert OD1 Selected Input" "No effect,Invetred"
|
|
bitfld.long 0x00 4.--5. " OD1IS ,OD1 Input Select" "High,Prog Pattern A,Prog Pattern B,Prot Engine Status"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OD0JE ,OD0 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " IOD0SI ,Invert OD0 Selected Input" "No effect,Inverted"
|
|
bitfld.long 0x00 0.--1. " OD0IS ,OD0 Input Select" "High,Prog Pattern A,Prog Pattern B,Prot Engine Activity"
|
|
group.long 0x3C++0x3
|
|
line.long 0x00 "SGODSR71,SGPIO Output Data Select Register7 1"
|
|
bitfld.long 0x00 11. " OD2JE ,OD2 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " IOD2SI ,Invert OD2 Selected Input" "No effect,Inverted"
|
|
bitfld.long 0x00 8.--9. " OD2IS ,OD2 Input Select" "High,Prog Pattern A,Prog Pattern B,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OD1JE ,OD1 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " IOD1SI ,Invert OD1 Selected Input" "No effect,Invetred"
|
|
bitfld.long 0x00 4.--5. " OD1IS ,OD1 Input Select" "High,Prog Pattern A,Prog Pattern B,Prot Engine Status"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OD0JE ,OD0 JOG Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " IOD0SI ,Invert OD0 Selected Input" "No effect,Inverted"
|
|
bitfld.long 0x00 0.--1. " OD0IS ,OD0 Input Select" "High,Prog Pattern A,Prog Pattern B,Prot Engine Activity"
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree "SC (System Controller)"
|
|
base asd:(0x0:0xFFD80000+0x1640)
|
|
width 0x9
|
|
group.long 0x0++0xb
|
|
line.long 0x0 "IBACR,Internal Bus Arbitration Control Register"
|
|
bitfld.long 0x00 21. " DMGC ,DDRMCU/MU Group Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 19. " ADMAGC ,Application DMA Group Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 18. " ATUXC ,ATU-X Control" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ATUEC ,ATU-E Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 16. " SMBGC ,SMBus Group Control" "Enabled,Disabled"
|
|
sif (cpu()=="I81342")||(cpu()=="I81342")
|
|
bitfld.long 0x00 1. " XSCC1C ,XSC CoreID1 Control" "Enabled,Disabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " XSCC0C ,XSC CoreID0 Control" "Enabled,Disabled"
|
|
line.long 0x04 "SIBATCR,South Internal Bus Address Test Control Register"
|
|
bitfld.long 0x04 20. " ADRPARMSK ,Address Parity Mask bit 4" "0,1"
|
|
bitfld.long 0x04 19. ",Address Parity Mask bit 3" "0,1"
|
|
bitfld.long 0x04 18. ",Address Parity Mask bit 2" "0,1"
|
|
bitfld.long 0x04 17. ",Address Parity Mask bit 1" "0,1"
|
|
bitfld.long 0x04 16. ",Address Parity Mask bit 0" "0,1"
|
|
bitfld.long 0x04 4.--7. " IID ,Initiator ID" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F"
|
|
bitfld.long 0x04 0. " ENABLE ,Enable bit" "Disabled,Enabled"
|
|
line.long 0x08 "SIBDTCR,South Internal Bus Data Test Control Register"
|
|
bitfld.long 0x08 31. " DPMASK ,Data Parity Mask bit 15" "0,1"
|
|
bitfld.long 0x08 30. ",Data Parity Mask bit 14" "0,1"
|
|
bitfld.long 0x08 29. ",Data Parity Mask bit 13" "0,1"
|
|
bitfld.long 0x08 28. ",Data Parity Mask bit 12" "0,1"
|
|
bitfld.long 0x08 27. ",Data Parity Mask bit 11" "0,1"
|
|
bitfld.long 0x08 26. ",Data Parity Mask bit 10" "0,1"
|
|
bitfld.long 0x08 25. ",Data Parity Mask bit 9" "0,1"
|
|
bitfld.long 0x08 24. ",Data Parity Mask bit 8" "0,1"
|
|
bitfld.long 0x08 23. ",Data Parity Mask bit 7" "0,1"
|
|
bitfld.long 0x08 22. ",Data Parity Mask bit 6" "0,1"
|
|
bitfld.long 0x08 21. ",Data Parity Mask bit 5" "0,1"
|
|
bitfld.long 0x08 20. ",Data Parity Mask bit 4" "0,1"
|
|
bitfld.long 0x08 19. ",Data Parity Mask bit 3" "0,1"
|
|
bitfld.long 0x08 18. ",Data Parity Mask bit 2" "0,1"
|
|
bitfld.long 0x08 17. ",Data Parity Mask bit 1" "0,1"
|
|
bitfld.long 0x08 16. ",Data Parity Mask bit 0" "0,1"
|
|
bitfld.long 0x08 4.--7. " IID ,Initiator ID" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F"
|
|
bitfld.long 0x08 0. " ENABLE ,Enable bit" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "Internal Bus Bridge"
|
|
base asd:(0x0:0xFFD80000+0x1780)
|
|
width 0x8
|
|
group.long 0x0++0xf
|
|
line.long 0x0 "BWBAR,Bridge Window Base Address Register"
|
|
hexmask.long 0x0 12.--31. 0x1000 " MEMWIN ,Bridge Memory Window Base Address"
|
|
line.long 0x4 "BWUBAR,Bridge Window Upper Base Address Register"
|
|
hexmask.long.byte 0x4 0.--3. 0x1 " MEMWINU ,Bridge Upper Memory Window Base Address"
|
|
line.long 0x8 "BELR,Bridge Limit Register"
|
|
hexmask.long 0x8 12.--31. 0x1000 " MEMWINLIM ,Bridge Memory Window Limit"
|
|
line.long 0xc "BECSR,Bridge Error Control and Status Register"
|
|
bitfld.long 0x0C 16. " EREPE ,Error Reporting Enable" "Disabled,Enabled"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.long 0x0C 8.--11. " RID ,Requester ID" "Reserved,Core 0,Core 1,ATU-X,ATU-E,ADMAs,N/A,LMU,Reserved,SMBus,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
|
|
else
|
|
bitfld.long 0x0C 8.--11. " RID ,Requester ID" "Reserved,Core 0,Reserved,ATU-X,ATU-E,ADMAs,N/A,LMU,Reserved,SMBus,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
|
|
endif
|
|
bitfld.long 0x0C 5. " IT ,Interface Type" "North,South"
|
|
textline " "
|
|
bitfld.long 0x0C 2.--3. " ERRT ,Error Type" "Master Abort,Bridge Master Address Error,Target Abort,Target Address Error"
|
|
bitfld.long 0x0C 4. " CT ,Command Type" "Read,Write"
|
|
eventfld.long 0x0C 1. " ERRNDET ,Error N Detected" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x0C 0. " ERRDET ,Error Detected" "No error,Error"
|
|
rgroup.long 0x10++0x7
|
|
line.long 0x0 "BERAR,Bridge Error Address Register"
|
|
line.long 0x4 "BERUAR,Bridge Error Upper Address Register"
|
|
hexmask.long.byte 0x04 0.--3. 1. " BERUA ,Error Address"
|
|
width 0xb
|
|
tree.end
|
|
tree "DMC (DDR SDRAM Memory Controller)"
|
|
base asd:(0x0:0xFFD80000+0x1800)
|
|
width 0xb
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "SDIR,DDR SDRAM Initialization Register"
|
|
bitfld.long 0x00 31. " CS0 ,Chip Select CS0" "Not selected,Selected"
|
|
bitfld.long 0x00 30. " CS1 ,Chip Select CS1" "Not selected,Selected"
|
|
bitfld.long 0x00 23.--25. " BA ,Bank Select Bits" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 7.--20. 0x80 " MA ,Address Bits"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RAS ,Row Address Strobe" "No effect,Strobed"
|
|
bitfld.long 0x00 5. " CAS ,Column Address Strobe" "No effect,Strobed"
|
|
bitfld.long 0x00 4. " WE ,Write Strobe" "No effect,Strobed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DT3 ,4-Bit Burst Code Bit 3" "0,1"
|
|
bitfld.long 0x00 2. " DT2 ,4-Bit Burst Code Bit 2" "0,1"
|
|
bitfld.long 0x00 1. " DT1 ,4-Bit Burst Code Bit 1" "0,1"
|
|
bitfld.long 0x00 0. " DT0 ,4-Bit Burst Code Bit 0" "0,1"
|
|
line.long 0x04 "SDCR0,SDRAM Control Register 0"
|
|
bitfld.long 0x04 27.--31. " RAS ,Active to Precharge duration in MCLK periods" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 24.--26. " RP ,Precharge Command Period in MCLK periods" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 20.--22. " RCD ,Active to Read, Active to Write Period in MCLK periods" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 16.--18. " tEDP ,Data Path Latency in MCLK periods" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 12.--13. " WDL ,Write Latency in MCLK periods" "0,1,2,3"
|
|
bitfld.long 0x04 8.--10. " CAS ,CAS Latency used by the Memory Controller state machine" "Reserved,Reserved,3,4,5,Reserved,Reserved,Reserved"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RRFIFO ,Reset read FIFO" "Reset,No effect"
|
|
bitfld.long 0x04 6. " IBAM ,Internal Bus Address Map Control" "0,1"
|
|
bitfld.long 0x04 4.--5. " ODTSTOP ,ODT Termination Value:" "Disabled,75 Ohm,150 Ohm,Reserved"
|
|
textline " "
|
|
bitfld.long 0x04 2. " DDRTYPE ,DDR Type" "0,1"
|
|
bitfld.long 0x04 1. " DATABUS ,Data Bus Width:" "64-bit,32-bit"
|
|
bitfld.long 0x04 0. " DIMM ,DIMM Type" "Unbuffered,Registered"
|
|
line.long 0x08 "SDCR1,DDR SDRAM Control Register 1"
|
|
bitfld.long 0x08 31. " DQS ,DQS Disable" "Enabled,Disabled"
|
|
bitfld.long 0x08 27.--30. " RTCMD ,Read to Command (non-Read) turnaround period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 23.--26. " WTCMD ,Write to Command (non-Read) turnaround period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 19.--22. " RTW ,Read to Write turnaround period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 12.--17. " RFC ,Refresh to Active and Refresh to Refresh period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 9.--11. " WR ,Write Recovery time" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 4.--8. " RC ,Active to Active and Active to Refresh period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 0.--3. " WTRD ,Write to Read turnaround period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0xc "SDBR,SDRAM Base Register"
|
|
hexmask.long 0xc 27.--31. 0x8000000 " SDRAMBA ,SDRAM Base Address"
|
|
line.long 0x10 "SDUBR,SDRAM Upper Base Register"
|
|
hexmask.long 0x10 0.--3. 1. " SDRAMUA ,SDRAM Upper Base Address"
|
|
if (((data.long(asd:((0x0:0xFFD80000+0x1800)+0x4)))&0x2)==0x2)
|
|
;SDCR0 -> DATABUS == 64-bit
|
|
group.long 0x14++0x13
|
|
line.long 0x0 "SBSR,SDRAM Bank Size Register"
|
|
bitfld.long 0x0 27.--31. " SDRAMSIZE ,SDRAM Bank Size:" "Empty,128 MB,256 MB,Reserved,512 MB,Reserved,Reserved,Reserved,1 GB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
|
|
bitfld.long 0x0 8.--11. " RMW ,Read to Write turnaround period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 2. " NOBANKS ,Number of DDR Banks" "2 Banks,1 Bank"
|
|
bitfld.long 0x0 0. " SDRAMTECH ,SDRAM Technology" "512 Mbit,1 Gbit"
|
|
else
|
|
group.long 0x14++0x13
|
|
line.long 0x0 "SBSR,SDRAM Bank Size Register"
|
|
bitfld.long 0x0 27.--31. " SDRAMSIZE ,SDRAM Bank Size:" "Empty,Reserved,256 MB,Reserved,512 MB,Reserved,Reserved,Reserved,1 GB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
|
|
bitfld.long 0x0 8.--11. " RMW ,Read to Write turnaround period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 2. " NOBANKS ,Number of DDR Banks" "2 Banks,1 Bank"
|
|
bitfld.long 0x0 0. " SDRAMTECH ,SDRAM Technology" "512 Mbit,1 Gbit"
|
|
endif
|
|
group.long 0x18++0x7
|
|
line.long 0x00 "S32SR,DDR SDRAM 32-bit Region Size Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " REGSIZE ,32-bit Region Size"
|
|
line.long 0x04 "DECCR,DDR ECC Control Register"
|
|
bitfld.long 0x04 3. " ECCEN ,ECC Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SBECEN ,Single Bit Error Correction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " MBEREN ,Multi-Bit Error Reporting Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " SBEREN ,Single Bit Error Reporting Enable" "Disabled,Enabled"
|
|
if ((((data.long(asd:((0x0:0xFFD80000+0x1800)+0x20)))&0xf0000)==0x0000)||(((data.long(asd:((0x0:0xFFD80000+0x1800)+0x20)))&0xf0000)==0x10000))
|
|
; this -> ECCEDMID == North bus OR|| South bus
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "DELOG0,DDR ECC Log Register 0"
|
|
hexmask.long.byte 0x0 28.--31. 0x1 " UECCADR ,Upper ECC Address"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.long 0x0 20.--23. " ECCER ,ECC Error Requester" "Reserved,CoreID0,CoreID1,ATUX,ATUE,Application DMA,Reserved,Reserved,Reserved,SMBus,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
|
|
else
|
|
bitfld.long 0x0 20.--23. " ECCER ,ECC Error Requester" "Reserved,CoreID0,Reserved,ATUX,ATUE,Application DMA,Reserved,Reserved,Reserved,SMBus,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
|
|
endif
|
|
bitfld.long 0x0 16.--19. " ECCEDMID ,ECC Error Direct Memory Port ID" "North bus,South bus,ADMA0,ADMA1,ADMA2,MU,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
|
|
textline " "
|
|
bitfld.long 0x0 12. " RW ,Read or Write" "Read,Write"
|
|
bitfld.long 0x0 8. " ERRTYPE ,ECC Error Type" "Single bit,Multi bit"
|
|
hexmask.long.byte 0x0 0.--7. 1. " SYNDROME ,Syndrome value indicating error"
|
|
else
|
|
; this -> ECCEDMID == North Internal OR|| South Internal
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "DELOG0,DDR ECC Log Register 0"
|
|
hexmask.long.byte 0x0 28.--31. 0x1 " UECCADR ,Upper ECC Address"
|
|
bitfld.long 0x0 16.--19. " ECCEDMID ,ECC Error Direct Memory Port ID" "North bus,South bus,ADMA0,ADMA1,ADMA2,MU,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
|
|
textline " "
|
|
bitfld.long 0x0 12. " RW ,Read or Write" "Read,Write"
|
|
bitfld.long 0x0 8. " ERRTYPE ,ECC Error Type" "Single bit,Multi bit"
|
|
hexmask.long.byte 0x0 0.--7. 1. " SYNDROME ,Syndrome value indicating error"
|
|
endif
|
|
if ((((data.long(asd:((0x0:0xFFD80000+0x1800)+0x24)))&0xf0000)==0x0000)||(((data.long(asd:((0x0:0xFFD80000+0x1800)+0x24)))&0xf0000)==0x10000))
|
|
; this -> ECCEDMID == North bus OR|| South bus
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "DELOG1,DDR ECC Log Register 1"
|
|
hexmask.long.byte 0x0 28.--31. 0x1 " UECCADR ,Upper ECC Address"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.long 0x0 20.--23. " ECCER ,ECC Error Requester" "Reserved,CoreID0,CoreID1,ATUX,ATUE,Application DMA,Reserved,Messaging Unit,Reserved,SMBus,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
|
|
else
|
|
bitfld.long 0x0 20.--23. " ECCER ,ECC Error Requester" "Reserved,CoreID0,Reserved,ATUX,ATUE,Application DMA,Reserved,Messaging Unit,Reserved,SMBus,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
|
|
endif
|
|
bitfld.long 0x0 16.--19. " ECCEDMID ,ECC Error Direct Memory Port ID" "North bus,South bus,ADMA0,ADMA1,ADMA2,MU,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
|
|
textline " "
|
|
bitfld.long 0x0 12. " RW ,Read or Write" "Read,Write"
|
|
bitfld.long 0x0 8. " ERRTYPE ,ECC Error Type" "Single bit,Multi bit"
|
|
hexmask.long.byte 0x0 0.--7. 1. " SYNDROME ,Syndrome value indicating error"
|
|
else
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "DELOG1,DDR ECC Log Register 1"
|
|
hexmask.long.byte 0x0 28.--31. 0x1 " UECCADR ,Upper ECC Address"
|
|
bitfld.long 0x0 16.--19. " ECCEDMID ,ECC Error Direct Memory Port ID" "North bus,South bus,ADMA0,ADMA1,ADMA2,MU,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
|
|
textline " "
|
|
bitfld.long 0x0 12. " RW ,Read or Write" "Read,Write"
|
|
bitfld.long 0x0 8. " ERRTYPE ,ECC Error Type" "Single bit,Multi bit"
|
|
hexmask.long.byte 0x0 0.--7. 1. " SYNDROME ,Syndrome value indicating error"
|
|
endif
|
|
if (((data.long(asd:((0x0:0xFFD80000+0x1800)+0x4)))&0x2)==0x2)
|
|
;SDCR0 -> DATABUS == 64-bit
|
|
rgroup.long 0x28++0x7
|
|
line.long 0x00 "DEAR0,DDR ECC Address Register 0"
|
|
hexmask.long 0x00 2.--31. 0x4 " ERRADR ,Error Address"
|
|
line.long 0x04 "DEAR1,DDR ECC Address Register 1"
|
|
hexmask.long 0x04 2.--31. 0x4 " ERRADR ,Error Address"
|
|
else
|
|
rgroup.long 0x28++0x7
|
|
line.long 0x00 "DEAR0,DDR ECC Address Register 0"
|
|
hexmask.long 0x00 3.--31. 0x8 " ERRADR ,Error Address"
|
|
line.long 0x04 "DEAR1,DDR ECC Address Register 1"
|
|
hexmask.long 0x04 3.--31. 0x8 " ERRADR ,Error Address"
|
|
endif
|
|
rgroup.long 0x30++0xf
|
|
line.long 0x0 "DECAR0,DDR ECC Context Address Register 0"
|
|
hexmask.long 0x0 5.--30. 0x20 " ADMAEDA ,ADMA Error Descriptor Address"
|
|
line.long 0x04 "DECAR1,DDR ECC Context Address Register 1"
|
|
hexmask.long 0x4 5.--30. 0x20 " ADMAEDA ,ADMA Error Descriptor Address"
|
|
line.long 0x08 "DECUAR0,DDR ECC Context Upper Address Register 0"
|
|
bitfld.long 0x8 2.--3. " DMACHN ,DMA Channel Number" "0,1,2,3"
|
|
line.long 0xc "DECUAR1,DDR ECC Context Upper Address Register 1"
|
|
bitfld.long 0xc 2.--3. " DMACHN ,DMA Channel Number" "0,1,2,3"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "DECTST,DDR ECC Test Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. " ECCMASK ,ECC Mask"
|
|
if ((((data.long(asd:((0x0:0xFFD80000+0x1800)+0x44)))&0xf0000)==0x0000)||(((data.long(asd:((0x0:0xFFD80000+0x1800)+0x44)))&0xf0000)==0x10000))
|
|
; this -> PEDMID == North bus OR|| South bus
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "DPCSR,DDR Parity Control and Status Register"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.long 0x0 20.--23. " PER ,Parity Error Requester" "Reserved,CoreID0,CoreID1,ATUX,ATUE,Application DMA,Reserved,Messaging Unit,Reserved,SMBus,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
|
|
else
|
|
bitfld.long 0x0 20.--23. " PER ,Parity Error Requester" "Reserved,CoreID0,Reserved,ATUX,ATUE,Application DMA,Reserved,Messaging Unit,Reserved,SMBus,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
|
|
endif
|
|
bitfld.long 0x0 16.--19. " PEDMID ,Parity Error Direct Memory Port ID" "North bus,South bus,ADMA0,ADMA1,ADMA2,MU,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
|
|
bitfld.long 0x0 0. " DMCUPAREN ,DMCU Parity Enabled" "Disabled,Enabled"
|
|
else
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "DPCSR,DDR Parity Control and Status Register"
|
|
bitfld.long 0x0 16.--19. " PEDMID ,Parity Error Direct Memory Port ID" "North bus,South bus,ADMA0,ADMA1,ADMA2,MU,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
|
|
bitfld.long 0x0 0. " DMCUPAREN ,DMCU Parity Enabled" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x48++0xb
|
|
line.long 0x0 "DPAR,DDR Parity Address Register"
|
|
hexmask.long 0x0 2.--31. 0x4 " ERRADR ,Parity Error Address"
|
|
line.long 0x4 "DPUAR,DDR Parity Upper Address Register"
|
|
hexmask.long.byte 0x4 0.--3. 1. " ERRUADR ,Parity Error Upper Address"
|
|
line.long 0x8 "DPCAR,DDR Parity Context Address Register"
|
|
hexmask.long 0x8 5.--30. 0x20 " ADMAEDA ,ADMA Error Descriptor Address"
|
|
rgroup.long 0x58++0x3
|
|
line.long 0x0 "DPCUAR,DDR Parity Context Upper Address Register"
|
|
bitfld.long 0x0 2.--3. " DMACHN ,DMA Channel Number" "0,1,2,3"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "DMCISR,DDR Memory Controller Interrupt Status Register"
|
|
eventfld.long 0x0 9. " PARERN ,Parity Error N" "No error,Error"
|
|
eventfld.long 0x0 8. " PARER0 ,Parity Error 0" "No error,Error"
|
|
eventfld.long 0x0 3. " ADDRRER ,Address Region Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x0 2. " ECCERN ,ECC Error N" "No error,Error"
|
|
eventfld.long 0x0 1. " ECCER1 ,ECC Error 1" "No error,Error"
|
|
eventfld.long 0x0 0. " ECCER0 ,ECC Error 0" "No error,Error"
|
|
group.long 0x68++0xb
|
|
line.long 0x0 "DMPTCR,DMCU Port Transaction Count Register"
|
|
bitfld.long 0x00 20.--23. " MOPTC ,MU Port Transaction Count" "16 transactions,1 transaction,2 transactions,3 transactions,4 transactions,5 transactions,6 transactions,7 transactions,8 transactions,9 transactions,10 transactions,11 transactions,12 transactions,13 transactions,14 transactions,15 transactions"
|
|
bitfld.long 0x00 16.--19. " ADMA2PTC ,ADMA 2 Port Transaction Count" "16 transactions,1 transaction,2 transactions,3 transactions,4 transactions,5 transactions,6 transactions,7 transactions,8 transactions,9 transactions,10 transactions,11 transactions,12 transactions,13 transactions,14 transactions,15 transactions"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " ADMA1PTC ,ADMA 1 Port Transaction Count" "16 transactions,1 transaction,2 transactions,3 transactions,4 transactions,5 transactions,6 transactions,7 transactions,8 transactions,9 transactions,10 transactions,11 transactions,12 transactions,13 transactions,14 transactions,15 transactions"
|
|
bitfld.long 0x00 8.--11. " ADMA0PTC ,ADMA 0 Port Transaction Count" "16 transactions,1 transaction,2 transactions,3 transactions,4 transactions,5 transactions,6 transactions,7 transactions,8 transactions,9 transactions,10 transactions,11 transactions,12 transactions,13 transactions,14 transactions,15 transactions"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SIBTC ,South Internal Bus Transaction Count" "16 transactions,1 transaction,2 transactions,3 transactions,4 transactions,5 transactions,6 transactions,7 transactions,8 transactions,9 transactions,10 transactions,11 transactions,12 transactions,13 transactions,14 transactions,15 transactions"
|
|
bitfld.long 0x00 0.--3. " NIBTC ,North Internal Bus Transaction Count" "16 transactions,1 transaction,2 transactions,3 transactions,4 transactions,5 transactions,6 transactions,7 transactions,8 transactions,9 transactions,10 transactions,11 transactions,12 transactions,13 transactions,14 transactions,15 transactions"
|
|
line.long 0x4 "DMPCR,DMCU Preemption Control Register"
|
|
bitfld.long 0x04 0.--3. " PDPC ,Preemption Data Phase Count" "Disabled,Reserved,Reserved,Reserved,4 bursts,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
|
|
line.long 0x8 "RFR,Refresh Frequency Register"
|
|
hexmask.long.word 0x8 0.--12. 1. " REFINT ,Refresh Interval"
|
|
group.long 0x800++0x33
|
|
textline " "
|
|
line.long 0x0 "DRCR,DDR RCOMP Control Register"
|
|
bitfld.long 0x0 13. " SLEW ,Slew rate manual override values" "Disabled,Enabled"
|
|
bitfld.long 0x0 11.--12. " ODTEN ,ODT Enable" "Disabled,150 Ohms,150 Ohms,75 Ohms"
|
|
bitfld.long 0x0 0. " RCOMPEN ,RCOMP State Machine Enable" "Disabled,Enabled"
|
|
line.long 0x4 "RPDSR,RCOMP Pad Drive Strength Select"
|
|
bitfld.long 0x04 9.--11. " DRVSTR0 ,Drive Strength Select for CKE[1:0] and CS[1:0]" "50 Ohm,35 Ohm,25 Ohm,17.9 Ohm,15 Ohm,Reserved,Reserved,Reserved"
|
|
bitfld.long 0x04 6.--8. " DRVSTR1 ,Drive Strength Select for M_CK[2:0] and M_CK[2:0]" "50 Ohm,35 Ohm,25 Ohm,17.9 Ohm,15 Ohm,Reserved,Reserved,Reserved"
|
|
bitfld.long 0x04 3.--5. " DRVSTR2 ,Drive Strength Select for BA[2:0], MA[13:0], WE, RAS, CAS, ODT[1:0]" "50 Ohm,35 Ohm,25 Ohm,17.9 Ohm,15 Ohm,Reserved,Reserved,Reserved"
|
|
textline " "
|
|
bitfld.long 0x04 0.--2. " DRVSTR3 ,Drive Strength Select for DQ[63:0]" "50 Ohm,35 Ohm,25 Ohm,17.9 Ohm,15 Ohm,Reserved,Reserved,Reserved"
|
|
line.long 0x8 "DQPODSR,DQ Pad ODT Drive Strength Manual Override Values Register"
|
|
hexmask.long.byte 0x8 6.--11. 1. " NODTSTR ,N-ODT drive strength manual override values for input DQ pad"
|
|
hexmask.long.byte 0x8 0.--5. 1. " PODTSTR ,P-ODT drive strength manual override values for input DQ pad"
|
|
line.long 0xc "DQPDSR,DQ Pad Drive Strength Manual Override Values Register"
|
|
hexmask.long.byte 0xc 15.--21. 1. " NDRVSTR ,N-drive strength for DQ[63:0]"
|
|
hexmask.long.byte 0xc 8.--14. 1. " PDRVSTR ,P-drive strength for DQ[63:0]"
|
|
bitfld.long 0xc 4.--7. " NSLEW ,N-slew rate for DQ[63:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xc 0.--3. " PSLEW ,P-slew rate for DQ[63:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "MAPDSR,MA Pad Drive Strength Manual Override Values Register"
|
|
hexmask.long.byte 0x10 15.--21. 1. " NDRVSTR ,N-drive strength for BA[2:0], MA[13:0], WE, RAS, CAS, ODT[1:0]"
|
|
hexmask.long.byte 0x10 8.--14. 1. " PDRVSTR ,P-drive strength for BA[2:0], MA[13:0], WE, RAS, CAS, ODT[1:0]"
|
|
bitfld.long 0x10 4.--7. " NSLEW ,N-slew rate for BA[2:0], MA[13:0], WE, RAS, CAS, ODT[1:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 0.--3. " PSLEW ,P-slew rate for BA[2:0], MA[13:0], WE, RAS, CAS, ODT[1:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x14 "MPDSR,MCLK Pad Drive Strength Manual Override Values Register"
|
|
hexmask.long.byte 0x14 15.--21. 1. " NDRVSTR ,N-drive strength for M_CK[2:0] and M_CK[2:0]"
|
|
hexmask.long.byte 0x14 8.--14. 1. " PDRVSTR ,P-drive strength for M_CK[2:0] and M_CK[2:0]"
|
|
bitfld.long 0x14 4.--7. " NSLEW ,N-slew rate for M_CK[2:0] and M_CK[2:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " PSLEW ,P-slew rate for M_CK[2:0] and M_CK[2:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "CKEPDSR,CKE/CS Pad Drive Strength Manual Override Values Register"
|
|
hexmask.long.byte 0x18 15.--21. 1. " NDRVSTR ,N-drive strength for CKE[1:0] and CS[1:0]"
|
|
hexmask.long.byte 0x18 8.--14. 1. " PDRVSTR ,P-drive strength for CKE[1:0] and CS[1:0]"
|
|
bitfld.long 0x18 4.--7. " NSLEW ,N-slew rate for CKE[1:0] and CS[1:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 0.--3. " PSLEW ,P-slew rate for CKE[1:0] and CS[1:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1c "DLLR0,DLL Delay Register 0"
|
|
bitfld.long 0x1c 24.--28. " DSSD ,Data Strobe Slave Delay for DQS1#" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x1c 16.--20. " DSSD ,Data Strobe Slave Delay for DQS1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x1c 8.--12. " DSSD ,Data Strobe Slave Delay for DQS0#" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x1c 0.--4. " DSSD ,Data Strobe Slave Delay for DQS0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x20 "DLLR1,DLL Delay Register 1"
|
|
bitfld.long 0x20 24.--28. " DSSD ,Data Strobe Slave Delay for DQS3#" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x20 16.--20. " DSSD ,Data Strobe Slave Delay for DQS3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x20 8.--12. " DSSD ,Data Strobe Slave Delay for DQS2#" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x20 0.--4. " DSSD ,Data Strobe Slave Delay for DQS2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x24 "DLLR2,DLL Delay Register 2"
|
|
bitfld.long 0x24 24.--28. " DSSD ,Data Strobe Slave Delay for DQS5#" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x24 16.--20. " DSSD ,Data Strobe Slave Delay for DQS5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x24 8.--12. " DSSD ,Data Strobe Slave Delay for DQS4#" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x24 0.--4. " DSSD ,Data Strobe Slave Delay for DQS4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x28 "DLLR3,DLL Delay Register 3"
|
|
bitfld.long 0x28 24.--28. " DSSD ,Data Strobe Slave Delay for DQS7#" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x28 16.--20. " DSSD ,Data Strobe Slave Delay for DQS7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x28 8.--12. " DSSD ,Data Strobe Slave Delay for DQS6#" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x28 0.--4. " DSSD ,Data Strobe Slave Delay for DQS6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x2c "DLLR4,DLL Delay Register 4"
|
|
bitfld.long 0x2c 24.--28. " DSSD ,Data Strobe Slave Delay for Receive Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x2c 16.--20. " DSSD ,Data Strobe Slave Delay for DQS[8:0] and DQS[8:0]# " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x2c 8.--12. " DSSD ,Data Strobe Slave Delay for DQS8#" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x2c 0.--4. " DSSD ,Data Strobe Slave Delay for DQS8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x30 "DLLRCVER,DLL Delay for Receive Enable Register"
|
|
bitfld.long 0x30 24. " RENRSL ,Receive Enable Result" "Disabled,Enabled"
|
|
bitfld.long 0x30 18. " RENRST ,Receive Enable Reset" "Disabled,Enabled"
|
|
bitfld.long 0x30 17. " RENSMEN ,Receive Enable State Machine Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 16. " DIMM ,DIMM Type" "Registered,Unbuffered"
|
|
bitfld.long 0x30 8.--10. " RENSD1 ,Receive Enable Slave Delay 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x30 0.--4. " RENSD0 ,Receive Enable Slave Delay 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x834++0x13
|
|
line.long 0x0 "DRSR15,DDR RCOMP Status Register for 15 Ohm RCOMP"
|
|
hexmask.long.byte 0x0 15.--21. 1. " NDRVSTR ,N-drive strength for 15 Ohm RCOMP"
|
|
hexmask.long.byte 0x0 8.--14. 1. " PDRVSTR ,P-drive strength for 15 Ohm RCOMP"
|
|
line.long 0x04 "DRSR17,DDR RCOMP Status Register for 17.9 Ohm RCOMP"
|
|
hexmask.long.byte 0x04 15.--21. 1. " NDRVSTR ,N-drive strength for 17.9 Ohm RCOMP"
|
|
hexmask.long.byte 0x04 8.--14. 1. " PDRVSTR ,P-drive strength for 17.9 Ohm RCOMP"
|
|
line.long 0x08 "DRSR25,DDR RCOMP Status Register for 25 Ohm RCOMP"
|
|
hexmask.long.byte 0x08 15.--21. 1. " NDRVSTR ,N-drive strength for 25 Ohm RCOMP"
|
|
hexmask.long.byte 0x08 8.--14. 1. " PDRVSTR ,P-drive strength for 25 Ohm RCOMP"
|
|
line.long 0x0c "DRSR35,DDR RCOMP Status Register for 35 Ohm RCOMP"
|
|
hexmask.long.byte 0x0c 15.--21. 1. " NDRVSTR ,N-drive strength for 35 Ohm RCOMP"
|
|
hexmask.long.byte 0x0c 8.--14. 1. " PDRVSTR ,P-drive strength for 35 Ohm RCOMP"
|
|
line.long 0x10 "DRSR50,DDR RCOMP Status Register for 50 Ohm RCOMP"
|
|
hexmask.long.byte 0x10 15.--21. 1. " NDRVSTR ,N-drive strength for 50 Ohm RCOMP"
|
|
hexmask.long.byte 0x10 8.--14. 1. " PDRVSTR ,P-drive strength for 50 Ohm RCOMP"
|
|
width 0xb
|
|
tree.end
|
|
sif (cpu()!="I81348")
|
|
tree "SMC (SRAM Memory Controller)"
|
|
base asd:(0x0:0xFFD80000+0x1500)
|
|
width 0xb
|
|
group.long 0x0++0xb
|
|
line.long 0x0 "SRAMBAR,SRAM Base Address Register"
|
|
hexmask.long 0x0 20.--31. 0x100000 " SBA ,SRAM Base Address"
|
|
line.long 0x4 "SRAMUBAR,SRAM Upper Base Address Register"
|
|
hexmask.long.byte 0x4 0.--3. 1. " SUBA ,SRAM Base Address"
|
|
line.long 0x8 "SECR,SRAM ECC Control Register"
|
|
bitfld.long 0x8 2. " SBECEN ,Single Bit Error Correction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 1. " MBEREN ,Multi-Bit Error Reporting Enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 0. " SBEREN ,Single Bit Error Reporting Enable" "Disabled,Enabled"
|
|
if (((data.long(asd:((0x0:0xFFD80000+0x1500)+0xc)))&0xf0000)==0x0000)
|
|
; this -> DMEMID == North bus
|
|
group.long 0xc++0x3
|
|
line.long 0x00 "SELOG,SRAM ECC Log Register"
|
|
hexmask.long 0x00 28.--31. 0x10000000 " ECCADRU ,Upper ECC Address"
|
|
sif (cpu()=="81342")
|
|
bitfld.long 0x00 20.--23. " ECCER ,ECC Error Requester" "Reserved,CoreID0,CoreID1,ATUX,ATUE,Application DMA,Reserved,Messaging Unit,Reserved,SMBus,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
|
|
else
|
|
bitfld.long 0x00 20.--23. " ECCER ,ECC Error Requester" "Reserved,CoreID0,Reserved,ATUX,ATUE,Application DMA,Reserved,Messaging Unit,Reserved,SMBus,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
|
|
endif
|
|
bitfld.long 0x00 16.--19. " DMEMID ,Direct Memory Port ID" "North bus,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RW ,Read or Write" "Read,Write"
|
|
bitfld.long 0x00 8. " ECCET ,ECC Error Type" "Single bit,Multi bit"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SYNDR ,Syndrome value indicating error"
|
|
else
|
|
group.long 0xc++0x3
|
|
line.long 0x00 "SELOG,SRAM ECC Log Register"
|
|
hexmask.long 0x00 28.--31. 0x10000000 " ECCADRU ,Upper ECC Address"
|
|
bitfld.long 0x00 16.--19. " DMEMID ,Direct Memory Port ID" "North bus,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RW ,Read or Write" "Read,Write"
|
|
bitfld.long 0x00 8. " ECCET ,ECC Error Type" "Single bit,Multi bit"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SYNDR ,Syndrome value indicating error"
|
|
endif
|
|
rgroup.long 0x10++0x7
|
|
line.long 0x0 "SEAR,SRAM ECC Address Register"
|
|
hexmask.long 0x0 2.--31. 0x4 " ERRADR ,Error Address"
|
|
line.long 0x4 "SECAR,SRAM ECC Context Address Register"
|
|
hexmask.long 0x4 0.--23. 1. " ERRADR ,Error Address"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "SECTST,SRAM ECC Test Register"
|
|
hexmask.long.byte 0x0 0.--6. 1. " ECCMASK ,ECC Mask"
|
|
if (((data.long(asd:((0x0:0xFFD80000+0x1500)+0x1c)))&0xf0000)==0x0000)
|
|
; this -> DMEMID == North bus
|
|
group.long 0x1c++0x3
|
|
line.long 0x00 "SPARCSR,SRAM Parity Control and Status Register"
|
|
sif (cpu()=="I81342")
|
|
bitfld.long 0x0 20.--23. " PARER ,Parity Error Requester" "Reserved,CoreID0,CoreID1,ATUX,ATUE,Application DMA,Reserved,Messaging Unit,Reserved,SMBus,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
|
|
else
|
|
bitfld.long 0x0 20.--23. " PARER ,Parity Error Requester" "Reserved,CoreID0,Reserved,ATUX,ATUE,Application DMA,Reserved,Messaging Unit,Reserved,SMBus,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
|
|
endif
|
|
bitfld.long 0x0 16.--19. " DMEMID ,Direct Memory Port ID" "North bus,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
|
|
bitfld.long 0x0 0. " SMCUPE ,SMCU Parity Enabled" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1c++0x3
|
|
line.long 0x00 "SPARCSR,SRAM Parity Control and Status Register"
|
|
bitfld.long 0x0 16.--19. " DMEMID ,Direct Memory Port ID" "North bus,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
|
|
bitfld.long 0x0 0. " SMCUPE ,SMCU Parity Enabled" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "SPAR,SRAM Parity Address Register"
|
|
hexmask.long 0x0 2.--31. 0x4 " ERRADRL ,Error Address"
|
|
line.long 0x4 "SPUAR,SRAM Parity Upper Address Register"
|
|
hexmask.long.byte 0x4 0.--3. 1. " ERRADRU ,Parity Error Address"
|
|
group.long 0x2c++0x3
|
|
line.long 0x0 "SMCISR,SRAM Memory Controller Interrupt Status Register"
|
|
eventfld.long 0x00 9. " PARN ,Parity N" "No error,Error"
|
|
eventfld.long 0x00 8. " PARER ,Parity Error" "No error,Error"
|
|
eventfld.long 0x00 3. " ADRRANER ,Address Range Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ECCERN ,ECC Error N" "No error,Error"
|
|
eventfld.long 0x00 0. " ECCER0 ,ECC Error 0" "No error,Error"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
tree "PBI (Peripheral Bus Interface)"
|
|
base asd:(0x0:0xFFD80000+0x1500)
|
|
width 0x8
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "PBCR,PBI Control Register"
|
|
hexmask.long.byte 0x0 24.--27. 0x1 " MEMWIN1 ,PBI Memory Window 1 Upper 4-bit address"
|
|
hexmask.long.byte 0x0 16.--19. 0x1 " MEMWIN0 ,PBI Memory Window 0 Upper 4-bit address"
|
|
bitfld.long 0x0 0. " PBIENA ,PBI Enable" "Disabled,Enabled"
|
|
line.long 0x4 "PBISR,PBI Status Register"
|
|
eventfld.long 0x4 0. " BCORER ,Byte Count Out of Range Error" "No error,Error"
|
|
group.long 0x88++0xf
|
|
line.long 0x0 "PBBAR0,PBI Base Address Register 0"
|
|
hexmask.long 0x0 12.--31. 0x1000 " MEMWIN0 ,Memory Window 0 Base Address"
|
|
bitfld.long 0x0 9.--11. " D2DWAIT ,Data-to-Data Wait States" "A2DWAIT,A2DWAIT,4 D2D,8 D2D,12 D2D,16 D2D,20 D2D,20 D2D"
|
|
bitfld.long 0x0 6.--8. " RECYWAIT ,Recovery Cycle Wait States" "1 state,4 states,8 states,12 states,16 states,20 states,20 states,20 states"
|
|
textline " "
|
|
bitfld.long 0x0 2.--4. " A2DWAIT ,Address-to-Data Wait States" "4 A2D,8 A2D,12 A2D,16 A2D,20 A2D,20 A2D,20 A2D,20 A2D"
|
|
bitfld.long 0x0 0.--1. " BWIDTH ,Bus Width" "8-bit,16-bit,Reserved,Reserved"
|
|
line.long 0x4 "PBLR0,PBI Limit Register 0"
|
|
hexmask.long 0x4 12.--31. 0x1000 " MEMWLIM0 ,Memory Window 0 Limit"
|
|
line.long 0x08 "PBBAR1,PBI Base Address Register 1"
|
|
hexmask.long 0x08 12.--31. 0x1000 " MEMWIN1 ,Memory Window 1 Base Address"
|
|
bitfld.long 0x08 9.--11. " D2DWAIT ,Data-to-Data Wait States" "A2DWAIT,A2DWAIT,4 D2D,8 D2D,12 D2D,16 D2D,20 D2D,20 D2D"
|
|
bitfld.long 0x08 6.--8. " RECYWAIT ,Recovery Cycle Wait States" "1 state,4 states,8 states,12 states,16 states,20 states,20 states,20 states"
|
|
textline " "
|
|
bitfld.long 0x08 2.--4. " A2DWAIT ,Address-to-Data Wait States" "4 A2D,8 A2D,12 A2D,16 A2D,20 A2D,20 A2D,20 A2D,20 A2D"
|
|
bitfld.long 0x08 0.--1. " BWIDTH ,Bus Width" "8-bit,16-bit,Reserved,Reserved"
|
|
line.long 0xc "PBLR1,PBI Limit Register 1"
|
|
hexmask.long 0xc 12.--31. 0x1000 " MEMWLIM1 ,Memory Window 1 Limit"
|
|
group.long 0xb80++0x3
|
|
line.long 0x0 "PBDSCR,PBI Drive Strength Control Register"
|
|
bitfld.long 0x0 16.--19. " NSLW ,Pull-Down Slew Rate Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 12.--15. " PSLW ,Pull-Up Slew Rate Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x0 6.--11. 1. " NDRV ,Pull-Down Drive Strength"
|
|
hexmask.long.byte 0x0 0.--5. 1. " PDRV ,Pull-Up Drive Strength"
|
|
rgroup.long 0xc80++0x3
|
|
line.long 0x0 "PFR,Processor Frequency Register"
|
|
bitfld.long 0x0 19.--20. " XSIBUSF ,XSI Bus Frequency Status" "Core_Freq/2,Core_Freq/3,Core_Freq/4,Reserved"
|
|
bitfld.long 0x0 16.--18. " FREQSTAT ,Processor Frequency Status" "600 MHz,667 MHz,800 MHz,933 MHz,100 MHz,1200 MHz,Reserved,Reserved"
|
|
sif (cpu()=="I81342")||(cpu()=="I81341")
|
|
group.long 0xc88++0x3
|
|
line.long 0x0 "ESSTS0,External Strap Status Register 0"
|
|
bitfld.long 0x0 16. " CLK_SRC_PCIE ,CLK_SRC_PCIE" "0,1"
|
|
bitfld.long 0x0 15. " INTERFACE_SEL_PCIX ,INTERFACE_SEL_PCIX" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 13. " LK_DN_RST_BYPASS ,CLK_SRC_PCIE" "0,1"
|
|
bitfld.long 0x0 12. " PCIX_PULLUP ,CLK_SRC_PCIE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 6. " BOOT_WIDTH_8 ,BOOT_WIDTH_8" "0,1"
|
|
bitfld.long 0x0 4.--5. " MEM_FREQ ,MEM_FREQ[1:0]" "0,1,2,3"
|
|
bitfld.long 0x0 0.--3. " SMBUS_ADDR_STR ,SMBus Address Straps" "SMB_A1,SMB_A2,SMB_A3,SMB_A5,?..."
|
|
elif (cpu()=="I81348")
|
|
group.long 0xc88++0x3
|
|
line.long 0x0 "ESSTS0,External Strap Status Register 0"
|
|
bitfld.long 0x0 16. " CLK_SRC_PCIE ,CLK_SRC_PCIE" "0,1"
|
|
bitfld.long 0x0 15. " INTERFACE_SEL_PCIX ,INTERFACE_SEL_PCIX" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 14. " CONTROLLER_ONLY ,CONTROLLER_ONLY" "0,1"
|
|
bitfld.long 0x0 13. " LK_DN_RST_BYPASS ,CLK_SRC_PCIE" "0,1"
|
|
bitfld.long 0x0 12. " PCIX_PULLUP ,CLK_SRC_PCIE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 6. " BOOT_WIDTH_8 ,BOOT_WIDTH_8" "0,1"
|
|
bitfld.long 0x0 4.--5. " MEM_FREQ ,MEM_FREQ[1:0]" "0,1,2,3"
|
|
bitfld.long 0x0 0.--3. " SMBUS_ADDR_STR ,SMBus Address Straps" "SMB_A1,SMB_A2,SMB_A3,SMB_A5,?..."
|
|
endif
|
|
rgroup.long 0xc94++0x7
|
|
line.long 0x0 "UID0,Unique ID Register 0"
|
|
hexmask.long 0x0 0.--27. 1. " UID0 ,Unique ID 0"
|
|
line.long 0x4 "UID1,Unique ID Register 1"
|
|
hexmask.long 0x4 0.--22. 1. " UID1 ,Unique ID 1"
|
|
width 0xb
|
|
tree.end
|
|
tree "IPU (Interprocessor Messaging Unit)"
|
|
base asd:(0x0:0xFFD80000+0xA00)
|
|
width 0x9
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "DBCR,Door Bell Control Register"
|
|
bitfld.long 0x00 28.--31. " HPDB ,Highest Priority Door Bell" "DBSTAT0,DBSTAT1,DBSTAT2,DBSTAT3,DBSTAT4,DBSTAT5,DBSTAT6,DBSTAT7,DBSTAT8,DBSTAT9,DBSTAT10,DBSTAT11,DBSTAT12,DBSTAT13,DBSTAT14,None"
|
|
bitfld.long 0x00 24.--27. " HPCQA ,Highest Priority Circular Queue Attention" "S0NF,R0NE,S1NF,R1NE,S2NF,R2NE,S3NF,R3NE,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,None"
|
|
bitfld.long 0x00 23. " R3NE ,Receive Queue 3 Not Empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x00 22. " S3NF ,Send Queue 3 Not Empty" "Empty,Not empty"
|
|
bitfld.long 0x00 21. " R2NE ,Receive Queue 2 Not Empty" "Empty,Not empty"
|
|
bitfld.long 0x00 20. " S2NF ,Send Queue 2 Not Empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x00 19. " R1NE ,Receive Queue 1 Not Empty" "Empty,Not empty"
|
|
bitfld.long 0x00 18. " S1NF ,Send Queue 1 Not Empty" "Empty,Not empty"
|
|
bitfld.long 0x00 17. " R0NE ,Receive Queue 0 Not Empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x00 16. " S0NF ,Send Queue 0 Not Empty" "Empty,Not empty"
|
|
textline " "
|
|
eventfld.long 0x00 14. " DBSTAT14 ,Door Bell 14 Status" "Not occurred,Occurred"
|
|
eventfld.long 0x00 13. " DBSTAT13 ,Door Bell 13 Status" "Not occurred,Occurred"
|
|
eventfld.long 0x00 12. " DBSTAT12 ,Door Bell 12 Status" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 11. " DBSTAT11 ,Door Bell 11 Status" "Not occurred,Occurred"
|
|
eventfld.long 0x00 10. " DBSTAT10 ,Door Bell 10 Status" "Not occurred,Occurred"
|
|
eventfld.long 0x00 9. " DBSTAT9 ,Door Bell 9 Status" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 8. " DBSTAT8 ,Door Bell 8 Status" "Not occurred,Occurred"
|
|
eventfld.long 0x00 7. " DBSTAT7 ,Door Bell 7 Status" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " DBSTAT6 ,Door Bell 6 Status" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 5. " DBSTAT5 ,Door Bell 5 Status" "Not occurred,Occurred"
|
|
eventfld.long 0x00 4. " DBSTAT4 ,Door Bell 4 Status" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " DBSTAT3 ,Door Bell 3 Status" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DBSTAT2 ,Door Bell 2 Status" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " DBSTAT1 ,Door Bell 1 Status" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " DBSTAT0 ,Door Bell 0 Status" "Not occurred,Occurred"
|
|
line.long 0x4 "DBER,Door Bell Enable Register"
|
|
bitfld.long 0x04 23. " ER3NE ,Enable Receive Queue 3 Not Empty Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " ES3NF ,Enable Send Queue 3 Not Empty Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " ER2NE ,Enable Receive Queue 2 Not Empty Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " ES2NF ,Enable Send Queue 2 Not Empty Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " ER1NE ,Enable Receive Queue 1 Not Empty Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " ES1NF ,Enable Send Queue 1 Not Empty Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " ER0NE ,Enable Receive Queue 0 Not Empty Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " ES0NF ,Enable Send Queue 0 Not Empty Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x04 14. " EDBST14 ,Enable Door Bell Status Interrupt 14" "Disabled,Enabled"
|
|
eventfld.long 0x04 13. " EDBST13 ,Enable Door Bell Status Interrupt 13" "Disabled,Enabled"
|
|
eventfld.long 0x04 12. " EDBST12 ,Enable Door Bell Status Interrupt 12" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x04 11. " EDBST11 ,Enable Door Bell Status Interrupt 11" "Disabled,Enabled"
|
|
eventfld.long 0x04 10. " EDBST10 ,Enable Door Bell Status Interrupt 10" "Disabled,Enabled"
|
|
eventfld.long 0x04 9. " EDBST9 ,Enable Door Bell Status Interrupt 9" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x04 8. " EDBST8 ,Enable Door Bell Status Interrupt 8" "Disabled,Enabled"
|
|
eventfld.long 0x04 7. " EDBST7 ,Enable Door Bell Status Interrupt 7" "Disabled,Enabled"
|
|
eventfld.long 0x04 6. " EDBST6 ,Enable Door Bell Status Interrupt 6" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x04 5. " EDBST5 ,Enable Door Bell Status Interrupt 5" "Disabled,Enabled"
|
|
eventfld.long 0x04 4. " EDBST4 ,Enable Door Bell Status Interrupt 4" "Disabled,Enabled"
|
|
eventfld.long 0x04 3. " EDBST3 ,Enable Door Bell Status Interrupt 3" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x04 2. " EDBST2 ,Enable Door Bell Status Interrupt 2" "Disabled,Enabled"
|
|
eventfld.long 0x04 1. " EDBST1 ,Enable Door Bell Status Interrupt 1" "Disabled,Enabled"
|
|
eventfld.long 0x04 0. " EDBST0 ,Enable Door Bell Status Interrupt 0" "Disabled,Enabled"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "DBAR,Door Bell Assertion Register"
|
|
bitfld.long 0x00 14. " DBSA14 ,Door Bell 14 Status Assertion" "Not asserted,Asserted"
|
|
bitfld.long 0x00 13. " DBSA13 ,Door Bell 13 Status Assertion" "Not asserted,Asserted"
|
|
bitfld.long 0x00 12. " DBSA12 ,Door Bell 12 Status Assertion" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DBSA11 ,Door Bell 11 Status Assertion" "Not asserted,Asserted"
|
|
bitfld.long 0x00 10. " DBSA10 ,Door Bell 10 Status Assertion" "Not asserted,Asserted"
|
|
bitfld.long 0x00 9. " DBSA9 ,Door Bell 9 Status Assertion" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DBSA8 ,Door Bell 8 Status Assertion" "Not asserted,Asserted"
|
|
bitfld.long 0x00 7. " DBSA7 ,Door Bell 7 Status Assertion" "Not asserted,Asserted"
|
|
bitfld.long 0x00 6. " DBSA6 ,Door Bell 6 Status Assertion" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DBSA5 ,Door Bell 5 Status Assertion" "Not asserted,Asserted"
|
|
bitfld.long 0x00 4. " DBSA4 ,Door Bell 4 Status Assertion" "Not asserted,Asserted"
|
|
bitfld.long 0x00 3. " DBSA3 ,Door Bell 3 Status Assertion" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DBSA2 ,Door Bell 2 Status Assertion" "Not asserted,Asserted"
|
|
bitfld.long 0x00 1. " DBSA1 ,Door Bell 1 Status Assertion" "Not asserted,Asserted"
|
|
bitfld.long 0x00 0. " DBSA0 ,Door Bell 0 Status Assertion" "Not asserted,Asserted"
|
|
line.long 0x4 "DBEOR,Door Bell Enable Other Processor Register"
|
|
bitfld.long 0x04 14. " EDBSTO14 ,Enable Door Bell 14 Status Interrupt for Other Processor" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " EDBSTO13 ,Enable Door Bell 13 Status Interrupt for Other Processor" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " EDBSTO12 ,Enable Door Bell 12 Status Interrupt for Other Processor" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " EDBSTO11 ,Enable Door Bell 11 Status Interrupt for Other Processor" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " EDBSTO10 ,Enable Door Bell 10 Status Interrupt for Other Processor" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " EDBSTO9 ,Enable Door Bell 9 Status Interrupt for Other Processor" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " EDBSTO8 ,Enable Door Bell 8 Status Interrupt for Other Processor" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " EDBSTO7 ,Enable Door Bell 7 Status Interrupt for Other Processor" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " EDBSTO6 ,Enable Door Bell 6 Status Interrupt for Other Processor" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " EDBSTO5 ,Enable Door Bell 5 Status Interrupt for Other Processor" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " EDBSTO4 ,Enable Door Bell 4 Status Interrupt for Other Processor" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " EDBSTO3 ,Enable Door Bell 3 Status Interrupt for Other Processor" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " EDBSTO2 ,Enable Door Bell 2 Status Interrupt for Other Processor" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " EDBSTO1 ,Enable Door Bell 1 Status Interrupt for Other Processor" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " EDBSTO0 ,Enable Door Bell 0 Status Interrupt for Other Processor" "Disabled,Enabled"
|
|
tree "IPMU 0"
|
|
group.long 0x20++0x1f
|
|
line.long 0x0 "SQPG0,Send Queue Put/Get Pointer Register 0"
|
|
hexmask.long.word 0x0 16.--31. 1. " SQ0GP ,Send Queue 0 Get Pointer"
|
|
hexmask.long.word 0x0 0.--15. 1. " SQ0PP ,Send Queue 0 Put Pointer"
|
|
line.long 0x4 "SQCR0,Send Queue Control Register 0"
|
|
bitfld.long 0x04 31. " SQ0R ,Send Queue 0 Reset" "No reset,Reset"
|
|
bitfld.long 0x04 30. " SQ0RR ,Send Queue 0 Reset Request" "Not requested,Requested"
|
|
hexmask.long.word 0x04 0.--15. 1. " SQ0S ,Send Queue 0 Size"
|
|
line.long 0x8 "SQLBAR0,Send Queue Lower Base Address Register 0"
|
|
line.long 0xc "SQUBAR0,Send Queue Upper Base Address Register 0"
|
|
hexmask.long.byte 0x0c 0.--3. 1. " SQUBAR0 ,Send Queue 0 Base Upper Base Address"
|
|
line.long 0x10 "RQPG0,Receive Queue Put/Get Pointer Register 0"
|
|
hexmask.long.word 0x10 16.--31. 1. " RQ0GP ,Receive Queue 0 Get Pointer"
|
|
hexmask.long.word 0x10 0.--15. 1. " RQ0PP ,Receive Queue 0 Put Pointer"
|
|
line.long 0x14 "RQPG0,Receive Queue Put/Get Pointer Register 0"
|
|
bitfld.long 0x14 31. " RQ0R ,Receive Queue 0 Reset" "No reset,Reset"
|
|
bitfld.long 0x14 30. " RQ0RR ,Receive Queue 0 Reset Request" "Not requested,Requested"
|
|
hexmask.long.word 0x14 0.--15. 1. " RQ0S ,Receive Queue 0 Size"
|
|
line.long 0x18 "RQLBAR0,Receive Queue Lower Base Address Register 0"
|
|
line.long 0x1c "RQUBAR0,Receive Queue Upper Base Address Register 0"
|
|
hexmask.long.byte 0x1c 0.--3. 1. " RQUBAR0 ,Receive Queue 0 Base Upper Base Address"
|
|
tree.end
|
|
tree "IPMU 1"
|
|
group.long 0x40++0x1f
|
|
line.long 0x0 "SQPG1,Send Queue Put/Get Pointer Register 1"
|
|
hexmask.long.word 0x0 16.--31. 1. " SQ1GP ,Send Queue 1 Get Pointer"
|
|
hexmask.long.word 0x0 0.--15. 1. " SQ1PP ,Send Queue 1 Put Pointer"
|
|
line.long 0x4 "SQCR1,Send Queue Control Register 1"
|
|
bitfld.long 0x04 31. " SQ1R ,Send Queue 1 Reset" "No reset,Reset"
|
|
bitfld.long 0x04 30. " SQ1RR ,Send Queue 1 Reset Request" "Not requested,Requested"
|
|
hexmask.long.word 0x04 0.--15. 1. " SQ1S ,Send Queue 1 Size"
|
|
line.long 0x8 "SQLBAR1,Send Queue Lower Base Address Register 1"
|
|
line.long 0xc "SQUBAR1,Send Queue Upper Base Address Register 1"
|
|
hexmask.long.byte 0x0c 0.--3. 1. " SQUBAR1 ,Send Queue 1 Base Upper Base Address"
|
|
line.long 0x10 "RQPG1,Receive Queue Put/Get Pointer Register 1"
|
|
hexmask.long.word 0x10 16.--31. 1. " RQ1GP ,Receive Queue 1 Get Pointer"
|
|
hexmask.long.word 0x10 0.--15. 1. " RQ1PP ,Receive Queue 1 Put Pointer"
|
|
line.long 0x14 "RQPG1,Receive Queue Put/Get Pointer Register 1"
|
|
bitfld.long 0x14 31. " RQ1R ,Receive Queue 1 Reset" "No reset,Reset"
|
|
bitfld.long 0x14 30. " RQ1RR ,Receive Queue 1 Reset Request" "Not requested,Requested"
|
|
hexmask.long.word 0x14 0.--15. 1. " RQ1S ,Receive Queue 1 Size"
|
|
line.long 0x18 "RQLBAR1,Receive Queue Lower Base Address Register 1"
|
|
line.long 0x1c "RQUBAR1,Receive Queue Upper Base Address Register 1"
|
|
hexmask.long.byte 0x1c 0.--3. 1. " RQUBAR1 ,Receive Queue 1 Base Upper Base Address"
|
|
tree.end
|
|
tree "IPMU 2"
|
|
group.long 0x60++0x1f
|
|
line.long 0x0 "SQPG2,Send Queue Put/Get Pointer Register 2"
|
|
hexmask.long.word 0x0 16.--31. 1. " SQ2GP ,Send Queue 2 Get Pointer"
|
|
hexmask.long.word 0x0 0.--15. 1. " SQ2PP ,Send Queue 2 Put Pointer"
|
|
line.long 0x4 "SQCR2,Send Queue Control Register 2"
|
|
bitfld.long 0x04 31. " SQ2R ,Send Queue 2 Reset" "No reset,Reset"
|
|
bitfld.long 0x04 30. " SQ2RR ,Send Queue 2 Reset Request" "Not requested,Requested"
|
|
hexmask.long.word 0x04 0.--15. 1. " SQ2S ,Send Queue 2 Size"
|
|
line.long 0x8 "SQLBAR2,Send Queue Lower Base Address Register 2"
|
|
line.long 0xc "SQUBAR2,Send Queue Upper Base Address Register 2"
|
|
hexmask.long.byte 0x0c 0.--3. 1. " SQUBAR2 ,Send Queue 2 Base Upper Base Address"
|
|
line.long 0x10 "RQPG2,Receive Queue Put/Get Pointer Register 2"
|
|
hexmask.long.word 0x10 16.--31. 1. " RQ2GP ,Receive Queue 2 Get Pointer"
|
|
hexmask.long.word 0x10 0.--15. 1. " RQ2PP ,Receive Queue 2 Put Pointer"
|
|
line.long 0x14 "RQPG2,Receive Queue Put/Get Pointer Register 2"
|
|
bitfld.long 0x14 31. " RQ2R ,Receive Queue 2 Reset" "No reset,Reset"
|
|
bitfld.long 0x14 30. " RQ2RR ,Receive Queue 2 Reset Request" "Not requested,Requested"
|
|
hexmask.long.word 0x14 0.--15. 1. " RQ2S ,Receive Queue 2 Size"
|
|
line.long 0x18 "RQLBAR2,Receive Queue Lower Base Address Register 2"
|
|
line.long 0x1c "RQUBAR2,Receive Queue Upper Base Address Register 2"
|
|
hexmask.long.byte 0x1c 0.--3. 1. " RQUBAR2 ,Receive Queue 2 Base Upper Base Address"
|
|
tree.end
|
|
tree "IPMU 3"
|
|
group.long 0x80++0x1f
|
|
line.long 0x0 "SQPG3,Send Queue Put/Get Pointer Register 3"
|
|
hexmask.long.word 0x0 16.--31. 1. " SQ3GP ,Send Queue 3 Get Pointer"
|
|
hexmask.long.word 0x0 0.--15. 1. " SQ3PP ,Send Queue 3 Put Pointer"
|
|
line.long 0x4 "SQCR3,Send Queue Control Register 3"
|
|
bitfld.long 0x04 31. " SQ3R ,Send Queue 3 Reset" "No reset,Reset"
|
|
bitfld.long 0x04 30. " SQ3RR ,Send Queue 3 Reset Request" "Not requested,Requested"
|
|
hexmask.long.word 0x04 0.--15. 1. " SQ3S ,Send Queue 3 Size"
|
|
line.long 0x8 "SQLBAR3,Send Queue Lower Base Address Register 3"
|
|
line.long 0xc "SQUBAR3,Send Queue Upper Base Address Register 3"
|
|
hexmask.long.byte 0x0c 0.--3. 1. " SQUBAR3 ,Send Queue 3 Base Upper Base Address"
|
|
line.long 0x10 "RQPG3,Receive Queue Put/Get Pointer Register 3"
|
|
hexmask.long.word 0x10 16.--31. 1. " RQ3GP ,Receive Queue 3 Get Pointer"
|
|
hexmask.long.word 0x10 0.--15. 1. " RQ3PP ,Receive Queue 3 Put Pointer"
|
|
line.long 0x14 "RQPG3,Receive Queue Put/Get Pointer Register 3"
|
|
bitfld.long 0x14 31. " RQ3R ,Receive Queue 3 Reset" "No reset,Reset"
|
|
bitfld.long 0x14 30. " RQ3RR ,Receive Queue 3 Reset Request" "Not requested,Requested"
|
|
hexmask.long.word 0x14 0.--15. 1. " RQ3S ,Receive Queue 3 Size"
|
|
line.long 0x18 "RQLBAR3,Receive Queue Lower Base Address Register 3"
|
|
line.long 0x1c "RQUBAR3,Receive Queue Upper Base Address Register 3"
|
|
hexmask.long.byte 0x1c 0.--3. 1. " RQUBAR3 ,Receive Queue 3 Base Upper Base Address"
|
|
tree.end
|
|
width 0xb
|
|
tree.open "IMU Test and Set Registers"
|
|
tree "IMUTSR 0 - 127"
|
|
group.byte 0x100++0x7f
|
|
line.byte 0x0 "IMUTSR0 ,IMU Test and Set Register 0 "
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x0 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x0 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x1 "IMUTSR1 ,IMU Test and Set Register 1 "
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x1 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x1 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x2 "IMUTSR2 ,IMU Test and Set Register 2 "
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x2 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x2 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x3 "IMUTSR3 ,IMU Test and Set Register 3 "
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x3 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x3 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x4 "IMUTSR4 ,IMU Test and Set Register 4 "
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x4 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x4 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x5 "IMUTSR5 ,IMU Test and Set Register 5 "
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x5 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x5 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x6 "IMUTSR6 ,IMU Test and Set Register 6 "
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x6 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x6 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x7 "IMUTSR7 ,IMU Test and Set Register 7 "
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x7 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x7 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x8 "IMUTSR8 ,IMU Test and Set Register 8 "
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x8 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x8 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x9 "IMUTSR9 ,IMU Test and Set Register 9 "
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x9 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x9 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0xA "IMUTSR10,IMU Test and Set Register 10"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0xA 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0xA 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0xB "IMUTSR11,IMU Test and Set Register 11"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0xB 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0xB 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0xC "IMUTSR12,IMU Test and Set Register 12"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0xC 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0xC 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0xD "IMUTSR13,IMU Test and Set Register 13"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0xD 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0xD 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0xE "IMUTSR14,IMU Test and Set Register 14"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0xE 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0xE 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0xF "IMUTSR15,IMU Test and Set Register 15"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0xF 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0xF 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x10 "IMUTSR16,IMU Test and Set Register 16"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x10 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x10 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x11 "IMUTSR17,IMU Test and Set Register 17"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x11 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x11 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x12 "IMUTSR18,IMU Test and Set Register 18"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x12 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x12 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x13 "IMUTSR19,IMU Test and Set Register 19"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x13 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x13 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x14 "IMUTSR20,IMU Test and Set Register 20"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x14 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x14 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x15 "IMUTSR21,IMU Test and Set Register 21"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x15 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x15 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x16 "IMUTSR22,IMU Test and Set Register 22"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x16 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x16 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x17 "IMUTSR23,IMU Test and Set Register 23"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x17 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x17 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x18 "IMUTSR24,IMU Test and Set Register 24"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x18 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x18 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x19 "IMUTSR25,IMU Test and Set Register 25"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x19 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x19 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x1A "IMUTSR26,IMU Test and Set Register 26"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x1A 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x1A 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x1B "IMUTSR27,IMU Test and Set Register 27"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x1B 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x1B 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x1C "IMUTSR28,IMU Test and Set Register 28"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x1C 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x1C 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x1D "IMUTSR29,IMU Test and Set Register 29"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x1D 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x1D 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x1E "IMUTSR30,IMU Test and Set Register 30"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x1E 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x1E 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x1F "IMUTSR31,IMU Test and Set Register 31"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x1F 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x1F 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x20 "IMUTSR32,IMU Test and Set Register 32"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x20 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x20 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x21 "IMUTSR33,IMU Test and Set Register 33"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x21 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x21 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x22 "IMUTSR34,IMU Test and Set Register 34"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x22 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x22 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x23 "IMUTSR35,IMU Test and Set Register 35"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x23 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x23 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x24 "IMUTSR36,IMU Test and Set Register 36"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x24 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x24 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x25 "IMUTSR37,IMU Test and Set Register 37"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x25 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x25 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x26 "IMUTSR38,IMU Test and Set Register 38"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x26 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x26 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x27 "IMUTSR39,IMU Test and Set Register 39"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x27 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x27 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x28 "IMUTSR40,IMU Test and Set Register 40"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x28 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x28 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x29 "IMUTSR41,IMU Test and Set Register 41"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x29 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x29 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x2A "IMUTSR42,IMU Test and Set Register 42"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x2A 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x2A 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x2B "IMUTSR43,IMU Test and Set Register 43"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x2B 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x2B 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x2C "IMUTSR44,IMU Test and Set Register 44"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x2C 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x2C 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x2D "IMUTSR45,IMU Test and Set Register 45"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x2D 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x2D 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x2E "IMUTSR46,IMU Test and Set Register 46"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x2E 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x2E 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x2F "IMUTSR47,IMU Test and Set Register 47"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x2F 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x2F 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x30 "IMUTSR48,IMU Test and Set Register 48"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x30 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x30 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x31 "IMUTSR49,IMU Test and Set Register 49"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x31 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x31 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x32 "IMUTSR50,IMU Test and Set Register 50"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x32 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x32 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x33 "IMUTSR51,IMU Test and Set Register 51"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x33 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x33 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x34 "IMUTSR52,IMU Test and Set Register 52"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x34 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x34 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x35 "IMUTSR53,IMU Test and Set Register 53"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x35 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x35 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x36 "IMUTSR54,IMU Test and Set Register 54"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x36 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x36 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x37 "IMUTSR55,IMU Test and Set Register 55"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x37 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x37 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x38 "IMUTSR56,IMU Test and Set Register 56"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x38 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x38 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x39 "IMUTSR57,IMU Test and Set Register 57"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x39 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x39 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x3A "IMUTSR58,IMU Test and Set Register 58"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x3A 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x3A 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x3B "IMUTSR59,IMU Test and Set Register 59"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x3B 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x3B 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x3C "IMUTSR60,IMU Test and Set Register 60"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x3C 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x3C 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x3D "IMUTSR61,IMU Test and Set Register 61"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x3D 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x3D 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x3E "IMUTSR62,IMU Test and Set Register 62"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x3E 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x3E 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x3F "IMUTSR63,IMU Test and Set Register 63"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x3F 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x3F 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x40 "IMUTSR64,IMU Test and Set Register 64"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x40 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x40 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x41 "IMUTSR65,IMU Test and Set Register 65"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x41 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x41 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x42 "IMUTSR66,IMU Test and Set Register 66"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x42 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x42 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x43 "IMUTSR67,IMU Test and Set Register 67"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x43 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x43 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x44 "IMUTSR68,IMU Test and Set Register 68"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x44 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x44 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x45 "IMUTSR69,IMU Test and Set Register 69"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x45 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x45 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x46 "IMUTSR70,IMU Test and Set Register 70"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x46 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x46 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x47 "IMUTSR71,IMU Test and Set Register 71"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x47 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x47 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x48 "IMUTSR72,IMU Test and Set Register 72"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x48 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x48 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x49 "IMUTSR73,IMU Test and Set Register 73"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x49 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x49 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x4A "IMUTSR74,IMU Test and Set Register 74"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x4A 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x4A 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x4B "IMUTSR75,IMU Test and Set Register 75"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x4B 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x4B 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x4C "IMUTSR76,IMU Test and Set Register 76"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x4C 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x4C 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x4D "IMUTSR77,IMU Test and Set Register 77"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x4D 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x4D 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x4E "IMUTSR78,IMU Test and Set Register 78"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x4E 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x4E 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x4F "IMUTSR79,IMU Test and Set Register 79"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x4F 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x4F 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x50 "IMUTSR80,IMU Test and Set Register 80"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x50 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x50 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x51 "IMUTSR81,IMU Test and Set Register 81"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x51 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x51 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x52 "IMUTSR82,IMU Test and Set Register 82"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x52 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x52 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x53 "IMUTSR83,IMU Test and Set Register 83"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x53 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x53 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x54 "IMUTSR84,IMU Test and Set Register 84"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x54 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x54 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x55 "IMUTSR85,IMU Test and Set Register 85"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x55 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x55 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x56 "IMUTSR86,IMU Test and Set Register 86"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x56 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x56 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x57 "IMUTSR87,IMU Test and Set Register 87"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x57 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x57 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x58 "IMUTSR88,IMU Test and Set Register 88"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x58 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x58 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x59 "IMUTSR89,IMU Test and Set Register 89"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x59 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x59 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x5A "IMUTSR90,IMU Test and Set Register 90"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x5A 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x5A 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x5B "IMUTSR91,IMU Test and Set Register 91"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x5B 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x5B 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x5C "IMUTSR92,IMU Test and Set Register 92"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x5C 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x5C 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x5D "IMUTSR93,IMU Test and Set Register 93"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x5D 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x5D 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x5E "IMUTSR94,IMU Test and Set Register 94"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x5E 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x5E 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x5F "IMUTSR95,IMU Test and Set Register 95"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x5F 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x5F 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x60 "IMUTSR96,IMU Test and Set Register 96"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x60 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x60 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x61 "IMUTSR97,IMU Test and Set Register 97"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x61 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x61 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x62 "IMUTSR98,IMU Test and Set Register 98"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x62 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x62 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x63 "IMUTSR99,IMU Test and Set Register 99"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x63 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x63 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x64 "IMUTSR100,IMU Test and Set Register 100"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x64 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x64 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x65 "IMUTSR101,IMU Test and Set Register 101"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x65 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x65 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x66 "IMUTSR102,IMU Test and Set Register 102"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x66 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x66 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x67 "IMUTSR103,IMU Test and Set Register 103"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x67 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x67 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x68 "IMUTSR104,IMU Test and Set Register 104"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x68 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x68 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x69 "IMUTSR105,IMU Test and Set Register 105"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x69 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x69 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x6A "IMUTSR106,IMU Test and Set Register 106"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x6A 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x6A 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x6B "IMUTSR107,IMU Test and Set Register 107"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x6B 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x6B 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x6C "IMUTSR108,IMU Test and Set Register 108"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x6C 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x6C 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x6D "IMUTSR109,IMU Test and Set Register 109"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x6D 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x6D 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x6E "IMUTSR110,IMU Test and Set Register 110"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x6E 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x6E 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x6F "IMUTSR111,IMU Test and Set Register 111"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x6F 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x6F 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x70 "IMUTSR112,IMU Test and Set Register 112"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x70 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x70 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x71 "IMUTSR113,IMU Test and Set Register 113"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x71 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x71 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x72 "IMUTSR114,IMU Test and Set Register 114"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x72 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x72 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x73 "IMUTSR115,IMU Test and Set Register 115"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x73 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x73 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x74 "IMUTSR116,IMU Test and Set Register 116"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x74 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x74 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x75 "IMUTSR117,IMU Test and Set Register 117"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x75 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x75 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x76 "IMUTSR118,IMU Test and Set Register 118"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x76 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x76 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x77 "IMUTSR119,IMU Test and Set Register 119"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x77 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x77 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x78 "IMUTSR120,IMU Test and Set Register 120"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x78 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x78 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x79 "IMUTSR121,IMU Test and Set Register 121"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x79 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x79 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x7A "IMUTSR122,IMU Test and Set Register 122"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x7A 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x7A 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x7B "IMUTSR123,IMU Test and Set Register 123"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x7B 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x7B 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x7C "IMUTSR124,IMU Test and Set Register 124"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x7C 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x7C 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x7D "IMUTSR125,IMU Test and Set Register 125"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x7D 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x7D 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x7E "IMUTSR126,IMU Test and Set Register 126"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x7E 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x7E 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x7F "IMUTSR127,IMU Test and Set Register 127"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x7F 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x7F 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
tree.end
|
|
tree "IMUTSR 128 - 255"
|
|
group.byte 0x180++0x7f
|
|
line.byte 0x0 "IMUTSR128,IMU Test and Set Register 128"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x0 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x0 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x1 "IMUTSR129,IMU Test and Set Register 129"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x1 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x1 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x2 "IMUTSR130,IMU Test and Set Register 130"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x2 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x2 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x3 "IMUTSR131,IMU Test and Set Register 131"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x3 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x3 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x4 "IMUTSR132,IMU Test and Set Register 132"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x4 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x4 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x5 "IMUTSR133,IMU Test and Set Register 133"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x5 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x5 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x6 "IMUTSR134,IMU Test and Set Register 134"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x6 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x6 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x7 "IMUTSR135,IMU Test and Set Register 135"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x7 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x7 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x8 "IMUTSR136,IMU Test and Set Register 136"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x8 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x8 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x9 "IMUTSR137,IMU Test and Set Register 137"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x9 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x9 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0xA "IMUTSR138,IMU Test and Set Register 138"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0xA 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0xA 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0xB "IMUTSR139,IMU Test and Set Register 139"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0xB 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0xB 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0xC "IMUTSR140,IMU Test and Set Register 140"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0xC 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0xC 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0xD "IMUTSR141,IMU Test and Set Register 141"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0xD 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0xD 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0xE "IMUTSR142,IMU Test and Set Register 142"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0xE 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0xE 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0xF "IMUTSR143,IMU Test and Set Register 143"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0xF 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0xF 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x10 "IMUTSR144,IMU Test and Set Register 144"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x10 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x10 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x11 "IMUTSR145,IMU Test and Set Register 145"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x11 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x11 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x12 "IMUTSR146,IMU Test and Set Register 146"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x12 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x12 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x13 "IMUTSR147,IMU Test and Set Register 147"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x13 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x13 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x14 "IMUTSR148,IMU Test and Set Register 148"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x14 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x14 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x15 "IMUTSR149,IMU Test and Set Register 149"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x15 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x15 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x16 "IMUTSR150,IMU Test and Set Register 150"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x16 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x16 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x17 "IMUTSR151,IMU Test and Set Register 151"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x17 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x17 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x18 "IMUTSR152,IMU Test and Set Register 152"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x18 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x18 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x19 "IMUTSR153,IMU Test and Set Register 153"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x19 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x19 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x1A "IMUTSR154,IMU Test and Set Register 154"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x1A 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x1A 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x1B "IMUTSR155,IMU Test and Set Register 155"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x1B 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x1B 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x1C "IMUTSR156,IMU Test and Set Register 156"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x1C 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x1C 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x1D "IMUTSR157,IMU Test and Set Register 157"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x1D 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x1D 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x1E "IMUTSR158,IMU Test and Set Register 158"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x1E 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x1E 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x1F "IMUTSR159,IMU Test and Set Register 159"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x1F 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x1F 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x20 "IMUTSR160,IMU Test and Set Register 160"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x20 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x20 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x21 "IMUTSR161,IMU Test and Set Register 161"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x21 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x21 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x22 "IMUTSR162,IMU Test and Set Register 162"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x22 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x22 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x23 "IMUTSR163,IMU Test and Set Register 163"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x23 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x23 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x24 "IMUTSR164,IMU Test and Set Register 164"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x24 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x24 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x25 "IMUTSR165,IMU Test and Set Register 165"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x25 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x25 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x26 "IMUTSR166,IMU Test and Set Register 166"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x26 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x26 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x27 "IMUTSR167,IMU Test and Set Register 167"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x27 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x27 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x28 "IMUTSR168,IMU Test and Set Register 168"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x28 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x28 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x29 "IMUTSR169,IMU Test and Set Register 169"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x29 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x29 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x2A "IMUTSR170,IMU Test and Set Register 170"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x2A 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x2A 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x2B "IMUTSR171,IMU Test and Set Register 171"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x2B 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x2B 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x2C "IMUTSR172,IMU Test and Set Register 172"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x2C 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x2C 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x2D "IMUTSR173,IMU Test and Set Register 173"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x2D 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x2D 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x2E "IMUTSR174,IMU Test and Set Register 174"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x2E 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x2E 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x2F "IMUTSR175,IMU Test and Set Register 175"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x2F 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x2F 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x30 "IMUTSR176,IMU Test and Set Register 176"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x30 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x30 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x31 "IMUTSR177,IMU Test and Set Register 177"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x31 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x31 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x32 "IMUTSR178,IMU Test and Set Register 178"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x32 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x32 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x33 "IMUTSR179,IMU Test and Set Register 179"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x33 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x33 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x34 "IMUTSR180,IMU Test and Set Register 180"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x34 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x34 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x35 "IMUTSR181,IMU Test and Set Register 181"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x35 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x35 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x36 "IMUTSR182,IMU Test and Set Register 182"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x36 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x36 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x37 "IMUTSR183,IMU Test and Set Register 183"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x37 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x37 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x38 "IMUTSR184,IMU Test and Set Register 184"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x38 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x38 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x39 "IMUTSR185,IMU Test and Set Register 185"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x39 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x39 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x3A "IMUTSR186,IMU Test and Set Register 186"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x3A 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x3A 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x3B "IMUTSR187,IMU Test and Set Register 187"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x3B 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x3B 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x3C "IMUTSR188,IMU Test and Set Register 188"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x3C 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x3C 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x3D "IMUTSR189,IMU Test and Set Register 189"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x3D 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x3D 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x3E "IMUTSR190,IMU Test and Set Register 190"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x3E 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x3E 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x3F "IMUTSR191,IMU Test and Set Register 191"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x3F 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x3F 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x40 "IMUTSR192,IMU Test and Set Register 192"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x40 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x40 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x41 "IMUTSR193,IMU Test and Set Register 193"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x41 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x41 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x42 "IMUTSR194,IMU Test and Set Register 194"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x42 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x42 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x43 "IMUTSR195,IMU Test and Set Register 195"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x43 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x43 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x44 "IMUTSR196,IMU Test and Set Register 196"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x44 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x44 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x45 "IMUTSR197,IMU Test and Set Register 197"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x45 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x45 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x46 "IMUTSR198,IMU Test and Set Register 198"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x46 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x46 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x47 "IMUTSR199,IMU Test and Set Register 199"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x47 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x47 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x48 "IMUTSR200,IMU Test and Set Register 200"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x48 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x48 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x49 "IMUTSR201,IMU Test and Set Register 201"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x49 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x49 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x4A "IMUTSR202,IMU Test and Set Register 202"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x4A 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x4A 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x4B "IMUTSR203,IMU Test and Set Register 203"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x4B 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x4B 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x4C "IMUTSR204,IMU Test and Set Register 204"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x4C 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x4C 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x4D "IMUTSR205,IMU Test and Set Register 205"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x4D 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x4D 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x4E "IMUTSR206,IMU Test and Set Register 206"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x4E 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x4E 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x4F "IMUTSR207,IMU Test and Set Register 207"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x4F 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x4F 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x50 "IMUTSR208,IMU Test and Set Register 208"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x50 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x50 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x51 "IMUTSR209,IMU Test and Set Register 209"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x51 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x51 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x52 "IMUTSR210,IMU Test and Set Register 210"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x52 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x52 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x53 "IMUTSR211,IMU Test and Set Register 211"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x53 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x53 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x54 "IMUTSR212,IMU Test and Set Register 212"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x54 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x54 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x55 "IMUTSR213,IMU Test and Set Register 213"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x55 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x55 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x56 "IMUTSR214,IMU Test and Set Register 214"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x56 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x56 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x57 "IMUTSR215,IMU Test and Set Register 215"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x57 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x57 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x58 "IMUTSR216,IMU Test and Set Register 216"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x58 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x58 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x59 "IMUTSR217,IMU Test and Set Register 217"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x59 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x59 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x5A "IMUTSR218,IMU Test and Set Register 218"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x5A 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x5A 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x5B "IMUTSR219,IMU Test and Set Register 219"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x5B 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x5B 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x5C "IMUTSR220,IMU Test and Set Register 220"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x5C 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x5C 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x5D "IMUTSR221,IMU Test and Set Register 221"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x5D 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x5D 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x5E "IMUTSR222,IMU Test and Set Register 222"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x5E 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x5E 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x5F "IMUTSR223,IMU Test and Set Register 223"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x5F 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x5F 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x60 "IMUTSR224,IMU Test and Set Register 224"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x60 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x60 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x61 "IMUTSR225,IMU Test and Set Register 225"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x61 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x61 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x62 "IMUTSR226,IMU Test and Set Register 226"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x62 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x62 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x63 "IMUTSR227,IMU Test and Set Register 227"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x63 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x63 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x64 "IMUTSR228,IMU Test and Set Register 228"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x64 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x64 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x65 "IMUTSR229,IMU Test and Set Register 229"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x65 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x65 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x66 "IMUTSR230,IMU Test and Set Register 230"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x66 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x66 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x67 "IMUTSR231,IMU Test and Set Register 231"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x67 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x67 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x68 "IMUTSR232,IMU Test and Set Register 232"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x68 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x68 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x69 "IMUTSR233,IMU Test and Set Register 233"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x69 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x69 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x6A "IMUTSR234,IMU Test and Set Register 234"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x6A 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x6A 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x6B "IMUTSR235,IMU Test and Set Register 235"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x6B 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x6B 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x6C "IMUTSR236,IMU Test and Set Register 236"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x6C 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x6C 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x6D "IMUTSR237,IMU Test and Set Register 237"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x6D 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x6D 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x6E "IMUTSR238,IMU Test and Set Register 238"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x6E 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x6E 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x6F "IMUTSR239,IMU Test and Set Register 239"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x6F 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x6F 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x70 "IMUTSR240,IMU Test and Set Register 240"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x70 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x70 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x71 "IMUTSR241,IMU Test and Set Register 241"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x71 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x71 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x72 "IMUTSR242,IMU Test and Set Register 242"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x72 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x72 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x73 "IMUTSR243,IMU Test and Set Register 243"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x73 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x73 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x74 "IMUTSR244,IMU Test and Set Register 244"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x74 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x74 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x75 "IMUTSR245,IMU Test and Set Register 245"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x75 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x75 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x76 "IMUTSR246,IMU Test and Set Register 246"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x76 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x76 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x77 "IMUTSR247,IMU Test and Set Register 247"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x77 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x77 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x78 "IMUTSR248,IMU Test and Set Register 248"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x78 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x78 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x79 "IMUTSR249,IMU Test and Set Register 249"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x79 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x79 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x7A "IMUTSR250,IMU Test and Set Register 250"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x7A 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x7A 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x7B "IMUTSR251,IMU Test and Set Register 251"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x7B 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x7B 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x7C "IMUTSR252,IMU Test and Set Register 252"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x7C 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x7C 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x7D "IMUTSR253,IMU Test and Set Register 253"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x7D 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x7D 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x7E "IMUTSR254,IMU Test and Set Register 254"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x7E 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x7E 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x7F "IMUTSR255,IMU Test and Set Register 255"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x7F 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x7F 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
tree.end
|
|
tree "IMUTSR 256 - 383"
|
|
group.byte 0x200++0x7f
|
|
line.byte 0x0 "IMUTSR256,IMU Test and Set Register 256"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x0 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x0 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x1 "IMUTSR257,IMU Test and Set Register 257"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x1 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x1 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x2 "IMUTSR258,IMU Test and Set Register 258"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x2 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x2 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x3 "IMUTSR259,IMU Test and Set Register 259"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x3 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x3 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x4 "IMUTSR260,IMU Test and Set Register 260"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x4 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x4 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x5 "IMUTSR261,IMU Test and Set Register 261"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x5 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x5 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x6 "IMUTSR262,IMU Test and Set Register 262"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x6 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x6 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x7 "IMUTSR263,IMU Test and Set Register 263"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x7 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x7 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x8 "IMUTSR264,IMU Test and Set Register 264"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x8 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x8 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x9 "IMUTSR265,IMU Test and Set Register 265"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x9 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x9 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0xA "IMUTSR266,IMU Test and Set Register 266"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0xA 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0xA 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0xB "IMUTSR267,IMU Test and Set Register 267"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0xB 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0xB 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0xC "IMUTSR268,IMU Test and Set Register 268"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0xC 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0xC 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0xD "IMUTSR269,IMU Test and Set Register 269"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0xD 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0xD 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0xE "IMUTSR270,IMU Test and Set Register 270"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0xE 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0xE 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0xF "IMUTSR271,IMU Test and Set Register 271"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0xF 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0xF 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x10 "IMUTSR272,IMU Test and Set Register 272"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x10 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x10 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x11 "IMUTSR273,IMU Test and Set Register 273"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x11 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x11 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x12 "IMUTSR274,IMU Test and Set Register 274"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x12 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x12 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x13 "IMUTSR275,IMU Test and Set Register 275"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x13 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x13 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x14 "IMUTSR276,IMU Test and Set Register 276"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x14 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x14 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x15 "IMUTSR277,IMU Test and Set Register 277"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x15 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x15 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x16 "IMUTSR278,IMU Test and Set Register 278"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x16 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x16 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x17 "IMUTSR279,IMU Test and Set Register 279"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x17 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x17 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x18 "IMUTSR280,IMU Test and Set Register 280"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x18 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x18 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x19 "IMUTSR281,IMU Test and Set Register 281"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x19 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x19 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x1A "IMUTSR282,IMU Test and Set Register 282"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x1A 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x1A 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x1B "IMUTSR283,IMU Test and Set Register 283"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x1B 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x1B 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x1C "IMUTSR284,IMU Test and Set Register 284"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x1C 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x1C 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x1D "IMUTSR285,IMU Test and Set Register 285"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x1D 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x1D 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x1E "IMUTSR286,IMU Test and Set Register 286"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x1E 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x1E 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x1F "IMUTSR287,IMU Test and Set Register 287"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x1F 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x1F 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x20 "IMUTSR288,IMU Test and Set Register 288"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x20 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x20 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x21 "IMUTSR289,IMU Test and Set Register 289"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x21 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x21 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x22 "IMUTSR290,IMU Test and Set Register 290"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x22 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x22 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x23 "IMUTSR291,IMU Test and Set Register 291"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x23 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x23 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x24 "IMUTSR292,IMU Test and Set Register 292"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x24 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x24 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x25 "IMUTSR293,IMU Test and Set Register 293"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x25 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x25 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x26 "IMUTSR294,IMU Test and Set Register 294"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x26 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x26 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x27 "IMUTSR295,IMU Test and Set Register 295"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x27 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x27 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x28 "IMUTSR296,IMU Test and Set Register 296"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x28 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x28 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x29 "IMUTSR297,IMU Test and Set Register 297"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x29 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x29 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x2A "IMUTSR298,IMU Test and Set Register 298"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x2A 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x2A 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x2B "IMUTSR299,IMU Test and Set Register 299"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x2B 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x2B 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x2C "IMUTSR300,IMU Test and Set Register 300"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x2C 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x2C 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x2D "IMUTSR301,IMU Test and Set Register 301"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x2D 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x2D 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x2E "IMUTSR302,IMU Test and Set Register 302"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x2E 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x2E 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x2F "IMUTSR303,IMU Test and Set Register 303"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x2F 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x2F 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x30 "IMUTSR304,IMU Test and Set Register 304"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x30 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x30 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x31 "IMUTSR305,IMU Test and Set Register 305"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x31 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x31 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x32 "IMUTSR306,IMU Test and Set Register 306"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x32 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x32 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x33 "IMUTSR307,IMU Test and Set Register 307"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x33 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x33 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x34 "IMUTSR308,IMU Test and Set Register 308"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x34 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x34 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x35 "IMUTSR309,IMU Test and Set Register 309"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x35 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x35 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x36 "IMUTSR310,IMU Test and Set Register 310"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x36 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x36 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x37 "IMUTSR311,IMU Test and Set Register 311"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x37 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x37 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x38 "IMUTSR312,IMU Test and Set Register 312"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x38 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x38 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x39 "IMUTSR313,IMU Test and Set Register 313"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x39 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x39 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x3A "IMUTSR314,IMU Test and Set Register 314"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x3A 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x3A 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x3B "IMUTSR315,IMU Test and Set Register 315"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x3B 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x3B 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x3C "IMUTSR316,IMU Test and Set Register 316"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x3C 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x3C 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x3D "IMUTSR317,IMU Test and Set Register 317"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x3D 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x3D 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x3E "IMUTSR318,IMU Test and Set Register 318"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x3E 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x3E 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x3F "IMUTSR319,IMU Test and Set Register 319"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x3F 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x3F 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x40 "IMUTSR320,IMU Test and Set Register 320"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x40 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x40 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x41 "IMUTSR321,IMU Test and Set Register 321"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x41 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x41 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x42 "IMUTSR322,IMU Test and Set Register 322"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x42 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x42 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x43 "IMUTSR323,IMU Test and Set Register 323"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x43 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x43 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x44 "IMUTSR324,IMU Test and Set Register 324"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x44 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x44 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x45 "IMUTSR325,IMU Test and Set Register 325"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x45 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x45 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x46 "IMUTSR326,IMU Test and Set Register 326"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x46 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x46 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x47 "IMUTSR327,IMU Test and Set Register 327"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x47 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x47 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x48 "IMUTSR328,IMU Test and Set Register 328"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x48 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x48 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x49 "IMUTSR329,IMU Test and Set Register 329"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x49 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x49 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x4A "IMUTSR330,IMU Test and Set Register 330"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x4A 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x4A 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x4B "IMUTSR331,IMU Test and Set Register 331"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x4B 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x4B 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x4C "IMUTSR332,IMU Test and Set Register 332"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x4C 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x4C 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x4D "IMUTSR333,IMU Test and Set Register 333"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x4D 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x4D 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x4E "IMUTSR334,IMU Test and Set Register 334"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x4E 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x4E 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x4F "IMUTSR335,IMU Test and Set Register 335"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x4F 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x4F 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x50 "IMUTSR336,IMU Test and Set Register 336"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x50 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x50 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x51 "IMUTSR337,IMU Test and Set Register 337"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x51 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x51 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x52 "IMUTSR338,IMU Test and Set Register 338"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x52 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x52 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x53 "IMUTSR339,IMU Test and Set Register 339"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x53 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x53 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x54 "IMUTSR340,IMU Test and Set Register 340"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x54 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x54 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x55 "IMUTSR341,IMU Test and Set Register 341"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x55 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x55 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x56 "IMUTSR342,IMU Test and Set Register 342"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x56 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x56 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x57 "IMUTSR343,IMU Test and Set Register 343"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x57 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x57 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x58 "IMUTSR344,IMU Test and Set Register 344"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x58 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x58 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x59 "IMUTSR345,IMU Test and Set Register 345"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x59 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x59 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x5A "IMUTSR346,IMU Test and Set Register 346"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x5A 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x5A 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x5B "IMUTSR347,IMU Test and Set Register 347"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x5B 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x5B 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x5C "IMUTSR348,IMU Test and Set Register 348"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x5C 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x5C 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x5D "IMUTSR349,IMU Test and Set Register 349"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x5D 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x5D 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x5E "IMUTSR350,IMU Test and Set Register 350"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x5E 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x5E 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x5F "IMUTSR351,IMU Test and Set Register 351"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x5F 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x5F 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x60 "IMUTSR352,IMU Test and Set Register 352"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x60 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x60 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x61 "IMUTSR353,IMU Test and Set Register 353"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x61 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x61 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x62 "IMUTSR354,IMU Test and Set Register 354"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x62 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x62 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x63 "IMUTSR355,IMU Test and Set Register 355"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x63 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x63 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x64 "IMUTSR356,IMU Test and Set Register 356"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x64 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x64 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x65 "IMUTSR357,IMU Test and Set Register 357"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x65 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x65 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x66 "IMUTSR358,IMU Test and Set Register 358"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x66 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x66 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x67 "IMUTSR359,IMU Test and Set Register 359"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x67 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x67 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x68 "IMUTSR360,IMU Test and Set Register 360"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x68 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x68 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x69 "IMUTSR361,IMU Test and Set Register 361"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x69 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x69 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x6A "IMUTSR362,IMU Test and Set Register 362"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x6A 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x6A 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x6B "IMUTSR363,IMU Test and Set Register 363"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x6B 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x6B 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x6C "IMUTSR364,IMU Test and Set Register 364"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x6C 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x6C 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x6D "IMUTSR365,IMU Test and Set Register 365"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x6D 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x6D 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x6E "IMUTSR366,IMU Test and Set Register 366"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x6E 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x6E 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x6F "IMUTSR367,IMU Test and Set Register 367"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x6F 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x6F 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x70 "IMUTSR368,IMU Test and Set Register 368"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x70 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x70 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x71 "IMUTSR369,IMU Test and Set Register 369"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x71 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x71 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x72 "IMUTSR370,IMU Test and Set Register 370"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x72 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x72 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x73 "IMUTSR371,IMU Test and Set Register 371"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x73 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x73 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x74 "IMUTSR372,IMU Test and Set Register 372"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x74 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x74 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x75 "IMUTSR373,IMU Test and Set Register 373"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x75 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x75 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x76 "IMUTSR374,IMU Test and Set Register 374"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x76 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x76 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x77 "IMUTSR375,IMU Test and Set Register 375"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x77 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x77 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x78 "IMUTSR376,IMU Test and Set Register 376"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x78 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x78 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x79 "IMUTSR377,IMU Test and Set Register 377"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x79 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x79 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x7A "IMUTSR378,IMU Test and Set Register 378"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x7A 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x7A 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x7B "IMUTSR379,IMU Test and Set Register 379"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x7B 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x7B 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x7C "IMUTSR380,IMU Test and Set Register 380"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x7C 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x7C 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x7D "IMUTSR381,IMU Test and Set Register 381"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x7D 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x7D 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x7E "IMUTSR382,IMU Test and Set Register 382"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x7E 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x7E 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x7F "IMUTSR383,IMU Test and Set Register 383"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x7F 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x7F 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
tree.end
|
|
tree "IMUTSR 384 - 511"
|
|
group.byte 0x280++0x7f
|
|
line.byte 0x0 "IMUTSR384,IMU Test and Set Register 384"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x0 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x0 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x1 "IMUTSR385,IMU Test and Set Register 385"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x1 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x1 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x2 "IMUTSR386,IMU Test and Set Register 386"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x2 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x2 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x3 "IMUTSR387,IMU Test and Set Register 387"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x3 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x3 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x4 "IMUTSR388,IMU Test and Set Register 388"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x4 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x4 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x5 "IMUTSR389,IMU Test and Set Register 389"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x5 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x5 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x6 "IMUTSR390,IMU Test and Set Register 390"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x6 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x6 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x7 "IMUTSR391,IMU Test and Set Register 391"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x7 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x7 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x8 "IMUTSR392,IMU Test and Set Register 392"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x8 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x8 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x9 "IMUTSR393,IMU Test and Set Register 393"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x9 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x9 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0xA "IMUTSR394,IMU Test and Set Register 394"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0xA 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0xA 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0xB "IMUTSR395,IMU Test and Set Register 395"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0xB 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0xB 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0xC "IMUTSR396,IMU Test and Set Register 396"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0xC 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0xC 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0xD "IMUTSR397,IMU Test and Set Register 397"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0xD 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0xD 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0xE "IMUTSR398,IMU Test and Set Register 398"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0xE 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0xE 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0xF "IMUTSR399,IMU Test and Set Register 399"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0xF 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0xF 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x10 "IMUTSR400,IMU Test and Set Register 400"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x10 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x10 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x11 "IMUTSR401,IMU Test and Set Register 401"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x11 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x11 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x12 "IMUTSR402,IMU Test and Set Register 402"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x12 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x12 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x13 "IMUTSR403,IMU Test and Set Register 403"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x13 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x13 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x14 "IMUTSR404,IMU Test and Set Register 404"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x14 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x14 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x15 "IMUTSR405,IMU Test and Set Register 405"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x15 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x15 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x16 "IMUTSR406,IMU Test and Set Register 406"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x16 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x16 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x17 "IMUTSR407,IMU Test and Set Register 407"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x17 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x17 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x18 "IMUTSR408,IMU Test and Set Register 408"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x18 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x18 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x19 "IMUTSR409,IMU Test and Set Register 409"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x19 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x19 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x1A "IMUTSR410,IMU Test and Set Register 410"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x1A 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x1A 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x1B "IMUTSR411,IMU Test and Set Register 411"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x1B 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x1B 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x1C "IMUTSR412,IMU Test and Set Register 412"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x1C 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x1C 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x1D "IMUTSR413,IMU Test and Set Register 413"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x1D 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x1D 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x1E "IMUTSR414,IMU Test and Set Register 414"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x1E 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x1E 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x1F "IMUTSR415,IMU Test and Set Register 415"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x1F 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x1F 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x20 "IMUTSR416,IMU Test and Set Register 416"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x20 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x20 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x21 "IMUTSR417,IMU Test and Set Register 417"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x21 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x21 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x22 "IMUTSR418,IMU Test and Set Register 418"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x22 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x22 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x23 "IMUTSR419,IMU Test and Set Register 419"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x23 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x23 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x24 "IMUTSR420,IMU Test and Set Register 420"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x24 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x24 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x25 "IMUTSR421,IMU Test and Set Register 421"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x25 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x25 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x26 "IMUTSR422,IMU Test and Set Register 422"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x26 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x26 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x27 "IMUTSR423,IMU Test and Set Register 423"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x27 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x27 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x28 "IMUTSR424,IMU Test and Set Register 424"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x28 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x28 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x29 "IMUTSR425,IMU Test and Set Register 425"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x29 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x29 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x2A "IMUTSR426,IMU Test and Set Register 426"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x2A 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x2A 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x2B "IMUTSR427,IMU Test and Set Register 427"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x2B 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x2B 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x2C "IMUTSR428,IMU Test and Set Register 428"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x2C 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x2C 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x2D "IMUTSR429,IMU Test and Set Register 429"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x2D 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x2D 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x2E "IMUTSR430,IMU Test and Set Register 430"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x2E 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x2E 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x2F "IMUTSR431,IMU Test and Set Register 431"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x2F 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x2F 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x30 "IMUTSR432,IMU Test and Set Register 432"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x30 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x30 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x31 "IMUTSR433,IMU Test and Set Register 433"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x31 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x31 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x32 "IMUTSR434,IMU Test and Set Register 434"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x32 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x32 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x33 "IMUTSR435,IMU Test and Set Register 435"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x33 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x33 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x34 "IMUTSR436,IMU Test and Set Register 436"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x34 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x34 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x35 "IMUTSR437,IMU Test and Set Register 437"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x35 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x35 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x36 "IMUTSR438,IMU Test and Set Register 438"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x36 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x36 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x37 "IMUTSR439,IMU Test and Set Register 439"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x37 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x37 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x38 "IMUTSR440,IMU Test and Set Register 440"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x38 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x38 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x39 "IMUTSR441,IMU Test and Set Register 441"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x39 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x39 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x3A "IMUTSR442,IMU Test and Set Register 442"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x3A 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x3A 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x3B "IMUTSR443,IMU Test and Set Register 443"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x3B 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x3B 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x3C "IMUTSR444,IMU Test and Set Register 444"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x3C 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x3C 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x3D "IMUTSR445,IMU Test and Set Register 445"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x3D 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x3D 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x3E "IMUTSR446,IMU Test and Set Register 446"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x3E 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x3E 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x3F "IMUTSR447,IMU Test and Set Register 447"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x3F 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x3F 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x40 "IMUTSR448,IMU Test and Set Register 448"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x40 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x40 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x41 "IMUTSR449,IMU Test and Set Register 449"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x41 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x41 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x42 "IMUTSR450,IMU Test and Set Register 450"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x42 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x42 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x43 "IMUTSR451,IMU Test and Set Register 451"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x43 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x43 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x44 "IMUTSR452,IMU Test and Set Register 452"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x44 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x44 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x45 "IMUTSR453,IMU Test and Set Register 453"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x45 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x45 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x46 "IMUTSR454,IMU Test and Set Register 454"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x46 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x46 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x47 "IMUTSR455,IMU Test and Set Register 455"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x47 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x47 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x48 "IMUTSR456,IMU Test and Set Register 456"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x48 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x48 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x49 "IMUTSR457,IMU Test and Set Register 457"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x49 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x49 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x4A "IMUTSR458,IMU Test and Set Register 458"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x4A 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x4A 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x4B "IMUTSR459,IMU Test and Set Register 459"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x4B 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x4B 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x4C "IMUTSR460,IMU Test and Set Register 460"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x4C 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x4C 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x4D "IMUTSR461,IMU Test and Set Register 461"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x4D 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x4D 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x4E "IMUTSR462,IMU Test and Set Register 462"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x4E 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x4E 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x4F "IMUTSR463,IMU Test and Set Register 463"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x4F 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x4F 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x50 "IMUTSR464,IMU Test and Set Register 464"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x50 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x50 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x51 "IMUTSR465,IMU Test and Set Register 465"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x51 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x51 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x52 "IMUTSR466,IMU Test and Set Register 466"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x52 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x52 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x53 "IMUTSR467,IMU Test and Set Register 467"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x53 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x53 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x54 "IMUTSR468,IMU Test and Set Register 468"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x54 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x54 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x55 "IMUTSR469,IMU Test and Set Register 469"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x55 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x55 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x56 "IMUTSR470,IMU Test and Set Register 470"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x56 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x56 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x57 "IMUTSR471,IMU Test and Set Register 471"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x57 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x57 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x58 "IMUTSR472,IMU Test and Set Register 472"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x58 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x58 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x59 "IMUTSR473,IMU Test and Set Register 473"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x59 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x59 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x5A "IMUTSR474,IMU Test and Set Register 474"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x5A 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x5A 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x5B "IMUTSR475,IMU Test and Set Register 475"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x5B 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x5B 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x5C "IMUTSR476,IMU Test and Set Register 476"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x5C 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x5C 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x5D "IMUTSR477,IMU Test and Set Register 477"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x5D 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x5D 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x5E "IMUTSR478,IMU Test and Set Register 478"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x5E 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x5E 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x5F "IMUTSR479,IMU Test and Set Register 479"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x5F 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x5F 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x60 "IMUTSR480,IMU Test and Set Register 480"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x60 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x60 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x61 "IMUTSR481,IMU Test and Set Register 481"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x61 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x61 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x62 "IMUTSR482,IMU Test and Set Register 482"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x62 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x62 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x63 "IMUTSR483,IMU Test and Set Register 483"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x63 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x63 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x64 "IMUTSR484,IMU Test and Set Register 484"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x64 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x64 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x65 "IMUTSR485,IMU Test and Set Register 485"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x65 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x65 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x66 "IMUTSR486,IMU Test and Set Register 486"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x66 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x66 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x67 "IMUTSR487,IMU Test and Set Register 487"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x67 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x67 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x68 "IMUTSR488,IMU Test and Set Register 488"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x68 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x68 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x69 "IMUTSR489,IMU Test and Set Register 489"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x69 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x69 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x6A "IMUTSR490,IMU Test and Set Register 490"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x6A 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x6A 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x6B "IMUTSR491,IMU Test and Set Register 491"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x6B 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x6B 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x6C "IMUTSR492,IMU Test and Set Register 492"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x6C 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x6C 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x6D "IMUTSR493,IMU Test and Set Register 493"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x6D 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x6D 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x6E "IMUTSR494,IMU Test and Set Register 494"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x6E 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x6E 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x6F "IMUTSR495,IMU Test and Set Register 495"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x6F 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x6F 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x70 "IMUTSR496,IMU Test and Set Register 496"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x70 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x70 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x71 "IMUTSR497,IMU Test and Set Register 497"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x71 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x71 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x72 "IMUTSR498,IMU Test and Set Register 498"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x72 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x72 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x73 "IMUTSR499,IMU Test and Set Register 499"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x73 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x73 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x74 "IMUTSR500,IMU Test and Set Register 500"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x74 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x74 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x75 "IMUTSR501,IMU Test and Set Register 501"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x75 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x75 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x76 "IMUTSR502,IMU Test and Set Register 502"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x76 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x76 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x77 "IMUTSR503,IMU Test and Set Register 503"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x77 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x77 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x78 "IMUTSR504,IMU Test and Set Register 504"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x78 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x78 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x79 "IMUTSR505,IMU Test and Set Register 505"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x79 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x79 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x7A "IMUTSR506,IMU Test and Set Register 506"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x7A 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x7A 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x7B "IMUTSR507,IMU Test and Set Register 507"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x7B 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x7B 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x7C "IMUTSR508,IMU Test and Set Register 508"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x7C 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x7C 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x7D "IMUTSR509,IMU Test and Set Register 509"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x7D 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x7D 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x7E "IMUTSR510,IMU Test and Set Register 510"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x7E 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x7E 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
line.byte 0x7F "IMUTSR511,IMU Test and Set Register 511"
|
|
sif (cpu()=="I81342")||(cpu()=="I81348")
|
|
bitfld.byte 0x7F 1. " BIT1 ,Intel XScale processor 1 bit" "0,1"
|
|
endif
|
|
bitfld.byte 0x7F 0. " BIT0 ,Intel XScale processor 0 bit" "0,1"
|
|
tree.end
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree.open "UART (Universal Asynchronous Receiver/Transmitter)"
|
|
tree "UART 0"
|
|
base asd:(0x0:0xFFD80000+0x2300)
|
|
width 0xb
|
|
if ((d.b(asd:(0x0:0xFFD80000+0x2300)+0xC)&0x80)==0x80)
|
|
; Divisor Latch Registers Access == DLL and DLH
|
|
group.byte 0x00++0x0
|
|
line.byte 0x00 "U0DLL,UART 0 Divisor Latch Register Low Byte"
|
|
group.byte 0x04++0x0
|
|
line.byte 0x00 "U0DLH,UART 0 Divisor Latch Register High Byte"
|
|
else
|
|
; == THR, RBR and Interrupt Enable Registers
|
|
hgroup.byte 0x00++0x0
|
|
hide.byte 0x00 "U0RBR/U0THR,Receive Buffer/Transmit Holding Register"
|
|
in
|
|
group.byte 0x04++0x0
|
|
line.byte 0x00 "U0IER,UART 0 Interrupt Enable Register"
|
|
bitfld.byte 0x00 6. " UUE ,UART Unit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " NRZE ,NRZ Coding Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RTOIE ,Receiver Time-out Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MIE ,Modem Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RLSE ,Receiver Line Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " TIE ,Transmit Data Request Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " RAVIE ,Receiver Data Available Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.byte 0x08++0x0
|
|
line.byte 0x00 "U0IIR,UART 0 Interrupt Identification Register"
|
|
bitfld.byte 0x00 6.--7. " FIFOES ,FIFO Mode Enable Status" "Non-FIFO,Reserved,Reserved,FIFO"
|
|
bitfld.byte 0x00 4. " ABL ,Auto-baud Lock" "Not locked,Locked"
|
|
bitfld.byte 0x00 3. " TOD ,Time Out Detected" "No time-out,Time-out"
|
|
textline " "
|
|
bitfld.byte 0x00 1.--2. " IID ,Interrupt Source Encoded" "Modem Status,Transmit FIFO,Received data,Receive error"
|
|
bitfld.byte 0x00 0. " IP ,Interrupt Pending" "Pending,Not pending"
|
|
wgroup.byte 0x08++0x0
|
|
line.byte 0x00 "U0FCR,UART 0 FIFO Control Register"
|
|
bitfld.byte 0x00 6.--7. " ITL ,Interrupt Trigger Level" ">=1 byte ,>=8 bytes,>=16 bytes,>=32 bytes"
|
|
bitfld.byte 0x00 3. " TIL ,Transmitter Interrupt Level " "FIFO half empty,FIFO empty"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RESETTF ,Reset Transmitter FIFO" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " RESETRF ,Reset Receive FIFO" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TRFIFOE ,Transmit and Receive FIFO Enable" "Disabled,Enabled"
|
|
if (((data.byte(asd:((0x0:0xFFD80000+0x2300)+0xC)))&0x3)==0x0)
|
|
; this -> WLS == 0 == 5-bit
|
|
group.byte 0x0C++0x0
|
|
line.byte 0x00 "U0LCR,UART 0 Line Control Register"
|
|
bitfld.byte 0x00 7. " DLAB ,Divisor Latch Access Bit" "THR/RBR/U0IER,DLL/DLH"
|
|
bitfld.byte 0x00 6. " SB ,Set Break" "No effect,Set"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " STKYP ,Sticky Parity" "No effect,Opposite of EPS"
|
|
bitfld.byte 0x00 4. " EPS ,Even Parity Select" "Odd,Even"
|
|
bitfld.byte 0x00 3. " PEN ,Parity Enable" "No parity,Parity"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " STB ,Stop Bits" "1 stop bit,1.5 stop bits"
|
|
bitfld.byte 0x00 0.--1. " WLS ,Word Length Select" "5-bit,6-bit,7-bit,8-bit"
|
|
else
|
|
group.byte 0x0C++0x0
|
|
line.byte 0x00 "U0LCR,UART 0 Line Control Register"
|
|
bitfld.byte 0x00 7. " DLAB ,Divisor Latch Access Bit" "THR/RBR/U0IER,DLL/DLH"
|
|
bitfld.byte 0x00 6. " SB ,Set Break" "No effect,Set"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " STKYP ,Sticky Parity" "No effect,Opposite of EPS"
|
|
bitfld.byte 0x00 4. " EPS ,Even Parity Select" "Odd,Even"
|
|
bitfld.byte 0x00 3. " PEN ,Parity Enable" "No parity,Parity"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " STB ,Stop Bits" "1 stop bit,2 stop bits"
|
|
bitfld.byte 0x00 0.--1. " WLS ,Word Length Select" "5-bit,6-bit,7-bit,8-bit"
|
|
endif
|
|
if (((data.byte(ad:(0x0:0xFFD80000+0x2300)+0x10))&0x20)==0x00)
|
|
; this -> AFE == 0 == Non-Autoflow
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "U0MCR,UART 0 Modem Control Register"
|
|
bitfld.byte 0x00 5. " AFE ,Autoflow Control Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LOOP ,Loopback Mode" "Normal,Loopback"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " IE ,Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RTS ,Request to Send" "RTS=1,RTS=0"
|
|
else
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "U0MCR,UART 0 Modem Control Register"
|
|
bitfld.byte 0x00 5. " AFE ,Autoflow Control Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LOOP ,Loopback Mode" "Normal,Loopback"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " IE ,Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RTS ,Request to Send" "Disabled,Enabled"
|
|
endif
|
|
rgroup.byte 0x14++0x0
|
|
line.byte 0x00 "U0LSR,UART 0 Line Status Register"
|
|
bitfld.byte 0x00 7. " FIFOE ,FIFO Error Status" "No error,Error"
|
|
bitfld.byte 0x00 6. " TEMT ,Transmitter Empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " TDRQ ,Transmit Data Request" "Not requested,Requested"
|
|
bitfld.byte 0x00 4. " BI ,Break Indicator" "No break,Break"
|
|
bitfld.byte 0x00 3. " FE ,Framing Error" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " PE ,Parity Error" "No error,Error"
|
|
bitfld.byte 0x00 1. " OE ,Overflow Error" "No error,Error"
|
|
bitfld.byte 0x00 0. " DR ,Data Ready" "Not ready,Ready"
|
|
rgroup.byte 0x18++0x0
|
|
line.byte 0x00 "U0MSR,UART 0 Modem Status Register"
|
|
bitfld.byte 0x00 4. " CTS ,Clear to Send" "CTS=1,CTS=0"
|
|
bitfld.byte 0x00 0. " DCTS ,Delta Clear to Send" "Not changed,Changed"
|
|
group.byte 0x1C++0x0
|
|
line.byte 0x00 "U0SCR,UART 0 Scratch Pad Register"
|
|
rgroup.byte 0x24++0x0
|
|
line.byte 0x00 "U0FOR,UART 0 FIFO Occupancy Register"
|
|
hexmask.byte 0x00 0.--5. 1. " FOR ,Number of bytes remaining in the receive FIFO"
|
|
group.byte 0x28++0x0
|
|
line.byte 0x00 "U0ABR,UART 0 Auto-Baud Control Register"
|
|
bitfld.byte 0x0 3. " ABT ,Table used to calculate baud rates" "Formula,Table"
|
|
bitfld.byte 0x0 2. " ABUP ,UART Programs DLL/DLH" "Software,UART"
|
|
textline " "
|
|
bitfld.byte 0x0 1. " ABLIE ,Auto-baud-lock Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 0. " ABE ,Auto-baud Enable" "Disabled,Enabled"
|
|
rgroup.word 0x2C++3
|
|
line.word 0x00 "U0ACR,Autobaud Count Register"
|
|
width 0xb
|
|
tree.end
|
|
tree "UART 1"
|
|
base asd:(0x0:0xFFD80000+0x2340)
|
|
width 0xb
|
|
if ((d.b(asd:(0x0:0xFFD80000+0x2300)+0xC)&0x80)==0x80)
|
|
; Divisor Latch Registers Access == DLL and DLH
|
|
group.byte 0x00++0x0
|
|
line.byte 0x00 "U0DLL,UART 0 Divisor Latch Register Low Byte"
|
|
group.byte 0x04++0x0
|
|
line.byte 0x00 "U0DLH,UART 0 Divisor Latch Register High Byte"
|
|
else
|
|
; == THR, RBR and Interrupt Enable Registers
|
|
hgroup.byte 0x00++0x0
|
|
hide.byte 0x00 "U0RBR/U0THR,Receive Buffer/Transmit Holding Register"
|
|
in
|
|
group.byte 0x04++0x0
|
|
line.byte 0x00 "U0IER,UART 0 Interrupt Enable Register"
|
|
bitfld.byte 0x00 6. " UUE ,UART Unit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " NRZE ,NRZ Coding Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RTOIE ,Receiver Time-out Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MIE ,Modem Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RLSE ,Receiver Line Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " TIE ,Transmit Data Request Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " RAVIE ,Receiver Data Available Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.byte 0x08++0x0
|
|
line.byte 0x00 "U0IIR,UART 0 Interrupt Identification Register"
|
|
bitfld.byte 0x00 6.--7. " FIFOES ,FIFO Mode Enable Status" "Non-FIFO,Reserved,Reserved,FIFO"
|
|
bitfld.byte 0x00 4. " ABL ,Auto-baud Lock" "Not locked,Locked"
|
|
bitfld.byte 0x00 3. " TOD ,Time Out Detected" "No time-out,Time-out"
|
|
textline " "
|
|
bitfld.byte 0x00 1.--2. " IID ,Interrupt Source Encoded" "Modem Status,Transmit FIFO,Received data,Receive error"
|
|
bitfld.byte 0x00 0. " IP ,Interrupt Pending" "Pending,Not pending"
|
|
wgroup.byte 0x08++0x0
|
|
line.byte 0x00 "U0FCR,UART 0 FIFO Control Register"
|
|
bitfld.byte 0x00 6.--7. " ITL ,Interrupt Trigger Level" ">=1 byte ,>=8 bytes,>=16 bytes,>=32 bytes"
|
|
bitfld.byte 0x00 3. " TIL ,Transmitter Interrupt Level " "FIFO half empty,FIFO empty"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RESETTF ,Reset Transmitter FIFO" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " RESETRF ,Reset Receive FIFO" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TRFIFOE ,Transmit and Receive FIFO Enable" "Disabled,Enabled"
|
|
if (((data.byte(asd:((0x0:0xFFD80000+0x2300)+0xC)))&0x3)==0x0)
|
|
; this -> WLS == 0 == 5-bit
|
|
group.byte 0x0C++0x0
|
|
line.byte 0x00 "U0LCR,UART 0 Line Control Register"
|
|
bitfld.byte 0x00 7. " DLAB ,Divisor Latch Access Bit" "THR/RBR/U0IER,DLL/DLH"
|
|
bitfld.byte 0x00 6. " SB ,Set Break" "No effect,Set"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " STKYP ,Sticky Parity" "No effect,Opposite of EPS"
|
|
bitfld.byte 0x00 4. " EPS ,Even Parity Select" "Odd,Even"
|
|
bitfld.byte 0x00 3. " PEN ,Parity Enable" "No parity,Parity"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " STB ,Stop Bits" "1 stop bit,1.5 stop bits"
|
|
bitfld.byte 0x00 0.--1. " WLS ,Word Length Select" "5-bit,6-bit,7-bit,8-bit"
|
|
else
|
|
group.byte 0x0C++0x0
|
|
line.byte 0x00 "U0LCR,UART 0 Line Control Register"
|
|
bitfld.byte 0x00 7. " DLAB ,Divisor Latch Access Bit" "THR/RBR/U0IER,DLL/DLH"
|
|
bitfld.byte 0x00 6. " SB ,Set Break" "No effect,Set"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " STKYP ,Sticky Parity" "No effect,Opposite of EPS"
|
|
bitfld.byte 0x00 4. " EPS ,Even Parity Select" "Odd,Even"
|
|
bitfld.byte 0x00 3. " PEN ,Parity Enable" "No parity,Parity"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " STB ,Stop Bits" "1 stop bit,2 stop bits"
|
|
bitfld.byte 0x00 0.--1. " WLS ,Word Length Select" "5-bit,6-bit,7-bit,8-bit"
|
|
endif
|
|
if (((data.byte(ad:(0x0:0xFFD80000+0x2300)+0x10))&0x20)==0x00)
|
|
; this -> AFE == 0 == Non-Autoflow
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "U0MCR,UART 0 Modem Control Register"
|
|
bitfld.byte 0x00 5. " AFE ,Autoflow Control Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LOOP ,Loopback Mode" "Normal,Loopback"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " IE ,Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RTS ,Request to Send" "RTS=1,RTS=0"
|
|
else
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "U0MCR,UART 0 Modem Control Register"
|
|
bitfld.byte 0x00 5. " AFE ,Autoflow Control Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LOOP ,Loopback Mode" "Normal,Loopback"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " IE ,Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RTS ,Request to Send" "Disabled,Enabled"
|
|
endif
|
|
rgroup.byte 0x14++0x0
|
|
line.byte 0x00 "U0LSR,UART 0 Line Status Register"
|
|
bitfld.byte 0x00 7. " FIFOE ,FIFO Error Status" "No error,Error"
|
|
bitfld.byte 0x00 6. " TEMT ,Transmitter Empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " TDRQ ,Transmit Data Request" "Not requested,Requested"
|
|
bitfld.byte 0x00 4. " BI ,Break Indicator" "No break,Break"
|
|
bitfld.byte 0x00 3. " FE ,Framing Error" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " PE ,Parity Error" "No error,Error"
|
|
bitfld.byte 0x00 1. " OE ,Overflow Error" "No error,Error"
|
|
bitfld.byte 0x00 0. " DR ,Data Ready" "Not ready,Ready"
|
|
rgroup.byte 0x18++0x0
|
|
line.byte 0x00 "U0MSR,UART 0 Modem Status Register"
|
|
bitfld.byte 0x00 4. " CTS ,Clear to Send" "CTS=1,CTS=0"
|
|
bitfld.byte 0x00 0. " DCTS ,Delta Clear to Send" "Not changed,Changed"
|
|
group.byte 0x1C++0x0
|
|
line.byte 0x00 "U0SCR,UART 0 Scratch Pad Register"
|
|
rgroup.byte 0x24++0x0
|
|
line.byte 0x00 "U0FOR,UART 0 FIFO Occupancy Register"
|
|
hexmask.byte 0x00 0.--5. 1. " FOR ,Number of bytes remaining in the receive FIFO"
|
|
group.byte 0x28++0x0
|
|
line.byte 0x00 "U0ABR,UART 0 Auto-Baud Control Register"
|
|
bitfld.byte 0x0 3. " ABT ,Table used to calculate baud rates" "Formula,Table"
|
|
bitfld.byte 0x0 2. " ABUP ,UART Programs DLL/DLH" "Software,UART"
|
|
textline " "
|
|
bitfld.byte 0x0 1. " ABLIE ,Auto-baud-lock Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 0. " ABE ,Auto-baud Enable" "Disabled,Enabled"
|
|
rgroup.word 0x2C++3
|
|
line.word 0x00 "U0ACR,Autobaud Count Register"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.open "I2C (Inter-Integrated Circuit)"
|
|
tree "I2C0"
|
|
base asd:(0x0:0xFFD80000+0x2500)
|
|
width 0x7
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "ICR0, I2C Control Register 0"
|
|
bitfld.long 0x00 15. " FM ,Fast Mode" "100 KBps,400 KBps"
|
|
bitfld.long 0x00 14. " UR ,Unit Reset" "No reset,Reset"
|
|
bitfld.long 0x00 13. " SADIE ,Slave Address Detected Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ALDIE ,Arbitration Loss Detected Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SSDIE ,Slave STOP Detected Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BEIE ,Bus Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 09. " IRFIE ,IDBR Receive Full Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 08. " ITEIE ,IDBR Transmit Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 07. " GCD ,General Call Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 06. " IUE ,I2C Unit Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 05. " SCLE ,SCL Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04. " MA ,Master Abort" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 03. " TB ,Transfer Byte" "No,Yes"
|
|
bitfld.long 0x00 02. " ACKNAK ,Positive/Negative Acknowledge" "ACK,NACK"
|
|
bitfld.long 0x00 01. " STOP ,Stop condition after transferring the next data byte on the I2C" "Sent,Not sent"
|
|
textline " "
|
|
bitfld.long 0x00 00. " START ,Start condition to the I2C" "Sent,Not sent"
|
|
group.long 0x4++0x3
|
|
line.long 0x00 "ISR0,I2C Status Register 0"
|
|
eventfld.long 0x00 10. " BED ,Bus Error Detected" "No error,Error"
|
|
eventfld.long 0x00 9. " SAD ,Slave Address Detected" "Not detected,Detected"
|
|
eventfld.long 0x00 8. " GCAD ,General Call Address" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 7. " IRF ,IDBR Receive Full" "Not full,Full"
|
|
eventfld.long 0x00 6. " ITE ,IDBR Transmit Empty" "Not empty,Empty"
|
|
eventfld.long 0x00 5. " ALD ,Arbitration Loss Detected" "Not lost,Lost"
|
|
textline " "
|
|
eventfld.long 0x00 4. " SSD ,Slave STOP Detected" "Not stopped,Stopped"
|
|
bitfld.long 0x00 3. " IBB ,I2C Bus Busy" "Not busy,Busy"
|
|
bitfld.long 0x00 2. " UB ,Unit Busy" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACKNACK ,Ack/Nack Status" "ACK,NACK"
|
|
bitfld.long 0x00 0. " RWM ,Read/Write Mode (Master/Slave)" "Tx/Rx,Rx/Tx"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "ISAR0, I2C Slave Address Register 0"
|
|
hexmask.long.byte 0x00 00.--06. 1. " SA ,Slave Address"
|
|
hgroup.long 0x0c++0x03
|
|
hide.long 0x00 "IDBR0, I2C Data Buffer Register 0"
|
|
in
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "IBMR0, I2C Bus Monitor Register 0"
|
|
bitfld.long 0x00 01. " SCL ,SCL Pin Status" "Low,High"
|
|
bitfld.long 0x00 00. " SDA ,SDA Pin Status" "Low,High"
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "IMBCR0,I2C Manual Bus Control Register 0"
|
|
bitfld.long 0x00 02. " SDAC ,SDA Pin Control" "Pulled Down,Not pulled down"
|
|
bitfld.long 0x00 01. " SCLC ,SCL Pin Control" "Pulled Down,Not pulled down"
|
|
bitfld.long 0x00 00. " MANUAL ,SDA and SCL Manual Control Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "I2C1"
|
|
base asd:(0x0:0xFFD80000+0x2520)
|
|
width 0x7
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "ICR1, I2C Control Register 1"
|
|
bitfld.long 0x00 15. " FM ,Fast Mode" "100 KBps,400 KBps"
|
|
bitfld.long 0x00 14. " UR ,Unit Reset" "No reset,Reset"
|
|
bitfld.long 0x00 13. " SADIE ,Slave Address Detected Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ALDIE ,Arbitration Loss Detected Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SSDIE ,Slave STOP Detected Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BEIE ,Bus Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 09. " IRFIE ,IDBR Receive Full Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 08. " ITEIE ,IDBR Transmit Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 07. " GCD ,General Call Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 06. " IUE ,I2C Unit Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 05. " SCLE ,SCL Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04. " MA ,Master Abort" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 03. " TB ,Transfer Byte" "No,Yes"
|
|
bitfld.long 0x00 02. " ACKNAK ,Positive/Negative Acknowledge" "ACK,NACK"
|
|
bitfld.long 0x00 01. " STOP ,Stop condition after transferring the next data byte on the I2C" "Sent,Not sent"
|
|
textline " "
|
|
bitfld.long 0x00 00. " START ,Start condition to the I2C" "Sent,Not sent"
|
|
group.long 0x4++0x3
|
|
line.long 0x00 "ISR1,I2C Status Register 1"
|
|
eventfld.long 0x00 10. " BED ,Bus Error Detected" "No error,Error"
|
|
eventfld.long 0x00 9. " SAD ,Slave Address Detected" "Not detected,Detected"
|
|
eventfld.long 0x00 8. " GCAD ,General Call Address" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 7. " IRF ,IDBR Receive Full" "Not full,Full"
|
|
eventfld.long 0x00 6. " ITE ,IDBR Transmit Empty" "Not empty,Empty"
|
|
eventfld.long 0x00 5. " ALD ,Arbitration Loss Detected" "Not lost,Lost"
|
|
textline " "
|
|
eventfld.long 0x00 4. " SSD ,Slave STOP Detected" "Not stopped,Stopped"
|
|
bitfld.long 0x00 3. " IBB ,I2C Bus Busy" "Not busy,Busy"
|
|
bitfld.long 0x00 2. " UB ,Unit Busy" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACKNACK ,Ack/Nack Status" "ACK,NACK"
|
|
bitfld.long 0x00 0. " RWM ,Read/Write Mode (Master/Slave)" "Tx/Rx,Rx/Tx"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "ISAR1, I2C Slave Address Register 1"
|
|
hexmask.long.byte 0x00 00.--06. 1. " SA ,Slave Address"
|
|
hgroup.long 0x0c++0x03
|
|
hide.long 0x00 "IDBR1, I2C Data Buffer Register 1"
|
|
in
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "IBMR1, I2C Bus Monitor Register 1"
|
|
bitfld.long 0x00 01. " SCL ,SCL Pin Status" "Low,High"
|
|
bitfld.long 0x00 00. " SDA ,SDA Pin Status" "Low,High"
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "IMBCR1,I2C Manual Bus Control Register 1"
|
|
bitfld.long 0x00 02. " SDAC ,SDA Pin Control" "Pulled Down,Not pulled down"
|
|
bitfld.long 0x00 01. " SCLC ,SCL Pin Control" "Pulled Down,Not pulled down"
|
|
bitfld.long 0x00 00. " MANUAL ,SDA and SCL Manual Control Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "I2C2"
|
|
base asd:(0x0:0xFFD80000+0x2540)
|
|
width 0x7
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "ICR2, I2C Control Register 2"
|
|
bitfld.long 0x00 15. " FM ,Fast Mode" "100 KBps,400 KBps"
|
|
bitfld.long 0x00 14. " UR ,Unit Reset" "No reset,Reset"
|
|
bitfld.long 0x00 13. " SADIE ,Slave Address Detected Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ALDIE ,Arbitration Loss Detected Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SSDIE ,Slave STOP Detected Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BEIE ,Bus Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 09. " IRFIE ,IDBR Receive Full Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 08. " ITEIE ,IDBR Transmit Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 07. " GCD ,General Call Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 06. " IUE ,I2C Unit Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 05. " SCLE ,SCL Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04. " MA ,Master Abort" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 03. " TB ,Transfer Byte" "No,Yes"
|
|
bitfld.long 0x00 02. " ACKNAK ,Positive/Negative Acknowledge" "ACK,NACK"
|
|
bitfld.long 0x00 01. " STOP ,Stop condition after transferring the next data byte on the I2C" "Sent,Not sent"
|
|
textline " "
|
|
bitfld.long 0x00 00. " START ,Start condition to the I2C" "Sent,Not sent"
|
|
group.long 0x4++0x3
|
|
line.long 0x00 "ISR2,I2C Status Register 2"
|
|
eventfld.long 0x00 10. " BED ,Bus Error Detected" "No error,Error"
|
|
eventfld.long 0x00 9. " SAD ,Slave Address Detected" "Not detected,Detected"
|
|
eventfld.long 0x00 8. " GCAD ,General Call Address" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 7. " IRF ,IDBR Receive Full" "Not full,Full"
|
|
eventfld.long 0x00 6. " ITE ,IDBR Transmit Empty" "Not empty,Empty"
|
|
eventfld.long 0x00 5. " ALD ,Arbitration Loss Detected" "Not lost,Lost"
|
|
textline " "
|
|
eventfld.long 0x00 4. " SSD ,Slave STOP Detected" "Not stopped,Stopped"
|
|
bitfld.long 0x00 3. " IBB ,I2C Bus Busy" "Not busy,Busy"
|
|
bitfld.long 0x00 2. " UB ,Unit Busy" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACKNACK ,Ack/Nack Status" "ACK,NACK"
|
|
bitfld.long 0x00 0. " RWM ,Read/Write Mode (Master/Slave)" "Tx/Rx,Rx/Tx"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "ISAR2, I2C Slave Address Register 2"
|
|
hexmask.long.byte 0x00 00.--06. 1. " SA ,Slave Address"
|
|
hgroup.long 0x0c++0x03
|
|
hide.long 0x00 "IDBR2, I2C Data Buffer Register 2"
|
|
in
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "IBMR2, I2C Bus Monitor Register 2"
|
|
bitfld.long 0x00 01. " SCL ,SCL Pin Status" "Low,High"
|
|
bitfld.long 0x00 00. " SDA ,SDA Pin Status" "Low,High"
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "IMBCR2,I2C Manual Bus Control Register 2"
|
|
bitfld.long 0x00 02. " SDAC ,SDA Pin Control" "Pulled Down,Not pulled down"
|
|
bitfld.long 0x00 01. " SCLC ,SCL Pin Control" "Pulled Down,Not pulled down"
|
|
bitfld.long 0x00 00. " MANUAL ,SDA and SCL Manual Control Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "GPIO (General Purpose Input/Output)"
|
|
base asd:(0x0:0xFFD80000+0x2480)
|
|
width 0x6
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "GPOE,GPIO Output Enable Register"
|
|
bitfld.long 0x00 15. " GPIO15 ,GPIO15 Output Enable" "Out,In"
|
|
bitfld.long 0x00 14. " GPIO14 ,GPIO14 Output Enable" "Out,In"
|
|
bitfld.long 0x00 13. " GPIO13 ,GPIO13 Output Enable" "Out,In"
|
|
bitfld.long 0x00 12. " GPIO12 ,GPIO12 Output Enable" "Out,In"
|
|
textline " "
|
|
bitfld.long 0x00 11. " GPIO11 ,GPIO11 Output Enable" "Out,In"
|
|
bitfld.long 0x00 10. " GPIO10 ,GPIO10 Output Enable" "Out,In"
|
|
bitfld.long 0x00 9. " GPIO9 ,GPIO9 Output Enable" "Out,In"
|
|
bitfld.long 0x00 8. " GPIO8 ,GPIO8 Output Enable" "Out,In"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GPIO7 ,GPIO7 Output Enable" "Out,In"
|
|
bitfld.long 0x00 6. " GPIO6 ,GPIO6 Output Enable" "Out,In"
|
|
bitfld.long 0x00 5. " GPIO5 ,GPIO5 Output Enable" "Out,In"
|
|
bitfld.long 0x00 4. " GPIO4 ,GPIO4 Output Enable" "Out,In"
|
|
textline " "
|
|
bitfld.long 0x00 3. " GPIO3 ,GPIO3 Output Enable" "Out,In"
|
|
bitfld.long 0x00 2. " GPIO2 ,GPIO2 Output Enable" "Out,In"
|
|
bitfld.long 0x00 1. " GPIO1 ,GPIO1 Output Enable" "Out,In"
|
|
bitfld.long 0x00 0. " GPIO0 ,GPIO0 Output Enable" "Out,In"
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x00 "GPID,GPIO Input Data Register"
|
|
bitfld.long 0x00 15. " GPIO15 ,GPIO15 Input Data" "Low,High"
|
|
bitfld.long 0x00 14. " GPIO14 ,GPIO14 Input Data" "Low,High"
|
|
bitfld.long 0x00 13. " GPIO13 ,GPIO13 Input Data" "Low,High"
|
|
bitfld.long 0x00 12. " GPIO12 ,GPIO12 Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " GPIO11 ,GPIO11 Input Data" "Low,High"
|
|
bitfld.long 0x00 10. " GPIO10 ,GPIO10 Input Data" "Low,High"
|
|
bitfld.long 0x00 9. " GPIO9 ,GPIO9 Input Data" "Low,High"
|
|
bitfld.long 0x00 8. " GPIO8 ,GPIO8 Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GPIO7 ,GPIO7 Input Data" "Low,High"
|
|
bitfld.long 0x00 6. " GPIO6 ,GPIO6 Input Data" "Low,High"
|
|
bitfld.long 0x00 5. " GPIO5 ,GPIO5 Input Data" "Low,High"
|
|
bitfld.long 0x00 4. " GPIO4 ,GPIO4 Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " GPIO3 ,GPIO3 Input Data" "Low,High"
|
|
bitfld.long 0x00 2. " GPIO2 ,GPIO2 Input Data" "Low,High"
|
|
bitfld.long 0x00 1. " GPIO1 ,GPIO1 Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " GPIO0 ,GPIO0 Input Data" "Low,High"
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "GPOD,GPIO Output Data Register"
|
|
bitfld.long 0x00 15. " GPIO15 ,GPIO15 Output Data" "Low,High"
|
|
bitfld.long 0x00 14. " GPIO14 ,GPIO14 Output Data" "Low,High"
|
|
bitfld.long 0x00 13. " GPIO13 ,GPIO13 Output Data" "Low,High"
|
|
bitfld.long 0x00 12. " GPIO12 ,GPIO12 Output Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " GPIO11 ,GPIO11 Output Data" "Low,High"
|
|
bitfld.long 0x00 10. " GPIO10 ,GPIO10 Output Data" "Low,High"
|
|
bitfld.long 0x00 9. " GPIO9 ,GPIO9 Output Data" "Low,High"
|
|
bitfld.long 0x00 8. " GPIO8 ,GPIO8 Output Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GPIO7 ,GPIO7 Output Data" "Low,High"
|
|
bitfld.long 0x00 6. " GPIO6 ,GPIO6 Output Data" "Low,High"
|
|
bitfld.long 0x00 5. " GPIO5 ,GPIO5 Output Data" "Low,High"
|
|
bitfld.long 0x00 4. " GPIO4 ,GPIO4 Output Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " GPIO3 ,GPIO3 Output Data" "Low,High"
|
|
bitfld.long 0x00 2. " GPIO2 ,GPIO2 Output Data" "Low,High"
|
|
bitfld.long 0x00 1. " GPIO1 ,GPIO1 Output Data" "Low,High"
|
|
bitfld.long 0x00 0. " GPIO0 ,GPIO0 Output Data" "Low,High"
|
|
width 0xb
|
|
tree.end
|
|
tree "PMON (Performance Monitoring)"
|
|
base asd:(0x0:0xFFD80000+0x4e000)
|
|
width 0xb
|
|
group.long 0x40++0x7
|
|
line.long 0x0 "PMONEN,PMON Feature Enable Register"
|
|
bitfld.long 0x0 1. " OUTEN ,PMON Indicator Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " INTEN , Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x04 "PMONSTAT,PMON Status Register"
|
|
eventfld.long 0x04 0. " INTSTAT ,Interrupt Status" "Not pending,Pending"
|
|
width 0xb
|
|
base asd:(0x0:0xFFD80000+0x1a000)
|
|
width 0xb
|
|
tree "Counter 0"
|
|
group.long 0x0++0xf
|
|
line.long 0x0 "PMON_CMD0,PMON Command Register 0"
|
|
bitfld.long 0x0 28. " IE ,Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 27. " IOE ,Indicator Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 26. " OUIE ,Overflow/Underflow Indicator Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " CTIE ,Command Trigger Indicator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 24. " THIE ,Threshold Indicator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 21.--23. " CC ,Condition Code" "False,Greater,Equal,Greater/Equal,Less,Not equal,Less/Equal,True"
|
|
textline " "
|
|
bitfld.long 0x0 20. " SAC ,Select ALL Counters" "One,All"
|
|
bitfld.long 0x0 16.--19. " OPC ,Opcode" "Stop,Start,Sample,Reserved,Reset,Restart,Sample/Restart,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Preload"
|
|
textline " "
|
|
bitfld.long 0x0 12.--14. " CTSS ,Command Trigger Source Select" "Port-0,Port-1,Port-2,Port-3,Port-4,Port-5,Port-6,Port-7"
|
|
hexmask.long.word 0x0 0.--11. 1. " CT ,Command Trigger"
|
|
line.long 0x4 "PMON_EVR0,PMON Event Register 0"
|
|
bitfld.long 0x4 31. " DOCE ,Decrement Occurrence Count Enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 28.--30. " DESS ,Decrement Event Source Select" "Port-0,Port-1,Port-2,Port-3,Port-4,Port-5,Port-6,Port-7"
|
|
hexmask.long.word 0x4 16.--27. 1. " DE ,Decrement Event"
|
|
textline " "
|
|
bitfld.long 0x4 15. " IOCE ,Increment Occurrence Count Enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 12.--14. " IESS ,Increment Event Source Select" "Port-0,Port-1,Port-2,Port-3,Port-4,Port-5,Port-6,Port-7"
|
|
hexmask.long.word 0x4 0.--11. 1. " IE ,Increment Event"
|
|
line.long 0x8 "PMON_STS0,PMON Status Register 0"
|
|
eventfld.long 0x8 31. " DEI ,Decrement Event Indicator" "Not detected,Detected"
|
|
eventfld.long 0x8 30. " IEI ,Increment Event Indicator" "Not detected,Detected"
|
|
bitfld.long 0x8 29. " CAI ,Counter Active Indicator" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x8 28. " IU ,In use" "Not in use,In use"
|
|
eventfld.long 0x8 27. " UEI ,Unsupported Event Indicator" "Not detected,Detected"
|
|
eventfld.long 0x8 26. " OUI ,Overflow/Underflow Indicator" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x8 25. " CTI ,Command Trigger Indicator" "Not detected,Detected"
|
|
eventfld.long 0x8 24. " THI ,Threshold Indicator" "Not detected,Detected"
|
|
hexmask.long.byte 0x8 4.--11. 1. " CP ,Clock Period"
|
|
line.long 0xc "PMON_DATA0,PMON Data Register 0"
|
|
tree.end
|
|
tree "Counter 1"
|
|
group.long 0x10++0xf
|
|
line.long 0x0 "PMON_CMD1,PMON Command Register 1"
|
|
bitfld.long 0x0 28. " IE ,Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 27. " IOE ,Indicator Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 26. " OUIE ,Overflow/Underflow Indicator Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " CTIE ,Command Trigger Indicator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 24. " THIE ,Threshold Indicator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 21.--23. " CC ,Condition Code" "False,Greater,Equal,Greater/Equal,Less,Not equal,Less/Equal,True"
|
|
textline " "
|
|
bitfld.long 0x0 20. " SAC ,Select ALL Counters" "One,All"
|
|
bitfld.long 0x0 16.--19. " OPC ,Opcode" "Stop,Start,Sample,Reserved,Reset,Restart,Sample/Restart,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Preload"
|
|
textline " "
|
|
bitfld.long 0x0 12.--14. " CTSS ,Command Trigger Source Select" "Port-0,Port-1,Port-2,Port-3,Port-4,Port-5,Port-6,Port-7"
|
|
hexmask.long.word 0x0 0.--11. 1. " CT ,Command Trigger"
|
|
line.long 0x4 "PMON_EVR1,PMON Event Register 1"
|
|
bitfld.long 0x4 31. " DOCE ,Decrement Occurrence Count Enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 28.--30. " DESS ,Decrement Event Source Select" "Port-0,Port-1,Port-2,Port-3,Port-4,Port-5,Port-6,Port-7"
|
|
hexmask.long.word 0x4 16.--27. 1. " DE ,Decrement Event"
|
|
textline " "
|
|
bitfld.long 0x4 15. " IOCE ,Increment Occurrence Count Enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 12.--14. " IESS ,Increment Event Source Select" "Port-0,Port-1,Port-2,Port-3,Port-4,Port-5,Port-6,Port-7"
|
|
hexmask.long.word 0x4 0.--11. 1. " IE ,Increment Event"
|
|
line.long 0x8 "PMON_STS1,PMON Status Register 1"
|
|
eventfld.long 0x8 31. " DEI ,Decrement Event Indicator" "Not detected,Detected"
|
|
eventfld.long 0x8 30. " IEI ,Increment Event Indicator" "Not detected,Detected"
|
|
bitfld.long 0x8 29. " CAI ,Counter Active Indicator" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x8 28. " IU ,In use" "Not in use,In use"
|
|
eventfld.long 0x8 27. " UEI ,Unsupported Event Indicator" "Not detected,Detected"
|
|
eventfld.long 0x8 26. " OUI ,Overflow/Underflow Indicator" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x8 25. " CTI ,Command Trigger Indicator" "Not detected,Detected"
|
|
eventfld.long 0x8 24. " THI ,Threshold Indicator" "Not detected,Detected"
|
|
hexmask.long.byte 0x8 4.--11. 1. " CP ,Clock Period"
|
|
line.long 0xc "PMON_DATA1,PMON Data Register 1"
|
|
tree.end
|
|
tree "Counter 2"
|
|
group.long 0x20++0xf
|
|
line.long 0x0 "PMON_CMD2,PMON Command Register 2"
|
|
bitfld.long 0x0 28. " IE ,Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 27. " IOE ,Indicator Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 26. " OUIE ,Overflow/Underflow Indicator Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " CTIE ,Command Trigger Indicator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 24. " THIE ,Threshold Indicator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 21.--23. " CC ,Condition Code" "False,Greater,Equal,Greater/Equal,Less,Not equal,Less/Equal,True"
|
|
textline " "
|
|
bitfld.long 0x0 20. " SAC ,Select ALL Counters" "One,All"
|
|
bitfld.long 0x0 16.--19. " OPC ,Opcode" "Stop,Start,Sample,Reserved,Reset,Restart,Sample/Restart,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Preload"
|
|
textline " "
|
|
bitfld.long 0x0 12.--14. " CTSS ,Command Trigger Source Select" "Port-0,Port-1,Port-2,Port-3,Port-4,Port-5,Port-6,Port-7"
|
|
hexmask.long.word 0x0 0.--11. 1. " CT ,Command Trigger"
|
|
line.long 0x4 "PMON_EVR2,PMON Event Register 2"
|
|
bitfld.long 0x4 31. " DOCE ,Decrement Occurrence Count Enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 28.--30. " DESS ,Decrement Event Source Select" "Port-0,Port-1,Port-2,Port-3,Port-4,Port-5,Port-6,Port-7"
|
|
hexmask.long.word 0x4 16.--27. 1. " DE ,Decrement Event"
|
|
textline " "
|
|
bitfld.long 0x4 15. " IOCE ,Increment Occurrence Count Enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 12.--14. " IESS ,Increment Event Source Select" "Port-0,Port-1,Port-2,Port-3,Port-4,Port-5,Port-6,Port-7"
|
|
hexmask.long.word 0x4 0.--11. 1. " IE ,Increment Event"
|
|
line.long 0x8 "PMON_STS2,PMON Status Register 2"
|
|
eventfld.long 0x8 31. " DEI ,Decrement Event Indicator" "Not detected,Detected"
|
|
eventfld.long 0x8 30. " IEI ,Increment Event Indicator" "Not detected,Detected"
|
|
bitfld.long 0x8 29. " CAI ,Counter Active Indicator" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x8 28. " IU ,In use" "Not in use,In use"
|
|
eventfld.long 0x8 27. " UEI ,Unsupported Event Indicator" "Not detected,Detected"
|
|
eventfld.long 0x8 26. " OUI ,Overflow/Underflow Indicator" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x8 25. " CTI ,Command Trigger Indicator" "Not detected,Detected"
|
|
eventfld.long 0x8 24. " THI ,Threshold Indicator" "Not detected,Detected"
|
|
hexmask.long.byte 0x8 4.--11. 1. " CP ,Clock Period"
|
|
line.long 0xc "PMON_DATA2,PMON Data Register 2"
|
|
tree.end
|
|
tree "Counter 3"
|
|
group.long 0x30++0xf
|
|
line.long 0x0 "PMON_CMD3,PMON Command Register 3"
|
|
bitfld.long 0x0 28. " IE ,Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 27. " IOE ,Indicator Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 26. " OUIE ,Overflow/Underflow Indicator Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " CTIE ,Command Trigger Indicator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 24. " THIE ,Threshold Indicator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 21.--23. " CC ,Condition Code" "False,Greater,Equal,Greater/Equal,Less,Not equal,Less/Equal,True"
|
|
textline " "
|
|
bitfld.long 0x0 20. " SAC ,Select ALL Counters" "One,All"
|
|
bitfld.long 0x0 16.--19. " OPC ,Opcode" "Stop,Start,Sample,Reserved,Reset,Restart,Sample/Restart,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Preload"
|
|
textline " "
|
|
bitfld.long 0x0 12.--14. " CTSS ,Command Trigger Source Select" "Port-0,Port-1,Port-2,Port-3,Port-4,Port-5,Port-6,Port-7"
|
|
hexmask.long.word 0x0 0.--11. 1. " CT ,Command Trigger"
|
|
line.long 0x4 "PMON_EVR3,PMON Event Register 3"
|
|
bitfld.long 0x4 31. " DOCE ,Decrement Occurrence Count Enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 28.--30. " DESS ,Decrement Event Source Select" "Port-0,Port-1,Port-2,Port-3,Port-4,Port-5,Port-6,Port-7"
|
|
hexmask.long.word 0x4 16.--27. 1. " DE ,Decrement Event"
|
|
textline " "
|
|
bitfld.long 0x4 15. " IOCE ,Increment Occurrence Count Enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 12.--14. " IESS ,Increment Event Source Select" "Port-0,Port-1,Port-2,Port-3,Port-4,Port-5,Port-6,Port-7"
|
|
hexmask.long.word 0x4 0.--11. 1. " IE ,Increment Event"
|
|
line.long 0x8 "PMON_STS3,PMON Status Register 3"
|
|
eventfld.long 0x8 31. " DEI ,Decrement Event Indicator" "Not detected,Detected"
|
|
eventfld.long 0x8 30. " IEI ,Increment Event Indicator" "Not detected,Detected"
|
|
bitfld.long 0x8 29. " CAI ,Counter Active Indicator" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x8 28. " IU ,In use" "Not in use,In use"
|
|
eventfld.long 0x8 27. " UEI ,Unsupported Event Indicator" "Not detected,Detected"
|
|
eventfld.long 0x8 26. " OUI ,Overflow/Underflow Indicator" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x8 25. " CTI ,Command Trigger Indicator" "Not detected,Detected"
|
|
eventfld.long 0x8 24. " THI ,Threshold Indicator" "Not detected,Detected"
|
|
hexmask.long.byte 0x8 4.--11. 1. " CP ,Clock Period"
|
|
line.long 0xc "PMON_DATA3,PMON Data Register 3"
|
|
tree.end
|
|
tree "Counter 4"
|
|
group.long 0x40++0xf
|
|
line.long 0x0 "PMON_CMD4,PMON Command Register 4"
|
|
bitfld.long 0x0 28. " IE ,Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 27. " IOE ,Indicator Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 26. " OUIE ,Overflow/Underflow Indicator Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " CTIE ,Command Trigger Indicator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 24. " THIE ,Threshold Indicator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 21.--23. " CC ,Condition Code" "False,Greater,Equal,Greater/Equal,Less,Not equal,Less/Equal,True"
|
|
textline " "
|
|
bitfld.long 0x0 20. " SAC ,Select ALL Counters" "One,All"
|
|
bitfld.long 0x0 16.--19. " OPC ,Opcode" "Stop,Start,Sample,Reserved,Reset,Restart,Sample/Restart,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Preload"
|
|
textline " "
|
|
bitfld.long 0x0 12.--14. " CTSS ,Command Trigger Source Select" "Port-0,Port-1,Port-2,Port-3,Port-4,Port-5,Port-6,Port-7"
|
|
hexmask.long.word 0x0 0.--11. 1. " CT ,Command Trigger"
|
|
line.long 0x4 "PMON_EVR4,PMON Event Register 4"
|
|
bitfld.long 0x4 31. " DOCE ,Decrement Occurrence Count Enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 28.--30. " DESS ,Decrement Event Source Select" "Port-0,Port-1,Port-2,Port-3,Port-4,Port-5,Port-6,Port-7"
|
|
hexmask.long.word 0x4 16.--27. 1. " DE ,Decrement Event"
|
|
textline " "
|
|
bitfld.long 0x4 15. " IOCE ,Increment Occurrence Count Enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 12.--14. " IESS ,Increment Event Source Select" "Port-0,Port-1,Port-2,Port-3,Port-4,Port-5,Port-6,Port-7"
|
|
hexmask.long.word 0x4 0.--11. 1. " IE ,Increment Event"
|
|
line.long 0x8 "PMON_STS4,PMON Status Register 4"
|
|
eventfld.long 0x8 31. " DEI ,Decrement Event Indicator" "Not detected,Detected"
|
|
eventfld.long 0x8 30. " IEI ,Increment Event Indicator" "Not detected,Detected"
|
|
bitfld.long 0x8 29. " CAI ,Counter Active Indicator" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x8 28. " IU ,In use" "Not in use,In use"
|
|
eventfld.long 0x8 27. " UEI ,Unsupported Event Indicator" "Not detected,Detected"
|
|
eventfld.long 0x8 26. " OUI ,Overflow/Underflow Indicator" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x8 25. " CTI ,Command Trigger Indicator" "Not detected,Detected"
|
|
eventfld.long 0x8 24. " THI ,Threshold Indicator" "Not detected,Detected"
|
|
hexmask.long.byte 0x8 4.--11. 1. " CP ,Clock Period"
|
|
line.long 0xc "PMON_DATA4,PMON Data Register 4"
|
|
tree.end
|
|
tree "Counter 5"
|
|
group.long 0x50++0xf
|
|
line.long 0x0 "PMON_CMD5,PMON Command Register 5"
|
|
bitfld.long 0x0 28. " IE ,Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 27. " IOE ,Indicator Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 26. " OUIE ,Overflow/Underflow Indicator Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " CTIE ,Command Trigger Indicator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 24. " THIE ,Threshold Indicator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 21.--23. " CC ,Condition Code" "False,Greater,Equal,Greater/Equal,Less,Not equal,Less/Equal,True"
|
|
textline " "
|
|
bitfld.long 0x0 20. " SAC ,Select ALL Counters" "One,All"
|
|
bitfld.long 0x0 16.--19. " OPC ,Opcode" "Stop,Start,Sample,Reserved,Reset,Restart,Sample/Restart,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Preload"
|
|
textline " "
|
|
bitfld.long 0x0 12.--14. " CTSS ,Command Trigger Source Select" "Port-0,Port-1,Port-2,Port-3,Port-4,Port-5,Port-6,Port-7"
|
|
hexmask.long.word 0x0 0.--11. 1. " CT ,Command Trigger"
|
|
line.long 0x4 "PMON_EVR5,PMON Event Register 5"
|
|
bitfld.long 0x4 31. " DOCE ,Decrement Occurrence Count Enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 28.--30. " DESS ,Decrement Event Source Select" "Port-0,Port-1,Port-2,Port-3,Port-4,Port-5,Port-6,Port-7"
|
|
hexmask.long.word 0x4 16.--27. 1. " DE ,Decrement Event"
|
|
textline " "
|
|
bitfld.long 0x4 15. " IOCE ,Increment Occurrence Count Enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 12.--14. " IESS ,Increment Event Source Select" "Port-0,Port-1,Port-2,Port-3,Port-4,Port-5,Port-6,Port-7"
|
|
hexmask.long.word 0x4 0.--11. 1. " IE ,Increment Event"
|
|
line.long 0x8 "PMON_STS5,PMON Status Register 5"
|
|
eventfld.long 0x8 31. " DEI ,Decrement Event Indicator" "Not detected,Detected"
|
|
eventfld.long 0x8 30. " IEI ,Increment Event Indicator" "Not detected,Detected"
|
|
bitfld.long 0x8 29. " CAI ,Counter Active Indicator" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x8 28. " IU ,In use" "Not in use,In use"
|
|
eventfld.long 0x8 27. " UEI ,Unsupported Event Indicator" "Not detected,Detected"
|
|
eventfld.long 0x8 26. " OUI ,Overflow/Underflow Indicator" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x8 25. " CTI ,Command Trigger Indicator" "Not detected,Detected"
|
|
eventfld.long 0x8 24. " THI ,Threshold Indicator" "Not detected,Detected"
|
|
hexmask.long.byte 0x8 4.--11. 1. " CP ,Clock Period"
|
|
line.long 0xc "PMON_DATA5,PMON Data Register 5"
|
|
tree.end
|
|
tree "Counter 6"
|
|
group.long 0x60++0xf
|
|
line.long 0x0 "PMON_CMD6,PMON Command Register 6"
|
|
bitfld.long 0x0 28. " IE ,Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 27. " IOE ,Indicator Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 26. " OUIE ,Overflow/Underflow Indicator Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " CTIE ,Command Trigger Indicator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 24. " THIE ,Threshold Indicator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 21.--23. " CC ,Condition Code" "False,Greater,Equal,Greater/Equal,Less,Not equal,Less/Equal,True"
|
|
textline " "
|
|
bitfld.long 0x0 20. " SAC ,Select ALL Counters" "One,All"
|
|
bitfld.long 0x0 16.--19. " OPC ,Opcode" "Stop,Start,Sample,Reserved,Reset,Restart,Sample/Restart,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Preload"
|
|
textline " "
|
|
bitfld.long 0x0 12.--14. " CTSS ,Command Trigger Source Select" "Port-0,Port-1,Port-2,Port-3,Port-4,Port-5,Port-6,Port-7"
|
|
hexmask.long.word 0x0 0.--11. 1. " CT ,Command Trigger"
|
|
line.long 0x4 "PMON_EVR6,PMON Event Register 6"
|
|
bitfld.long 0x4 31. " DOCE ,Decrement Occurrence Count Enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 28.--30. " DESS ,Decrement Event Source Select" "Port-0,Port-1,Port-2,Port-3,Port-4,Port-5,Port-6,Port-7"
|
|
hexmask.long.word 0x4 16.--27. 1. " DE ,Decrement Event"
|
|
textline " "
|
|
bitfld.long 0x4 15. " IOCE ,Increment Occurrence Count Enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 12.--14. " IESS ,Increment Event Source Select" "Port-0,Port-1,Port-2,Port-3,Port-4,Port-5,Port-6,Port-7"
|
|
hexmask.long.word 0x4 0.--11. 1. " IE ,Increment Event"
|
|
line.long 0x8 "PMON_STS6,PMON Status Register 6"
|
|
eventfld.long 0x8 31. " DEI ,Decrement Event Indicator" "Not detected,Detected"
|
|
eventfld.long 0x8 30. " IEI ,Increment Event Indicator" "Not detected,Detected"
|
|
bitfld.long 0x8 29. " CAI ,Counter Active Indicator" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x8 28. " IU ,In use" "Not in use,In use"
|
|
eventfld.long 0x8 27. " UEI ,Unsupported Event Indicator" "Not detected,Detected"
|
|
eventfld.long 0x8 26. " OUI ,Overflow/Underflow Indicator" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x8 25. " CTI ,Command Trigger Indicator" "Not detected,Detected"
|
|
eventfld.long 0x8 24. " THI ,Threshold Indicator" "Not detected,Detected"
|
|
hexmask.long.byte 0x8 4.--11. 1. " CP ,Clock Period"
|
|
line.long 0xc "PMON_DATA6,PMON Data Register 6"
|
|
tree.end
|
|
tree "Counter 7"
|
|
group.long 0x70++0xf
|
|
line.long 0x0 "PMON_CMD7,PMON Command Register 7"
|
|
bitfld.long 0x0 28. " IE ,Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 27. " IOE ,Indicator Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 26. " OUIE ,Overflow/Underflow Indicator Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " CTIE ,Command Trigger Indicator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 24. " THIE ,Threshold Indicator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 21.--23. " CC ,Condition Code" "False,Greater,Equal,Greater/Equal,Less,Not equal,Less/Equal,True"
|
|
textline " "
|
|
bitfld.long 0x0 20. " SAC ,Select ALL Counters" "One,All"
|
|
bitfld.long 0x0 16.--19. " OPC ,Opcode" "Stop,Start,Sample,Reserved,Reset,Restart,Sample/Restart,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Preload"
|
|
textline " "
|
|
bitfld.long 0x0 12.--14. " CTSS ,Command Trigger Source Select" "Port-0,Port-1,Port-2,Port-3,Port-4,Port-5,Port-6,Port-7"
|
|
hexmask.long.word 0x0 0.--11. 1. " CT ,Command Trigger"
|
|
line.long 0x4 "PMON_EVR7,PMON Event Register 7"
|
|
bitfld.long 0x4 31. " DOCE ,Decrement Occurrence Count Enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 28.--30. " DESS ,Decrement Event Source Select" "Port-0,Port-1,Port-2,Port-3,Port-4,Port-5,Port-6,Port-7"
|
|
hexmask.long.word 0x4 16.--27. 1. " DE ,Decrement Event"
|
|
textline " "
|
|
bitfld.long 0x4 15. " IOCE ,Increment Occurrence Count Enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 12.--14. " IESS ,Increment Event Source Select" "Port-0,Port-1,Port-2,Port-3,Port-4,Port-5,Port-6,Port-7"
|
|
hexmask.long.word 0x4 0.--11. 1. " IE ,Increment Event"
|
|
line.long 0x8 "PMON_STS7,PMON Status Register 7"
|
|
eventfld.long 0x8 31. " DEI ,Decrement Event Indicator" "Not detected,Detected"
|
|
eventfld.long 0x8 30. " IEI ,Increment Event Indicator" "Not detected,Detected"
|
|
bitfld.long 0x8 29. " CAI ,Counter Active Indicator" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x8 28. " IU ,In use" "Not in use,In use"
|
|
eventfld.long 0x8 27. " UEI ,Unsupported Event Indicator" "Not detected,Detected"
|
|
eventfld.long 0x8 26. " OUI ,Overflow/Underflow Indicator" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x8 25. " CTI ,Command Trigger Indicator" "Not detected,Detected"
|
|
eventfld.long 0x8 24. " THI ,Threshold Indicator" "Not detected,Detected"
|
|
hexmask.long.byte 0x8 4.--11. 1. " CP ,Clock Period"
|
|
line.long 0xc "PMON_DATA7,PMON Data Register 7"
|
|
tree.end
|
|
tree.end
|
|
textline ""
|