356 lines
8.9 KiB
Plaintext
356 lines
8.9 KiB
Plaintext
; --------------------------------------------------------------------------------
|
|
; @Title: Z20K148M Specific Menu
|
|
; @Props: Released
|
|
; @Author: NEJ
|
|
; @Changelog: 2022-10-04 NEJ
|
|
; @Manufacturer: Zhixin - Zhixin Semiconductor Co. Ltd.
|
|
; @Core: Cortex-M4F
|
|
; @Chip: Z20K148M
|
|
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
|
|
; --------------------------------------------------------------------------------
|
|
; $Id: menz20k148m.men 16339 2023-07-03 13:30:14Z pegold $
|
|
|
|
add
|
|
menu
|
|
(
|
|
IF SOFTWARE.BUILD.BASE()>=69655.
|
|
(
|
|
popup "&CPU"
|
|
(
|
|
separator
|
|
IF CPU.FEATURE(MMU)
|
|
(
|
|
popup "[:mmu]MMU"
|
|
(
|
|
menuitem "[:mmureg]MMU Control" "MMU.view"
|
|
separator
|
|
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
|
|
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
|
|
separator
|
|
IF CPU.FEATURE(ITLBDUMP)
|
|
(
|
|
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
|
|
)
|
|
IF CPU.FEATURE(DTLBDUMP)
|
|
(
|
|
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
|
|
)
|
|
IF CPU.FEATURE(TLB0DUMP)
|
|
(
|
|
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
|
|
)
|
|
IF CPU.FEATURE(TLB1DUMP)
|
|
(
|
|
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
|
|
)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU")
|
|
(
|
|
popup "[:mmu]SMMU"
|
|
(
|
|
menuitem "[:chip]SMMU1 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU1 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU2")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU2 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU2 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU3")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU3 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU3 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU4")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU4 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU4 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU5")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU5 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU5 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU6")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU6 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU6 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
)
|
|
)
|
|
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
|
|
(
|
|
popup "[:cache]Cache"
|
|
(
|
|
IF CPU.FEATURE(L1ICACHEDUMP)
|
|
(
|
|
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
|
|
menuitem "[:cache]ICACHE List" "CACHE.List IC"
|
|
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
|
|
)
|
|
IF CPU.FEATURE(L1DCACHEDUMP)
|
|
(
|
|
separator
|
|
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
|
|
menuitem "[:cache]DCACHE List" "CACHE.List DC"
|
|
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
|
|
)
|
|
IF CPU.FEATURE(L2CACHEDUMP)
|
|
(
|
|
separator
|
|
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
|
|
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
|
|
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
|
|
)
|
|
)
|
|
)
|
|
)
|
|
popup "&Trace"
|
|
(
|
|
separator
|
|
IF COMPonent.AVAILable("ITM")
|
|
(
|
|
popup "ITM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]ITM settings..." "ITM.state"
|
|
separator
|
|
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("STM")
|
|
(
|
|
popup "STM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]STM settings..." "STM.state"
|
|
separator
|
|
menuitem "[:alist]STMTrace List" "STMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("HTM")
|
|
(
|
|
popup "HTM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]HTM settings..." "HTM.state"
|
|
separator
|
|
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("TPIU")
|
|
(
|
|
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
|
|
)
|
|
IF COMPonent.AVAILable("ETR")
|
|
(
|
|
menuitem "[:oconfig]ETR settings..."
|
|
(
|
|
PRIVATE &pdd
|
|
&pdd=OS.PDD()
|
|
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
|
|
)
|
|
)
|
|
)
|
|
popup "&Misc"
|
|
(
|
|
popup "Tools"
|
|
(
|
|
IF CPUIS64BIT()||CPU.FEATURE("SPR")
|
|
(
|
|
menuitem "ARM System Register Converter"
|
|
(
|
|
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
|
|
)
|
|
)
|
|
IF CPU.FEATURE("C15")
|
|
(
|
|
menuitem "ARM Coprocessor Converter"
|
|
(
|
|
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
|
|
)
|
|
)
|
|
)
|
|
)
|
|
popup "&Perf"
|
|
(
|
|
IF CPU.FEATURE(BMC)
|
|
(
|
|
before "Reset"
|
|
menuitem "[:bmc]Benchmark Counters" "BMC.state"
|
|
before "Reset"
|
|
separator
|
|
)
|
|
)
|
|
)
|
|
popup "Peripherals"
|
|
(
|
|
popup "[:chip]Core Registers (Cortex-M4F)"
|
|
(
|
|
menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M4F),System Control"""
|
|
menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M4F),Memory Protection Unit"""
|
|
menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M4F),Nested Vectored Interrupt Controller"""
|
|
menuitem "[:chip]FPU;Floating-point Unit" "per , ""Core Registers (Cortex-M4F),Floating-point Unit"""
|
|
popup "[:chip]Debug"
|
|
(
|
|
menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M4F),Debug,Core Debug"""
|
|
menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M4F),Debug,Flash Patch and Breakpoint Unit (FPB)"""
|
|
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M4F),Debug,Data Watchpoint and Trace Unit (DWT)"""
|
|
)
|
|
)
|
|
separator
|
|
popup "ADC"
|
|
(
|
|
menuitem "ADC0" "per , ""ADC,ADC0"""
|
|
menuitem "ADC1" "per , ""ADC,ADC1"""
|
|
)
|
|
menuitem "AES" "per , ""AES"""
|
|
popup "CAN"
|
|
(
|
|
menuitem "CAN0" "per , ""CAN,CAN0"""
|
|
menuitem "CAN1" "per , ""CAN,CAN1"""
|
|
menuitem "CAN2" "per , ""CAN,CAN2"""
|
|
menuitem "CAN3" "per , ""CAN,CAN3"""
|
|
menuitem "CAN4" "per , ""CAN,CAN4"""
|
|
menuitem "CAN5" "per , ""CAN,CAN5"""
|
|
menuitem "CAN6" "per , ""CAN,CAN6"""
|
|
menuitem "CAN7" "per , ""CAN,CAN7"""
|
|
)
|
|
menuitem "CMP" "per , ""CMP"""
|
|
popup "CMU"
|
|
(
|
|
menuitem "CMU0" "per , ""CMU,CMU0"""
|
|
menuitem "CMU1" "per , ""CMU,CMU1"""
|
|
menuitem "CMU2" "per , ""CMU,CMU2"""
|
|
)
|
|
menuitem "CRC" "per , ""CRC"""
|
|
menuitem "DMA" "per , ""DMA"""
|
|
menuitem "DMUX" "per , ""DMUX"""
|
|
menuitem "EIRU" "per , ""EIRU"""
|
|
menuitem "FLASHC" "per , ""FLASHC"""
|
|
menuitem "GPIO" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines)"""
|
|
popup "I2C;Inter-Integrated Circuit"
|
|
(
|
|
menuitem "I2C0" "per , ""I2C (Inter-Integrated Circuit),I2C0"""
|
|
menuitem "I2C1" "per , ""I2C (Inter-Integrated Circuit),I2C1"""
|
|
)
|
|
popup "I2S;Inter-Integrated Sound Bus Controller"
|
|
(
|
|
menuitem "I2S0" "per , ""I2S (Inter-Integrated Sound Bus Controller),I2S0"""
|
|
menuitem "I2S1" "per , ""I2S (Inter-Integrated Sound Bus Controller),I2S1"""
|
|
)
|
|
popup "MCPWM"
|
|
(
|
|
menuitem "MCPWM0" "per , ""MCPWM,MCPWM0"""
|
|
menuitem "MCPWM1" "per , ""MCPWM,MCPWM1"""
|
|
)
|
|
menuitem "PARCC" "per , ""PARCC"""
|
|
menuitem "PMU" "per , ""PMU (Program Memory Unit)"""
|
|
menuitem "PORT" "per , ""PORT"""
|
|
menuitem "REGFILE" "per , ""REGFILE"""
|
|
menuitem "RTC" "per , ""RTC (Real-time Counter)"""
|
|
menuitem "SCC" "per , ""SCC"""
|
|
menuitem "SCM" "per , ""SCM"""
|
|
menuitem "SERU" "per , ""SERU"""
|
|
menuitem "SMPU" "per , ""SMPU"""
|
|
popup "SPI"
|
|
(
|
|
menuitem "SPI0" "per , ""SPI,SPI0"""
|
|
menuitem "SPI1" "per , ""SPI,SPI1"""
|
|
menuitem "SPI2" "per , ""SPI,SPI2"""
|
|
menuitem "SPI3" "per , ""SPI,SPI3"""
|
|
)
|
|
menuitem "SRMC" "per , ""SRMC"""
|
|
menuitem "STIM" "per , ""STIM"""
|
|
popup "TDG"
|
|
(
|
|
menuitem "TDG0" "per , ""TDG,TDG0"""
|
|
menuitem "TDG1" "per , ""TDG,TDG1"""
|
|
)
|
|
popup "TIM"
|
|
(
|
|
menuitem "TIM0" "per , ""TIM,TIM0"""
|
|
menuitem "TIM1" "per , ""TIM,TIM1"""
|
|
menuitem "TIM2" "per , ""TIM,TIM2"""
|
|
menuitem "TIM3" "per , ""TIM,TIM3"""
|
|
)
|
|
menuitem "TMU" "per , ""TMU (Thermal Monitoring Unit)"""
|
|
menuitem "TRNG" "per , ""TRNG"""
|
|
popup "UART;Universal Asynchronous Receiver/Transmitter"
|
|
(
|
|
menuitem "UART0" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART0"""
|
|
menuitem "UART1" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART1"""
|
|
menuitem "UART2" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART2"""
|
|
menuitem "UART3" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART3"""
|
|
menuitem "UART4" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART4"""
|
|
menuitem "UART5" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART5"""
|
|
)
|
|
menuitem "WDOG" "per , ""WDOG (Watchdog Timer Unit)"""
|
|
)
|
|
)
|