324 lines
9.2 KiB
Plaintext
324 lines
9.2 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: TMS570LS20216 Specific Menu
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; @Props: Released
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; @Author: ADI
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; @Changelog: 2008-10-22 ADI
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; @Manufacturer: TI - Texas Instruments
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; @Core: Cortex-R4F
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; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: mentms570ls20216.men 16339 2023-07-03 13:30:14Z pegold $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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popup "[:chip]Core Registers (Cortex-R4F)"
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(
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menuitem "[:chip]ID Registers" "per , ""Core Registers (Cortex-R4F),ID Registers"""
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menuitem "[:chip]System Control and Configuration" "per , ""Core Registers (Cortex-R4F),System Control and Configuration"""
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menuitem "[:chip]MPU Control and Configuration" "per , ""Core Registers (Cortex-R4F),MPU Control and Configuration"""
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menuitem "[:chip]Cache Control and Configuration" "per , ""Core Registers (Cortex-R4F),Cache Control and Configuration"""
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menuitem "[:chip]TCM Control and Configuration" "per , ""Core Registers (Cortex-R4F),TCM Control and Configuration"""
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menuitem "[:chip]System Performance Monitor" "per , ""Core Registers (Cortex-R4F),System Performance Monitor"""
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separator
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menuitem "[:chip]Debug Registers" "per , ""Core Registers (Cortex-R4F),Debug Registers"""
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menuitem "[:chip]Breakpoint Registers" "per , ""Core Registers (Cortex-R4F),Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Control Registers" "per , ""Core Registers (Cortex-R4F),Watchpoint Control Registers"""
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)
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separator
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popup "ADC"
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(
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menuitem "MIBADC1" "per , ""ADC (Analog to Digital Converter),MIBADC1"""
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menuitem "MIBADC2" "per , ""ADC (Analog to Digital Converter),MIBADC2"""
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)
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popup "DCAN"
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(
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menuitem "DCAN1" "per , ""DCAN (Controller Area Network),DCAN1"""
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menuitem "DCAN2" "per , ""DCAN (Controller Area Network),DCAN2"""
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menuitem "DCAN3" "per , ""DCAN (Controller Area Network),DCAN3"""
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)
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menuitem "Flexray" "per , ""Flexray"""
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menuitem "FlexrayTU" "per , ""FlexrayTU"""
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popup "GPIO"
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(
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menuitem "GIO" "per , ""GPIO (General-Purpose Input/Output),GIO"""
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menuitem "GIOA" "per , ""GPIO (General-Purpose Input/Output),GIOA"""
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menuitem "GIOB" "per , ""GPIO (General-Purpose Input/Output),GIOB"""
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)
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menuitem "NHET" "per , ""NHET (New High End Timer)"""
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menuitem "HTU" "per , ""HTU (High End Timer Transfer Unit)"""
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popup "SPI"
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(
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menuitem "MIBSPI1" "per , ""SPI (Serial Peripheral Interface),MIBSPI1"""
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menuitem "MIBSPI3" "per , ""SPI (Serial Peripheral Interface),MIBSPI3"""
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menuitem "MIBSPIP5" "per , ""SPI (Serial Peripheral Interface),MIPSPIP5"""
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)
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popup "SCI"
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(
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menuitem "LIN1" "per , ""SCI (Serial Communication Interface),LIN1"""
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menuitem "LIN2" "per , ""SCI (Serial Communication Interface),LIN2"""
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)
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menuitem "CCMR4" "per , ""CCMR4 (CPU Compare Module - CortexR4)"""
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menuitem "CRC" "per , ""CRC"""
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menuitem "DMA" "per , ""DMA (Direct Memory Access)"""
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menuitem "DMM" "per , ""DMM (Data Modification Module)"""
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menuitem "ESM" "per , ""ESM (Error Signaling Module)"""
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menuitem "Flash Wrapper" "per , ""Flash_Wrapper"""
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menuitem "PBIST" "per , ""PBIST (Programmable Built-In Self-Test)"""
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menuitem "RTP" "per , ""RTP (RAM Trace Port)"""
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menuitem "RTI" "per , ""RTI (Real Time Interrupt)"""
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menuitem "STC" "per , ""STC (Self-Test Controller)"""
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menuitem "SYS" "per , ""SYS (System Registers)"""
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popup "VIM"
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(
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menuitem "VIM" "per , ""VIM (Vectored Interrupt Manager),VIM"""
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menuitem "VIMPAR" "per , ""VIM (Vectored Interrupt Manager),VIMPAR"""
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)
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menuitem "POM" "per , ""POM (Parameter Overlay Module)"""
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menuitem "EMIF" "per , ""EMIF (Asynchronous External Memory Interface)"""
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menuitem "PCR" "per , ""PCR (Peripheral Central Resource)"""
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popup "RAM Wrapper"
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(
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menuitem "RAM Wrapper Even" "per , ""RAM Wrapper,RAM_Wrapper_even"""
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menuitem "RAM Wrapper Odd" "per , ""RAM Wrapper,RAM_Wrapper_odd"""
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)
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)
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)
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