324 lines
8.0 KiB
Plaintext
324 lines
8.0 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: TMPM066 Specific Menu
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; @Props: Released
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; @Author: NEJ
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; @Changelog: 2022-04-07 NEJ
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; @Manufacturer: TOSHIBA - Toshiba
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; @Core: Cortex-M0
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; @Chip: TMPM066FWUG
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: mentmpm066.men 16339 2023-07-03 13:30:14Z pegold $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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popup "[:chip]Core Registers (Cortex-M0)"
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(
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menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M0),System Control"""
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menuitem "[:chip]Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M0),Nested Vectored Interrupt Controller (NVIC)"""
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popup "[:chip]Debug"
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(
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menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M0),Debug,Core Debug"""
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menuitem "[:chip]BPU;Breakpoint Unit" "per , ""Core Registers (Cortex-M0),Debug,Breakpoint Unit (BPU)"""
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menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M0),Debug,Data Watchpoint and Trace Unit (DWT)"""
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)
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)
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separator
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menuitem "ADC" "per , ""ADC (10-bit Analog/Digital Converter)"""
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menuitem "AOREG" "per , ""AOREG (AO Area Registers)"""
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menuitem "CG" "per , ""CG (Clock Generator)"""
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menuitem "DMAC" "per , ""DMAC (DMA Controller)"""
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menuitem "FC" "per , ""FC (Flash Control)"""
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popup "I2C"
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(
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menuitem "I2C0" "per , ""I2C (Inter-Integrated Circuit),I2C0"""
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menuitem "I2C1" "per , ""I2C (Inter-Integrated Circuit),I2C1"""
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)
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menuitem "I2CS" "per , ""I2CS (I2C Wakeup Function Control Registers)"""
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menuitem "INTIFAO" "per , ""INTIFAO (AO Area Interrupt Control)"""
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menuitem "INTIFSD" "per , ""INTIFSD (SD Area Interrupt Control)"""
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menuitem "LVD" "per , ""LVD (Low-Voltage Detection Circuit)"""
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menuitem "PA" "per , ""PA (Port A)"""
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menuitem "PB" "per , ""PB (Port B)"""
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menuitem "PC" "per , ""PC (Port C)"""
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menuitem "PD" "per , ""PD (Port D)"""
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menuitem "PE" "per , ""PE (Port E)"""
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menuitem "PF" "per , ""PF (Port F)"""
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menuitem "PG" "per , ""PG (Port G)"""
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menuitem "PH" "per , ""PH (Port H)"""
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menuitem "PJ" "per , ""PJ (Port J)"""
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popup "SC"
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(
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menuitem "SC0" "per , ""SC (Serial Channel),SC0"""
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menuitem "SC1" "per , ""SC (Serial Channel),SC1"""
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)
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popup "TMR16A"
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(
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menuitem "T16A0" "per , ""TMR16A (16-bit Timer A),T16A0"""
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menuitem "T16A1" "per , ""TMR16A (16-bit Timer A),T16A1"""
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)
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popup "TMRB"
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(
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menuitem "TB0" "per , ""TMRB (16-bit Timer/Event Counter),TB0"""
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menuitem "TB1" "per , ""TMRB (16-bit Timer/Event Counter),TB1"""
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menuitem "TB2" "per , ""TMRB (16-bit Timer/Event Counter),TB2"""
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menuitem "TB3" "per , ""TMRB (16-bit Timer/Event Counter),TB3"""
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menuitem "TB4" "per , ""TMRB (16-bit Timer/Event Counter),TB4"""
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menuitem "TB5" "per , ""TMRB (16-bit Timer/Event Counter),TB5"""
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menuitem "TB6" "per , ""TMRB (16-bit Timer/Event Counter),TB6"""
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menuitem "TB7" "per , ""TMRB (16-bit Timer/Event Counter),TB7"""
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)
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popup "TMRD"
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(
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menuitem "TD" "per , ""TMRD (16-bit Timer D),TD"""
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menuitem "TD0" "per , ""TMRD (16-bit Timer D),TD0"""
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menuitem "TD1" "per , ""TMRD (16-bit Timer D),TD1"""
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)
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menuitem "TSPI" "per , ""TSPI (Serial Interface)"""
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popup "USBD"
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(
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menuitem "UDFS" "per , ""USBD (USB Device Controller),UDFS"""
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menuitem "UDFS2" "per , ""USBD (USB Device Controller),UDFS2"""
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)
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menuitem "WDT" "per , ""WDT (Watchdog Timer)"""
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)
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)
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