438 lines
21 KiB
Plaintext
438 lines
21 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: Stratix 10 Specific Menu
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; @Props: Released
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; @Author: CEZ, MKO, MRO, DLI, PID, KRZ
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; @Changelog: 2019-10-10 MKO
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; @Manufacturer: INTEL - Intel Corporation
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; @Core: Cortex-A53
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; @Chip: STRATIX10SX
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; @Copyright: (C) 1989-2019 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: menstratix10.men 16339 2023-07-03 13:30:14Z pegold $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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popup "[:chip]Core Registers (Cortex-A53)"
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(
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menuitem "[:chip]ID Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,ID Registers"""
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menuitem "[:chip]System Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,System Control and Configuration"""
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menuitem "[:chip]Memory Management Unit[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Memory Management Unit"""
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menuitem "[:chip]Virtualization Extensions[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Virtualization Extensions"""
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menuitem "[:chip]Cache Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,System Performance Monitor"""
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menuitem "[:chip]System Timer Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,System Timer Registers"""
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menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Generic Interrupt Controller CPU Interface"""
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separator
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menuitem "[:chip]Debug Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Debug Registers"""
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separator
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menuitem "[:chip]Breakpoint Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Control Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Watchpoint Control Registers"""
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separator
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menuitem "[:chip]ID Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,ID Registers"""
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menuitem "[:chip]System Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,System Control and Configuration"""
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menuitem "[:chip]Memory Management Unit[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Memory Management Unit"""
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menuitem "[:chip]Virtualization Extensions[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Virtualization Extensions"""
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menuitem "[:chip]Cache Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,System Performance Monitor"""
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menuitem "[:chip]System Timer Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,System Timer Registers"""
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menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Generic Interrupt Controller CPU Interface"""
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separator
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menuitem "[:chip]Debug Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Debug Registers"""
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separator
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menuitem "[:chip]Breakpoint Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Control Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Watchpoint Control Registers"""
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separator
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menuitem "[:chip]Interrupt Controller (GIC-400)" "per , ""Core Registers (Cortex-A53),Interrupt Controller (GIC-400)"""
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)
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separator
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menuitem "CCU;Cache Coherency Unit" "per , ""CCU (Cache Coherency Unit)"""
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; menuitem "SMMU;System Memory Management Unit" "per , ""SMMU (System Memory Management Unit)"""
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popup "SDRAML3INT;SDRAM L3 Interconnect"
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(
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menuitem "DDR_T_MAIN_PROBE" "per , ""SDRAML3INT (SDRAM L3 Interconnect),DDR_T_MAIN_PROBE"""
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menuitem "DDR_SCHEDULER_DDR_T_MAIN_SCHEDULER" "per , ""SDRAML3INT (SDRAM L3 Interconnect),DDR_SCHEDULER_DDR_T_MAIN_SCHEDULER"""
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menuitem "IOHMC_CTRL_MMR_TOP_INST" "per , ""SDRAML3INT (SDRAM L3 Interconnect),IOHMC_CTRL_MMR_TOP_INST"""
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menuitem "HMC_ADP_CSR_OCP_SLV" "per , ""SDRAML3INT (SDRAM L3 Interconnect),HMC_ADP_CSR_OCP_SLV"""
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menuitem "FIREWALL_DDR_SCHEDULER_MPFE_SCR" "per , ""SDRAML3INT (SDRAM L3 Interconnect),FIREWALL_DDR_SCHEDULER_MPFE_SCR"""
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menuitem "FIREWALL_MPU_DDR_SCR" "per , ""SDRAML3INT (SDRAM L3 Interconnect),FIREWALL_MPU_DDR_SCR"""
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menuitem "FIREWALL_DDR_FPGA2SDRAM_INST_0_SCR" "per , ""SDRAML3INT (SDRAM L3 Interconnect),FIREWALL_DDR_FPGA2SDRAM_INST_0_SCR"""
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menuitem "FIREWALL_DDR_FPGA2SDRAM_INST_1_DDR_SCR" "per , ""SDRAML3INT (SDRAM L3 Interconnect),FIREWALL_DDR_FPGA2SDRAM_INST_1_DDR_SCR"""
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menuitem "FIREWALL_DDR_FPGA2SDRAM_INST_2_SCR" "per , ""SDRAML3INT (SDRAM L3 Interconnect),FIREWALL_DDR_FPGA2SDRAM_INST_2_SCR"""
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menuitem "DDR_SCHEDULER_CS_OBS_AT_MAIN_ATBENDPOINT" "per , ""SDRAML3INT (SDRAM L3 Interconnect),DDR_SCHEDULER_CS_OBS_AT_MAIN_ATBENDPOINT"""
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menuitem "DDR_SCHEDULER_CCU_MEM0_I_MAIN_QOSGENERATOR" "per , ""SDRAML3INT (SDRAM L3 Interconnect),DDR_SCHEDULER_CCU_MEM0_I_MAIN_QOSGENERATOR"""
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menuitem "DDR_SCHEDULER_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR" "per , ""SDRAML3INT (SDRAM L3 Interconnect),DDR_SCHEDULER_FPGA2SDRAM0_AXI128_I_MAIN_QOSGENERATOR"""
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menuitem "DDR_SCHEDULER_FPGA2SDRAM0_AXI132_I_MAIN_QOSGENERATOR" "per , ""SDRAML3INT (SDRAM L3 Interconnect),DDR_SCHEDULER_FPGA2SDRAM0_AXI132_I_MAIN_QOSGENERATOR"""
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menuitem "DDR_SCHEDULER_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR" "per , ""SDRAML3INT (SDRAM L3 Interconnect),DDR_SCHEDULER_FPGA2SDRAM0_AXI64_I_MAIN_QOSGENERATOR"""
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menuitem "DDR_SCHEDULER_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR" "per , ""SDRAML3INT (SDRAM L3 Interconnect),DDR_SCHEDULER_FPGA2SDRAM1_AXI128_I_MAIN_QOSGENERATOR"""
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menuitem "DDR_SCHEDULER_FPGA2SDRAM1_AXI132_I_MAIN_QOSGENERATOR" "per , ""SDRAML3INT (SDRAM L3 Interconnect),DDR_SCHEDULER_FPGA2SDRAM1_AXI132_I_MAIN_QOSGENERATOR"""
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menuitem "DDR_SCHEDULER_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR" "per , ""SDRAML3INT (SDRAM L3 Interconnect),DDR_SCHEDULER_FPGA2SDRAM1_AXI64_I_MAIN_QOSGENERATOR"""
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menuitem "DDR_SCHEDULER_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR" "per , ""SDRAML3INT (SDRAM L3 Interconnect),DDR_SCHEDULER_FPGA2SDRAM2_AXI128_I_MAIN_QOSGENERATOR"""
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menuitem "DDR_SCHEDULER_FPGA2SDRAM2_AXI132_I_MAIN_QOSGENERATOR" "per , ""SDRAML3INT (SDRAM L3 Interconnect),DDR_SCHEDULER_FPGA2SDRAM2_AXI132_I_MAIN_QOSGENERATOR"""
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menuitem "DDR_SCHEDULER_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR" "per , ""SDRAML3INT (SDRAM L3 Interconnect),DDR_SCHEDULER_FPGA2SDRAM2_AXI64_I_MAIN_QOSGENERATOR"""
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menuitem "DDR_SCHEDULER_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER" "per , ""SDRAML3INT (SDRAM L3 Interconnect),DDR_SCHEDULER_FPGA2SDRAM_MANAGER_MAIN_SIDEBANDMANAGER"""
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)
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menuitem "FPGA_BRIDGE_SOC2FPGA;FPGA Bridge SOC 2 FPGA" "per , ""FPGA_BRIDGE_SOC2FPGA (FPGA Bridge SOC 2 FPGA)"""
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menuitem "FPGA_BRIDGE_SOC2FPGA_DEF;FPGA Bridge SOC 2 FPGA Default" "per , ""FPGA_BRIDGE_SOC2FPGA_DEF (FPGA Bridge SOC 2 FPGA Default)"""
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menuitem "FPGA_BRIDGE_LWSOC2FPGA;FPGA Bridge LWSOC 2 FPGA" "per , ""FPGA_BRIDGE_LWSOC2FPGA (FPGA Bridge LWSOC 2 FPGA)"""
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menuitem "DMA;Direct Memory Access" "per , ""DMA (Direct Memory Access)"""
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menuitem "OC_RAM;OnChip RAM" "per , ""OC_RAM (OnChip RAM)"""
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popup "ECC;ECC Address Block Group"
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(
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menuitem "EMAC0 RX" "per , ""ECC (ECC Address Block Group),EMAC0 RX"""
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menuitem "EMAC0 TX" "per , ""ECC (ECC Address Block Group),EMAC0 TX"""
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menuitem "EMAC1 RX" "per , ""ECC (ECC Address Block Group),EMAC1 RX"""
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menuitem "EMAC1 TX" "per , ""ECC (ECC Address Block Group),EMAC1 TX"""
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menuitem "EMAC2 RX" "per , ""ECC (ECC Address Block Group),EMAC2 RX"""
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menuitem "EMAC2 TX" "per , ""ECC (ECC Address Block Group),EMAC2 TX"""
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menuitem "USB0" "per , ""ECC (ECC Address Block Group),USB0"""
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menuitem "USB1" "per , ""ECC (ECC Address Block Group),USB1"""
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menuitem "NANDe" "per , ""ECC (ECC Address Block Group),NANDe"""
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menuitem "NANDr" "per , ""ECC (ECC Address Block Group),NANDr"""
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menuitem "NANDw" "per , ""ECC (ECC Address Block Group),NANDw"""
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menuitem "SDMMC" "per , ""ECC (ECC Address Block Group),SDMMC"""
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menuitem "DMAC" "per , ""ECC (ECC Address Block Group),DMAC"""
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menuitem "OnChip RAM" "per , ""ECC (ECC Address Block Group),OnChip RAM"""
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)
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popup "CLK_MGR;Clock Manager"
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(
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menuitem "CLK_MGR_CTRL;Control Status" "per , ""CLK_MGR (Clock Manager),CLK_MGR_CTRL (Control Status)"""
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menuitem "MAINPLL_GRP;Control Status" "per , ""CLK_MGR (Clock Manager),MAINPLL_GRP (Control Status)"""
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menuitem "PERIPHPLL_GRP;Settings for the Peripheral PLL" "per , ""CLK_MGR (Clock Manager),PERIPHPLL_GRP (Settings for the Peripheral PLL)"""
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)
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popup "SDM;SDM Address Block Group"
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(
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menuitem "SDM SDMMC" "per , ""SDM (SDM Address Block Group),SDM SDMMC"""
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menuitem "SDM QSPI" "per , ""SDM (SDM Address Block Group),SDM QSPI"""
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)
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menuitem "RESET_MGR;Reset Manager" "per , ""RESET_MGR (Reset Manager)"""
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menuitem "SYSTEM_MGR;System Manager" "per , ""SYSTEM_MGR (System Manager)"""
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menuitem "DEDICATED_PINMUX;HPS Pinmux CSR" "per , ""DEDICATED_PINMUX (HPS Pinmux CSR)"""
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popup "NAND"
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(
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menuitem "NAND_CONFIG;NAND Configuration Registers" "per , ""NAND,NAND_CONFIG (NAND Configuration Registers)"""
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menuitem "NAND_PARAM;NAND Parameters Registers" "per , ""NAND,NAND_PARAM (NAND Parameters Registers)"""
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menuitem "NAND_STATUS;NAND Status Registers" "per , ""NAND,NAND_STATUS (NAND Status Registers)"""
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menuitem "NAND_ECC;NAND ECC Registers" "per , ""NAND,NAND_ECC (NAND ECC Registers)"""
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menuitem "NAMD_DMA;NAND DMA Registers" "per , ""NAND,NAMD_DMA (NAND DMA Registers)"""
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menuitem "NAND_DATA;NAND DATA Registers" "per , ""NAND,NAND_DATA (NAND DATA Registers)"""
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)
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menuitem "SDMMC;SD/MMC Controller" "per , ""SDMMC (SD/MMC Controller)"""
|
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popup "EMAC;Ethernet Media Access Controller"
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|
(
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menuitem "EMAC0" "per , ""EMAC (Ethernet Media Access Controller),EMAC0"""
|
|
menuitem "EMAC1" "per , ""EMAC (Ethernet Media Access Controller),EMAC1"""
|
|
menuitem "EMAC2" "per , ""EMAC (Ethernet Media Access Controller),EMAC2"""
|
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)
|
|
popup "USB;Universal Serial Bus"
|
|
(
|
|
menuitem "USBOTG 0" "per , ""USB (Universal Serial Bus),USBOTG 0"""
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|
menuitem "USBOTG 1" "per , ""USB (Universal Serial Bus),USBOTG 1"""
|
|
)
|
|
popup "SPI;Serial Peripheral Interface"
|
|
(
|
|
popup "SPI Slave"
|
|
(
|
|
menuitem "SPIS_0" "per , ""SPI (Serial Peripheral Interface),SPI Slave,SPIS_0"""
|
|
menuitem "SPIS_1" "per , ""SPI (Serial Peripheral Interface),SPI Slave,SPIS_1"""
|
|
)
|
|
popup "SPI Master"
|
|
(
|
|
menuitem "SPIM_0" "per , ""SPI (Serial Peripheral Interface),SPI Master,SPIM_0"""
|
|
menuitem "SPIM_1" "per , ""SPI (Serial Peripheral Interface),SPI Master,SPIM_1"""
|
|
)
|
|
)
|
|
popup "I2C;Inter-Integrated Circuit"
|
|
(
|
|
menuitem "I2C_0" "per , ""I2C (Inter-Integrated Circuit),I2C_0"""
|
|
menuitem "I2C_1" "per , ""I2C (Inter-Integrated Circuit),I2C_1"""
|
|
)
|
|
popup "I2C_EMAC;Inter-Integrated Circuit EMAC"
|
|
(
|
|
menuitem "I2C_EMAC_0" "per , ""I2C_EMAC (Inter-Integrated Circuit EMAC),I2C_EMAC_0"""
|
|
menuitem "I2C_EMAC_1" "per , ""I2C_EMAC (Inter-Integrated Circuit EMAC),I2C_EMAC_1"""
|
|
menuitem "I2C_EMAC_2" "per , ""I2C_EMAC (Inter-Integrated Circuit EMAC),I2C_EMAC_2"""
|
|
)
|
|
menuitem "UART;Universal Asynchronous Receiver-Transmitter" "per , ""UART (Universal Asynchronous Receiver-Transmitter)"""
|
|
popup "GPIO;General-Purpose I/O Interface"
|
|
(
|
|
menuitem "GPIO 0" "per , ""GPIO (General-Purpose I/O Interface),GPIO 0"""
|
|
menuitem "GPIO 1" "per , ""GPIO (General-Purpose I/O Interface),GPIO 1"""
|
|
)
|
|
popup "TIMER;Timer System"
|
|
(
|
|
menuitem "TIMER 0" "per , ""TIMER (Timer System),TIMER 0"""
|
|
menuitem "TIMER 1" "per , ""TIMER (Timer System),TIMER 1"""
|
|
)
|
|
popup "TIMER_SP;Timer SP"
|
|
(
|
|
menuitem "TIMER_SP0" "per , ""TIMER_SP (Timer SP),TIMER_SP0"""
|
|
menuitem "TIMER_SP1" "per , ""TIMER_SP (Timer SP),TIMER_SP1"""
|
|
)
|
|
popup "WDT;Watchdog Timer"
|
|
(
|
|
menuitem "WDT 0" "per , ""WDT (Watchdog Timer),WDT 0"""
|
|
menuitem "WDT 1" "per , ""WDT (Watchdog Timer),WDT 1"""
|
|
menuitem "WDT 2" "per , ""WDT (Watchdog Timer),WDT 2"""
|
|
menuitem "WDT 3" "per , ""WDT (Watchdog Timer),WDT 3"""
|
|
)
|
|
popup "L3IC;L3interconnect"
|
|
(
|
|
menuitem "Per-Master Security" "per , ""L3IC (L3interconnect),Per-Master Security"""
|
|
menuitem "CoreSight Observer Main ATB Endpoint" "per , ""L3IC (L3interconnect),CoreSight Observer Main ATB Endpoint"""
|
|
menuitem "CoreSight Observer Main Error Logger 0" "per , ""L3IC (L3interconnect),CoreSight Observer Main Error Logger 0"""
|
|
menuitem "CCU Probe" "per , ""L3IC (L3interconnect),CCU Probe"""
|
|
menuitem "EMAC Probe" "per , ""L3IC (L3interconnect),EMAC Probe"""
|
|
menuitem "SOC2FPGA Probe" "per , ""L3IC (L3interconnect),SOC2FPGA Probe"""
|
|
menuitem "EMAC Probe Transaction Statistics Profiler" "per , ""L3IC (L3interconnect),EMAC Probe Transaction Statistics Profiler"""
|
|
menuitem "CCU IOS QoS Generator" "per , ""L3IC (L3interconnect),CCU IOS QoS Generator"""
|
|
menuitem "DMA TBU QoS Generator" "per , ""L3IC (L3interconnect),DMA TBU QoS Generator"""
|
|
menuitem "EMAC TBU QoS Generator" "per , ""L3IC (L3interconnect),EMAC TBU QoS Generator"""
|
|
menuitem "IO TBU QoS Generator" "per , ""L3IC (L3interconnect),IO TBU QoS Generator"""
|
|
menuitem "SDM TBU QoS Generator" "per , ""L3IC (L3interconnect),SDM TBU QoS Generator"""
|
|
menuitem "EMAC TBU Transaction Statistics Filter" "per , ""L3IC (L3interconnect),EMAC TBU Transaction Statistics Filter"""
|
|
menuitem "Privilege" "per , ""L3IC (L3interconnect),Privilege"""
|
|
menuitem "L4 Link Responder Rate Adapter" "per , ""L3IC (L3interconnect),L4 Link Responder Rate Adapter"""
|
|
)
|
|
menuitem "NOC_CACHE_CLEAN;NOC Cache Clean" "per , ""NOC_CACHE_CLEAN (NOC Cache Clean)"""
|
|
menuitem "MBOX;Mailbox Registers" "per , ""MBOX (Mailbox Registers)"""
|
|
)
|
|
)
|