340 lines
12 KiB
Plaintext
340 lines
12 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: STM32L412 Specific Menu
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; @Props: Released
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; @Author: DAB, NEJ
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; @Changelog: 2022-03-25 DAB
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; 2023-09-14 NEJ
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; @Manufacturer: STM - ST Microelectronics N.V.
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; @Core: Cortex-M4F
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; @Chip: STM32L412C8, STM32L412K8, STM32L412R8, STM32L412T8,
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; STM32L412CB, STM32L412KB, STM32L412RB, STM32L412TB,
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; STM32L422CB, STM32L422KB, STM32L422RB, STM32L422TB
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; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: menstm32l412.men 16640 2023-09-21 10:18:51Z kwisniewski $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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popup "[:chip]Core Registers (Cortex-M4F)"
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(
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menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M4F),System Control"""
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menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M4F),Memory Protection Unit"""
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menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M4F),Nested Vectored Interrupt Controller"""
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menuitem "[:chip]FPU;Floating-point Unit" "per , ""Core Registers (Cortex-M4F),Floating-point Unit"""
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popup "[:chip]Debug"
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(
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menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M4F),Debug,Core Debug"""
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menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M4F),Debug,Flash Patch and Breakpoint Unit (FPB)"""
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menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M4F),Debug,Data Watchpoint and Trace Unit (DWT)"""
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)
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)
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separator
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popup "ADC;Analog-to-Digital Converter"
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(
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menuitem "ADC1" "per , ""ADC (Analog-to-Digital Converters),ADC1"""
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menuitem "ADC2" "per , ""ADC (Analog-to-Digital Converters),ADC2"""
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menuitem "ADC12_COMMON" "per , ""ADC (Analog-to-Digital Converters),ADC12_COMMON"""
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)
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menuitem "COMP;Comparator" "per , ""COMP (Comparator)"""
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menuitem "CRC;Cyclic Redundancy Check Calculation Unit" "per , ""CRC (Cyclic Redundancy Check Calculation Unit)"""
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menuitem "CRS;Clock Recovery System" "per , ""CRS (Clock Recovery System)"""
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menuitem "DBGMCU;MCU Debug Component" "per , ""DBGMCU (MCU Debug Component)"""
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popup "DMA;Direct Memory Access Controller"
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(
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menuitem "DMA1" "per , ""DMA (Direct Memory Access Controller),DMA1"""
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menuitem "DMA2" "per , ""DMA (Direct Memory Access Controller),DMA2"""
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)
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menuitem "EXTI;External Interrupt/Event Controller" "per , ""EXTI (External Interrupt/Event Controller)"""
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menuitem "FIREWALL" "per , ""FIREWALL"""
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menuitem "FLASH" "per , ""FLASH"""
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popup "GPIO;General Purpose I/O Ports and Peripheral I/O Lines"
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(
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menuitem "GPIOA" "per , ""GPIO (General Purpose I/O Ports and Peripheral I/O Lines),GPIOA"""
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menuitem "GPIOB" "per , ""GPIO (General Purpose I/O Ports and Peripheral I/O Lines),GPIOB"""
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menuitem "GPIOC" "per , ""GPIO (General Purpose I/O Ports and Peripheral I/O Lines),GPIOC"""
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menuitem "GPIOD" "per , ""GPIO (General Purpose I/O Ports and Peripheral I/O Lines),GPIOD"""
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menuitem "GPIOH" "per , ""GPIO (General Purpose I/O Ports and Peripheral I/O Lines),GPIOH"""
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)
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popup "I2C;Inter-Integrated Circuit"
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(
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menuitem "I2C1" "per , ""I2C (Inter-Integrated Circuit),I2C1"""
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menuitem "I2C2" "per , ""I2C (Inter-Integrated Circuit),I2C2"""
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menuitem "I2C3" "per , ""I2C (Inter-Integrated Circuit),I2C3"""
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)
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menuitem "IWDG;Independent Watchdog" "per , ""IWDG (Independent Watchdog)"""
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popup "LPTIM;Low Power Timer"
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(
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menuitem "LPTIM1" "per , ""LPTIM (Low Power Timer),LPTIM1"""
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menuitem "LPTIM2" "per , ""LPTIM (Low Power Timer),LPTIM2"""
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)
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menuitem "OPAMP;Operational Amplifiers" "per , ""OPAMP (Operational Amplifiers)"""
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menuitem "PWR;Power Control" "per , ""PWR (Power Control)"""
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menuitem "QUADSPI;QuadSPI Interface" "per , ""QUADSPI (QuadSPI Interface)"""
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menuitem "RCC;Reset and Clock Control" "per , ""RCC (Reset and Clock Control)"""
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menuitem "RNG;Random Number Generator" "per , ""RNG (Random Number Generator)"""
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menuitem "RTC;Real-Time Counter" "per , ""RTC (Real-Time Counter)"""
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popup "SPI;Serial Peripheral Interface/Inter-IC Sound"
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(
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menuitem "SPI1" "per , ""SPI (Serial Peripheral Interface/Inter-IC Sound),SPI1"""
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menuitem "SPI2" "per , ""SPI (Serial Peripheral Interface/Inter-IC Sound),SPI2"""
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)
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menuitem "SYSCFG;System Configuration Controller" "per , ""SYSCFG (System Configuration Controller)"""
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popup "TIM;Advanced-Timers"
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(
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menuitem "TIM1" "per , ""TIM (Advanced-Timers),TIM1"""
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menuitem "TIM2" "per , ""TIM (Advanced-Timers),TIM2"""
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menuitem "TIM6" "per , ""TIM (Advanced-Timers),TIM6"""
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menuitem "TIM15" "per , ""TIM (Advanced-Timers),TIM15"""
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menuitem "TIM16" "per , ""TIM (Advanced-Timers),TIM16"""
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)
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menuitem "TSC;Touch Sensing Controller" "per , ""TSC (Touch Sensing Controller)"""
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popup "USART;Universal Synchronous Asynchronous Receiver/Transmitter"
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(
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menuitem "LPUART1" "per , ""USART (Universal Synchronous Asynchronous Receiver/Transmitter),LPUART1"""
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menuitem "USART1" "per , ""USART (Universal Synchronous Asynchronous Receiver/Transmitter),USART1"""
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menuitem "USART2" "per , ""USART (Universal Synchronous Asynchronous Receiver/Transmitter),USART2"""
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menuitem "USART3" "per , ""USART (Universal Synchronous Asynchronous Receiver/Transmitter),USART3"""
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)
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menuitem "USB;Universal Serial Bus" "per , ""USB (Universal Serial Bus)"""
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menuitem "WWDG;System Window Watchdog" "per , ""WWDG (System Window Watchdog)"""
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)
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)
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