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Gen4_R-Car_Trace32/2_Trunk/menstm32l0.men
woody d411edd9b4 add Trace32 File
2025-10-14 09:52:32 +09:00

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; --------------------------------------------------------------------------------
; @Title: STM32L0 Specific Menu
; @Props: Released
; @Author: KNO, BGA, STR, JAM
; @Changelog: 2016-11-07 BGA
; 2017-05-20 STR
; 2019-01-23 JAM
; @Manufacturer: STM - ST Microelectronics N.V.
; @Core: Cortex-M0+
; @Chip: STM32L011D3, STM32L011D4, STM32L011E3, STM32L011E4, STM32L011F3,
; STM32L011F4, STM32L011G3, STM32L011G4, STM32L011K3, STM32L011K4,
; STM32L021D4, STM32L021F4, STM32L021G4, STM32L021K4, STM32L031C4,
; STM32L031C6, STM32L031E4, STM32L031E6, STM32L031F4, STM32L031F6,
; STM32L031G4, STM32L031G6, STM32L031K4, STM32L031K6, STM32L041C6,
; STM32L041F6, STM32L041G6, STM32L041K6, STM32L071C8, STM32L071CB,
; STM32L071CZ, STM32L071K8, STM32L071KB, STM32L071KZ, STM32L071RB,
; STM32L071RZ, STM32L071V8, STM32L071VB, STM32L071VZ, STM32L072CB,
; STM32L072KB, STM32L072KZ, STM32L072RB, STM32L072RZ, STM32L072V8,
; STM32L072VB, STM32L072VZ, STM32L073CB, STM32L073CZ, STM32L073RB,
; STM32L073RZ, STM32L073V8, STM32L073VB, STM32L073VZ, STM32L081CZ,
; STM32L081KZ, STM32L082KB, STM32L082KZ, STM32L083CB, STM32L083CZ,
; STM32L083RB, STM32L083RZ
; @Copyright: (C) 1989-2019 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: menstm32l0.men 16339 2023-07-03 13:30:14Z pegold $
add
menu
(
IF SOFTWARE.BUILD.BASE()>=69655.
(
popup "&CPU"
(
separator
IF CPU.FEATURE(MMU)
(
popup "[:mmu]MMU"
(
menuitem "[:mmureg]MMU Control" "MMU.view"
separator
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
separator
IF CPU.FEATURE(ITLBDUMP)
(
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
)
IF CPU.FEATURE(DTLBDUMP)
(
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
)
IF CPU.FEATURE(TLB0DUMP)
(
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
)
IF CPU.FEATURE(TLB1DUMP)
(
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
)
)
)
IF COMPonent.AVAILable("SMMU")
(
popup "[:mmu]SMMU"
(
menuitem "[:chip]SMMU1 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU1 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.StreamMapTable &(name)
)
IF COMPonent.AVAILable("SMMU2")
(
separator
menuitem "[:chip]SMMU2 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU2 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU3")
(
separator
menuitem "[:chip]SMMU3 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU3 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU4")
(
separator
menuitem "[:chip]SMMU4 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU4 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU5")
(
separator
menuitem "[:chip]SMMU5 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU5 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU6")
(
separator
menuitem "[:chip]SMMU6 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU6 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.StreamMapTable &(name)
)
)
)
)
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
(
popup "[:cache]Cache"
(
IF CPU.FEATURE(L1ICACHEDUMP)
(
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
menuitem "[:cache]ICACHE List" "CACHE.List IC"
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
)
IF CPU.FEATURE(L1DCACHEDUMP)
(
separator
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
menuitem "[:cache]DCACHE List" "CACHE.List DC"
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
)
IF CPU.FEATURE(L2CACHEDUMP)
(
separator
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
)
)
)
)
popup "&Trace"
(
separator
IF COMPonent.AVAILable("ITM")
(
popup "ITM"
(
default
menuitem "[:oconfig]ITM settings..." "ITM.state"
separator
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
)
)
IF COMPonent.AVAILable("STM")
(
popup "STM"
(
default
menuitem "[:oconfig]STM settings..." "STM.state"
separator
menuitem "[:alist]STMTrace List" "STMTrace.List"
)
)
IF COMPonent.AVAILable("HTM")
(
popup "HTM"
(
default
menuitem "[:oconfig]HTM settings..." "HTM.state"
separator
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
)
)
IF COMPonent.AVAILable("TPIU")
(
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
)
IF COMPonent.AVAILable("ETR")
(
menuitem "[:oconfig]ETR settings..."
(
PRIVATE &pdd
&pdd=OS.PDD()
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
)
)
)
popup "&Misc"
(
popup "Tools"
(
IF CPUIS64BIT()||CPU.FEATURE("SPR")
(
menuitem "ARM System Register Converter"
(
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
)
)
IF CPU.FEATURE("C15")
(
menuitem "ARM Coprocessor Converter"
(
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
)
)
)
)
popup "&Perf"
(
IF CPU.FEATURE(BMC)
(
before "Reset"
menuitem "[:bmc]Benchmark Counters" "BMC.state"
before "Reset"
separator
)
)
)
popup "Peripherals"
(
popup "[:chip]Core Registers (Cortex-M0+)"
(
menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M0+),System Control"""
menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M0+),Memory Protection Unit (MPU)"""
menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M0+),Nested Vectored Interrupt Controller (NVIC)"""
popup "[:chip]Debug"
(
menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M0+),Debug,Core Debug"""
menuitem "[:chip]BPU;Breakpoint Unit" "per , ""Core Registers (Cortex-M0+),Debug,Breakpoint Unit (BPU)"""
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M0+),Debug,Data Watchpoint and Trace Unit (DWT)"""
)
)
separator
menuitem "Flash" "per , ""FLASH (Flash Memory and data EEPROM)"""
menuitem "CRC" "per , ""CRC (Cyclic redundancy check calculation unit)"""
menuitem "Firewall" "per , ""FW (Firewall)"""
menuitem "Power Control" "per , ""PWR (Power Control Register)"""
menuitem "RCC" "per , ""RCC (Reset and Clock Control)"""
if !CPUIS("STM32L0?1*")
(
menuitem "CRS" "per , ""CRS (Clock recovery system)"""
)
menuitem "GPIO" "per , ""GPIO (General Port Inputs and Outputs)"""
menuitem "SYSCFG" "per , ""SYSCFG (System configuration controller)"""
menuitem "DMA" "per , ""DMA (Direct memory access controller)"""
menuitem "EXTI" "per , ""EXTI (Extended interrupt and event controller)"""
menuitem "ADC" "per , ""ADC (Analog to Digital Converter)"""
if (!CPUIS("STM32L0?1*"))
(
menuitem "DAC" "per , ""DAC (Digital to Analog Converter)"""
)
if cpuis("STM32L0?3*")
(
menuitem "LCD" "per , ""LCD (Liquid crystal display controller)"""
)
if (cpuis("STM32L0?2*"))||(cpuis("STM32L0?3*"))
(
menuitem "TSC" "per , ""TSC (Touch sensing controller)"""
)
if (!cpuis("STM32L011*")&&!cpuis("STM32L031*")&&!cpuis("STM32L051*")&&!cpuis("STM32L052*")&&!cpuis("STM32L053*")&&!cpuis("STM32L071*")&&!cpuis("STM32L072*")&&!cpuis("STM32L073*"))
(
menuitem "AES" "per , ""AES (Advanced encryption standard hardware accelerator)"""
)
if (cpuis("STM32L0?2*"))||(cpuis("STM32L0?3*"))
(
menuitem "RNG" "per , ""RNG (Random number generator)"""
)
menuitem "General purpose timers" "per , ""General purpose timers"""
if ((cpu()!="STM32L011D3")&&(cpu()!="STM32L011D4")&&(cpu()!="STM32L011E3")&&(cpu()!="STM32L011E4")&&(cpu()!="STM32L011F3")&&(cpu()!="STM32L011F4")&&(cpu()!="STM32L011G3")&&(cpu()!="STM32L011G4")&&(cpu()!="STM32L011K3")&&(cpu()!="STM32L011K4")&&(cpu()!="STM32L021D4")&&(cpu()!="STM32L021F4")&&(cpu()!="STM32L021G4")&&(cpu()!="STM32L021K4")&&(cpu()!="STM32L031C4")&&(cpu()!="STM32L031C6")&&(cpu()!="STM32L031E4")&&(cpu()!="STM32L031E6")&&(cpu()!="STM32L031F4")&&(cpu()!="STM32L031F6")&&(cpu()!="STM32L031G4")&&(cpu()!="STM32L031G6")&&(cpu()!="STM32L031K4")&&(cpu()!="STM32L031K6")&&(cpu()!="STM32L041C6")&&(cpu()!="STM32L041F6")&&(cpu()!="STM32L041G6")&&(cpu()!="STM32L041K6"))
(
menuitem "Basic timers" "per , ""Basic timers"""
)
menuitem "LPTIM1" "per , ""LPTIM1 (Low power timer 1)"""
menuitem "IWDG" "per , ""IWDG (Independent watchdog)"""
menuitem "WWDG" "per , ""WWDG (System window watchdog)"""
menuitem "RTC" "per , ""RTC (Real time clock)"""
menuitem "I2C" "per , ""I2C (Inter-integrated circuit interface)"""
menuitem "USART" "per , ""USART (Universal synchronous asynchronous receiver transmitter)"""
if (!cpuis("STM32L051K*"))&&(!cpuis("STM32L052K*"))
(
menuitem "LPUART" "per , ""LPUART (Low-power universal asynchronous receiver transmitter)"""
)
if ((cpuis("STM32L011*"))||(cpuis("STM32L021*"))||(cpuis("STM32L041*"))||(cpuis("STM32L071K*"))||(cpuis("STM32L072K*"))||(cpuis("STM32L081K*"))||(cpuis("STM32L082K*")))
(
menuitem "SPI" "per , ""SPI (Serial peripheral interface)"""
)
if ((!cpuis("STM32L011*"))&&(!cpuis("STM32L021*"))&&(!cpuis("STM32L041*"))&&(!cpuis("STM32L071K*"))&&(!cpuis("STM32L072K*"))&&(!cpuis("STM32L081K*"))&&(!cpuis("STM32L082K*")))
(
menuitem "SPI/I2S" "per , ""SPI/I2S (Serial peripheral interface/Inter-IC sound)"""
)
if (cpuis("STM32L0?2*"))||(cpuis("STM32L0?3*"))
(
menuitem "USB" "per , ""USB (Universal Serial Bus)"""
)
menuitem "DBG" "per , ""DBG (Debug support)"""
menuitem "ESIG" "per , ""Device electronic signature"""
)
)
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