453 lines
14 KiB
Plaintext
453 lines
14 KiB
Plaintext
; --------------------------------------------------------------------------------
|
|
; @Title: S32K Specific Menu
|
|
; @Props: Released
|
|
; @Author: ASK, TPP, WMA, KOL, KWI, DAB
|
|
; @Changelog: 2015-09-09 ASK
|
|
; 2016-01-20 ASK
|
|
; 2017-02-24 KOL
|
|
; 2017-05-10 ASK
|
|
; 2020-07-06 KWI
|
|
; 2022-02-04 DAB
|
|
; @Manufacturer: NXP - NXP Semiconductors
|
|
; @Core: Cortex-M4F, Cortex-M0+
|
|
; @Chip: S32K116, S32K118, S32K142, S32K144, S32K146, S32K148
|
|
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
|
|
; --------------------------------------------------------------------------------
|
|
; $Id: mens32k.men 16339 2023-07-03 13:30:14Z pegold $
|
|
|
|
add
|
|
menu
|
|
(
|
|
IF SOFTWARE.BUILD.BASE()>=69655.
|
|
(
|
|
popup "&CPU"
|
|
(
|
|
separator
|
|
IF CPU.FEATURE(MMU)
|
|
(
|
|
popup "[:mmu]MMU"
|
|
(
|
|
menuitem "[:mmureg]MMU Control" "MMU.view"
|
|
separator
|
|
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
|
|
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
|
|
separator
|
|
IF CPU.FEATURE(ITLBDUMP)
|
|
(
|
|
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
|
|
)
|
|
IF CPU.FEATURE(DTLBDUMP)
|
|
(
|
|
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
|
|
)
|
|
IF CPU.FEATURE(TLB0DUMP)
|
|
(
|
|
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
|
|
)
|
|
IF CPU.FEATURE(TLB1DUMP)
|
|
(
|
|
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
|
|
)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU")
|
|
(
|
|
popup "[:mmu]SMMU"
|
|
(
|
|
menuitem "[:chip]SMMU1 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU1 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU2")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU2 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU2 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU3")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU3 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU3 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU4")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU4 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU4 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU5")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU5 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU5 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU6")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU6 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU6 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
)
|
|
)
|
|
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
|
|
(
|
|
popup "[:cache]Cache"
|
|
(
|
|
IF CPU.FEATURE(L1ICACHEDUMP)
|
|
(
|
|
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
|
|
menuitem "[:cache]ICACHE List" "CACHE.List IC"
|
|
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
|
|
)
|
|
IF CPU.FEATURE(L1DCACHEDUMP)
|
|
(
|
|
separator
|
|
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
|
|
menuitem "[:cache]DCACHE List" "CACHE.List DC"
|
|
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
|
|
)
|
|
IF CPU.FEATURE(L2CACHEDUMP)
|
|
(
|
|
separator
|
|
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
|
|
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
|
|
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
|
|
)
|
|
)
|
|
)
|
|
)
|
|
popup "&Trace"
|
|
(
|
|
separator
|
|
IF COMPonent.AVAILable("ITM")
|
|
(
|
|
popup "ITM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]ITM settings..." "ITM.state"
|
|
separator
|
|
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("STM")
|
|
(
|
|
popup "STM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]STM settings..." "STM.state"
|
|
separator
|
|
menuitem "[:alist]STMTrace List" "STMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("HTM")
|
|
(
|
|
popup "HTM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]HTM settings..." "HTM.state"
|
|
separator
|
|
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("TPIU")
|
|
(
|
|
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
|
|
)
|
|
IF COMPonent.AVAILable("ETR")
|
|
(
|
|
menuitem "[:oconfig]ETR settings..."
|
|
(
|
|
PRIVATE &pdd
|
|
&pdd=OS.PDD()
|
|
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
|
|
)
|
|
)
|
|
)
|
|
popup "&Misc"
|
|
(
|
|
popup "Tools"
|
|
(
|
|
IF CPUIS64BIT()||CPU.FEATURE("SPR")
|
|
(
|
|
menuitem "ARM System Register Converter"
|
|
(
|
|
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
|
|
)
|
|
)
|
|
IF CPU.FEATURE("C15")
|
|
(
|
|
menuitem "ARM Coprocessor Converter"
|
|
(
|
|
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
|
|
)
|
|
)
|
|
)
|
|
)
|
|
popup "&Perf"
|
|
(
|
|
IF CPU.FEATURE(BMC)
|
|
(
|
|
before "Reset"
|
|
menuitem "[:bmc]Benchmark Counters" "BMC.state"
|
|
before "Reset"
|
|
separator
|
|
)
|
|
)
|
|
)
|
|
popup "Peripherals"
|
|
(
|
|
if (STRING.SCAN(CORENAME(),"M4",0.)>0.)
|
|
(
|
|
popup "[:chip]Core Registers (Cortex-M4F)"
|
|
(
|
|
menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M4F),System Control"""
|
|
menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M4F),Memory Protection Unit"""
|
|
menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M4F),Nested Vectored Interrupt Controller"""
|
|
menuitem "[:chip]FPU;Floating-point Unit" "per , ""Core Registers (Cortex-M4F),Floating-point Unit"""
|
|
popup "[:chip]Debug"
|
|
(
|
|
menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M4F),Debug,Core Debug"""
|
|
menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M4F),Debug,Flash Patch and Breakpoint Unit (FPB)"""
|
|
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M4F),Debug,Data Watchpoint and Trace Unit (DWT)"""
|
|
)
|
|
)
|
|
)
|
|
else
|
|
(
|
|
popup "[:chip]Core Registers (Cortex-M0+)"
|
|
(
|
|
menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M0+),System Control"""
|
|
menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M0+),Memory Protection Unit (MPU)"""
|
|
menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M0+),Nested Vectored Interrupt Controller (NVIC)"""
|
|
popup "[:chip]Debug"
|
|
(
|
|
menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M0+),Debug,Core Debug"""
|
|
menuitem "[:chip]BPU;Breakpoint Unit" "per , ""Core Registers (Cortex-M0+),Debug,Breakpoint Unit (BPU)"""
|
|
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M0+),Debug,Data Watchpoint and Trace Unit (DWT)"""
|
|
)
|
|
)
|
|
)
|
|
separator
|
|
menuitem "CSE_PRAM" "per , ""CSE_PRAM,CSE_PRAM"""
|
|
menuitem "AIPS" "per , ""AIPS (AIPS-Lite Bridge)"""
|
|
menuitem "MSCM" "per , ""MSCM"""
|
|
menuitem "DMA" "per , ""DMA (Enhanced Direct Memory Access)"""
|
|
menuitem "MPU" "per , ""MPU (Memory protection unit)"""
|
|
menuitem "ERM" "per , ""ERM"""
|
|
menuitem "EIM" "per , ""EIM (Error Injection Module)"""
|
|
menuitem "FTFC" "per , ""FTFC"""
|
|
menuitem "DMAMUX" "per , ""DMAMUX (DMA channel multiplexor)"""
|
|
menuitem "CRC" "per , ""CRC (Cyclic Redundancy Check)"""
|
|
menuitem "LPIT0" "per , ""LPIT0 (Low Power Periodic Interrupt Timer (LPIT))"""
|
|
menuitem "RTC" "per , ""RTC (Real-time Counter)"""
|
|
menuitem "LPTMR0" "per , ""LPTMR0 (Low Power Timer)"""
|
|
menuitem "SIM" "per , ""SIM (System Integration Module)"""
|
|
menuitem "WDOG" "per , ""WDOG (Watchdog Timer Unit)"""
|
|
menuitem "FLEXIO" "per , ""FLEXIO (The FLEXIO Memory Map/Register Definition can be found here.)"""
|
|
if (cpuis("S32K148")||cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146"))
|
|
(
|
|
menuitem "EWM" "per , ""EWM (External Watchdog Monitor),EWM"""
|
|
)
|
|
menuitem "TRGMUX" "per , ""TRGMUX"""
|
|
menuitem "SCG" "per , ""SCG (System Clock Generator)"""
|
|
menuitem "PCC" "per , ""PCC"""
|
|
menuitem "CMP0" "per , ""CMP0 (High-Speed Comparator (CMP) Voltage Reference (VREF) Digital-to-Analog Converter (DAC) and Analog Mux (ANMUX))"""
|
|
if (cpuis("S32K148"))
|
|
(
|
|
menuitem "QUADSPI" "per , ""QUADSPI (QuadSPI),QUADSPI"""
|
|
menuitem "ENET" "per , ""ENET (Ethernet MAC),ENET"""
|
|
)
|
|
menuitem "PMC" "per , ""PMC"""
|
|
menuitem "SMC" "per , ""SMC (System Mode Controller)"""
|
|
menuitem "RCM" "per , ""RCM (Reset Control Module)"""
|
|
menuitem "S32_SCB" "per , ""S32_SCB (System Control Registers)"""
|
|
menuitem "S32_SYSTICK" "per , ""S32_SYSTICK (System timer)"""
|
|
menuitem "S32_NVIC" "per , ""S32_NVIC (Nested Vectored Interrupt Controller)"""
|
|
menuitem "MCM" "per , ""MCM (Core Platform Miscellaneous Control Module),MCM"""
|
|
menuitem "LMEM" "per , ""LMEM (Local Memory Controller)"""
|
|
if (cpuis("S32K148")||cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146"))
|
|
(
|
|
popup "CAN (Flex Controller Area Network module)"
|
|
(
|
|
menuitem "CAN0" "per , ""CAN (Flex Controller Area Network module),CAN0"""
|
|
menuitem "CAN1" "per , ""CAN (Flex Controller Area Network module),CAN1"""
|
|
if (cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148"))
|
|
(
|
|
menuitem "CAN2" "per , ""CAN (Flex Controller Area Network module),CAN2"""
|
|
)
|
|
)
|
|
)
|
|
popup "FTM (FlexTimer Module)"
|
|
(
|
|
menuitem "FTM0" "per , ""FTM (FlexTimer Module),FTM0"""
|
|
menuitem "FTM1" "per , ""FTM (FlexTimer Module),FTM1"""
|
|
if (cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148"))
|
|
(
|
|
menuitem "FTM2" "per , ""FTM (FlexTimer Module),FTM2"""
|
|
menuitem "FTM3" "per , ""FTM (FlexTimer Module),FTM3"""
|
|
)
|
|
if (cpuis("S32K146")||cpuis("S32K148"))
|
|
(
|
|
menuitem "FTM4" "per , ""FTM (FlexTimer Module),FTM4"""
|
|
menuitem "FTM5" "per , ""FTM (FlexTimer Module),FTM5"""
|
|
)
|
|
if (cpuis("S32K148"))
|
|
(
|
|
menuitem "FTM6" "per , ""FTM (FlexTimer Module),FTM6"""
|
|
menuitem "FTM7" "per , ""FTM (FlexTimer Module),FTM7"""
|
|
)
|
|
)
|
|
if (cpuis("S32K148")||cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146"))
|
|
(
|
|
popup "ADC (Analog-to-Digital Converter)"
|
|
(
|
|
menuitem "ADC0" "per , ""ADC (Analog-to-Digital Converter),ADC0"""
|
|
menuitem "ADC1" "per , ""ADC (Analog-to-Digital Converter),ADC1"""
|
|
)
|
|
)
|
|
if (cpuis("S32K148")||cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146"))
|
|
(
|
|
popup "LPSPI (The LPSPI Memory Map/Register Definition can be found here.)"
|
|
(
|
|
menuitem "LPSPI0" "per , ""LPSPI (The LPSPI Memory Map/Register Definition can be found here.),LPSPI0"""
|
|
menuitem "LPSPI1" "per , ""LPSPI (The LPSPI Memory Map/Register Definition can be found here.),LPSPI1"""
|
|
if (cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148"))
|
|
(
|
|
menuitem "LPSPI2" "per , ""LPSPI (The LPSPI Memory Map/Register Definition can be found here.),LPSPI2"""
|
|
)
|
|
)
|
|
)
|
|
if (cpuis("S32K148")||cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146"))
|
|
(
|
|
popup "PDB (Programmable Delay Block)"
|
|
(
|
|
menuitem "PDB0" "per , ""PDB (Programmable Delay Block),PDB0"""
|
|
menuitem "PDB1" "per , ""PDB (Programmable Delay Block),PDB1"""
|
|
)
|
|
)
|
|
popup "PORT (Pin Control and Interrupts)"
|
|
(
|
|
menuitem "PORTA" "per , ""PORT (Pin Control and Interrupts),PORTA"""
|
|
menuitem "PORTB" "per , ""PORT (Pin Control and Interrupts),PORTB"""
|
|
menuitem "PORTC" "per , ""PORT (Pin Control and Interrupts),PORTC"""
|
|
menuitem "PORTD" "per , ""PORT (Pin Control and Interrupts),PORTD"""
|
|
menuitem "PORTE" "per , ""PORT (Pin Control and Interrupts),PORTE"""
|
|
)
|
|
if (cpuis("S32K148"))
|
|
(
|
|
popup "SAI (Synchronous Serial Interface)"
|
|
(
|
|
menuitem "SAI0" "per , ""SAI (Synchronous Serial Interface),SAI0"""
|
|
menuitem "SAI1" "per , ""SAI (Synchronous Serial Interface),SAI1"""
|
|
)
|
|
popup "LPI2C (The LPI2C Memory Map/Register Definition can be found here.)"
|
|
(
|
|
menuitem "LPI2C0" "per , ""LPI2C (The LPI2C Memory Map/Register Definition can be found here.),LPI2C0"""
|
|
menuitem "LPI2C1" "per , ""LPI2C (The LPI2C Memory Map/Register Definition can be found here.),LPI2C1"""
|
|
)
|
|
)
|
|
popup "LPUART (Universal Asynchronous Receiver/Transmitter)"
|
|
(
|
|
menuitem "LPUART0" "per , ""LPUART (Universal Asynchronous Receiver/Transmitter),LPUART0"""
|
|
menuitem "LPUART1" "per , ""LPUART (Universal Asynchronous Receiver/Transmitter),LPUART1"""
|
|
if (cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148"))
|
|
(
|
|
menuitem "LPUART2" "per , ""LPUART (Universal Asynchronous Receiver/Transmitter),LPUART2"""
|
|
)
|
|
)
|
|
popup "GPIO (General Purpose I/O Ports And Peripheral I/O Lines)"
|
|
(
|
|
menuitem "PTA" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),PTA"""
|
|
menuitem "PTB" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),PTB"""
|
|
menuitem "PTC" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),PTC"""
|
|
menuitem "PTD" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),PTD"""
|
|
menuitem "PTE" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),PTE"""
|
|
)
|
|
menuitem "MDM-AP" "per , ""MDM-AP"""
|
|
if (cpuis("S32K116")||cpuis("S32K118"))
|
|
(
|
|
menuitem "CAN0" "per , ""CAN0 (Flex Controller Area Network module),CAN0"""
|
|
)
|
|
if (cpuis("S32K116"))
|
|
(
|
|
menuitem "LPSPI0" "per , ""LPSPI0 (The LPSPI Memory Map/Register Definition can be found here.),LPSPI0"""
|
|
)
|
|
if (cpuis("S32K116")||cpuis("S32K118"))
|
|
(
|
|
menuitem "PDB0" "per , ""PDB0 (Programmable Delay Block),PDB0"""
|
|
menuitem "ADC0" "per , ""ADC0 (Analog-to-Digital Converter),ADC0"""
|
|
)
|
|
if (cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146"))
|
|
(
|
|
menuitem "LPI2C0" "per , ""LPI2C0 (The LPI2C Memory Map/Register Definition can be found here.),LPI2C0"""
|
|
)
|
|
if (cpuis("S32K116")||cpuis("S32K118"))
|
|
(
|
|
popup "CMU_FC"
|
|
(
|
|
menuitem "CMU_FC_0" "per , ""CMU_FC,CMU_FC_0"""
|
|
menuitem "CMU_FC_1" "per , ""CMU_FC,CMU_FC_1"""
|
|
)
|
|
)
|
|
)
|
|
)
|