439 lines
20 KiB
Plaintext
439 lines
20 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: RZN2L Specific Menu
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; @Props: Released
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; @Author: NEJ, KRZ
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; @Changelog: 2022-06-21 NEJ
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; 2022-07-06 KRZ
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; 2022-08-10 KRZ
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; @Manufacturer: RENESAS - Renesas Technology, Corp.
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; @Core: Cortex-R52
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; @Chip: RZN2L
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: menrzn2l.men 16339 2023-07-03 13:30:14Z pegold $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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popup "[:chip]Core Registers (Cortex-R52)"
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(
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menuitem "[:chip]ID Registers" "per , ""Core Registers (Cortex-R52),ID Registers"""
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menuitem "[:chip]System Control and Configuration" "per , ""Core Registers (Cortex-R52),System Control and Configuration"""
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menuitem "[:chip]MPU Control and Configuration" "per , ""Core Registers (Cortex-R52),MPU Control and Configuration"""
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menuitem "[:chip]Memory Protection Unit PL1" "per , ""Core Registers (Cortex-R52),Memory Protection Unit PL1"""
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menuitem "[:chip]Memory Protection Unit PL2" "per , ""Core Registers (Cortex-R52),Memory Protection Unit PL2"""
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menuitem "[:chip]Virtualization Extensions" "per , ""Core Registers (Cortex-R52),Virtualization Extensions"""
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menuitem "[:chip]Cache Control and Configuration" "per , ""Core Registers (Cortex-R52),Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor" "per , ""Core Registers (Cortex-R52),System Performance Monitor"""
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menuitem "[:chip]System Timer Registers" "per , ""Core Registers (Cortex-R52),System Timer Registers"""
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menuitem "[:chip]Generic Interrupt Controller CPU Interface" "per , ""Core Registers (Cortex-R52),Generic Interrupt Controller CPU Interface"""
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separator
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menuitem "[:chip]Debug Registers" "per , ""Core Registers (Cortex-R52),Debug Registers"""
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separator
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menuitem "[:chip]Breakpoint Registers" "per , ""Core Registers (Cortex-R52),Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Registers" "per , ""Core Registers (Cortex-R52),Watchpoint Registers"""
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)
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separator
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popup "ADC;12-Bit A/D Converter"
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(
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menuitem "ADC120" "per , ""ADC (12-Bit A/D Converter),ADC120"""
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menuitem "ADC121" "per , ""ADC (12-Bit A/D Converter),ADC121"""
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)
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menuitem "BSC;Bus State Controller" "per , ""BSC (Bus State Controller)"""
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menuitem "CANFD;CAN-FD" "per , ""CANFD (CAN-FD)"""
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popup "CLMA;Clock Monitor Circuit"
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(
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menuitem "CLMA0" "per , ""CLMA (Clock Monitor Circuit),CLMA0"""
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menuitem "CLMA1" "per , ""CLMA (Clock Monitor Circuit),CLMA1"""
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menuitem "CLMA2" "per , ""CLMA (Clock Monitor Circuit),CLMA2"""
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menuitem "CLMA3" "per , ""CLMA (Clock Monitor Circuit),CLMA3"""
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)
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popup "CMT;Compare Match Timer"
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(
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menuitem "CMT0" "per , ""CMT (Compare Match Timer),CMT0"""
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menuitem "CMT1" "per , ""CMT (Compare Match Timer),CMT1"""
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menuitem "CMT2" "per , ""CMT (Compare Match Timer),CMT2"""
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menuitem "CMT3" "per , ""CMT (Compare Match Timer),CMT3"""
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menuitem "CMT4" "per , ""CMT (Compare Match Timer),CMT4"""
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menuitem "CMT5" "per , ""CMT (Compare Match Timer),CMT5"""
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)
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menuitem "CMTC;Compare Match Timer Control" "per , ""CMTC (Compare Match Timer Control)"""
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popup "CMTW;Compare Match Timer W"
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(
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menuitem "CMTW0" "per , ""CMTW (Compare Match Timer W),CMTW0"""
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menuitem "CMTW1" "per , ""CMTW (Compare Match Timer W),CMTW1"""
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)
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popup "CRC;CRC Unit"
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(
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menuitem "CRC0" "per , ""CRC (CRC Unit),CRC0"""
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menuitem "CRC1" "per , ""CRC (CRC Unit),CRC1"""
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)
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menuitem "DMA;DMAC Configuration" "per , ""DMA (DMAC Configuration)"""
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popup "DMAC;DMA Controller"
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(
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menuitem "DMAC0" "per , ""DMAC (DMA Controller),DMAC0"""
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menuitem "DMAC1" "per , ""DMAC (DMA Controller),DMAC1"""
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)
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menuitem "DOC;Data Operation Circuit" "per , ""DOC (Data Operation Circuit)"""
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popup "DSMIF;Delta-Sigma Interface"
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(
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menuitem "DSMIF0" "per , ""DSMIF (Delta-Sigma Interface),DSMIF0"""
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menuitem "DSMIF1" "per , ""DSMIF (Delta-Sigma Interface),DSMIF1"""
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)
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menuitem "ELC;Evnet Link Controller" "per , ""ELC (Evnet Link Controller)"""
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menuitem "ELO;Evnet Link Option Setting" "per , ""ELO (Evnet Link Option Setting)"""
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menuitem "ESC;EtherCAT Slave Controller" "per , ""ESC (EtherCAT Slave Controller)"""
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menuitem "ESC_INI;Initial Configuration for EtherCAT Slave.." "per , ""ESC_INI (Initial Configuration for EtherCAT Slave Controller)"""
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menuitem "ETHSS;Ethernet Subsystem" "per , ""ETHSS (Ethernet Subsystem)"""
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menuitem "ETHSW;Ethernet Switch" "per , ""ETHSW (Ethernet Switch)"""
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menuitem "ETHSW_PTP;Ethernet Switch for PTP" "per , ""ETHSW_PTP (Ethernet Switch for PTP)"""
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menuitem "GMAC;Ethernet MAC" "per , ""GMAC (Ethernet MAC)"""
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popup "GPT;General Purpose Timer"
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(
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menuitem "GPT0" "per , ""GPT (General Purpose Timer),GPT0"""
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menuitem "GPT1" "per , ""GPT (General Purpose Timer),GPT1"""
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menuitem "GPT2" "per , ""GPT (General Purpose Timer),GPT2"""
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menuitem "GPT3" "per , ""GPT (General Purpose Timer),GPT3"""
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menuitem "GPT4" "per , ""GPT (General Purpose Timer),GPT4"""
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menuitem "GPT5" "per , ""GPT (General Purpose Timer),GPT5"""
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menuitem "GPT6" "per , ""GPT (General Purpose Timer),GPT6"""
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menuitem "GPT7" "per , ""GPT (General Purpose Timer),GPT7"""
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menuitem "GPT8" "per , ""GPT (General Purpose Timer),GPT8"""
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menuitem "GPT9" "per , ""GPT (General Purpose Timer),GPT9"""
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menuitem "GPT10" "per , ""GPT (General Purpose Timer),GPT10"""
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menuitem "GPT11" "per , ""GPT (General Purpose Timer),GPT11"""
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menuitem "GPT12" "per , ""GPT (General Purpose Timer),GPT12"""
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menuitem "GPT13" "per , ""GPT (General Purpose Timer),GPT13"""
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menuitem "GPT14" "per , ""GPT (General Purpose Timer),GPT14"""
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menuitem "GPT15" "per , ""GPT (General Purpose Timer),GPT15"""
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menuitem "GPT16" "per , ""GPT (General Purpose Timer),GPT16"""
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menuitem "GPT17" "per , ""GPT (General Purpose Timer),GPT17"""
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)
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menuitem "GSC;Global System Counter" "per , ""GSC (Global System Counter)"""
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menuitem "ICU;Interrupt Controller" "per , ""ICU (Interrupt Controller)"""
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menuitem "ICU_NS;Interrupt Controller in Non Safety Domain" "per , ""ICU_NS (Interrupt Controller in Non Safety Domain)"""
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popup "IIC;I2C Bus Interface"
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(
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menuitem "IIC0" "per , ""IIC (I2C Bus Interface),IIC0"""
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menuitem "IIC1" "per , ""IIC (I2C Bus Interface),IIC1"""
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menuitem "IIC2" "per , ""IIC (I2C Bus Interface),IIC2"""
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)
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menuitem "MBXSEM;Mailbox and Semaphore" "per , ""MBXSEM (Mailbox and Semaphore)"""
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popup "MPU;Master MPU"
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(
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menuitem "MPU0" "per , ""MPU (Master MPU),MPU0"""
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menuitem "MPU1" "per , ""MPU (Master MPU),MPU1"""
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menuitem "MPU2" "per , ""MPU (Master MPU),MPU2"""
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menuitem "MPU3" "per , ""MPU (Master MPU),MPU3"""
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menuitem "MPU4" "per , ""MPU (Master MPU),MPU4"""
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menuitem "MPU6" "per , ""MPU (Master MPU),MPU6"""
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menuitem "MPU7" "per , ""MPU (Master MPU),MPU7"""
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menuitem "MPU8" "per , ""MPU (Master MPU),MPU8"""
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)
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menuitem "MTU;Multi-Function Timer Pulse Unit" "per , ""MTU (Memory Test Unit)"""
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menuitem "MTU_NF;Multi-Function Timer Pulse Unit Noise Filter" "per , ""MTU_NF (Multi-Function Timer Pulse Unit Noise Filter)"""
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popup "MTU;Memory Test Unit"
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(
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menuitem "MTU0" "per , ""MTU (Memory Test Unit),MTU0"""
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menuitem "MTU1" "per , ""MTU (Memory Test Unit),MTU1"""
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menuitem "MTU2" "per , ""MTU (Memory Test Unit),MTU2"""
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menuitem "MTU3" "per , ""MTU (Memory Test Unit),MTU3"""
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menuitem "MTU4" "per , ""MTU (Memory Test Unit),MTU4"""
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menuitem "MTU5" "per , ""MTU (Memory Test Unit),MTU5"""
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menuitem "MTU6" "per , ""MTU (Memory Test Unit),MTU6"""
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menuitem "MTU7" "per , ""MTU (Memory Test Unit),MTU7"""
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menuitem "MTU8" "per , ""MTU (Memory Test Unit),MTU8"""
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)
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menuitem "OTP;One-Time Programmable Memory" "per , ""OTP (One-Time Programmable Memory)"""
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menuitem "PHOSTIF;Parallel Host Interface" "per , ""PHOSTIF (Parallel Host Interface)"""
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menuitem "PHOSTIF_CFG;Parallel Host Interface Configuration" "per , ""PHOSTIF_CFG (Parallel Host Interface Configuration)"""
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menuitem "POE3;Port Output Enable 3" "per , ""POE3 (Port Output Enable 3)"""
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popup "POEG;GPT Port Output Enable"
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(
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menuitem "POEG0" "per , ""POEG (GPT Port Output Enable),POEG0"""
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menuitem "POEG1" "per , ""POEG (GPT Port Output Enable),POEG1"""
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menuitem "POEG2" "per , ""POEG (GPT Port Output Enable),POEG2"""
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)
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menuitem "PORT_NSR;I/O Ports (Non safety region)" "per , ""PORT_NSR (I/O Ports (Non safety region))"""
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menuitem "PORT_SR;I/O Ports (Safety region)" "per , ""PORT_SR (I/O Ports (Safety region))"""
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menuitem "PTADR;Port Address Selection" "per , ""PTADR (Port Address Selection)"""
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menuitem "RTC;Real Time Clock" "per , ""RTC (Real-time Counter)"""
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menuitem "RWP_NS;Register Write Protection for Non-safety Area" "per , ""RWP_NS (Register Write Protection for Non-safety Area)"""
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menuitem "RWP_S;Register Write Protection for Safety Area" "per , ""RWP_S (Register Write Protection for Safety Area)"""
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popup "SCI;Serial Communication Interface"
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(
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menuitem "SCI0" "per , ""SCI (Serial Communication Interface),SCI0"""
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menuitem "SCI1" "per , ""SCI (Serial Communication Interface),SCI1"""
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menuitem "SCI2" "per , ""SCI (Serial Communication Interface),SCI2"""
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menuitem "SCI3" "per , ""SCI (Serial Communication Interface),SCI3"""
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menuitem "SCI4" "per , ""SCI (Serial Communication Interface),SCI4"""
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menuitem "SCI5" "per , ""SCI (Serial Communication Interface),SCI5"""
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)
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menuitem "SHOSTIF;Serial Host Interface" "per , ""SHOSTIF (Serial Host Interface)"""
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menuitem "SHOSTIF_CFG;Serial Host Interface Configuration" "per , ""SHOSTIF_CFG (Serial Host Interface Configuration)"""
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popup "SPI;Serial Peripheral Interface"
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(
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menuitem "SPI0" "per , ""SPI (Serial Peripheral Interface),SPI0"""
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menuitem "SPI1" "per , ""SPI (Serial Peripheral Interface),SPI1"""
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menuitem "SPI2" "per , ""SPI (Serial Peripheral Interface),SPI2"""
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menuitem "SPI3" "per , ""SPI (Serial Peripheral Interface),SPI3"""
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)
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menuitem "SYSC_NS;System Control for Non-safety region" "per , ""SYSC_NS (System Control for Non-safety region)"""
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menuitem "SYSC_S;Register Write Protection for Safety Area" "per , ""SYSC_S (Register Write Protection for Safety Area)"""
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menuitem "SYSRAM_CTL;System SRAM Control" "per , ""SYSRAM_CTL (System SRAM Control)"""
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popup "SYSRAM;System SRAM"
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(
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menuitem "SYSRAM0" "per , ""SYSRAM (System SRAM),SYSRAM0"""
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menuitem "SYSRAM1" "per , ""SYSRAM (System SRAM),SYSRAM1"""
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menuitem "SYSRAM2" "per , ""SYSRAM (System SRAM),SYSRAM2"""
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)
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menuitem "TFU;Trigonometric Function Unit" "per , ""TFU (Trigonometric Function Unit)"""
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menuitem "TSU;Temperature Sensor Unit" "per , ""TSU (Temperature Sensor Unit)"""
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menuitem "USBF;USB 2.0 Host and Function Module" "per , ""USBF (USB 2.0 Host and Function Module)"""
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menuitem "USBHC;USB 2.0 HS Host Module" "per , ""USBHC (USB 2.0 HS Host Module)"""
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menuitem "WDT;Watchdog Timer" "per , ""WDT0 (Watchdog Timer)"""
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popup "XSPI;xSPI"
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(
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menuitem "XSPI0" "per , ""XSPI (xSPI),XSPI0"""
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menuitem "XSPI1" "per , ""XSPI (xSPI),XSPI1"""
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)
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)
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)
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