496 lines
18 KiB
Plaintext
496 lines
18 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: RCARV3U Specific Menu
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; @Props: Released
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; @Author: KWI, PIW
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; @Changelog: 2020-09-17 KWI
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; 2022-05-23 PIW
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; @Manufacturer: RENESAS - Renesas Technology, Corp.
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; @Core: Cortex-A76, Cortex-R52
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; @Chip: R8A779A0, R8A779A0-R52
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: menrcarv3u.men 16339 2023-07-03 13:30:14Z pegold $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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if (CORENAME()=="CORTEXR52")
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(
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popup "[:chip]Core Registers (Cortex-R52)"
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(
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menuitem "[:chip]ID Registers" "per , ""Core Registers (Cortex-R52),ID Registers"""
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menuitem "[:chip]System Control and Configuration" "per , ""Core Registers (Cortex-R52),System Control and Configuration"""
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menuitem "[:chip]MPU Control and Configuration" "per , ""Core Registers (Cortex-R52),MPU Control and Configuration"""
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menuitem "[:chip]Memory Protection Unit PL1" "per , ""Core Registers (Cortex-R52),Memory Protection Unit PL1"""
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menuitem "[:chip]Memory Protection Unit PL2" "per , ""Core Registers (Cortex-R52),Memory Protection Unit PL2"""
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menuitem "[:chip]Virtualization Extensions" "per , ""Core Registers (Cortex-R52),Virtualization Extensions"""
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menuitem "[:chip]Cache Control and Configuration" "per , ""Core Registers (Cortex-R52),Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor" "per , ""Core Registers (Cortex-R52),System Performance Monitor"""
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menuitem "[:chip]System Timer Registers" "per , ""Core Registers (Cortex-R52),System Timer Registers"""
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menuitem "[:chip]Generic Interrupt Controller CPU Interface" "per , ""Core Registers (Cortex-R52),Generic Interrupt Controller CPU Interface"""
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separator
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menuitem "[:chip]Debug Registers" "per , ""Core Registers (Cortex-R52),Debug Registers"""
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separator
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menuitem "[:chip]Breakpoint Registers" "per , ""Core Registers (Cortex-R52),Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Registers" "per , ""Core Registers (Cortex-R52),Watchpoint Registers"""
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separator
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menuitem "[:chip]Interrupt Controller (GIC-500)" "per , ""Core Registers (Cortex-R52),Interrupt Controller (GIC-500)"""
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)
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)
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if (CORENAME()=="CORTEXA76")
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(
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popup "[:chip]Core Registers (Cortex-A76)"
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(
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menuitem "[:chip]ID Registers[AArch64]" "per , ""Core Registers (Cortex-A76),AArch64,ID Registers"""
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menuitem "[:chip]System Control And Configuration[AArch64]" "per , ""Core Registers (Cortex-A76),AArch64,System Control And Configuration"""
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menuitem "[:chip]System Instructions[AArch64]" "per , ""Core Registers (Cortex-A76),AArch64,System Instructions"""
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menuitem "[:chip]Memory Management Unit[AArch64]" "per , ""Core Registers (Cortex-A76),AArch64,Memory Management Unit"""
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menuitem "[:chip]Virtualization Extensions[AArch64]" "per , ""Core Registers (Cortex-A76),AArch64,Virtualization Extensions"""
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menuitem "[:chip]Cache Control And Configuration[AArch64]" "per , ""Core Registers (Cortex-A76),AArch64,Cache Control And Configuration"""
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menuitem "[:chip]System Performance Monitor[AArch64]" "per , ""Core Registers (Cortex-A76),AArch64,System Performance Monitor"""
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menuitem "[:chip]System Timer Registers[AArch64]" "per , ""Core Registers (Cortex-A76),AArch64,System Timer Registers"""
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menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch64]" "per , ""Core Registers (Cortex-A76),AArch64,Generic Interrupt Controller CPU Interface"""
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separator
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menuitem "[:chip]Debug Registers[AArch64]" "per , ""Core Registers (Cortex-A76),AArch64,Debug Registers"""
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separator
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menuitem "[:chip]Activity Monitors Unit[AArch64]" "per , ""Core Registers (Cortex-A76),AArch64,Activity Monitors Unit"""
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menuitem "[:chip]Breakpoint Registers[AArch64]" "per , ""Core Registers (Cortex-A76),AArch64,Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Registers[AArch64]" "per , ""Core Registers (Cortex-A76),AArch64,Watchpoint Registers"""
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separator
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menuitem "[:chip]LORegions Registers[AArch64]" "per , ""Core Registers (Cortex-A76),AArch64,LORegions Registers"""
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separator
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menuitem "[:chip]DynamIQ Shared Unit[AArch64]" "per , ""Core Registers (Cortex-A76),AArch64,DynamIQ Shared Unit"""
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separator
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menuitem "[:chip]System Control And Configuration[AArch32]" "per , ""Core Registers (Cortex-A76),AArch32,System Control And Configuration"""
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menuitem "[:chip]System Instructions[AArch32]" "per , ""AArch32,System Instructions"""
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menuitem "[:chip]Virtualization Extensions[AArch32]" "per , ""Core Registers (Cortex-A76),AArch32,Virtualization Extensions"""
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menuitem "[:chip]System Performance Monitor[AArch32]" "per , ""Core Registers (Cortex-A76),AArch32,System Performance Monitor"""
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menuitem "[:chip]System Timer Registers[AArch32]" "per , ""Core Registers (Cortex-A76),AArch32,System Timer Registers"""
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separator
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menuitem "[:chip]Debug Registers[AArch32]" "per , ""Core Registers (Cortex-A76),AArch32,Debug Registers"""
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separator
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menuitem "[:chip]Interrupt Controller (GIC-500)" "per , ""Core Registers (Cortex-A76),Interrupt Controller (GIC-500)"""
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)
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)
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separator
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popup "PFC"
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(
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menuitem "PFC_0" "per , ""PFC,PFC_0"""
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menuitem "PFC_1" "per , ""PFC,PFC_1"""
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menuitem "PFC_2" "per , ""PFC,PFC_2"""
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menuitem "PFC_3" "per , ""PFC,PFC_3"""
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)
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menuitem "PFC_SYS" "per , ""PFC_SYS"""
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menuitem "CPG" "per , ""CPG"""
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menuitem "MSTPCR" "per , ""MSTPCR"""
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menuitem "MSTPSR" "per , ""MSTPSR"""
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menuitem "SRCR" "per , ""SRCR"""
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popup "APMU_Domain"
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(
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menuitem "APMU_Domain_0" "per , ""APMU_Domain,APMU_Domain_0"""
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menuitem "APMU_Domain_1" "per , ""APMU_Domain,APMU_Domain_1"""
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menuitem "APMU_Domain_2" "per , ""APMU_Domain,APMU_Domain_2"""
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menuitem "APMU_Domain_3" "per , ""APMU_Domain,APMU_Domain_3"""
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)
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popup "SYSC"
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(
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menuitem "SYSC_0" "per , ""SYSC,SYSC_0"""
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menuitem "SYSC_1" "per , ""SYSC,SYSC_1"""
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menuitem "SYSC_2" "per , ""SYSC,SYSC_2"""
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menuitem "SYSC_3" "per , ""SYSC,SYSC_3"""
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)
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popup "TSC"
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(
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menuitem "TSC_0" "per , ""TSC,TSC_0"""
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menuitem "TSC_1" "per , ""TSC,TSC_1"""
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menuitem "TSC_2" "per , ""TSC,TSC_2"""
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menuitem "TSC_3" "per , ""TSC,TSC_3"""
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menuitem "TSC_4" "per , ""TSC,TSC_4"""
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)
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popup "INTC"
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(
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menuitem "INTC" "per , ""INTC,INTC"""
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menuitem "INTC-EX" "per , ""INTC,INTC-EX"""
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)
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menuitem "MFIS" "per , ""MFIS"""
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menuitem "ECM" "per , ""ECM"""
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menuitem "AXI" "per , ""AXI"""
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menuitem "AXMM" "per , ""AXMM"""
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menuitem "QOS" "per , ""QOS"""
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menuitem "RT_SRAM" "per , ""RT_SRAM"""
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menuitem "BKBUF" "per , ""BKBUF"""
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menuitem "VCP" "per , ""VCP"""
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popup "SCIF"
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(
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menuitem "SCIF_0" "per , ""SCIF,SCIF_0"""
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menuitem "SCIF_1" "per , ""SCIF,SCIF_1"""
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menuitem "SCIF_2" "per , ""SCIF,SCIF_2"""
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menuitem "SCIF_3" "per , ""SCIF,SCIF_3"""
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)
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popup "HSCIF"
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(
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menuitem "HSCIF_0" "per , ""HSCIF,HSCIF_0"""
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menuitem "HSCIF_1" "per , ""HSCIF,HSCIF_1"""
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menuitem "HSCIF_2" "per , ""HSCIF,HSCIF_2"""
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menuitem "HSCIF_3" "per , ""HSCIF,HSCIF_3"""
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)
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popup "I2C"
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(
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menuitem "I2C_0" "per , ""I2C,I2C_0"""
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menuitem "I2C_1" "per , ""I2C,I2C_1"""
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menuitem "I2C_2" "per , ""I2C,I2C_2"""
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menuitem "I2C_3" "per , ""I2C,I2C_3"""
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menuitem "I2C_4" "per , ""I2C,I2C_4"""
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menuitem "I2C_5" "per , ""I2C,I2C_5"""
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menuitem "I2C_6" "per , ""I2C,I2C_6"""
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)
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popup "MSIOF"
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(
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menuitem "MSIOF_0" "per , ""MSIOF,MSIOF_0"""
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menuitem "MSIOF_1" "per , ""MSIOF,MSIOF_1"""
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menuitem "MSIOF_2" "per , ""MSIOF,MSIOF_2"""
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menuitem "MSIOF_3" "per , ""MSIOF,MSIOF_3"""
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menuitem "MSIOF_4" "per , ""MSIOF,MSIOF_4"""
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menuitem "MSIOF_5" "per , ""MSIOF,MSIOF_5"""
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)
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popup "PWM"
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(
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menuitem "PWM_0" "per , ""PWM,PWM_0"""
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menuitem "PWM_1" "per , ""PWM,PWM_1"""
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menuitem "PWM_2" "per , ""PWM,PWM_2"""
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menuitem "PWM_3" "per , ""PWM,PWM_3"""
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menuitem "PWM_4" "per , ""PWM,PWM_4"""
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)
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menuitem "LIFEC" "per , ""LIFEC"""
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popup "CRC"
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(
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menuitem "CRC_0" "per , ""CRC,CRC_0"""
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menuitem "CRC_1" "per , ""CRC,CRC_1"""
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menuitem "CRC_2" "per , ""CRC,CRC_2"""
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menuitem "CRC_3" "per , ""CRC,CRC_3"""
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menuitem "CRC_4" "per , ""CRC,CRC_4"""
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)
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popup "KCRC"
|
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(
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menuitem "KCRC_0" "per , ""KCRC,KCRC_0"""
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menuitem "KCRC_1" "per , ""KCRC,KCRC_1"""
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menuitem "KCRC_2" "per , ""KCRC,KCRC_2"""
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menuitem "KCRC_3" "per , ""KCRC,KCRC_3"""
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)
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popup "WCRC"
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(
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menuitem "WCRC_0" "per , ""WCRC,WCRC_0"""
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menuitem "WCRC_1" "per , ""WCRC,WCRC_1"""
|
|
menuitem "WCRC_2" "per , ""WCRC,WCRC_2"""
|
|
menuitem "WCRC_3" "per , ""WCRC,WCRC_3"""
|
|
)
|
|
popup "RFSO"
|
|
(
|
|
menuitem "RFSO_0" "per , ""RFSO,RFSO_0"""
|
|
menuitem "RFSO_1" "per , ""RFSO,RFSO_1"""
|
|
menuitem "RFSO_2" "per , ""RFSO,RFSO_2"""
|
|
menuitem "RFSO_3" "per , ""RFSO,RFSO_3"""
|
|
menuitem "RFSO_4" "per , ""RFSO,RFSO_4"""
|
|
menuitem "RFSO_5" "per , ""RFSO,RFSO_5"""
|
|
menuitem "RFSO_6" "per , ""RFSO,RFSO_6"""
|
|
menuitem "RFSO_7" "per , ""RFSO,RFSO_7"""
|
|
menuitem "RFSO_8" "per , ""RFSO,RFSO_8"""
|
|
menuitem "RFSO_9" "per , ""RFSO,RFSO_9"""
|
|
menuitem "RFSO_10" "per , ""RFSO,RFSO_10"""
|
|
)
|
|
menuitem "RWDT" "per , ""RWDT"""
|
|
popup "WWDT"
|
|
(
|
|
menuitem "WWDT_0" "per , ""WWDT,WWDT_0"""
|
|
menuitem "WWDT_1" "per , ""WWDT,WWDT_1"""
|
|
menuitem "WWDT_2" "per , ""WWDT,WWDT_2"""
|
|
menuitem "WWDT_3" "per , ""WWDT,WWDT_3"""
|
|
menuitem "WWDT_4" "per , ""WWDT,WWDT_4"""
|
|
menuitem "WWDT_5" "per , ""WWDT,WWDT_5"""
|
|
menuitem "WWDT_6" "per , ""WWDT,WWDT_6"""
|
|
menuitem "WWDT_7" "per , ""WWDT,WWDT_7"""
|
|
menuitem "WWDT_8" "per , ""WWDT,WWDT_8"""
|
|
menuitem "WWDT_9" "per , ""WWDT,WWDT_9"""
|
|
)
|
|
menuitem "SWDT" "per , ""SWDT"""
|
|
menuitem "TPU" "per , ""TPU"""
|
|
popup "CMT"
|
|
(
|
|
menuitem "CMT_0" "per , ""CMT,CMT_0"""
|
|
menuitem "CMT_1" "per , ""CMT,CMT_1"""
|
|
menuitem "CMT_2" "per , ""CMT,CMT_2"""
|
|
menuitem "CMT_3" "per , ""CMT,CMT_3"""
|
|
)
|
|
popup "TMU"
|
|
(
|
|
menuitem "TMU_0" "per , ""TMU,TMU_0"""
|
|
menuitem "TMU_1" "per , ""TMU,TMU_1"""
|
|
menuitem "TMU_2" "per , ""TMU,TMU_2"""
|
|
menuitem "TMU_3" "per , ""TMU,TMU_3"""
|
|
menuitem "TMU_4" "per , ""TMU,TMU_4"""
|
|
menuitem "TMU_5" "per , ""TMU,TMU_5"""
|
|
menuitem "TMU_6" "per , ""TMU,TMU_6"""
|
|
menuitem "TMU_7" "per , ""TMU,TMU_7"""
|
|
menuitem "TMU_8" "per , ""TMU,TMU_8"""
|
|
menuitem "TMU_9" "per , ""TMU,TMU_9"""
|
|
menuitem "TMU_10" "per , ""TMU,TMU_10"""
|
|
menuitem "TMU_11" "per , ""TMU,TMU_11"""
|
|
menuitem "TMU_12" "per , ""TMU,TMU_12"""
|
|
menuitem "TMU_13" "per , ""TMU,TMU_13"""
|
|
menuitem "TMU_14" "per , ""TMU,TMU_14"""
|
|
)
|
|
menuitem "AppA" "per , ""AppA"""
|
|
menuitem "IPC_DataLink" "per , ""IPC_DataLink"""
|
|
menuitem "IPC_HSSL" "per , ""IPC_HSSL"""
|
|
popup "Domain"
|
|
(
|
|
menuitem "Domain_0" "per , ""Domain,Domain_0"""
|
|
menuitem "Domain_1" "per , ""Domain,Domain_1"""
|
|
menuitem "Domain_2" "per , ""Domain,Domain_2"""
|
|
menuitem "Domain_3" "per , ""Domain,Domain_3"""
|
|
)
|
|
popup "DBSC"
|
|
(
|
|
menuitem "DBSC_0" "per , ""DBSC,DBSC_0"""
|
|
menuitem "DBSC_1" "per , ""DBSC,DBSC_1"""
|
|
)
|
|
)
|
|
)
|