345 lines
13 KiB
Plaintext
345 lines
13 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: RA4E1 Specific Menu
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; @Props: Released
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; @Author: PIW, NEJ
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; @Changelog: 2022-05-16 PIW
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; 2023-09-13 NEJ
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; @Manufacturer: RENESAS - Renesas Technology, Corp.
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; @Core: Cortex-M33F
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; @Chip: R7FA4E10B2CFM, R7FA4E10B2CNE, R7FA4E10D2CFM, R7FA4E10D2CNE
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; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: menra4e1.men 16620 2023-09-14 10:36:24Z apopow $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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popup "[:chip]Core Registers (Cortex-M33F)"
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(
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menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M33F),System Control"""
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menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M33F),Memory Protection Unit (MPU)"""
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menuitem "[:chip]SAU;Security Attribution Unit" "per , ""Core Registers (Cortex-M33F),Security Attribution Unit (SAU)"""
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menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M33F),Nested Vectored Interrupt Controller (NVIC)"""
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menuitem "[:chip]FPU;Floating-point Unit" "per , ""Core Registers (Cortex-M33F),Floating-point Unit (FPU)"""
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popup "[:chip]Debug"
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(
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menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M33F),Debug,Core Debug"""
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menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M33F),Debug,Flash Patch and Breakpoint Unit (FPB)"""
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menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M33F),Debug,Data Watchpoint and Trace Unit (DWT)"""
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)
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)
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separator
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menuitem "ADC12;12-bit A/D Converter" "per , ""ADC12 (12-bit A/D Converter)"""
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popup "AGT;Low Power Asynchronous General Purpose Timer"
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(
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menuitem "AGT0" "per , ""AGT (Low Power Asynchronous General Purpose Timer),AGT0"""
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menuitem "AGT1" "per , ""AGT (Low Power Asynchronous General Purpose Timer),AGT1"""
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menuitem "AGT2" "per , ""AGT (Low Power Asynchronous General Purpose Timer),AGT2"""
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menuitem "AGT3" "per , ""AGT (Low Power Asynchronous General Purpose Timer),AGT3"""
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menuitem "AGT5" "per , ""AGT (Low Power Asynchronous General Purpose Timer),AGT5"""
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)
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menuitem "BUS;Bus Control" "per , ""BUS (Bus Control)"""
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menuitem "CAC;Clock Frequency Accuracy Measurement Circuit" "per , ""CAC (Clock Frequency Accuracy Measurement Circuit)"""
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menuitem "CAN0;Controller Area Network" "per , ""CAN0 (Controller Area Network)"""
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menuitem "CPSCU;CPU System Security Control Unit" "per , ""CPSCU (CPU System Security Control Unit)"""
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menuitem "CRC;Cyclic Redundancy Check Calculator" "per , ""CRC (Cyclic Redundancy Check Calculator)"""
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menuitem "DAC12;12-bit D/A Converter" "per , ""DAC12 (12-bit D/A Converter)"""
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menuitem "DBG;Debug Function" "per , ""DBG (Debug Function)"""
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menuitem "DMA;DMAC Module Activation" "per , ""DMA (DMAC Module Activation)"""
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popup "DMAC;Direct Memory Access Controller"
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(
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menuitem "DMAC0" "per , ""DMAC (Direct Memory Access Controller),DMAC0"""
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menuitem "DMAC1" "per , ""DMAC (Direct Memory Access Controller),DMAC1"""
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menuitem "DMAC2" "per , ""DMAC (Direct Memory Access Controller),DMAC2"""
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menuitem "DMAC3" "per , ""DMAC (Direct Memory Access Controller),DMAC3"""
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menuitem "DMAC4" "per , ""DMAC (Direct Memory Access Controller),DMAC4"""
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menuitem "DMAC5" "per , ""DMAC (Direct Memory Access Controller),DMAC5"""
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menuitem "DMAC6" "per , ""DMAC (Direct Memory Access Controller),DMAC6"""
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menuitem "DMAC7" "per , ""DMAC (Direct Memory Access Controller),DMAC7"""
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)
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menuitem "DOC;Data Operation Circuit" "per , ""DOC (Data Operation Circuit)"""
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menuitem "DTC;Data Transfer Controller" "per , ""DTC (Data Transfer Controller)"""
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menuitem "ELC;Event Link Controller" "per , ""ELC (Event Link Controller)"""
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menuitem "FACI;Flash/CPU Interface" "per , ""FACI (Flash/CPU Interface)"""
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menuitem "FCACHE;SYSTEM/FLASH" "per , ""FCACHE (SYSTEM/FLASH)"""
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menuitem "FLAD;Data Flash" "per , ""FLAD (Data Flash)"""
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popup "GPT;General Purpose Timer"
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(
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menuitem "GPT164" "per , ""GPT (General Purpose Timer),GPT164"""
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menuitem "GPT165" "per , ""GPT (General Purpose Timer),GPT165"""
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menuitem "GPT321" "per , ""GPT (General Purpose Timer),GPT321"""
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menuitem "GPT322" "per , ""GPT (General Purpose Timer),GPT322"""
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)
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menuitem "ICU;Interrupt Controller" "per , ""ICU (Interrupt Controller)"""
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menuitem "IIC0;Inter-Integrated Circuit 0" "per , ""IIC0 (Inter-Integrated Circuit 0)"""
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menuitem "IIC0WU;Inter-Integrated Circuit 0 Wake-up Unit" "per , ""IIC0WU (Inter-Integrated Circuit 0 Wake-up Unit)"""
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menuitem "IWDT;Independent Watchdog Timer" "per , ""IWDT (Independent Watchdog Timer)"""
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menuitem "MSTP;Module Stop Control" "per , ""MSTP (Module Stop Control)"""
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menuitem "PFS;Control Register" "per , ""PFS (Control Register)"""
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menuitem "POEG;Port Output Enable Module for GPT" "per , ""POEG (Port Output Enable Module for GPT)"""
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popup "PORT;Pmn Pin Function Control Registers"
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(
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menuitem "PORT0" "per , ""PORT (Pmn Pin Function Control Registers),PORT0"""
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menuitem "PORT1" "per , ""PORT (Pmn Pin Function Control Registers),PORT1"""
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menuitem "PORT2" "per , ""PORT (Pmn Pin Function Control Registers),PORT2"""
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menuitem "PORT3" "per , ""PORT (Pmn Pin Function Control Registers),PORT3"""
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menuitem "PORT4" "per , ""PORT (Pmn Pin Function Control Registers),PORT4"""
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menuitem "PORT5" "per , ""PORT (Pmn Pin Function Control Registers),PORT5"""
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)
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menuitem "PSCU;Peripheral Security Control Unit" "per , ""PSCU (Peripheral Security Control Unit)"""
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menuitem "QSPI;Quad Serial Peripheral Interface" "per , ""QSPI (Quad Serial Peripheral Interface)"""
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menuitem "RMPU;Renesas Memory Protection Unit" "per , ""RMPU (Renesas Memory Protection Unit)"""
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menuitem "RTC;Real-Time Clock" "per , ""RTC (Real-Time Clock)"""
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popup "SCI;Serial Communication Interface"
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(
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menuitem "SCI0" "per , ""SCI (Serial Communication Interface),SCI0"""
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menuitem "SCI3" "per , ""SCI (Serial Communication Interface),SCI3"""
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menuitem "SCI4" "per , ""SCI (Serial Communication Interface),SCI4"""
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menuitem "SCI9" "per , ""SCI (Serial Communication Interface),SCI9"""
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)
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menuitem "SPI0;Serial Peripheral Interface" "per , ""SPI0 (Serial Peripheral Interface)"""
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menuitem "SRAM;SRAM Control" "per , ""SRAM (SRAM Control)"""
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menuitem "SYSC;System Control" "per , ""SYSC (System Control)"""
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menuitem "TZF;TrustZone Filter" "per , ""TZF (TrustZone Filter)"""
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menuitem "USBFS;USB 2.0 Full-Speed Module" "per , ""USBFS (USB 2.0 Full-Speed Module)"""
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menuitem "WDT;Watchdog Timer" "per , ""WDT (Watchdog Timer)"""
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)
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)
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