316 lines
8.8 KiB
Plaintext
316 lines
8.8 KiB
Plaintext
; --------------------------------------------------------------------------------
|
|
; @Title: PSoC 4000S Specific Menu
|
|
; @Props: Released
|
|
; @Author: KWI, JON, DAB
|
|
; @Changelog: 2019-01-23 KWI
|
|
; 2022-01-20 DAB
|
|
; @Manufacturer: CYPRESS - Cypress Semiconductor Corporation
|
|
; @Core: Cortex-M0P
|
|
; @Chip: CY8C4024FNI-S402, CY8C4024LQI-S401, CY8C4024LQI-S402, CY8C4024AXI-S402,
|
|
; CY8C4024LQI-S403, CY8C4024AZI-S403, CY8C4024FNI-S412, CY8C4024LQI-S411,
|
|
; CY8C4024LQI-S412, CY8C4024AXI-S412, CY8C4024LQI-S413, CY8C4024AZI-S413,
|
|
; CY8C4025FNI-S402, CY8C4025LQI-S401, CY8C4025LQI-S402, CY8C4025AXI-S402,
|
|
; CY8C4025AZI-S403, CY8C4025FNI-S412, CY8C4025LQI-S411, CY8C4025LQI-S412,
|
|
; CY8C4025AXI-S412, CY8C4025AZI-S413, CY8C4045FNI-S412, CY8C4045LQI-S411,
|
|
; CY8C4045LQI-S412, CY8C4045AXI-S412, CY8C4045AZI-S413
|
|
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
|
|
; --------------------------------------------------------------------------------
|
|
; $Id: menpsoc4000s.men 16339 2023-07-03 13:30:14Z pegold $
|
|
|
|
add
|
|
menu
|
|
(
|
|
IF SOFTWARE.BUILD.BASE()>=69655.
|
|
(
|
|
popup "&CPU"
|
|
(
|
|
separator
|
|
IF CPU.FEATURE(MMU)
|
|
(
|
|
popup "[:mmu]MMU"
|
|
(
|
|
menuitem "[:mmureg]MMU Control" "MMU.view"
|
|
separator
|
|
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
|
|
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
|
|
separator
|
|
IF CPU.FEATURE(ITLBDUMP)
|
|
(
|
|
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
|
|
)
|
|
IF CPU.FEATURE(DTLBDUMP)
|
|
(
|
|
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
|
|
)
|
|
IF CPU.FEATURE(TLB0DUMP)
|
|
(
|
|
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
|
|
)
|
|
IF CPU.FEATURE(TLB1DUMP)
|
|
(
|
|
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
|
|
)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU")
|
|
(
|
|
popup "[:mmu]SMMU"
|
|
(
|
|
menuitem "[:chip]SMMU1 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU1 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU2")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU2 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU2 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU3")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU3 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU3 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU4")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU4 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU4 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU5")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU5 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU5 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU6")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU6 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU6 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
)
|
|
)
|
|
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
|
|
(
|
|
popup "[:cache]Cache"
|
|
(
|
|
IF CPU.FEATURE(L1ICACHEDUMP)
|
|
(
|
|
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
|
|
menuitem "[:cache]ICACHE List" "CACHE.List IC"
|
|
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
|
|
)
|
|
IF CPU.FEATURE(L1DCACHEDUMP)
|
|
(
|
|
separator
|
|
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
|
|
menuitem "[:cache]DCACHE List" "CACHE.List DC"
|
|
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
|
|
)
|
|
IF CPU.FEATURE(L2CACHEDUMP)
|
|
(
|
|
separator
|
|
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
|
|
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
|
|
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
|
|
)
|
|
)
|
|
)
|
|
)
|
|
popup "&Trace"
|
|
(
|
|
separator
|
|
IF COMPonent.AVAILable("ITM")
|
|
(
|
|
popup "ITM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]ITM settings..." "ITM.state"
|
|
separator
|
|
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("STM")
|
|
(
|
|
popup "STM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]STM settings..." "STM.state"
|
|
separator
|
|
menuitem "[:alist]STMTrace List" "STMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("HTM")
|
|
(
|
|
popup "HTM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]HTM settings..." "HTM.state"
|
|
separator
|
|
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("TPIU")
|
|
(
|
|
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
|
|
)
|
|
IF COMPonent.AVAILable("ETR")
|
|
(
|
|
menuitem "[:oconfig]ETR settings..."
|
|
(
|
|
PRIVATE &pdd
|
|
&pdd=OS.PDD()
|
|
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
|
|
)
|
|
)
|
|
)
|
|
popup "&Misc"
|
|
(
|
|
popup "Tools"
|
|
(
|
|
IF CPUIS64BIT()||CPU.FEATURE("SPR")
|
|
(
|
|
menuitem "ARM System Register Converter"
|
|
(
|
|
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
|
|
)
|
|
)
|
|
IF CPU.FEATURE("C15")
|
|
(
|
|
menuitem "ARM Coprocessor Converter"
|
|
(
|
|
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
|
|
)
|
|
)
|
|
)
|
|
)
|
|
popup "&Perf"
|
|
(
|
|
IF CPU.FEATURE(BMC)
|
|
(
|
|
before "Reset"
|
|
menuitem "[:bmc]Benchmark Counters" "BMC.state"
|
|
before "Reset"
|
|
separator
|
|
)
|
|
)
|
|
)
|
|
popup "Peripherals"
|
|
(
|
|
popup "[:chip]Core Registers (Cortex-M0+)"
|
|
(
|
|
menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M0+),System Control"""
|
|
menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M0+),Memory Protection Unit (MPU)"""
|
|
menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M0+),Nested Vectored Interrupt Controller (NVIC)"""
|
|
popup "[:chip]Debug"
|
|
(
|
|
menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M0+),Debug,Core Debug"""
|
|
menuitem "[:chip]BPU;Breakpoint Unit" "per , ""Core Registers (Cortex-M0+),Debug,Breakpoint Unit (BPU)"""
|
|
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M0+),Debug,Data Watchpoint and Trace Unit (DWT)"""
|
|
)
|
|
)
|
|
separator
|
|
menuitem "CM0P" "per , ""CM0P (Cortex-M0+ System Bus (ARM PPB Peripherals))"""
|
|
menuitem "CPUSS" "per , ""CPUSS (CPU Subsystem)"""
|
|
menuitem "CSD" "per , ""CSD (Capsense Controller)"""
|
|
menuitem "GPIO" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines)"""
|
|
popup "GPIO_PRT (GPIO port registers)"
|
|
(
|
|
menuitem "GPIO_PRT0" "per , ""GPIO_PRT (GPIO port registers),GPIO_PRT0"""
|
|
menuitem "GPIO_PRT1" "per , ""GPIO_PRT (GPIO port registers),GPIO_PRT1"""
|
|
menuitem "GPIO_PRT2" "per , ""GPIO_PRT (GPIO port registers),GPIO_PRT2"""
|
|
menuitem "GPIO_PRT3" "per , ""GPIO_PRT (GPIO port registers),GPIO_PRT3"""
|
|
menuitem "GPIO_PRT4" "per , ""GPIO_PRT (GPIO port registers),GPIO_PRT4"""
|
|
)
|
|
menuitem "HSIOM" "per , ""HSIOM (High Speed IO Matrix (HSIOM))"""
|
|
menuitem "LCD" "per , ""LCD (LCD Controller Block)"""
|
|
menuitem "LPCOMP" "per , ""LPCOMP (Low-power Comparator)"""
|
|
menuitem "PERI" "per , ""PERI (Peripheral Interconnect)"""
|
|
menuitem "PERI_TR_GROUP" "per , ""PERI_TR_GROUP (Peripheral Interconnect trigger group control registers)"""
|
|
popup "PRGIO_PRT (Programmable IO port registers)"
|
|
(
|
|
menuitem "PRGIO_PRT0" "per , ""PRGIO_PRT (Programmable IO port registers),PRGIO_PRT0"""
|
|
menuitem "PRGIO_PRT1" "per , ""PRGIO_PRT (Programmable IO port registers),PRGIO_PRT1"""
|
|
)
|
|
menuitem "ROMTABLE" "per , ""ROMTABLE (CoreSight ROM-Table with Cypress Vendor/Silicon ID)"""
|
|
popup "SCB (Serial Communications Block (SPI/UART/I2C))"
|
|
(
|
|
menuitem "SCB0" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB0"""
|
|
menuitem "SCB1" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB1"""
|
|
)
|
|
menuitem "SFLASH" "per , ""SFLASH (Supervisory Flash Area (Cypress Trim & Wounding Info))"""
|
|
menuitem "SPCIF" "per , ""SPCIF (Flash Control Interface)"""
|
|
menuitem "SRSSLT" "per , ""SRSSLT (System Resources Lite Subsystem)"""
|
|
menuitem "TCPWM" "per , ""TCPWM (Timer/Counter/PWM)"""
|
|
popup "TCPWM_CNT (Timer/Counter/PWM Counter Module)"
|
|
(
|
|
menuitem "TCPWM_CNT0" "per , ""TCPWM_CNT (Timer/Counter/PWM Counter Module),TCPWM_CNT0"""
|
|
menuitem "TCPWM_CNT1" "per , ""TCPWM_CNT (Timer/Counter/PWM Counter Module),TCPWM_CNT1"""
|
|
menuitem "TCPWM_CNT2" "per , ""TCPWM_CNT (Timer/Counter/PWM Counter Module),TCPWM_CNT2"""
|
|
menuitem "TCPWM_CNT3" "per , ""TCPWM_CNT (Timer/Counter/PWM Counter Module),TCPWM_CNT3"""
|
|
menuitem "TCPWM_CNT4" "per , ""TCPWM_CNT (Timer/Counter/PWM Counter Module),TCPWM_CNT4"""
|
|
)
|
|
menuitem "WCO" "per , ""WCO (32KHz Oscillator)"""
|
|
)
|
|
)
|