330 lines
12 KiB
Plaintext
330 lines
12 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: OMAP4430 Specific Menu
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; @Props: Released
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; @Author: KAM, KRU, LEM, SLA
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; @Changelog:
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; 2011-02-03
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; 2011-04-20
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; 2011-08-31
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; 2011-12-13
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; 2012-04-18
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; @Manufacturer: TI - Texas Instruments
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; @Core: Cortex-A9
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; @Chip: OMAP4430
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; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: menomap4430app.men 16339 2023-07-03 13:30:14Z pegold $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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popup "[:chip]Core Registers (Cortex-A9MPCore)"
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(
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menuitem "[:chip]ID Registers" "per , ""Core Registers (Cortex-A9MPCore),ID Registers"""
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menuitem "[:chip]System Control and Configuration" "per , ""Core Registers (Cortex-A9MPCore),System Control and Configuration"""
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menuitem "[:chip]Memory Management Unit" "per , ""Core Registers (Cortex-A9MPCore),Memory Management Unit"""
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menuitem "[:chip]Cache Control and Configuration" "per , ""Core Registers (Cortex-A9MPCore),Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor" "per , ""Core Registers (Cortex-A9MPCore),System Performance Monitor"""
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menuitem "[:chip]Preload Engine" "per , ""Core Registers (Cortex-A9MPCore),Preload Engine"""
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menuitem "[:chip]NEON" "per , ""Core Registers (Cortex-A9MPCore),NEON"""
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separator
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menuitem "[:chip]Debug Registers" "per , ""Core Registers (Cortex-A9MPCore),Debug Registers"""
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menuitem "[:chip]Breakpoint Registers" "per , ""Core Registers (Cortex-A9MPCore),Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Control Registers" "per , ""Core Registers (Cortex-A9MPCore),Watchpoint Control Registers"""
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separator
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menuitem "[:chip]Snoop Control Unit (SCU)" "per , ""Core Registers (Cortex-A9MPCore),Snoop Control Unit (SCU)"""
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menuitem "[:chip]Timer and Watchdog Blocks" "per , ""Core Registers (Cortex-A9MPCore),Timer and Watchdog Blocks"""
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menuitem "[:chip]Interrupt Controller (PL-390)" "per , ""Core Registers (Cortex-A9MPCore),Interrupt Controller (PL-390)"""
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)
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separator
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menuitem "PRCM" "PER , ""PRCM"""
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menuitem "Dual_Cortex_A9_MPU_Subsystem" "PER , ""Dual_Cortex_A9_MPU_Subsystem"""
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menuitem "IVA_HD" "PER , ""IVA_HD"""
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menuitem "Dual_Cortex_M3_MPU_Subsystem" "PER , ""Dual_Cortex_M3_MPU_Subsystem"""
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menuitem "ISS_Overview" "PER , ""ISS_Overview"""
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menuitem "ISS_Interfaces" "PER , ""ISS_Interfaces"""
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menuitem "ISS_ISP" "PER , ""ISS_ISP"""
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menuitem "ISS_SIMCOP_Overview" "PER , ""ISS_SIMCOP_Overview"""
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menuitem "ISS_SIMCOP_Hardware_Sequencer_and_Buffers" "PER , ""ISS_SIMCOP_Hardware_Sequencer_and_Buffers"""
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menuitem "ISS_SIMCOP_DMA_Module" "PER , ""ISS_SIMCOP_DMA_Module"""
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menuitem "ISS_SIMCOP_Discrete_Cosine_Transform_Module" "PER , ""ISS_SIMCOP_Discrete_Cosine_Transform_Module"""
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menuitem "ISS_SIMCOP_Variable_Length_Coder_Decoder_for_JPEG_Module" "PER , ""ISS_SIMCOP_Variable_Length_Coder_Decoder_for_JPEG_Module"""
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menuitem "ISS_SIMCOP_Rotation_Accelerator_Module" "PER , ""ISS_SIMCOP_Rotation_Accelerator_Module"""
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menuitem "Face_Detect" "PER , ""Face_Detect"""
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menuitem "Display_Subsystem_Overview" "PER , ""Display_Subsystem_Overview"""
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menuitem "Display_Controller" "PER , ""Display_Controller"""
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menuitem "MIPI_Display_Serial_Interface" "PER , ""MIPI_Display_Serial_Interface"""
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menuitem "Remote_Frame_Buffer_Interface" "PER , ""Remote_Frame_Buffer_Interface"""
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menuitem "Video_Encoder" "PER , ""Video_Encoder"""
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menuitem "SGX_Overview" "PER , ""SGX_Overview"""
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menuitem "L3_Interconnect" "PER , ""L3_Interconnect"""
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menuitem "L4_Interconnects" "PER , ""L4_Interconnects"""
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menuitem "C2C" "PER , ""C2C"""
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menuitem "Dynamic_Memory_Manager" "PER , ""Dynamic_Memory_Manager"""
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menuitem "EMIF_Controller" "PER , ""EMIF_Controller"""
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menuitem "General_Purpose_Memory_Controller" "PER , ""General_Purpose_Memory_Controller"""
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menuitem "Error_Location_Module" "PER , ""Error_Location_Module"""
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menuitem "sDMA_Module" "PER , ""sDMA_Module"""
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menuitem "Control_Module" "PER , ""Control_Module"""
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menuitem "Mailbox" "PER , ""Mailbox"""
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menuitem "MMU" "PER , ""MMU"""
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menuitem "Spinlock" "PER , ""Spinlock"""
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menuitem "General_Purpose_Timers" "PER , ""General_Purpose_Timers"""
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menuitem "Watchdog_Timers" "PER , ""Watchdog_Timers"""
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menuitem "_32_kHz_Synchronized_Timer" "PER , ""_32_kHz_Synchronized_Timer"""
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menuitem "High_Speed_Multiport_USB_Host_Subsystem" "PER , ""High_Speed_Multiport_USB_Host_Subsystem"""
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menuitem "High_Speed_USB_OTG_Controller" "PER , ""High_Speed_USB_OTG_Controller"""
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menuitem "Full_Speed_USB_Host_Controller" "PER , ""Full_Speed_USB_Host_Controller"""
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menuitem "Multimaster_High_Speed_I2C_Controller" "PER , ""Multimaster_High_Speed_I2C_Controller"""
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menuitem "HDQ_1_Wire" "PER , ""HDQ_1_Wire"""
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menuitem "UART_IrDA_CIR" "PER , ""UART_IrDA_CIR"""
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menuitem "Multichannel_Serial_Port_Interface" "PER , ""Multichannel_Serial_Port_Interface"""
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menuitem "Multichannel_Buffered_Serial_Port_McBSP" "PER , ""Multichannel_Buffered_Serial_Port_McBSP"""
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menuitem "Multichannel_PDM_Controller" "PER , ""Multichannel_PDM_Controller"""
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menuitem "Digital_Microphone_Module" "PER , ""Digital_Microphone_Module"""
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menuitem "Multichannel_Audio_Serial_Port" "PER , ""Multichannel_Audio_Serial_Port"""
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menuitem "Serial_Low_Power_Inter_Chip_Media_Bus_Controller" "PER , ""Serial_Low_Power_Inter_Chip_Media_Bus_Controller"""
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menuitem "MMC_SD_SDIO" "PER , ""MMC_SD_SDIO"""
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menuitem "General_Purpose_Interface" "PER , ""General_Purpose_Interface"""
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menuitem "Keyboard_Controller" "PER , ""Keyboard_Controller"""
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menuitem "HSI" "PER , ""HSI"""
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)
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)
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