361 lines
10 KiB
Plaintext
361 lines
10 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: NS9210/9215/9360/9750/9775 Specific Menu
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; @Props: Released
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; @Author: DAN
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; @Changelog: 2010-04-07 DAN
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; @Manufacturer: DIGI - Digi International Inc.
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; @Core: ARM926EJ-S
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; @Chip:
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; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: menns9xxx.men 16339 2023-07-03 13:30:14Z pegold $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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popup "[:chip]Core"
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(
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menuitem "[:chip]ID Registers" "per , ""ARM Core Registers,ID Registers"""
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menuitem "[:chip]MMU Control and Configuration" "per , ""ARM Core Registers,MMU Control and Configuration"""
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menuitem "[:chip]Cache Control and Configuration" "per , ""ARM Core Registers,Cache Control and Configuration"""
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menuitem "[:chip]TCM Control and Configuration" "per , ""ARM Core Registers,TCM Control and Configuration"""
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menuitem "[:chip]Test and Debug" "per , ""ARM Core Registers,Test and Debug"""
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menuitem "[:chip]ICEbreaker" "per , ""ARM Core Registers,ICEbreaker"""
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)
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separator
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if (cpu()=="NS9210"||cpu()=="NS9215")
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(
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menuitem "GPIO" "per , ""GPIO (General Purpose I/O Ports)"""
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)
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menuitem "System Control Module" "per , ""System Control Module"""
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menuitem "Memory Control" "per , ""Memory Control"""
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menuitem "Ethernet" "per , ""Ethernet"""
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if (cpu()=="NS9210"||cpu()=="NS9215")
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(
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menuitem "External DMA" "per , ""External DMA (External Direct Memory Access)"""
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)
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if (cpu()=="NS9360")
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(
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menuitem "BBus Bridge" "per , ""BBus Bridge"""
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popup "BBus DMA Controller"
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(
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menuitem "DMA1" "per , ""BBus DMA Controller,DMA1"""
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menuitem "DMA2" "per , ""BBus DMA Controller,DMA2"""
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)
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menuitem "BBus Utility" "per , ""BBus Utility"""
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)
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if (cpu()=="NS9750")
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(
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menuitem "PCI-to-AHB Bridge" "per , ""PCI-to-AHB Bridge"""
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menuitem "BBus Bridge" "per , ""BBus Bridge"""
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menuitem "BBus Utility" "per , ""BBus Utility"""
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popup "BBus DMA Controller"
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(
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menuitem "DMA1" "per , ""BBus DMA Controller,DMA1"""
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menuitem "DMA2" "per , ""BBus DMA Controller,DMA2"""
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)
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)
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if (cpu()=="NS9775")
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(
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menuitem "PCI-to-AHB Bridge" "per , ""PCI-to-AHB Bridge"""
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menuitem "BBus Bridge" "per , ""BBus Bridge"""
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popup "BBus DMA Controller"
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(
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menuitem "DMA1" "per , ""BBus DMA Controller,DMA1"""
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menuitem "DMA2" "per , ""BBus DMA Controller,DMA2"""
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)
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menuitem "BBus Utility" "per , ""BBus Utility"""
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)
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if (cpu()=="NS9360")
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(
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menuitem "RTC" "per , ""RTC (Real Time Clock Module)"""
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menuitem "I2C Master/Slave Interface" "per , ""I2C Master/Slave Interface"""
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menuitem "LCD Controller" "per , ""LCD Controller"""
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popup "Serial Control Module"
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(
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menuitem "Serial Channel B" "per , ""Serial Control Module,Serial Channel B"""
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menuitem "Serial Channel A" "per , ""Serial Control Module,Serial Channel A"""
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menuitem "Serial Channel C" "per , ""Serial Control Module,Serial Channel C"""
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menuitem "Serial Channel D" "per , ""Serial Control Module,Serial Channel D"""
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)
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menuitem "IEEE 1284 Peripheral Controller" "per , ""IEEE 1284 Peripheral Controller"""
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menuitem "USB Host Module" "per , ""USB Host Module"""
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menuitem "USB Device Module" "per , ""USB Device Module"""
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)
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if (cpu()=="NS9750"||cpu()=="NS9775")
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(
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menuitem "I2C Master/Slave Interface" "per , ""I2C Master/Slave Interface"""
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menuitem "LCD Controller" "per , ""LCD Controller"""
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popup "Serial Control Module"
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(
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menuitem "Serial Channel B" "per , ""Serial Control Module,Serial Channel B"""
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menuitem "Serial Channel A" "per , ""Serial Control Module,Serial Channel A"""
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menuitem "Serial Channel C" "per , ""Serial Control Module,Serial Channel C"""
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menuitem "Serial Channel D" "per , ""Serial Control Module,Serial Channel D"""
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)
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menuitem "IEEE 1284 Peripheral Controller" "per , ""IEEE 1284 Peripheral Controller"""
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menuitem "USB Controller Module" "per , ""USB Controller Module"""
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)
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if (cpu()=="NS9210"||cpu()=="NS9215")
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(
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popup "FIM (Flexible Interface Module)"
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(
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menuitem "FIM 0" "per , ""FIM (Flexible Interface Module),FIM 0"""
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menuitem "FIM 1" "per , ""FIM (Flexible Interface Module),FIM 1"""
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)
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popup "UART (Universal Asynchronous Receiver and Transmitter)"
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(
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menuitem "UART A" "per , ""UART (Universal Asynchronous Receiver and Transmitter),UART A"""
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menuitem "UART B" "per , ""UART (Universal Asynchronous Receiver and Transmitter),UART B"""
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menuitem "UART C" "per , ""UART (Universal Asynchronous Receiver and Transmitter),UART C"""
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menuitem "UART D" "per , ""UART (Universal Asynchronous Receiver and Transmitter),UART D"""
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)
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menuitem "HDLC (High Level Data Link Controller)" "per , ""HDLC (High Level Data Link Controller)"""
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menuitem "SPI (Serial Peripheral Interface)" "per , ""SPI (Serial Peripheral Interface)"""
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menuitem "I2C Master/Slave Interface" "per , ""I2C Master/Slave Interface"""
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)
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if (cpu()=="NS9215")
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(
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menuitem "RTC (Real Time Clock Module)" "per , ""RTC (Real Time Clock Module)"""
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menuitem "ADC (Analog to Digital Converter)" "per , ""ADC (Analog to Digital Converter)"""
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)
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)
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)
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