369 lines
13 KiB
Plaintext
369 lines
13 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: MWCT101x Specific Menu
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; @Props: Released
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; @Author: RAB, PAK, DLI
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; @Changelog: 2019-07-12 RAB
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; @Manufacturer: NXP - NXP Semiconductors
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; @Core: Cortex-M4
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; @Chip: MWCT1014S, MWCT1015S, MWCT1016S
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; @Copyright: (C) 1989-2019 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: menmwct101x.men 16339 2023-07-03 13:30:14Z pegold $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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if (CORENAME()=="CORTEXM4F")
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(
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popup "[:chip]Core Registers (Cortex-M4F)"
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(
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menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M4F),System Control"""
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menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M4F),Memory Protection Unit"""
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menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M4F),Nested Vectored Interrupt Controller"""
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menuitem "[:chip]FPU;Floating-point Unit" "per , ""Core Registers (Cortex-M4F),Floating-point Unit"""
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popup "[:chip]Debug"
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(
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menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M4F),Debug,Core Debug"""
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menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M4F),Debug,Flash Patch and Breakpoint Unit (FPB)"""
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menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M4F),Debug,Data Watchpoint and Trace Unit (DWT)"""
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)
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)
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)
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menuitem "MCM;Miscellaneous Control Module" "per , ""MCM (Miscellaneous Control Module)"""
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menuitem "SIM;System Integration Module" "per , ""SIM (System Integration Module)"""
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popup "PORT;Port Control and Interrupts"
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(
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menuitem "PORT A" "per , ""PORT (Port Control and Interrupts),PORT A"""
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menuitem "PORT B" "per , ""PORT (Port Control and Interrupts),PORT B"""
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menuitem "PORT C" "per , ""PORT (Port Control and Interrupts),PORT C"""
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menuitem "PORT D" "per , ""PORT (Port Control and Interrupts),PORT D"""
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menuitem "PORT E" "per , ""PORT (Port Control and Interrupts),PORT E"""
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)
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popup "GPIO;General-Purpose Input/Output"
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(
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menuitem "Port A" "per , ""GPIO (General-Purpose Input/Output),Port A"""
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menuitem "Port B" "per , ""GPIO (General-Purpose Input/Output),Port B"""
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menuitem "Port C" "per , ""GPIO (General-Purpose Input/Output),Port C"""
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menuitem "Port D" "per , ""GPIO (General-Purpose Input/Output),Port D"""
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menuitem "Port E" "per , ""GPIO (General-Purpose Input/Output),Port E"""
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)
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menuitem "MPU;System Integration Module" "per , ""MPU (Memory Protection Unit)"""
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menuitem "AIPS-LITE;Peripheral Bridge" "per , ""AIPS-LITE (Peripheral Bridge)"""
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menuitem "DMAMUX;Direct Memory Access Multiplexer" "per , ""DMAMUX (Direct Memory Access Multiplexer)"""
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menuitem "EDMA;Enhanced Direct Memory Access" "per , ""EDMA (Enhanced Direct Memory Access)"""
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menuitem "TRGMUX;Trigger MUX Control" "per , ""TRGMUX (Trigger MUX Control)"""
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menuitem "EWM;External Watchdog Monitor" "per , ""EWM (External Watchdog Monitor)"""
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menuitem "EIM;Error Injection Module" "per , ""EIM (Error Injection Module)"""
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menuitem "ERM;Error Reporting Module" "per , ""ERM (Error Reporting Module)"""
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menuitem "WDOG;Watchdog Timer" "per , ""WDOG (Watchdog Timer)"""
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menuitem "CRC;Cyclic Redundancy Check" "per , ""CRC (Cyclic Redundancy Check)"""
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menuitem "RCM;Reset Control Module" "per , ""RCM (Reset Control Module)"""
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menuitem "SCG;System Clock Generator" "per , ""SCG (System Clock Generator)"""
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menuitem "PCC;Peripheral Clock Controller" "per , ""PCC (Peripheral Clock Controller)"""
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menuitem "LMEM;Local Memory Controller" "per , ""LMEM (Local Memory Controller)"""
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menuitem "MSCM;Miscellaneous System Control Module" "per , ""MSCM (Miscellaneous System Control Module)"""
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menuitem "FTFC;Flash Memory Module" "per , ""FTFC (Flash Memory Module)"""
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if !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")
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(
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menuitem "QUADSPI;Quad Serial Peripheral Interface" "per , ""QUADSPI (Quad Serial Peripheral Interface)"""
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)
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menuitem "SMC;System Mode Controller" "per , ""SMC (System Mode Controller)"""
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menuitem "PMC;Power Management Controller" "per , ""PMC (Power Management Controller)"""
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popup "ADC;Analog-to-Digital Converter"
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(
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menuitem "ADC0" "per , ""ADC (Analog-to-Digital Converter),ADC0"""
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menuitem "ADC1" "per , ""ADC (Analog-to-Digital Converter),ADC1"""
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)
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menuitem "CMP;Comparator" "per , ""CMP (Comparator)"""
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popup "PDB;Programmable Delay Block"
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(
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menuitem "PDB0" "per , ""PDB (Programmable Delay Block),PDB0"""
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menuitem "PDB1" "per , ""PDB (Programmable Delay Block),PDB1"""
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)
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popup "FTM;FlexTimer Module"
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(
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menuitem "FTM0" "per , ""FTM (FlexTimer Module),FTM0"""
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menuitem "FTM1" "per , ""FTM (FlexTimer Module),FTM1"""
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menuitem "FTM2" "per , ""FTM (FlexTimer Module),FTM2"""
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menuitem "FTM3" "per , ""FTM (FlexTimer Module),FTM3"""
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if !cpuis("MWCT1014S")
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(
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menuitem "FTM4" "per , ""FTM (FlexTimer Module),FTM4"""
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menuitem "FTM5" "per , ""FTM (FlexTimer Module),FTM5"""
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)
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if !cpuis("MWCT1014S")&&!cpuis("MWCT1015S")
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(
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menuitem "FTM6" "per , ""FTM (FlexTimer Module),FTM6"""
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menuitem "FTM7" "per , ""FTM (FlexTimer Module),FTM7"""
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)
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)
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menuitem "LPIT;Low Power Interrupt Timer" "per , ""LPIT (Low Power Interrupt Timer)"""
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menuitem "LPTMR;Low Power Timer" "per , ""LPTMR (Low Power Timer)"""
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menuitem "RTC;Real Time Clock" "per , ""RTC (Real Time Clock)"""
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popup "LPSPI;Low Power Serial Peripheral Interface"
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(
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menuitem "LPSPI0" "per , ""LPSPI (Low Power Serial Peripheral Interface),LPSPI0"""
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menuitem "LPSPI1" "per , ""LPSPI (Low Power Serial Peripheral Interface),LPSPI1"""
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menuitem "LPSPI2" "per , ""LPSPI (Low Power Serial Peripheral Interface),LPSPI2"""
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)
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popup "LPI2C;Low Power Inter-Integrated Circuit"
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(
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menuitem "LPI2C0" "per , ""LPI2C (Low Power Inter-Integrated Circuit),LPI2C0"""
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if cpuis("MWCT1016S")
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(
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menuitem "LPI2C1" "per , ""LPI2C (Low Power Inter-Integrated Circuit),LPI2C1"""
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)
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)
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popup "LPUART;Low Power Universal Asynchronous Receiver/Transmitter"
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(
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menuitem "LPUART0" "per , ""LPUART (Low Power Universal Asynchronous Receiver/Transmitter),LPUART0"""
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menuitem "LPUART1" "per , ""LPUART (Low Power Universal Asynchronous Receiver/Transmitter),LPUART1"""
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menuitem "LPUART2" "per , ""LPUART (Low Power Universal Asynchronous Receiver/Transmitter),LPUART2"""
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)
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menuitem "FLEXIO;Flexible I/O)" "per , ""FLEXIO (Flexible I/O)"""
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popup "FCAN;FlexCAN"
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(
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menuitem "FCAN0" "per , ""FCAN (FlexCAN),FCAN0"""
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menuitem "FCAN1" "per , ""FCAN (FlexCAN),FCAN1"""
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menuitem "FCAN2" "per , ""FCAN (FlexCAN),FCAN2"""
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)
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)
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)
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