535 lines
28 KiB
Plaintext
535 lines
28 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: LS20XX Specific Menu
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; @Props: Released
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; @Author: ADP, BCA, JAS, MRD, DAM, RAJ, KOF, PID, DAS, TRJ
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; @Changelog: 2016-04-25 ADP
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; 2018-09-25 BCA
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; 2019-02-13 JAS
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; 2020-04-07 RAJ
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; 2021-05-11 TRJ
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; @Manufacturer: NXP - NXP Semiconductors
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; @Core: Cortex-A57, Cortex-A72
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; @Chip: LS2044A, LS2048A, LS2084A, LS2088A
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; @Copyright: (C) 1989-2021 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: menls20xx.men 16339 2023-07-03 13:30:14Z pegold $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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if (CORENAME()=="CORTEXA72")
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(
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popup "[:chip]Core Registers (Cortex-A72)"
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(
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menuitem "[:chip]ID Registers[AArch64]" "per , ""Core Registers (Cortex-A72),AArch64,ID Registers"""
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menuitem "[:chip]System Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A72),AArch64,System Control and Configuration"""
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menuitem "[:chip]Memory Management Unit[AArch64]" "per , ""Core Registers (Cortex-A72),AArch64,Memory Management Unit"""
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menuitem "[:chip]Virtualization Extensions[AArch64]" "per , ""Core Registers (Cortex-A72),AArch64,Virtualization Extensions"""
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menuitem "[:chip]Cache Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A72),AArch64,Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor[AArch64]" "per , ""Core Registers (Cortex-A72),AArch64,System Performance Monitor"""
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menuitem "[:chip]System Timer Registers[AArch64]" "per , ""Core Registers (Cortex-A72),AArch64,System Timer Registers"""
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menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch64]" "per , ""Core Registers (Cortex-A72),AArch64,Generic Interrupt Controller CPU Interface"""
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separator
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menuitem "[:chip]Debug Registers[AArch64]" "per , ""Core Registers (Cortex-A72),AArch64,Debug Registers"""
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separator
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menuitem "[:chip]Breakpoint Registers[AArch64]" "per , ""Core Registers (Cortex-A72),AArch64,Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Registers[AArch64]" "per , ""Core Registers (Cortex-A72),AArch64,Watchpoint Control Registers"""
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separator
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menuitem "[:chip]ID Registers[AArch32]" "per , ""Core Registers (Cortex-A72),AArch32,ID Registers"""
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menuitem "[:chip]System Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A72),AArch32,System Control and Configuration"""
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menuitem "[:chip]Memory Management Unit[AArch32]" "per , ""Core Registers (Cortex-A72),AArch32,Memory Management Unit"""
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menuitem "[:chip]Virtualization Extensions[AArch32]" "per , ""Core Registers (Cortex-A72),AArch32,Virtualization Extensions"""
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menuitem "[:chip]Cache Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A72),AArch32,Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor[AArch32]" "per , ""Core Registers (Cortex-A72),AArch32,System Performance Monitor"""
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menuitem "[:chip]System Timer Registers[AArch32]" "per , ""Core Registers (Cortex-A72),AArch32,System Timer Registers"""
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menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch32]" "per , ""Core Registers (Cortex-A72),AArch32,Generic Interrupt Controller CPU Interface"""
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separator
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menuitem "[:chip]Debug Registers[AArch32]" "per , ""Core Registers (Cortex-A72),AArch32,Debug Registers"""
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separator
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menuitem "[:chip]Breakpoint Registers[AArch32]" "per , ""Core Registers (Cortex-A72),AArch32,Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Registers[AArch32]" "per , ""Core Registers (Cortex-A72),AArch32,Watchpoint Control Registers"""
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separator
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menuitem "[:chip]Interrupt Controller (GIC-500)" "per , ""Core Registers (Cortex-A72),Interrupt Controller (GIC-500)"""
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)
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)
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else
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(
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popup "[:chip]Core Registers (Cortex-A57)"
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(
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menuitem "[:chip]ID Registers[AArch64]" "per , ""Core Registers (Cortex-A57),AArch64,ID Registers"""
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menuitem "[:chip]System Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A57),AArch64,System Control and Configuration"""
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menuitem "[:chip]Memory Management Unit[AArch64]" "per , ""Core Registers (Cortex-A57),AArch64,Memory Management Unit"""
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menuitem "[:chip]Virtualization Extensions[AArch64]" "per , ""Core Registers (Cortex-A57),AArch64,Virtualization Extensions"""
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menuitem "[:chip]Cache Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A57),AArch64,Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor[AArch64]" "per , ""Core Registers (Cortex-A57),AArch64,System Performance Monitor"""
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menuitem "[:chip]System Timer Registers[AArch64]" "per , ""Core Registers (Cortex-A57),AArch64,System Timer Registers"""
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menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch64]" "per , ""Core Registers (Cortex-A57),AArch64,Generic Interrupt Controller CPU Interface"""
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separator
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menuitem "[:chip]Debug Registers[AArch64]" "per , ""Core Registers (Cortex-A57),AArch64,Debug Registers"""
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separator
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menuitem "[:chip]Breakpoint Registers[AArch64]" "per , ""Core Registers (Cortex-A57),AArch64,Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Control Registers[AArch64]" "per , ""Core Registers (Cortex-A57),AArch64,Watchpoint Control Registers"""
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separator
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menuitem "[:chip]ID Registers[AArch32]" "per , ""Core Registers (Cortex-A57),AArch32,ID Registers"""
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menuitem "[:chip]System Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A57),AArch32,System Control and Configuration"""
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menuitem "[:chip]Memory Management Unit[AArch32]" "per , ""Core Registers (Cortex-A57),AArch32,Memory Management Unit"""
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menuitem "[:chip]Virtualization Extensions[AArch32]" "per , ""Core Registers (Cortex-A57),AArch32,Virtualization Extensions"""
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menuitem "[:chip]Cache Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A57),AArch32,Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor[AArch32]" "per , ""Core Registers (Cortex-A57),AArch32,System Performance Monitor"""
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menuitem "[:chip]System Timer Registers[AArch32]" "per , ""Core Registers (Cortex-A57),AArch32,System Timer Registers"""
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menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch32]" "per , ""Core Registers (Cortex-A57),AArch32,Generic Interrupt Controller CPU Interface"""
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separator
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menuitem "[:chip]Debug Registers[AArch32]" "per , ""Core Registers (Cortex-A57),AArch32,Debug Registers"""
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separator
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menuitem "[:chip]Breakpoint Registers[AArch32]" "per , ""Core Registers (Cortex-A57),AArch32,Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Control Registers[AArch32]" "per , ""Core Registers (Cortex-A57),AArch32,Watchpoint Control Registers"""
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separator
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menuitem "[:chip]Interrupt Controller (GIC-500)" "per , ""Core Registers (Cortex-A57),Interrupt Controller (GIC-500)"""
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)
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)
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separator
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popup "RST/CLK;Reset Clocking and Initialization"
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(
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menuitem "Reset" "per , ""RST/CLK (Reset Clocking and Initialization),Reset"""
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popup "Clock"
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(
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menuitem "CGU Platform" "per , ""RST/CLK (Reset Clocking and Initialization),Clock,CGU Platform"""
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menuitem "CGU1 CGA" "per , ""RST/CLK (Reset Clocking and Initialization),Clock,CGU1 CGA"""
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menuitem "CGU2 CGB" "per , ""RST/CLK (Reset Clocking and Initialization),Clock,CGU2 CGB"""
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menuitem "CGU DDR Unit 1" "per , ""RST/CLK (Reset Clocking and Initialization),Clock,CGU DDR Unit 1"""
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menuitem "CGU DDR Unit 2" "per , ""RST/CLK (Reset Clocking and Initialization),Clock,CGU DDR Unit 2"""
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menuitem "CGU Core Cluster Unit" "per , ""RST/CLK (Reset Clocking and Initialization),Clock,CGU Core Cluster Unit"""
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)
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)
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menuitem "ISC;Interrupt Sampling" "per , ""ISC (Interrupt Sampling)"""
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menuitem "DCFG;Device Configuration" "per , ""DCFG (Device Configuration)"""
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menuitem "SCFG;Supplemental Configuration Unit" "per , ""SCFG (Supplemental Configuration Unit)"""
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popup "DPAA2;Data Path Acceleration Architecture"
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(
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popup "QBMAN;Queue/Buffer Manager"
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(
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menuitem "QMAN_CCSR" "per , ""DPAA2 (Data Path Acceleration Architecture),QBMAN (Queue/Buffer Manager),QMAN_CCSR"""
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; popup "QMAN_SWP"
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; (
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; menuitem "Software Portal $2" "per , ""DPAA2 (Data Path Acceleration Architecture),QBMAN (Queue/Buffer Manager),QMAN_SWP,Software Portal $2"""
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; menuitem "Software Portal $2 Alias" "per , ""DPAA2 (Data Path Acceleration Architecture),QBMAN (Queue/Buffer Manager),QMAN_SWP,Software Portal $2 Alias"""
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; )
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)
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menuitem "MC;Management Complex" "per , ""DPAA2 (Data Path Acceleration Architecture),MC (Management Complex)"""
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popup "WRIOP;Wire Rate IO Processor"
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(
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; popup "Interface Profile Record Registers"
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; (
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; menuitem "Ingress" "per , ""DPAA2 (Data Path Acceleration Architecture),WRIOP (Wire Rate IO Processor),Interface Profile Record Registers,Ingress"""
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; menuitem "Egress" "per , ""DPAA2 (Data Path Acceleration Architecture),WRIOP (Wire Rate IO Processor),Interface Profile Record Registers,Egress"""
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; )
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; menuitem "Interface Profile Special Functions Registers" "per , ""DPAA2 (Data Path Acceleration Architecture),WRIOP (Wire Rate IO Processor),Interface Profile Special Functions Registers"""
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menuitem "Global Registers" "per , ""DPAA2 (Data Path Acceleration Architecture),WRIOP (Wire Rate IO Processor),Global Registers"""
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menuitem "Port Registers" "per , ""DPAA2 (Data Path Acceleration Architecture),WRIOP (Wire Rate IO Processor),Port Registers"""
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popup "CTLU"
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(
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menuitem "Ingress" "per , ""DPAA2 (Data Path Acceleration Architecture),WRIOP (Wire Rate IO Processor),CTLU,Ingress"""
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menuitem "Egress" "per , ""DPAA2 (Data Path Acceleration Architecture),WRIOP (Wire Rate IO Processor),CTLU,Egress"""
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)
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)
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menuitem "1588 TIM IP;1588 Timer IP Module" "per , ""DPAA2 (Data Path Acceleration Architecture),1588 TIM IP (1588 Timer IP Module)"""
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menuitem "PEBM;Packet Express Buffer Memory" "per , ""DPAA2 (Data Path Acceleration Architecture),PEBM (Packet Express Buffer Memory)"""
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; menuitem "CTLU_QOS;CTLU QoS Mapping and Policer" "per , ""DPAA2 (Data Path Acceleration Architecture),CTLU_QOS (CTLU QoS Mapping and Policer)"""
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menuitem "mEMAC;Multirate Ethernet Media Access Controller" "per , ""DPAA2 (Data Path Acceleration Architecture),mEMAC (Multirate Ethernet Media Access Controller)"""
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menuitem "MACSec" "per , ""DPAA2 (Data Path Acceleration Architecture),MACSec"""
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if cpuis("LS2088A")
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(
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popup "AIOP;Advanced IO Processor"
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(
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menuitem "CTLU" "per , ""DPAA2 (Data Path Acceleration Architecture),AIOP (Advanced IO Processor),CTLU"""
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)
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)
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menuitem "SEC;Security and Encryption" "per , ""DPAA2 (Data Path Acceleration Architecture),SEC (Security and Encryption)"""
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menuitem "qDMA;Queue Direct Memory Access Controller" "per , ""DPAA2 (Data Path Acceleration Architecture),qDMA (Queue Direct Memory Access Controller)"""
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menuitem "PME;Pattern Matching Engine" "per , ""DPAA2 (Data Path Acceleration Architecture),PME (Pattern Matching Engine)"""
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menuitem "DCE;Decompression/Compression Engine" "per , ""DPAA2 (Data Path Acceleration Architecture),DCE (Decompression/Compression Engine)"""
|
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popup "PMU;Power Management Unit"
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(
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menuitem "COP_PMU_CCSR" "per , ""DPAA2 (Data Path Acceleration Architecture),PMU (Power Management Unit),COP_PMU_CCSR"""
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; menuitem "COP_PMU_DCSR" "per , ""DPAA2 (Data Path Acceleration Architecture),PMU (Power Management Unit),COP_PMU_DCSR"""
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)
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)
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popup "CCI;Cache Coherent Interconnect"
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(
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menuitem "MN Registers" "per , ""CCI (Cache Coherent Interconnect),MN Registers"""
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popup "XP Registers"
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(
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menuitem "XP ID 0;region 64" "per , ""CCI (Cache Coherent Interconnect),XP Registers,XP ID 0 (region 64)"""
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menuitem "XP ID 1;region 65" "per , ""CCI (Cache Coherent Interconnect),XP Registers,XP ID 1 (region 65)"""
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menuitem "XP ID 2;region 66" "per , ""CCI (Cache Coherent Interconnect),XP Registers,XP ID 2 (region 66)"""
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menuitem "XP ID 3;region 67" "per , ""CCI (Cache Coherent Interconnect),XP Registers,XP ID 3 (region 67)"""
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menuitem "XP ID 4;region 68" "per , ""CCI (Cache Coherent Interconnect),XP Registers,XP ID 4 (region 68)"""
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menuitem "XP ID 5;region 69" "per , ""CCI (Cache Coherent Interconnect),XP Registers,XP ID 5 (region 69)"""
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menuitem "XP ID 6;region 70" "per , ""CCI (Cache Coherent Interconnect),XP Registers,XP ID 6 (region 70)"""
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|
menuitem "XP ID 7;region 71" "per , ""CCI (Cache Coherent Interconnect),XP Registers,XP ID 7 (region 71)"""
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|
menuitem "XP ID 8;region 72" "per , ""CCI (Cache Coherent Interconnect),XP Registers,XP ID 8 (region 72)"""
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menuitem "XP ID 9;region 73" "per , ""CCI (Cache Coherent Interconnect),XP Registers,XP ID 9 (region 73)"""
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menuitem "XP ID 10;region 74" "per , ""CCI (Cache Coherent Interconnect),XP Registers,XP ID 10 (region 74)"""
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)
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popup "HN-F Registers"
|
|
(
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menuitem "Node ID 3;region 32" "per , ""CCI (Cache Coherent Interconnect),HN-F Registers,Node ID 3 (region 32)"""
|
|
menuitem "Node ID 5;region 33" "per , ""CCI (Cache Coherent Interconnect),HN-F Registers,Node ID 5 (region 33)"""
|
|
menuitem "Node ID 7;region 34" "per , ""CCI (Cache Coherent Interconnect),HN-F Registers,Node ID 7 (region 34)"""
|
|
menuitem "Node ID 8;region 35" "per , ""CCI (Cache Coherent Interconnect),HN-F Registers,Node ID 8 (region 35)"""
|
|
menuitem "Node ID 13;region 36" "per , ""CCI (Cache Coherent Interconnect),HN-F Registers,Node ID 13 (region 36)"""
|
|
menuitem "Node ID 15;region 37" "per , ""CCI (Cache Coherent Interconnect),HN-F Registers,Node ID 15 (region 37)"""
|
|
menuitem "Node ID 17;region 38" "per , ""CCI (Cache Coherent Interconnect),HN-F Registers,Node ID 17 (region 38)"""
|
|
menuitem "Node ID 18;region 39" "per , ""CCI (Cache Coherent Interconnect),HN-F Registers,Node ID 18 (region 39)"""
|
|
)
|
|
menuitem "HN-I Registers" "per , ""CCI (Cache Coherent Interconnect),HN-I Registers"""
|
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popup "RN-I Bridge Register"
|
|
(
|
|
menuitem "Node ID 0;region 128" "per , ""CCI (Cache Coherent Interconnect),RN-I Bridge Register,Node ID 0 (region 128)"""
|
|
menuitem "Node ID 2;region 130" "per , ""CCI (Cache Coherent Interconnect),RN-I Bridge Register,Node ID 2 (region 130)"""
|
|
menuitem "Node ID 6;region 134" "per , ""CCI (Cache Coherent Interconnect),RN-I Bridge Register,Node ID 6 (region 134)"""
|
|
menuitem "Node ID 12;region 140" "per , ""CCI (Cache Coherent Interconnect),RN-I Bridge Register,Node ID 12 (region 140)"""
|
|
menuitem "Node ID 16;region 144" "per , ""CCI (Cache Coherent Interconnect),RN-I Bridge Register,Node ID 16 (region 144)"""
|
|
menuitem "Node ID 20;region 148" "per , ""CCI (Cache Coherent Interconnect),RN-I Bridge Register,Node ID 20 (region 148)"""
|
|
)
|
|
popup "SBSX Registers"
|
|
(
|
|
menuitem "Node ID 4;region 16" "per , ""CCI (Cache Coherent Interconnect),SBSX Registers,Node ID 4 (region 16)"""
|
|
menuitem "Node ID 14;region 17" "per , ""CCI (Cache Coherent Interconnect),SBSX Registers,Node ID 14 (region 17)"""
|
|
)
|
|
)
|
|
popup "DDR;DDR Memory Controllers"
|
|
(
|
|
menuitem "DDR1" "per , ""DDR (DDR Memory Controllers),DDR1"""
|
|
menuitem "DDR2" "per , ""DDR (DDR Memory Controllers),DDR2"""
|
|
)
|
|
popup "DUART;Dual Universal Asynchronous Receiver/Transmitter"
|
|
(
|
|
popup "DUART 1"
|
|
(
|
|
menuitem "UART 1" "per , ""DUART (Dual Universal Asynchronous Receiver/Transmitter),DUART 1,UART 1"""
|
|
menuitem "UART 2" "per , ""DUART (Dual Universal Asynchronous Receiver/Transmitter),DUART 1,UART 2"""
|
|
)
|
|
popup "DUART 2"
|
|
(
|
|
menuitem "UART 3" "per , ""DUART (Dual Universal Asynchronous Receiver/Transmitter),DUART 2,UART 3"""
|
|
menuitem "UART 4" "per , ""DUART (Dual Universal Asynchronous Receiver/Transmitter),DUART 2,UART 4"""
|
|
)
|
|
)
|
|
menuitem "eSDHC;Enhanced Secured Digital Host Controller" "per , ""eSDHC (Enhanced Secured Digital Host Controller)"""
|
|
popup "FTM;FlexTimer Module"
|
|
(
|
|
menuitem "FlexTimer 1" "per , ""FTM (FlexTimer Module),FlexTimer 1"""
|
|
menuitem "FlexTimer 2" "per , ""FTM (FlexTimer Module),FlexTimer 2"""
|
|
menuitem "FlexTimer 3" "per , ""FTM (FlexTimer Module),FlexTimer 3"""
|
|
menuitem "FlexTimer 4" "per , ""FTM (FlexTimer Module),FlexTimer 4"""
|
|
)
|
|
popup "GPIO;General Purpose I/O"
|
|
(
|
|
menuitem "GPIO 1" "per , ""GPIO (General Purpose I/O),GPIO 1"""
|
|
menuitem "GPIO 2" "per , ""GPIO (General Purpose I/O),GPIO 2"""
|
|
menuitem "GPIO 3" "per , ""GPIO (General Purpose I/O),GPIO 3"""
|
|
menuitem "GPIO 4" "per , ""GPIO (General Purpose I/O),GPIO 4"""
|
|
)
|
|
menuitem "IFC;Integrated Flash Controller" "per , ""IFC (Integrated Flash Controller)"""
|
|
popup "I2C;Inter-Integrated Circuit"
|
|
(
|
|
menuitem "I2C 1" "per , ""I2C (Inter-Integrated Circuit),I2C 1"""
|
|
menuitem "I2C 2" "per , ""I2C (Inter-Integrated Circuit),I2C 2"""
|
|
menuitem "I2C 3" "per , ""I2C (Inter-Integrated Circuit),I2C 3"""
|
|
menuitem "I2C 4" "per , ""I2C (Inter-Integrated Circuit),I2C 4"""
|
|
)
|
|
popup "PEX;PCI Express Interface Controller"
|
|
(
|
|
menuitem "PEX 1" "per , ""PEX (PCI Express Interface Controller),PEX 1"""
|
|
menuitem "PEX 2" "per , ""PEX (PCI Express Interface Controller),PEX 2"""
|
|
menuitem "PEX 3" "per , ""PEX (PCI Express Interface Controller),PEX 3"""
|
|
menuitem "PEX 4" "per , ""PEX (PCI Express Interface Controller),PEX 4"""
|
|
)
|
|
menuitem "PMU;Power Management Unit" "per , ""PMU (Power Management Unit)"""
|
|
menuitem "QuadSPI;Quad Serial Peripheral Interface" "per , ""QuadSPI (Quad Serial Peripheral Interface)"""
|
|
popup "SATA 3.0;Serial ATA 3.0"
|
|
(
|
|
menuitem "SATA 1" "per , ""SATA 3.0 (Serial ATA 3.0),SATA 1"""
|
|
menuitem "SATA 2" "per , ""SATA 3.0 (Serial ATA 3.0),SATA 2"""
|
|
)
|
|
popup "SerDes;SerDes Module"
|
|
(
|
|
menuitem "Serdes 1" "per , ""SerDes (SerDes Module),Serdes 1"""
|
|
menuitem "Serdes 2" "per , ""SerDes (SerDes Module),Serdes 2"""
|
|
; menuitem "MDIO;Management Data In/Out" "per , ""SerDes (SerDes Module),MDIO (Management Data In/Out)"""
|
|
)
|
|
menuitem "SPI;Serial Peripheral Interface" "per , ""SPI (Serial Peripheral Interface)"""
|
|
popup "TZM;TrustZone Modules"
|
|
(
|
|
popup "TZC-400;TrustZone Address Space Controller"
|
|
(
|
|
menuitem "TZC 1" "per , ""TZM (TrustZone Modules),TZC-400 (TrustZone Address Space Controller),TZC 1"""
|
|
menuitem "TZC 2" "per , ""TZM (TrustZone Modules),TZC-400 (TrustZone Address Space Controller),TZC 2"""
|
|
)
|
|
menuitem "TZPC;TrustZone Protection Controller" "per , ""TZM (TrustZone Modules),TZPC (TrustZone Protection Controller)"""
|
|
)
|
|
menuitem "TMU;Thermal Monitoring Unit" "per , ""TMU (Thermal Monitoring Unit)"""
|
|
popup "USB;Universal Serial Bus Interface 3.0"
|
|
(
|
|
menuitem "USB 1" "per , ""USB (Universal Serial Bus Interface 3.0),USB 1"""
|
|
menuitem "USB 2" "per , ""USB (Universal Serial Bus Interface 3.0),USB 2"""
|
|
menuitem "USB PHY SS 1" "per , ""USB (Universal Serial Bus Interface 3.0),USB PHY SS 1"""
|
|
menuitem "USB PHY SS 2" "per , ""USB (Universal Serial Bus Interface 3.0),USB PHY SS 2"""
|
|
)
|
|
popup "WDOG;Watchdog Timer Unit"
|
|
(
|
|
menuitem "TrustZone WDOG" "per , ""WDOG (Watchdog Timer Unit),TrustZone WDOG"""
|
|
menuitem "WDOG 1" "per , ""WDOG (Watchdog Timer Unit),WDOG 1"""
|
|
menuitem "WDOG 2" "per , ""WDOG (Watchdog Timer Unit),WDOG 2"""
|
|
menuitem "WDOG 3" "per , ""WDOG (Watchdog Timer Unit),WDOG 3"""
|
|
menuitem "WDOG 4" "per , ""WDOG (Watchdog Timer Unit),WDOG 4"""
|
|
if !cpuis("LS2048A*")&&!cpuis("LS2044A*")
|
|
(
|
|
menuitem "WDOG 5" "per , ""WDOG (Watchdog Timer Unit),WDOG 5"""
|
|
menuitem "WDOG 6" "per , ""WDOG (Watchdog Timer Unit),WDOG 6"""
|
|
menuitem "WDOG 7" "per , ""WDOG (Watchdog Timer Unit),WDOG 7"""
|
|
menuitem "WDOG 8" "per , ""WDOG (Watchdog Timer Unit),WDOG 8"""
|
|
)
|
|
)
|
|
menuitem "EPU;Event Processing Unit" "per , ""EPU (Event Processing Unit)"""
|
|
)
|
|
)
|