392 lines
13 KiB
Plaintext
392 lines
13 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: LPC8xx Specific Menu
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; @Props: Released
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; @Author: GAJ, KKW, KOB, BUM, KMW
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; @Changelog: 2017-10-10 KOB
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; 2018-11-06 KMW
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; @Manufacturer: NXP - NXP Semiconductors
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; @Doc: UM10800.pdf (Rev.1 2014-09)
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; UM10601.pdf (Rev.1.6 2014-04)
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; LPC81XM.pdf (Rev.4.4 2015-06)
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; UM11029.pdf (Rev.1.3 2017-08)
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; UM11021.pdf (Rev.1.6 2014-02)
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; UM11074-rev1.1.pdf (Rev.1.1 2017-12)
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; UM11065-rev1.2.pdf (Rev.1.2 2018-03)
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; UM11045-rev1.3.pdf (Rev.1.3 2018-03)
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; @Chip: LPC812M101JD20, LPC812M101JDH16, LPC812M101JTB16, LPC812M101JDH20
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; LPC822M101JDH20, LPC822M101JHI33, LPC824M201JDH20, LPC824M201JHI33
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; LPC811M001JDH16, LPC832M101FDH20, LPC844M201JBD48, LPC844M201JBD64
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; LPC844M201JHI33, LPC834M101FHI33, LPC844M201JHI48, LPC845M301JBD48
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; LPC845M301JBD64, LPC845M301JHI33, LPC845M301JHI48, LPC802M001JDH16
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; LPC802M001JDH20, LPC802M001JHI33, LPC802M011JDH20, LPC804M101JDH20
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; LPC804M101JDH24, LPC804M101JHI33, LPC804M111JDH24, LPC8N04
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; @Core: Cortex-M0P
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; @Copyright: (C) 1989-2018 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: menlpc8xx.men 16339 2023-07-03 13:30:14Z pegold $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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popup "[:chip]Core Registers (Cortex-M0+)"
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(
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menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M0+),System Control"""
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menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M0+),Memory Protection Unit (MPU)"""
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menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M0+),Nested Vectored Interrupt Controller (NVIC)"""
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popup "[:chip]Debug"
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(
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menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M0+),Debug,Core Debug"""
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menuitem "[:chip]BPU;Breakpoint Unit" "per , ""Core Registers (Cortex-M0+),Debug,Breakpoint Unit (BPU)"""
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menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M0+),Debug,Data Watchpoint and Trace Unit (DWT)"""
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)
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)
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separator
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menuitem "SYSCON;System Configuration" "per , ""SYSCON (System Configuration)"""
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if (cpuis("LPC80*"))
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(
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menuitem "PMU;Reduced Power Modes and Power Management" "per , ""PMU (Reduced Power Modes and Power Management)"""
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)
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else
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(
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menuitem "PMU;Power Management Unit" "per , ""PMU (Power Management Unit)"""
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)
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menuitem "IOCON;I/O Configuration" "per , ""IOCON (I/O Configuration)"""
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menuitem "GPIO;General Purpose Input/Output" "per , ""GPIO (General Purpose Input/Output)"""
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if (!cpuis("LPC8N04"))
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(
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menuitem "Pin Interrupts/Pattern Match Engine" "per , ""Pin interrupts/Pattern match engine"""
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)
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if (cpuis("LPC82*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*"))
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(
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menuitem "INPUT MUX/DMA TRIGMUX" "per , ""INPUT MUX/DMA TRIGMUX (Input Multiplexing and DMA Trigger Multiplexing)"""
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menuitem "DMA;DMA controller" "per , ""DMA (DMA controller)"""
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)
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if (!cpuis("LPC8N04"))
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(
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menuitem "SWM;Switch Matrix" "per , ""SWM (Switch Matrix)"""
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)
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if (!cpuis("LPC80*")&&!cpuis("LPC8N04"))
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(
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menuitem "SCT;State Configurable Timer" "per , ""SCT (State Configurable Timer)"""
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)
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if (!cpuis("LPC8N04"))
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(
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menuitem "MRT;Multi-Rate Timer" "per , ""MRT (Multi-Rate Timer)"""
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)
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menuitem "WWDT;Windowed Watchdog Timer" "per , ""WWDT (Windowed Watchdog Timer)"""
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if (cpu()!="LPC832M101FDH20"&&cpu()!="LPC834M101FHI33"&&!cpuis("LPC8N04"))
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(
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menuitem "AC;Analog Comparator" "per , ""AC (Analog Comparator)"""
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)
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if (!cpuis("LPC8N04"))
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(
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menuitem "WKT;Self Wake-up Timer" "per , ""WKT (Self Wake-up Timer)"""
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)
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if (cpuis("LPC82*")||cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")||cpuis("LPC802*")||cpuis("LPC804*"))
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(
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menuitem "ADC;Analog to Digital Converter" "per , ""ADC (Analog to Digital Converter)"""
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)
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if (cpu()=="LPC832M101FDH20"||cpu()=="LPC834M101FHI33"||cpuis("LPC84*")||cpu()=="LPC811M001JDH16")
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(
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menuitem "SysTick;SysTick Timer" "per , ""SysTick (SysTick Timer)"""
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)
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if (!cpuis("LPC8N04"))
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(
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popup "USART;Universal Synchronous/Asynchronous Receiver/Transmitter"
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(
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menuitem "USART_0" "per , ""USART (Universal Synchronous/Asynchronous Receiver/Transmitter),USART_0"""
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if (cpu()!="LPC832M101FDH20"&&cpu()!="LPC834M101FHI33")
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(
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menuitem "USART_1" "per , ""USART (Universal Synchronous/Asynchronous Receiver/Transmitter),USART_1"""
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)
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if (cpu()=="LPC812M101FDH16"||cpu()=="LPC812M101FDH20"||cpu()=="LPC812M101JTB16"||cpu()=="LPC812M101JDH20"||cpu()=="LPC812M101JDH16"||cpu()=="LPC824M201JHI33"||cpu()=="LPC822M101JHI33"||cpu()=="LPC824M201JDH20"||cpu()=="LPC822M101JDH20"||cpuis("LPC84*"))
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(
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menuitem "USART_2" "per , ""USART (Universal Synchronous/Asynchronous Receiver/Transmitter),USART_2"""
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)
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if (cpuis("LPC84*"))
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(
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menuitem "USART_3" "per , ""USART (Universal Synchronous/Asynchronous Receiver/Transmitter),USART_3"""
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menuitem "USART_4" "per , ""USART (Universal Synchronous/Asynchronous Receiver/Transmitter),USART_4"""
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)
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)
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)
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menuitem "I2C;I2C-Bus Interface" "per , ""I2C (I2C-Bus Interface)"""
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if (cpuis("LPC8N04"))
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(
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menuitem "SPI/SSP;Serial Peripheral Interface" "per , ""SPI/SSP (Serial Peripheral Interface)"""
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)
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else
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(
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menuitem "SPI;Serial Peripheral Interface" "per , ""SPI (Serial Peripheral Interface)"""
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)
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if (cpuis("LPC84*")||cpuis("LPC802*")||cpuis("LPC804*")||cpuis("LPC8N04"))
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(
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menuitem "CTIMER;Standard Counter/Timer" "per , ""CTIMER (Standard Counter/Timer)"""
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if (cpu()=="LPC845M301JBD64"||cpu()=="LPC845M301JBD48"||cpu()=="LPC845M301JHI48"||cpuis("LPC804*"))
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(
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menuitem "CT;Capacitive Touch" "per , ""CT (c)"""
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)
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if (!cpuis("LPC802*")&&!cpuis("LPC8N04"))
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(
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menuitem "DAC;Digital-to-Analog Converter" "per , ""DAC (Digital-to-Analog Converter)"""
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)
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)
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if (cpuis("LPC804*"))
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(
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menuitem "PLU;Programmable Logic Unit" "per , ""PLU (Programmable Logic Unit)"""
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)
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if (!cpuis("LPC8N04"))
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(
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menuitem "CRC;Cyclic Redundancy Check" "per , ""CRC (Cyclic Redundancy Check)"""
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)
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if (!cpuis("LPC802*")&&!cpuis("LPC804*"))
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(
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menuitem "Flash Controller" "per , ""Flash Controller"""
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)
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if (cpuis("LPC8N04"))
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(
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menuitem "TS;Temperature sensor" "per , ""TS (Temperature sensor)"""
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menuitem "RFID/NFC Communication Unit" "per , ""RFID/NFC Communication Unit"""
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menuitem "RTC;Real-Time Clock" "per , ""RTC (Real-Time Clock)"""
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menuitem "EEPROM;EEPROM Controller" "per , ""EEPROM (EEPROM Controller)"""
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)
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)
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)
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