343 lines
11 KiB
Plaintext
343 lines
11 KiB
Plaintext
; --------------------------------------------------------------------------------
|
|
; @Title: LPC43xx Specific Menu
|
|
; @Props: Released
|
|
; @Author: BIC, KBR, JKA, PBU, TRJ
|
|
; @Changelog: 2016-06-27
|
|
; @Manufacturer: NXP - NXP Semiconductors
|
|
; @Core: Cortex-M0, Cortex-M4
|
|
; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
|
|
; --------------------------------------------------------------------------------
|
|
; $Id: menlpc43xx.men 16339 2023-07-03 13:30:14Z pegold $
|
|
|
|
add
|
|
menu
|
|
(
|
|
IF SOFTWARE.BUILD.BASE()>=69655.
|
|
(
|
|
popup "&CPU"
|
|
(
|
|
separator
|
|
IF CPU.FEATURE(MMU)
|
|
(
|
|
popup "[:mmu]MMU"
|
|
(
|
|
menuitem "[:mmureg]MMU Control" "MMU.view"
|
|
separator
|
|
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
|
|
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
|
|
separator
|
|
IF CPU.FEATURE(ITLBDUMP)
|
|
(
|
|
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
|
|
)
|
|
IF CPU.FEATURE(DTLBDUMP)
|
|
(
|
|
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
|
|
)
|
|
IF CPU.FEATURE(TLB0DUMP)
|
|
(
|
|
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
|
|
)
|
|
IF CPU.FEATURE(TLB1DUMP)
|
|
(
|
|
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
|
|
)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU")
|
|
(
|
|
popup "[:mmu]SMMU"
|
|
(
|
|
menuitem "[:chip]SMMU1 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU1 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU2")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU2 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU2 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU3")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU3 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU3 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU4")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU4 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU4 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU5")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU5 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU5 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU6")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU6 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU6 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
)
|
|
)
|
|
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
|
|
(
|
|
popup "[:cache]Cache"
|
|
(
|
|
IF CPU.FEATURE(L1ICACHEDUMP)
|
|
(
|
|
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
|
|
menuitem "[:cache]ICACHE List" "CACHE.List IC"
|
|
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
|
|
)
|
|
IF CPU.FEATURE(L1DCACHEDUMP)
|
|
(
|
|
separator
|
|
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
|
|
menuitem "[:cache]DCACHE List" "CACHE.List DC"
|
|
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
|
|
)
|
|
IF CPU.FEATURE(L2CACHEDUMP)
|
|
(
|
|
separator
|
|
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
|
|
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
|
|
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
|
|
)
|
|
)
|
|
)
|
|
)
|
|
popup "&Trace"
|
|
(
|
|
separator
|
|
IF COMPonent.AVAILable("ITM")
|
|
(
|
|
popup "ITM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]ITM settings..." "ITM.state"
|
|
separator
|
|
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("STM")
|
|
(
|
|
popup "STM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]STM settings..." "STM.state"
|
|
separator
|
|
menuitem "[:alist]STMTrace List" "STMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("HTM")
|
|
(
|
|
popup "HTM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]HTM settings..." "HTM.state"
|
|
separator
|
|
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("TPIU")
|
|
(
|
|
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
|
|
)
|
|
IF COMPonent.AVAILable("ETR")
|
|
(
|
|
menuitem "[:oconfig]ETR settings..."
|
|
(
|
|
PRIVATE &pdd
|
|
&pdd=OS.PDD()
|
|
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
|
|
)
|
|
)
|
|
)
|
|
popup "&Misc"
|
|
(
|
|
popup "Tools"
|
|
(
|
|
IF CPUIS64BIT()||CPU.FEATURE("SPR")
|
|
(
|
|
menuitem "ARM System Register Converter"
|
|
(
|
|
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
|
|
)
|
|
)
|
|
IF CPU.FEATURE("C15")
|
|
(
|
|
menuitem "ARM Coprocessor Converter"
|
|
(
|
|
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
|
|
)
|
|
)
|
|
)
|
|
)
|
|
popup "&Perf"
|
|
(
|
|
IF CPU.FEATURE(BMC)
|
|
(
|
|
before "Reset"
|
|
menuitem "[:bmc]Benchmark Counters" "BMC.state"
|
|
before "Reset"
|
|
separator
|
|
)
|
|
)
|
|
)
|
|
popup "Peripherals"
|
|
(
|
|
if STRing.SCAN(CORENAME(),"M0",0.)>=0.
|
|
(
|
|
popup "[:chip]Core Registers (Cortex-M0)"
|
|
(
|
|
menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M0),System Control"""
|
|
menuitem "[:chip]Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M0),Nested Vectored Interrupt Controller (NVIC)"""
|
|
popup "[:chip]Debug"
|
|
(
|
|
menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M0),Debug,Core Debug"""
|
|
menuitem "[:chip]BPU;Breakpoint Unit" "per , ""Core Registers (Cortex-M0),Debug,Breakpoint Unit (BPU)"""
|
|
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M0),Debug,Data Watchpoint and Trace Unit (DWT)"""
|
|
)
|
|
)
|
|
)
|
|
else
|
|
(
|
|
popup "[:chip]Core Registers (Cortex-M4F)"
|
|
(
|
|
menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M4F),System Control"""
|
|
menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M4F),Memory Protection Unit"""
|
|
menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M4F),Nested Vectored Interrupt Controller"""
|
|
menuitem "[:chip]FPU;Floating-point Unit" "per , ""Core Registers (Cortex-M4F),Floating-point Unit"""
|
|
popup "[:chip]Debug"
|
|
(
|
|
menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M4F),Debug,Core Debug"""
|
|
menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M4F),Debug,Flash Patch and Breakpoint Unit (FPB)"""
|
|
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M4F),Debug,Data Watchpoint and Trace Unit (DWT)"""
|
|
)
|
|
)
|
|
)
|
|
separator
|
|
menuitem "OTP" "per , ""OTP (One-Time Programmable)"""
|
|
menuitem "ER" "per , ""ER (Event router)"""
|
|
menuitem "CREG" "per , ""CREG (Configuration Registers)"""
|
|
menuitem "PMC" "per , ""PMC (Power Management Controller)"""
|
|
menuitem "CGU" "per , ""CGU (Clock Generation Unit)"""
|
|
menuitem "CCU" "per , ""CCU (Clock Control Unit)"""
|
|
menuitem "RGU" "per , ""RGU (Reset Generation Unit)"""
|
|
menuitem "SCU" "per , ""SCU (System Control Unit / IO configuration)"""
|
|
menuitem "GIMA" "per , ""GIMA (Global Input Multiplexer Array)"""
|
|
menuitem "GPIO" "per , ""GPIO (General Purpose Input/Output)"""
|
|
menuitem "SGPIO" "per , ""SGPIO (Serial GPIO)"""
|
|
menuitem "GPDMA" "per , ""GPDMA (General Purpose DMA)"""
|
|
menuitem "SD" "per , ""SD (SD/MMC interface)"""
|
|
menuitem "EMC" "per , ""EMC (External Memory Controller)"""
|
|
menuitem "SPIFI" "per , ""SPIFI (SPI Flash Interface)"""
|
|
if !cpuis("LPC431*")
|
|
(
|
|
menuitem "USB" "per , ""USB (USB Host/Device/OTG controller)"""
|
|
)
|
|
if cpuis("LPC433*")||cpuis("LPC435*")||cpuis("LPC437*")||cpuis("LPC43S3*")||cpuis("LPC43S5*")||cpuis("LPC43S7*")
|
|
(
|
|
menuitem "ETH" "per , ""ETH (Ethernet)"""
|
|
)
|
|
if (cpuis("LPC435*")||cpuis("LPC4370???25*")||cpuis("LPC43S5*")||cpuis("LPC43S70???25*"))
|
|
(
|
|
menuitem "LCD" "per , ""LCD"""
|
|
)
|
|
menuitem "SCT" "per , ""SCT (State Configurable Timer)"""
|
|
menuitem "TIMER" "per , ""TIMER 0/1/2/3"""
|
|
if !cpuis("LPC43?????10*")
|
|
(
|
|
menuitem "MC PWM" "per , ""MC PWM (Motor Control Pulse Width Modulator)"""
|
|
)
|
|
if (cpuis("LPC43?????18*")||cpuis("LPC43?????20*")||cpuis("LPC43?????25*")||cpuis("LPC43S?????18*")||cpuis("LPC43S?????20*")||cpuis("LPC43S?????25*"))
|
|
(
|
|
menuitem "QEI" "per , ""QEI (Quadrature Encoder Interface)"""
|
|
)
|
|
menuitem "RIT" "per , ""RIT (Repetitive Interrupt Timer)"""
|
|
menuitem "AT" "per , ""AT (Alarm timer)"""
|
|
menuitem "WWDT" "per , ""WWDT (Windowed Watchdog timer)"""
|
|
menuitem "RTC" "per , ""RTC (Real-Time Clock)"""
|
|
if !((cpuis("LPC4310*")||cpuis("LPC4320*")||cpuis("LPC4330*")||cpuis("LPC4350*")||cpuis("LPC4370*")||cpuis("LPC43S20*")||cpuis("LPC43S30*")||cpuis("LPC43S50*")||cpuis("LPC43S70*")))
|
|
(
|
|
menuitem "EMR" "per , ""EMR (Event monitor/recorder)"""
|
|
)
|
|
menuitem "USART" "per , ""USART (Universal Synchronous Asynchronous Receiver/Transmitter)"""
|
|
menuitem "SSP" "per , ""SSP (Synchronous Serial Port)"""
|
|
menuitem "SPI" "per , ""SPI (Serial Peripheral Interface)"""
|
|
menuitem "I2S" "per , ""I2S interface"""
|
|
menuitem "CAN" "per , ""CAN (Controller Area Network)"""
|
|
menuitem "I2C" "per , ""I2C (I2C-bus interface)"""
|
|
menuitem "ADC" "per , ""ADC (Analog-to-Digital Converter)"""
|
|
menuitem "DAC" "per , ""DAC (Digital-to-Analog Converter)"""
|
|
if !((cpuis("LPC4310*")||cpuis("LPC4320*")||cpuis("LPC4330*")||cpuis("LPC4350*")||cpuis("LPC4370*")||cpuis("LPC43S20*")||cpuis("LPC43S30*")||cpuis("LPC43S50*")||cpuis("LPC43S70*")))
|
|
(
|
|
menuitem "FMC" "per , ""FMC (Flash programming/ISP and IAP)"""
|
|
menuitem "EEPROM memory" "per , ""EEPROM memory"""
|
|
)
|
|
)
|
|
)
|