387 lines
14 KiB
Plaintext
387 lines
14 KiB
Plaintext
; --------------------------------------------------------------------------------
|
|
; @Title: LPC3220/30/40/50 Specific Menu
|
|
; @Props: Released
|
|
; @Author: BOB
|
|
; @Changelog: 2009-02-23 BOB
|
|
; @Manufacturer: NXP - NXP Semiconductors
|
|
; @Core: ARM926EJ-S
|
|
; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
|
|
; --------------------------------------------------------------------------------
|
|
; $Id: menlpc3xxx.men 16339 2023-07-03 13:30:14Z pegold $
|
|
|
|
add
|
|
menu
|
|
(
|
|
IF SOFTWARE.BUILD.BASE()>=69655.
|
|
(
|
|
popup "&CPU"
|
|
(
|
|
separator
|
|
IF CPU.FEATURE(MMU)
|
|
(
|
|
popup "[:mmu]MMU"
|
|
(
|
|
menuitem "[:mmureg]MMU Control" "MMU.view"
|
|
separator
|
|
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
|
|
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
|
|
separator
|
|
IF CPU.FEATURE(ITLBDUMP)
|
|
(
|
|
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
|
|
)
|
|
IF CPU.FEATURE(DTLBDUMP)
|
|
(
|
|
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
|
|
)
|
|
IF CPU.FEATURE(TLB0DUMP)
|
|
(
|
|
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
|
|
)
|
|
IF CPU.FEATURE(TLB1DUMP)
|
|
(
|
|
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
|
|
)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU")
|
|
(
|
|
popup "[:mmu]SMMU"
|
|
(
|
|
menuitem "[:chip]SMMU1 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU1 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU2")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU2 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU2 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU3")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU3 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU3 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU4")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU4 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU4 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU5")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU5 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU5 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU6")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU6 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU6 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
)
|
|
)
|
|
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
|
|
(
|
|
popup "[:cache]Cache"
|
|
(
|
|
IF CPU.FEATURE(L1ICACHEDUMP)
|
|
(
|
|
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
|
|
menuitem "[:cache]ICACHE List" "CACHE.List IC"
|
|
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
|
|
)
|
|
IF CPU.FEATURE(L1DCACHEDUMP)
|
|
(
|
|
separator
|
|
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
|
|
menuitem "[:cache]DCACHE List" "CACHE.List DC"
|
|
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
|
|
)
|
|
IF CPU.FEATURE(L2CACHEDUMP)
|
|
(
|
|
separator
|
|
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
|
|
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
|
|
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
|
|
)
|
|
)
|
|
)
|
|
)
|
|
popup "&Trace"
|
|
(
|
|
separator
|
|
IF COMPonent.AVAILable("ITM")
|
|
(
|
|
popup "ITM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]ITM settings..." "ITM.state"
|
|
separator
|
|
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("STM")
|
|
(
|
|
popup "STM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]STM settings..." "STM.state"
|
|
separator
|
|
menuitem "[:alist]STMTrace List" "STMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("HTM")
|
|
(
|
|
popup "HTM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]HTM settings..." "HTM.state"
|
|
separator
|
|
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("TPIU")
|
|
(
|
|
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
|
|
)
|
|
IF COMPonent.AVAILable("ETR")
|
|
(
|
|
menuitem "[:oconfig]ETR settings..."
|
|
(
|
|
PRIVATE &pdd
|
|
&pdd=OS.PDD()
|
|
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
|
|
)
|
|
)
|
|
)
|
|
popup "&Misc"
|
|
(
|
|
popup "Tools"
|
|
(
|
|
IF CPUIS64BIT()||CPU.FEATURE("SPR")
|
|
(
|
|
menuitem "ARM System Register Converter"
|
|
(
|
|
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
|
|
)
|
|
)
|
|
IF CPU.FEATURE("C15")
|
|
(
|
|
menuitem "ARM Coprocessor Converter"
|
|
(
|
|
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
|
|
)
|
|
)
|
|
)
|
|
)
|
|
popup "&Perf"
|
|
(
|
|
IF CPU.FEATURE(BMC)
|
|
(
|
|
before "Reset"
|
|
menuitem "[:bmc]Benchmark Counters" "BMC.state"
|
|
before "Reset"
|
|
separator
|
|
)
|
|
)
|
|
)
|
|
popup "Peripherals"
|
|
(
|
|
popup "[:chip]Core"
|
|
(
|
|
menuitem "[:chip]ID Registers" "per , ""ARM Core Registers,ID Registers"""
|
|
menuitem "[:chip]MMU Control and Configuration" "per , ""ARM Core Registers,MMU Control and Configuration"""
|
|
menuitem "[:chip]Cache Control and Configuration" "per , ""ARM Core Registers,Cache Control and Configuration"""
|
|
menuitem "[:chip]TCM Control and Configuration" "per , ""ARM Core Registers,TCM Control and Configuration"""
|
|
menuitem "[:chip]Test and Debug" "per , ""ARM Core Registers,Test and Debug"""
|
|
menuitem "[:chip]ICEbreaker" "per , ""ARM Core Registers,ICEbreaker"""
|
|
)
|
|
separator
|
|
menuitem "System Control" "per , ""System Control"""
|
|
popup "Clocking And Power"
|
|
(
|
|
menuitem "Clocking And Power Control" "per , ""Clocking And Power Control"""
|
|
menuitem "Start Enable Registers" "per , ""Clocking And Power Control,Start Enable Registers"""
|
|
menuitem "Start Status Registers" "per , ""Clocking And Power Control,Start Status Registers"""
|
|
menuitem "Start Activation Polarity Registers" "per , ""Clocking And Power Control,Start Activation Polarity Registers"""
|
|
)
|
|
popup "Interrupt Controller"
|
|
(
|
|
menuitem "General Registers" "per , ""Interrupt Controller,General Registers"""
|
|
menuitem "Main Interrupt Controller" "per , ""Interrupt Controller,Main Interrupt Controller"""
|
|
menuitem "Sub Interrupt Controller 1" "per , ""Interrupt Controller,Sub Interrupt Controller 1"""
|
|
menuitem "Sub Interrupt Controller 2" "per , ""Interrupt Controller,Sub Interrupt Controller 2"""
|
|
)
|
|
popup "GPDMA"
|
|
(
|
|
menuitem "General DMA Registers" "per , ""GPDMA (General Purpose DMA),General DMA Registers"""
|
|
menuitem "Channel 0" "per , ""GPDMA (General Purpose DMA),Channel 0"""
|
|
menuitem "Channel 1" "per , ""GPDMA (General Purpose DMA),Channel 1"""
|
|
menuitem "Channel 2" "per , ""GPDMA (General Purpose DMA),Channel 2"""
|
|
menuitem "Channel 3" "per , ""GPDMA (General Purpose DMA),Channel 3"""
|
|
menuitem "Channel 4" "per , ""GPDMA (General Purpose DMA),Channel 4"""
|
|
menuitem "Channel 5" "per , ""GPDMA (General Purpose DMA),Channel 5"""
|
|
menuitem "Channel 6" "per , ""GPDMA (General Purpose DMA),Channel 6"""
|
|
menuitem "Channel 7" "per , ""GPDMA (General Purpose DMA),Channel 7"""
|
|
)
|
|
menuitem "EMC" "per , ""EMC (External Memory Controller)"""
|
|
menuitem "ML FLASH " "per , ""ML FLASH (Multi-Level NAND Flash Controller)"""
|
|
menuitem "SL FLASH" "per , ""SL FLASH (Single-Level NAND Flash Controller)"""
|
|
if (cpu()=="LPC3230"||cpu()=="LPC3250")
|
|
(
|
|
popup "LCD"
|
|
(
|
|
menuitem "LCD" "per , ""LCD (Liquid Crystal Display)"""
|
|
menuitem "Color Palette" "per , ""LCD (Liquid Crystal Display),Color Palette Registers"""
|
|
menuitem "Cursor Image" "per , ""LCD (Liquid Crystal Display),Cursor Image Registers"""
|
|
)
|
|
)
|
|
menuitem "TSC" "per , ""TSC (Touch Screen Controller)"""
|
|
menuitem "ADC" "per , ""ADC (Analog/Digital Converter)"""
|
|
menuitem "Keyboard" "per , ""Keyboard Scan"""
|
|
if (cpu()=="LPC3240"||(cpu()=="LPC3250"))
|
|
(
|
|
popup "Ethernet"
|
|
(
|
|
menuitem "MA" "per , ""Ethernet Controller,MAC registers"""
|
|
menuitem "Control" "per , ""Ethernet Controller,Control registers"""
|
|
menuitem "Receive filter" "per , ""Ethernet Controller,Receive filter registers"""
|
|
menuitem "Module control" "per , ""Ethernet Controller,Module control registers"""
|
|
)
|
|
)
|
|
popup "USB Device"
|
|
(
|
|
menuitem "Interrupt" "per , ""USB Device Controller,Interrupt Registers"""
|
|
menuitem "Realization Transfer Command" "per , ""USB Device Controller,Realization, Transfer and Command Registers"""
|
|
menuitem "DMA" "per , ""USB Device Controller,Interrupt Registers"""
|
|
)
|
|
menuitem "USB Host" "per , ""USB Host (OHCI) Controller"""
|
|
menuitem "USB OTG" "per , ""USB OTG (On-The-Go) Controller"""
|
|
menuitem "SD Card" "per , ""SD (Secure Digital) Card Interface"""
|
|
popup "UART"
|
|
(
|
|
menuitem "Standard UART 3" "per , ""UART (Universal Asynchronous Receiver/Transmitter),Standard UART 3"""
|
|
menuitem "Standard UART 4" "per , ""UART (Universal Asynchronous Receiver/Transmitter),Standard UART 4"""
|
|
menuitem "Standard UART 5" "per , ""UART (Universal Asynchronous Receiver/Transmitter),Standard UART 5"""
|
|
menuitem "Standard UART 6" "per , ""UART (Universal Asynchronous Receiver/Transmitter),Standard UART 6"""
|
|
menuitem "Fast UART 1" "per , ""UART (Universal Asynchronous Receiver/Transmitter),Fast UART 1"""
|
|
menuitem "Fast UART 2" "per , ""UART (Universal Asynchronous Receiver/Transmitter),Fast UART 2"""
|
|
menuitem "Fast UART 7" "per , ""UART (Universal Asynchronous Receiver/Transmitter),Fast UART 7"""
|
|
menuitem "Additional Control" "per , ""UART (Universal Asynchronous Receiver/Transmitter),Additional Control Registers"""
|
|
)
|
|
popup "SPI"
|
|
(
|
|
menuitem "SPI 1" "per , ""SPI (Serial Peripheral Interface),SPI 1"""
|
|
menuitem "SPI 2" "per , ""SPI (Serial Peripheral Interface),SPI 2"""
|
|
)
|
|
popup "SSP"
|
|
(
|
|
menuitem "SSP 0" "per , ""SSP (Synchronous Serial Port),SSP 0"""
|
|
menuitem "SSP 1" "per , ""SSP (Synchronous Serial Port),SSP 1"""
|
|
)
|
|
popup "I2C"
|
|
(
|
|
menuitem "I2C 1" "per , ""I2C (Inter-Integrated Circuit),I2C 1"""
|
|
menuitem "I2C 2" "per , ""I2C (Inter-Integrated Circuit),I2C 2"""
|
|
)
|
|
popup "I2S"
|
|
(
|
|
menuitem "I2S 0" "per , ""I2S (Inter-IC Sound),I2S 0"""
|
|
menuitem "I2S 1" "per , ""I2S (Inter-IC Sound),I2S 1"""
|
|
)
|
|
popup "Standard Timers"
|
|
(
|
|
menuitem "Timer 0" "per , ""Standard Timers,Timer 0"""
|
|
menuitem "Timer 1" "per , ""Standard Timers,Timer 1"""
|
|
menuitem "Timer 2" "per , ""Standard Timers,Timer 2"""
|
|
menuitem "Timer 3" "per , ""Standard Timers,Timer 3"""
|
|
menuitem "Timer 4" "per , ""Standard Timers,Timer 4"""
|
|
menuitem "Timer 5" "per , ""Standard Timers,Timer 5"""
|
|
)
|
|
menuitem "HS Timer" "per , ""High Speed Timer"""
|
|
menuitem "MS Timer" "per , ""Milisecond Timer"""
|
|
menuitem "RTC" "per , ""RTC (Real Time Clock And Battery Ram)"""
|
|
menuitem "WDT" "per , ""WDT (Watchdog Timer)"""
|
|
menuitem "MCPWM" "per , ""MCPWM (Motor Control Pulse Width Modulators)"""
|
|
menuitem "PWM" "per , ""PWM (Pulse Width Modulators)"""
|
|
popup "GPIO"
|
|
(
|
|
menuitem "Port 0" "per , ""GPIO (General Purpose Input/Output),Port 0"""
|
|
menuitem "Port 1" "per , ""GPIO (General Purpose Input/Output),Port 1"""
|
|
menuitem "Port 2" "per , ""GPIO (General Purpose Input/Output),Port 2"""
|
|
menuitem "Port 3" "per , ""GPIO (General Purpose Input/Output),Port 3"""
|
|
)
|
|
popup "PINMUX"
|
|
(
|
|
menuitem "Peripheral MUX" "per , ""PINMUX (Pin Multiplexing),Peripheral MUX"""
|
|
menuitem "Port 0" "per , ""PINMUX (Pin Multiplexing),Port 0"""
|
|
menuitem "Port 1" "per , ""PINMUX (Pin Multiplexing),Port 1"""
|
|
menuitem "Port 2" "per , ""PINMUX (Pin Multiplexing),Port 2"""
|
|
menuitem "Port 3" "per , ""PINMUX (Pin Multiplexing),Port 3"""
|
|
)
|
|
menuitem "DEBUG" "per , ""DEBUG"""
|
|
)
|
|
)
|