327 lines
8.3 KiB
Plaintext
327 lines
8.3 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: LPC11xx Specific Menu
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; @Props: Released
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; @Author: ART, EMK, KRU, SLA, STR, TPP, MAF, LUK
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; @Changelog: 2018-12-21 LUK
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; @Manufacturer: NXP - NXP Semiconductors
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; @Core: Cortex-M0
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; @Chip: LPC1102, LPC1102LV, LPC1104, LPC1110, LPC1111/002, LPC1111/101
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; LPC1111/102, LPC1111/103, LPC1111/201, LPC1111/202 LPC1111/203
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; LPC1112/101, LPC1112/102, LPC1112/103, LPC1112/201, LPC1112/202
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; LPC1112/203, LPC1112LV, LPC1113/201, LPC1113/202, LPC1113/203
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; LPC1113/301, LPC1113/302, LPC1113/303, LPC1114/102, LPC1114/201
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; LPC1114/202, LPC1114/203, LPC1114/301, LPC1114/302, LPC1114/303
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; LPC1114/323, LPC1114/333, LPC1114LV, LPC1115/303, LPC1124JBD48
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; LPC1125JBD48, LPC1101LV
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; @Copyright: (C) 1989-2018 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: menlpc11xx.men 16339 2023-07-03 13:30:14Z pegold $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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popup "[:chip]Core Registers (Cortex-M0)"
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(
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menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M0),System Control"""
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menuitem "[:chip]Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M0),Nested Vectored Interrupt Controller (NVIC)"""
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popup "[:chip]Debug"
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(
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menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M0),Debug,Core Debug"""
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menuitem "[:chip]BPU;Breakpoint Unit" "per , ""Core Registers (Cortex-M0),Debug,Breakpoint Unit (BPU)"""
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menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M0),Debug,Data Watchpoint and Trace Unit (DWT)"""
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)
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)
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separator
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menuitem "System Control" "per , ""System Control"""
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if !cpuis("LPC11*LV")
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(
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menuitem "PMU" "per , ""Power Management Unit (PMU)"""
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)
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menuitem "I/O configuration" "per , ""I/O Configuration"""
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popup "GPIO (General Purpose Input/Output)"
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(
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menuitem "GPIO Port 0" "per , ""GPIO (General Purpose Input/Output),Port 0"""
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menuitem "GPIO Port 1" "per , ""GPIO (General Purpose Input/Output),Port 1"""
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if !cpuis("LPC1102")&&!cpuis("LPC1104")&&!cpuis("LPC1110")
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(
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menuitem "GPIO Port 2" "per , ""GPIO (General Purpose Input/Output),Port 2"""
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if !cpuis("LPC110*LV")
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(
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menuitem "GPIO Port 3" "per , ""GPIO (General Purpose Input/Output),Port 3"""
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)
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)
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)
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popup "UART (Universal Asynchronous Receiver/Transmitter)"
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(
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menuitem "UART 0" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART 0"""
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if cpuis("LPC112*")
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(
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menuitem "UART 1" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART 1"""
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menuitem "UART 2" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART 2"""
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)
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)
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if cpuis("LPC1102")||cpuis("LPC111*")||cpuis("LPC1104")
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(
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menuitem "I2C" "per , ""I2C (I2C Bus Interface)"""
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)
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popup "SSP (Synchronous Serial Port)"
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(
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menuitem "SSP0" "per , ""SSP (Synchronous Serial Port),SSP0"""
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if cpuis("LPC112*")||cpuis("LPC111*")
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(
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menuitem "SSP1" "per , ""SSP (Synchronous Serial Port),SSP1"""
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)
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)
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menuitem "ADC" "per , ""ADC (Analog-to-Digital Converter)"""
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popup "CT16B0/1;16-bit counter/timer"
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(
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menuitem "CT16B0" "per , ""CT16B (16-bit counter/timer),CT16B0"""
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menuitem "CT16B1" "per , ""CT16B (16-bit counter/timer),CT16B1"""
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)
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popup "CT32B0/1;32-bit counter/timer"
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(
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menuitem "CT32B0" "per , ""CT32B (32-bit counter/timer),CT32B0"""
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menuitem "CT32B1" "per , ""CT32B (32-bit counter/timer),CT32B1"""
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)
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menuitem "WDT" "per , ""WDT (Watchdog Timer)"""
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menuitem "FMC" "per , ""FMC (Flash memory programming firmware)"""
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)
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)
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