1233 lines
56 KiB
Plaintext
1233 lines
56 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: J7VCL Specific Menu
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; @Props: Released
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; @Author: KWI, KRZ
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; @Changelog: 2022-04-22 KRZ
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; @Manufacturer: TI - Texas Instruments
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; @Core: Cortex-A72, Cortex-R5F, Cortex-M3
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; @Chip: DRA821, DRA821-CM3, DRA821-CR5, DRA821-CR5-MAIN, DRA821-CR5-MCU
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: menj7vcl.men 16339 2023-07-03 13:30:14Z pegold $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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if (CORENAME()=="CORTEXM3")
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(
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popup "[:chip]Core Registers (Cortex-M3)"
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(
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menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M3),System Control"""
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menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M3),Memory Protection Unit"""
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menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M3),Nested Vectored Interrupt Controller"""
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popup "[:chip]Debug"
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(
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menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M3),Debug,Core Debug"""
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menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M3),Debug,Flash Patch and Breakpoint Unit (FPB)"""
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menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M3),Debug,Data Watchpoint and Trace Unit (DWT)"""
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)
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)
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)
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else
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(
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if (CORENAME()=="CORTEXR5F")
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(
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popup "[:chip]Core Registers (Cortex-R5F)"
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(
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menuitem "[:chip]ID Registers" "per , ""Core Registers (Cortex-R5F),ID Registers"""
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menuitem "[:chip]System Control and Configuration" "per , ""Core Registers (Cortex-R5F),System Control and Configuration"""
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menuitem "[:chip]MPU Control and Configuration" "per , ""Core Registers (Cortex-R5F),MPU Control and Configuration"""
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menuitem "[:chip]Cache Control and Configuration" "per , ""Core Registers (Cortex-R5F),Cache Control and Configuration"""
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menuitem "[:chip]TCM Control and Configuration" "per , ""Core Registers (Cortex-R5F),TCM Control and Configuration"""
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menuitem "[:chip]System Performance Monitor" "per , ""Core Registers (Cortex-R5F),System Performance Monitor"""
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separator
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menuitem "[:chip]Debug Registers" "per , ""Core Registers (Cortex-R5F),Debug Registers"""
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menuitem "[:chip]Breakpoint Registers" "per , ""Core Registers (Cortex-R5F),Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Control Registers" "per , ""Core Registers (Cortex-R5F),Watchpoint Control Registers"""
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)
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)
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else if (CORENAME()=="CORTEXA72")
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(
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popup "[:chip]Core Registers (Cortex-A72)"
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(
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menuitem "[:chip]ID Registers[AArch64]" "per , ""Core Registers (Cortex-A72),AArch64,ID Registers"""
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menuitem "[:chip]System Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A72),AArch64,System Control and Configuration"""
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menuitem "[:chip]Memory Management Unit[AArch64]" "per , ""Core Registers (Cortex-A72),AArch64,Memory Management Unit"""
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menuitem "[:chip]Virtualization Extensions[AArch64]" "per , ""Core Registers (Cortex-A72),AArch64,Virtualization Extensions"""
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menuitem "[:chip]Cache Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A72),AArch64,Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor[AArch64]" "per , ""Core Registers (Cortex-A72),AArch64,System Performance Monitor"""
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menuitem "[:chip]System Timer Registers[AArch64]" "per , ""Core Registers (Cortex-A72),AArch64,System Timer Registers"""
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menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch64]" "per , ""Core Registers (Cortex-A72),AArch64,Generic Interrupt Controller CPU Interface"""
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separator
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menuitem "[:chip]Debug Registers[AArch64]" "per , ""Core Registers (Cortex-A72),AArch64,Debug Registers"""
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separator
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menuitem "[:chip]Breakpoint Registers[AArch64]" "per , ""Core Registers (Cortex-A72),AArch64,Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Registers[AArch64]" "per , ""Core Registers (Cortex-A72),AArch64,Watchpoint Control Registers"""
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separator
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menuitem "[:chip]ID Registers[AArch32]" "per , ""Core Registers (Cortex-A72),AArch32,ID Registers"""
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menuitem "[:chip]System Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A72),AArch32,System Control and Configuration"""
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menuitem "[:chip]Memory Management Unit[AArch32]" "per , ""Core Registers (Cortex-A72),AArch32,Memory Management Unit"""
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menuitem "[:chip]Virtualization Extensions[AArch32]" "per , ""Core Registers (Cortex-A72),AArch32,Virtualization Extensions"""
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menuitem "[:chip]Cache Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A72),AArch32,Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor[AArch32]" "per , ""Core Registers (Cortex-A72),AArch32,System Performance Monitor"""
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menuitem "[:chip]System Timer Registers[AArch32]" "per , ""Core Registers (Cortex-A72),AArch32,System Timer Registers"""
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menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch32]" "per , ""Core Registers (Cortex-A72),AArch32,Generic Interrupt Controller CPU Interface"""
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separator
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menuitem "[:chip]Debug Registers[AArch32]" "per , ""Core Registers (Cortex-A72),AArch32,Debug Registers"""
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separator
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menuitem "[:chip]Breakpoint Registers[AArch32]" "per , ""Core Registers (Cortex-A72),AArch32,Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Registers[AArch32]" "per , ""Core Registers (Cortex-A72),AArch32,Watchpoint Control Registers"""
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separator
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menuitem "[:chip]Interrupt Controller (GIC-500)" "per , ""Core Registers (Cortex-A72),Interrupt Controller (GIC-500)"""
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)
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)
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separator
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popup "A72SS"
|
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(
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popup "CLUSTER_ECC"
|
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(
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menuitem "COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR" "per , ""A72SS_CLUSTER_ECC,COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR"""
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)
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popup "CORE0_ECC"
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(
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menuitem "COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR" "per , ""A72SS_CORE0_ECC,COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR"""
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)
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popup "CORE1_ECC"
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(
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menuitem "COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR" "per , ""A72SS_CORE1_ECC,COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR"""
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)
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)
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popup "ADC"
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(
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menuitem "MCU_ADC0" "per , ""ADC,MCU_ADC0"""
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menuitem "MCU_ADC0_ECC" "per , ""ADC,MCU_ADC0_ECC"""
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menuitem "MCU_ADC0_FIFO" "per , ""ADC,MCU_ADC0_FIFO"""
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)
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popup "ATL"
|
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(
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menuitem "ATL0_REG" "per , ""ATL,ATL0_REG"""
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)
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popup "Compute_Cluster"
|
|
(
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menuitem "COMPUTE_CLUSTER0_DMSC_BOOT" "per , ""Compute_Cluster,COMPUTE_CLUSTER0_DMSC_BOOT"""
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)
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popup "Control_Module"
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(
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menuitem "CTRL_MMR0" "per , ""Control_Module,CTRL_MMR0"""
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menuitem "MCU_CTRL_MMR0" "per , ""Control_Module,MCU_CTRL_MMR0"""
|
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menuitem "WKUP_CTRL_MMR0" "per , ""Control_Module,WKUP_CTRL_MMR0"""
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)
|
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popup "CPSW0"
|
|
(
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popup "ALE"
|
|
(
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menuitem "CPSW0_NUSS_ALE" "per , ""CPSW0_ALE,CPSW0_NUSS_ALE"""
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)
|
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popup "CONTROL"
|
|
(
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menuitem "CPSW0_NUSS_CONTROL" "per , ""CPSW0_CONTROL,CPSW0_NUSS_CONTROL"""
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)
|
|
popup "CPINT"
|
|
(
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menuitem "CPSW0_NUSS_CPINT" "per , ""CPSW0_CPINT,CPSW0_NUSS_CPINT"""
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|
)
|
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popup "CPTS"
|
|
(
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menuitem "CPSW0_NUSS_CPTS" "per , ""CPSW0_CPTS,CPSW0_NUSS_CPTS"""
|
|
)
|
|
popup "ECC"
|
|
(
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|
menuitem "CPSW0_ECC" "per , ""CPSW0_ECC,CPSW0_ECC"""
|
|
)
|
|
popup "MDIO"
|
|
(
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|
menuitem "CPSW0_NUSS_MDIO" "per , ""CPSW0_MDIO,CPSW0_NUSS_MDIO"""
|
|
)
|
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popup "Subsystem__SS_"
|
|
(
|
|
menuitem "CPSW0_NUSS_SS" "per , ""CPSW0_NUSS_Subsystem__SS_,CPSW0_NUSS_SS"""
|
|
)
|
|
popup "PCSR"
|
|
(
|
|
menuitem "CPSW0_NUSS_PCSR" "per , ""CPSW0_PCSR,CPSW0_NUSS_PCSR"""
|
|
)
|
|
popup "RAM"
|
|
(
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|
menuitem "CPSW0_NUSS_RAM" "per , ""CPSW0_RAM,CPSW0_NUSS_RAM"""
|
|
)
|
|
popup "SGMII"
|
|
(
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menuitem "CPSW0_NUSS_SGMII" "per , ""CPSW0_SGMII,CPSW0_NUSS_SGMII"""
|
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)
|
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popup "STAT"
|
|
(
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menuitem "CPSW0_NUSS_STAT" "per , ""CPSW0_STAT,CPSW0_NUSS_STAT"""
|
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)
|
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)
|
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popup "CPTS"
|
|
(
|
|
menuitem "NAVSS0_CPTS" "per , ""CPTS,NAVSS0_CPTS"""
|
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)
|
|
popup "DCC"
|
|
(
|
|
menuitem "MCU_DCC0" "per , ""DCC,MCU_DCC0"""
|
|
menuitem "MCU_DCC1" "per , ""DCC,MCU_DCC1"""
|
|
menuitem "MCU_DCC2" "per , ""DCC,MCU_DCC2"""
|
|
menuitem "DCC0" "per , ""DCC,DCC0"""
|
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menuitem "DCC1" "per , ""DCC,DCC1"""
|
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menuitem "DCC2" "per , ""DCC,DCC2"""
|
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menuitem "DCC3" "per , ""DCC,DCC3"""
|
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menuitem "DCC4" "per , ""DCC,DCC4"""
|
|
menuitem "DCC5" "per , ""DCC,DCC5"""
|
|
menuitem "DCC6" "per , ""DCC,DCC6"""
|
|
)
|
|
popup "DDR"
|
|
(
|
|
popup "Controller"
|
|
(
|
|
menuitem "COMPUTE_CLUSTER0_CTL_CFG" "per , ""DDR_Controller,COMPUTE_CLUSTER0_CTL_CFG"""
|
|
)
|
|
popup "PHY"
|
|
(
|
|
menuitem "COMPUTE_CLUSTER0_CTL_CFG_PHY" "per , ""DDR_PHY,COMPUTE_CLUSTER0_CTL_CFG_PHY"""
|
|
)
|
|
popup "Subsystem"
|
|
(
|
|
menuitem "COMPUTE_CLUSTER0_SS_CFG" "per , ""DDR_Subsystem,COMPUTE_CLUSTER0_SS_CFG"""
|
|
)
|
|
popup "DDRSS0_ECC_AGGR_CFG"
|
|
(
|
|
menuitem "COMPUTE_CLUSTER0_ECC_AGGR_CFG" "per , ""DDRSS0_ECC_AGGR_CFG,COMPUTE_CLUSTER0_ECC_AGGR_CFG"""
|
|
)
|
|
popup "DDRSS0_ECC_AGGR_CTL"
|
|
(
|
|
menuitem "COMPUTE_CLUSTER0_ECC_AGGR_CTL" "per , ""DDRSS0_ECC_AGGR_CTL,COMPUTE_CLUSTER0_ECC_AGGR_CTL"""
|
|
)
|
|
popup "DDRSS0_ECC_AGGR_VBUS"
|
|
(
|
|
menuitem "COMPUTE_CLUSTER0_ECC_AGGR_VBUS" "per , ""DDRSS0_ECC_AGGR_VBUS,COMPUTE_CLUSTER0_ECC_AGGR_VBUS"""
|
|
)
|
|
)
|
|
popup "ECAP"
|
|
(
|
|
menuitem "ECAP0_CTL_STS" "per , ""ECAP,ECAP0_CTL_STS"""
|
|
menuitem "ECAP1_CTL_STS" "per , ""ECAP,ECAP1_CTL_STS"""
|
|
menuitem "ECAP2_CTL_STS" "per , ""ECAP,ECAP2_CTL_STS"""
|
|
)
|
|
popup "ELM"
|
|
(
|
|
menuitem "ELM0" "per , ""ELM,ELM0"""
|
|
)
|
|
popup "EPWM"
|
|
(
|
|
menuitem "EHRPWM0_EHRPWM" "per , ""EPWM,EHRPWM0_EHRPWM"""
|
|
menuitem "EHRPWM1_EHRPWM" "per , ""EPWM,EHRPWM1_EHRPWM"""
|
|
menuitem "EHRPWM2_EHRPWM" "per , ""EPWM,EHRPWM2_EHRPWM"""
|
|
menuitem "EHRPWM3_EHRPWM" "per , ""EPWM,EHRPWM3_EHRPWM"""
|
|
menuitem "EHRPWM4_EHRPWM" "per , ""EPWM,EHRPWM4_EHRPWM"""
|
|
menuitem "EHRPWM5_EHRPWM" "per , ""EPWM,EHRPWM5_EHRPWM"""
|
|
menuitem "EHRPWM0_EPWM" "per , ""EPWM,EHRPWM0_EPWM"""
|
|
menuitem "EHRPWM1_EPWM" "per , ""EPWM,EHRPWM1_EPWM"""
|
|
menuitem "EHRPWM2_EPWM" "per , ""EPWM,EHRPWM2_EPWM"""
|
|
menuitem "EHRPWM3_EPWM" "per , ""EPWM,EHRPWM3_EPWM"""
|
|
menuitem "EHRPWM4_EPWM" "per , ""EPWM,EHRPWM4_EPWM"""
|
|
menuitem "EHRPWM5_EPWM" "per , ""EPWM,EHRPWM5_EPWM"""
|
|
)
|
|
popup "EQEP"
|
|
(
|
|
menuitem "EQEP0_REG" "per , ""EQEP,EQEP0_REG"""
|
|
menuitem "EQEP1_REG" "per , ""EQEP,EQEP1_REG"""
|
|
menuitem "EQEP2_REG" "per , ""EQEP,EQEP2_REG"""
|
|
)
|
|
popup "ESM"
|
|
(
|
|
menuitem "ESM0_CFG" "per , ""ESM,ESM0_CFG"""
|
|
menuitem "MCU_ESM0_CFG" "per , ""ESM,MCU_ESM0_CFG"""
|
|
menuitem "WKUP_ESM0_CFG" "per , ""ESM,WKUP_ESM0_CFG"""
|
|
)
|
|
popup "Firewall_Exception"
|
|
(
|
|
menuitem "CBASS_DATADEBUG0_GLB" "per , ""Firewall_Exception,CBASS_DATADEBUG0_GLB"""
|
|
menuitem "CBASS_HC2_0_GLB" "per , ""Firewall_Exception,CBASS_HC2_0_GLB"""
|
|
menuitem "CBASS_HC_CFG0_GLB" "per , ""Firewall_Exception,CBASS_HC_CFG0_GLB"""
|
|
menuitem "CBASS_INFRA0_GLB" "per , ""Firewall_Exception,CBASS_INFRA0_GLB"""
|
|
menuitem "CBASS_INFRA_NON_SAFE0_GLB" "per , ""Firewall_Exception,CBASS_INFRA_NON_SAFE0_GLB"""
|
|
menuitem "CBASS_IPPHY0_GLB" "per , ""Firewall_Exception,CBASS_IPPHY0_GLB"""
|
|
menuitem "CBASS_IPPHY_SAFE0_GLB" "per , ""Firewall_Exception,CBASS_IPPHY_SAFE0_GLB"""
|
|
menuitem "CBASS_MCASP_G0_0_GLB" "per , ""Firewall_Exception,CBASS_MCASP_G0_0_GLB"""
|
|
menuitem "CBASS_RC0_GLB" "per , ""Firewall_Exception,CBASS_RC0_GLB"""
|
|
menuitem "CBASS_RC_CFG0_GLB" "per , ""Firewall_Exception,CBASS_RC_CFG0_GLB"""
|
|
menuitem "MCU_CBASS0_GLB" "per , ""Firewall_Exception,MCU_CBASS0_GLB"""
|
|
menuitem "WKUP_CBASS0_GLB" "per , ""Firewall_Exception,WKUP_CBASS0_GLB"""
|
|
)
|
|
popup "FSS"
|
|
(
|
|
menuitem "MCU_FSS0_CFG" "per , ""FSS,MCU_FSS0_CFG"""
|
|
)
|
|
popup "GIC_ECC_AGGR"
|
|
(
|
|
menuitem "COMPUTE_CLUSTER0_ECC_AGGR" "per , ""GIC_ECC_AGGR,COMPUTE_CLUSTER0_ECC_AGGR"""
|
|
)
|
|
popup "GPIO"
|
|
(
|
|
popup "GPIO0"
|
|
(
|
|
menuitem "WKUP_GPIO1" "per , ""GPIO,GPIO0,WKUP_GPIO1"""
|
|
menuitem "WKUP_GPIO0" "per , ""GPIO,GPIO0,WKUP_GPIO0"""
|
|
menuitem "GPIO0" "per , ""GPIO,GPIO0,GPIO0"""
|
|
menuitem "GPIO2" "per , ""GPIO,GPIO0,GPIO2"""
|
|
menuitem "GPIO4" "per , ""GPIO,GPIO0,GPIO4"""
|
|
menuitem "GPIO6" "per , ""GPIO,GPIO0,GPIO6"""
|
|
)
|
|
)
|
|
popup "GPMC"
|
|
(
|
|
menuitem "GPMC0_CFG" "per , ""GPMC,GPMC0_CFG"""
|
|
)
|
|
popup "GTC0_GTC_CFG0"
|
|
(
|
|
menuitem "GTC0_GTC_CFG0" "per , ""GTC0_GTC_CFG0"""
|
|
menuitem "GTC0_GTC_CFG1" "per , ""GTC0_GTC_CFG1"""
|
|
menuitem "GTC0_GTC_CFG2" "per , ""GTC0_GTC_CFG2"""
|
|
menuitem "GTC0_GTC_CFG3" "per , ""GTC0_GTC_CFG3"""
|
|
)
|
|
popup "HyperBus"
|
|
(
|
|
menuitem "MCU_FSS0_HPB_CTRL" "per , ""HyperBus,MCU_FSS0_HPB_CTRL"""
|
|
menuitem "MCU_FSS0_HPB_ECC_AGGR" "per , ""HyperBus,MCU_FSS0_HPB_ECC_AGGR"""
|
|
menuitem "MCU_FSS0_HPB_SS_CFG" "per , ""HyperBus,MCU_FSS0_HPB_SS_CFG"""
|
|
)
|
|
popup "I2C"
|
|
(
|
|
menuitem "I2C0_CFG" "per , ""I2C,I2C0_CFG"""
|
|
menuitem "I2C1_CFG" "per , ""I2C,I2C1_CFG"""
|
|
menuitem "I2C2_CFG" "per , ""I2C,I2C2_CFG"""
|
|
menuitem "I2C3_CFG" "per , ""I2C,I2C3_CFG"""
|
|
menuitem "I2C4_CFG" "per , ""I2C,I2C4_CFG"""
|
|
menuitem "I2C5_CFG" "per , ""I2C,I2C5_CFG"""
|
|
menuitem "I2C6_CFG" "per , ""I2C,I2C6_CFG"""
|
|
menuitem "MCU_I2C0_CFG" "per , ""I2C,MCU_I2C0_CFG"""
|
|
menuitem "MCU_I2C1_CFG" "per , ""I2C,MCU_I2C1_CFG"""
|
|
menuitem "WKUP_I2C0_CFG" "per , ""I2C,WKUP_I2C0_CFG"""
|
|
)
|
|
popup "I3C"
|
|
(
|
|
menuitem "I3C0_MMR_MMRVBP" "per , ""I3C,I3C0_MMR_MMRVBP"""
|
|
menuitem "MCU_I3C0_MMR_MMRVBP" "per , ""I3C,MCU_I3C0_MMR_MMRVBP"""
|
|
menuitem "I3C0_P_ECC_AGGR_CFG" "per , ""I3C,I3C0_P_ECC_AGGR_CFG"""
|
|
menuitem "MCU_I3C0_P_ECC_AGGR_CFG" "per , ""I3C,MCU_I3C0_P_ECC_AGGR_CFG"""
|
|
menuitem "I3C0_S_ECC_AGGR_CFG" "per , ""I3C,I3C0_S_ECC_AGGR_CFG"""
|
|
menuitem "MCU_I3C0_S_ECC_AGGR_CFG" "per , ""I3C,MCU_I3C0_S_ECC_AGGR_CFG"""
|
|
menuitem "I3C0_VBP2APB_WRAP_CORE_VBP_MIPI_I3C_MST" "per , ""I3C,I3C0_VBP2APB_WRAP_CORE_VBP_MIPI_I3C_MST"""
|
|
menuitem "MCU_I3C0_VBP2APB_WRAP_CORE_VBP_MIPI_I3C_MST" "per , ""I3C,MCU_I3C0_VBP2APB_WRAP_CORE_VBP_MIPI_I3C_MST"""
|
|
)
|
|
popup "INTR0_INTR_ROUTER_CFG"
|
|
(
|
|
menuitem "MCU_NAVSS0_INTR0_CFG" "per , ""INTR0_INTR_ROUTER_CFG,MCU_NAVSS0_INTR0_CFG"""
|
|
menuitem "NAVSS0_INTR0_INTR_ROUTER_CFG" "per , ""INTR0_INTR_ROUTER_CFG,NAVSS0_INTR0_INTR_ROUTER_CFG"""
|
|
)
|
|
popup "Mailbox"
|
|
(
|
|
popup "NAVSS0_MAILBOX0_REGS0"
|
|
(
|
|
menuitem "NAVSS0_MAILBOX0_REGS0" "per , ""Mailbox,NAVSS0_MAILBOX0_REGS0,NAVSS0_MAILBOX0_REGS0"""
|
|
menuitem "NAVSS0_MAILBOX0_REGS1" "per , ""Mailbox,NAVSS0_MAILBOX0_REGS0,NAVSS0_MAILBOX0_REGS1"""
|
|
menuitem "NAVSS0_MAILBOX0_REGS2" "per , ""Mailbox,NAVSS0_MAILBOX0_REGS0,NAVSS0_MAILBOX0_REGS2"""
|
|
menuitem "NAVSS0_MAILBOX0_REGS3" "per , ""Mailbox,NAVSS0_MAILBOX0_REGS0,NAVSS0_MAILBOX0_REGS3"""
|
|
menuitem "NAVSS0_MAILBOX0_REGS4" "per , ""Mailbox,NAVSS0_MAILBOX0_REGS0,NAVSS0_MAILBOX0_REGS4"""
|
|
menuitem "NAVSS0_MAILBOX0_REGS5" "per , ""Mailbox,NAVSS0_MAILBOX0_REGS0,NAVSS0_MAILBOX0_REGS5"""
|
|
menuitem "NAVSS0_MAILBOX0_REGS6" "per , ""Mailbox,NAVSS0_MAILBOX0_REGS0,NAVSS0_MAILBOX0_REGS6"""
|
|
menuitem "NAVSS0_MAILBOX0_REGS7" "per , ""Mailbox,NAVSS0_MAILBOX0_REGS0,NAVSS0_MAILBOX0_REGS7"""
|
|
menuitem "NAVSS0_MAILBOX0_REGS8" "per , ""Mailbox,NAVSS0_MAILBOX0_REGS0,NAVSS0_MAILBOX0_REGS8"""
|
|
menuitem "NAVSS0_MAILBOX0_REGS9" "per , ""Mailbox,NAVSS0_MAILBOX0_REGS0,NAVSS0_MAILBOX0_REGS9"""
|
|
menuitem "NAVSS0_MAILBOX0_REGS10" "per , ""Mailbox,NAVSS0_MAILBOX0_REGS0,NAVSS0_MAILBOX0_REGS10"""
|
|
menuitem "NAVSS0_MAILBOX0_REGS11" "per , ""Mailbox,NAVSS0_MAILBOX0_REGS0,NAVSS0_MAILBOX0_REGS11"""
|
|
)
|
|
)
|
|
popup "MCAN"
|
|
(
|
|
popup "Core"
|
|
(
|
|
menuitem "MCAN0_CFG" "per , ""MCAN_Core,MCAN0_CFG"""
|
|
menuitem "MCAN1_CFG" "per , ""MCAN_Core,MCAN1_CFG"""
|
|
menuitem "MCAN2_CFG" "per , ""MCAN_Core,MCAN2_CFG"""
|
|
menuitem "MCAN3_CFG" "per , ""MCAN_Core,MCAN3_CFG"""
|
|
menuitem "MCAN4_CFG" "per , ""MCAN_Core,MCAN4_CFG"""
|
|
menuitem "MCAN5_CFG" "per , ""MCAN_Core,MCAN5_CFG"""
|
|
menuitem "MCAN6_CFG" "per , ""MCAN_Core,MCAN6_CFG"""
|
|
menuitem "MCAN7_CFG" "per , ""MCAN_Core,MCAN7_CFG"""
|
|
menuitem "MCAN8_CFG" "per , ""MCAN_Core,MCAN8_CFG"""
|
|
menuitem "MCAN9_CFG" "per , ""MCAN_Core,MCAN9_CFG"""
|
|
menuitem "MCAN10_CFG" "per , ""MCAN_Core,MCAN10_CFG"""
|
|
menuitem "MCAN11_CFG" "per , ""MCAN_Core,MCAN11_CFG"""
|
|
menuitem "MCAN12_CFG" "per , ""MCAN_Core,MCAN12_CFG"""
|
|
menuitem "MCAN13_CFG" "per , ""MCAN_Core,MCAN13_CFG"""
|
|
menuitem "MCAN14_CFG" "per , ""MCAN_Core,MCAN14_CFG"""
|
|
menuitem "MCAN15_CFG" "per , ""MCAN_Core,MCAN15_CFG"""
|
|
menuitem "MCAN16_CFG" "per , ""MCAN_Core,MCAN16_CFG"""
|
|
menuitem "MCAN17_CFG" "per , ""MCAN_Core,MCAN17_CFG"""
|
|
menuitem "MCU_MCAN0_CFG" "per , ""MCAN_Core,MCU_MCAN0_CFG"""
|
|
menuitem "MCU_MCAN1_CFG" "per , ""MCAN_Core,MCU_MCAN1_CFG"""
|
|
)
|
|
popup "ECC_Aggregator"
|
|
(
|
|
menuitem "MCAN0_ECC_AGGR" "per , ""MCAN_ECC_Aggregator,MCAN0_ECC_AGGR"""
|
|
menuitem "MCAN1_ECC_AGGR" "per , ""MCAN_ECC_Aggregator,MCAN1_ECC_AGGR"""
|
|
menuitem "MCAN2_ECC_AGGR" "per , ""MCAN_ECC_Aggregator,MCAN2_ECC_AGGR"""
|
|
menuitem "MCAN3_ECC_AGGR" "per , ""MCAN_ECC_Aggregator,MCAN3_ECC_AGGR"""
|
|
menuitem "MCAN4_ECC_AGGR" "per , ""MCAN_ECC_Aggregator,MCAN4_ECC_AGGR"""
|
|
menuitem "MCAN5_ECC_AGGR" "per , ""MCAN_ECC_Aggregator,MCAN5_ECC_AGGR"""
|
|
menuitem "MCAN6_ECC_AGGR" "per , ""MCAN_ECC_Aggregator,MCAN6_ECC_AGGR"""
|
|
menuitem "MCAN7_ECC_AGGR" "per , ""MCAN_ECC_Aggregator,MCAN7_ECC_AGGR"""
|
|
menuitem "MCAN8_ECC_AGGR" "per , ""MCAN_ECC_Aggregator,MCAN8_ECC_AGGR"""
|
|
menuitem "MCAN9_ECC_AGGR" "per , ""MCAN_ECC_Aggregator,MCAN9_ECC_AGGR"""
|
|
menuitem "MCAN10_ECC_AGGR" "per , ""MCAN_ECC_Aggregator,MCAN10_ECC_AGGR"""
|
|
menuitem "MCAN11_ECC_AGGR" "per , ""MCAN_ECC_Aggregator,MCAN11_ECC_AGGR"""
|
|
menuitem "MCAN12_ECC_AGGR" "per , ""MCAN_ECC_Aggregator,MCAN12_ECC_AGGR"""
|
|
menuitem "MCAN13_ECC_AGGR" "per , ""MCAN_ECC_Aggregator,MCAN13_ECC_AGGR"""
|
|
menuitem "MCAN14_ECC_AGGR" "per , ""MCAN_ECC_Aggregator,MCAN14_ECC_AGGR"""
|
|
menuitem "MCAN15_ECC_AGGR" "per , ""MCAN_ECC_Aggregator,MCAN15_ECC_AGGR"""
|
|
menuitem "MCAN16_ECC_AGGR" "per , ""MCAN_ECC_Aggregator,MCAN16_ECC_AGGR"""
|
|
menuitem "MCAN17_ECC_AGGR" "per , ""MCAN_ECC_Aggregator,MCAN17_ECC_AGGR"""
|
|
menuitem "MCU_MCAN0_ECC_AGGR" "per , ""MCAN_ECC_Aggregator,MCU_MCAN0_ECC_AGGR"""
|
|
menuitem "MCU_MCAN1_ECC_AGGR" "per , ""MCAN_ECC_Aggregator,MCU_MCAN1_ECC_AGGR"""
|
|
)
|
|
popup "Subsystem"
|
|
(
|
|
menuitem "MCAN0_SS" "per , ""MCAN_Subsystem,MCAN0_SS"""
|
|
menuitem "MCAN1_SS" "per , ""MCAN_Subsystem,MCAN1_SS"""
|
|
menuitem "MCAN2_SS" "per , ""MCAN_Subsystem,MCAN2_SS"""
|
|
menuitem "MCAN3_SS" "per , ""MCAN_Subsystem,MCAN3_SS"""
|
|
menuitem "MCAN4_SS" "per , ""MCAN_Subsystem,MCAN4_SS"""
|
|
menuitem "MCAN5_SS" "per , ""MCAN_Subsystem,MCAN5_SS"""
|
|
menuitem "MCAN6_SS" "per , ""MCAN_Subsystem,MCAN6_SS"""
|
|
menuitem "MCAN7_SS" "per , ""MCAN_Subsystem,MCAN7_SS"""
|
|
menuitem "MCAN8_SS" "per , ""MCAN_Subsystem,MCAN8_SS"""
|
|
menuitem "MCAN9_SS" "per , ""MCAN_Subsystem,MCAN9_SS"""
|
|
menuitem "MCAN10_SS" "per , ""MCAN_Subsystem,MCAN10_SS"""
|
|
menuitem "MCAN11_SS" "per , ""MCAN_Subsystem,MCAN11_SS"""
|
|
menuitem "MCAN12_SS" "per , ""MCAN_Subsystem,MCAN12_SS"""
|
|
menuitem "MCAN13_SS" "per , ""MCAN_Subsystem,MCAN13_SS"""
|
|
menuitem "MCAN14_SS" "per , ""MCAN_Subsystem,MCAN14_SS"""
|
|
menuitem "MCAN15_SS" "per , ""MCAN_Subsystem,MCAN15_SS"""
|
|
menuitem "MCAN16_SS" "per , ""MCAN_Subsystem,MCAN16_SS"""
|
|
menuitem "MCAN17_SS" "per , ""MCAN_Subsystem,MCAN17_SS"""
|
|
menuitem "MCU_MCAN0_SS" "per , ""MCAN_Subsystem,MCU_MCAN0_SS"""
|
|
menuitem "MCU_MCAN1_SS" "per , ""MCAN_Subsystem,MCU_MCAN1_SS"""
|
|
)
|
|
)
|
|
popup "MCASP"
|
|
(
|
|
menuitem "MCASP0_CFG" "per , ""MCASP,MCASP0_CFG"""
|
|
menuitem "MCASP1_CFG" "per , ""MCASP,MCASP1_CFG"""
|
|
menuitem "MCASP2_CFG" "per , ""MCASP,MCASP2_CFG"""
|
|
menuitem "MCASP0_DMA" "per , ""MCASP,MCASP0_DMA"""
|
|
menuitem "MCASP1_DMA" "per , ""MCASP,MCASP1_DMA"""
|
|
menuitem "MCASP2_DMA" "per , ""MCASP,MCASP2_DMA"""
|
|
)
|
|
popup "MCRC"
|
|
(
|
|
menuitem "MCU_NAVSS0_MCRC" "per , ""MCRC,MCU_NAVSS0_MCRC"""
|
|
menuitem "NAVSS0_MCRC" "per , ""MCRC,NAVSS0_MCRC"""
|
|
)
|
|
popup "MCSPI"
|
|
(
|
|
menuitem "MCSPI0_CFG" "per , ""MCSPI,MCSPI0_CFG"""
|
|
menuitem "MCSPI1_CFG" "per , ""MCSPI,MCSPI1_CFG"""
|
|
menuitem "MCSPI2_CFG" "per , ""MCSPI,MCSPI2_CFG"""
|
|
menuitem "MCSPI3_CFG" "per , ""MCSPI,MCSPI3_CFG"""
|
|
menuitem "MCSPI4_CFG" "per , ""MCSPI,MCSPI4_CFG"""
|
|
menuitem "MCU_MCSPI0_CFG" "per , ""MCSPI,MCU_MCSPI0_CFG"""
|
|
menuitem "MCU_MCSPI1_CFG" "per , ""MCSPI,MCU_MCSPI1_CFG"""
|
|
menuitem "MCU_MCSPI2_CFG" "per , ""MCSPI,MCU_MCSPI2_CFG"""
|
|
)
|
|
popup "MCU"
|
|
(
|
|
popup "MCU_CPSW0_ALE"
|
|
(
|
|
menuitem "MCU_CPSW0_NUSS_ALE" "per , ""MCU_CPSW0_ALE,MCU_CPSW0_NUSS_ALE"""
|
|
)
|
|
popup "MCU_CPSW0_CONTROL"
|
|
(
|
|
menuitem "MCU_CPSW0_NUSS_CONTROL" "per , ""MCU_CPSW0_CONTROL,MCU_CPSW0_NUSS_CONTROL"""
|
|
)
|
|
popup "MCU_CPSW0_CPINT"
|
|
(
|
|
menuitem "MCU_CPSW0_NUSS_CPINT" "per , ""MCU_CPSW0_CPINT,MCU_CPSW0_NUSS_CPINT"""
|
|
)
|
|
popup "MCU_CPSW0_CPTS"
|
|
(
|
|
menuitem "MCU_CPSW0_NUSS_CPTS" "per , ""MCU_CPSW0_CPTS,MCU_CPSW0_NUSS_CPTS"""
|
|
)
|
|
popup "MCU_CPSW0_ECC"
|
|
(
|
|
menuitem "MCU_CPSW0_ECC" "per , ""MCU_CPSW0_ECC,MCU_CPSW0_ECC"""
|
|
)
|
|
popup "MCU_CPSW0_MDIO"
|
|
(
|
|
menuitem "MCU_CPSW0_NUSS_MDIO" "per , ""MCU_CPSW0_MDIO,MCU_CPSW0_NUSS_MDIO"""
|
|
)
|
|
popup "MCU_CPSW0_NUSS_Subsystem__SS_"
|
|
(
|
|
menuitem "MCU_CPSW0_NUSS_SS" "per , ""MCU_CPSW0_NUSS_Subsystem__SS_,MCU_CPSW0_NUSS_SS"""
|
|
)
|
|
popup "MCU_CPSW0_RAM"
|
|
(
|
|
menuitem "MCU_CPSW0_NUSS_RAM" "per , ""MCU_CPSW0_RAM,MCU_CPSW0_NUSS_RAM"""
|
|
)
|
|
popup "MCU_CPSW0_SGMII"
|
|
(
|
|
menuitem "MCU_CPSW0_NUSS_SGMII" "per , ""MCU_CPSW0_SGMII,MCU_CPSW0_NUSS_SGMII"""
|
|
)
|
|
popup "MCU_CPSW0_STAT$1"
|
|
(
|
|
menuitem "MCU_CPSW0_NUSS_STAT0" "per , ""MCU_CPSW0_STAT$1,MCU_CPSW0_NUSS_STAT0"""
|
|
)
|
|
popup "MCU_NAVSS0_CFG"
|
|
(
|
|
menuitem "MCU_NAVSS0_CFG" "per , ""MCU_NAVSS0_CFG,MCU_NAVSS0_CFG"""
|
|
)
|
|
popup "MCU_NAVSS0_UDMASS_ECCAGGR0"
|
|
(
|
|
menuitem "MCU_NAVSS0_UDMASS_ECCAGGR0" "per , ""MCU_NAVSS0_UDMASS_ECCAGGR0,MCU_NAVSS0_UDMASS_ECCAGGR0"""
|
|
)
|
|
popup "MCU_NAVSS0_UDMASS_RINGACC0_ISC_ISC"
|
|
(
|
|
menuitem "MCU_NAVSS0_UDMASS_RINGACC0_ISC_ISC" "per , ""MCU_NAVSS0_UDMASS_RINGACC0_ISC_ISC,MCU_NAVSS0_UDMASS_RINGACC0_ISC_ISC"""
|
|
)
|
|
popup "MCU_PLL0_CFG"
|
|
(
|
|
menuitem "MCU_PLL0_CFG" "per , ""MCU_PLL0_CFG,MCU_PLL0_CFG"""
|
|
)
|
|
popup "MCU_SEC_MMR0_DBG_CTRL"
|
|
(
|
|
menuitem "MCU_SEC_MMR0_BOOT_CTRL" "per , ""MCU_SEC_MMR0_DBG_CTRL,MCU_SEC_MMR0_BOOT_CTRL"""
|
|
menuitem "MCU_SEC_MMR0_DBG_CTRL" "per , ""MCU_SEC_MMR0_DBG_CTRL,MCU_SEC_MMR0_DBG_CTRL"""
|
|
)
|
|
)
|
|
popup "MMCSD0"
|
|
(
|
|
popup "Host_Controller"
|
|
(
|
|
menuitem "MMCSD0_CTL_CFG" "per , ""MMCSD0_Host_Controller,MMCSD0_CTL_CFG"""
|
|
)
|
|
popup "RX_RAM_ECC_Aggregator"
|
|
(
|
|
menuitem "ECC_AGGR_RXMEM" "per , ""MMCSD0_RX_RAM_ECC_Aggregator,MMCSD0_ECC_AGGR_RXMEM"""
|
|
)
|
|
popup "Subsystem"
|
|
(
|
|
menuitem "MMCSD0_SS_CFG" "per , ""MMCSD0_Subsystem,MMCSD0_SS_CFG"""
|
|
)
|
|
popup "TX_RAM_ECC_Aggregator"
|
|
(
|
|
menuitem "MMCSD0_ECC_AGGR_TXMEM" "per , ""MMCSD0_TX_RAM_ECC_Aggregator,MMCSD0_ECC_AGGR_TXMEM"""
|
|
)
|
|
)
|
|
popup "MMCSD1"
|
|
(
|
|
popup "Host_Controller"
|
|
(
|
|
menuitem "MMCSD1_CTL_CFG" "per , ""MMCSD1_Host_Controller,MMCSD1_CTL_CFG"""
|
|
)
|
|
popup "RX_RAM_ECC_Aggregator"
|
|
(
|
|
menuitem "MMCSD1_ECC_AGGR_RXMEM" "per , ""MMCSD1_RX_RAM_ECC_Aggregator,MMCSD1_ECC_AGGR_RXMEM"""
|
|
)
|
|
popup "Subsystem"
|
|
(
|
|
menuitem "MMCSD1_SS_CFG" "per , ""MMCSD1_Subsystem,MMCSD1_SS_CFG"""
|
|
)
|
|
popup "TX_RAM_ECC_Aggregator"
|
|
(
|
|
menuitem "MMCSD1_ECC_AGGR_TXMEM" "per , ""MMCSD1_TX_RAM_ECC_Aggregator,MMCSD1_ECC_AGGR_TXMEM"""
|
|
)
|
|
)
|
|
popup "MODSS"
|
|
(
|
|
popup "INTA_CFG"
|
|
(
|
|
menuitem "NAVSS0_MODSS_INTA0_CFG" "per , ""MODSS_INTA_CFG,NAVSS0_MODSS_INTA0_CFG"""
|
|
menuitem "NAVSS0_MODSS_INTA1_CFG" "per , ""MODSS_INTA_CFG,NAVSS0_MODSS_INTA1_CFG"""
|
|
)
|
|
popup "INTA_CFG_IMAP"
|
|
(
|
|
menuitem "NAVSS0_MODSS_INTA0_CFG_IMAP" "per , ""MODSS_INTA_CFG_IMAP,NAVSS0_MODSS_INTA0_CFG_IMAP"""
|
|
menuitem "NAVSS0_MODSS_INTA1_CFG_IMAP" "per , ""MODSS_INTA_CFG_IMAP,NAVSS0_MODSS_INTA1_CFG_IMAP"""
|
|
)
|
|
popup "INTA_CFG_INTR"
|
|
(
|
|
menuitem "NAVSS0_MODSS_INTA0_CFG_INTR" "per , ""MODSS_INTA_CFG_INTR,NAVSS0_MODSS_INTA0_CFG_INTR"""
|
|
menuitem "NAVSS0_MODSS_INTA1_CFG_INTR" "per , ""MODSS_INTA_CFG_INTR,NAVSS0_MODSS_INTA1_CFG_INTR"""
|
|
)
|
|
)
|
|
popup "MSMC"
|
|
(
|
|
menuitem "COMPUTE_CLUSTER0_MSMC_CFGS0" "per , ""MSMC,COMPUTE_CLUSTER0_MSMC_CFGS0"""
|
|
)
|
|
popup "NAVSS0"
|
|
(
|
|
popup "NBSS_CFG_REGS0_MMRS"
|
|
(
|
|
menuitem "NAVSS0_NBSS_CFG_REGS0_MMRS" "per , ""NAVSS0_NBSS_CFG_REGS0_MMRS,NAVSS0_NBSS_CFG_REGS0_MMRS"""
|
|
)
|
|
popup "NBSS_NB0_MEM_ATTR0_CFG"
|
|
(
|
|
menuitem "NAVSS0_NBSS_NB0_MEM_ATTR0_CFG" "per , ""NAVSS0_NBSS_NB0_MEM_ATTR0_CFG,NAVSS0_NBSS_NB0_MEM_ATTR0_CFG"""
|
|
)
|
|
popup "NBSS_NB0_MEM_ATTR1_CFG"
|
|
(
|
|
menuitem "NAVSS0_NBSS_NB0_MEM_ATTR1_CFG" "per , ""NAVSS0_NBSS_NB0_MEM_ATTR1_CFG,NAVSS0_NBSS_NB0_MEM_ATTR1_CFG"""
|
|
)
|
|
popup "NBSS_NB1_MEM_ATTR0_CFG"
|
|
(
|
|
menuitem "NAVSS0_NBSS_NB1_MEM_ATTR0_CFG" "per , ""NAVSS0_NBSS_NB1_MEM_ATTR0_CFG,NAVSS0_NBSS_NB1_MEM_ATTR0_CFG"""
|
|
)
|
|
popup "NBSS_NB1_MEM_ATTR1_CFG"
|
|
(
|
|
menuitem "NAVSS0_NBSS_NB1_MEM_ATTR1_CFG" "per , ""NAVSS0_NBSS_NB1_MEM_ATTR1_CFG,NAVSS0_NBSS_NB1_MEM_ATTR1_CFG"""
|
|
)
|
|
popup "NBSS_NB_CFG_MMRS"
|
|
(
|
|
menuitem "NAVSS0_NBSS_NB0_CFG_MMRS" "per , ""NAVSS0_NBSS_NB_CFG_MMRS,NAVSS0_NBSS_NB0_CFG_MMRS"""
|
|
)
|
|
popup "PROXY0_BUF_CFG"
|
|
(
|
|
menuitem "MCU_NAVSS0_PROXY0_BUF_CFG" "per , ""NAVSS0_PROXY0_BUF_CFG,MCU_NAVSS0_PROXY0_BUF_CFG"""
|
|
menuitem "NAVSS0_PROXY0_BUF_CFG" "per , ""NAVSS0_PROXY0_BUF_CFG,NAVSS0_PROXY0_BUF_CFG"""
|
|
)
|
|
popup "PROXY0_CFG_BUF_CFG"
|
|
(
|
|
menuitem "MCU_NAVSS0_PROXY_CFG_GCFG" "per , ""NAVSS0_PROXY0_CFG_BUF_CFG,MCU_NAVSS0_PROXY_CFG_GCFG"""
|
|
menuitem "NAVSS0_PROXY0_CFG_BUF_CFG" "per , ""NAVSS0_PROXY0_CFG_BUF_CFG,NAVSS0_PROXY0_CFG_BUF_CFG"""
|
|
)
|
|
popup "PROXY_BUF"
|
|
(
|
|
menuitem "MCU_NAVSS0_PROXY_CFG_BUF" "per , ""NAVSS0_PROXY_BUF,MCU_NAVSS0_PROXY_CFG_BUF"""
|
|
menuitem "NAVSS0_PROXY_BUF" "per , ""NAVSS0_PROXY_BUF,NAVSS0_PROXY_BUF"""
|
|
)
|
|
popup "PROXY_TARGET0_DATA"
|
|
(
|
|
menuitem "MCU_NAVSS0_PROXY0_TARGET0_DATA" "per , ""NAVSS0_PROXY_TARGET0_DATA,MCU_NAVSS0_PROXY0_TARGET0_DATA"""
|
|
menuitem "NAVSS0_PROXY_TARGET0_DATA" "per , ""NAVSS0_PROXY_TARGET0_DATA,NAVSS0_PROXY_TARGET0_DATA"""
|
|
)
|
|
popup "PVU_CFG_TLBIF"
|
|
(
|
|
menuitem "NAVSS0_IO_PVU0_CFG_TLBIF" "per , ""NAVSS0_PVU_CFG_TLBIF,NAVSS0_IO_PVU0_CFG_TLBIF"""
|
|
)
|
|
popup "SEC_PROXY0_CFG_MMRS"
|
|
(
|
|
menuitem "MCU_NAVSS0_SEC_PROXY0_CFG" "per , ""NAVSS0_SEC_PROXY0_CFG_MMRS,MCU_NAVSS0_SEC_PROXY0_CFG"""
|
|
menuitem "NAVSS0_SEC_PROXY0_CFG_MMRS" "per , ""NAVSS0_SEC_PROXY0_CFG_MMRS,NAVSS0_SEC_PROXY0_CFG_MMRS"""
|
|
)
|
|
popup "SEC_PROXY0_CFG_RT"
|
|
(
|
|
menuitem "MCU_NAVSS0_SEC_PROXY0_CFG_RT" "per , ""NAVSS0_SEC_PROXY0_CFG_RT,MCU_NAVSS0_SEC_PROXY0_CFG_RT"""
|
|
menuitem "NAVSS0_SEC_PROXY0_CFG_RT" "per , ""NAVSS0_SEC_PROXY0_CFG_RT,NAVSS0_SEC_PROXY0_CFG_RT"""
|
|
)
|
|
popup "SEC_PROXY0_CFG_SCFG"
|
|
(
|
|
menuitem "MCU_NAVSS0_SEC_PROXY0_CFG_SCFG" "per , ""NAVSS0_SEC_PROXY0_CFG_SCFG,MCU_NAVSS0_SEC_PROXY0_CFG_SCFG"""
|
|
menuitem "NAVSS0_SEC_PROXY0_CFG_SCFG" "per , ""NAVSS0_SEC_PROXY0_CFG_SCFG,NAVSS0_SEC_PROXY0_CFG_SCFG"""
|
|
)
|
|
popup "SEC_PROXY0_SRC_TARGET_DATA"
|
|
(
|
|
menuitem "MCU_NAVSS0_SEC_PROXY0_TARGET_DATA" "per , ""NAVSS0_SEC_PROXY0_SRC_TARGET_DATA,MCU_NAVSS0_SEC_PROXY0_TARGET_DATA"""
|
|
menuitem "NAVSS0_SEC_PROXY0_SRC_TARGET_DATA" "per , ""NAVSS0_SEC_PROXY0_SRC_TARGET_DATA,NAVSS0_SEC_PROXY0_SRC_TARGET_DATA"""
|
|
)
|
|
popup "UDMASS_RINGACC0_CFG"
|
|
(
|
|
menuitem "MCU_NAVSS0_UDMASS_RINGACC0_CFG" "per , ""NAVSS0_UDMASS_RINGACC0_CFG,MCU_NAVSS0_UDMASS_RINGACC0_CFG"""
|
|
menuitem "NAVSS0_UDMASS_RINGACC0_CFG" "per , ""NAVSS0_UDMASS_RINGACC0_CFG,NAVSS0_UDMASS_RINGACC0_CFG"""
|
|
)
|
|
popup "UDMASS_RINGACC0_CFG_MON"
|
|
(
|
|
menuitem "MCU_NAVSS0_UDMASS_RINGACC0_CFG_MON" "per , ""NAVSS0_UDMASS_RINGACC0_CFG_MON,MCU_NAVSS0_UDMASS_RINGACC0_CFG_MON"""
|
|
menuitem "NAVSS0_UDMASS_RINGACC0_CFG_MON" "per , ""NAVSS0_UDMASS_RINGACC0_CFG_MON,NAVSS0_UDMASS_RINGACC0_CFG_MON"""
|
|
)
|
|
popup "UDMASS_RINGACC0_CFG_RT"
|
|
(
|
|
menuitem "MCU_NAVSS0_UDMASS_RINGACC0_CFG_RT" "per , ""NAVSS0_UDMASS_RINGACC0_CFG_RT,MCU_NAVSS0_UDMASS_RINGACC0_CFG_RT"""
|
|
menuitem "NAVSS0_UDMASS_RINGACC0_CFG_RT" "per , ""NAVSS0_UDMASS_RINGACC0_CFG_RT,NAVSS0_UDMASS_RINGACC0_CFG_RT"""
|
|
)
|
|
popup "UDMASS_RINGACC0_GCFG"
|
|
(
|
|
menuitem "MCU_NAVSS0_UDMASS_RINGACC0_CFG_GCFG" "per , ""NAVSS0_UDMASS_RINGACC0_GCFG,MCU_NAVSS0_UDMASS_RINGACC0_CFG_GCFG"""
|
|
menuitem "NAVSS0_UDMASS_RINGACC0_GCFG" "per , ""NAVSS0_UDMASS_RINGACC0_GCFG,NAVSS0_UDMASS_RINGACC0_GCFG"""
|
|
)
|
|
popup "UDMASS_RINGACC0_SRC_FIFOS"
|
|
(
|
|
menuitem "MCU_NAVSS0_UDMASS_RINGACC0_FIFOS" "per , ""NAVSS0_UDMASS_RINGACC0_SRC_FIFOS,MCU_NAVSS0_UDMASS_RINGACC0_FIFOS"""
|
|
menuitem "NAVSS0_UDMASS_RINGACC0_SRC_FIFOS" "per , ""NAVSS0_UDMASS_RINGACC0_SRC_FIFOS,NAVSS0_UDMASS_RINGACC0_SRC_FIFOS"""
|
|
)
|
|
)
|
|
popup "NAVSS_PVU_CFG"
|
|
(
|
|
menuitem "NAVSS0_DMA_PVU0_CFG" "per , ""NAVSS_PVU_CFG,NAVSS0_DMA_PVU0_CFG"""
|
|
menuitem "NAVSS0_IO_PVU0_CFG" "per , ""NAVSS_PVU_CFG,NAVSS0_IO_PVU0_CFG"""
|
|
)
|
|
popup "Null_Error_Reporting"
|
|
(
|
|
menuitem "CBASS_DATADEBUG0_ERR" "per , ""Null_Error_Reporting,CBASS_DATADEBUG0_ERR"""
|
|
menuitem "CBASS_FW0_ERR" "per , ""Null_Error_Reporting,CBASS_FW0_ERR"""
|
|
menuitem "CBASS_HC2_0_ERR" "per , ""Null_Error_Reporting,CBASS_HC2_0_ERR"""
|
|
menuitem "CBASS_HC_CFG0_ERR" "per , ""Null_Error_Reporting,CBASS_HC_CFG0_ERR"""
|
|
menuitem "CBASS_INFRA0_ERR" "per , ""Null_Error_Reporting,CBASS_INFRA0_ERR"""
|
|
menuitem "CBASS_INFRA_NON_SAFE0_ERR" "per , ""Null_Error_Reporting,CBASS_INFRA_NON_SAFE0_ERR"""
|
|
menuitem "CBASS_IPPHY0_ERR" "per , ""Null_Error_Reporting,CBASS_IPPHY0_ERR"""
|
|
menuitem "CBASS_IPPHY_SAFE0_ERR" "per , ""Null_Error_Reporting,CBASS_IPPHY_SAFE0_ERR"""
|
|
menuitem "CBASS_MCASP_G0_0_ERR" "per , ""Null_Error_Reporting,CBASS_MCASP_G0_0_ERR"""
|
|
menuitem "CBASS_RC0_ERR" "per , ""Null_Error_Reporting,CBASS_RC0_ERR"""
|
|
menuitem "CBASS_RC_CFG0_ERR" "per , ""Null_Error_Reporting,CBASS_RC_CFG0_ERR"""
|
|
menuitem "MCU_CBASS0_ERR" "per , ""Null_Error_Reporting,MCU_CBASS0_ERR"""
|
|
menuitem "MCU_CBASS_FW0_ERR" "per , ""Null_Error_Reporting,MCU_CBASS_FW0_ERR"""
|
|
menuitem "WKUP_CBASS0_ERR" "per , ""Null_Error_Reporting,WKUP_CBASS0_ERR"""
|
|
menuitem "WKUP_CBASS_FW0_ERR" "per , ""Null_Error_Reporting,WKUP_CBASS_FW0_ERR"""
|
|
)
|
|
popup "OSPI"
|
|
(
|
|
menuitem "MCU_FSS0_OSPI0_CTRL" "per , ""OSPI,MCU_FSS0_OSPI0_CTRL"""
|
|
menuitem "MCU_FSS0_OSPI0_ECC_AGGR" "per , ""OSPI,MCU_FSS0_OSPI0_ECC_AGGR"""
|
|
menuitem "MCU_FSS0_OSPI0_SS_CFG" "per , ""OSPI,MCU_FSS0_OSPI0_SS_CFG"""
|
|
)
|
|
popup "PCIE"
|
|
(
|
|
popup "CORE_AXI"
|
|
(
|
|
menuitem "PCIE1_CORE_DBN_CFG_PCIE_CORE" "per , ""PCIE_CORE_AXI,PCIE1_CORE_DBN_CFG_PCIE_CORE"""
|
|
)
|
|
popup "CPTS"
|
|
(
|
|
menuitem "PCIE1_CORE_CPTS_CFG_CPTS_VBUSP" "per , ""PCIE_CPTS,PCIE1_CORE_CPTS_CFG_CPTS_VBUSP"""
|
|
)
|
|
popup "DAT0"
|
|
(
|
|
menuitem "PCIE1_DAT0" "per , ""PCIE1_DAT0"""
|
|
)
|
|
popup "DAT1"
|
|
(
|
|
menuitem "PCIE1_DAT1" "per , ""PCIE1_DAT1"""
|
|
)
|
|
popup "ECC_AGGR0"
|
|
(
|
|
menuitem "PCIE1_CORE_ECC_AGGR0" "per , ""PCIE1_CORE_ECC_AGGR0"""
|
|
)
|
|
popup "ECC_AGGR1"
|
|
(
|
|
menuitem "PCIE1_CORE_ECC_AGGR1" "per , ""PCIE1_CORE_ECC_AGGR1"""
|
|
)
|
|
popup "INTD"
|
|
(
|
|
menuitem "PCIE1_CORE_PCIE_INTD_CFG_INTD_CFG" "per , ""PCIE_INTD,PCIE1_CORE_PCIE_INTD_CFG_INTD_CFG"""
|
|
)
|
|
popup "USER_CFG"
|
|
(
|
|
menuitem "PCIE1_CORE_USER_CFG_USER_CFG" "per , ""PCIE_USER_CFG,PCIE1_CORE_USER_CFG_USER_CFG"""
|
|
)
|
|
popup "VMAP"
|
|
(
|
|
menuitem "PCIE1_CORE_VMAP_MMRS" "per , ""PCIE_VMAP,PCIE1_CORE_VMAP_MMRS"""
|
|
)
|
|
)
|
|
popup "PDMA10_ECC"
|
|
(
|
|
menuitem "PDMA10_REGS" "per , ""PDMA10_ECC,PDMA10_REGS"""
|
|
)
|
|
popup "PDMA5_ECC"
|
|
(
|
|
menuitem "PDMA5_REGS" "per , ""PDMA5_ECC,PDMA5_REGS"""
|
|
)
|
|
popup "PDMA9_ECC"
|
|
(
|
|
menuitem "PDMA9_REGS" "per , ""PDMA9_ECC,PDMA9_REGS"""
|
|
)
|
|
popup "PI"
|
|
(
|
|
menuitem "COMPUTE_CLUSTER0_CTL_CFG_PI" "per , ""PI,COMPUTE_CLUSTER0_CTL_CFG_PI"""
|
|
)
|
|
popup "PLL0_CFG"
|
|
(
|
|
menuitem "PLL0_CFG" "per , ""PLL0_CFG,PLL0_CFG"""
|
|
)
|
|
popup "PLLCTRL0"
|
|
(
|
|
menuitem "PLLCTRL0" "per , ""PLLCTRL0,PLLCTRL0"""
|
|
menuitem "WKUP_PLLCTRL0" "per , ""PLLCTRL0,WKUP_PLLCTRL0"""
|
|
)
|
|
popup "PSC"
|
|
(
|
|
menuitem "PSC0" "per , ""PSC,PSC0"""
|
|
menuitem "WKUP_PSC0" "per , ""PSC,WKUP_PSC0"""
|
|
)
|
|
popup "PSI_L_CFG_PROXY"
|
|
(
|
|
menuitem "MCU_NAVSS0_UDMASS_PSILSS_CFG0_PROXY" "per , ""PSI_L_CFG_PROXY,MCU_NAVSS0_UDMASS_PSILSS_CFG0_PROXY"""
|
|
menuitem "NAVSS0_UDMASS_PSILCFG0_CFG_PROXY" "per , ""PSI_L_CFG_PROXY,NAVSS0_UDMASS_PSILCFG0_CFG_PROXY"""
|
|
)
|
|
popup "R5FSS"
|
|
(
|
|
popup "CCMR5"
|
|
(
|
|
menuitem "MCU_R5FSS0_COMPARE_CFG" "per , ""R5FSS_CCMR5,MCU_R5FSS0_COMPARE_CFG"""
|
|
menuitem "R5FSS0_COMPARE_CFG" "per , ""R5FSS_CCMR5,R5FSS0_COMPARE_CFG"""
|
|
)
|
|
popup "CPU0_ECC_AGGR_CFG_REGS"
|
|
(
|
|
menuitem "MCU_R5FSS0_CORE0_ECC_AGGR" "per , ""R5FSS_CPU0_ECC_AGGR_CFG_REGS,MCU_R5FSS0_CORE0_ECC_AGGR"""
|
|
menuitem "R5FSS0_CORE0_ECC_AGGR" "per , ""R5FSS_CPU0_ECC_AGGR_CFG_REGS,R5FSS0_CORE0_ECC_AGGR"""
|
|
)
|
|
popup "CPU1_ECC_AGGR_CFG_REGS"
|
|
(
|
|
menuitem "MCU_R5FSS0_ECC_AGGR" "per , ""R5FSS_CPU1_ECC_AGGR_CFG_REGS,MCU_R5FSS0_ECC_AGGR"""
|
|
menuitem "R5FSS0_ECC_AGGR" "per , ""R5FSS_CPU1_ECC_AGGR_CFG_REGS,R5FSS0_ECC_AGGR"""
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|
)
|
|
popup "EVNT_BUS_VBUSP_MMRS"
|
|
(
|
|
menuitem "MCU_R5FSS0" "per , ""R5FSS_EVNT_BUS_VBUSP_MMRS,MCU_R5FSS0"""
|
|
menuitem "R5FSS0" "per , ""R5FSS_EVNT_BUS_VBUSP_MMRS,R5FSS0"""
|
|
)
|
|
popup "VIM"
|
|
(
|
|
menuitem "ARMSS_VIC_CFG" "per , ""R5FSS_VIM,ARMSS_VIC_CFG"""
|
|
menuitem "MCU_ARMSS_VIC_CFG" "per , ""R5FSS_VIM,MCU_ARMSS_VIC_CFG"""
|
|
)
|
|
)
|
|
popup "RTI"
|
|
(
|
|
menuitem "MCU_RTI0_CFG" "per , ""RTI,MCU_RTI0_CFG"""
|
|
menuitem "MCU_RTI1_CFG" "per , ""RTI,MCU_RTI1_CFG"""
|
|
menuitem "RTI0_CFG" "per , ""RTI,RTI0_CFG"""
|
|
menuitem "RTI1_CFG" "per , ""RTI,RTI1_CFG"""
|
|
menuitem "RTI28_CFG" "per , ""RTI,RTI28_CFG"""
|
|
menuitem "RTI29_CFG" "per , ""RTI,RTI29_CFG"""
|
|
)
|
|
popup "SEC_MMR0_DBG_CTRL"
|
|
(
|
|
menuitem "SEC_MMR0_BOOT_CTRL" "per , ""SEC_MMR0_DBG_CTRL,SEC_MMR0_BOOT_CTRL"""
|
|
menuitem "SEC_MMR0_DBG_CTRL" "per , ""SEC_MMR0_DBG_CTRL,SEC_MMR0_DBG_CTRL"""
|
|
)
|
|
popup "SerDes"
|
|
(
|
|
menuitem "SERDES_10G0" "per , ""SerDes,SERDES_10G0"""
|
|
)
|
|
popup "Spinlock"
|
|
(
|
|
menuitem "NAVSS0_SPINLOCK" "per , ""Spinlock,NAVSS0_SPINLOCK"""
|
|
)
|
|
popup "TIMERMGR"
|
|
(
|
|
popup "CFG_CFG"
|
|
(
|
|
menuitem "NAVSS0_TIMERMGR0_CFG" "per , ""TIMERMGR_CFG_CFG,NAVSS0_TIMERMGR0_CFG"""
|
|
menuitem "NAVSS0_TIMERMGR1_CFG" "per , ""TIMERMGR_CFG_CFG,NAVSS0_TIMERMGR1_CFG"""
|
|
)
|
|
popup "CFG_OES"
|
|
(
|
|
menuitem "NAVSS0_TIMERMGR0_CFG_OES" "per , ""TIMERMGR_CFG_OES,NAVSS0_TIMERMGR0_CFG_OES"""
|
|
menuitem "NAVSS0_TIMERMGR1_CFG_OES" "per , ""TIMERMGR_CFG_OES,NAVSS0_TIMERMGR1_CFG_OES"""
|
|
)
|
|
popup "CFG_TIMERS"
|
|
(
|
|
menuitem "NAVSS0_TIMERMGR0_CFG_TIMERS" "per , ""TIMERMGR_CFG_TIMERS,NAVSS0_TIMERMGR0_CFG_TIMERS"""
|
|
menuitem "NAVSS0_TIMERMGR1_CFG_TIMERS" "per , ""TIMERMGR_CFG_TIMERS,NAVSS0_TIMERMGR1_CFG_TIMERS"""
|
|
)
|
|
)
|
|
popup "Timers"
|
|
(
|
|
menuitem "MCU_TIMER0_CFG" "per , ""Timers,MCU_TIMER0_CFG"""
|
|
menuitem "MCU_TIMER1_CFG" "per , ""Timers,MCU_TIMER1_CFG"""
|
|
menuitem "MCU_TIMER2_CFG" "per , ""Timers,MCU_TIMER2_CFG"""
|
|
menuitem "MCU_TIMER3_CFG" "per , ""Timers,MCU_TIMER3_CFG"""
|
|
menuitem "MCU_TIMER4_CFG" "per , ""Timers,MCU_TIMER4_CFG"""
|
|
menuitem "MCU_TIMER5_CFG" "per , ""Timers,MCU_TIMER5_CFG"""
|
|
menuitem "MCU_TIMER6_CFG" "per , ""Timers,MCU_TIMER6_CFG"""
|
|
menuitem "MCU_TIMER7_CFG" "per , ""Timers,MCU_TIMER7_CFG"""
|
|
menuitem "MCU_TIMER8_CFG" "per , ""Timers,MCU_TIMER8_CFG"""
|
|
menuitem "MCU_TIMER9_CFG" "per , ""Timers,MCU_TIMER9_CFG"""
|
|
menuitem "TIMER0_CFG" "per , ""Timers,TIMER0_CFG"""
|
|
menuitem "TIMER1_CFG" "per , ""Timers,TIMER1_CFG"""
|
|
menuitem "TIMER2_CFG" "per , ""Timers,TIMER2_CFG"""
|
|
menuitem "TIMER3_CFG" "per , ""Timers,TIMER3_CFG"""
|
|
menuitem "TIMER4_CFG" "per , ""Timers,TIMER4_CFG"""
|
|
menuitem "TIMER5_CFG" "per , ""Timers,TIMER5_CFG"""
|
|
menuitem "TIMER6_CFG" "per , ""Timers,TIMER6_CFG"""
|
|
menuitem "TIMER7_CFG" "per , ""Timers,TIMER7_CFG"""
|
|
menuitem "TIMER8_CFG" "per , ""Timers,TIMER8_CFG"""
|
|
menuitem "TIMER9_CFG" "per , ""Timers,TIMER9_CFG"""
|
|
menuitem "TIMER10_CFG" "per , ""Timers,TIMER10_CFG"""
|
|
menuitem "TIMER11_CFG" "per , ""Timers,TIMER11_CFG"""
|
|
menuitem "TIMER12_CFG" "per , ""Timers,TIMER12_CFG"""
|
|
menuitem "TIMER13_CFG" "per , ""Timers,TIMER13_CFG"""
|
|
menuitem "TIMER14_CFG" "per , ""Timers,TIMER14_CFG"""
|
|
menuitem "TIMER15_CFG" "per , ""Timers,TIMER15_CFG"""
|
|
menuitem "TIMER16_CFG" "per , ""Timers,TIMER16_CFG"""
|
|
menuitem "TIMER17_CFG" "per , ""Timers,TIMER17_CFG"""
|
|
menuitem "TIMER18_CFG" "per , ""Timers,TIMER18_CFG"""
|
|
menuitem "TIMER19_CFG" "per , ""Timers,TIMER19_CFG"""
|
|
)
|
|
popup "TIMESYNC_INTRTR0"
|
|
(
|
|
menuitem "CMPEVENT_INTRTR0_INTR_ROUTER_CFG" "per , ""TIMESYNC_INTRTR0,CMPEVENT_INTRTR0_INTR_ROUTER_CFG"""
|
|
menuitem "TIMESYNC_INTRTR0_INTR_ROUTER_CFG" "per , ""TIMESYNC_INTRTR0,TIMESYNC_INTRTR0_INTR_ROUTER_CFG"""
|
|
)
|
|
popup "UART"
|
|
(
|
|
popup "UART0"
|
|
(
|
|
menuitem "MCU_UART0" "per , ""UART,UART0,MCU_UART0"""
|
|
menuitem "UART0" "per , ""UART,UART0,UART0"""
|
|
menuitem "UART1" "per , ""UART,UART0,UART1"""
|
|
menuitem "UART2" "per , ""UART,UART0,UART2"""
|
|
menuitem "UART3" "per , ""UART,UART0,UART3"""
|
|
menuitem "UART4" "per , ""UART,UART0,UART4"""
|
|
menuitem "UART5" "per , ""UART,UART0,UART5"""
|
|
menuitem "UART6" "per , ""UART,UART0,UART6"""
|
|
menuitem "UART7" "per , ""UART,UART0,UART7"""
|
|
menuitem "UART8" "per , ""UART,UART0,UART8"""
|
|
menuitem "UART9" "per , ""UART,UART0,UART9"""
|
|
menuitem "WKUP_UART0" "per , ""UART,UART0,WKUP_UART0"""
|
|
)
|
|
)
|
|
popup "UDMASS"
|
|
(
|
|
popup "INTA0_CFG"
|
|
(
|
|
menuitem "MCU_NAVSS0_UDMASS_INTA0_CFG" "per , ""UDMASS_INTA0_CFG,MCU_NAVSS0_UDMASS_INTA0_CFG"""
|
|
menuitem "NAVSS0_UDMASS_INTA0_CFG" "per , ""UDMASS_INTA0_CFG,NAVSS0_UDMASS_INTA0_CFG"""
|
|
)
|
|
popup "INTA0_CFG_GCNTCFG"
|
|
(
|
|
menuitem "MCU_NAVSS0_UDMASS_INTA0_CFG_GCNTCFG" "per , ""UDMASS_INTA0_CFG_GCNTCFG,MCU_NAVSS0_UDMASS_INTA0_CFG_GCNTCFG"""
|
|
menuitem "NAVSS0_UDMASS_INTA0_CFG_GCNTCFG" "per , ""UDMASS_INTA0_CFG_GCNTCFG,NAVSS0_UDMASS_INTA0_CFG_GCNTCFG"""
|
|
)
|
|
popup "INTA0_CFG_GCNTRTI"
|
|
(
|
|
menuitem "MCU_NAVSS0_UDMASS_INTA0_GCNTRTI" "per , ""UDMASS_INTA0_CFG_GCNTRTI,MCU_NAVSS0_UDMASS_INTA0_GCNTRTI"""
|
|
menuitem "NAVSS0_UDMASS_INTA0_CFG_GCNTRTI" "per , ""UDMASS_INTA0_CFG_GCNTRTI,NAVSS0_UDMASS_INTA0_CFG_GCNTRTI"""
|
|
)
|
|
popup "INTA0_CFG_IMAP"
|
|
(
|
|
menuitem "MCU_NAVSS0_UDMASS_INTA0_CFG_IMAP" "per , ""UDMASS_INTA0_CFG_IMAP,MCU_NAVSS0_UDMASS_INTA0_CFG_IMAP"""
|
|
menuitem "NAVSS0_UDMASS_INTA0_CFG_IMAP" "per , ""UDMASS_INTA0_CFG_IMAP,NAVSS0_UDMASS_INTA0_CFG_IMAP"""
|
|
)
|
|
popup "INTA0_CFG_INTR"
|
|
(
|
|
menuitem "MCU_NAVSS0_UDMASS_INTA0_CFG_INTR" "per , ""UDMASS_INTA0_CFG_INTR,MCU_NAVSS0_UDMASS_INTA0_CFG_INTR"""
|
|
menuitem "NAVSS0_UDMASS_INTA0_CFG_INTR" "per , ""UDMASS_INTA0_CFG_INTR,NAVSS0_UDMASS_INTA0_CFG_INTR"""
|
|
)
|
|
popup "INTA0_CFG_L2G"
|
|
(
|
|
menuitem "MCU_NAVSS0_UDMASS_INTA0_CFG_L2G" "per , ""UDMASS_INTA0_CFG_L2G,MCU_NAVSS0_UDMASS_INTA0_CFG_L2G"""
|
|
menuitem "NAVSS0_UDMASS_INTA0_CFG_L2G" "per , ""UDMASS_INTA0_CFG_L2G,NAVSS0_UDMASS_INTA0_CFG_L2G"""
|
|
)
|
|
popup "INTA0_CFG_MCAST"
|
|
(
|
|
menuitem "MCU_NAVSS0_UDMASS_INTA0_CFG_MCAST" "per , ""UDMASS_INTA0_CFG_MCAST,MCU_NAVSS0_UDMASS_INTA0_CFG_MCAST"""
|
|
menuitem "NAVSS0_UDMASS_INTA0_CFG_MCAST" "per , ""UDMASS_INTA0_CFG_MCAST,NAVSS0_UDMASS_INTA0_CFG_MCAST"""
|
|
)
|
|
popup "UDMAP0_CFG"
|
|
(
|
|
menuitem "MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG" "per , ""UDMASS_UDMAP0_CFG,MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG"""
|
|
menuitem "NAVSS0_UDMASS_UDMAP0_CFG" "per , ""UDMASS_UDMAP0_CFG,NAVSS0_UDMASS_UDMAP0_CFG"""
|
|
)
|
|
popup "UDMAP0_CFG_RCHAN"
|
|
(
|
|
menuitem "MCU_NAVSS0_UDMASS_UDMAP0_RCHAN" "per , ""UDMASS_UDMAP0_CFG_RCHAN,MCU_NAVSS0_UDMASS_UDMAP0_RCHAN"""
|
|
menuitem "NAVSS0_UDMASS_UDMAP0_CFG_RCHAN" "per , ""UDMASS_UDMAP0_CFG_RCHAN,NAVSS0_UDMASS_UDMAP0_CFG_RCHAN"""
|
|
)
|
|
popup "UDMAP0_CFG_RCHANRT"
|
|
(
|
|
menuitem "MCU_NAVSS0_UDMASS_UDMAP_RCHANRT" "per , ""UDMASS_UDMAP0_CFG_RCHANRT,MCU_NAVSS0_UDMASS_UDMAP_RCHANRT"""
|
|
menuitem "NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT" "per , ""UDMASS_UDMAP0_CFG_RCHANRT,NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT"""
|
|
)
|
|
popup "UDMAP0_CFG_RFLOW"
|
|
(
|
|
menuitem "MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW" "per , ""UDMASS_UDMAP0_CFG_RFLOW,MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW"""
|
|
menuitem "NAVSS0_UDMASS_UDMAP0_CFG_RFLOW" "per , ""UDMASS_UDMAP0_CFG_RFLOW,NAVSS0_UDMASS_UDMAP0_CFG_RFLOW"""
|
|
)
|
|
popup "UDMAP0_CFG_TCHAN"
|
|
(
|
|
menuitem "MCU_NAVSS0_UDMASS_UDMAP0_TCHAN" "per , ""UDMASS_UDMAP0_CFG_TCHAN,MCU_NAVSS0_UDMASS_UDMAP0_TCHAN"""
|
|
menuitem "NAVSS0_UDMASS_UDMAP0_CFG_TCHAN" "per , ""UDMASS_UDMAP0_CFG_TCHAN,NAVSS0_UDMASS_UDMAP0_CFG_TCHAN"""
|
|
)
|
|
popup "UDMAP0_CFG_TCHANRT"
|
|
(
|
|
menuitem "MCU_NAVSS0_UDMASS_UDMAP_TCHANRT" "per , ""UDMASS_UDMAP0_CFG_TCHANRT,MCU_NAVSS0_UDMASS_UDMAP_TCHANRT"""
|
|
menuitem "NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT" "per , ""UDMASS_UDMAP0_CFG_TCHANRT,NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT"""
|
|
)
|
|
)
|
|
popup "USB"
|
|
(
|
|
popup "USB3P0SS_MMR_MMRVBP_USBSS_CMN"
|
|
(
|
|
menuitem "USB0_MMR_MMRVBP_USBSS_CMN" "per , ""USB3P0SS_MMR_MMRVBP_USBSS_CMN,USB0_MMR_MMRVBP_USBSS_CMN"""
|
|
)
|
|
popup "ECC_AGGR_CFG"
|
|
(
|
|
menuitem "USB0_ECC_AGGR" "per , ""USB_ECC_AGGR_CFG,USB0_ECC_AGGR"""
|
|
)
|
|
popup "RAMS_INJ_CFG"
|
|
(
|
|
menuitem "USB0_RAMS_INJ_CFG" "per , ""USB_RAMS_INJ_CFG,USB0_RAMS_INJ_CFG"""
|
|
)
|
|
)
|
|
popup "VIRTID_CFG_MMRS"
|
|
(
|
|
menuitem "NAV_DDR0_VIRTID_CFG_MMRS" "per , ""VIRTID_CFG_MMRS,NAV_DDR0_VIRTID_CFG_MMRS"""
|
|
menuitem "NAV_DDR1_VIRTID_CFG_MMRS" "per , ""VIRTID_CFG_MMRS,NAV_DDR1_VIRTID_CFG_MMRS"""
|
|
menuitem "NBSS_CFG_MSMC0_SLV_VIRTID_CFG_MMRS" "per , ""VIRTID_CFG_MMRS,NBSS_CFG_MSMC0_SLV_VIRTID_CFG_MMRS"""
|
|
)
|
|
popup "WKUP_GPIOMUX_INTRTR0"
|
|
(
|
|
menuitem "GPIOMUX_INTRTR0_INTR_ROUTER_CFG" "per , ""WKUP_GPIOMUX_INTRTR0,GPIOMUX_INTRTR0_INTR_ROUTER_CFG"""
|
|
menuitem "MAIN2MCU_LVL_INTRTR0_CFG" "per , ""WKUP_GPIOMUX_INTRTR0,MAIN2MCU_LVL_INTRTR0_CFG"""
|
|
menuitem "MAIN2MCU_PLS_INTRTR0_CFG" "per , ""WKUP_GPIOMUX_INTRTR0,MAIN2MCU_PLS_INTRTR0_CFG"""
|
|
menuitem "WKUP_GPIOMUX_INTRTR0_CFG" "per , ""WKUP_GPIOMUX_INTRTR0,WKUP_GPIOMUX_INTRTR0_CFG"""
|
|
)
|
|
popup "WKUP_VTM0"
|
|
(
|
|
menuitem "WKUP_VTM0_ECCAGGR_CFG" "per , ""WKUP_VTM0,WKUP_VTM0_ECCAGGR_CFG"""
|
|
menuitem "WKUP_VTM0_MMR_VBUSP_CFG1" "per , ""WKUP_VTM0,WKUP_VTM0_MMR_VBUSP_CFG1"""
|
|
menuitem "WKUP_VTM0_MMR_VBUSP_CFG2" "per , ""WKUP_VTM0,WKUP_VTM0_MMR_VBUSP_CFG2"""
|
|
)
|
|
)
|
|
)
|
|
)
|