937 lines
54 KiB
Plaintext
937 lines
54 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: IMX8QM Specific Menu
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; @Props: Released
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; @Author: KWI, JON
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; @Changelog: 18-09-2020 KWI
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; @Changelog: 22-01-2022 JON
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; @Manufacturer: NXP - NXP Semiconductors
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; @Core: Cortex-A53, Cortex-A72, Cortex-M4, Cortex-M0+
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; @Chip: IMX8Q, IMX8QP, IMX8QM, IMX8QM-CM4-0,IMX8QM-CM4-1
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: menimx8qm.men 16339 2023-07-03 13:30:14Z pegold $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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if CPUIS("IMX8QP")||CPUIS("IMX8QM")
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(
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popup "[:chip]Core Registers (Cortex-A72/A53)"
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(
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menuitem "[:chip]ID Registers[AArch64]" "per , ""Core Registers (Cortex-A72/A53),AArch64,ID Registers"""
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menuitem "[:chip]System Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A72/A53),AArch64,System Control and Configuration"""
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menuitem "[:chip]Memory Management Unit[AArch64]" "per , ""Core Registers (Cortex-A72/A53),AArch64,Memory Management Unit"""
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menuitem "[:chip]Virtualization Extensions[AArch64]" "per , ""Core Registers (Cortex-A72/A53),AArch64,Virtualization Extensions"""
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menuitem "[:chip]Cache Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A72/A53),AArch64,Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor[AArch64]" "per , ""Core Registers (Cortex-A72/A53),AArch64,System Performance Monitor"""
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menuitem "[:chip]System Timer Registers[AArch64]" "per , ""Core Registers (Cortex-A72/A53),AArch64,System Timer Registers"""
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menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch64]" "per , ""Core Registers (Cortex-A72/A53),AArch64,Generic Interrupt Controller CPU Interface"""
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separator
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menuitem "[:chip]Debug Registers[AArch64]" "per , ""Core Registers (Cortex-A72/A53),AArch64,Debug Registers"""
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separator
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menuitem "[:chip]Breakpoint Registers[AArch64]" "per , ""Core Registers (Cortex-A72/A53),AArch64,Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Control Registers[AArch64]" "per , ""Core Registers (Cortex-A72/A53),AArch64,Watchpoint Control Registers"""
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separator
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menuitem "[:chip]ID Registers[AArch32]" "per , ""Core Registers (Cortex-A72/A53),AArch32,ID Registers"""
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menuitem "[:chip]System Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A72/A53),AArch32,System Control and Configuration"""
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menuitem "[:chip]Memory Management Unit[AArch32]" "per , ""Core Registers (Cortex-A72/A53),AArch32,Memory Management Unit"""
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menuitem "[:chip]Virtualization Extensions[AArch32]" "per , ""Core Registers (Cortex-A72/A53),AArch32,Virtualization Extensions"""
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menuitem "[:chip]Cache Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A72/A53),AArch32,Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor[AArch32]" "per , ""Core Registers (Cortex-A72/A53),AArch32,System Performance Monitor"""
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menuitem "[:chip]System Timer Registers[AArch32]" "per , ""Core Registers (Cortex-A72/A53),AArch32,System Timer Registers"""
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menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch32]" "per , ""Core Registers (Cortex-A72/A53),AArch32,Generic Interrupt Controller CPU Interface"""
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separator
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menuitem "[:chip]Debug Registers[AArch32]" "per , ""Core Registers (Cortex-A72/A53),AArch32,Debug Registers"""
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separator
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menuitem "[:chip]Breakpoint Registers[AArch32]" "per , ""Core Registers (Cortex-A72/A53),AArch32,Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Control Registers[AArch32]" "per , ""Core Registers (Cortex-A72/A53),AArch32,Watchpoint Control Registers"""
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separator
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menuitem "[:chip]Interrupt Controller (GIC-500)" "per , ""Core Registers (Cortex-A72/A53),Interrupt Controller (GIC-500)"""
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)
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)
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else if CPUIS("IMX8*-ZPU")
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(
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popup "[:chip]Core Registers (Cortex-A53)"
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(
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menuitem "[:chip]ID Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,ID Registers"""
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menuitem "[:chip]System Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,System Control and Configuration"""
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menuitem "[:chip]Memory Management Unit[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Memory Management Unit"""
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menuitem "[:chip]Virtualization Extensions[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Virtualization Extensions"""
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menuitem "[:chip]Cache Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,System Performance Monitor"""
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menuitem "[:chip]System Timer Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,System Timer Registers"""
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menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Generic Interrupt Controller CPU Interface"""
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separator
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menuitem "[:chip]Debug Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Debug Registers"""
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separator
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menuitem "[:chip]Breakpoint Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Control Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Watchpoint Control Registers"""
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separator
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menuitem "[:chip]ID Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,ID Registers"""
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menuitem "[:chip]System Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,System Control and Configuration"""
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menuitem "[:chip]Memory Management Unit[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Memory Management Unit"""
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menuitem "[:chip]Virtualization Extensions[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Virtualization Extensions"""
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menuitem "[:chip]Cache Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,System Performance Monitor"""
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menuitem "[:chip]System Timer Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,System Timer Registers"""
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menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Generic Interrupt Controller CPU Interface"""
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separator
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menuitem "[:chip]Debug Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Debug Registers"""
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separator
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menuitem "[:chip]Breakpoint Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Control Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Watchpoint Control Registers"""
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)
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)
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else if CPUIS("IMX8Q")
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(
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popup "[:chip]Core Registers (Cortex-A53)"
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(
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menuitem "[:chip]ID Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,ID Registers"""
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menuitem "[:chip]System Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,System Control and Configuration"""
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menuitem "[:chip]Memory Management Unit[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Memory Management Unit"""
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menuitem "[:chip]Virtualization Extensions[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Virtualization Extensions"""
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menuitem "[:chip]Cache Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,System Performance Monitor"""
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menuitem "[:chip]System Timer Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,System Timer Registers"""
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menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Generic Interrupt Controller CPU Interface"""
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separator
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menuitem "[:chip]Debug Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Debug Registers"""
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separator
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menuitem "[:chip]Breakpoint Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Control Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Watchpoint Control Registers"""
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separator
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menuitem "[:chip]ID Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,ID Registers"""
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menuitem "[:chip]System Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,System Control and Configuration"""
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menuitem "[:chip]Memory Management Unit[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Memory Management Unit"""
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|
menuitem "[:chip]Virtualization Extensions[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Virtualization Extensions"""
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menuitem "[:chip]Cache Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,System Performance Monitor"""
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|
menuitem "[:chip]System Timer Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,System Timer Registers"""
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menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Generic Interrupt Controller CPU Interface"""
|
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separator
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menuitem "[:chip]Debug Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Debug Registers"""
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separator
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menuitem "[:chip]Breakpoint Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Control Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Watchpoint Control Registers"""
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separator
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menuitem "[:chip]Interrupt Controller (GIC-500)" "per , ""Core Registers (Cortex-A53),Interrupt Controller (GIC-500)"""
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)
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)
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else if CORENAME()=="CORTEXM4F"
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(
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popup "[:chip]Core Registers (Cortex-M4F)"
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(
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menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M4F),System Control"""
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menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M4F),Memory Protection Unit"""
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menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M4F),Nested Vectored Interrupt Controller"""
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menuitem "[:chip]FPU;Floating-point Unit" "per , ""Core Registers (Cortex-M4F),Floating-point Unit"""
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popup "[:chip]Debug"
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(
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menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M4F),Debug,Core Debug"""
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menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M4F),Debug,Flash Patch and Breakpoint Unit (FPB)"""
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menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M4F),Debug,Data Watchpoint and Trace Unit (DWT)"""
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)
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)
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)
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else
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(
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popup "[:chip]Core Registers (Cortex-M0+)"
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(
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menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M0+),System Control"""
|
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menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M0+),Memory Protection Unit (MPU)"""
|
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menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M0+),Nested Vectored Interrupt Controller (NVIC)"""
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popup "[:chip]Debug"
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(
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menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M0+),Debug,Core Debug"""
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menuitem "[:chip]BPU;Breakpoint Unit" "per , ""Core Registers (Cortex-M0+),Debug,Breakpoint Unit (BPU)"""
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menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M0+),Debug,Data Watchpoint and Trace Unit (DWT)"""
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)
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)
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)
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separator
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if (cpuis("IMX8*-CM4-0")||cpuis("IMX8*-CM4-1"))
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(
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menuitem "LMEM" "per , ""AHB_LMEM64_REV2 (LMEM64),LMEM"""
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)
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menuitem "CONNECTIVITY__APBH" "per , ""APBHDMA (APBH)"""
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popup "ASRC"
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(
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menuitem "AUDIO__ASRC0" "per , ""ASRC,AUDIO__ASRC0"""
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menuitem "AUDIO__ASRC1" "per , ""ASRC,AUDIO__ASRC1"""
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)
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menuitem "AUDIO__LPCG_ACM_REGS" "per , ""AUDIO_LPCG_ACM_REGS"""
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menuitem "AUDIO__LPCG_AMIX" "per , ""AUDIO_LPCG_AMIX"""
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popup "AUDIO_LPCG_ASRC"
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(
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menuitem "AUDIO__LPCG_ASRC0" "per , ""AUDIO_LPCG_ASRC,AUDIO__LPCG_ASRC0"""
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menuitem "AUDIO__LPCG_ASRC1" "per , ""AUDIO_LPCG_ASRC,AUDIO__LPCG_ASRC1"""
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)
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popup "AUDIO_LPCG_AUD_PLL_DIV_CLK"
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(
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menuitem "AUDIO__LPCG_ACM_AUD_PLL_DIV_CLK0" "per , ""AUDIO_LPCG_AUD_PLL_DIV_CLK,AUDIO__LPCG_ACM_AUD_PLL_DIV_CLK0"""
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menuitem "AUDIO__LPCG_ACM_AUD_PLL_DIV_CLK1" "per , ""AUDIO_LPCG_AUD_PLL_DIV_CLK,AUDIO__LPCG_ACM_AUD_PLL_DIV_CLK1"""
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)
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popup "AUDIO_LPCG_AUD_REC_CLK"
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(
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menuitem "AUDIO__LPCG_ACM_AUD_REC_CLK0" "per , ""AUDIO_LPCG_AUD_REC_CLK,AUDIO__LPCG_ACM_AUD_REC_CLK0"""
|
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menuitem "AUDIO__LPCG_ACM_AUD_REC_CLK1" "per , ""AUDIO_LPCG_AUD_REC_CLK,AUDIO__LPCG_ACM_AUD_REC_CLK1"""
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)
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popup "AUDIO_LPCG_EDMA"
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|
(
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menuitem "AUDIO__LPCG_EDMA0" "per , ""AUDIO_LPCG_EDMA,AUDIO__LPCG_EDMA0"""
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|
menuitem "AUDIO__LPCG_EDMA1" "per , ""AUDIO_LPCG_EDMA,AUDIO__LPCG_EDMA1"""
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)
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popup "AUDIO_LPCG_ESAI"
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|
(
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menuitem "AUDIO__LPCG_ESAI0" "per , ""AUDIO_LPCG_ESAI,AUDIO__LPCG_ESAI0"""
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|
menuitem "AUDIO__LPCG_ESAI1" "per , ""AUDIO_LPCG_ESAI,AUDIO__LPCG_ESAI1"""
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|
)
|
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popup "AUDIO_LPCG_GPT"
|
|
(
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menuitem "AUDIO__LPCG_GPT0" "per , ""AUDIO_LPCG_GPT,AUDIO__LPCG_GPT0"""
|
|
menuitem "AUDIO__LPCG_GPT1" "per , ""AUDIO_LPCG_GPT,AUDIO__LPCG_GPT1"""
|
|
menuitem "AUDIO__LPCG_GPT2" "per , ""AUDIO_LPCG_GPT,AUDIO__LPCG_GPT2"""
|
|
menuitem "AUDIO__LPCG_GPT3" "per , ""AUDIO_LPCG_GPT,AUDIO__LPCG_GPT3"""
|
|
menuitem "AUDIO__LPCG_GPT4" "per , ""AUDIO_LPCG_GPT,AUDIO__LPCG_GPT4"""
|
|
menuitem "AUDIO__LPCG_GPT5" "per , ""AUDIO_LPCG_GPT,AUDIO__LPCG_GPT5"""
|
|
)
|
|
popup "AUDIO_LPCG_MCLKOUT"
|
|
(
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|
menuitem "AUDIO__LPCG_MCLKOUT0" "per , ""AUDIO_LPCG_MCLKOUT,AUDIO__LPCG_MCLKOUT0"""
|
|
menuitem "AUDIO__LPCG_MCLKOUT1" "per , ""AUDIO_LPCG_MCLKOUT,AUDIO__LPCG_MCLKOUT1"""
|
|
)
|
|
menuitem "AUDIO__LPCG_MQS_REGS" "per , ""AUDIO_LPCG_MQS_REGS"""
|
|
menuitem "AUDIO__LPCG_SAI_HDMIRX0" "per , ""AUDIO_LPCG_SAI_HDMIRX0"""
|
|
menuitem "AUDIO__LPCG_SAI_HDMITX0" "per , ""AUDIO_LPCG_SAI_HDMITX0"""
|
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popup "AUDIO_LPCG_SAI"
|
|
(
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menuitem "AUDIO__LPCG_SAI0" "per , ""AUDIO_LPCG_SAI,AUDIO__LPCG_SAI0"""
|
|
menuitem "AUDIO__LPCG_SAI1" "per , ""AUDIO_LPCG_SAI,AUDIO__LPCG_SAI1"""
|
|
menuitem "AUDIO__LPCG_SAI2" "per , ""AUDIO_LPCG_SAI,AUDIO__LPCG_SAI2"""
|
|
menuitem "AUDIO__LPCG_SAI3" "per , ""AUDIO_LPCG_SAI,AUDIO__LPCG_SAI3"""
|
|
menuitem "AUDIO__LPCG_SAI6" "per , ""AUDIO_LPCG_SAI,AUDIO__LPCG_SAI6"""
|
|
menuitem "AUDIO__LPCG_SAI7" "per , ""AUDIO_LPCG_SAI,AUDIO__LPCG_SAI7"""
|
|
)
|
|
popup "AUDIO_LPCG_SPDIF"
|
|
(
|
|
menuitem "AUDIO__LPCG_SPDIF0" "per , ""AUDIO_LPCG_SPDIF,AUDIO__LPCG_SPDIF0"""
|
|
menuitem "AUDIO__LPCG_SPDIF1" "per , ""AUDIO_LPCG_SPDIF,AUDIO__LPCG_SPDIF1"""
|
|
)
|
|
menuitem "CONNECTIVITY__BCH" "per , ""BCH32 (BCH)"""
|
|
popup "CM4_LPCG_LPI2C"
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|
(
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menuitem "CM4_0__LPCG_LPI2C" "per , ""CM4_LPCG_LPI2C,CM4_0__LPCG_LPI2C"""
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|
menuitem "CM4_1__LPCG_LPI2C" "per , ""CM4_LPCG_LPI2C,CM4_1__LPCG_LPI2C"""
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)
|
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popup "CM4_LPCG_LPIT"
|
|
(
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menuitem "CM4_0__LPCG_LPIT" "per , ""CM4_LPCG_LPIT,CM4_0__LPCG_LPIT"""
|
|
menuitem "CM4_1__LPCG_LPIT" "per , ""CM4_LPCG_LPIT,CM4_1__LPCG_LPIT"""
|
|
)
|
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popup "CM4_LPCG_LPUART"
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|
(
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menuitem "CM4_0__LPCG_LPUART" "per , ""CM4_LPCG_LPUART,CM4_0__LPCG_LPUART"""
|
|
menuitem "CM4_1__LPCG_LPUART" "per , ""CM4_LPCG_LPUART,CM4_1__LPCG_LPUART"""
|
|
)
|
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popup "CM4_LPCG_MMCAU_HCLK"
|
|
(
|
|
menuitem "CM4_0__LPCG_MMCAU_HCLK" "per , ""CM4_LPCG_MMCAU_HCLK,CM4_0__LPCG_MMCAU_HCLK"""
|
|
menuitem "CM4_1__LPCG_MMCAU_HCLK" "per , ""CM4_LPCG_MMCAU_HCLK,CM4_1__LPCG_MMCAU_HCLK"""
|
|
)
|
|
popup "CM4_LPCG_TCMC_HCLK"
|
|
(
|
|
menuitem "CM4_0__LPCG_TCMC_HCLK" "per , ""CM4_LPCG_TCMC_HCLK,CM4_0__LPCG_TCMC_HCLK"""
|
|
menuitem "CM4_1__LPCG_TCMC_HCLK" "per , ""CM4_LPCG_TCMC_HCLK,CM4_1__LPCG_TCMC_HCLK"""
|
|
)
|
|
popup "CM4_LPCG_TPM"
|
|
(
|
|
menuitem "CM4_0__LPCG_TPM" "per , ""CM4_LPCG_TPM,CM4_0__LPCG_TPM"""
|
|
menuitem "CM4_1__LPCG_TPM" "per , ""CM4_LPCG_TPM,CM4_1__LPCG_TPM"""
|
|
)
|
|
menuitem "CONNECTIVITY__LPCG_DTCP" "per , ""CONNECTIVITY_LPCG_DTC"""
|
|
menuitem "CONNECTIVITY__LPCG_EDMA" "per , ""CONNECTIVITY_LPCG_EDMA"""
|
|
popup "CONNECTIVITY_LPCG_ENET"
|
|
(
|
|
menuitem "CONNECTIVITY__LPCG_ENET0" "per , ""CONNECTIVITY_LPCG_ENET,CONNECTIVITY__LPCG_ENET0"""
|
|
menuitem "CONNECTIVITY__LPCG_ENET1" "per , ""CONNECTIVITY_LPCG_ENET,CONNECTIVITY__LPCG_ENET1"""
|
|
)
|
|
menuitem "CONNECTIVITY__LPCG_MLB" "per , ""CONNECTIVITY_LPCG_MLB"""
|
|
menuitem "CONNECTIVITY__LPCG_RAWNAND" "per , ""CONNECTIVITY_LPCG_RAWNAND"""
|
|
popup "CONNECTIVITY_LPCG_USB"
|
|
(
|
|
menuitem "CONNECTIVITY__LPCG_USB2" "per , ""CONNECTIVITY_LPCG_USB,CONNECTIVITY__LPCG_USB2"""
|
|
menuitem "CONNECTIVITY__LPCG_USB3" "per , ""CONNECTIVITY_LPCG_USB,CONNECTIVITY__LPCG_USB3"""
|
|
)
|
|
popup "CONNECTIVITY_LPCG_USDHC"
|
|
(
|
|
menuitem "CONNECTIVITY__LPCG_USDHC0" "per , ""CONNECTIVITY_LPCG_USDHC,CONNECTIVITY__LPCG_USDHC0"""
|
|
menuitem "CONNECTIVITY__LPCG_USDHC1" "per , ""CONNECTIVITY_LPCG_USDHC,CONNECTIVITY__LPCG_USDHC1"""
|
|
menuitem "CONNECTIVITY__LPCG_USDHC2" "per , ""CONNECTIVITY_LPCG_USDHC,CONNECTIVITY__LPCG_USDHC2"""
|
|
)
|
|
popup "CSI2_RX_TOP"
|
|
(
|
|
menuitem "MIPI_CSI_0__MIPI_CSI2RX" "per , ""CSI2_RX_TOP,MIPI_CSI_0__MIPI_CSI2RX"""
|
|
menuitem "MIPI_CSI_1__MIPI_CSI2RX" "per , ""CSI2_RX_TOP,MIPI_CSI_1__MIPI_CSI2RX"""
|
|
)
|
|
popup "D_IP_ADCSAR_FIFO_SYN (ADC)"
|
|
(
|
|
menuitem "DMA__ADC0" "per , ""D_IP_ADCSAR_FIFO_SYN (ADC),DMA__ADC0"""
|
|
menuitem "DMA__ADC1" "per , ""D_IP_ADCSAR_FIFO_SYN (ADC),DMA__ADC1"""
|
|
)
|
|
popup "D_IP_FLEXCAN3_SYN (CAN)"
|
|
(
|
|
menuitem "DMA__CAN0" "per , ""D_IP_FLEXCAN3_SYN (CAN),DMA__CAN0"""
|
|
menuitem "DMA__CAN1" "per , ""D_IP_FLEXCAN3_SYN (CAN),DMA__CAN1"""
|
|
menuitem "DMA__CAN2" "per , ""D_IP_FLEXCAN3_SYN (CAN),DMA__CAN2"""
|
|
)
|
|
popup "D_IP_FLEXSPI_SYN (FlexSPI)"
|
|
(
|
|
menuitem "LSIO__FLEXSPI0" "per , ""D_IP_FLEXSPI_SYN (FlexSPI),LSIO__FLEXSPI0"""
|
|
menuitem "LSIO__FLEXSPI1" "per , ""D_IP_FLEXSPI_SYN (FlexSPI),LSIO__FLEXSPI1"""
|
|
)
|
|
popup "D_IP_FLEXTIMER32_SYN (FTM)"
|
|
(
|
|
menuitem "DMA__FTM0" "per , ""D_IP_FLEXTIMER32_SYN (FTM),DMA__FTM0"""
|
|
menuitem "DMA__FTM1" "per , ""D_IP_FLEXTIMER32_SYN (FTM),DMA__FTM1"""
|
|
)
|
|
popup "D_IP_LPIT_SYN (LPIT)"
|
|
(
|
|
menuitem "CM4_0__LPIT" "per , ""D_IP_LPIT_SYN (LPIT),CM4_0__LPIT"""
|
|
menuitem "CM4_1__LPIT" "per , ""D_IP_LPIT_SYN (LPIT),CM4_1__LPIT"""
|
|
menuitem "SCU__LPIT" "per , ""D_IP_LPIT_SYN (LPIT),SCU__LPIT"""
|
|
)
|
|
menuitem "CONNECTIVITY__USBDCD" "per , ""D_IP_USB_DCD_SYN (USBHSDCD)"""
|
|
popup "D_IP_WDG_SYN (WDOG)"
|
|
(
|
|
menuitem "CM4_0__WDOG" "per , ""D_IP_WDG_SYN (WDOG),CM4_0__WDOG"""
|
|
menuitem "CM4_1__WDOG" "per , ""D_IP_WDG_SYN (WDOG),CM4_1__WDOG"""
|
|
menuitem "SCU__WDOG" "per , ""D_IP_WDG_SYN (WDOG),SCU__WDOG"""
|
|
)
|
|
menuitem "SCU__LPC" "per , ""D_SSL_SCU_LPC_SYN (SCU_LPC)"""
|
|
menuitem "CONNECTIVITY__USB3" "per , ""DA_IP_USB3_WRAP"""
|
|
menuitem "DB__LPCG_BN_GATED" "per , ""DB_LPCG_BN"""
|
|
popup "DB_LPCG_PG"
|
|
(
|
|
menuitem "DB__LPCG_PG0" "per , ""DB_LPCG_PG,DB__LPCG_PG0"""
|
|
menuitem "DB__LPCG_PG1" "per , ""DB_LPCG_PG,DB__LPCG_PG1"""
|
|
menuitem "DB__LPCG_PG2" "per , ""DB_LPCG_PG,DB__LPCG_PG2"""
|
|
menuitem "DB__LPCG_PG3" "per , ""DB_LPCG_PG,DB__LPCG_PG3"""
|
|
)
|
|
menuitem "DBLOG__LPCG_CLK" "per , ""DBLOG_LPCG"""
|
|
popup "DC_LPCG"
|
|
(
|
|
menuitem "DC_0__LPCG_DSP0_CLK" "per , ""DC_LPCG,DC_0__LPCG_DSP0_CLK"""
|
|
menuitem "DC_1__LPCG_DSP0_CLK" "per , ""DC_LPCG,DC_1__LPCG_DSP0_CLK"""
|
|
)
|
|
menuitem "DI_HDMI__LPCG_CLK" "per , ""DI_HDMI_LPCG"""
|
|
popup "DI_LVDS_LPCG"
|
|
(
|
|
menuitem "DI_LVDS_0__LPCG_CLK" "per , ""DI_LVDS_LPCG,DI_LVDS_0__LPCG_CLK"""
|
|
menuitem "DI_LVDS_1__LPCG_CLK" "per , ""DI_LVDS_LPCG,DI_LVDS_1__LPCG_CLK"""
|
|
)
|
|
popup "DI_MIPI_LPCG"
|
|
(
|
|
menuitem "DI_MIPI_0__LPCG_CLK" "per , ""DI_MIPI_LPCG,DI_MIPI_0__LPCG_CLK"""
|
|
menuitem "DI_MIPI_1__LPCG_CLK" "per , ""DI_MIPI_LPCG,DI_MIPI_1__LPCG_CLK"""
|
|
)
|
|
popup "DMA_LPCG_ADC"
|
|
(
|
|
menuitem "DMA__LPCG_ADC0" "per , ""DMA_LPCG_ADC,DMA__LPCG_ADC0"""
|
|
menuitem "DMA__LPCG_ADC1" "per , ""DMA_LPCG_ADC,DMA__LPCG_ADC1"""
|
|
)
|
|
popup "DMA_LPCG_CAN"
|
|
(
|
|
menuitem "DMA__LPCG_CAN0" "per , ""DMA_LPCG_CAN,DMA__LPCG_CAN0"""
|
|
menuitem "DMA__LPCG_CAN1" "per , ""DMA_LPCG_CAN,DMA__LPCG_CAN1"""
|
|
menuitem "DMA__LPCG_CAN2" "per , ""DMA_LPCG_CAN,DMA__LPCG_CAN2"""
|
|
)
|
|
popup "DMA_LPCG_EMV_SIM"
|
|
(
|
|
menuitem "DMA__LPCG_EMV_SIM0" "per , ""DMA_LPCG_EMV_SIM,DMA__LPCG_EMV_SIM0"""
|
|
menuitem "DMA__LPCG_EMV_SIM1" "per , ""DMA_LPCG_EMV_SIM,DMA__LPCG_EMV_SIM1"""
|
|
)
|
|
popup "DMA_LPCG_FTM"
|
|
(
|
|
menuitem "DMA__LPCG_FTM0" "per , ""DMA_LPCG_FTM,DMA__LPCG_FTM0"""
|
|
menuitem "DMA__LPCG_FTM1" "per , ""DMA_LPCG_FTM,DMA__LPCG_FTM1"""
|
|
)
|
|
popup "DMA_LPCG_LPI2C"
|
|
(
|
|
menuitem "DMA__LPCG_LPI2C0" "per , ""DMA_LPCG_LPI2C,DMA__LPCG_LPI2C0"""
|
|
menuitem "DMA__LPCG_LPI2C1" "per , ""DMA_LPCG_LPI2C,DMA__LPCG_LPI2C1"""
|
|
menuitem "DMA__LPCG_LPI2C2" "per , ""DMA_LPCG_LPI2C,DMA__LPCG_LPI2C2"""
|
|
menuitem "DMA__LPCG_LPI2C3" "per , ""DMA_LPCG_LPI2C,DMA__LPCG_LPI2C3"""
|
|
menuitem "DMA__LPCG_LPI2C4" "per , ""DMA_LPCG_LPI2C,DMA__LPCG_LPI2C4"""
|
|
)
|
|
popup "DMA_LPCG_LPSPI"
|
|
(
|
|
menuitem "DMA__LPCG_LPSPI0" "per , ""DMA_LPCG_LPSPI,DMA__LPCG_LPSPI0"""
|
|
menuitem "DMA__LPCG_LPSPI1" "per , ""DMA_LPCG_LPSPI,DMA__LPCG_LPSPI1"""
|
|
menuitem "DMA__LPCG_LPSPI2" "per , ""DMA_LPCG_LPSPI,DMA__LPCG_LPSPI2"""
|
|
menuitem "DMA__LPCG_LPSPI3" "per , ""DMA_LPCG_LPSPI,DMA__LPCG_LPSPI3"""
|
|
)
|
|
popup "DMA_LPCG_LPUART"
|
|
(
|
|
menuitem "DMA__LPCG_LPUART0" "per , ""DMA_LPCG_LPUART,DMA__LPCG_LPUART0"""
|
|
menuitem "DMA__LPCG_LPUART1" "per , ""DMA_LPCG_LPUART,DMA__LPCG_LPUART1"""
|
|
menuitem "DMA__LPCG_LPUART2" "per , ""DMA_LPCG_LPUART,DMA__LPCG_LPUART2"""
|
|
menuitem "DMA__LPCG_LPUART3" "per , ""DMA_LPCG_LPUART,DMA__LPCG_LPUART3"""
|
|
menuitem "DMA__LPCG_LPUART4" "per , ""DMA_LPCG_LPUART,DMA__LPCG_LPUART4"""
|
|
)
|
|
popup "DRC_LPCG_"
|
|
(
|
|
menuitem "DRC_0__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK" "per , ""DRC_LPCG_,DRC_0__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK"""
|
|
menuitem "DRC_0__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0" "per , ""DRC_LPCG_,DRC_0__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0"""
|
|
menuitem "DRC_0__LPCG_DDR_PHY_PUB_CLK_CLK_MUX_D1" "per , ""DRC_LPCG_,DRC_0__LPCG_DDR_PHY_PUB_CLK_CLK_MUX_D1"""
|
|
menuitem "DRC_0__LPCG_SSI_PORT0_CLK" "per , ""DRC_LPCG_,DRC_0__LPCG_SSI_PORT0_CLK"""
|
|
menuitem "DRC_1__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK" "per , ""DRC_LPCG_,DRC_1__LPCG_DDR_CTL_CORE_DDRC_CORE_CLK"""
|
|
menuitem "DRC_1__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0" "per , ""DRC_LPCG_,DRC_1__LPCG_DDR_CTL_PCLK_LPDDR_INIT_CLK_MUX_D0"""
|
|
menuitem "DRC_1__LPCG_DDR_PHY_PUB_CLK_CLK_MUX_D1" "per , ""DRC_LPCG_,DRC_1__LPCG_DDR_PHY_PUB_CLK_CLK_MUX_D1"""
|
|
menuitem "DRC_1__LPCG_SSI_PORT0_CLK" "per , ""DRC_LPCG_,DRC_1__LPCG_SSI_PORT0_CLK"""
|
|
)
|
|
popup "DSI_HOST"
|
|
(
|
|
menuitem "DI_MIPI_0__MIPI_DSI_HOST" "per , ""DSI_HOST,DI_MIPI_0__MIPI_DSI_HOST"""
|
|
menuitem "DI_MIPI_1__MIPI_DSI_HOST" "per , ""DSI_HOST,DI_MIPI_1__MIPI_DSI_HOST"""
|
|
)
|
|
menuitem "CONNECTIVITY__DTCP" "per , ""DTCP"""
|
|
popup "EMV_SIM (EMVSIM)"
|
|
(
|
|
menuitem "DMA__EMV_SIM0" "per , ""EMV_SIM (EMVSIM),DMA__EMV_SIM0"""
|
|
menuitem "DMA__EMV_SIM1" "per , ""EMV_SIM (EMVSIM),DMA__EMV_SIM1"""
|
|
)
|
|
popup "ESAI"
|
|
(
|
|
menuitem "AUDIO__ESAI0" "per , ""ESAI,AUDIO__ESAI0"""
|
|
menuitem "AUDIO__ESAI1" "per , ""ESAI,AUDIO__ESAI1"""
|
|
)
|
|
popup "GPIO (General Purpose I/O Ports And Peripheral I/O Lines)"
|
|
(
|
|
menuitem "DI_HDMI__GPIO" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),DI_HDMI__GPIO"""
|
|
menuitem "DI_LVDS_0__GPIO" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),DI_LVDS_0__GPIO"""
|
|
menuitem "DI_LVDS_1__GPIO" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),DI_LVDS_1__GPIO"""
|
|
menuitem "DI_MIPI_0__GPIO" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),DI_MIPI_0__GPIO"""
|
|
menuitem "DI_MIPI_1__GPIO" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),DI_MIPI_1__GPIO"""
|
|
menuitem "HSIO__GPIO" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),HSIO__GPIO"""
|
|
menuitem "LSIO__GPIO0" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),LSIO__GPIO0"""
|
|
menuitem "LSIO__GPIO1" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),LSIO__GPIO1"""
|
|
menuitem "LSIO__GPIO2" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),LSIO__GPIO2"""
|
|
menuitem "LSIO__GPIO3" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),LSIO__GPIO3"""
|
|
menuitem "LSIO__GPIO4" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),LSIO__GPIO4"""
|
|
menuitem "LSIO__GPIO5" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),LSIO__GPIO5"""
|
|
menuitem "LSIO__GPIO6" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),LSIO__GPIO6"""
|
|
menuitem "LSIO__GPIO7" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),LSIO__GPIO7"""
|
|
menuitem "MIPI_CSI_0__GPIO" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),MIPI_CSI_0__GPIO"""
|
|
menuitem "MIPI_CSI_1__GPIO" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),MIPI_CSI_1__GPIO"""
|
|
menuitem "RX_HDMI__GPIO" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),RX_HDMI__GPIO"""
|
|
)
|
|
menuitem "CONNECTIVITY__GPMI" "per , ""GPMI2 (GPMI)"""
|
|
popup "GPT (General Purpose Timer)"
|
|
(
|
|
menuitem "AUDIO__GPT0" "per , ""GPT (General Purpose Timer),AUDIO__GPT0"""
|
|
menuitem "AUDIO__GPT1" "per , ""GPT (General Purpose Timer),AUDIO__GPT1"""
|
|
menuitem "AUDIO__GPT2" "per , ""GPT (General Purpose Timer),AUDIO__GPT2"""
|
|
menuitem "AUDIO__GPT3" "per , ""GPT (General Purpose Timer),AUDIO__GPT3"""
|
|
menuitem "AUDIO__GPT4" "per , ""GPT (General Purpose Timer),AUDIO__GPT4"""
|
|
menuitem "AUDIO__GPT5" "per , ""GPT (General Purpose Timer),AUDIO__GPT5"""
|
|
menuitem "LSIO__GPT0" "per , ""GPT (General Purpose Timer),LSIO__GPT0"""
|
|
menuitem "LSIO__GPT1" "per , ""GPT (General Purpose Timer),LSIO__GPT1"""
|
|
menuitem "LSIO__GPT2" "per , ""GPT (General Purpose Timer),LSIO__GPT2"""
|
|
menuitem "LSIO__GPT3" "per , ""GPT (General Purpose Timer),LSIO__GPT3"""
|
|
menuitem "LSIO__GPT4" "per , ""GPT (General Purpose Timer),LSIO__GPT4"""
|
|
)
|
|
menuitem "HSIO__LPCG_GPIO" "per , ""HSIO_LPCG_GPIO"""
|
|
menuitem "HSIO__LPCG_MISC_REGS" "per , ""HSIO_LPCG_MISC_REGS"""
|
|
menuitem "HSIO__LPCG_PCIEX1" "per , ""HSIO_LPCG_PCIEX1"""
|
|
menuitem "HSIO__LPCG_PCIEX1_REGS" "per , ""HSIO_LPCG_PCIEX1_REGS"""
|
|
menuitem "HSIO__LPCG_PCIEX2" "per , ""HSIO_LPCG_PCIEX2"""
|
|
menuitem "HSIO__LPCG_PCIEX2_REGS" "per , ""HSIO_LPCG_PCIEX2_REGS"""
|
|
menuitem "HSIO__LPCG_PHYX1" "per , ""HSIO_LPCG_PHYX1"""
|
|
menuitem "HSIO__LPCG_PHYX1_REGS" "per , ""HSIO_LPCG_PHYX1_REGS"""
|
|
menuitem "HSIO__LPCG_PHYX2" "per , ""HSIO_LPCG_PHYX2"""
|
|
menuitem "HSIO__LPCG_PHYX2_REGS" "per , ""HSIO_LPCG_PHYX2_REGS"""
|
|
menuitem "HSIO__LPCG_SATA" "per , ""HSIO_LPCG_SATA"""
|
|
menuitem "HSIO__LPCG_SATA_REGS" "per , ""HSIO_LPCG_SATA_REGS"""
|
|
menuitem "IMAGING__LPCG_DECODE_JPEG_CLK" "per , ""IMAGING_LPCG_MJPEG_COMMON_DEC"""
|
|
menuitem "IMAGING__LPCG_ENCODE_JPEG_CLK" "per , ""IMAGING_LPCG_MJPEG_COMMON_ENC"""
|
|
popup "IMAGING_LPCG_PDMA"
|
|
(
|
|
menuitem "IMAGING__LPCG_PROC_CLK_0" "per , ""IMAGING_LPCG_PDMA,IMAGING__LPCG_PROC_CLK_0"""
|
|
menuitem "IMAGING__LPCG_PROC_CLK_1" "per , ""IMAGING_LPCG_PDMA,IMAGING__LPCG_PROC_CLK_1"""
|
|
menuitem "IMAGING__LPCG_PROC_CLK_2" "per , ""IMAGING_LPCG_PDMA,IMAGING__LPCG_PROC_CLK_2"""
|
|
menuitem "IMAGING__LPCG_PROC_CLK_3" "per , ""IMAGING_LPCG_PDMA,IMAGING__LPCG_PROC_CLK_3"""
|
|
menuitem "IMAGING__LPCG_PROC_CLK_4" "per , ""IMAGING_LPCG_PDMA,IMAGING__LPCG_PROC_CLK_4"""
|
|
menuitem "IMAGING__LPCG_PROC_CLK_5" "per , ""IMAGING_LPCG_PDMA,IMAGING__LPCG_PROC_CLK_5"""
|
|
menuitem "IMAGING__LPCG_PROC_CLK_6" "per , ""IMAGING_LPCG_PDMA,IMAGING__LPCG_PROC_CLK_6"""
|
|
menuitem "IMAGING__LPCG_PROC_CLK_7" "per , ""IMAGING_LPCG_PDMA,IMAGING__LPCG_PROC_CLK_7"""
|
|
)
|
|
popup "IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI"
|
|
(
|
|
menuitem "IMAGING__LPCG_PIXEL_LINK_SLV_CSI0" "per , ""IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI,IMAGING__LPCG_PIXEL_LINK_SLV_CSI0"""
|
|
menuitem "IMAGING__LPCG_PIXEL_LINK_SLV_CSI1" "per , ""IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI,IMAGING__LPCG_PIXEL_LINK_SLV_CSI1"""
|
|
)
|
|
popup "IMAGING_LPCG_PIXEL_LINK_SLAVE_DC"
|
|
(
|
|
menuitem "IMAGING__LPCG_PIXEL_LINK_SLV_DC0_INGRESS_CLK" "per , ""IMAGING_LPCG_PIXEL_LINK_SLAVE_DC,IMAGING__LPCG_PIXEL_LINK_SLV_DC0_INGRESS_CLK"""
|
|
menuitem "IMAGING__LPCG_PIXEL_LINK_SLV_DC1_INGRESS_CLK" "per , ""IMAGING_LPCG_PIXEL_LINK_SLAVE_DC,IMAGING__LPCG_PIXEL_LINK_SLV_DC1_INGRESS_CLK"""
|
|
)
|
|
menuitem "IMAGING__LPCG_PIXEL_LINK_SLV_HDMI_IN_INGRESS_CLK" "per , ""IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN"""
|
|
popup "INT_MUX (INTMUX)"
|
|
(
|
|
menuitem "CM4_0__INTMUX" "per , ""INT_MUX (INTMUX),CM4_0__INTMUX"""
|
|
menuitem "CM4_1__INTMUX" "per , ""INT_MUX (INTMUX),CM4_1__INTMUX"""
|
|
menuitem "SCU__INTMUX" "per , ""INT_MUX (INTMUX),SCU__INTMUX"""
|
|
)
|
|
menuitem "IOMUXD" "per , ""IOMUXD"""
|
|
popup "ISI_REGS (ISI Memory Map)"
|
|
(
|
|
menuitem "IMAGING__ISI0" "per , ""ISI_REGS (ISI Memory Map),IMAGING__ISI0"""
|
|
menuitem "IMAGING__ISI1" "per , ""ISI_REGS (ISI Memory Map),IMAGING__ISI1"""
|
|
menuitem "IMAGING__ISI2" "per , ""ISI_REGS (ISI Memory Map),IMAGING__ISI2"""
|
|
menuitem "IMAGING__ISI3" "per , ""ISI_REGS (ISI Memory Map),IMAGING__ISI3"""
|
|
menuitem "IMAGING__ISI4" "per , ""ISI_REGS (ISI Memory Map),IMAGING__ISI4"""
|
|
menuitem "IMAGING__ISI5" "per , ""ISI_REGS (ISI Memory Map),IMAGING__ISI5"""
|
|
menuitem "IMAGING__ISI6" "per , ""ISI_REGS (ISI Memory Map),IMAGING__ISI6"""
|
|
menuitem "IMAGING__ISI7" "per , ""ISI_REGS (ISI Memory Map),IMAGING__ISI7"""
|
|
)
|
|
menuitem "LSIO__KPP" "per , ""KPP"""
|
|
popup "LPI2C"
|
|
(
|
|
menuitem "CM4_0__LPI2C" "per , ""LPI2C,CM4_0__LPI2C"""
|
|
menuitem "CM4_1__LPI2C" "per , ""LPI2C,CM4_1__LPI2C"""
|
|
menuitem "DI_HDMI__LPI2C" "per , ""LPI2C,DI_HDMI__LPI2C"""
|
|
menuitem "DI_LVDS_0__LPI2C0" "per , ""LPI2C,DI_LVDS_0__LPI2C0"""
|
|
menuitem "DI_LVDS_0__LPI2C1" "per , ""LPI2C,DI_LVDS_0__LPI2C1"""
|
|
menuitem "DI_LVDS_1__LPI2C0" "per , ""LPI2C,DI_LVDS_1__LPI2C0"""
|
|
menuitem "DI_LVDS_1__LPI2C1" "per , ""LPI2C,DI_LVDS_1__LPI2C1"""
|
|
menuitem "DI_MIPI_0__LPI2C0" "per , ""LPI2C,DI_MIPI_0__LPI2C0"""
|
|
menuitem "DI_MIPI_0__LPI2C1" "per , ""LPI2C,DI_MIPI_0__LPI2C1"""
|
|
menuitem "DI_MIPI_1__LPI2C0" "per , ""LPI2C,DI_MIPI_1__LPI2C0"""
|
|
menuitem "DI_MIPI_1__LPI2C1" "per , ""LPI2C,DI_MIPI_1__LPI2C1"""
|
|
menuitem "DMA__LPI2C0" "per , ""LPI2C,DMA__LPI2C0"""
|
|
menuitem "DMA__LPI2C1" "per , ""LPI2C,DMA__LPI2C1"""
|
|
menuitem "DMA__LPI2C2" "per , ""LPI2C,DMA__LPI2C2"""
|
|
menuitem "DMA__LPI2C3" "per , ""LPI2C,DMA__LPI2C3"""
|
|
menuitem "DMA__LPI2C4" "per , ""LPI2C,DMA__LPI2C4"""
|
|
menuitem "MIPI_CSI_0__LPI2C" "per , ""LPI2C,MIPI_CSI_0__LPI2C"""
|
|
menuitem "MIPI_CSI_1__LPI2C" "per , ""LPI2C,MIPI_CSI_1__LPI2C"""
|
|
menuitem "RX_HDMI__LPI2C" "per , ""LPI2C,RX_HDMI__LPI2C"""
|
|
menuitem "SCU__LPI2C" "per , ""LPI2C,SCU__LPI2C"""
|
|
)
|
|
popup "LPSPI"
|
|
(
|
|
menuitem "DMA__LPSPI0" "per , ""LPSPI,DMA__LPSPI0"""
|
|
menuitem "DMA__LPSPI1" "per , ""LPSPI,DMA__LPSPI1"""
|
|
menuitem "DMA__LPSPI2" "per , ""LPSPI,DMA__LPSPI2"""
|
|
menuitem "DMA__LPSPI3" "per , ""LPSPI,DMA__LPSPI3"""
|
|
)
|
|
popup "LPTPM (TPM)"
|
|
(
|
|
menuitem "CM4_0__TPM" "per , ""LPTPM (TPM),CM4_0__TPM"""
|
|
menuitem "CM4_1__TPM" "per , ""LPTPM (TPM),CM4_1__TPM"""
|
|
menuitem "SCU__TPM" "per , ""LPTPM (TPM),SCU__TPM"""
|
|
)
|
|
popup "LPUART"
|
|
(
|
|
menuitem "CM4_0__LPUART" "per , ""LPUART,CM4_0__LPUART"""
|
|
menuitem "CM4_1__LPUART" "per , ""LPUART,CM4_1__LPUART"""
|
|
menuitem "DMA__LPUART0" "per , ""LPUART,DMA__LPUART0"""
|
|
menuitem "DMA__LPUART1" "per , ""LPUART,DMA__LPUART1"""
|
|
menuitem "DMA__LPUART2" "per , ""LPUART,DMA__LPUART2"""
|
|
menuitem "DMA__LPUART3" "per , ""LPUART,DMA__LPUART3"""
|
|
menuitem "DMA__LPUART4" "per , ""LPUART,DMA__LPUART4"""
|
|
menuitem "SCU__LPUART" "per , ""LPUART,SCU__LPUART"""
|
|
)
|
|
popup "LSIO_LPCG_GPIO"
|
|
(
|
|
menuitem "LSIO__LPCG_GPIO0" "per , ""LSIO_LPCG_GPIO,LSIO__LPCG_GPIO0"""
|
|
menuitem "LSIO__LPCG_GPIO1" "per , ""LSIO_LPCG_GPIO,LSIO__LPCG_GPIO1"""
|
|
menuitem "LSIO__LPCG_GPIO2" "per , ""LSIO_LPCG_GPIO,LSIO__LPCG_GPIO2"""
|
|
menuitem "LSIO__LPCG_GPIO3" "per , ""LSIO_LPCG_GPIO,LSIO__LPCG_GPIO3"""
|
|
menuitem "LSIO__LPCG_GPIO4" "per , ""LSIO_LPCG_GPIO,LSIO__LPCG_GPIO4"""
|
|
menuitem "LSIO__LPCG_GPIO5" "per , ""LSIO_LPCG_GPIO,LSIO__LPCG_GPIO5"""
|
|
menuitem "LSIO__LPCG_GPIO6" "per , ""LSIO_LPCG_GPIO,LSIO__LPCG_GPIO6"""
|
|
menuitem "LSIO__LPCG_GPIO7" "per , ""LSIO_LPCG_GPIO,LSIO__LPCG_GPIO7"""
|
|
)
|
|
popup "LSIO_LPCG_GPT"
|
|
(
|
|
menuitem "LSIO__LPCG_GPT0" "per , ""LSIO_LPCG_GPT,LSIO__LPCG_GPT0"""
|
|
menuitem "LSIO__LPCG_GPT1" "per , ""LSIO_LPCG_GPT,LSIO__LPCG_GPT1"""
|
|
menuitem "LSIO__LPCG_GPT2" "per , ""LSIO_LPCG_GPT,LSIO__LPCG_GPT2"""
|
|
menuitem "LSIO__LPCG_GPT3" "per , ""LSIO_LPCG_GPT,LSIO__LPCG_GPT3"""
|
|
menuitem "LSIO__LPCG_GPT4" "per , ""LSIO_LPCG_GPT,LSIO__LPCG_GPT4"""
|
|
)
|
|
menuitem "LSIO__LPCG_KPP" "per , ""LSIO_LPCG_KPP"""
|
|
menuitem "LSIO__LPCG_MU10_DSP" "per , ""LSIO_LPCG_MU10_DSP"""
|
|
menuitem "LSIO__LPCG_MU10_MCU" "per , ""LSIO_LPCG_MU10_MCU"""
|
|
menuitem "LSIO__LPCG_MU11_DSP" "per , ""LSIO_LPCG_MU11_DSP"""
|
|
menuitem "LSIO__LPCG_MU11_MCU" "per , ""LSIO_LPCG_MU11_MCU"""
|
|
menuitem "LSIO__LPCG_MU12_DSP" "per , ""LSIO_LPCG_MU12_DSP"""
|
|
menuitem "LSIO__LPCG_MU12_MCU" "per , ""LSIO_LPCG_MU12_MCU"""
|
|
menuitem "LSIO__LPCG_MU13_DSP" "per , ""LSIO_LPCG_MU13_DSP"""
|
|
menuitem "LSIO__LPCG_MU13_MCU" "per , ""LSIO_LPCG_MU13_MCU"""
|
|
menuitem "LSIO__LPCG_MU5_DSP" "per , ""LSIO_LPCG_MU5_DSP"""
|
|
menuitem "LSIO__LPCG_MU5_MCU" "per , ""LSIO_LPCG_MU5_MCU"""
|
|
menuitem "LSIO__LPCG_MU6_DSP" "per , ""LSIO_LPCG_MU6_DSP"""
|
|
menuitem "LSIO__LPCG_MU6_MCU" "per , ""LSIO_LPCG_MU6_MCU"""
|
|
menuitem "LSIO__LPCG_MU7_DSP" "per , ""LSIO_LPCG_MU7_DSP"""
|
|
menuitem "LSIO__LPCG_MU7_MCU" "per , ""LSIO_LPCG_MU7_MCU"""
|
|
menuitem "LSIO__LPCG_MU8_DSP" "per , ""LSIO_LPCG_MU8_DSP"""
|
|
menuitem "LSIO__LPCG_MU8_MCU" "per , ""LSIO_LPCG_MU8_MCU"""
|
|
menuitem "LSIO__LPCG_MU9_DSP" "per , ""LSIO_LPCG_MU9_DSP"""
|
|
menuitem "LSIO__LPCG_MU9_MCU" "per , ""LSIO_LPCG_MU9_MCU"""
|
|
menuitem "LSIO__LPCG_OCRAM" "per , ""LSIO_LPCG_OCRAM"""
|
|
popup "LSIO_LPCG_PWM"
|
|
(
|
|
menuitem "LSIO__LPCG_PWM0" "per , ""LSIO_LPCG_PWM,LSIO__LPCG_PWM0"""
|
|
menuitem "LSIO__LPCG_PWM1" "per , ""LSIO_LPCG_PWM,LSIO__LPCG_PWM1"""
|
|
menuitem "LSIO__LPCG_PWM2" "per , ""LSIO_LPCG_PWM,LSIO__LPCG_PWM2"""
|
|
menuitem "LSIO__LPCG_PWM3" "per , ""LSIO_LPCG_PWM,LSIO__LPCG_PWM3"""
|
|
menuitem "LSIO__LPCG_PWM4" "per , ""LSIO_LPCG_PWM,LSIO__LPCG_PWM4"""
|
|
menuitem "LSIO__LPCG_PWM5" "per , ""LSIO_LPCG_PWM,LSIO__LPCG_PWM5"""
|
|
menuitem "LSIO__LPCG_PWM6" "per , ""LSIO_LPCG_PWM,LSIO__LPCG_PWM6"""
|
|
menuitem "LSIO__LPCG_PWM7" "per , ""LSIO_LPCG_PWM,LSIO__LPCG_PWM7"""
|
|
)
|
|
popup "LSIO_LPCG_QSPI"
|
|
(
|
|
menuitem "LSIO__LPCG_QSPI0" "per , ""LSIO_LPCG_QSPI,LSIO__LPCG_QSPI0"""
|
|
menuitem "LSIO__LPCG_QSPI1" "per , ""LSIO_LPCG_QSPI,LSIO__LPCG_QSPI1"""
|
|
)
|
|
popup "MIPI_CSI_LPCG"
|
|
(
|
|
menuitem "MIPI_CSI_0__LPCG_CLK" "per , ""MIPI_CSI_LPCG,MIPI_CSI_0__LPCG_CLK"""
|
|
menuitem "MIPI_CSI_1__LPCG_CLK" "per , ""MIPI_CSI_LPCG,MIPI_CSI_1__LPCG_CLK"""
|
|
)
|
|
if (cpuis("IMX8*-CM4-0")||cpuis("IMX8*-CM4-1"))
|
|
(
|
|
menuitem "MMCAU" "per , ""MMCAU_APB3 (CAU),MMCAU"""
|
|
)
|
|
popup "PWM (Pulse-Width Modulator)"
|
|
(
|
|
menuitem "DI_HDMI__PWM" "per , ""PWM (Pulse-Width Modulator),DI_HDMI__PWM"""
|
|
menuitem "DI_LVDS_0__PWM" "per , ""PWM (Pulse-Width Modulator),DI_LVDS_0__PWM"""
|
|
menuitem "DI_LVDS_1__PWM" "per , ""PWM (Pulse-Width Modulator),DI_LVDS_1__PWM"""
|
|
menuitem "DI_MIPI_0__PWM" "per , ""PWM (Pulse-Width Modulator),DI_MIPI_0__PWM"""
|
|
menuitem "DI_MIPI_1__PWM" "per , ""PWM (Pulse-Width Modulator),DI_MIPI_1__PWM"""
|
|
menuitem "LSIO__PWM0" "per , ""PWM (Pulse-Width Modulator),LSIO__PWM0"""
|
|
menuitem "LSIO__PWM1" "per , ""PWM (Pulse-Width Modulator),LSIO__PWM1"""
|
|
menuitem "LSIO__PWM2" "per , ""PWM (Pulse-Width Modulator),LSIO__PWM2"""
|
|
menuitem "LSIO__PWM3" "per , ""PWM (Pulse-Width Modulator),LSIO__PWM3"""
|
|
menuitem "LSIO__PWM4" "per , ""PWM (Pulse-Width Modulator),LSIO__PWM4"""
|
|
menuitem "LSIO__PWM5" "per , ""PWM (Pulse-Width Modulator),LSIO__PWM5"""
|
|
menuitem "LSIO__PWM6" "per , ""PWM (Pulse-Width Modulator),LSIO__PWM6"""
|
|
menuitem "LSIO__PWM7" "per , ""PWM (Pulse-Width Modulator),LSIO__PWM7"""
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menuitem "MIPI_CSI_0__PWM" "per , ""PWM (Pulse-Width Modulator),MIPI_CSI_0__PWM"""
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menuitem "MIPI_CSI_1__PWM" "per , ""PWM (Pulse-Width Modulator),MIPI_CSI_1__PWM"""
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menuitem "RX_HDMI__PWM" "per , ""PWM (Pulse-Width Modulator),RX_HDMI__PWM"""
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)
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popup "RGPIO2P (GPIO)"
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(
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menuitem "CM4_0__RGPIO" "per , ""RGPIO2P (GPIO),CM4_0__RGPIO"""
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menuitem "CM4_1__RGPIO" "per , ""RGPIO2P (GPIO),CM4_1__RGPIO"""
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menuitem "SCU__RGPIO" "per , ""RGPIO2P (GPIO),SCU__RGPIO"""
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)
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popup "ROMCP (ROMC)"
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(
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menuitem "LSIO__ROMCP" "per , ""ROMCP (ROMC),LSIO__ROMCP"""
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menuitem "SCU__ROMCP" "per , ""ROMCP (ROMC),SCU__ROMCP"""
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)
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menuitem "RX_HDMI__LPCG_GPIO_IPG_CLK_S" "per , ""RX_HDMI_LPCG"""
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popup "SAI (I2S)"
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(
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menuitem "AUDIO__SAI0" "per , ""SAI (I2S),AUDIO__SAI0"""
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menuitem "AUDIO__SAI1" "per , ""SAI (I2S),AUDIO__SAI1"""
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menuitem "AUDIO__SAI2" "per , ""SAI (I2S),AUDIO__SAI2"""
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menuitem "AUDIO__SAI3" "per , ""SAI (I2S),AUDIO__SAI3"""
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menuitem "AUDIO__SAI6" "per , ""SAI (I2S),AUDIO__SAI6"""
|
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menuitem "AUDIO__SAI7" "per , ""SAI (I2S),AUDIO__SAI7"""
|
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menuitem "AUDIO__SAI_HDMIRX0" "per , ""SAI (I2S),AUDIO__SAI_HDMIRX0"""
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|
menuitem "AUDIO__SAI_HDMITX0" "per , ""SAI (I2S),AUDIO__SAI_HDMITX0"""
|
|
)
|
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menuitem "HSIO__SATA" "per , ""SATAHOST"""
|
|
menuitem "SCU__LPCG_LPI2C" "per , ""SCU_LPCG_LPI2C"""
|
|
menuitem "SCU__LPCG_LPIT" "per , ""SCU_LPCG_LPIT"""
|
|
menuitem "SCU__LPCG_LPUART" "per , ""SCU_LPCG_LPUART"""
|
|
menuitem "SCU__LPCG_MMCAU_HCLK" "per , ""SCU_LPCG_MMCAU_HCLK"""
|
|
menuitem "SCU__LPCG_TCMC_HCLK" "per , ""SCU_LPCG_TCMC_HCLK"""
|
|
menuitem "SCU__LPCG_TPM" "per , ""SCU_LPCG_TPM"""
|
|
popup "SEMA42_IPS (sema42_ips)"
|
|
(
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|
menuitem "CM4_0__SEMA42" "per , ""SEMA42_IPS (sema42_ips),CM4_0__SEMA42"""
|
|
menuitem "CM4_1__SEMA42" "per , ""SEMA42_IPS (sema42_ips),CM4_1__SEMA42"""
|
|
menuitem "SCU__SEMA42" "per , ""SEMA42_IPS (sema42_ips),SCU__SEMA42"""
|
|
)
|
|
popup "SPDIF (Sony/Philips Digital Interface)"
|
|
(
|
|
menuitem "AUDIO__SPDIF0" "per , ""SPDIF (Sony/Philips Digital Interface),AUDIO__SPDIF0"""
|
|
menuitem "AUDIO__SPDIF1" "per , ""SPDIF (Sony/Philips Digital Interface),AUDIO__SPDIF1"""
|
|
)
|
|
popup "SPP_DMA3 (DMA MP)"
|
|
(
|
|
menuitem "AUDIO__EDMA0" "per , ""SPP_DMA3 (DMA MP),AUDIO__EDMA0"""
|
|
menuitem "AUDIO__EDMA1" "per , ""SPP_DMA3 (DMA MP),AUDIO__EDMA1"""
|
|
menuitem "CONNECTIVITY__EDMA" "per , ""SPP_DMA3 (DMA MP),CONNECTIVITY__EDMA"""
|
|
menuitem "DMA__EDMA0" "per , ""SPP_DMA3 (DMA MP),DMA__EDMA0"""
|
|
menuitem "DMA__EDMA1" "per , ""SPP_DMA3 (DMA MP),DMA__EDMA1"""
|
|
)
|
|
menuitem "AUDIO__ACM" "per , ""SS_AUDIO__ACM (ACM control IPS slave)"""
|
|
menuitem "AUDIO__MQS_REGS" "per , ""SS_AUDIO__MQS_REGS (MQS control register IPS slave)"""
|
|
popup "USDHC (Ultra Secured Digital Host Controller)"
|
|
(
|
|
menuitem "CONNECTIVITY__USDHC0" "per , ""USDHC (Ultra Secured Digital Host Controller),CONNECTIVITY__USDHC0"""
|
|
menuitem "CONNECTIVITY__USDHC1" "per , ""USDHC (Ultra Secured Digital Host Controller),CONNECTIVITY__USDHC1"""
|
|
menuitem "CONNECTIVITY__USDHC2" "per , ""USDHC (Ultra Secured Digital Host Controller),CONNECTIVITY__USDHC2"""
|
|
)
|
|
menuitem "VPU__LPCG_AVSD" "per , ""VPU_LPCG_AVSD"""
|
|
popup "VPU_LPCG_ENC"
|
|
(
|
|
menuitem "VPU__LPCG_ENC0" "per , ""VPU_LPCG_ENC,VPU__LPCG_ENC0"""
|
|
menuitem "VPU__LPCG_ENC1" "per , ""VPU_LPCG_ENC,VPU__LPCG_ENC1"""
|
|
)
|
|
menuitem "VPU__LPCG_H264" "per , ""VPU_LPCG_H264"""
|
|
menuitem "VPU__LPCG_HIFI4" "per , ""VPU_LPCG_HIFI4"""
|
|
menuitem "VPU__LPCG_MFD" "per , ""VPU_LPCG_MFD"""
|
|
menuitem "VPU__LPCG_MPGD" "per , ""VPU_LPCG_MPGD"""
|
|
menuitem "VPU__LPCG_OCRAM" "per , ""VPU_LPCG_OCRAM"""
|
|
menuitem "VPU__LPCG_VC1D" "per , ""VPU_LPCG_VC1D"""
|
|
menuitem "VPU__LPCG_XUVI" "per , ""VPU_LPCG_XUVI"""
|
|
)
|
|
)
|