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Gen4_R-Car_Trace32/2_Trunk/menimx8mm.men
woody d411edd9b4 add Trace32 File
2025-10-14 09:52:32 +09:00

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; --------------------------------------------------------------------------------
; @Title: IMX8MM Specific Menu
; @Props: Released
; @Author: BGI, KWI, RSA
; @Changelog: 2019-04-11 BGI
; 2019-08-28 KWI
; 2022-02-21 RSA
; @Manufacturer: NXP - NXP Semiconductors
; @Core: Cortex-A53, Cortex-M4F
; @Chip: IMX8MMQ-CM4, IMX8MMQ
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: menimx8mm.men 16339 2023-07-03 13:30:14Z pegold $
add
menu
(
IF SOFTWARE.BUILD.BASE()>=69655.
(
popup "&CPU"
(
separator
IF CPU.FEATURE(MMU)
(
popup "[:mmu]MMU"
(
menuitem "[:mmureg]MMU Control" "MMU.view"
separator
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
separator
IF CPU.FEATURE(ITLBDUMP)
(
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
)
IF CPU.FEATURE(DTLBDUMP)
(
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
)
IF CPU.FEATURE(TLB0DUMP)
(
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
)
IF CPU.FEATURE(TLB1DUMP)
(
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
)
)
)
IF COMPonent.AVAILable("SMMU")
(
popup "[:mmu]SMMU"
(
menuitem "[:chip]SMMU1 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU1 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.StreamMapTable &(name)
)
IF COMPonent.AVAILable("SMMU2")
(
separator
menuitem "[:chip]SMMU2 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU2 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU3")
(
separator
menuitem "[:chip]SMMU3 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU3 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU4")
(
separator
menuitem "[:chip]SMMU4 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU4 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU5")
(
separator
menuitem "[:chip]SMMU5 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU5 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU6")
(
separator
menuitem "[:chip]SMMU6 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU6 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.StreamMapTable &(name)
)
)
)
)
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
(
popup "[:cache]Cache"
(
IF CPU.FEATURE(L1ICACHEDUMP)
(
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
menuitem "[:cache]ICACHE List" "CACHE.List IC"
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
)
IF CPU.FEATURE(L1DCACHEDUMP)
(
separator
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
menuitem "[:cache]DCACHE List" "CACHE.List DC"
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
)
IF CPU.FEATURE(L2CACHEDUMP)
(
separator
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
)
)
)
)
popup "&Trace"
(
separator
IF COMPonent.AVAILable("ITM")
(
popup "ITM"
(
default
menuitem "[:oconfig]ITM settings..." "ITM.state"
separator
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
)
)
IF COMPonent.AVAILable("STM")
(
popup "STM"
(
default
menuitem "[:oconfig]STM settings..." "STM.state"
separator
menuitem "[:alist]STMTrace List" "STMTrace.List"
)
)
IF COMPonent.AVAILable("HTM")
(
popup "HTM"
(
default
menuitem "[:oconfig]HTM settings..." "HTM.state"
separator
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
)
)
IF COMPonent.AVAILable("TPIU")
(
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
)
IF COMPonent.AVAILable("ETR")
(
menuitem "[:oconfig]ETR settings..."
(
PRIVATE &pdd
&pdd=OS.PDD()
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
)
)
)
popup "&Misc"
(
popup "Tools"
(
IF CPUIS64BIT()||CPU.FEATURE("SPR")
(
menuitem "ARM System Register Converter"
(
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
)
)
IF CPU.FEATURE("C15")
(
menuitem "ARM Coprocessor Converter"
(
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
)
)
)
)
popup "&Perf"
(
IF CPU.FEATURE(BMC)
(
before "Reset"
menuitem "[:bmc]Benchmark Counters" "BMC.state"
before "Reset"
separator
)
)
)
popup "Peripherals"
(
if (CORENAME()=="CORTEXM4F")
(
popup "[:chip]Core Registers (Cortex-M4F)"
(
menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M4F),System Control"""
menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M4F),Memory Protection Unit"""
menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M4F),Nested Vectored Interrupt Controller"""
menuitem "[:chip]FPU;Floating-point Unit" "per , ""Core Registers (Cortex-M4F),Floating-point Unit"""
popup "[:chip]Debug"
(
menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M4F),Debug,Core Debug"""
menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M4F),Debug,Flash Patch and Breakpoint Unit (FPB)"""
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M4F),Debug,Data Watchpoint and Trace Unit (DWT)"""
)
)
)
else
(
popup "[:chip]Core Registers (Cortex-A53)"
(
menuitem "[:chip]ID Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,ID Registers"""
menuitem "[:chip]System Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,System Control and Configuration"""
menuitem "[:chip]Memory Management Unit[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Memory Management Unit"""
menuitem "[:chip]Virtualization Extensions[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Virtualization Extensions"""
menuitem "[:chip]Cache Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Cache Control and Configuration"""
menuitem "[:chip]System Performance Monitor[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,System Performance Monitor"""
menuitem "[:chip]System Timer Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,System Timer Registers"""
menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Generic Interrupt Controller CPU Interface"""
separator
menuitem "[:chip]Debug Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Debug Registers"""
separator
menuitem "[:chip]Breakpoint Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Breakpoint Registers"""
menuitem "[:chip]Watchpoint Control Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Watchpoint Control Registers"""
separator
menuitem "[:chip]ID Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,ID Registers"""
menuitem "[:chip]System Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,System Control and Configuration"""
menuitem "[:chip]Memory Management Unit[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Memory Management Unit"""
menuitem "[:chip]Virtualization Extensions[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Virtualization Extensions"""
menuitem "[:chip]Cache Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Cache Control and Configuration"""
menuitem "[:chip]System Performance Monitor[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,System Performance Monitor"""
menuitem "[:chip]System Timer Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,System Timer Registers"""
menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Generic Interrupt Controller CPU Interface"""
separator
menuitem "[:chip]Debug Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Debug Registers"""
separator
menuitem "[:chip]Breakpoint Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Breakpoint Registers"""
menuitem "[:chip]Watchpoint Control Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Watchpoint Control Registers"""
separator
menuitem "[:chip]Interrupt Controller (GIC-500)" "per , ""Core Registers (Cortex-A53),Interrupt Controller (GIC-500)"""
)
)
separator
menuitem "AIPSTZ" "per , ""AIPSTZ"""
popup "I2S"
(
menuitem "I2S1" "per , ""I2S,I2S1"""
menuitem "I2S2" "per , ""I2S,I2S2"""
menuitem "I2S3" "per , ""I2S,I2S3"""
menuitem "I2S5" "per , ""I2S,I2S5"""
menuitem "I2S6" "per , ""I2S,I2S6"""
)
menuitem "PDM" "per , ""PDM"""
popup "SPDIF"
(
menuitem "SPDIF1" "per , ""SPDIF,SPDIF1"""
menuitem "SPDIF2" "per , ""SPDIF,SPDIF2"""
)
popup "GPIO"
(
menuitem "GPIO1" "per , ""GPIO,GPIO1"""
menuitem "GPIO2" "per , ""GPIO,GPIO2"""
menuitem "GPIO3" "per , ""GPIO,GPIO3"""
menuitem "GPIO4" "per , ""GPIO,GPIO4"""
menuitem "GPIO5" "per , ""GPIO,GPIO5"""
)
menuitem "TMU" "per , ""TMU"""
menuitem "XTALOSC" "per , ""XTALOSC"""
popup "WDOG"
(
menuitem "WDOG1" "per , ""WDOG,WDOG1"""
menuitem "WDOG2" "per , ""WDOG,WDOG2"""
menuitem "WDOG3" "per , ""WDOG,WDOG3"""
)
popup "GPT"
(
menuitem "GPT1" "per , ""GPT,GPT1"""
menuitem "GPT2" "per , ""GPT,GPT2"""
menuitem "GPT3" "per , ""GPT,GPT3"""
menuitem "GPT6" "per , ""GPT,GPT6"""
menuitem "GPT5" "per , ""GPT,GPT5"""
menuitem "GPT4" "per , ""GPT,GPT4"""
)
menuitem "IOMUXC" "per , ""IOMUXC"""
menuitem "IOMUXC_GPR" "per , ""IOMUXC_GPR"""
menuitem "OCOTP" "per , ""OCOTP"""
menuitem "CCM_ANALOG" "per , ""CCM_ANALOG"""
menuitem "SNVS" "per , ""SNVS"""
menuitem "CCM" "per , ""CCM"""
menuitem "SRC" "per , ""SRC"""
menuitem "GPC" "per , ""GPC"""
menuitem "GPC_PGC" "per , ""GPC_PGC"""
popup "RDC_SEMAPHORE"
(
menuitem "RDC_SEMAPHORE1" "per , ""RDC_SEMAPHORE,RDC_SEMAPHORE1"""
menuitem "RDC_SEMAPHORE2" "per , ""RDC_SEMAPHORE,RDC_SEMAPHORE2"""
)
menuitem "RDC" "per , ""RDC"""
popup "PWM"
(
menuitem "PWM1" "per , ""PWM,PWM1"""
menuitem "PWM2" "per , ""PWM,PWM2"""
menuitem "PWM3" "per , ""PWM,PWM3"""
menuitem "PWM4" "per , ""PWM,PWM4"""
)
popup "ECSPI"
(
menuitem "ECSPI1" "per , ""ECSPI,ECSPI1"""
menuitem "ECSPI2" "per , ""ECSPI,ECSPI2"""
menuitem "ECSPI3" "per , ""ECSPI,ECSPI3"""
)
popup "UART"
(
menuitem "UART1" "per , ""UART,UART1"""
menuitem "UART3" "per , ""UART,UART3"""
menuitem "UART2" "per , ""UART,UART2"""
menuitem "UART4" "per , ""UART,UART4"""
)
popup "SPBA"
(
menuitem "SPBA1" "per , ""SPBA,SPBA1"""
menuitem "SPBA2" "per , ""SPBA,SPBA2"""
)
popup "I2C"
(
menuitem "I2C1" "per , ""I2C,I2C1"""
menuitem "I2C2" "per , ""I2C,I2C2"""
menuitem "I2C3" "per , ""I2C,I2C3"""
menuitem "I2C4" "per , ""I2C,I2C4"""
)
menuitem "MUB" "per , ""MUB"""
menuitem "SEMA4" "per , ""SEMA4"""
popup "USDHC"
(
menuitem "USDHC1" "per , ""USDHC,USDHC1"""
menuitem "USDHC2" "per , ""USDHC,USDHC2"""
menuitem "USDHC3" "per , ""USDHC,USDHC3"""
)
menuitem "FLEXSPI" "per , ""FLEXSPI"""
popup "SDMAARM"
(
menuitem "SDMAARM1" "per , ""SDMAARM,SDMAARM1"""
menuitem "SDMAARM3" "per , ""SDMAARM,SDMAARM3"""
menuitem "SDMAARM2" "per , ""SDMAARM,SDMAARM2"""
)
menuitem "ENET" "per , ""ENET"""
menuitem "LCDIF" "per , ""LCDIF"""
menuitem "MIPI_DSI" "per , ""MIPI_DSI"""
menuitem "CSI" "per , ""CSI"""
menuitem "MIPI_CSI" "per , ""MIPI_CSI"""
menuitem "USBNC" "per , ""USBNC"""
popup "USB"
(
menuitem "USB_OTG1" "per , ""USB,USB_OTG1"""
menuitem "USB_OTG2" "per , ""USB,USB_OTG2"""
)
menuitem "PCIE_PHY" "per , ""PCIE_PHY"""
menuitem "APBH" "per , ""APBH"""
menuitem "GPMI" "per , ""GPMI"""
menuitem "BCH" "per , ""BCH"""
menuitem "PCIE1" "per , ""PCIE"""
menuitem "VPU_G1" "per , ""VPU_G1"""
menuitem "VPU_G1_H264" "per , ""VPU_G1_H264"""
menuitem "VPU_G1_VP7_VP8" "per , ""VPU_G1_VP7_VP8"""
menuitem "VPU_G1_VP8" "per , ""VPU_G1_VP8"""
menuitem "VPU_G2" "per , ""VPU_G2"""
menuitem "VPU_H1" "per , ""VPU_H1"""
menuitem "VPU_H1_H264" "per , ""VPU_H1_H264"""
menuitem "VPU_H1_VP8" "per , ""VPU_H1_VP8"""
popup "DWC_DDRPHYA_ANIB"
(
menuitem "DWC_DDRPHYA_ANIB0" "per , ""DWC_DDRPHYA_ANIB,DWC_DDRPHYA_ANIB0"""
menuitem "DWC_DDRPHYA_ANIB1" "per , ""DWC_DDRPHYA_ANIB,DWC_DDRPHYA_ANIB1"""
menuitem "DWC_DDRPHYA_ANIB2" "per , ""DWC_DDRPHYA_ANIB,DWC_DDRPHYA_ANIB2"""
menuitem "DWC_DDRPHYA_ANIB3" "per , ""DWC_DDRPHYA_ANIB,DWC_DDRPHYA_ANIB3"""
menuitem "DWC_DDRPHYA_ANIB4" "per , ""DWC_DDRPHYA_ANIB,DWC_DDRPHYA_ANIB4"""
menuitem "DWC_DDRPHYA_ANIB5" "per , ""DWC_DDRPHYA_ANIB,DWC_DDRPHYA_ANIB5"""
menuitem "DWC_DDRPHYA_ANIB6" "per , ""DWC_DDRPHYA_ANIB,DWC_DDRPHYA_ANIB6"""
menuitem "DWC_DDRPHYA_ANIB7" "per , ""DWC_DDRPHYA_ANIB,DWC_DDRPHYA_ANIB7"""
menuitem "DWC_DDRPHYA_ANIB8" "per , ""DWC_DDRPHYA_ANIB,DWC_DDRPHYA_ANIB8"""
menuitem "DWC_DDRPHYA_ANIB9" "per , ""DWC_DDRPHYA_ANIB,DWC_DDRPHYA_ANIB9"""
)
popup "DWC_DDRPHYA_DBYTE"
(
menuitem "DWC_DDRPHYA_DBYTE0" "per , ""DWC_DDRPHYA_DBYTE,DWC_DDRPHYA_DBYTE0"""
menuitem "DWC_DDRPHYA_DBYTE1" "per , ""DWC_DDRPHYA_DBYTE,DWC_DDRPHYA_DBYTE1"""
menuitem "DWC_DDRPHYA_DBYTE2" "per , ""DWC_DDRPHYA_DBYTE,DWC_DDRPHYA_DBYTE2"""
menuitem "DWC_DDRPHYA_DBYTE3" "per , ""DWC_DDRPHYA_DBYTE,DWC_DDRPHYA_DBYTE3"""
)
menuitem "DWC_DDRPHYA_MASTER0" "per , ""DWC_DDRPHYA_MASTER"""
menuitem "DWC_DDRPHYA_INITENG0" "per , ""DWC_DDRPHYA_INITENG"""
menuitem "DWC_DDRPHYA_DRTUB0" "per , ""DWC_DDRPHYA_DRTUB"""
menuitem "DWC_DDRPHYA_APBONLY0" "per , ""DWC_DDRPHYA_APBONLY"""
menuitem "DDRC" "per , ""DDRC"""
if cpuis("IMX8MMQ-CM4")
(
menuitem "MCM" "per , ""MCM,MCM"""
menuitem "LMEM" "per , ""LMEM,LMEM"""
)
)
)
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