505 lines
22 KiB
Plaintext
505 lines
22 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: IMX8M Specific Menu
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; @Props: Released
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; @Author: BCA
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; @Changelog: 2018-02-24 BCA
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; @Manufacturer: NXP - NXP Semiconductors
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; @Core: Cortex-A53, Cortex-M4F
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; @Chip: IMX8MQ, IMX8MQ-CM4
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; @Copyright: (C) 1989-2018 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: menimx8m.men 16339 2023-07-03 13:30:14Z pegold $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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if (CORENAME()=="CORTEXM4F")
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(
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popup "[:chip]Core Registers (Cortex-M4F)"
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(
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menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M4F),System Control"""
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menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M4F),Memory Protection Unit"""
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menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M4F),Nested Vectored Interrupt Controller"""
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menuitem "[:chip]FPU;Floating-point Unit" "per , ""Core Registers (Cortex-M4F),Floating-point Unit"""
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popup "[:chip]Debug"
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(
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menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M4F),Debug,Core Debug"""
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menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M4F),Debug,Flash Patch and Breakpoint Unit (FPB)"""
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menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M4F),Debug,Data Watchpoint and Trace Unit (DWT)"""
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)
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)
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)
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if (CORENAME()=="CORTEXA53")
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(
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popup "[:chip]Core Registers (Cortex-A53)"
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(
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menuitem "[:chip]ID Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,ID Registers"""
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menuitem "[:chip]System Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,System Control and Configuration"""
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menuitem "[:chip]Memory Management Unit[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Memory Management Unit"""
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menuitem "[:chip]Virtualization Extensions[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Virtualization Extensions"""
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menuitem "[:chip]Cache Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,System Performance Monitor"""
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menuitem "[:chip]System Timer Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,System Timer Registers"""
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menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Generic Interrupt Controller CPU Interface"""
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separator
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menuitem "[:chip]Debug Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Debug Registers"""
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separator
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menuitem "[:chip]Breakpoint Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Control Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Watchpoint Control Registers"""
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separator
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menuitem "[:chip]ID Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,ID Registers"""
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menuitem "[:chip]System Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,System Control and Configuration"""
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menuitem "[:chip]Memory Management Unit[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Memory Management Unit"""
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menuitem "[:chip]Virtualization Extensions[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Virtualization Extensions"""
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menuitem "[:chip]Cache Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,System Performance Monitor"""
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menuitem "[:chip]System Timer Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,System Timer Registers"""
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menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Generic Interrupt Controller CPU Interface"""
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separator
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menuitem "[:chip]Debug Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Debug Registers"""
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separator
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menuitem "[:chip]Breakpoint Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Control Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Watchpoint Control Registers"""
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separator
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menuitem "[:chip]Interrupt Controller (GIC-500)" "per , ""Core Registers (Cortex-A53),Interrupt Controller (GIC-500)"""
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)
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)
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separator
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popup "Security"
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(
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menuitem "RDC" "per , ""Security,RDC (Resources Domain Controller)"""
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popup "RDC_SEMA42"
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(
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menuitem "RDC_SEMAPHORE_1" "per , ""Security,RDC_SEMA42 (Resources Domain Controller Semaphore),RDC_SEMAPHORE_1"""
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menuitem "RDC_SEMAPHORE_2" "per , ""Security,RDC_SEMA42 (Resources Domain Controller Semaphore),RDC_SEMAPHORE_2"""
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)
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)
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popup "Arm platform and debug"
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(
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menuitem "LMEM" "per , ""ARM Platform and Debug,LMEM (Local Memory Controller)"""
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menuitem "MCM" "per , ""ARM Platform and Debug,MCM (Miscellaneous Control Module)"""
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popup "MU"
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(
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menuitem "MUA" "per , ""ARM Platform and Debug,MU (Messaging Unit),MUA (MU Processor A-side"""
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menuitem "MUB" "per , ""ARM Platform and Debug,MU (Messaging Unit),MUB (MU Processor B-side"""
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)
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menuitem "SEMA4" "per , ""ARM Platform and Debug,SEMA4 (Semaphore)"""
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menuitem "AIPSTZ" "per , ""ARM Platform and Debug,AIPSTZ (AHB to IP Bridge)"""
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popup "SPBA"
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(
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menuitem "Channel 2" "per , ""ARM Platform and Debug,SPBA (Shared Peripheral Bus Arbiter),Channel 2"""
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menuitem "Channel 1" "per , ""ARM Platform and Debug,SPBA (Shared Peripheral Bus Arbiter),Channel 1"""
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)
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menuitem "ROMPC" "per , ""ARM Platform and Debug,ROMPC (ROM Controller with Patch)"""
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popup "WDOG"
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(
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menuitem "Channel 1" "per , ""ARM Platform and Debug,WDOG (Watchdog Timer),Channel 1"""
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menuitem "Channel 2" "per , ""ARM Platform and Debug,WDOG (Watchdog Timer),Channel 2"""
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menuitem "Channel 3" "per , ""ARM Platform and Debug,WDOG (Watchdog Timer),Channel 3"""
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)
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menuitem "TZASC" "per , ""ARM Platform and Debug,TZASC"""
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)
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popup "Clocks and Power Management"
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(
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menuitem "CCM" "per , ""Clocks and Power Management,CCM (Clock Control Module)"""
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menuitem "CCMA" "per , ""Clocks and Power Management,CCMA (Clock Control Module Analog)"""
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menuitem "GPC" "per , ""Clocks and Power Management,GPC (General Power Controller)"""
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menuitem "GPC_PGC" "per , ""Clocks and Power Management,GPC_PGC (General Power Controller - Power Gating Controller)"""
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popup "XTALOSC"
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(
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menuitem "XTALOSC_OSC275" "per , ""Clocks and Power Management,XTALOSC (Crystal Oscillator),XTALOSC_OSC25M (25M Oscillator)"""
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menuitem "XTALOSC_OSC27M" "per , ""Clocks and Power Management,XTALOSC (Crystal Oscillator),XTALOSC_OSC27M (27M Oscillator)"""
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)
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menuitem "TMU" "per , ""Clocks and Power Management,TMU (Thermal Management Unit)"""
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)
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popup "SNVS/Reset/Fuse/Boot"
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(
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menuitem "OCOTP" "per , ""SNVS and Reset and Fuse and Boot,OCOTP (On-chip OTP Controller)"""
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menuitem "SNVS" "per , ""SNVS and Reset and Fuse and Boot,SNVS (Secure Non-Volatile Storage)"""
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menuitem "SRC" "per , ""SNVS and Reset and Fuse and Boot,SRC (System Reset Controller)"""
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)
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popup "SDMAARM"
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(
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menuitem "SDMAARM1" "per , ""SDMA (Smart DIrect Memory Access Controller),SDMAARM (Smart Direct Memory Access - Arm Platform),SDMAARM1"""
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menuitem "SDMAARM2" "per , ""SDMA (Smart DIrect Memory Access Controller),SDMAARM (Smart Direct Memory Access - Arm Platform),SDMAARM2"""
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)
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popup "Chip IO and Pinmux"
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(
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menuitem "IOMUXC_GPR" "per , ""Chip IO and Pinmux,IOMUXC_GPR (IOMUX Controller General Purpose Registers)"""
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menuitem "IOMUXC" "per , ""Chip IO and Pinmux,IOMUXC (IOMUX Controller)"""
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popup "GPIO"
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(
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menuitem "GPIO 1" "per , ""Chip IO and Pinmux,GPIO (General Purpose Input/Output),GPIO 1"""
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menuitem "GPIO 2" "per , ""Chip IO and Pinmux,GPIO (General Purpose Input/Output),GPIO 2"""
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menuitem "GPIO 3" "per , ""Chip IO and Pinmux,GPIO (General Purpose Input/Output),GPIO 3"""
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menuitem "GPIO 4" "per , ""Chip IO and Pinmux,GPIO (General Purpose Input/Output),GPIO 4"""
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menuitem "GPIO 5" "per , ""Chip IO and Pinmux,GPIO (General Purpose Input/Output),GPIO 5"""
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)
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)
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popup "External Memory"
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(
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menuitem "DDRC" "per , ""External Memory,DDRC (DDR Controller)"""
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menuitem "APBH" "per , ""External Memory,APBH (AHB-to-APBH Bridge with DMA)"""
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menuitem "BCH" "per , ""External Memory,BCH (62BIT Correcting ECC Accelrator)"""
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menuitem "GPMI" "per , ""External Memory,GPMI (General Purpose Media Interface)"""
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)
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popup "Mass Storage"
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(
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popup "ECSPI"
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(
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menuitem "ECSPI1" "per , ""Mass Storage,ECSPI (Enhanced Configurable SPI),ECSPI 1"""
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menuitem "ECSPI2" "per , ""Mass Storage,ECSPI (Enhanced Configurable SPI),ECSPI 2"""
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menuitem "ECSPI3" "per , ""Mass Storage,ECSPI (Enhanced Configurable SPI),ECSPI 3"""
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)
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menuitem "QuadSPI" "per , ""Mass Storage,QuadSPI (Quad Serial Peripheral Interface"""
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popup "uSDHC"
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(
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menuitem "uSDHC1" "per , ""Mass Storage,uSDHC (Ultra Secured Digital Host Controller,uSDHC1"""
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menuitem "uSDHC2" "per , ""Mass Storage,uSDHC (Ultra Secured Digital Host Controller,uSDHC2"""
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)
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)
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popup "Connectivity"
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(
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popup "USB3.0"
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(
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menuitem "USB1" "per , ""Connectivity,USB3.0 (Universal Serial Bus Control 3.0),USB1"""
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menuitem "USB2" "per , ""Connectivity,USB3.0 (Universal Serial Bus Control 3.0),USB2"""
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)
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popup "PCIe"
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(
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menuitem "PCIe 1" "per , ""Connectivity,PCIe (PCI express),PCIe 1"""
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menuitem "PCIe 2" "per , ""Connectivity,PCIe (PCI express),PCIe 2"""
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)
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menuitem "ENET" "per , ""Connectivity,ENET (Ethernet MAC)"""
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)
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popup "Timers"
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(
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popup "GPT"
|
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(
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menuitem "GPT1" "per , ""Timers,GPT (General Purpose Timer),GPT1"""
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menuitem "GPT2" "per , ""Timers,GPT (General Purpose Timer),GPT2"""
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menuitem "GPT3" "per , ""Timers,GPT (General Purpose Timer),GPT3"""
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menuitem "GPT4" "per , ""Timers,GPT (General Purpose Timer),GPT4"""
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menuitem "GPT5" "per , ""Timers,GPT (General Purpose Timer),GPT5"""
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menuitem "GPT6" "per , ""Timers,GPT (General Purpose Timer),GPT6"""
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)
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popup "PWM"
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(
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menuitem "PWM1" "per , ""Timers,PWM (Pulse Width Modulation),PWM1"""
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menuitem "PWM2" "per , ""Timers,PWM (Pulse Width Modulation),PWM2"""
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)
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)
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popup "Multimedia"
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(
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menuitem "eLCDIF" "per , ""Multimedia,eLCDIF (Enhanced LCD Interface)"""
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menuitem "HDMI TX" "per , ""Multimedia,HDMI TX (HD Display Transmitter Controller)"""
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popup "MIPI_DSI"
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(
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menuitem "MIPI_DSI_HOST" "per , ""Multimedia,MIPI_DSI (MIPI DSI Host Controller),MIPI_DSI_HOST"""
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menuitem "MIPI_DSI_HOST_DPI_INTFC" "per , ""Multimedia,MIPI_DSI (MIPI DSI Host Controller),MIPI_DSI_HOST_DPI_INTFC"""
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menuitem "MIPI_DSI_HOST_APB_PKT_IF" "per , ""Multimedia,MIPI_DSI (MIPI DSI Host Controller),MIPI_DSI_HOST_APB_PKT_IF"""
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menuitem "MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC" "per , ""Multimedia,MIPI_DSI (MIPI DSI Host Controller),MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC"""
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)
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menuitem "MIPI_CSI" "per , ""Multimedia,MIPI_CSI (MIPI CSI Host Controller)"""
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popup "SPDIF"
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|
(
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menuitem "SPDIF1" "per , ""Multimedia,SPDIF (Sony/Philips Digital Interface),SPDIF1"""
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menuitem "SPDIF2" "per , ""Multimedia,SPDIF (Sony/Philips Digital Interface),SPDIF2"""
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)
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popup "SAI"
|
|
(
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menuitem "SAI1" "per , ""Multimedia,SAI (Synchronous Audio Interface),SAI1"""
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|
menuitem "SAI2" "per , ""Multimedia,SAI (Synchronous Audio Interface),SAI2"""
|
|
menuitem "SAI3" "per , ""Multimedia,SAI (Synchronous Audio Interface),SAI3"""
|
|
menuitem "SAI4" "per , ""Multimedia,SAI (Synchronous Audio Interface),SAI4"""
|
|
menuitem "SAI5" "per , ""Multimedia,SAI (Synchronous Audio Interface),SAI5"""
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|
menuitem "SAI6" "per , ""Multimedia,SAI (Synchronous Audio Interface),SAI6"""
|
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)
|
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)
|
|
popup "VPU"
|
|
(
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menuitem "VPU_G1" "per , ""VPU (Video Processing Unit),VPU_G1"""
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menuitem "VPU_G2" "per , ""VPU (Video Processing Unit),VPU_G2"""
|
|
)
|
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popup "Display Controller Subsystem"
|
|
(
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menuitem "BLK_CTL" "per , ""Display Controller Subsystem,BLK_CTL (DCSS Block Control)"""
|
|
menuitem "DTG" "per , ""Display Controller Subsystem,DTG (Display Timing Generator)"""
|
|
menuitem "CTX_LD" "per , ""Display Controller Subsystem,CTX_LD (Context Load)"""
|
|
menuitem "DEC400D" "per , ""Display Controller Subsystem,DEC400D (Graphics Decompression)"""
|
|
popup "DTRC"
|
|
(
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menuitem "DTRC_CHAN2" "per , ""Display Controller Subsystem,DTRC (Decompression and Tile to Raster Conversion),DTRC_CHAN2"""
|
|
menuitem "DTRC_CHAN3" "per , ""Display Controller Subsystem,DTRC (Decompression and Tile to Raster Conversion),DTRC_CHAN3"""
|
|
)
|
|
popup "DPR"
|
|
(
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menuitem "DPR1" "per , ""Display Controller Subsystem,DPR (Display Prefetch and Resolve),DPR1"""
|
|
menuitem "DPR2" "per , ""Display Controller Subsystem,DPR (Display Prefetch and Resolve),DPR2"""
|
|
menuitem "DPR3" "per , ""Display Controller Subsystem,DPR (Display Prefetch and Resolve),DPR3"""
|
|
)
|
|
menuitem "MED_DC_SCALE" "per , ""Display Controller Subsystem,MED_DC_SCALE (Scaler)"""
|
|
menuitem "LUT_LD" "per , ""Display Controller Subsystem,LUT_LD (Look Up Table Load)"""
|
|
menuitem "MED_HDR10" "per , ""Display Controller Subsystem,MED_HDR10 (HDR10 Image Processing)"""
|
|
menuitem "SUBSAM" "per , ""Display Controller Subsystem,SUBSAM (Color Sub-Sampler)"""
|
|
menuitem "WR_SCL" "per , ""Display Controller Subsystem,WR_SCL (Write Scale)"""
|
|
menuitem "RD_SRC" "per , ""Display Controller Subsystem,RD_SRC (Read Surface)"""
|
|
menuitem "IRQ_STEER" "per , ""Display Controller Subsystem,IRQ_STEER (Interrupt Request Steering)"""
|
|
)
|
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popup "Low Speed Communication and Interconnects"
|
|
(
|
|
popup "I2C"
|
|
(
|
|
menuitem "I2C1" "per , ""Low Speed Communication and Interconnects,I2C (I2C Controller),I2C1"""
|
|
menuitem "I2C2" "per , ""Low Speed Communication and Interconnects,I2C (I2C Controller),I2C2"""
|
|
menuitem "I2C3" "per , ""Low Speed Communication and Interconnects,I2C (I2C Controller),I2C3"""
|
|
menuitem "I2C4" "per , ""Low Speed Communication and Interconnects,I2C (I2C Controller),I2C4"""
|
|
)
|
|
popup "UART"
|
|
(
|
|
menuitem "UART1" "per , ""Low Speed Communication and Interconnects,UART (Universal Asynchronous Receiver/Transmitter),UART1"""
|
|
menuitem "UART2" "per , ""Low Speed Communication and Interconnects,UART (Universal Asynchronous Receiver/Transmitter),UART2"""
|
|
menuitem "UART3" "per , ""Low Speed Communication and Interconnects,UART (Universal Asynchronous Receiver/Transmitter),UART3"""
|
|
menuitem "UART4" "per , ""Low Speed Communication and Interconnects,UART (Universal Asynchronous Receiver/Transmitter),UART4"""
|
|
)
|
|
)
|
|
)
|
|
)
|