495 lines
17 KiB
Plaintext
495 lines
17 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: IMX7ULP Specific Menu
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; @Props: Released
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; @Author: JMI, RSA
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; @Changelog: 2019-11-28 JMI
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; 2022-02-21 RSA
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; @Manufacturer: NXP - NXP Semiconductors
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; @Core: Cortex-A7, Cortex-M4F
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; @Chip: IMX7ULP-CA7, IMX7ULP-CM4
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: menimx7ulp.men 16339 2023-07-03 13:30:14Z pegold $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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if CORENAME()=="CORTEXM4F"
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(
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popup "[:chip]Core Registers (Cortex-M4F)"
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(
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menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M4F),System Control"""
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menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M4F),Memory Protection Unit"""
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menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M4F),Nested Vectored Interrupt Controller"""
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menuitem "[:chip]FPU;Floating-point Unit" "per , ""Core Registers (Cortex-M4F),Floating-point Unit"""
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popup "[:chip]Debug"
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(
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menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M4F),Debug,Core Debug"""
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menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M4F),Debug,Flash Patch and Breakpoint Unit (FPB)"""
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menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M4F),Debug,Data Watchpoint and Trace Unit (DWT)"""
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)
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)
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)
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else if CORENAME()=="CORTEXA7MPCORE"
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(
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popup "[:chip]Core Registers (Cortex-A7MPCore)"
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(
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menuitem "[:chip]ID Registers" "per , ""Core Registers (Cortex-A7MPCore),ID Registers"""
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menuitem "[:chip]System Control and Configuration" "per , ""Core Registers (Cortex-A7MPCore),System Control and Configuration"""
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menuitem "[:chip]Memory Management Unit" "per , ""Core Registers (Cortex-A7MPCore),Memory Management Unit"""
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menuitem "[:chip]Virtualization Extensions" "per , ""Core Registers (Cortex-A7MPCore),Virtualization Extensions"""
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menuitem "[:chip]Cache Control and Configuration" "per , ""Core Registers (Cortex-A7MPCore),Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor" "per , ""Core Registers (Cortex-A7MPCore),System Performance Monitor"""
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menuitem "[:chip]System Timer Register" "per , ""Core Registers (Cortex-A7MPCore),System Timer Register"""
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separator
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menuitem "[:chip]Debug Registers" "per , ""Core Registers (Cortex-A7MPCore),Debug Registers"""
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menuitem "[:chip]Breakpoint Registers" "per , ""Core Registers (Cortex-A7MPCore),Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Control Registers" "per , ""Core Registers (Cortex-A7MPCore),Watchpoint Control Registers"""
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separator
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menuitem "[:chip]Interrupt Controller" "per , ""Core Registers (Cortex-A7MPCore),Interrupt Controller"""
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)
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)
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separator
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menuitem "FB" "per , ""FB"""
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popup "USB (Universal Serial Bus)"
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(
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menuitem "USB0" "per , ""USB (Universal Serial Bus),USB0"""
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menuitem "USB1" "per , ""USB (Universal Serial Bus),USB1"""
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)
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popup "USBNC (Universal Serial Bus)"
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(
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menuitem "USBNC0" "per , ""USBNC (Universal Serial Bus),USBNC0"""
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menuitem "USBNC1" "per , ""USBNC (Universal Serial Bus),USBNC1"""
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)
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menuitem "USBPHY" "per , ""USBPHY (USBPHY Register Reference Index)"""
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menuitem "DCD" "per , ""DCD (USBDCD),DCD"""
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popup "USDHC (Ultra Secured Digital Host Controller)"
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(
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menuitem "USDHC0" "per , ""USDHC (Ultra Secured Digital Host Controller),USDHC0"""
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menuitem "USDHC1" "per , ""USDHC (Ultra Secured Digital Host Controller),USDHC1"""
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)
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popup "TRGMUX"
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(
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menuitem "TRGMUX1" "per , ""TRGMUX,TRGMUX1"""
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menuitem "TRGMUX0" "per , ""TRGMUX,TRGMUX0"""
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)
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popup "SCG"
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(
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menuitem "SCG1" "per , ""SCG,SCG1"""
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menuitem "SCG0" "per , ""SCG,SCG0"""
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)
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popup "PCC"
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(
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menuitem "PCC2" "per , ""PCC,PCC2"""
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menuitem "PCC3" "per , ""PCC,PCC3"""
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menuitem "PCC0" "per , ""PCC,PCC0"""
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menuitem "PCC1" "per , ""PCC,PCC1"""
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)
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menuitem "PMC1" "per , ""PMC1 (PMC)"""
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menuitem "VIU" "per , ""VIU"""
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menuitem "MIPI_DSI_HOST0" "per , ""MIPI_DSI_HOST (MIPI DSI HOST)"""
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menuitem "MIPI_DSI_HOST_DPI_INTFC0" "per , ""MIPI_DSI_HOST_DPI_INTFC (MIPI DSI HOST DPI INTFC)"""
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menuitem "MIPI_DSI_HOST_APB_PKT_IF0" "per , ""MIPI_DSI_HOST_APB_PKT_IF (MIPI DSI HOST APB PKT IF)"""
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menuitem "MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC0" "per , ""MIPI_DSI_HOST_FSL_IP1_DPHY_INTFC (MIPI DSI HOST FSL IP1 DPHY INTFC)"""
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menuitem "LCDIF0" "per , ""LCDIF (LCD Interface)"""
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menuitem "MMDC0" "per , ""MMDC"""
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menuitem "IOMUXC1" "per , ""IOMUXC1 (IOMUXC1 Register Index)"""
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menuitem "IOMUXC1_DDR" "per , ""IOMUXC1_DDR (IOMUXC1_DDR Register Index)"""
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popup "PORT"
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(
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menuitem "PORTD" "per , ""PORT,PORTD"""
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menuitem "PORTE" "per , ""PORT,PORTE"""
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menuitem "PORTA" "per , ""PORT,PORTA"""
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menuitem "PORTB" "per , ""PORT,PORTB"""
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menuitem "PORTC" "per , ""PORT,PORTC"""
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menuitem "PORTF" "per , ""PORT,PORTF"""
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)
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popup "DMA"
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(
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menuitem "DMA0" "per , ""DMA,DMA0"""
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menuitem "DMA1" "per , ""DMA,DMA1"""
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)
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popup "GPIO (General Purpose I/O Ports And Peripheral I/O Lines)"
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(
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menuitem "GPIOA" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIOA"""
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menuitem "GPIOC" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIOC"""
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menuitem "GPIOD" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIOD"""
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menuitem "GPIOE" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIOE"""
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menuitem "GPIOF" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIOF"""
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menuitem "GPIOB" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIOB"""
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)
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menuitem "XRDC" "per , ""XRDC"""
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popup "SEMA42"
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(
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menuitem "SEMA42_0" "per , ""SEMA42 (sema42_ips),SEMA42_0"""
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menuitem "SEMA42_1" "per , ""SEMA42 (sema42_ips),SEMA42_1"""
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)
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popup "DMA_CH_MUX"
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(
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menuitem "DMA_CH_MUX0" "per , ""DMA_CH_MUX,DMA_CH_MUX0"""
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menuitem "DMA_CH_MUX1" "per , ""DMA_CH_MUX,DMA_CH_MUX1"""
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)
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menuitem "LLWU" "per , ""LLWU"""
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if (cpuis("IMX7ULP-CM4"))
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(
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menuitem "MUA" "per , ""MU (MUA),MUA"""
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)
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popup "WDOG (Watchdog Timer Unit)"
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(
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menuitem "WDOG0" "per , ""WDOG (Watchdog Timer Unit),WDOG0"""
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menuitem "WDOG1" "per , ""WDOG (Watchdog Timer Unit),WDOG1"""
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menuitem "WDOG2" "per , ""WDOG (Watchdog Timer Unit),WDOG2"""
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)
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menuitem "CRC0" "per , ""CRC"""
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menuitem "LTC0" "per , ""LTC"""
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menuitem "TRNG0" "per , ""TRNG (TRNG0)"""
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popup "LPIT"
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(
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menuitem "LPIT0" "per , ""LPIT,LPIT0"""
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menuitem "LPIT1" "per , ""LPIT,LPIT1"""
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)
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popup "LPTIMER (LPTMR)"
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(
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menuitem "LPTMR0" "per , ""LPTIMER (LPTMR),LPTMR0"""
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menuitem "LPTMR1" "per , ""LPTIMER (LPTMR),LPTMR1"""
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)
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popup "TPM"
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(
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menuitem "TPM0" "per , ""TPM,TPM0"""
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menuitem "TPM4" "per , ""TPM,TPM4"""
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menuitem "TPM5" "per , ""TPM,TPM5"""
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menuitem "TPM6" "per , ""TPM,TPM6"""
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menuitem "TPM7" "per , ""TPM,TPM7"""
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menuitem "TPM1" "per , ""TPM,TPM1"""
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menuitem "TPM2" "per , ""TPM,TPM2"""
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menuitem "TPM3" "per , ""TPM,TPM3"""
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)
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popup "FLEXIO"
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(
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menuitem "FLEXIO0" "per , ""FLEXIO,FLEXIO0"""
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menuitem "FLEXIO1" "per , ""FLEXIO,FLEXIO1"""
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)
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popup "LPI2C"
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(
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menuitem "LPI2C0" "per , ""LPI2C,LPI2C0"""
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menuitem "LPI2C4" "per , ""LPI2C,LPI2C4"""
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menuitem "LPI2C5" "per , ""LPI2C,LPI2C5"""
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menuitem "LPI2C6" "per , ""LPI2C,LPI2C6"""
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menuitem "LPI2C7" "per , ""LPI2C,LPI2C7"""
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menuitem "LPI2C1" "per , ""LPI2C,LPI2C1"""
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menuitem "LPI2C2" "per , ""LPI2C,LPI2C2"""
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menuitem "LPI2C3" "per , ""LPI2C,LPI2C3"""
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)
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popup "I2S (Inter-Integrated Sound Bus Controller)"
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(
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menuitem "I2S0" "per , ""I2S (Inter-Integrated Sound Bus Controller),I2S0"""
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menuitem "I2S1" "per , ""I2S (Inter-Integrated Sound Bus Controller),I2S1"""
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)
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popup "LPSPI"
|
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(
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menuitem "LPSPI0" "per , ""LPSPI,LPSPI0"""
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menuitem "LPSPI2" "per , ""LPSPI,LPSPI2"""
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menuitem "LPSPI3" "per , ""LPSPI,LPSPI3"""
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menuitem "LPSPI1" "per , ""LPSPI,LPSPI1"""
|
|
)
|
|
popup "LPUART"
|
|
(
|
|
menuitem "LPUART0" "per , ""LPUART,LPUART0"""
|
|
menuitem "LPUART4" "per , ""LPUART,LPUART4"""
|
|
menuitem "LPUART5" "per , ""LPUART,LPUART5"""
|
|
menuitem "LPUART6" "per , ""LPUART,LPUART6"""
|
|
menuitem "LPUART7" "per , ""LPUART,LPUART7"""
|
|
menuitem "LPUART1" "per , ""LPUART,LPUART1"""
|
|
menuitem "LPUART2" "per , ""LPUART,LPUART2"""
|
|
menuitem "LPUART3" "per , ""LPUART,LPUART3"""
|
|
)
|
|
menuitem "IOMUXC0" "per , ""IOMUXC0 (IOMUXC1 Register Index)"""
|
|
popup "ADC"
|
|
(
|
|
menuitem "ADC0" "per , ""ADC,ADC0"""
|
|
menuitem "ADC1" "per , ""ADC,ADC1"""
|
|
)
|
|
popup "CMP"
|
|
(
|
|
menuitem "CMP0" "per , ""CMP,CMP0"""
|
|
menuitem "CMP1" "per , ""CMP,CMP1"""
|
|
)
|
|
popup "DAC"
|
|
(
|
|
menuitem "DAC0" "per , ""DAC,DAC0"""
|
|
menuitem "DAC1" "per , ""DAC,DAC1"""
|
|
)
|
|
menuitem "SNVS" "per , ""SVNS (Secure Non-Volatile Storage)"""
|
|
popup "ROMC"
|
|
(
|
|
menuitem "ROMC0" "per , ""ROMC,ROMC0"""
|
|
menuitem "ROMC1" "per , ""ROMC,ROMC1"""
|
|
)
|
|
menuitem "EWM" "per , ""EWM"""
|
|
menuitem "PMC0" "per , ""PMC0 (PMC)"""
|
|
menuitem "SIM" "per , ""SIM (SIM Memory Map)"""
|
|
menuitem "TSTMRA" "per , ""TSTMRA"""
|
|
menuitem "TSTMRB" "per , ""TSTMRB"""
|
|
popup "MSMC (SMC)"
|
|
(
|
|
menuitem "MSMC0" "per , ""MSMC (SMC),MSMC0"""
|
|
menuitem "MSMC1" "per , ""MSMC (SMC),MSMC1"""
|
|
)
|
|
menuitem "QUADSPI0" "per , ""QUADSPI (QuadSPI)"""
|
|
menuitem "OTFAD" "per , ""OTFAD"""
|
|
menuitem "OCOTP_CTRL" "per , ""OCOTP_CTRL (OCOTP)"""
|
|
if (cpuis("IMX7ULP-CM4"))
|
|
(
|
|
menuitem "MCM" "per , ""MCM (Core Platform Miscellaneous Control Module),MCM"""
|
|
menuitem "MMCAU" "per , ""MMCAU (CAU),MMCAU"""
|
|
menuitem "LMEM" "per , ""LMEM (LMEM64),LMEM"""
|
|
)
|
|
popup "FGPIO (GPIO)"
|
|
(
|
|
menuitem "FGPIOA" "per , ""FGPIO (GPIO),FGPIOA"""
|
|
menuitem "FGPIOB" "per , ""FGPIO (GPIO),FGPIOB"""
|
|
)
|
|
if (cpuis("IMX7ULP-CA7"))
|
|
(
|
|
menuitem "MUB" "per , ""MUB (Messaging Unit Processor B-side),MUB"""
|
|
)
|
|
)
|
|
)
|