394 lines
15 KiB
Plaintext
394 lines
15 KiB
Plaintext
; --------------------------------------------------------------------------------
|
|
; @Title: iMX6SLL Specific Menu
|
|
; @Props: Released
|
|
; @Author: MSU, KOF
|
|
; @Changelog: 2019-01-16 KOF
|
|
; @Manufacturer: NXP - NXP Semiconductors
|
|
; @Core: Cortex-A9
|
|
; @Chip: IMX6SLL
|
|
; @Copyright: (C) 1989-2019 Lauterbach GmbH, licensed for use with TRACE32(R) only
|
|
; --------------------------------------------------------------------------------
|
|
; $Id: menimx6sll.men 16339 2023-07-03 13:30:14Z pegold $
|
|
|
|
add
|
|
menu
|
|
(
|
|
IF SOFTWARE.BUILD.BASE()>=69655.
|
|
(
|
|
popup "&CPU"
|
|
(
|
|
separator
|
|
IF CPU.FEATURE(MMU)
|
|
(
|
|
popup "[:mmu]MMU"
|
|
(
|
|
menuitem "[:mmureg]MMU Control" "MMU.view"
|
|
separator
|
|
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
|
|
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
|
|
separator
|
|
IF CPU.FEATURE(ITLBDUMP)
|
|
(
|
|
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
|
|
)
|
|
IF CPU.FEATURE(DTLBDUMP)
|
|
(
|
|
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
|
|
)
|
|
IF CPU.FEATURE(TLB0DUMP)
|
|
(
|
|
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
|
|
)
|
|
IF CPU.FEATURE(TLB1DUMP)
|
|
(
|
|
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
|
|
)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU")
|
|
(
|
|
popup "[:mmu]SMMU"
|
|
(
|
|
menuitem "[:chip]SMMU1 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU1 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU2")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU2 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU2 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU3")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU3 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU3 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU4")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU4 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU4 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU5")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU5 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU5 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU6")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU6 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU6 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
)
|
|
)
|
|
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
|
|
(
|
|
popup "[:cache]Cache"
|
|
(
|
|
IF CPU.FEATURE(L1ICACHEDUMP)
|
|
(
|
|
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
|
|
menuitem "[:cache]ICACHE List" "CACHE.List IC"
|
|
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
|
|
)
|
|
IF CPU.FEATURE(L1DCACHEDUMP)
|
|
(
|
|
separator
|
|
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
|
|
menuitem "[:cache]DCACHE List" "CACHE.List DC"
|
|
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
|
|
)
|
|
IF CPU.FEATURE(L2CACHEDUMP)
|
|
(
|
|
separator
|
|
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
|
|
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
|
|
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
|
|
)
|
|
)
|
|
)
|
|
)
|
|
popup "&Trace"
|
|
(
|
|
separator
|
|
IF COMPonent.AVAILable("ITM")
|
|
(
|
|
popup "ITM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]ITM settings..." "ITM.state"
|
|
separator
|
|
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("STM")
|
|
(
|
|
popup "STM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]STM settings..." "STM.state"
|
|
separator
|
|
menuitem "[:alist]STMTrace List" "STMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("HTM")
|
|
(
|
|
popup "HTM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]HTM settings..." "HTM.state"
|
|
separator
|
|
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("TPIU")
|
|
(
|
|
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
|
|
)
|
|
IF COMPonent.AVAILable("ETR")
|
|
(
|
|
menuitem "[:oconfig]ETR settings..."
|
|
(
|
|
PRIVATE &pdd
|
|
&pdd=OS.PDD()
|
|
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
|
|
)
|
|
)
|
|
)
|
|
popup "&Misc"
|
|
(
|
|
popup "Tools"
|
|
(
|
|
IF CPUIS64BIT()||CPU.FEATURE("SPR")
|
|
(
|
|
menuitem "ARM System Register Converter"
|
|
(
|
|
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
|
|
)
|
|
)
|
|
IF CPU.FEATURE("C15")
|
|
(
|
|
menuitem "ARM Coprocessor Converter"
|
|
(
|
|
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
|
|
)
|
|
)
|
|
)
|
|
)
|
|
popup "&Perf"
|
|
(
|
|
IF CPU.FEATURE(BMC)
|
|
(
|
|
before "Reset"
|
|
menuitem "[:bmc]Benchmark Counters" "BMC.state"
|
|
before "Reset"
|
|
separator
|
|
)
|
|
)
|
|
)
|
|
popup "Peripherals"
|
|
(
|
|
popup "[:chip]Core Registers (Cortex-A9MPCore)"
|
|
(
|
|
menuitem "[:chip]ID Registers" "per , ""Core Registers (Cortex-A9MPCore),ID Registers"""
|
|
menuitem "[:chip]System Control and Configuration" "per , ""Core Registers (Cortex-A9MPCore),System Control and Configuration"""
|
|
menuitem "[:chip]Memory Management Unit" "per , ""Core Registers (Cortex-A9MPCore),Memory Management Unit"""
|
|
menuitem "[:chip]Cache Control and Configuration" "per , ""Core Registers (Cortex-A9MPCore),Cache Control and Configuration"""
|
|
menuitem "[:chip]System Performance Monitor" "per , ""Core Registers (Cortex-A9MPCore),System Performance Monitor"""
|
|
menuitem "[:chip]Preload Engine" "per , ""Core Registers (Cortex-A9MPCore),Preload Engine"""
|
|
menuitem "[:chip]NEON" "per , ""Core Registers (Cortex-A9MPCore),NEON"""
|
|
separator
|
|
menuitem "[:chip]Debug Registers" "per , ""Core Registers (Cortex-A9MPCore),Debug Registers"""
|
|
menuitem "[:chip]Breakpoint Registers" "per , ""Core Registers (Cortex-A9MPCore),Breakpoint Registers"""
|
|
menuitem "[:chip]Watchpoint Control Registers" "per , ""Core Registers (Cortex-A9MPCore),Watchpoint Control Registers"""
|
|
separator
|
|
menuitem "[:chip]Snoop Control Unit (SCU)" "per , ""Core Registers (Cortex-A9MPCore),Snoop Control Unit (SCU)"""
|
|
menuitem "[:chip]Timer and Watchdog Blocks" "per , ""Core Registers (Cortex-A9MPCore),Timer and Watchdog Blocks"""
|
|
menuitem "[:chip]Interrupt Controller (GIC-400)" "per , ""Core Registers (Cortex-A9MPCore),Interrupt Controller (GIC-400)"""
|
|
)
|
|
separator
|
|
popup "AIPSTZ;AHB to IP Bridge Trust Zone"
|
|
(
|
|
menuitem "AIPSTZ 1" "per , ""AIPSTZ (AHB to IP Bridge Trust Zone),AIPSTZ 1"""
|
|
menuitem "AIPSTZ 2" "per , ""AIPSTZ (AHB to IP Bridge Trust Zone),AIPSTZ 2"""
|
|
)
|
|
menuitem "AUDMUX;Digital Audio Multiplexer" "per , ""AUDMUX (Digital Audio Multiplexer)"""
|
|
popup "CCM;Clock Control Module"
|
|
(
|
|
menuitem "CCM" "per , ""CCM (Clock Control Module),CCM"""
|
|
menuitem "CCM_ANALOG" "per , ""CCM (Clock Control Module),CCM_ANALOG"""
|
|
)
|
|
menuitem "CSI;CMOS Sensor Interface" "per , ""CSI (CMOS Sensor Interface)"""
|
|
popup "ECSPI;Enhanced Configurable SPI Registers"
|
|
(
|
|
menuitem "ECSPI 1" "per , ""ECSPI (Enhanced Configurable SPI Registers),ECSPI 1"""
|
|
menuitem "ECSPI 2" "per , ""ECSPI (Enhanced Configurable SPI Registers),ECSPI 2"""
|
|
menuitem "ECSPI 3" "per , ""ECSPI (Enhanced Configurable SPI Registers),ECSPI 3"""
|
|
menuitem "ECSPI 4" "per , ""ECSPI (Enhanced Configurable SPI Registers),ECSPI 4"""
|
|
)
|
|
menuitem "ELCDIF;Enhanced LCD Interface" "per , ""ELCDIF (Enhanced LCD Interface)"""
|
|
menuitem "EPDC;Electrophoretic Display Controller" "per , ""EPDC (Electrophoretic Display Controller)"""
|
|
popup "EPIT;Enhanced Periodic Interrupt Timer"
|
|
(
|
|
menuitem "EPIT 1" "per , ""EPIT (Enhanced Periodic Interrupt Timer),EPIT 1"""
|
|
menuitem "EPIT 2" "per , ""EPIT (Enhanced Periodic Interrupt Timer),EPIT 2"""
|
|
)
|
|
popup "GPC;Global Power Controller"
|
|
(
|
|
menuitem "GPC" "per , ""GPC (Global Power Controller),GPC"""
|
|
menuitem "PGC" "per , ""GPC (Global Power Controller),PGC"""
|
|
)
|
|
popup "GPIO;General Purpose Input/Output"
|
|
(
|
|
menuitem "GPIO 1" "per , ""GPIO (General Purpose Input/Output),GPIO 1"""
|
|
menuitem "GPIO 2" "per , ""GPIO (General Purpose Input/Output),GPIO 2"""
|
|
menuitem "GPIO 3" "per , ""GPIO (General Purpose Input/Output),GPIO 3"""
|
|
menuitem "GPIO 4" "per , ""GPIO (General Purpose Input/Output),GPIO 4"""
|
|
menuitem "GPIO 5" "per , ""GPIO (General Purpose Input/Output),GPIO 5"""
|
|
menuitem "GPIO 6" "per , ""GPIO (General Purpose Input/Output),GPIO 6"""
|
|
)
|
|
menuitem "GPT;General Purpose Timer" "per , ""GPT (General Purpose Timer)"""
|
|
popup "I2C;I2C Controller"
|
|
(
|
|
menuitem "I2C 1" "per , ""I2C (I2C Controller),I2C 1"""
|
|
menuitem "I2C 2" "per , ""I2C (I2C Controller),I2C 2"""
|
|
menuitem "I2C 3" "per , ""I2C (I2C Controller),I2C 3"""
|
|
)
|
|
popup "IOMUXC;IOMUX Controller"
|
|
(
|
|
menuitem "IOMUXC_SNVS" "per , ""IOMUXC (IOMUX Controller),IOMUXC_SNVS"""
|
|
menuitem "IOMUXC_SNVS_GPR" "per , ""IOMUXC (IOMUX Controller),IOMUXC_SNVS_GPR"""
|
|
menuitem "IOMUXC_GPR" "per , ""IOMUXC (IOMUX Controller),IOMUXC_GPR"""
|
|
menuitem "IOMUXC" "per , ""IOMUXC (IOMUX Controller),IOMUXC"""
|
|
)
|
|
menuitem "KPP;Keypad Port Registers" "per , ""KPP (Keypad Port Registers)"""
|
|
menuitem "MMDC;Multi Mode DDR Controller" "per , ""MMDC (Multi Mode DDR Controller)"""
|
|
menuitem "OCOTP_CTRL;On-Chip OTP Controller" "per , ""OCOTP_CTRL (On-Chip OTP Controller)"""
|
|
menuitem "PMU;Power Management Unit" "per , ""PMU (Power Management Unit)"""
|
|
popup "PWM;Pulse Width Modulation"
|
|
(
|
|
menuitem "PWM 1" "per , ""PWM (Pulse Width Modulation),PWM 1"""
|
|
menuitem "PWM 2" "per , ""PWM (Pulse Width Modulation),PWM 2"""
|
|
menuitem "PWM 3" "per , ""PWM (Pulse Width Modulation),PWM 3"""
|
|
menuitem "PWM 4" "per , ""PWM (Pulse Width Modulation),PWM 4"""
|
|
)
|
|
menuitem "PXP;Pixel Pipeline" "per , ""PXP (Pixel Pipeline)"""
|
|
menuitem "RNGB;Random Number Generator" "per , ""RNGB (Random Number Generator)"""
|
|
menuitem "ROMC;ROM Controller With Patch" "per , ""ROMC (ROM Controller With Patch)"""
|
|
menuitem "SDMA;Smart Direct Memory Access Controller" "per , ""SDMA (Smart Direct Memory Access Controller)"""
|
|
menuitem "SNVS;Secure Non-Volatile Storage" "per , ""SNVS (Secure Non-Volatile Storage)"""
|
|
menuitem "SPBA;Shared Peripheral Bus Arbiter" "per , ""SPBA (Shared Peripheral Bus Arbiter)"""
|
|
menuitem "SPDIF;Sony/Philips Digital Interface" "per , ""SPDIF (Sony/Philips Digital Interface)"""
|
|
menuitem "SRC;System Reset Controller" "per , ""SRC (System Reset Controller)"""
|
|
popup "SSI;Synchronous Serial Interface"
|
|
(
|
|
menuitem "SSI 1" "per , ""SSI (Synchronous Serial Interface),SSI 1"""
|
|
menuitem "SSI 2" "per , ""SSI (Synchronous Serial Interface),SSI 2"""
|
|
menuitem "SSI 3" "per , ""SSI (Synchronous Serial Interface),SSI 3"""
|
|
)
|
|
menuitem "TEMPMON;Temperature Monitor" "per , ""TEMPMON (Temperature Monitor)"""
|
|
menuitem "TZASC;TrustZone Address Space Controller" "per , ""TZASC (TrustZone Address Space Controller)"""
|
|
popup "UART;Universal Asynchronous Receiver/Transmitter"
|
|
(
|
|
menuitem "UART 4" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART 4"""
|
|
menuitem "UART 1" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART 1"""
|
|
menuitem "UART 2" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART 2"""
|
|
menuitem "UART 3" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART 3"""
|
|
menuitem "UART 5" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART 5"""
|
|
)
|
|
popup "USB Controller;Universal Serial Bus Controller"
|
|
(
|
|
menuitem "USBNC;USB Non-Core" "per , ""USB Controller (Universal Serial Bus Controller),USBNC (USB Non-Core)"""
|
|
popup "USBC;USB Core"
|
|
(
|
|
menuitem "UOG 1" "per , ""USB Controller (Universal Serial Bus Controller),USBC (USB Core),UOG 1"""
|
|
menuitem "UOG 2" "per , ""USB Controller (Universal Serial Bus Controller),USBC (USB Core),UOG 2"""
|
|
menuitem "UH 1" "per , ""USB Controller (Universal Serial Bus Controller),USBC (USB Core),UH 1"""
|
|
)
|
|
)
|
|
popup "USB_PHY;Universal Serial Bus 2.0 Integrated PHY"
|
|
(
|
|
popup "USB_PHY Registers"
|
|
(
|
|
menuitem "USBPHY 1" "per , ""USB_PHY (Universal Serial Bus 2.0 Integrated PHY),USB_PHY,USBPHY 1"""
|
|
menuitem "USBPHY 2" "per , ""USB_PHY (Universal Serial Bus 2.0 Integrated PHY),USB_PHY,USBPHY 2"""
|
|
)
|
|
menuitem "USB Analog" "per , ""USB_PHY (Universal Serial Bus 2.0 Integrated PHY),USB_ANALOG"""
|
|
)
|
|
popup "USDHC;Ultra Secured Digital Host Controller"
|
|
(
|
|
menuitem "USDHC 1" "per , ""USDHC (Ultra Secured Digital Host Controller),USDHC 1"""
|
|
menuitem "USDHC 2" "per , ""USDHC (Ultra Secured Digital Host Controller),USDHC 2"""
|
|
menuitem "USDHC 3" "per , ""USDHC (Ultra Secured Digital Host Controller),USDHC 3"""
|
|
)
|
|
popup "WDOG;Watchdog"
|
|
(
|
|
menuitem "WDOG 1" "per , ""WDOG (Watchdog),WDOG 1"""
|
|
menuitem "WDOG 2" "per , ""WDOG (Watchdog),WDOG 2"""
|
|
)
|
|
menuitem "XTALOSC;Crystal Oscillator" "per , ""XTALOSC (Crystal Oscillator)"""
|
|
)
|
|
)
|