328 lines
9.2 KiB
Plaintext
328 lines
9.2 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: tbd.
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; @Props: Released
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; @Author: -
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; @Changelog:
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; @Manufacturer:
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; @Core:
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; @Chip:
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; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: mendra72xipu.men 16339 2023-07-03 13:30:14Z pegold $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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popup "[:chip]Core Registers (Cortex-M4F)"
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(
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menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M4F),System Control"""
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menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M4F),Memory Protection Unit"""
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menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M4F),Nested Vectored Interrupt Controller"""
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menuitem "[:chip]FPU;Floating-point Unit" "per , ""Core Registers (Cortex-M4F),Floating-point Unit"""
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popup "[:chip]Debug"
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(
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menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M4F),Debug,Core Debug"""
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menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M4F),Debug,Flash Patch and Breakpoint Unit (FPB)"""
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menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M4F),Debug,Data Watchpoint and Trace Unit (DWT)"""
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)
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)
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separator
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menuitem "PRCM" "PER , ""PRCM"""
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menuitem "Cortex_A15_MPU_Subsystem" "PER , ""Cortex_A15_MPU_Subsystem"""
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menuitem "DSP_Subsystem" "PER , ""DSP_Subsystem"""
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menuitem "IVA_Overview" "PER , ""IVA_Overview"""
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menuitem "IVA_Video_Direct_Memory_Access" "PER , ""IVA_Video_Direct_Memory_Access"""
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menuitem "IVA_Synchronization_Box" "PER , ""IVA_Synchronization_Box"""
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menuitem "IVA_Load_and_Store_Engine" "PER , ""IVA_Load_and_Store_Engine"""
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menuitem "IVA_Motion_Estimation" "PER , ""IVA_Motion_Estimation"""
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menuitem "IVA_Intra_Prediction_Estimation" "PER , ""IVA_Intra_Prediction_Estimation"""
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menuitem "IVA_Loop_Filter" "PER , ""IVA_Loop_Filter"""
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menuitem "IVA_Motion_Compensation" "PER , ""IVA_Motion_Compensation"""
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menuitem "IVA_CALCulation_Engine_3" "PER , ""IVA_CALCulation_Engine_3"""
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menuitem "IVA_Entropy_Coder_Decoder" "PER , ""IVA_Entropy_Coder_Decoder"""
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menuitem "Dual_Cortex_M4_IPU_Subsystem" "PER , ""Dual_Cortex_M4_IPU_Subsystem"""
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menuitem "CAMSS" "PER , ""CAMSS"""
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menuitem "VIP" "PER , ""VIP"""
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menuitem "VPE" "PER , ""VPE"""
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menuitem "Display_Subsystem_Overview" "PER , ""Display_Subsystem_Overview"""
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menuitem "Display_Controller" "PER , ""Display_Controller"""
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menuitem "GPU" "PER , ""GPU"""
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menuitem "BB2D" "PER , ""BB2D"""
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menuitem "L3_MAIN_Interconnect" "PER , ""L3_MAIN_Interconnect"""
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menuitem "L4_Interconnects" "PER , ""L4_Interconnects"""
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menuitem "Dynamic_Memory_Manager" "PER , ""Dynamic_Memory_Manager"""
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menuitem "EMIF_Controller" "PER , ""EMIF_Controller"""
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menuitem "General_Purpose_Memory_Controller" "PER , ""General_Purpose_Memory_Controller"""
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menuitem "Error_Location_Module" "PER , ""Error_Location_Module"""
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menuitem "On_Chip_Memory_OCM_Subsystem" "PER , ""On_Chip_Memory_OCM_Subsystem"""
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menuitem "System_DMA" "PER , ""System_DMA"""
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menuitem "Control_Module" "PER , ""Control_Module"""
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menuitem "Mailbox" "PER , ""Mailbox"""
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menuitem "MMU" "PER , ""MMU"""
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menuitem "Spinlock" "PER , ""Spinlock"""
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menuitem "General_Purpose_Timers" "PER , ""General_Purpose_Timers"""
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menuitem "Watchdog_Timers" "PER , ""Watchdog_Timers"""
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menuitem "_32_kHz_Synchronized_Timer_COUNTER_32K_" "PER , ""_32_kHz_Synchronized_Timer_COUNTER_32K_"""
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menuitem "RTC_Overview" "PER , ""RTC_Overview"""
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menuitem "Multimaster_High_Speed_I2C_Controller" "PER , ""Multimaster_High_Speed_I2C_Controller"""
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menuitem "HDQ_1_Wire" "PER , ""HDQ_1_Wire"""
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menuitem "UART_IrDA_CIR" "PER , ""UART_IrDA_CIR"""
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menuitem "Multichannel_Serial_Peripheral_Interface" "PER , ""Multichannel_Serial_Peripheral_Interface"""
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menuitem "Quad_Serial_Peripheral_Interface" "PER , ""Quad_Serial_Peripheral_Interface"""
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menuitem "Multichannel_Audio_Serial_Ports" "PER , ""Multichannel_Audio_Serial_Ports"""
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menuitem "SuperSpeed_USB_DRD" "PER , ""SuperSpeed_USB_DRD"""
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menuitem "SATA_Controller" "PER , ""SATA_Controller"""
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menuitem "PCIe_Controllers" "PER , ""PCIe_Controllers"""
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menuitem "DCAN" "PER , ""DCAN"""
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menuitem "Gigabit_Ethernet_Switch_GMAC_SW" "PER , ""Gigabit_Ethernet_Switch_GMAC_SW"""
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menuitem "Media_Local_Bus_MLB" "PER , ""Media_Local_Bus_MLB"""
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menuitem "eMMC_SD_SDIO" "PER , ""eMMC_SD_SDIO"""
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menuitem "SATA_PHY_Subsystem" "PER , ""SATA_PHY_Subsystem"""
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menuitem "USB3_PHY_Subsystem" "PER , ""USB3_PHY_Subsystem"""
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menuitem "PCIe_Shared_PHY_Subsystem" "PER , ""PCIe_Shared_PHY_Subsystem"""
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menuitem "General_Purpose_Interface" "PER , ""General_Purpose_Interface"""
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menuitem "Keyboard_Controller" "PER , ""Keyboard_Controller"""
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menuitem "PWM_Subsystem_Resources" "PER , ""PWM_Subsystem_Resources"""
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menuitem "VCP" "PER , ""VCP"""
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menuitem "ATL" "PER , ""ATL"""
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menuitem "EDMA" "PER , ""EDMA"""
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)
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)
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