365 lines
13 KiB
Plaintext
365 lines
13 KiB
Plaintext
; --------------------------------------------------------------------------------
|
|
; @Title: CYT6BJx Specific Menu
|
|
; @Props: Released
|
|
; @Author: JDU, NEJ
|
|
; @Changelog: 2023-05-19 JDU
|
|
; 2023-11-03 NEJ
|
|
; @Manufacturer: CYPRESS - Cypress Semiconductor Corporation
|
|
; @Core: Cortex-M0+,Cortex-M7F
|
|
; @Chip: CYT6BJ8-CM0+, CYT6BJ8-CM7, CYT6BJ8-CM7-0, CYT6BJ8-CM7-1, CYT6BJ8-CM7-2,
|
|
; CYT6BJ8-CM7-3, CYT6BJB-CM0+, CYT6BJB-CM7, CYT6BJB-CM7-0, CYT6BJB-CM7-1,
|
|
; CYT6BJB-CM7-2, CYT6BJB-CM7-3, CYT6BJC-CM0+, CYT6BJC-CM7, CYT6BJC-CM7-0,
|
|
; CYT6BJC-CM7-1, CYT6BJC-CM7-2, CYT6BJC-CM7-3
|
|
; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
|
|
; --------------------------------------------------------------------------------
|
|
; $Id: mencyt6bj.men 16948 2023-11-08 11:06:33Z kwisniewski $
|
|
|
|
add
|
|
menu
|
|
(
|
|
IF SOFTWARE.BUILD.BASE()>=69655.
|
|
(
|
|
popup "&CPU"
|
|
(
|
|
separator
|
|
IF CPU.FEATURE(MMU)
|
|
(
|
|
popup "[:mmu]MMU"
|
|
(
|
|
menuitem "[:mmureg]MMU Control" "MMU.view"
|
|
separator
|
|
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
|
|
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
|
|
separator
|
|
IF CPU.FEATURE(ITLBDUMP)
|
|
(
|
|
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
|
|
)
|
|
IF CPU.FEATURE(DTLBDUMP)
|
|
(
|
|
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
|
|
)
|
|
IF CPU.FEATURE(TLB0DUMP)
|
|
(
|
|
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
|
|
)
|
|
IF CPU.FEATURE(TLB1DUMP)
|
|
(
|
|
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
|
|
)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU")
|
|
(
|
|
popup "[:mmu]SMMU"
|
|
(
|
|
menuitem "[:chip]SMMU1 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU1 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU2")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU2 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU2 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU3")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU3 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU3 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU4")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU4 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU4 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU5")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU5 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU5 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU6")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU6 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU6 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
)
|
|
)
|
|
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
|
|
(
|
|
popup "[:cache]Cache"
|
|
(
|
|
IF CPU.FEATURE(L1ICACHEDUMP)
|
|
(
|
|
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
|
|
menuitem "[:cache]ICACHE List" "CACHE.List IC"
|
|
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
|
|
)
|
|
IF CPU.FEATURE(L1DCACHEDUMP)
|
|
(
|
|
separator
|
|
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
|
|
menuitem "[:cache]DCACHE List" "CACHE.List DC"
|
|
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
|
|
)
|
|
IF CPU.FEATURE(L2CACHEDUMP)
|
|
(
|
|
separator
|
|
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
|
|
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
|
|
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
|
|
)
|
|
)
|
|
)
|
|
)
|
|
popup "&Trace"
|
|
(
|
|
separator
|
|
IF COMPonent.AVAILable("ITM")
|
|
(
|
|
popup "ITM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]ITM settings..." "ITM.state"
|
|
separator
|
|
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("STM")
|
|
(
|
|
popup "STM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]STM settings..." "STM.state"
|
|
separator
|
|
menuitem "[:alist]STMTrace List" "STMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("HTM")
|
|
(
|
|
popup "HTM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]HTM settings..." "HTM.state"
|
|
separator
|
|
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("TPIU")
|
|
(
|
|
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
|
|
)
|
|
IF COMPonent.AVAILable("ETR")
|
|
(
|
|
menuitem "[:oconfig]ETR settings..."
|
|
(
|
|
PRIVATE &pdd
|
|
&pdd=OS.PDD()
|
|
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
|
|
)
|
|
)
|
|
)
|
|
popup "&Misc"
|
|
(
|
|
popup "Tools"
|
|
(
|
|
IF CPUIS64BIT()||CPU.FEATURE("SPR")
|
|
(
|
|
menuitem "ARM System Register Converter"
|
|
(
|
|
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
|
|
)
|
|
)
|
|
IF CPU.FEATURE("C15")
|
|
(
|
|
menuitem "ARM Coprocessor Converter"
|
|
(
|
|
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
|
|
)
|
|
)
|
|
)
|
|
)
|
|
popup "&Perf"
|
|
(
|
|
IF CPU.FEATURE(BMC)
|
|
(
|
|
before "Reset"
|
|
menuitem "[:bmc]Benchmark Counters" "BMC.state"
|
|
before "Reset"
|
|
separator
|
|
)
|
|
)
|
|
)
|
|
popup "Peripherals"
|
|
(
|
|
if (CORENAME()=="CORTEXM0+")
|
|
(
|
|
popup "[:chip]Core Registers (Cortex-M0+)"
|
|
(
|
|
menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M0+),System Control"""
|
|
menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M0+),Memory Protection Unit (MPU)"""
|
|
menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M0+),Nested Vectored Interrupt Controller (NVIC)"""
|
|
popup "[:chip]Debug"
|
|
(
|
|
menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M0+),Debug,Core Debug"""
|
|
menuitem "[:chip]BPU;Breakpoint Unit" "per , ""Core Registers (Cortex-M0+),Debug,Breakpoint Unit (BPU)"""
|
|
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M0+),Debug,Data Watchpoint and Trace Unit (DWT)"""
|
|
)
|
|
)
|
|
)
|
|
else
|
|
(
|
|
popup "[:chip]Core Registers (Cortex-M7F)"
|
|
(
|
|
menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M7F),System Control"""
|
|
menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M7F),Memory Protection Unit (MPU)"""
|
|
menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M7F),Nested Vectored Interrupt Controller (NVIC)"""
|
|
menuitem "[:chip]FPU;Floating-point Unit" "per , ""Core Registers (Cortex-M7F),Floating-point Unit (FPU)"""
|
|
popup "[:chip]Debug"
|
|
(
|
|
menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M7F),Debug,Core Debug"""
|
|
menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M7F),Debug,Flash Patch and Breakpoint Unit (FPB)"""
|
|
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M7F),Debug,Data Watchpoint and Trace Unit (DWT)"""
|
|
)
|
|
)
|
|
)
|
|
separator
|
|
menuitem "BACKUP;SRSS Backup Domain" "per , ""BACKUP (SRSS Backup Domain)"""
|
|
popup "CANFD;CAN Controller"
|
|
(
|
|
menuitem "CANFD0" "per , ""CANFD (CAN Controller),CANFD0"""
|
|
menuitem "CANFD1" "per , ""CANFD (CAN Controller),CANFD1"""
|
|
)
|
|
menuitem "CPUSS;CPU Subsystem" "per , ""CPUSS (CPU Subsystem)"""
|
|
menuitem "CRYPTO;Cryptography Component" "per , ""CRYPTO (Cryptography Component)"""
|
|
menuitem "DMAC;Direct Memory Access Controller" "per , ""DMAC (Direct Memory Access Controller)"""
|
|
popup "DW;Datawire Controller"
|
|
(
|
|
menuitem "DW0" "per , ""DW (Datawire Controller),DW0"""
|
|
menuitem "DW1" "per , ""DW (Datawire Controller),DW1"""
|
|
)
|
|
popup "EFUSE;OTP eFuse Memory"
|
|
(
|
|
menuitem "EFUSE_MXS40" "per , ""EFUSE (OTP eFuse Memory),EFUSE_MXS40"""
|
|
menuitem "EFUSE_DATA" "per , ""EFUSE (OTP eFuse Memory),EFUSE_DATA"""
|
|
)
|
|
popup "ETH;Ethernet Interface"
|
|
(
|
|
menuitem "ETH0" "per , ""ETH (Ethernet Interface),ETH0"""
|
|
menuitem "ETH1" "per , ""ETH (Ethernet Interface),ETH1"""
|
|
)
|
|
menuitem "EVTGEN;Event Generator" "per , ""EVTGEN (Event Generator)"""
|
|
menuitem "FAULT;Fault Structures" "per , ""FAULT (Fault Structures)"""
|
|
popup "FLASHC;Flash Controller"
|
|
(
|
|
menuitem "FLASHC" "per , ""FLASHC (Flash controller),FLASHC"""
|
|
menuitem "FLASHC1" "per , ""FLASHC (Flash controller),FLASHC1"""
|
|
)
|
|
menuitem "FLEXRAY;FlexRay Bus Interface" "per , ""FLEXRAY (FlexRay Bus Interface)"""
|
|
menuitem "GPIO;General Purpose I/O Ports And Peripheral I/O Lines" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines)"""
|
|
menuitem "HSIOM;High Speed IO Matrix" "per , ""HSIOM (High Speed IO Matrix)"""
|
|
popup "I2S;Inter-IC Sound"
|
|
(
|
|
menuitem "I2S0" "per , ""I2S (Inter-IC Sound),I2S0"""
|
|
menuitem "I2S1" "per , ""I2S (Inter-IC Sound),I2S1"""
|
|
menuitem "I2S2" "per , ""I2S (Inter-IC Sound),I2S2"""
|
|
)
|
|
menuitem "IPC;Interprocessor Communication" "per , ""IPC (Interprocessor Communication)"""
|
|
menuitem "LIN;Local Interconnect Network" "per , ""LIN (Local Interconnect Network)"""
|
|
menuitem "PASS;Programmable Analog Subsystem for S40E" "per , ""PASS (Programmable Analog Subsystem for S40E)"""
|
|
menuitem "PERI;Peripheral Interconnect" "per , ""PERI (Peripheral Interconnect)"""
|
|
menuitem "PERI_MS;Peripheral interconnect - Master Interface" "per , ""PERI_MS (Peripheral interconnect - Master Interface)"""
|
|
menuitem "PERI_PCLK;Peripheral interconnect - Peripheral Clock" "per , ""PERI_PCLK (Peripheral interconnect - Peripheral Clock)"""
|
|
menuitem "PROT;Protection" "per , ""PROT (Protection)"""
|
|
popup "SCB;Serial Communications Block (SPI/UART/I2C)"
|
|
(
|
|
menuitem "SCB0" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB0"""
|
|
menuitem "SCB1" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB1"""
|
|
menuitem "SCB2" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB2"""
|
|
menuitem "SCB3" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB3"""
|
|
menuitem "SCB4" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB4"""
|
|
menuitem "SCB5" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB5"""
|
|
menuitem "SCB6" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB6"""
|
|
menuitem "SCB7" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB7"""
|
|
menuitem "SCB8" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB8"""
|
|
menuitem "SCB9" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB9"""
|
|
menuitem "SCB10" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB10"""
|
|
)
|
|
popup "SDHC;SD/eMMC Host Controller"
|
|
(
|
|
menuitem "CORE" "per , ""SDHC (SD/eMMC Host Controller),CORE"""
|
|
menuitem "WRAP" "per , ""SDHC (SD/eMMC Host Controller),WRAP"""
|
|
)
|
|
menuitem "SMARTIO;Programmable IO Configuration" "per , ""SMARTIO (Programmable IO Configuration)"""
|
|
menuitem "SMIF;Serial Memory Interface" "per , ""SMIF (Serial Memory Interface)"""
|
|
menuitem "SRSS;SRSS Core Registers" "per , ""SRSS (SRSS Core Registers)"""
|
|
popup "TCPWM;Timer/Counter/PWM"
|
|
(
|
|
menuitem "TCPWM0" "per , ""TCPWM (Timer/Counter/PWM),TCPWM0"""
|
|
menuitem "TCPWM1" "per , ""TCPWM (Timer/Counter/PWM),TCPWM1"""
|
|
)
|
|
)
|
|
)
|