343 lines
12 KiB
Plaintext
343 lines
12 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: CYT2CL Specific Menu
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; @Props: Released
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; @Author: RSA, DAB, KRZ
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; @Changelog: 2021-11-15 RSA
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; 2022-01-20 DAB
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; 2022-09-12 KRZ
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; @Manufacturer: CYPRESS - Cypress Semiconductor Corporation
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; @Core: Cortex-M0+, Cortex-M4
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; @Chip: CYT2C97-CM0+, CYT2C97-CM4, CYT2C98-CM0+, CYT2C98-CM4, CYT2C9H-CM0+,
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; CYT2C9H-CM4, CYT2CL7-CM0+, CYT2CL7-CM4, CYT2CL8-CM0+, CYT2CL8-CM4,
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; CYT2CLH-CM0+, CYT2CLH-CM4
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; @Copyright: (C) 1989-2021 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: mencyt2cl.men 16348 2023-07-05 11:56:58Z alintner $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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if (CORENAME()=="CORTEXM4F")
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(
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popup "[:chip]Core Registers (Cortex-M4F)"
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(
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menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M4F),System Control"""
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menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M4F),Memory Protection Unit"""
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menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M4F),Nested Vectored Interrupt Controller"""
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menuitem "[:chip]FPU;Floating-point Unit" "per , ""Core Registers (Cortex-M4F),Floating-point Unit"""
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popup "[:chip]Debug"
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(
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menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M4F),Debug,Core Debug"""
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menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M4F),Debug,Flash Patch and Breakpoint Unit (FPB)"""
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menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M4F),Debug,Data Watchpoint and Trace Unit (DWT)"""
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)
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)
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)
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else if (CORENAME()=="CORTEXM0+")
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(
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popup "[:chip]Core Registers (Cortex-M0+)"
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(
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menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M0+),System Control"""
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menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M0+),Memory Protection Unit (MPU)"""
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menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M0+),Nested Vectored Interrupt Controller (NVIC)"""
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popup "[:chip]Debug"
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(
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menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M0+),Debug,Core Debug"""
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menuitem "[:chip]BPU;Breakpoint Unit" "per , ""Core Registers (Cortex-M0+),Debug,Breakpoint Unit (BPU)"""
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menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M0+),Debug,Data Watchpoint and Trace Unit (DWT)"""
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)
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)
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)
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separator
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menuitem "BACKUP;SRSS Backup Domain" "per , ""BACKUP (SRSS Backup Domain)"""
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popup "CANFD;CAN Controller"
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(
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menuitem "CANFD0" "per , ""CANFD (CAN Controller),CANFD0"""
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menuitem "CANFD1" "per , ""CANFD (CAN Controller),CANFD1"""
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)
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menuitem "CPUSS;CPU subsystem" "per , ""CPUSS (CPU subsystem)"""
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menuitem "CRYPTO;Cryptography component" "per , ""CRYPTO (Cryptography component)"""
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menuitem "CXPI" "per , ""CXPI"""
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menuitem "DMAC" "per , ""DMAC"""
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popup "DW;Datawire Controller"
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(
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menuitem "DW0" "per , ""DW (Datawire Controller),DW0"""
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menuitem "DW1" "per , ""DW (Datawire Controller),DW1"""
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)
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menuitem "EFUSE;EFUSE MXS40 registers" "per , ""EFUSE (EFUSE MXS40 registers)"""
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menuitem "EFUSE_DATA;eFUSE memory" "per , ""EFUSE_DATA (eFUSE memory)"""
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menuitem "EVTGEN;Event generator" "per , ""EVTGEN (Event generator)"""
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menuitem "FAULT;Fault structures" "per , ""FAULT (Fault structures)"""
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menuitem "FLASHC;Flash controller" "per , ""FLASHC (Flash controller)"""
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menuitem "GPIO;GPIO port control/configuration" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines)"""
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menuitem "HSIOM;High Speed IO Matrix" "per , ""HSIOM (High Speed IO Matrix)"""
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menuitem "IPC" "per , ""IPC (Interprocessor Communication)"""
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menuitem "LCD;LCD Controller Block" "per , ""LCD (LCD Controller Block)"""
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menuitem "LIN" "per , ""LIN"""
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menuitem "MIXER" "per , ""MIXER"""
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menuitem "PASS;Programmable Analog Subsystem for S40E" "per , ""PASS (Programmable Analog Subsystem for S40E)"""
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menuitem "PERI;Peripheral interconnect" "per , ""PERI (Peripheral interconnect)"""
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menuitem "PERI_MS;Peripheral interconnect master interface" "per , ""PERI_MS (Peripheral interconnect master interface)"""
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menuitem "PROT;Protection" "per , ""PROT (Protection)"""
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menuitem "PWM" "per , ""PWM"""
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popup "SCB;Serial Communications Block (SPI/UART/I2C)"
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(
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menuitem "SCB0" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB0"""
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menuitem "SCB1" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB1"""
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menuitem "SCB2" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB2"""
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menuitem "SCB3" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB3"""
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menuitem "SCB4" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB4"""
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menuitem "SCB5" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB5"""
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menuitem "SCB6" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB6"""
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menuitem "SCB7" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB7"""
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menuitem "SCB8" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB8"""
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menuitem "SCB9" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB9"""
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menuitem "SCB10" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB10"""
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menuitem "SCB11" "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB11"""
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)
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menuitem "SG" "per , ""SG"""
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menuitem "SMARTIO;Programmable IO configuration" "per , ""SMARTIO (Programmable IO configuration)"""
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menuitem "SMIF;Serial Memory Interface" "per , ""SMIF (Serial Memory Interface)"""
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menuitem "SRSS;SRSS Core Registers" "per , ""SRSS (SRSS Core Registers)"""
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menuitem "TCPWM;Timer/Counter/PWM" "per , ""TCPWM (Timer/Counter/PWM)"""
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menuitem "TDM" "per , ""TDM"""
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)
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)
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