326 lines
8.7 KiB
Plaintext
326 lines
8.7 KiB
Plaintext
; --------------------------------------------------------------------------------
|
|
; @Title: ATSAMV7x Specific Menu
|
|
; @Author: JRK, ZUO
|
|
; @Changelog:
|
|
; @Manufacturer: ATMEL - Atmel Corporation
|
|
; @Core: Cortex-M7
|
|
; @Chiplist: ATMSAMV70, ATSAMV71
|
|
; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
|
|
; --------------------------------------------------------------------------------
|
|
; $Id: menatsamv7x.men 16339 2023-07-03 13:30:14Z pegold $
|
|
|
|
add
|
|
menu
|
|
(
|
|
IF SOFTWARE.BUILD.BASE()>=69655.
|
|
(
|
|
popup "&CPU"
|
|
(
|
|
separator
|
|
IF CPU.FEATURE(MMU)
|
|
(
|
|
popup "[:mmu]MMU"
|
|
(
|
|
menuitem "[:mmureg]MMU Control" "MMU.view"
|
|
separator
|
|
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
|
|
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
|
|
separator
|
|
IF CPU.FEATURE(ITLBDUMP)
|
|
(
|
|
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
|
|
)
|
|
IF CPU.FEATURE(DTLBDUMP)
|
|
(
|
|
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
|
|
)
|
|
IF CPU.FEATURE(TLB0DUMP)
|
|
(
|
|
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
|
|
)
|
|
IF CPU.FEATURE(TLB1DUMP)
|
|
(
|
|
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
|
|
)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU")
|
|
(
|
|
popup "[:mmu]SMMU"
|
|
(
|
|
menuitem "[:chip]SMMU1 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU1 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU2")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU2 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU2 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU3")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU3 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU3 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU4")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU4 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU4 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU5")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU5 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU5 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU6")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU6 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU6 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
)
|
|
)
|
|
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
|
|
(
|
|
popup "[:cache]Cache"
|
|
(
|
|
IF CPU.FEATURE(L1ICACHEDUMP)
|
|
(
|
|
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
|
|
menuitem "[:cache]ICACHE List" "CACHE.List IC"
|
|
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
|
|
)
|
|
IF CPU.FEATURE(L1DCACHEDUMP)
|
|
(
|
|
separator
|
|
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
|
|
menuitem "[:cache]DCACHE List" "CACHE.List DC"
|
|
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
|
|
)
|
|
IF CPU.FEATURE(L2CACHEDUMP)
|
|
(
|
|
separator
|
|
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
|
|
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
|
|
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
|
|
)
|
|
)
|
|
)
|
|
)
|
|
popup "&Trace"
|
|
(
|
|
separator
|
|
IF COMPonent.AVAILable("ITM")
|
|
(
|
|
popup "ITM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]ITM settings..." "ITM.state"
|
|
separator
|
|
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("STM")
|
|
(
|
|
popup "STM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]STM settings..." "STM.state"
|
|
separator
|
|
menuitem "[:alist]STMTrace List" "STMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("HTM")
|
|
(
|
|
popup "HTM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]HTM settings..." "HTM.state"
|
|
separator
|
|
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("TPIU")
|
|
(
|
|
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
|
|
)
|
|
IF COMPonent.AVAILable("ETR")
|
|
(
|
|
menuitem "[:oconfig]ETR settings..."
|
|
(
|
|
PRIVATE &pdd
|
|
&pdd=OS.PDD()
|
|
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
|
|
)
|
|
)
|
|
)
|
|
popup "&Misc"
|
|
(
|
|
popup "Tools"
|
|
(
|
|
IF CPUIS64BIT()||CPU.FEATURE("SPR")
|
|
(
|
|
menuitem "ARM System Register Converter"
|
|
(
|
|
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
|
|
)
|
|
)
|
|
IF CPU.FEATURE("C15")
|
|
(
|
|
menuitem "ARM Coprocessor Converter"
|
|
(
|
|
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
|
|
)
|
|
)
|
|
)
|
|
)
|
|
popup "&Perf"
|
|
(
|
|
IF CPU.FEATURE(BMC)
|
|
(
|
|
before "Reset"
|
|
menuitem "[:bmc]Benchmark Counters" "BMC.state"
|
|
before "Reset"
|
|
separator
|
|
)
|
|
)
|
|
)
|
|
popup "Peripherals"
|
|
(
|
|
popup "[:chip]Core Registers (Cortex-M7F)"
|
|
(
|
|
menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M7F),System Control"""
|
|
menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M7F),Memory Protection Unit (MPU)"""
|
|
menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M7F),Nested Vectored Interrupt Controller (NVIC)"""
|
|
menuitem "[:chip]FPU;Floating-point Unit" "per , ""Core Registers (Cortex-M7F),Floating-point Unit (FPU)"""
|
|
popup "[:chip]Debug"
|
|
(
|
|
menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M7F),Debug,Core Debug"""
|
|
menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M7F),Debug,Flash Patch and Breakpoint Unit (FPB)"""
|
|
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M7F),Debug,Data Watchpoint and Trace Unit (DWT)"""
|
|
)
|
|
)
|
|
separator
|
|
menuitem "MATRIX" "per , ""MATRIX (Bus Matrix)"""
|
|
menuitem "UTMI" "per , ""UTMI (USB Transmitter Macrocell Interface)"""
|
|
menuitem "CHIPID" "per , ""CHIPID (Chip Identifier)"""
|
|
menuitem "EEFC" "per , ""EEFC (Enhanced Embedded Flash Controller)"""
|
|
menuitem "SUPC" "per , ""SUPC (Supply Controller)"""
|
|
menuitem "WDT" "per , ""WDT (Watchdog Timer)"""
|
|
menuitem "RSWDT" "per , ""RSWDT (Reinforced Safety Watchdog Timer)"""
|
|
menuitem "RSTC" "per , ""RSTC (Reset Controller)"""
|
|
menuitem "RTC" "per , ""RTC (Real-time Clock)"""
|
|
menuitem "RTT" "per , ""RTT (Real-time Timer)"""
|
|
menuitem "GPBR" "per , ""GPBR (General Purpose Backup Registers)"""
|
|
menuitem "PMC" "per , ""PMC (Power Management Controller)"""
|
|
menuitem "PIO" "per , ""PIO (Parallel Input/Output)"""
|
|
if (cpuis("ATSAMV71Q*")||cpuis("ATSAMV70Q*"))
|
|
(
|
|
menuitem "SDRAMC" "per , ""SDRAMC (SDRAM Controller)"""
|
|
)
|
|
menuitem "SMC" "per , ""SMC (Static Memory Controller)"""
|
|
menuitem "XDMAC" "per , ""XDMAC (Extensible DMA Controller)"""
|
|
menuitem "ISI" "per , ""ISI (Image Sensor Interface)"""
|
|
menuitem "USBHS" "per , ""USBHS (USB High-Speed Interface)"""
|
|
if (cpuis("ATSAMV71*"))
|
|
(
|
|
menuitem "GMAC" "per , ""GMAC (Gigabit Ethernet MAC)"""
|
|
)
|
|
if (!cpuis("ATSAMV70J*")&&!cpuis("ATSAMV71J*"))
|
|
(
|
|
menuitem "HSMCI" "per , ""HSMCI (High Speed MultiMedia Card Interface)"""
|
|
)
|
|
menuitem "QSPI" "per , ""QSPI (Quad SPI Interface)"""
|
|
if (!cpuis("ATSAMV70J*")&&!cpuis("ATSAMV71J*"))
|
|
(
|
|
menuitem "SPI" "per , ""SPI (Serial Peripheral Interface)"""
|
|
)
|
|
menuitem "TWIHS" "per , ""TWIHS (Two-wire Interface)"""
|
|
menuitem "SSC" "per , ""SSC (Synchronous Serial Controller)"""
|
|
if (!cpuis("ATSAMV71*A"))
|
|
(
|
|
menuitem "I2SC" "per , ""I2SC (Inter-IC Sound Controller)"""
|
|
)
|
|
if (!cpuis("ATSAMV70J*")&&!cpuis("ATSAMV71J*"))
|
|
(
|
|
menuitem "USART" "per , ""USART (Universal Synchronous Asynchronous Receiver Transmitter)"""
|
|
)
|
|
menuitem "UART" "per , ""UART (Universal Asynchronous Receiver Transmitter)"""
|
|
if (!cpuis("ATSAMV70J*"))
|
|
(
|
|
menuitem "MLB" "per , ""MLB (Media Local Bus)"""
|
|
)
|
|
menuitem "MCAN" "per , ""MCAN (Controller Area Network)"""
|
|
menuitem "TC" "per , ""TC (Timer Counter)"""
|
|
menuitem "PWM" "per , ""PWM (Pulse Width Modulation Controller)"""
|
|
menuitem "DACC" "per , ""DACC (Digital-to-Analog Converter Controller)"""
|
|
menuitem "ACC" "per , ""ACC (Analog Comparator Controller)"""
|
|
menuitem "SMC" "per , ""SMC (Static Memory Controller)"""
|
|
menuitem "ICM" "per , ""ICM (Integrity Check Monitor)"""
|
|
menuitem "TRNG" "per , ""TRNG (True Random Number Generator)"""
|
|
menuitem "AES" "per , ""AES (Advanced Encryption Standard)"""
|
|
)
|
|
)
|