372 lines
14 KiB
Plaintext
372 lines
14 KiB
Plaintext
; --------------------------------------------------------------------------------
|
|
; @Title: ATSAMA5D29 Specific Menu
|
|
; @Props: Released
|
|
; @Author: JDU, NEJ
|
|
; @Changelog: 2023-06-23 JDU
|
|
; 2023-11-23 NEJ
|
|
; @Manufacturer: MICROCHIP - Microchip Technology Inc.
|
|
; @Core: Cortex-A5
|
|
; @Chip: ATSAMA5D29
|
|
; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
|
|
; --------------------------------------------------------------------------------
|
|
; $Id: menatsama5d29.men 17103 2023-11-25 11:20:10Z kwisniewski $
|
|
|
|
add
|
|
menu
|
|
(
|
|
IF SOFTWARE.BUILD.BASE()>=69655.
|
|
(
|
|
popup "&CPU"
|
|
(
|
|
separator
|
|
IF CPU.FEATURE(MMU)
|
|
(
|
|
popup "[:mmu]MMU"
|
|
(
|
|
menuitem "[:mmureg]MMU Control" "MMU.view"
|
|
separator
|
|
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
|
|
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
|
|
separator
|
|
IF CPU.FEATURE(ITLBDUMP)
|
|
(
|
|
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
|
|
)
|
|
IF CPU.FEATURE(DTLBDUMP)
|
|
(
|
|
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
|
|
)
|
|
IF CPU.FEATURE(TLB0DUMP)
|
|
(
|
|
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
|
|
)
|
|
IF CPU.FEATURE(TLB1DUMP)
|
|
(
|
|
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
|
|
)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU")
|
|
(
|
|
popup "[:mmu]SMMU"
|
|
(
|
|
menuitem "[:chip]SMMU1 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU1 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU2")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU2 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU2 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU3")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU3 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU3 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU4")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU4 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU4 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU5")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU5 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU5 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU6")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU6 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU6 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
)
|
|
)
|
|
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
|
|
(
|
|
popup "[:cache]Cache"
|
|
(
|
|
IF CPU.FEATURE(L1ICACHEDUMP)
|
|
(
|
|
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
|
|
menuitem "[:cache]ICACHE List" "CACHE.List IC"
|
|
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
|
|
)
|
|
IF CPU.FEATURE(L1DCACHEDUMP)
|
|
(
|
|
separator
|
|
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
|
|
menuitem "[:cache]DCACHE List" "CACHE.List DC"
|
|
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
|
|
)
|
|
IF CPU.FEATURE(L2CACHEDUMP)
|
|
(
|
|
separator
|
|
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
|
|
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
|
|
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
|
|
)
|
|
)
|
|
)
|
|
)
|
|
popup "&Trace"
|
|
(
|
|
separator
|
|
IF COMPonent.AVAILable("ITM")
|
|
(
|
|
popup "ITM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]ITM settings..." "ITM.state"
|
|
separator
|
|
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("STM")
|
|
(
|
|
popup "STM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]STM settings..." "STM.state"
|
|
separator
|
|
menuitem "[:alist]STMTrace List" "STMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("HTM")
|
|
(
|
|
popup "HTM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]HTM settings..." "HTM.state"
|
|
separator
|
|
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("TPIU")
|
|
(
|
|
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
|
|
)
|
|
IF COMPonent.AVAILable("ETR")
|
|
(
|
|
menuitem "[:oconfig]ETR settings..."
|
|
(
|
|
PRIVATE &pdd
|
|
&pdd=OS.PDD()
|
|
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
|
|
)
|
|
)
|
|
)
|
|
popup "&Misc"
|
|
(
|
|
popup "Tools"
|
|
(
|
|
IF CPUIS64BIT()||CPU.FEATURE("SPR")
|
|
(
|
|
menuitem "ARM System Register Converter"
|
|
(
|
|
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
|
|
)
|
|
)
|
|
IF CPU.FEATURE("C15")
|
|
(
|
|
menuitem "ARM Coprocessor Converter"
|
|
(
|
|
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
|
|
)
|
|
)
|
|
)
|
|
)
|
|
popup "&Perf"
|
|
(
|
|
IF CPU.FEATURE(BMC)
|
|
(
|
|
before "Reset"
|
|
menuitem "[:bmc]Benchmark Counters" "BMC.state"
|
|
before "Reset"
|
|
separator
|
|
)
|
|
)
|
|
)
|
|
popup "Peripherals"
|
|
(
|
|
popup "[:chip]Core Registers (Cortex-A5)"
|
|
(
|
|
menuitem "[:chip]ID Registers" "per , ""Core Registers (Cortex-A5),ID Registers"""
|
|
menuitem "[:chip]System Control and Configuration" "per , ""Core Registers (Cortex-A5),System Control and Configuration"""
|
|
menuitem "[:chip]Memory Management Unit" "per , ""Core Registers (Cortex-A5),Memory Management Unit"""
|
|
menuitem "[:chip]Cache Control and Configuration" "per , ""Core Registers (Cortex-A5),Cache Control and Configuration"""
|
|
menuitem "[:chip]L2 Preload Engine" "per , ""Core Registers (Cortex-A5),L2 Preload Engine"""
|
|
menuitem "[:chip]System Performance Monitor" "per , ""Core Registers (Cortex-A5),System Performance Monitor"""
|
|
menuitem "[:chip]Debug" "per , ""Core Registers (Cortex-A5),Debug"""
|
|
)
|
|
separator
|
|
menuitem "ACC;Analog Comparator Controller" "per , ""ACC (Analog Comparator Controller)"""
|
|
menuitem "ADC;Analog-to-Digital Converter" "per , ""ADC (Analog-to-Digital Converter)"""
|
|
menuitem "AES;Advanced Encryption Standard" "per , ""AES (Advanced Encryption Standard)"""
|
|
menuitem "AESB;Advanced Encryption Standard Bridge" "per , ""AESB (Advanced Encryption Standard Bridge)"""
|
|
popup "AIC;Advanced Interrupt Controller"
|
|
(
|
|
menuitem "AIC" "per , ""AIC (Advanced Interrupt Controller),AIC"""
|
|
menuitem "SAIC" "per , ""AIC (Advanced Interrupt Controller),SAIC"""
|
|
)
|
|
menuitem "AXIMX;AXI Matrix" "per , ""AXIMX (AXI Matrix)"""
|
|
menuitem "CHIPID;Chip Identifier" "per , ""CHIPID (Chip Identifier)"""
|
|
menuitem "CLASSD;Audio Class D Amplifier" "per , ""CLASSD (Audio Class D Amplifier)"""
|
|
popup "FLEXCOM;Flexible Serial Communication Controller"
|
|
(
|
|
menuitem "FLEXCOM0" "per , ""FLEXCOM (Flexible Serial Communication Controller),FLEXCOM0"""
|
|
menuitem "FLEXCOM1" "per , ""FLEXCOM (Flexible Serial Communication Controller),FLEXCOM1"""
|
|
menuitem "FLEXCOM2" "per , ""FLEXCOM (Flexible Serial Communication Controller),FLEXCOM2"""
|
|
menuitem "FLEXCOM3" "per , ""FLEXCOM (Flexible Serial Communication Controller),FLEXCOM3"""
|
|
menuitem "FLEXCOM4" "per , ""FLEXCOM (Flexible Serial Communication Controller),FLEXCOM4"""
|
|
)
|
|
menuitem "GMAC;Ethernet MAC" "per , ""GMAC (Ethernet MAC)"""
|
|
menuitem "HSMC;Static Memory Controller" "per , ""HSMC (Static Memory Controller)"""
|
|
popup "I2SC;Inter-IC Sound Controller"
|
|
(
|
|
menuitem "I2SC0" "per , ""I2SC (Inter-IC Sound Controller),I2SC0"""
|
|
menuitem "I2SC1" "per , ""I2SC (Inter-IC Sound Controller),I2SC1"""
|
|
)
|
|
menuitem "ICM;Integrity Check Monitor" "per , ""ICM (Integrity Check Monitor)"""
|
|
menuitem "ISC;Image Sensor Controller" "per , ""ISC (Image Sensor Controller)"""
|
|
menuitem "L2CC;L2 Cache Controller" "per , ""L2CC (L2 Cache Controller)"""
|
|
menuitem "LCDC;LCD Controller" "per , ""LCDC (LCD Controller)"""
|
|
popup "MATRIX;AHB Bus Matrix"
|
|
(
|
|
menuitem "MATRIX0" "per , ""MATRIX (AHB Bus Matrix),MATRIX0"""
|
|
menuitem "MATRIX1" "per , ""MATRIX (AHB Bus Matrix),MATRIX1"""
|
|
)
|
|
popup "MCAN;Controller Area Network"
|
|
(
|
|
menuitem "MCAN0" "per , ""MCAN (Controller Area Network),MCAN0"""
|
|
menuitem "MCAN1" "per , ""MCAN (Controller Area Network),MCAN1"""
|
|
)
|
|
menuitem "MPDDRC;DDR-SDRAM Controller" "per , ""MPDDRC (DDR-SDRAM Controller)"""
|
|
menuitem "PDMIC;Pulse Density Modulation Interface Controller" "per , ""PDMIC (Pulse Density Modulation Interface Controller)"""
|
|
menuitem "PIO;Parallel Input/Output Controller" "per , ""PIO (Parallel Input/Output Controller)"""
|
|
menuitem "PIT;Periodic Interval Timer" "per , ""PIT (Periodic Interval Timer)"""
|
|
menuitem "PMC;Power Management Controller" "per , ""PMC (Power Management Controller)"""
|
|
menuitem "PTC;Peripheral Touch Controller" "per , ""PTC (Peripheral Touch Controller)"""
|
|
menuitem "PWM;Pulse Width Modulator" "per , ""PWM (Pulse Width Modulator)"""
|
|
popup "QSPI;Quad Serial Peripheral Interface"
|
|
(
|
|
menuitem "QSPI0" "per , ""QSPI (Quad Serial Peripheral Interface),QSPI0"""
|
|
menuitem "QSPI1" "per , ""QSPI (Quad Serial Peripheral Interface),QSPI1"""
|
|
)
|
|
menuitem "RSTC;Reset Controller" "per , ""RSTC (Reset Controller)"""
|
|
menuitem "RTC;Real-Time Clock" "per , ""RTC (Real-Time Clock)"""
|
|
menuitem "RXLP;Low Power Asynchronous Receiver" "per , ""RXLP (Low Power Asynchronous Receiver)"""
|
|
menuitem "SCKC;Slow Clock Controller" "per , ""SCKC (Slow Clock Controller)"""
|
|
popup "SDMMC;Secure Digital MultiMedia Card Controller"
|
|
(
|
|
menuitem "SDMMC0" "per , ""SDMMC (Secure Digital MultiMedia Card Controller),SDMMC0"""
|
|
menuitem "SDMMC1" "per , ""SDMMC (Secure Digital MultiMedia Card Controller),SDMMC1"""
|
|
)
|
|
menuitem "SECUMOD;Security Module" "per , ""SECUMOD (Security Module)"""
|
|
menuitem "SFC;Secure Fuse Controller" "per , ""SFC (Secure Fuse Controller)"""
|
|
menuitem "SFR;Special Function Registers" "per , ""SFR (Special Function Registers)"""
|
|
menuitem "SFRBU;Special Function Registers Backup" "per , ""SFRBU (Special Function Registers Backup)"""
|
|
menuitem "SHA;Secure Hash Algorithm" "per , ""SHA (Secure Hash Algorithm)"""
|
|
menuitem "SHDWC;Shutdown Controller" "per , ""SHDWC (Shutdown Controller)"""
|
|
popup "SPI;Serial Peripheral Interface"
|
|
(
|
|
menuitem "SPI0" "per , ""SPI (Serial Peripheral Interface),SPI0"""
|
|
menuitem "SPI1" "per , ""SPI (Serial Peripheral Interface),SPI1"""
|
|
)
|
|
popup "SSC;Synchronous Serial Controller"
|
|
(
|
|
menuitem "SSC0" "per , ""SSC (Synchronous Serial Controller),SSC0"""
|
|
menuitem "SSC1" "per , ""SSC (Synchronous Serial Controller),SSC1"""
|
|
)
|
|
popup "TC;Timer/Counter"
|
|
(
|
|
menuitem "TC0" "per , ""TC (Timer/Counter),TC0"""
|
|
menuitem "TC1" "per , ""TC (Timer/Counter),TC1"""
|
|
)
|
|
menuitem "TDES;Triple Data Encryption Standard" "per , ""TDES (Triple Data Encryption Standard)"""
|
|
menuitem "TRNG;True Random Number Generator" "per , ""TRNG (True Random Number Generator)"""
|
|
popup "TWIHS;Two-wire Interface"
|
|
(
|
|
menuitem "TWIHS0" "per , ""TWIHS (Two-wire Interface),TWIHS0"""
|
|
menuitem "TWIHS1" "per , ""TWIHS (Two-wire Interface),TWIHS1"""
|
|
)
|
|
popup "UART;Universal Asynchronous Receiver Transmitter"
|
|
(
|
|
menuitem "UART0" "per , ""UART (Universal Asynchronous Receiver Transmitter),UART0"""
|
|
menuitem "UART1" "per , ""UART (Universal Asynchronous Receiver Transmitter),UART1"""
|
|
menuitem "UART2" "per , ""UART (Universal Asynchronous Receiver Transmitter),UART2"""
|
|
menuitem "UART3" "per , ""UART (Universal Asynchronous Receiver Transmitter),UART3"""
|
|
menuitem "UART4" "per , ""UART (Universal Asynchronous Receiver Transmitter),UART4"""
|
|
)
|
|
menuitem "UDPHS;USB Device High Speed Port" "per , ""UDPHS (USB Device High Speed Port)"""
|
|
menuitem "WDT;Watchdog Timer" "per , ""WDT (Watchdog Timer)"""
|
|
popup "XDMAC;Extensible DMA Controller"
|
|
(
|
|
menuitem "XDMAC0" "per , ""XDMAC (Extensible DMA Controller),XDMAC0"""
|
|
menuitem "XDMAC1" "per , ""XDMAC (Extensible DMA Controller),XDMAC1"""
|
|
)
|
|
)
|
|
)
|