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Gen4_R-Car_Trace32/2_Trunk/menatsam4c.men
woody d411edd9b4 add Trace32 File
2025-10-14 09:52:32 +09:00

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; --------------------------------------------------------------------------------
; @Title: ATSAM4C Specific Menu
; @Props: Released
; @Author: ADK
; @Changelog: 2014-09-11 ADK
; 2015-05-29 STR
; @Manufacturer: ATMEL - Atmel Corporation
; @Core: Cortex-M4
; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: menatsam4c.men 16339 2023-07-03 13:30:14Z pegold $
add
menu
(
IF SOFTWARE.BUILD.BASE()>=69655.
(
popup "&CPU"
(
separator
IF CPU.FEATURE(MMU)
(
popup "[:mmu]MMU"
(
menuitem "[:mmureg]MMU Control" "MMU.view"
separator
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
separator
IF CPU.FEATURE(ITLBDUMP)
(
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
)
IF CPU.FEATURE(DTLBDUMP)
(
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
)
IF CPU.FEATURE(TLB0DUMP)
(
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
)
IF CPU.FEATURE(TLB1DUMP)
(
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
)
)
)
IF COMPonent.AVAILable("SMMU")
(
popup "[:mmu]SMMU"
(
menuitem "[:chip]SMMU1 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU1 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.StreamMapTable &(name)
)
IF COMPonent.AVAILable("SMMU2")
(
separator
menuitem "[:chip]SMMU2 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU2 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU3")
(
separator
menuitem "[:chip]SMMU3 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU3 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU4")
(
separator
menuitem "[:chip]SMMU4 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU4 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU5")
(
separator
menuitem "[:chip]SMMU5 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU5 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU6")
(
separator
menuitem "[:chip]SMMU6 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU6 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.StreamMapTable &(name)
)
)
)
)
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
(
popup "[:cache]Cache"
(
IF CPU.FEATURE(L1ICACHEDUMP)
(
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
menuitem "[:cache]ICACHE List" "CACHE.List IC"
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
)
IF CPU.FEATURE(L1DCACHEDUMP)
(
separator
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
menuitem "[:cache]DCACHE List" "CACHE.List DC"
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
)
IF CPU.FEATURE(L2CACHEDUMP)
(
separator
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
)
)
)
)
popup "&Trace"
(
separator
IF COMPonent.AVAILable("ITM")
(
popup "ITM"
(
default
menuitem "[:oconfig]ITM settings..." "ITM.state"
separator
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
)
)
IF COMPonent.AVAILable("STM")
(
popup "STM"
(
default
menuitem "[:oconfig]STM settings..." "STM.state"
separator
menuitem "[:alist]STMTrace List" "STMTrace.List"
)
)
IF COMPonent.AVAILable("HTM")
(
popup "HTM"
(
default
menuitem "[:oconfig]HTM settings..." "HTM.state"
separator
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
)
)
IF COMPonent.AVAILable("TPIU")
(
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
)
IF COMPonent.AVAILable("ETR")
(
menuitem "[:oconfig]ETR settings..."
(
PRIVATE &pdd
&pdd=OS.PDD()
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
)
)
)
popup "&Misc"
(
popup "Tools"
(
IF CPUIS64BIT()||CPU.FEATURE("SPR")
(
menuitem "ARM System Register Converter"
(
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
)
)
IF CPU.FEATURE("C15")
(
menuitem "ARM Coprocessor Converter"
(
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
)
)
)
)
popup "&Perf"
(
IF CPU.FEATURE(BMC)
(
before "Reset"
menuitem "[:bmc]Benchmark Counters" "BMC.state"
before "Reset"
separator
)
)
)
popup "Peripherals"
(
popup "[:chip]Core Registers (Cortex-M4F)"
(
menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M4F),System Control"""
menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M4F),Memory Protection Unit"""
menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M4F),Nested Vectored Interrupt Controller"""
menuitem "[:chip]FPU;Floating-point Unit" "per , ""Core Registers (Cortex-M4F),Floating-point Unit"""
popup "[:chip]Debug"
(
menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M4F),Debug,Core Debug"""
menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M4F),Debug,Flash Patch and Breakpoint Unit (FPB)"""
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M4F),Debug,Data Watchpoint and Trace Unit (DWT)"""
)
)
separator
menuitem "RSTC" "per , ""RSTC (Reset Controller)"""
menuitem "RTT" "per , ""RTT (Real-time Timer)"""
menuitem "RTC" "per , ""RTC (Real-time Clock)"""
menuitem "WDT" "per , ""WDT (Watchdog Timer)"""
menuitem "RSWDT" "per , ""RSWDT (Reinforced Safety Watchdog Timer)"""
menuitem "SUPC" "per , ""SUPC (Supply Controller)"""
menuitem "GPBR" "per , ""GPBR (General Purpose Backup Registers)"""
menuitem "EEFC" "per , ""EEFC (Enhanced Embedded Flash Controller)"""
menuitem "CMCC" "per , ""CMCC (Cortex M Cache Controller)"""
menuitem "IPC" "per , ""IPC (Inter-processor Communication Interface)"""
menuitem "MATRIX" "per , ""MATRIX (AHB Bus Matrix User Interface)"""
if ((cpu()=="ATSAM4C16C-CORE0")||(cpu()=="ATSAM4C8C-CORE0")||(cpu()=="ATSAM4CMP16C-CORE0")||(cpu()=="ATSAM4CMP8C-CORE0")||(cpu()=="ATSAM4CMS8C-CORE0")||(cpu()=="ATSAM4CMS16C-CORE0"))
(
menuitem "SMC 0" "per , ""SMC 0 (Static Memory Controller 0)"""
)
else
(
menuitem "SMC 1" "per , ""SMC 1 (Static Memory Controller 1)"""
)
menuitem "PMC" "per , ""PMC (Power Management Controller)"""
menuitem "CHIPID" "per , ""CHIPID (Chip Identifier)"""
menuitem "PIO" "per , ""PIO (Parallel Input/Output"""
if (cpu()=="ATSAM4C16C-CORE0"||cpu()=="ATSAM4C8C-CORE0")
(
menuitem "SPI 0" "per , ""SPI 0 (Serial Peripheral Interface 0)"""
)
if (cpu()=="ATSAM4C16C-CORE1"||cpu()=="ATSAM4C8C-CORE1")
(
menuitem "SPI 1" "per , ""SPI 1 (Serial Peripheral Interface 1)"""
)
if (cpu()=="ATSAM4CMP16C-CORE0"||cpu()=="ATSAM4CMP8C-CORE0"||cpu()=="ATSAM4CMS8C-CORE0"||cpu()=="ATSAM4CMS16C-CORE0")
(
menuitem "SPI" "per , ""SPI (Serial Peripheral Interface)"""
)
if (cpu()=="ATSAM4C16C-CORE0"||cpu()=="ATSAM4C8C-CORE0"||cpu()=="ATSAM4CMP16C-CORE0"||cpu()=="ATSAM4CMP8C-CORE0"||cpu()=="ATSAM4CMS8C-CORE0"||cpu()=="ATSAM4CMS16C-CORE0")
(
menuitem "TWI" "per , ""TWI (Two-Wire Interface)"""
)
if (cpu()=="ATSAM4C16C-CORE0"||cpu()=="ATSAM4C8C-CORE0"||cpu()=="ATSAM4CMP16C-CORE0"||cpu()=="ATSAM4CMP8C-CORE0"||cpu()=="ATSAM4CMS8C-CORE0"||cpu()=="ATSAM4CMS16C-CORE0")
(
menuitem "UART 0" "per , ""UART 0 (Universal Asynchronous Receiver Transmitter 0)"""
)
else
(
menuitem "UART 1" "per , ""UART 1 (Universal Asynchronous Receiver Transmitter 1)"""
)
if (cpu()=="ATSAM4C16C-CORE0"||cpu()=="ATSAM4C8C-CORE0"||cpu()=="ATSAM4CMP16C-CORE0"||cpu()=="ATSAM4CMP8C-CORE0"||cpu()=="ATSAM4CMS8C-CORE0"||cpu()=="ATSAM4CMS16C-CORE0")
(
menuitem "USART" "per , ""USART (Universal Synchronous Asynchronous Receiver Transmitter)"""
menuitem "TC" "per , ""TC (Timer Counter)"""
)
if (cpu()=="ATSAM4C16C-CORE1"||cpu()=="ATSAM4C8C-CORE1"||cpu()=="ATSAM4CMP16C-CORE1"||cpu()=="ATSAM4CMP8C-CORE1"||cpu()=="ATSAM4CMS8C-CORE1"||cpu()=="ATSAM4CMS16C-CORE1")
(
menuitem "PWM" "per , ""PWM (Pulse Width Modulation Controller)"""
)
if (cpu()=="ATSAM4C16C-CORE0"||cpu()=="ATSAM4C8C-CORE0"||cpu()=="ATSAM4CMP16C-CORE0"||cpu()=="ATSAM4CMP8C-CORE0"||cpu()=="ATSAM4CMS8C-CORE0"||cpu()=="ATSAM4CMS16C-CORE0")
(
menuitem "SLCDC" "per , ""SLCDC (Segment Liquid Crystal Display Controller Interface)"""
menuitem "ADC" "per , ""ADC (Analog to Digital Converter)"""
menuitem "AES" "per , ""AES (Advanced Encryption Standard)"""
menuitem "ICM" "per , ""ICM (Integrity Check Monitor)"""
menuitem "TRNG" "per , ""TRNG (True Random Number Generator)"""
)
)
)
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