346 lines
12 KiB
Plaintext
346 lines
12 KiB
Plaintext
; --------------------------------------------------------------------------------
|
|
; @Title: AT91SAM9N12 Specific Menu
|
|
; @Props: Released
|
|
; @Author: BUJ, RAF
|
|
; @Changelog: 2012-11-13
|
|
; @Manufacturer: ATMEL - Atmel Corporation
|
|
; @Core: ARM926EJ-S
|
|
; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
|
|
; --------------------------------------------------------------------------------
|
|
; $Id: menat91sam9n.men 16339 2023-07-03 13:30:14Z pegold $
|
|
|
|
add
|
|
menu
|
|
(
|
|
IF SOFTWARE.BUILD.BASE()>=69655.
|
|
(
|
|
popup "&CPU"
|
|
(
|
|
separator
|
|
IF CPU.FEATURE(MMU)
|
|
(
|
|
popup "[:mmu]MMU"
|
|
(
|
|
menuitem "[:mmureg]MMU Control" "MMU.view"
|
|
separator
|
|
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
|
|
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
|
|
separator
|
|
IF CPU.FEATURE(ITLBDUMP)
|
|
(
|
|
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
|
|
)
|
|
IF CPU.FEATURE(DTLBDUMP)
|
|
(
|
|
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
|
|
)
|
|
IF CPU.FEATURE(TLB0DUMP)
|
|
(
|
|
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
|
|
)
|
|
IF CPU.FEATURE(TLB1DUMP)
|
|
(
|
|
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
|
|
)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU")
|
|
(
|
|
popup "[:mmu]SMMU"
|
|
(
|
|
menuitem "[:chip]SMMU1 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU1 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU2")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU2 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU2 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU3")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU3 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU3 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU4")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU4 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU4 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU5")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU5 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU5 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("SMMU6")
|
|
(
|
|
separator
|
|
menuitem "[:chip]SMMU6 Registers"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
|
|
SMMU.Register.Global &(name)
|
|
)
|
|
menuitem "[:mmureg]SMMU6 StreamMapTable"
|
|
(
|
|
PRIVATE &name
|
|
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
|
|
SMMU.StreamMapTable &(name)
|
|
)
|
|
)
|
|
)
|
|
)
|
|
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
|
|
(
|
|
popup "[:cache]Cache"
|
|
(
|
|
IF CPU.FEATURE(L1ICACHEDUMP)
|
|
(
|
|
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
|
|
menuitem "[:cache]ICACHE List" "CACHE.List IC"
|
|
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
|
|
)
|
|
IF CPU.FEATURE(L1DCACHEDUMP)
|
|
(
|
|
separator
|
|
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
|
|
menuitem "[:cache]DCACHE List" "CACHE.List DC"
|
|
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
|
|
)
|
|
IF CPU.FEATURE(L2CACHEDUMP)
|
|
(
|
|
separator
|
|
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
|
|
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
|
|
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
|
|
)
|
|
)
|
|
)
|
|
)
|
|
popup "&Trace"
|
|
(
|
|
separator
|
|
IF COMPonent.AVAILable("ITM")
|
|
(
|
|
popup "ITM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]ITM settings..." "ITM.state"
|
|
separator
|
|
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("STM")
|
|
(
|
|
popup "STM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]STM settings..." "STM.state"
|
|
separator
|
|
menuitem "[:alist]STMTrace List" "STMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("HTM")
|
|
(
|
|
popup "HTM"
|
|
(
|
|
default
|
|
menuitem "[:oconfig]HTM settings..." "HTM.state"
|
|
separator
|
|
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
|
|
)
|
|
)
|
|
IF COMPonent.AVAILable("TPIU")
|
|
(
|
|
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
|
|
)
|
|
IF COMPonent.AVAILable("ETR")
|
|
(
|
|
menuitem "[:oconfig]ETR settings..."
|
|
(
|
|
PRIVATE &pdd
|
|
&pdd=OS.PDD()
|
|
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
|
|
)
|
|
)
|
|
)
|
|
popup "&Misc"
|
|
(
|
|
popup "Tools"
|
|
(
|
|
IF CPUIS64BIT()||CPU.FEATURE("SPR")
|
|
(
|
|
menuitem "ARM System Register Converter"
|
|
(
|
|
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
|
|
)
|
|
)
|
|
IF CPU.FEATURE("C15")
|
|
(
|
|
menuitem "ARM Coprocessor Converter"
|
|
(
|
|
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
|
|
)
|
|
)
|
|
)
|
|
)
|
|
popup "&Perf"
|
|
(
|
|
IF CPU.FEATURE(BMC)
|
|
(
|
|
before "Reset"
|
|
menuitem "[:bmc]Benchmark Counters" "BMC.state"
|
|
before "Reset"
|
|
separator
|
|
)
|
|
)
|
|
)
|
|
popup "Peripherals"
|
|
(
|
|
popup "[:chip]Core"
|
|
(
|
|
menuitem "[:chip]ID Registers" "per , ""ARM Core Registers,ID Registers"""
|
|
menuitem "[:chip]MMU Control and Configuration" "per , ""ARM Core Registers,MMU Control and Configuration"""
|
|
menuitem "[:chip]Cache Control and Configuration" "per , ""ARM Core Registers,Cache Control and Configuration"""
|
|
menuitem "[:chip]TCM Control and Configuration" "per , ""ARM Core Registers,TCM Control and Configuration"""
|
|
menuitem "[:chip]Test and Debug" "per , ""ARM Core Registers,Test and Debug"""
|
|
menuitem "[:chip]ICEbreaker" "per , ""ARM Core Registers,ICEbreaker"""
|
|
)
|
|
separator
|
|
menuitem "AIC" "per , ""AIC (Advanced Interrupt Controller)"""
|
|
menuitem "BSC" "per , ""BSC (Boot Sequence Controller)"""
|
|
menuitem "RSTC" "per , ""RSTC (Reset Controller)"""
|
|
menuitem "RTC" "per , ""RTC (Real Time Clock)"""
|
|
menuitem "PIT" "per , ""PIT (Periodic Interval Timer)"""
|
|
menuitem "WDT" "per , ""WDT (Watchdog Timer)"""
|
|
menuitem "SHDWC" "per , ""SHDWC (Shutdown Controller)"""
|
|
menuitem "GPBR" "per , ""GPBR (General Purpose Backup Registers)"""
|
|
menuitem "SCKC" "per , ""SCKC (Slow Clock Controller)"""
|
|
menuitem "PMC" "per , ""PMC (Power Management Controller)"""
|
|
popup "PIO"
|
|
(
|
|
menuitem "PIO A" "per , ""PIO (Parallel Input/Output Controller),PIO A"""
|
|
menuitem "PIO B" "per , ""PIO (Parallel Input/Output Controller),PIO B"""
|
|
menuitem "PIO C" "per , ""PIO (Parallel Input/Output Controller),PIO C"""
|
|
menuitem "PIO D" "per , ""PIO (Parallel Input/Output Controller),PIO D"""
|
|
)
|
|
menuitem "DBGU" "per , ""DBGU (Debug Unit)"""
|
|
menuitem "FUSE" "per , ""FUSE (UMC Fuse Controller)"""
|
|
menuitem "MATRIX" "per , ""MATRIX (Bus Matrix)"""
|
|
menuitem "PMECC" "per , ""PMECC (Programmable Multibit ECC Controller)"""
|
|
menuitem "PMERRLOC" "per , ""PMERRLOC (Programmable Multibit ECC Error Location)"""
|
|
popup "SMC"
|
|
(
|
|
menuitem "CS0" "per , ""SMC (Static Memory Controller),CS0"""
|
|
menuitem "CS1" "per , ""SMC (Static Memory Controller),CS1"""
|
|
menuitem "CS2" "per , ""SMC (Static Memory Controller),CS2"""
|
|
menuitem "CS3" "per , ""SMC (Static Memory Controller),CS3"""
|
|
menuitem "CS4" "per , ""SMC (Static Memory Controller),CS4"""
|
|
menuitem "CS5" "per , ""SMC (Static Memory Controller),CS5"""
|
|
menuitem "Delay I/O" "per , ""SMC (Static Memory Controller),Delay I/O Registers"""
|
|
menuitem "Write Protect Registers" "per , ""SMC (Static Memory Controller),Write Protect Registers"""
|
|
)
|
|
menuitem "DDRSDRC" "per , ""DDRSDRC (DDR/SDR SDRAM Controller)"""
|
|
menuitem "DMAC" "per , ""DMAC (Direct Memory Access Controller)"""
|
|
menuitem "UDP" "per , ""UDP (USB Device Port)"""
|
|
popup "UHP OHCI"
|
|
(
|
|
menuitem "Control and Status Partition" "per , ""UHP (USB Host Port),Control and Status Partition"""
|
|
menuitem "Memory Pointer Partition" "per , ""UHP (USB Host Port),Memory Pointer Partition"""
|
|
menuitem "Frame Counter Partition" "per , ""UHP (USB Host Port),Frame Counter Partition"""
|
|
menuitem "Root Hub Partition" "per , ""UHP (USB Host Port)),Root Hub Partition"""
|
|
)
|
|
menuitem "HSMCI" "per , ""HSMCI (High Speed MultiMedia Card Interface)"""
|
|
popup "SPI"
|
|
(
|
|
menuitem "SPI0" "per , ""SPI (Serial Peripheral Interface),SPI0"""
|
|
menuitem "SPI1" "per , ""SPI (Serial Peripheral Interface),SPI1"""
|
|
)
|
|
popup "TC"
|
|
(
|
|
menuitem "TC Channel 0" "per , ""TC (Timer/Counter),TC Channel 0"""
|
|
menuitem "TC Channel 1" "per , ""TC (Timer/Counter),TC Channel 1"""
|
|
menuitem "TC Channel 2" "per , ""TC (Timer/Counter),TC Channel 2"""
|
|
menuitem "Block Registers (TC0 - TC2)" "per , ""TC (Timer/Counter),Block Registers (TC0 - TC2)"""
|
|
menuitem "TC Channel 3" "per , ""TC (Timer/Counter),TC Channel 3"""
|
|
menuitem "TC Channel 4" "per , ""TC (Timer/Counter),TC Channel 4"""
|
|
menuitem "TC Channel 5" "per , ""TC (Timer/Counter),TC Channel 5"""
|
|
menuitem "Block Registers (TC3 - TC5)" "per , ""TC (Timer/Counter),Block Registers (TC3 - TC5)"""
|
|
)
|
|
menuitem "PWM" "per , ""PWM (Pulse Width Modulation Controller)"""
|
|
popup "TWI"
|
|
(
|
|
menuitem "TWI 1" "per , ""TWI (Two-wire Interface),TWI 1"""
|
|
menuitem "TWI 2" "per , ""TWI (Two-wire Interface),TWI 2"""
|
|
)
|
|
popup "USART"
|
|
(
|
|
menuitem "USART0" "per , ""USART (Universal Synchronous Asynchronous Receiver Transmitter),USART0"""
|
|
menuitem "USART1" "per , ""USART (Universal Synchronous Asynchronous Receiver Transmitter),USART1"""
|
|
menuitem "USART2" "per , ""USART (Universal Synchronous Asynchronous Receiver Transmitter),USART2"""
|
|
menuitem "USART3" "per , ""USART (Universal Synchronous Asynchronous Receiver Transmitter),USART3"""
|
|
)
|
|
popup "UART"
|
|
(
|
|
menuitem "UART0" "per , ""UART (Universal Asynchronous Receiver Transceiver),UART0"""
|
|
menuitem "UART1" "per , ""UART (Universal Asynchronous Receiver Transceiver),UART1"""
|
|
)
|
|
menuitem "ADC" "per , ""ADC (Analog-to-Digital Converter)"""
|
|
menuitem "SSC" "per , ""SSC (Synchronous Serial Controller)"""
|
|
menuitem "LCDC" "per , ""LCDC (LCD Controller)"""
|
|
menuitem "TRNG" "per , ""TRNG (True Random Number Generator)"""
|
|
)
|
|
)
|