334 lines
9.5 KiB
Plaintext
334 lines
9.5 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: AT91SAM3U1C/2C/4C/1E/2E/4E Specific Menu
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; @Props: Released
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; @Author: BOB
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; @Changelog: 2009-09-30 BOB
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; @Manufacturer: ATMEL - Atmel Corporation
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; @Core: Cortex-M3
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; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: menat91sam3u.men 16339 2023-07-03 13:30:14Z pegold $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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popup "[:chip]Core Registers (Cortex-M3)"
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(
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menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M3),System Control"""
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menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M3),Memory Protection Unit"""
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menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M3),Nested Vectored Interrupt Controller"""
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popup "[:chip]Debug"
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(
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menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M3),Debug,Core Debug"""
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menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M3),Debug,Flash Patch and Breakpoint Unit (FPB)"""
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menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M3),Debug,Data Watchpoint and Trace Unit (DWT)"""
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)
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)
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separator
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menuitem "RSTC" "per , ""RSTC (Reset Controller)"""
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menuitem "Real-time Timer" "per , ""Real-time Timer"""
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menuitem "RTC" "per , ""RTC (Real-time Clock)"""
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menuitem "WDT" "per , ""WDT (Watchdog Timer)"""
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menuitem "SUPC" "per , ""SUPC (Supply Controller)"""
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menuitem "GPBR" "per , ""GPBR (General Purpose Backup Registers)"""
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popup "EEFC"
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(
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menuitem "EFC 0" "per , ""EEFC (Enhanced Embedded Flash Controller),EFC 0"""
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menuitem "EFC 1" "per , ""EEFC (Enhanced Embedded Flash Controller),EFC 1"""
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)
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menuitem "MATRIX" "per , ""MATRIX (Bus Matrix)"""
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menuitem "SMC" "per , ""SMC (Static Memory Controller)"""
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menuitem "PMC" "per , ""PMC (Power Management Controller)"""
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menuitem "CHIPID" "per , ""CHIPID (Chip Identifier)"""
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popup "PIO"
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(
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menuitem "Port A" "per , ""PIO (Parallel Input/Output),Port A"""
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menuitem "Port B" "per , ""PIO (Parallel Input/Output),Port B"""
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if (cpu()=="AT91SAM3U1E"||cpu()=="AT91SAM3U2E"||cpu()=="AT91SAM3U4E")
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(
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menuitem "Port C" "per , ""PIO (Parallel Input/Output),Port C"""
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)
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)
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menuitem "SSC" "per , ""SSC (Synchronous Serial Controller)"""
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menuitem "SPI" "per , ""SPI (Serial Peripheral Interface)"""
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popup "TWI"
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(
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menuitem "TWI 0" "per , ""TWI (Two-wire Interface),TWI 0"""
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if (cpu()=="AT91SAM3U1E"||cpu()=="AT91SAM3U2E"||cpu()=="AT91SAM3U4E")
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(
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menuitem "TWI 1" "per , ""TWI (Two-wire Interface),TWI 1"""
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)
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)
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menuitem "UART" "per , ""UART (Universal Asynchronous Receiver Transmitter)"""
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popup "USART"
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(
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menuitem "USART 0" "per , ""USART (Universal Synchronous Asynchronous Receiver Transmitter),USART 0"""
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menuitem "USART 1" "per , ""USART (Universal Synchronous Asynchronous Receiver Transmitter),USART 1"""
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menuitem "USART 2" "per , ""USART (Universal Synchronous Asynchronous Receiver Transmitter),USART 2"""
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if (cpu()=="AT91SAM3U1E"||cpu()=="AT91SAM3U2E"||cpu()=="AT91SAM3U4E")
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(
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menuitem "USART 3" "per , ""USART (Universal Synchronous Asynchronous Receiver Transmitter),USART 3"""
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)
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)
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popup "TC"
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(
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menuitem "Block Register" "per , ""TC (Timer Counter),Block Register"""
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menuitem "TC Channel 0" "per , ""TC (Timer Counter),TC Channel 0"""
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menuitem "TC Channel 1" "per , ""TC (Timer Counter),TC Channel 1"""
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menuitem "TC Channel 2" "per , ""TC (Timer Counter),TC Channel 2"""
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)
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menuitem "HSMCI" "per , ""HSMCI (High Speed MultiMedia Card Interface)"""
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popup "PWM"
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(
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menuitem "Common Registers" "per , ""PWM (Pulse Width Modulation Controller),Common Registers"""
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menuitem "Comparison Registers" "per , ""PWM (Pulse Width Modulation Controller),Comparison Registers"""
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menuitem "Channel 0" "per , ""PWM (Pulse Width Modulation Controller),Channel 0"""
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menuitem "Channel 1" "per , ""PWM (Pulse Width Modulation Controller),Channel 1"""
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menuitem "Channel 2" "per , ""PWM (Pulse Width Modulation Controller),Channel 2"""
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menuitem "Channel 3" "per , ""PWM (Pulse Width Modulation Controller),Channel 3"""
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menuitem "PDC" "per , ""PWM (Pulse Width Modulation Controller),PDC (Peripheral DMA Controller)"""
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)
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menuitem "UDPHS" "per , ""UDPHS (USB High Speed Device Port)"""
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menuitem "DMAC" "per , ""DMAC (Direct Memory Access Controller)"""
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menuitem "ADC12B" "per , ""ADC12B (12-bit Analog-to-Digital Converter)"""
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menuitem "ADC" "per , ""ADC (Analog-to-Digital Converter)"""
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)
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)
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