335 lines
10 KiB
Plaintext
335 lines
10 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: Apollo 2 Specific Menu
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; @Props: Released
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; @Author: STR, KWI, KRZ, JDU
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; @Changelog: 2017-12-13 STR
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; 2020-07-24 KWI
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; 2022-02-15 KRZ
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; 2023-02-23 JDU
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; @Manufacturer: AMBIQ - Ambiq Micro, Inc.
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; @Core: Cortex-M4F
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; @Chip: AMAPH1KK, AMA2B1KK
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; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: menapollo2.men 16339 2023-07-03 13:30:14Z pegold $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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popup "[:chip]Core Registers (Cortex-M4F)"
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(
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menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M4F),System Control"""
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menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M4F),Memory Protection Unit"""
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menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M4F),Nested Vectored Interrupt Controller"""
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menuitem "[:chip]FPU;Floating-point Unit" "per , ""Core Registers (Cortex-M4F),Floating-point Unit"""
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popup "[:chip]Debug"
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(
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menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M4F),Debug,Core Debug"""
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menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M4F),Debug,Flash Patch and Breakpoint Unit (FPB)"""
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menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M4F),Debug,Data Watchpoint and Trace Unit (DWT)"""
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)
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)
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separator
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if cpuis("AMAPH1KK")
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(
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menuitem "PWRCTRL;PWR Controller Register Bank" "per , ""PWRCTRL (PWR Controller Register Bank)"""
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menuitem "ITM;Instrumentation Trace Macrocell" "per , ""ITM (Instrumentation Trace Macrocell)"""
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menuitem "MCUCTRL;MCU Miscellaneous Control Logic" "per , ""MCUCTRL (MCU Miscellaneous Control Logic)"""
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menuitem "CACHECTRL;Flash Cache Controller" "per , ""CACHECTRL (Flash Cache Controller)"""
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menuitem "FLASHCTRL;Flash Memory Controller" "per , ""FLASHCTRL (Flash Memory Controller)"""
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popup "I2C Master;I2C/SPI Master"
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(
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menuitem "I2C0 Master" "per , ""I2C Master (I2C/SPI Master),I2C0 Master"""
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menuitem "I2C1 Master" "per , ""I2C Master (I2C/SPI Master),I2C1 Master"""
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menuitem "I2C2 Master" "per , ""I2C Master (I2C/SPI Master),I2C2 Master"""
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menuitem "I2C3 Master" "per , ""I2C Master (I2C/SPI Master),I2C3 Master"""
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menuitem "I2C4 Master" "per , ""I2C Master (I2C/SPI Master),I2C4 Master"""
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menuitem "I2C5 Master" "per , ""I2C Master (I2C/SPI Master),I2C5 Master"""
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)
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menuitem "I2C Slave;I2C/SPI Slave" "per , ""I2C Slave (I2C/SPI Slave)"""
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menuitem "PDM;PDM Audio" "per , ""PDM (PDM Audio)"""
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menuitem "GPIO;General Purpose IO" "per , ""GPIO (General Purpose IO)"""
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menuitem "CLKGEN;Clock Generator" "per , ""CLKGEN (Clock Generator)"""
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menuitem "RTC;Real Time Clock" "per , ""RTC (Real Time Clock)"""
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menuitem "CTIMER;Counter/Timer" "per , ""CTIMER (Counter/Timer)"""
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menuitem "STIMER;System Timer" "per , ""STIMER (System Timer)"""
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menuitem "WDT;Watchdog Timer" "per , ""WDT (Watchdog Timer)"""
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menuitem "RSTGEN;MCU Reset Generator" "per , ""RSTGEN (MCU Reset Generator)"""
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popup "UART;Serial UART"
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(
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menuitem "UART0" "per , ""UART (Serial UART),UART0"""
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menuitem "UART1" "per , ""UART (Serial UART),UART1"""
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)
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menuitem "ADC;Analog to Digital Converter" "per , ""ADC (Analog to Digital Converter)"""
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menuitem "VCOMP;Voltage Comparator Module" "per , ""VCOMP (Voltage Comparator Module)"""
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)
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else if cpuis("AMA2B1KK")
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(
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menuitem "ADC" "per , ""ADC (Analog Digital Converter Control)"""
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menuitem "CACHECTRL" "per , ""CACHECTRL (Flash Cache Controller)"""
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menuitem "CLKGEN" "per , ""CLKGEN (Clock Generator)"""
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menuitem "CTIMER" "per , ""CTIMER (Counter/Timer)"""
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menuitem "GPIO" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines)"""
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popup "IOMSTR (I2C/SPI Master)"
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(
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menuitem "IOMSTR0" "per , ""IOMSTR (I2C/SPI Master),IOMSTR0"""
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menuitem "IOMSTR1" "per , ""IOMSTR (I2C/SPI Master),IOMSTR1"""
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menuitem "IOMSTR2" "per , ""IOMSTR (I2C/SPI Master),IOMSTR2"""
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menuitem "IOMSTR3" "per , ""IOMSTR (I2C/SPI Master),IOMSTR3"""
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menuitem "IOMSTR4" "per , ""IOMSTR (I2C/SPI Master),IOMSTR4"""
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menuitem "IOMSTR5" "per , ""IOMSTR (I2C/SPI Master),IOMSTR5"""
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)
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menuitem "IOSLAVE" "per , ""IOSLAVE (I2C/SPI Slave)"""
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menuitem "MCUCTRL" "per , ""MCUCTRL (MCU Miscellaneous Control Logic)"""
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menuitem "PDM" "per , ""PDM (Pulse Density Modulation (Digital Microphone) Interface)"""
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menuitem "PWRCTRL" "per , ""PWRCTRL (PWR Controller Register Bank)"""
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menuitem "RSTGEN" "per , ""RSTGEN (MCU Reset Generator)"""
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menuitem "RTC" "per , ""RTC (Real-time Counter)"""
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popup "UART (Universal Asynchronous Receiver/Transmitter)"
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(
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menuitem "UART0" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART0"""
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menuitem "UART1" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART1"""
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)
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menuitem "VCOMP" "per , ""VCOMP (Voltage Comparator)"""
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menuitem "WDT" "per , ""WDT (Watchdog Timer Unit)"""
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)
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)
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)
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