1179 lines
62 KiB
Plaintext
1179 lines
62 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: AM65xx Specific Menu
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; @Props: Released
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; @Author: KOL
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; @Changelog: 2019-01-09 KOL
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; 2019-12-06 KOL
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; @Manufacturer: TI - Texas Instruments
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; @Core: Cortex-A53, Cortex-R5F
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; @Chip: AM6526, AM6526-CR7, AM6527-CR7, AM6528, AM6528-CR7, AM6546, DRA804M-CR7
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; AM6546-CR7, AM6548, AM6548-CR7, DRA802M, DRA802M-CR7, DRA804M, AM6527
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; @Copyright: (C) 1989-2019 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: menam65xx_es1.men 16339 2023-07-03 13:30:14Z pegold $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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if (CORENAME()!="PRU")
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(
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if (CORENAME()=="CORTEXA53")
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(
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popup "[:chip]Core Registers (Cortex-A53)"
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(
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menuitem "[:chip]ID Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,ID Registers"""
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menuitem "[:chip]System Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,System Control and Configuration"""
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menuitem "[:chip]Memory Management Unit[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Memory Management Unit"""
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menuitem "[:chip]Virtualization Extensions[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Virtualization Extensions"""
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menuitem "[:chip]Cache Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,System Performance Monitor"""
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menuitem "[:chip]System Timer Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,System Timer Registers"""
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menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Generic Interrupt Controller CPU Interface"""
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separator
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menuitem "[:chip]Debug Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Debug Registers"""
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separator
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menuitem "[:chip]Breakpoint Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Control Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Watchpoint Control Registers"""
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separator
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menuitem "[:chip]ID Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,ID Registers"""
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menuitem "[:chip]System Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,System Control and Configuration"""
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menuitem "[:chip]Memory Management Unit[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Memory Management Unit"""
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menuitem "[:chip]Virtualization Extensions[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Virtualization Extensions"""
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menuitem "[:chip]Cache Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,System Performance Monitor"""
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menuitem "[:chip]System Timer Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,System Timer Registers"""
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menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Generic Interrupt Controller CPU Interface"""
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separator
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menuitem "[:chip]Debug Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Debug Registers"""
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separator
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menuitem "[:chip]Breakpoint Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Control Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Watchpoint Control Registers"""
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separator
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menuitem "[:chip]Interrupt Controller (GIC-500)" "per , ""Core Registers (Cortex-A53),Interrupt Controller (GIC-500)"""
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)
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)
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else
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(
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popup "[:chip]Core Registers (Cortex-R5F)"
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(
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menuitem "[:chip]ID Registers" "per , ""Core Registers (Cortex-R5F),ID Registers"""
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menuitem "[:chip]System Control and Configuration" "per , ""Core Registers (Cortex-R5F),System Control and Configuration"""
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menuitem "[:chip]MPU Control and Configuration" "per , ""Core Registers (Cortex-R5F),MPU Control and Configuration"""
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menuitem "[:chip]Cache Control and Configuration" "per , ""Core Registers (Cortex-R5F),Cache Control and Configuration"""
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menuitem "[:chip]TCM Control and Configuration" "per , ""Core Registers (Cortex-R5F),TCM Control and Configuration"""
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menuitem "[:chip]System Performance Monitor" "per , ""Core Registers (Cortex-R5F),System Performance Monitor"""
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separator
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menuitem "[:chip]Debug Registers" "per , ""Core Registers (Cortex-R5F),Debug Registers"""
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menuitem "[:chip]Breakpoint Registers" "per , ""Core Registers (Cortex-R5F),Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Control Registers" "per , ""Core Registers (Cortex-R5F),Watchpoint Control Registers"""
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)
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)
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separator
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popup "ADC"
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(
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popup "MCU_ADC_ECC"
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(
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menuitem "MCU_ADC0_ECC" "per , ""ADC,MCU_ADC_ECC,MCU_ADC0_ECC"""
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menuitem "MCU_ADC1_ECC" "per , ""ADC,MCU_ADC_ECC,MCU_ADC1_ECC"""
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)
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popup "MCU_ADC_FIFO"
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(
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menuitem "MCU_ADC0_FIFO" "per , ""ADC,MCU_ADC_FIFO,MCU_ADC0_FIFO"""
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menuitem "MCU_ADC1_FIFO" "per , ""ADC,MCU_ADC_FIFO,MCU_ADC1_FIFO"""
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)
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popup "MCU_ADC"
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(
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menuitem "MCU_ADC0" "per , ""ADC,MCU_ADC,MCU_ADC0"""
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menuitem "MCU_ADC1" "per , ""ADC,MCU_ADC,MCU_ADC1"""
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)
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)
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popup "CALSS"
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(
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menuitem "CAL" "per , ""CALSS,CAL"""
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)
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popup "CAMERARX"
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(
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menuitem "CAMERARX0" "per , ""CAMERARX,CAMERARX0"""
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)
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popup "PSILSS_CFG_MMRS"
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(
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menuitem "PSILSS0_CFG_MMRS2" "per , ""PSILSS_CFG_MMRS,PSILSS0_CFG_MMRS2"""
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menuitem "PSILSS0_CFG_MMRS1" "per , ""PSILSS_CFG_MMRS,PSILSS0_CFG_MMRS1"""
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)
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popup "PSI_L_CFG_PROXY"
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(
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menuitem "MCU_NAVSS0_UDMASS_PSILSS_CFG0_PROXY" "per , ""PSI_L_CFG_PROXY,MCU_NAVSS0_UDMASS_PSILSS_CFG0_PROXY"""
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menuitem "NAVSS0_UDMASS_PSILCFG0_CFG_PROXY" "per , ""PSI_L_CFG_PROXY,NAVSS0_UDMASS_PSILCFG0_CFG_PROXY"""
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)
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popup "Firewall_Region"
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(
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menuitem "PSRAM0" "per , ""Firewall_Region,PSRAM0"""
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menuitem "PSRAM0_ECC_AGGR" "per , ""Firewall_Region,PSRAM0_ECC_AGGR"""
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menuitem "PSC0" "per , ""Firewall_Region,PSC0"""
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menuitem "PLLCTRL0_SLV" "per , ""Firewall_Region,PLLCTRL0_SLV"""
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menuitem "GTC0" "per , ""Firewall_Region,GTC0"""
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menuitem "PLL_MMR0" "per , ""Firewall_Region,PLL_MMR0"""
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menuitem "CTRL_MMR0" "per , ""Firewall_Region,CTRL_MMR0"""
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menuitem "EFUSE0_SLV" "per , ""Firewall_Region,EFUSE0_SLV"""
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menuitem "PBIST0_CFG" "per , ""Firewall_Region,PBIST0_CFG"""
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menuitem "PBIST1_CFG" "per , ""Firewall_Region,PBIST1_CFG"""
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menuitem "GPIO0" "per , ""Firewall_Region,GPIO0"""
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menuitem "GPIO1" "per , ""Firewall_Region,GPIO1"""
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menuitem "ESM0_CFG" "per , ""Firewall_Region,ESM0_CFG"""
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menuitem "DCC0" "per , ""Firewall_Region,DCC0"""
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menuitem "DCC1" "per , ""Firewall_Region,DCC1"""
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menuitem "DCC2" "per , ""Firewall_Region,DCC2"""
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menuitem "DCC3" "per , ""Firewall_Region,DCC3"""
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menuitem "DCC4" "per , ""Firewall_Region,DCC4"""
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menuitem "DCC5" "per , ""Firewall_Region,DCC5"""
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menuitem "DCC6" "per , ""Firewall_Region,DCC6"""
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menuitem "DCC7" "per , ""Firewall_Region,DCC7"""
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menuitem "SERDES0_SLV" "per , ""Firewall_Region,SERDES0_SLV"""
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menuitem "SERDES1_SLV" "per , ""Firewall_Region,SERDES1_SLV"""
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menuitem "GPIOMUX_INTRTR0_CFG" "per , ""Firewall_Region,GPIOMUX_INTRTR0_CFG"""
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menuitem "MAIN2MCU_LVL_INTRTR0_CFG" "per , ""Firewall_Region,MAIN2MCU_LVL_INTRTR0_CFG"""
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menuitem "MAIN2MCU_PLS_INTRTR0_CFG" "per , ""Firewall_Region,MAIN2MCU_PLS_INTRTR0_CFG"""
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menuitem "CMPEVT_INTRTR0_CFG" "per , ""Firewall_Region,CMPEVT_INTRTR0_CFG"""
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menuitem "TIMESYNC_INTRTR0_CFG" "per , ""Firewall_Region,TIMESYNC_INTRTR0_CFG"""
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menuitem "CBASS_FW0" "per , ""Firewall_Region,CBASS_FW0"""
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menuitem "INFRA_CBASS0" "per , ""Firewall_Region,INFRA_CBASS0"""
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menuitem "ECC_AGGR3" "per , ""Firewall_Region,ECC_AGGR3"""
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menuitem "ECC_AGGR0" "per , ""Firewall_Region,ECC_AGGR0"""
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menuitem "WKUP_PSC0" "per , ""Firewall_Region,WKUP_PSC0"""
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menuitem "WKUP_PLLCTRL0_SLV" "per , ""Firewall_Region,WKUP_PLLCTRL0_SLV"""
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menuitem "WKUP_CTRL_MMR0" "per , ""Firewall_Region,WKUP_CTRL_MMR0"""
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menuitem "WKUP_GPIO0" "per , ""Firewall_Region,WKUP_GPIO0"""
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menuitem "WKUP_ESM0_CFG" "per , ""Firewall_Region,WKUP_ESM0_CFG"""
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menuitem "WKUP_VTM0" "per , ""Firewall_Region,WKUP_VTM0"""
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menuitem "WKUP_I2C0" "per , ""Firewall_Region,WKUP_I2C0"""
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menuitem "WKUP_USART0" "per , ""Firewall_Region,WKUP_USART0"""
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menuitem "WKUP_GPIOMUX_INTRTR0_CFG" "per , ""Firewall_Region,WKUP_GPIOMUX_INTRTR0_CFG"""
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menuitem "WKUP_CBASS0" "per , ""Firewall_Region,WKUP_CBASS0"""
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menuitem "WKUP_CBASS_FW0" "per , ""Firewall_Region,WKUP_CBASS_FW0"""
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menuitem "WKUP_ECC_AGGR0" "per , ""Firewall_Region,WKUP_ECC_AGGR0"""
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menuitem "MCU_ARMSS0_CORE0_SLV" "per , ""Firewall_Region,MCU_ARMSS0_CORE0_SLV"""
|
|
menuitem "MCU_ARMSS0_CORE0_CFG_SLV" "per , ""Firewall_Region,MCU_ARMSS0_CORE0_CFG_SLV"""
|
|
menuitem "MCU_RTI0_SLV" "per , ""Firewall_Region,MCU_RTI0_SLV"""
|
|
menuitem "MCU_ARMSS0_CORE1_SLV" "per , ""Firewall_Region,MCU_ARMSS0_CORE1_SLV"""
|
|
menuitem "MCU_ARMSS0_CORE1_CFG_SLV" "per , ""Firewall_Region,MCU_ARMSS0_CORE1_CFG_SLV"""
|
|
menuitem "MCU_RTI1_SLV" "per , ""Firewall_Region,MCU_RTI1_SLV"""
|
|
menuitem "MCU_FSS0_CFG" "per , ""Firewall_Region,MCU_FSS0_CFG"""
|
|
menuitem "MCU_FSS0_S1" "per , ""Firewall_Region,MCU_FSS0_S1"""
|
|
menuitem "MCU_FSS0_S0" "per , ""Firewall_Region,MCU_FSS0_S0"""
|
|
menuitem "MCU_ROM0_SLV" "per , ""Firewall_Region,MCU_ROM0_SLV"""
|
|
menuitem "MCU_MSRAM_SLV" "per , ""Firewall_Region,MCU_MSRAM_SLV"""
|
|
menuitem "MCU_MSRAM_CFG" "per , ""Firewall_Region,MCU_MSRAM_CFG"""
|
|
menuitem "MCU_PSRAM0" "per , ""Firewall_Region,MCU_PSRAM0"""
|
|
menuitem "MCU_TIMER0" "per , ""Firewall_Region,MCU_TIMER0"""
|
|
menuitem "MCU_TIMER1" "per , ""Firewall_Region,MCU_TIMER1"""
|
|
menuitem "MCU_TIMER2" "per , ""Firewall_Region,MCU_TIMER2"""
|
|
menuitem "MCU_TIMER3" "per , ""Firewall_Region,MCU_TIMER3"""
|
|
menuitem "MCU_MCSPI0_SLV" "per , ""Firewall_Region,MCU_MCSPI0_SLV"""
|
|
menuitem "MCU_MCSPI1_SLV" "per , ""Firewall_Region,MCU_MCSPI1_SLV"""
|
|
menuitem "MCU_MCSPI2_SLV" "per , ""Firewall_Region,MCU_MCSPI2_SLV"""
|
|
menuitem "MCU_DCC0" "per , ""Firewall_Region,MCU_DCC0"""
|
|
menuitem "MCU_DCC1" "per , ""Firewall_Region,MCU_DCC1"""
|
|
menuitem "MCU_DCC2" "per , ""Firewall_Region,MCU_DCC2"""
|
|
menuitem "MCU_ADC0_DMA" "per , ""Firewall_Region,MCU_ADC0_DMA"""
|
|
menuitem "MCU_ADC0_CFG" "per , ""Firewall_Region,MCU_ADC0_CFG"""
|
|
menuitem "MCU_ADC1_DMA" "per , ""Firewall_Region,MCU_ADC1_DMA"""
|
|
menuitem "MCU_ADC1_CFG" "per , ""Firewall_Region,MCU_ADC1_CFG"""
|
|
menuitem "MCU_USART0" "per , ""Firewall_Region,MCU_USART0"""
|
|
menuitem "MCU_I2C0" "per , ""Firewall_Region,MCU_I2C0"""
|
|
menuitem "MCU_ESM0_CFG" "per , ""Firewall_Region,MCU_ESM0_CFG"""
|
|
menuitem "MCU_MCAN0" "per , ""Firewall_Region,MCU_MCAN0"""
|
|
menuitem "MCU_MCAN1" "per , ""Firewall_Region,MCU_MCAN1"""
|
|
menuitem "MCU_CTRL_MMR0" "per , ""Firewall_Region,MCU_CTRL_MMR0"""
|
|
menuitem "MCU_PLL_MMR0" "per , ""Firewall_Region,MCU_PLL_MMR0"""
|
|
menuitem "MCU_EFUSE0_SLV" "per , ""Firewall_Region,MCU_EFUSE0_SLV"""
|
|
menuitem "MCU_PBIST0_CFG" "per , ""Firewall_Region,MCU_PBIST0_CFG"""
|
|
menuitem "MCU_CPSW0" "per , ""Firewall_Region,MCU_CPSW0"""
|
|
menuitem "MCU_PDMA0_ECC_AGGR" "per , ""Firewall_Region,MCU_PDMA0_ECC_AGGR"""
|
|
menuitem "MCU_PDMA1_ECC_AGGR" "per , ""Firewall_Region,MCU_PDMA1_ECC_AGGR"""
|
|
menuitem "MCU_CBASS0" "per , ""Firewall_Region,MCU_CBASS0"""
|
|
menuitem "MCU_CBASS_FW0" "per , ""Firewall_Region,MCU_CBASS_FW0"""
|
|
menuitem "MCU_ECC_AGGR0" "per , ""Firewall_Region,MCU_ECC_AGGR0"""
|
|
menuitem "MCU_ECC_AGGR1" "per , ""Firewall_Region,MCU_ECC_AGGR1"""
|
|
menuitem "NAVSS0_NBSS_CFG" "per , ""Firewall_Region,NAVSS0_NBSS_CFG"""
|
|
menuitem "COMPUTE_CLUSTER0_CFG" "per , ""Firewall_Region,COMPUTE_CLUSTER0_CFG"""
|
|
menuitem "MMCSD1_CFG" "per , ""Firewall_Region,MMCSD1_CFG"""
|
|
menuitem "MMCSD0_CFG" "per , ""Firewall_Region,MMCSD0_CFG"""
|
|
menuitem "PRU_ICSSG0_SLV" "per , ""Firewall_Region,PRU_ICSSG0_SLV"""
|
|
menuitem "PRU_ICSSG1_SLV" "per , ""Firewall_Region,PRU_ICSSG1_SLV"""
|
|
menuitem "PRU_ICSSG2_SLV" "per , ""Firewall_Region,PRU_ICSSG2_SLV"""
|
|
menuitem "CAL0_CFG" "per , ""Firewall_Region,CAL0_CFG"""
|
|
menuitem "ELM0" "per , ""Firewall_Region,ELM0"""
|
|
menuitem "GPMC0_SLV" "per , ""Firewall_Region,GPMC0_SLV"""
|
|
menuitem "GIC0_CFG" "per , ""Firewall_Region,GIC0_CFG"""
|
|
menuitem "GIC0_ECC_AGGR_CFG" "per , ""Firewall_Region,GIC0_ECC_AGGR_CFG"""
|
|
menuitem "USB3SS0_SLV0" "per , ""Firewall_Region,USB3SS0_SLV0"""
|
|
menuitem "USB3SS0_SLV1" "per , ""Firewall_Region,USB3SS0_SLV1"""
|
|
menuitem "USB3SS1_SLV0" "per , ""Firewall_Region,USB3SS1_SLV0"""
|
|
menuitem "USB3SS1_SLV1" "per , ""Firewall_Region,USB3SS1_SLV1"""
|
|
menuitem "EQEP0" "per , ""Firewall_Region,EQEP0"""
|
|
menuitem "EQEP1" "per , ""Firewall_Region,EQEP1"""
|
|
menuitem "EQEP2" "per , ""Firewall_Region,EQEP2"""
|
|
menuitem "ECAP0" "per , ""Firewall_Region,ECAP0"""
|
|
menuitem "EPWM0" "per , ""Firewall_Region,EPWM0"""
|
|
menuitem "HRPWM0" "per , ""Firewall_Region,HRPWM0"""
|
|
menuitem "EPWM5" "per , ""Firewall_Region,EPWM5"""
|
|
menuitem "HRPWM5" "per , ""Firewall_Region,HRPWM5"""
|
|
menuitem "EPWM4" "per , ""Firewall_Region,EPWM4"""
|
|
menuitem "HRPWM4" "per , ""Firewall_Region,HRPWM4"""
|
|
menuitem "EPWM3" "per , ""Firewall_Region,EPWM3"""
|
|
menuitem "HRPWM3" "per , ""Firewall_Region,HRPWM3"""
|
|
menuitem "EPWM2" "per , ""Firewall_Region,EPWM2"""
|
|
menuitem "HRPWM2" "per , ""Firewall_Region,HRPWM2"""
|
|
menuitem "EPWM1" "per , ""Firewall_Region,EPWM1"""
|
|
menuitem "HRPWM1" "per , ""Firewall_Region,HRPWM1"""
|
|
menuitem "TIMER0" "per , ""Firewall_Region,TIMER0"""
|
|
menuitem "TIMER1" "per , ""Firewall_Region,TIMER1"""
|
|
menuitem "TIMER2" "per , ""Firewall_Region,TIMER2"""
|
|
menuitem "TIMER3" "per , ""Firewall_Region,TIMER3"""
|
|
menuitem "TIMER4" "per , ""Firewall_Region,TIMER4"""
|
|
menuitem "TIMER5" "per , ""Firewall_Region,TIMER5"""
|
|
menuitem "TIMER6" "per , ""Firewall_Region,TIMER6"""
|
|
menuitem "TIMER7" "per , ""Firewall_Region,TIMER7"""
|
|
menuitem "TIMER8" "per , ""Firewall_Region,TIMER8"""
|
|
menuitem "TIMER9" "per , ""Firewall_Region,TIMER9"""
|
|
menuitem "TIMER10" "per , ""Firewall_Region,TIMER10"""
|
|
menuitem "TIMER11" "per , ""Firewall_Region,TIMER11"""
|
|
menuitem "DDRSS0_CFG" "per , ""Firewall_Region,DDRSS0_CFG"""
|
|
menuitem "I2C0" "per , ""Firewall_Region,I2C0"""
|
|
menuitem "I2C1" "per , ""Firewall_Region,I2C1"""
|
|
menuitem "I2C2" "per , ""Firewall_Region,I2C2"""
|
|
menuitem "I2C3" "per , ""Firewall_Region,I2C3"""
|
|
menuitem "PCIE0_SLV" "per , ""Firewall_Region,PCIE0_SLV"""
|
|
menuitem "PCIE1_SLV" "per , ""Firewall_Region,PCIE1_SLV"""
|
|
menuitem "STM0" "per , ""Firewall_Region,STM0"""
|
|
menuitem "DEBUGSS0_CFG" "per , ""Firewall_Region,DEBUGSS0_CFG"""
|
|
menuitem "MCSPI0_SLV" "per , ""Firewall_Region,MCSPI0_SLV"""
|
|
menuitem "MCSPI1_SLV" "per , ""Firewall_Region,MCSPI1_SLV"""
|
|
menuitem "MCSPI2_SLV" "per , ""Firewall_Region,MCSPI2_SLV"""
|
|
menuitem "MCSPI3_SLV" "per , ""Firewall_Region,MCSPI3_SLV"""
|
|
menuitem "MCSPI4_SLV" "per , ""Firewall_Region,MCSPI4_SLV"""
|
|
menuitem "USART0" "per , ""Firewall_Region,USART0"""
|
|
menuitem "USART1" "per , ""Firewall_Region,USART1"""
|
|
menuitem "USART2" "per , ""Firewall_Region,USART2"""
|
|
menuitem "MCASP0_CFG" "per , ""Firewall_Region,MCASP0_CFG"""
|
|
menuitem "MCASP0_DMA" "per , ""Firewall_Region,MCASP0_DMA"""
|
|
menuitem "MCASP1_CFG" "per , ""Firewall_Region,MCASP1_CFG"""
|
|
menuitem "MCASP1_DMA" "per , ""Firewall_Region,MCASP1_DMA"""
|
|
menuitem "MCASP2_CFG" "per , ""Firewall_Region,MCASP2_CFG"""
|
|
menuitem "MCASP2_DMA" "per , ""Firewall_Region,MCASP2_DMA"""
|
|
menuitem "CC_DEBUG_CELL0" "per , ""Firewall_Region,CC_DEBUG_CELL0"""
|
|
menuitem "MAIN_DEBUG_CELL0" "per , ""Firewall_Region,MAIN_DEBUG_CELL0"""
|
|
menuitem "MCU_DEBUG_CELL0" "per , ""Firewall_Region,MCU_DEBUG_CELL0"""
|
|
menuitem "DSS0_CFG" "per , ""Firewall_Region,DSS0_CFG"""
|
|
menuitem "PCIE0_CFG" "per , ""Firewall_Region,PCIE0_CFG"""
|
|
menuitem "PCIE1_CFG" "per , ""Firewall_Region,PCIE1_CFG"""
|
|
menuitem "GPU0_KLIO_CFG" "per , ""Firewall_Region,GPU0_KLIO_CFG"""
|
|
menuitem "GPU0_RAT_CFG" "per , ""Firewall_Region,GPU0_RAT_CFG"""
|
|
menuitem "PDMA_DEBUG0_ECC_AGGR" "per , ""Firewall_Region,PDMA_DEBUG0_ECC_AGGR"""
|
|
menuitem "PDMA0_ECC_AGGR" "per , ""Firewall_Region,PDMA0_ECC_AGGR"""
|
|
menuitem "PDMA1_ECC_AGGR" "per , ""Firewall_Region,PDMA1_ECC_AGGR"""
|
|
menuitem "NAVSS0_NB0_BP" "per , ""Firewall_Region,NAVSS0_NB0_BP"""
|
|
menuitem "ECC_AGGR1" "per , ""Firewall_Region,ECC_AGGR1"""
|
|
menuitem "ECC_AGGR2" "per , ""Firewall_Region,ECC_AGGR2"""
|
|
menuitem "CBASS0" "per , ""Firewall_Region,CBASS0"""
|
|
)
|
|
popup "Firewall_Exception"
|
|
(
|
|
menuitem "WKUP_CBASS0_GLB" "per , ""Firewall_Exception,WKUP_CBASS0_GLB"""
|
|
menuitem "MCU_CBASS0_GLB" "per , ""Firewall_Exception,MCU_CBASS0_GLB"""
|
|
menuitem "CBASS0_GLB" "per , ""Firewall_Exception,CBASS0_GLB"""
|
|
menuitem "CBASS_INFRA0_GLB" "per , ""Firewall_Exception,CBASS_INFRA0_GLB"""
|
|
)
|
|
popup "QoS"
|
|
(
|
|
menuitem "MCU_ARMSS0_DBG_RD0" "per , ""QoS,MCU_ARMSS0_DBG_RD0"""
|
|
menuitem "MCU_ARMSS0_DBG_WR0" "per , ""QoS,MCU_ARMSS0_DBG_WR0"""
|
|
menuitem "MCU_ARMSS0_P0" "per , ""QoS,MCU_ARMSS0_P0"""
|
|
menuitem "MCU_ARMSS0_DBG_RD1" "per , ""QoS,MCU_ARMSS0_DBG_RD1"""
|
|
menuitem "MCU_ARMSS0_DBG_WR1" "per , ""QoS,MCU_ARMSS0_DBG_WR1"""
|
|
menuitem "MCU_ARMSS0_P1" "per , ""QoS,MCU_ARMSS0_P1"""
|
|
menuitem "MMCSD1_WR" "per , ""QoS,MMCSD1_WR"""
|
|
menuitem "MMCSD1_RD" "per , ""QoS,MMCSD1_RD"""
|
|
menuitem "MMCSD0_RD" "per , ""QoS,MMCSD0_RD"""
|
|
menuitem "MMCSD0_WR" "per , ""QoS,MMCSD0_WR"""
|
|
menuitem "PRU_ICSSG0" "per , ""QoS,PRU_ICSSG0"""
|
|
menuitem "PRU_ICSSG1" "per , ""QoS,PRU_ICSSG1"""
|
|
menuitem "PRU_ICSSG2" "per , ""QoS,PRU_ICSSG2"""
|
|
menuitem "CAL0" "per , ""QoS,CAL0"""
|
|
menuitem "GIC0_RD" "per , ""QoS,GIC0_RD"""
|
|
menuitem "GIC0_WR" "per , ""QoS,GIC0_WR"""
|
|
menuitem "USB3SS0_WR" "per , ""QoS,USB3SS0_WR"""
|
|
menuitem "USB3SS0_RD" "per , ""QoS,USB3SS0_RD"""
|
|
menuitem "USB3SS1_WR" "per , ""QoS,USB3SS1_WR"""
|
|
menuitem "USB3SS1_RD" "per , ""QoS,USB3SS1_RD"""
|
|
menuitem "DSS0" "per , ""QoS,DSS0"""
|
|
menuitem "DEBUGSS0_RD" "per , ""QoS,DEBUGSS0_RD"""
|
|
menuitem "DEBUGSS0_WR" "per , ""QoS,DEBUGSS0_WR"""
|
|
menuitem "PCIE0_RD_HP" "per , ""QoS,PCIE0_RD_HP"""
|
|
menuitem "PCIE0_WR_HP" "per , ""QoS,PCIE0_WR_HP"""
|
|
menuitem "PCIE0_RD_LP" "per , ""QoS,PCIE0_RD_LP"""
|
|
menuitem "PCIE0_WR_LP" "per , ""QoS,PCIE0_WR_LP"""
|
|
menuitem "PCIE1_RD_HP" "per , ""QoS,PCIE1_RD_HP"""
|
|
menuitem "PCIE1_WR_HP" "per , ""QoS,PCIE1_WR_HP"""
|
|
menuitem "PCIE1_RD_LP" "per , ""QoS,PCIE1_RD_LP"""
|
|
menuitem "PCIE1_WR_LP" "per , ""QoS,PCIE1_WR_LP"""
|
|
menuitem "GPU0_P0" "per , ""QoS,GPU0_P0"""
|
|
menuitem "GPU0_P1" "per , ""QoS,GPU0_P1"""
|
|
menuitem "PDMA_DEBUG0_RD" "per , ""QoS,PDMA_DEBUG0_RD"""
|
|
)
|
|
menuitem "MSMC" "per , ""MSMC"""
|
|
popup "CTRL_MMR"
|
|
(
|
|
menuitem "CTRL_MMR0_CFG0" "per , ""CTRL_MMR,CTRL_MMR0_CFG0"""
|
|
)
|
|
popup "MCU_CTRL_MMR"
|
|
(
|
|
menuitem "MCU_CTRL_MMR0_CFG0" "per , ""MCU_CTRL_MMR,MCU_CTRL_MMR0_CFG0"""
|
|
)
|
|
popup "WKUP_CTRL_MMR"
|
|
(
|
|
menuitem "WKUP_CTRL_MMR0_CFG0" "per , ""WKUP_CTRL_MMR,WKUP_CTRL_MMR0_CFG0"""
|
|
)
|
|
popup "Compute_Cluster"
|
|
(
|
|
menuitem "COMPUTE_CLUSTER0_DMSC_BOOT" "per , ""Compute_Cluster,COMPUTE_CLUSTER0_DMSC_BOOT"""
|
|
)
|
|
popup "DRU"
|
|
(
|
|
menuitem "COMPUTE_CLUSTER0_DRU" "per , ""DRU,COMPUTE_CLUSTER0_DRU"""
|
|
)
|
|
popup "DRU_DMA_FW"
|
|
(
|
|
menuitem "COMPUTE_CLUSTER0_DRU_FW" "per , ""DRU_DMA_FW,COMPUTE_CLUSTER0_DRU_FW"""
|
|
)
|
|
popup "DRU_DMA_FW_GLB"
|
|
(
|
|
menuitem "COMPUTE_CLUSTER0_DRU_FW_GLB" "per , ""DRU_DMA_FW_GLB,COMPUTE_CLUSTER0_DRU_FW_GLB"""
|
|
)
|
|
popup "DRU_MMR_FW"
|
|
(
|
|
menuitem "COMPUTE_CLUSTER0_DRU_MMR_FW" "per , ""DRU_MMR_FW,COMPUTE_CLUSTER0_DRU_MMR_FW"""
|
|
)
|
|
popup "DRU_MMR_FW_GLB"
|
|
(
|
|
menuitem "COMPUTE_CLUSTER0_DRU_MMR_FW_GLB" "per , ""DRU_MMR_FW_GLB,COMPUTE_CLUSTER0_DRU_MMR_FW_GLB"""
|
|
)
|
|
popup "DDR_Controller"
|
|
(
|
|
menuitem "DDRSS0_CTL_CFG" "per , ""DDR_Controller,DDRSS0_CTL_CFG"""
|
|
)
|
|
popup "ECC_Aggregator"
|
|
(
|
|
menuitem "DDRSS0_ECC_AGGR_CTL" "per , ""ECC_Aggregator,DDRSS0_ECC_AGGR_CTL"""
|
|
)
|
|
popup "VBUSMC_ECC_Aggregator"
|
|
(
|
|
menuitem "DDRSS0_ECC_AGGR_VBUS" "per , ""VBUSMC_ECC_Aggregator,DDRSS0_ECC_AGGR_VBUS"""
|
|
)
|
|
popup "DDR_PHY"
|
|
(
|
|
menuitem "DDRSS0_PHY_CFG" "per , ""DDR_PHY,DDRSS0_PHY_CFG"""
|
|
)
|
|
popup "DDR_Subsystem_Wrapper_Logic"
|
|
(
|
|
menuitem "DDRSS0_SS_CFG" "per , ""DDR_Subsystem_Wrapper_Logic,DDRSS0_SS_CFG"""
|
|
)
|
|
popup "Clocking"
|
|
(
|
|
menuitem "MCU_PLL0_CFG" "per , ""Clocking,MCU_PLL0_CFG"""
|
|
menuitem "PLL0_CFG" "per , ""Clocking,PLL0_CFG"""
|
|
menuitem "PLLCTRL0" "per , ""Clocking,PLLCTRL0"""
|
|
menuitem "WKUP_PLLCTRL0" "per , ""Clocking,WKUP_PLLCTRL0"""
|
|
)
|
|
popup "MCU_CPSW"
|
|
(
|
|
menuitem "MCU_CPSW0_NUSS" "per , ""MCU_CPSW,MCU_CPSW0_NUSS"""
|
|
menuitem "MCU_CPSW0_ECC" "per , ""MCU_CPSW,MCU_CPSW0_ECC"""
|
|
)
|
|
menuitem "CPU0_ECC_AGGR_CFG_REGS" "per , ""CPU0_ECC_AGGR_CFG_REGS"""
|
|
menuitem "CPU1_ECC_AGGR_CFG_REGS" "per , ""CPU1_ECC_AGGR_CFG_REGS"""
|
|
popup "DCC"
|
|
(
|
|
menuitem "DCC0" "per , ""DCC,DCC0"""
|
|
menuitem "DCC1" "per , ""DCC,DCC1"""
|
|
menuitem "DCC2" "per , ""DCC,DCC2"""
|
|
menuitem "DCC3" "per , ""DCC,DCC3"""
|
|
menuitem "DCC4" "per , ""DCC,DCC4"""
|
|
menuitem "DCC5" "per , ""DCC,DCC5"""
|
|
menuitem "DCC6" "per , ""DCC,DCC6"""
|
|
menuitem "DCC7" "per , ""DCC,DCC7"""
|
|
menuitem "MCU_DCC0" "per , ""DCC,MCU_DCC0"""
|
|
menuitem "MCU_DCC1" "per , ""DCC,MCU_DCC1"""
|
|
menuitem "MCU_DCC2" "per , ""DCC,MCU_DCC2"""
|
|
)
|
|
popup "DSS0_COMMON"
|
|
(
|
|
menuitem "DSS0_COMMON1" "per , ""DSS0_COMMON,DSS0_COMMON1"""
|
|
)
|
|
menuitem "DSS0_COMMON" "per , ""DSS0_COMMON"""
|
|
popup "DSS0_OVR"
|
|
(
|
|
menuitem "DSS0_OVR1" "per , ""DSS0_OVR,DSS0_OVR1"""
|
|
menuitem "DSS0_OVR2" "per , ""DSS0_OVR,DSS0_OVR2"""
|
|
)
|
|
popup "DSS_VID"
|
|
(
|
|
menuitem "DSS0_VIDL1" "per , ""DSS_VID,DSS0_VIDL1"""
|
|
menuitem "DSS0_VID" "per , ""DSS_VID,DSS0_VID"""
|
|
)
|
|
popup "DSS0_VP"
|
|
(
|
|
menuitem "DSS0_VP1" "per , ""DSS0_VP,DSS0_VP1"""
|
|
menuitem "DSS0_VP2" "per , ""DSS0_VP,DSS0_VP2"""
|
|
)
|
|
popup "ECAP"
|
|
(
|
|
menuitem "ECAP0_CTL_STS" "per , ""ECAP,ECAP0_CTL_STS"""
|
|
)
|
|
popup "ELM"
|
|
(
|
|
menuitem "ELM0" "per , ""ELM,ELM0"""
|
|
)
|
|
popup "EPWM"
|
|
(
|
|
menuitem "EHRPWM0_EPWM" "per , ""EPWM,EHRPWM0_EPWM"""
|
|
menuitem "EHRPWM1_EPWM" "per , ""EPWM,EHRPWM1_EPWM"""
|
|
menuitem "EHRPWM2_EPWM" "per , ""EPWM,EHRPWM2_EPWM"""
|
|
menuitem "EHRPWM3_EPWM" "per , ""EPWM,EHRPWM3_EPWM"""
|
|
menuitem "EHRPWM4_EPWM" "per , ""EPWM,EHRPWM4_EPWM"""
|
|
menuitem "EHRPWM5_EPWM" "per , ""EPWM,EHRPWM5_EPWM"""
|
|
)
|
|
popup "EQEP"
|
|
(
|
|
menuitem "EQEP0_REG" "per , ""EQEP,EQEP0_REG"""
|
|
menuitem "EQEP1_REG" "per , ""EQEP,EQEP1_REG"""
|
|
menuitem "EQEP2_REG" "per , ""EQEP,EQEP2_REG"""
|
|
)
|
|
popup "ESM"
|
|
(
|
|
menuitem "ESM0" "per , ""ESM,ESM0"""
|
|
menuitem "MCU_ESM0" "per , ""ESM,MCU_ESM0"""
|
|
menuitem "WKUP_ESM0" "per , ""ESM,WKUP_ESM0"""
|
|
)
|
|
popup "FSS"
|
|
(
|
|
menuitem "MCU_FSS0_CFG" "per , ""FSS,MCU_FSS0_CFG"""
|
|
)
|
|
popup "GPIO"
|
|
(
|
|
menuitem "GPIO0" "per , ""GPIO,GPIO0"""
|
|
menuitem "GPIO1" "per , ""GPIO,GPIO1"""
|
|
menuitem "WKUP_GPIO0" "per , ""GPIO,WKUP_GPIO0"""
|
|
)
|
|
popup "GPMC"
|
|
(
|
|
menuitem "GPMC0_CFG" "per , ""GPMC,GPMC0_CFG"""
|
|
)
|
|
popup "GPU"
|
|
(
|
|
menuitem "GPU0_KLIOMP1_HL_MMRS" "per , ""GPU,GPU0_KLIOMP1_HL_MMRS"""
|
|
)
|
|
menuitem "GTC0_GTC_CFG0" "per , ""GTC0_GTC_CFG0"""
|
|
menuitem "GTC0_GTC_CFG1" "per , ""GTC0_GTC_CFG1"""
|
|
menuitem "GTC0_GTC_CFG2" "per , ""GTC0_GTC_CFG2"""
|
|
menuitem "GTC0_GTC_CFG3" "per , ""GTC0_GTC_CFG3"""
|
|
popup "Hyperbus"
|
|
(
|
|
menuitem "MCU_FSS0_HPB_SS_CFG" "per , ""Hyperbus,MCU_FSS0_HPB_SS_CFG"""
|
|
menuitem "MCU_FSS0_HPB_CTRL" "per , ""Hyperbus,MCU_FSS0_HPB_CTRL"""
|
|
menuitem "MCU_FSS0_HPB_ECC_AGGR" "per , ""Hyperbus,MCU_FSS0_HPB_ECC_AGGR"""
|
|
)
|
|
popup "I2C"
|
|
(
|
|
menuitem "I2C0_CFG" "per , ""I2C,I2C0_CFG"""
|
|
menuitem "I2C1_CFG" "per , ""I2C,I2C1_CFG"""
|
|
menuitem "I2C2_CFG" "per , ""I2C,I2C2_CFG"""
|
|
menuitem "I2C3_CFG" "per , ""I2C,I2C3_CFG"""
|
|
menuitem "MCU_I2C0_CFG" "per , ""I2C,MCU_I2C0_CFG"""
|
|
menuitem "WKUP_I2C0_CFG" "per , ""I2C,WKUP_I2C0_CFG"""
|
|
)
|
|
popup "Interrupt_Routers"
|
|
(
|
|
menuitem "WKUP_GPIOMUX_INTRTR0" "per , ""Interrupt_Routers,WKUP_GPIOMUX_INTRTR0"""
|
|
menuitem "GPIO_INTRTR0" "per , ""Interrupt_Routers,GPIO_INTRTR0"""
|
|
menuitem "MAIN2MCU_LVL_INTRTR0" "per , ""Interrupt_Routers,MAIN2MCU_LVL_INTRTR0"""
|
|
menuitem "MAIN2MCU_PLS_INTRTR0" "per , ""Interrupt_Routers,MAIN2MCU_PLS_INTRTR0"""
|
|
)
|
|
popup "MCAN"
|
|
(
|
|
menuitem "MCU_MCAN0_SS" "per , ""MCAN,MCU_MCAN0_SS"""
|
|
menuitem "MCU_MCAN1_SS" "per , ""MCAN,MCU_MCAN1_SS"""
|
|
menuitem "MCU_MCAN0_CFG" "per , ""MCAN,MCU_MCAN0_CFG"""
|
|
menuitem "MCU_MCAN1_CFG" "per , ""MCAN,MCU_MCAN1_CFG"""
|
|
menuitem "MCU_MCAN0_MSGMEM_RAM" "per , ""MCAN,MCU_MCAN0_MSGMEM_RAM"""
|
|
menuitem "MCU_MCAN1_MSGMEM_RAM" "per , ""MCAN,MCU_MCAN1_MSGMEM_RAM"""
|
|
)
|
|
popup "MCASP"
|
|
(
|
|
menuitem "MCASP0_CFG" "per , ""MCASP,MCASP0_CFG"""
|
|
menuitem "MCASP1_CFG" "per , ""MCASP,MCASP1_CFG"""
|
|
menuitem "MCASP2_CFG" "per , ""MCASP,MCASP2_CFG"""
|
|
)
|
|
popup "MCSPI"
|
|
(
|
|
menuitem "MCSPI0_CFG" "per , ""MCSPI,MCSPI0_CFG"""
|
|
menuitem "MCSPI1_CFG" "per , ""MCSPI,MCSPI1_CFG"""
|
|
menuitem "MCSPI2_CFG" "per , ""MCSPI,MCSPI2_CFG"""
|
|
menuitem "MCSPI3_CFG" "per , ""MCSPI,MCSPI3_CFG"""
|
|
menuitem "MCSPI4_CFG" "per , ""MCSPI,MCSPI4_CFG"""
|
|
menuitem "MCU_MCSPI0_CFG" "per , ""MCSPI,MCU_MCSPI0_CFG"""
|
|
menuitem "MCU_MCSPI1_CFG" "per , ""MCSPI,MCU_MCSPI1_CFG"""
|
|
menuitem "MCU_MCSPI2_CFG" "per , ""MCSPI,MCU_MCSPI2_CFG"""
|
|
)
|
|
menuitem "MCU_ARMSS_CCMR5" "per , ""MCU_ARMSS_CCMR5"""
|
|
menuitem "MCU_PDMA0" "per , ""MCU_PDMA0"""
|
|
menuitem "MCU_PDMA1" "per , ""MCU_PDMA1"""
|
|
popup "MMCSD"
|
|
(
|
|
menuitem "MMCSD0_SS_CFG" "per , ""MMCSD,MMCSD0_SS_CFG"""
|
|
menuitem "MMCSD0_ECC_AGGR_RXMEM" "per , ""MMCSD,MMCSD0_ECC_AGGR_RXMEM"""
|
|
menuitem "MMCSD1_ECC_AGGR_RXMEM" "per , ""MMCSD,MMCSD1_ECC_AGGR_RXMEM"""
|
|
menuitem "MMCSD1_ECC_AGGR_TXMEM" "per , ""MMCSD,MMCSD1_ECC_AGGR_TXMEM"""
|
|
menuitem "MMCSD1_CTL_CFG" "per , ""MMCSD,MMCSD1_CTL_CFG"""
|
|
menuitem "MMCSD1_SS_CFG" "per , ""MMCSD,MMCSD1_SS_CFG"""
|
|
menuitem "MMCSD0_ECC_AGGR_TXMEM" "per , ""MMCSD,MMCSD0_ECC_AGGR_TXMEM"""
|
|
menuitem "MMCSD0_CTL_CFG" "per , ""MMCSD,MMCSD0_CTL_CFG"""
|
|
)
|
|
popup "MCU_FSS"
|
|
(
|
|
popup "MCU_FSS0_OSPI_ECC_AGGR"
|
|
(
|
|
menuitem "MCU_FSS0_OSPI1_ECC_AGGR" "per , ""MCU_FSS,MCU_FSS0_OSPI_ECC_AGGR,MCU_FSS0_OSPI1_ECC_AGGR"""
|
|
menuitem "MCU_FSS0_OSPI0_ECC_AGGR" "per , ""MCU_FSS,MCU_FSS0_OSPI_ECC_AGGR,MCU_FSS0_OSPI0_ECC_AGGR"""
|
|
)
|
|
popup "MCU_FSS0_OSPI_SS_CFG"
|
|
(
|
|
menuitem "MCU_FSS0_OSPI0_SS_CFG" "per , ""MCU_FSS,MCU_FSS0_OSPI_SS_CFG,MCU_FSS0_OSPI0_SS_CFG"""
|
|
menuitem "MCU_FSS0_OSPI1_SS_CFG" "per , ""MCU_FSS,MCU_FSS0_OSPI_SS_CFG,MCU_FSS0_OSPI1_SS_CFG"""
|
|
)
|
|
popup "MCU_FSS0_OSPI_CTRL"
|
|
(
|
|
menuitem "MCU_FSS0_OSPI0_CTRL" "per , ""MCU_FSS,MCU_FSS0_OSPI_CTRL,MCU_FSS0_OSPI0_CTRL"""
|
|
menuitem "MCU_FSS0_OSPI1_CTRL" "per , ""MCU_FSS,MCU_FSS0_OSPI_CTRL,MCU_FSS0_OSPI1_CTRL"""
|
|
)
|
|
)
|
|
popup "PCIE_CORE_EP"
|
|
(
|
|
popup "PCIE_DAT"
|
|
(
|
|
menuitem "PCIE0_DAT" "per , ""PCIE_CORE_EP,PCIE_DAT,PCIE0_DAT"""
|
|
menuitem "PCIE1_DAT" "per , ""PCIE_CORE_EP,PCIE_DAT,PCIE1_DAT"""
|
|
)
|
|
)
|
|
popup "PCIE_CORE_RC"
|
|
(
|
|
popup "PCIE_DAT"
|
|
(
|
|
menuitem "PCIE0_DAT" "per , ""PCIE_CORE_RC,PCIE_DAT,PCIE0_DAT"""
|
|
menuitem "PCIE1_DAT" "per , ""PCIE_CORE_RC,PCIE_DAT,PCIE1_DAT"""
|
|
)
|
|
)
|
|
popup "PCIE_CPTS"
|
|
(
|
|
menuitem "PCIE0_CPTS" "per , ""PCIE_CPTS,PCIE0_CPTS"""
|
|
menuitem "PCIE1_CPTS" "per , ""PCIE_CPTS,PCIE1_CPTS"""
|
|
)
|
|
popup "PCIE_DAT0"
|
|
(
|
|
menuitem "PCIE0_DAT0" "per , ""PCIE_DAT0,PCIE0_DAT0"""
|
|
menuitem "PCIE1_DAT0" "per , ""PCIE_DAT0,PCIE1_DAT0"""
|
|
)
|
|
popup "PCIE_DAT1"
|
|
(
|
|
menuitem "PCIE0_DAT1" "per , ""PCIE_DAT1,PCIE0_DAT1"""
|
|
menuitem "PCIE1_DAT1" "per , ""PCIE_DAT1,PCIE1_DAT1"""
|
|
)
|
|
popup "PCIE_ECC_AGGR0"
|
|
(
|
|
menuitem "PCIE0_CORE_ECC_AGGR0" "per , ""PCIE_ECC_AGGR0,PCIE0_CORE_ECC_AGGR0"""
|
|
menuitem "PCIE1_CORE_ECC_AGGR0" "per , ""PCIE_ECC_AGGR0,PCIE1_CORE_ECC_AGGR0"""
|
|
)
|
|
popup "PCIE_ECC_AGGR1"
|
|
(
|
|
menuitem "PCIE0_CORE_ECC_AGGR1" "per , ""PCIE_ECC_AGGR1,PCIE0_CORE_ECC_AGGR1"""
|
|
menuitem "PCIE1_CORE_ECC_AGGR1" "per , ""PCIE_ECC_AGGR1,PCIE1_CORE_ECC_AGGR1"""
|
|
)
|
|
popup "PCIE_VMAP_HP"
|
|
(
|
|
menuitem "PCIE0_CORE_VMAP_HP_MMRS" "per , ""PCIE_VMAP_HP,PCIE0_CORE_VMAP_HP_MMRS"""
|
|
menuitem "PCIE1_CORE_VMAP_HP_MMRS" "per , ""PCIE_VMAP_HP,PCIE1_CORE_VMAP_HP_MMRS"""
|
|
)
|
|
popup "PCIE_VMAP_LP"
|
|
(
|
|
menuitem "PCIE0_CORE_VMAP_LP_MMRS" "per , ""PCIE_VMAP_LP,PCIE0_CORE_VMAP_LP_MMRS"""
|
|
menuitem "PCIE1_CORE_VMAP_LP_MMRS" "per , ""PCIE_VMAP_LP,PCIE1_CORE_VMAP_LP_MMRS"""
|
|
)
|
|
menuitem "PDMA0" "per , ""PDMA0"""
|
|
menuitem "PDMA1" "per , ""PDMA1"""
|
|
menuitem "PDMA_DEBUG" "per , ""PDMA_DEBUG"""
|
|
popup "RAT"
|
|
(
|
|
menuitem "RAT_0" "per , ""RAT,RAT_0"""
|
|
menuitem "RAT_1" "per , ""RAT,RAT_1"""
|
|
)
|
|
popup "RTI"
|
|
(
|
|
menuitem "RTI0" "per , ""RTI,RTI0"""
|
|
menuitem "RTI1" "per , ""RTI,RTI1"""
|
|
menuitem "RTI2" "per , ""RTI,RTI2"""
|
|
menuitem "RTI3" "per , ""RTI,RTI3"""
|
|
menuitem "MCU_RTI0" "per , ""RTI,MCU_RTI0"""
|
|
menuitem "MCU_RTI1" "per , ""RTI,MCU_RTI1"""
|
|
)
|
|
popup "SerDes"
|
|
(
|
|
menuitem "SERDES0" "per , ""SerDes,SERDES0"""
|
|
menuitem "SERDES1" "per , ""SerDes,SERDES1"""
|
|
)
|
|
popup "Timers"
|
|
(
|
|
menuitem "TIMER0" "per , ""Timers,TIMER0"""
|
|
menuitem "TIMER1" "per , ""Timers,TIMER1"""
|
|
menuitem "TIMER2" "per , ""Timers,TIMER2"""
|
|
menuitem "TIMER3" "per , ""Timers,TIMER3"""
|
|
menuitem "TIMER4" "per , ""Timers,TIMER4"""
|
|
menuitem "TIMER5" "per , ""Timers,TIMER5"""
|
|
menuitem "TIMER6" "per , ""Timers,TIMER6"""
|
|
menuitem "TIMER7" "per , ""Timers,TIMER7"""
|
|
menuitem "TIMER8" "per , ""Timers,TIMER8"""
|
|
menuitem "TIMER9" "per , ""Timers,TIMER9"""
|
|
menuitem "TIMER10" "per , ""Timers,TIMER10"""
|
|
menuitem "TIMER11" "per , ""Timers,TIMER11"""
|
|
menuitem "MCU_TIMER0" "per , ""Timers,MCU_TIMER0"""
|
|
menuitem "MCU_TIMER1" "per , ""Timers,MCU_TIMER1"""
|
|
menuitem "MCU_TIMER2" "per , ""Timers,MCU_TIMER2"""
|
|
menuitem "MCU_TIMER3" "per , ""Timers,MCU_TIMER3"""
|
|
)
|
|
popup "Time_Sync_Routers"
|
|
(
|
|
menuitem "TIMESYNC_INTRTR0" "per , ""Time_Sync_Routers,TIMESYNC_INTRTR0"""
|
|
menuitem "CMPEVT_INTRTR0" "per , ""Time_Sync_Routers,CMPEVT_INTRTR0"""
|
|
)
|
|
popup "UART"
|
|
(
|
|
menuitem "UART0" "per , ""UART,UART0"""
|
|
menuitem "UART1" "per , ""UART,UART1"""
|
|
menuitem "UART2" "per , ""UART,UART2"""
|
|
menuitem "MCU_UART0" "per , ""UART,MCU_UART0"""
|
|
menuitem "WKUP_UART0" "per , ""UART,WKUP_UART0"""
|
|
)
|
|
popup "USB3SS_PHY"
|
|
(
|
|
popup "USB3SS_PHY2"
|
|
(
|
|
menuitem "USB3SS0_PHY2" "per , ""USB3SS_PHY,USB3SS_PHY2,USB3SS0_PHY2"""
|
|
menuitem "USB3SS1_PHY2" "per , ""USB3SS_PHY,USB3SS_PHY2,USB3SS1_PHY2"""
|
|
)
|
|
popup "USB3SS_ECC_AGGR"
|
|
(
|
|
menuitem "USB3SS0_ECC_AGGR" "per , ""USB3SS_PHY,USB3SS_ECC_AGGR,USB3SS0_ECC_AGGR"""
|
|
menuitem "USB3SS1_ECC_AGGR" "per , ""USB3SS_PHY,USB3SS_ECC_AGGR,USB3SS1_ECC_AGGR"""
|
|
)
|
|
popup "USB3SS"
|
|
(
|
|
menuitem "USB3SS0" "per , ""USB3SS_PHY,USB3SS,USB3SS0"""
|
|
menuitem "USB3SS1" "per , ""USB3SS_PHY,USB3SS,USB3SS1"""
|
|
)
|
|
)
|
|
popup "VIM"
|
|
(
|
|
menuitem "VIM_CFG0" "per , ""VIM,VIM_CFG0"""
|
|
menuitem "VIM_CFG1" "per , ""VIM,VIM_CFG1"""
|
|
)
|
|
)
|
|
else
|
|
(
|
|
popup "ICSS_0"
|
|
(
|
|
popup "PRU_ICSSG_CFG"
|
|
(
|
|
menuitem "PRU_ICSSG0_PR1_CFG_SLV" "per , ""ICSS_0,PRU_ICSSG_CFG,PRU_ICSSG0_PR1_CFG_SLV"""
|
|
)
|
|
popup "PRU_ICSSG_DRAM0"
|
|
(
|
|
menuitem "PRU_ICSSG0_DRAM0_SLV_RAM" "per , ""ICSS_0,PRU_ICSSG_DRAM0,PRU_ICSSG0_DRAM0_SLV_RAM"""
|
|
menuitem "PRU_ICSSG0_DRAM1_SLV_RAM" "per , ""ICSS_0,PRU_ICSSG_DRAM0,PRU_ICSSG0_DRAM1_SLV_RAM"""
|
|
)
|
|
popup "PRU_ICSSG_ECAP0"
|
|
(
|
|
menuitem "PRU_ICSSG0_PR1_ICSS_ECAP0_ECAP_SLV" "per , ""ICSS_0,PRU_ICSSG_ECAP0,PRU_ICSSG0_PR1_ICSS_ECAP0_ECAP_SLV"""
|
|
)
|
|
popup "PRU_ICSSG_ECC_AGGR"
|
|
(
|
|
menuitem "PRU_ICSSG0_ECC_AGGR" "per , ""ICSS_0,PRU_ICSSG_ECC_AGGR,PRU_ICSSG0_ECC_AGGR"""
|
|
)
|
|
popup "PRU_ICSSG_IEP0"
|
|
(
|
|
menuitem "PRU_ICSSG0_IEP0" "per , ""ICSS_0,PRU_ICSSG_IEP0,PRU_ICSSG0_IEP0"""
|
|
menuitem "PRU_ICSSG0_IEP1" "per , ""ICSS_0,PRU_ICSSG_IEP0,PRU_ICSSG0_IEP1"""
|
|
)
|
|
popup "PRU_ICSSG_INTC"
|
|
(
|
|
menuitem "PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV" "per , ""ICSS_0,PRU_ICSSG_INTC,PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV"""
|
|
)
|
|
popup "PRU_ICSSG_MDIO"
|
|
(
|
|
menuitem "PRU_ICSSG0_PR1_MDIO_V1P7_MDIO" "per , ""ICSS_0,PRU_ICSSG_MDIO,PRU_ICSSG0_PR1_MDIO_V1P7_MDIO"""
|
|
)
|
|
popup "PRU_ICSSG_MII_G_RT"
|
|
(
|
|
menuitem "PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G" "per , ""ICSS_0,PRU_ICSSG_MII_G_RT,PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G"""
|
|
)
|
|
popup "PRU_ICSSG_MII_RT"
|
|
(
|
|
menuitem "PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG" "per , ""ICSS_0,PRU_ICSSG_MII_RT,PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG"""
|
|
)
|
|
popup "PRU_ICSSG_PROTECT"
|
|
(
|
|
menuitem "PRU_ICSSG0_PR1_PROT_SLV" "per , ""ICSS_0,PRU_ICSSG_PROTECT,PRU_ICSSG0_PR1_PROT_SLV"""
|
|
)
|
|
popup "PRU_ICSSG_PR1_PDSP0_IRAM"
|
|
(
|
|
menuitem "PRU_ICSSG0_PR1_PDSP0_IRAM" "per , ""ICSS_0,PRU_ICSSG_PR1_PDSP0_IRAM,PRU_ICSSG0_PR1_PDSP0_IRAM"""
|
|
menuitem "PRU_ICSSG0_PR1_PDSP1_IRAM" "per , ""ICSS_0,PRU_ICSSG_PR1_PDSP0_IRAM,PRU_ICSSG0_PR1_PDSP1_IRAM"""
|
|
menuitem "PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM" "per , ""ICSS_0,PRU_ICSSG_PR1_PDSP0_IRAM,PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM"""
|
|
menuitem "PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM" "per , ""ICSS_0,PRU_ICSSG_PR1_PDSP0_IRAM,PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM"""
|
|
)
|
|
popup "PRU_ICSSG_PR1_PDSP0_IRAM_DEBUG"
|
|
(
|
|
menuitem "PRU_ICSSG0_PR1_PDSP0_IRAM_DEBUG" "per , ""ICSS_0,PRU_ICSSG_PR1_PDSP0_IRAM_DEBUG,PRU_ICSSG0_PR1_PDSP0_IRAM_DEBUG"""
|
|
menuitem "PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_DEBUG" "per , ""ICSS_0,PRU_ICSSG_PR1_PDSP0_IRAM_DEBUG,PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_DEBUG"""
|
|
menuitem "PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_DEBUG" "per , ""ICSS_0,PRU_ICSSG_PR1_PDSP0_IRAM_DEBUG,PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_DEBUG"""
|
|
menuitem "PRU_ICSSG0_PR1_PDSP1_IRAM_DEBUG" "per , ""ICSS_0,PRU_ICSSG_PR1_PDSP0_IRAM_DEBUG,PRU_ICSSG0_PR1_PDSP1_IRAM_DEBUG"""
|
|
)
|
|
popup "PRU_ICSSG_RAM"
|
|
(
|
|
menuitem "PRU_ICSSG0_RAM_SLV_RAM" "per , ""ICSS_0,PRU_ICSSG_RAM,PRU_ICSSG0_RAM_SLV_RAM"""
|
|
)
|
|
popup "PRU_ICSSG_RAT_SLICE0"
|
|
(
|
|
menuitem "PRU_ICSSG0_RAT_SLICE0_CFG_CFG" "per , ""ICSS_0,PRU_ICSSG_RAT_SLICE0,PRU_ICSSG0_RAT_SLICE0_CFG_CFG"""
|
|
menuitem "PRU_ICSSG0_RAT_SLICE1_CFG" "per , ""ICSS_0,PRU_ICSSG_RAT_SLICE0,PRU_ICSSG0_RAT_SLICE1_CFG"""
|
|
)
|
|
popup "PRU_ICSSG_TASKS_MGR_PRU0"
|
|
(
|
|
menuitem "PRU_ICSSG0_TASKS_MGR_PRU0" "per , ""ICSS_0,PRU_ICSSG_TASKS_MGR_PRU0,PRU_ICSSG0_TASKS_MGR_PRU0"""
|
|
menuitem "PRU_ICSSG0_TASKS_MGR_RTU0" "per , ""ICSS_0,PRU_ICSSG_TASKS_MGR_PRU0,PRU_ICSSG0_TASKS_MGR_RTU0"""
|
|
menuitem "PRU_ICSSG0_TASKS_MGR_PRU1" "per , ""ICSS_0,PRU_ICSSG_TASKS_MGR_PRU0,PRU_ICSSG0_TASKS_MGR_PRU1"""
|
|
menuitem "PRU_ICSSG0_TASKS_MGR_RTU1" "per , ""ICSS_0,PRU_ICSSG_TASKS_MGR_PRU0,PRU_ICSSG0_TASKS_MGR_RTU1"""
|
|
)
|
|
popup "PRU_ICSSG_UART0"
|
|
(
|
|
menuitem "PRU_ICSSG0_PR1_ICSS_UART_UART_SLV" "per , ""ICSS_0,PRU_ICSSG_UART0,PRU_ICSSG0_PR1_ICSS_UART_UART_SLV"""
|
|
)
|
|
)
|
|
popup "ICSS_1"
|
|
(
|
|
popup "PRU_ICSSG_CFG"
|
|
(
|
|
menuitem "PRU_ICSSG1_PR1_CFG_SLV" "per , ""ICSS_1,PRU_ICSSG_CFG,PRU_ICSSG1_PR1_CFG_SLV"""
|
|
)
|
|
popup "PRU_ICSSG_DRAM0"
|
|
(
|
|
menuitem "PRU_ICSSG1_DRAM0_SLV_RAM" "per , ""ICSS_1,PRU_ICSSG_DRAM0,PRU_ICSSG1_DRAM0_SLV_RAM"""
|
|
menuitem "PRU_ICSSG1_DRAM1_SLV_RAM" "per , ""ICSS_1,PRU_ICSSG_DRAM0,PRU_ICSSG1_DRAM1_SLV_RAM"""
|
|
)
|
|
popup "PRU_ICSSG_ECAP0"
|
|
(
|
|
menuitem "PRU_ICSSG1_PR1_ICSS_ECAP0_ECAP_SLV" "per , ""ICSS_1,PRU_ICSSG_ECAP0,PRU_ICSSG1_PR1_ICSS_ECAP0_ECAP_SLV"""
|
|
)
|
|
popup "PRU_ICSSG_ECC_AGGR"
|
|
(
|
|
menuitem "PRU_ICSSG0_ECC_AGGR" "per , ""ICSS_1,PRU_ICSSG_ECC_AGGR,PRU_ICSSG0_ECC_AGGR"""
|
|
)
|
|
popup "PRU_ICSSG_IEP"
|
|
(
|
|
popup "PRU_ICSSG0_IEP0"
|
|
(
|
|
menuitem "PRU_ICSSG1_IEP0" "per , ""ICSS_1,PRU_ICSSG_IEP,PRU_ICSSG0_IEP0,PRU_ICSSG1_IEP0"""
|
|
)
|
|
popup "PRU_ICSSG0_IEP1"
|
|
(
|
|
menuitem "PRU_ICSSG1_IEP1" "per , ""ICSS_1,PRU_ICSSG_IEP,PRU_ICSSG0_IEP1,PRU_ICSSG1_IEP1"""
|
|
)
|
|
)
|
|
popup "PRU_ICSSG_INTC"
|
|
(
|
|
menuitem "PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV" "per , ""ICSS_1,PRU_ICSSG_INTC,PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV"""
|
|
)
|
|
popup "PRU_ICSSG_MDIO"
|
|
(
|
|
menuitem "PRU_ICSSG0_PR1_MDIO_V1P7_MDIO" "per , ""ICSS_1,PRU_ICSSG_MDIO,PRU_ICSSG0_PR1_MDIO_V1P7_MDIO"""
|
|
)
|
|
popup "PRU_ICSSG_MII_G_RT"
|
|
(
|
|
menuitem "PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G" "per , ""ICSS_1,PRU_ICSSG_MII_G_RT,PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G"""
|
|
)
|
|
popup "PRU_ICSSG_MII_RT"
|
|
(
|
|
menuitem "PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG" "per , ""ICSS_1,PRU_ICSSG_MII_RT,PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG"""
|
|
)
|
|
popup "PRU_ICSSG_PROTECT"
|
|
(
|
|
menuitem "PRU_ICSSG0_PR1_PROT_SLV" "per , ""ICSS_1,PRU_ICSSG_PROTECT,PRU_ICSSG0_PR1_PROT_SLV"""
|
|
)
|
|
popup "PRU_ICSSG_PR1_PDSP0_IRAM"
|
|
(
|
|
menuitem "PRU_ICSSG1_PR1_PDSP0_IRAM" "per , ""ICSS_1,PRU_ICSSG_PR1_PDSP0_IRAM,PRU_ICSSG1_PR1_PDSP0_IRAM"""
|
|
menuitem "PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM" "per , ""ICSS_1,PRU_ICSSG_PR1_PDSP0_IRAM,PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM"""
|
|
menuitem "PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM" "per , ""ICSS_1,PRU_ICSSG_PR1_PDSP0_IRAM,PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM"""
|
|
menuitem "PRU_ICSSG1_PR1_PDSP1_IRAM" "per , ""ICSS_1,PRU_ICSSG_PR1_PDSP0_IRAM,PRU_ICSSG1_PR1_PDSP1_IRAM"""
|
|
)
|
|
popup "PRU_ICSSG_PR1_PDSP0_IRAM_DEBUG"
|
|
(
|
|
menuitem "PRU_ICSSG1_PR1_PDSP0_IRAM_DEBUG" "per , ""ICSS_1,PRU_ICSSG_PR1_PDSP0_IRAM_DEBUG,PRU_ICSSG1_PR1_PDSP0_IRAM_DEBUG"""
|
|
menuitem "PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_DEBUG" "per , ""ICSS_1,PRU_ICSSG_PR1_PDSP0_IRAM_DEBUG,PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_DEBUG"""
|
|
menuitem "PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_DEBUG" "per , ""ICSS_1,PRU_ICSSG_PR1_PDSP0_IRAM_DEBUG,PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_DEBUG"""
|
|
menuitem "PRU_ICSSG1_PR1_PDSP1_IRAM_DEBUG" "per , ""ICSS_1,PRU_ICSSG_PR1_PDSP0_IRAM_DEBUG,PRU_ICSSG1_PR1_PDSP1_IRAM_DEBUG"""
|
|
)
|
|
popup "PRU_ICSSG_RAM"
|
|
(
|
|
menuitem "PRU_ICSSG1_RAM_SLV_RAM" "per , ""ICSS_1,PRU_ICSSG_RAM,PRU_ICSSG1_RAM_SLV_RAM"""
|
|
)
|
|
popup "PRU_ICSSG_RAT_SLICE0"
|
|
(
|
|
menuitem "PRU_ICSSG1_RAT_SLICE0_CFG_CFG" "per , ""ICSS_1,PRU_ICSSG_RAT_SLICE0,PRU_ICSSG1_RAT_SLICE0_CFG_CFG"""
|
|
menuitem "PRU_ICSSG1_RAT_SLICE1_CFG" "per , ""ICSS_1,PRU_ICSSG_RAT_SLICE0,PRU_ICSSG1_RAT_SLICE1_CFG"""
|
|
)
|
|
popup "PRU_ICSSG_TASKS_MGR_PRU0"
|
|
(
|
|
menuitem "PRU_ICSSG1_TASKS_MGR_PRU0" "per , ""ICSS_1,PRU_ICSSG_TASKS_MGR_PRU0,PRU_ICSSG1_TASKS_MGR_PRU0"""
|
|
menuitem "PRU_ICSSG1_TASKS_MGR_RTU0" "per , ""ICSS_1,PRU_ICSSG_TASKS_MGR_PRU0,PRU_ICSSG1_TASKS_MGR_RTU0"""
|
|
menuitem "PRU_ICSSG1_TASKS_MGR_PRU1" "per , ""ICSS_1,PRU_ICSSG_TASKS_MGR_PRU0,PRU_ICSSG1_TASKS_MGR_PRU1"""
|
|
menuitem "PRU_ICSSG1_TASKS_MGR_RTU1" "per , ""ICSS_1,PRU_ICSSG_TASKS_MGR_PRU0,PRU_ICSSG1_TASKS_MGR_RTU1"""
|
|
)
|
|
popup "PRU_ICSSG_UART0"
|
|
(
|
|
menuitem "PRU_ICSSG1_PR1_ICSS_UART_UART_SLV" "per , ""ICSS_1,PRU_ICSSG_UART0,PRU_ICSSG1_PR1_ICSS_UART_UART_SLV"""
|
|
)
|
|
)
|
|
popup "ICSS_2"
|
|
(
|
|
popup "PRU_ICSSG_CFG"
|
|
(
|
|
menuitem "PRU_ICSSG2_PR1_CFG_SLV" "per , ""ICSS_2,PRU_ICSSG_CFG,PRU_ICSSG2_PR1_CFG_SLV"""
|
|
)
|
|
popup "PRU_ICSSG_DRAM0"
|
|
(
|
|
menuitem "PRU_ICSSG2_DRAM0_SLV_RAM" "per , ""ICSS_2,PRU_ICSSG_DRAM0,PRU_ICSSG2_DRAM0_SLV_RAM"""
|
|
menuitem "PRU_ICSSG2_DRAM1_SLV_RAM" "per , ""ICSS_2,PRU_ICSSG_DRAM0,PRU_ICSSG2_DRAM1_SLV_RAM"""
|
|
)
|
|
popup "PRU_ICSSG_ECAP0"
|
|
(
|
|
menuitem "PRU_ICSSG2_PR1_ICSS_ECAP0_ECAP_SLV" "per , ""ICSS_2,PRU_ICSSG_ECAP0,PRU_ICSSG2_PR1_ICSS_ECAP0_ECAP_SLV"""
|
|
)
|
|
popup "PRU_ICSSG_ECC_AGGR"
|
|
(
|
|
menuitem "PRU_ICSSG2_ECC_AGGR" "per , ""ICSS_2,PRU_ICSSG_ECC_AGGR,PRU_ICSSG2_ECC_AGGR"""
|
|
)
|
|
popup "PRU_ICSSG_IEP0"
|
|
(
|
|
menuitem "PRU_ICSSG2_IEP0" "per , ""ICSS_2,PRU_ICSSG_IEP0,PRU_ICSSG2_IEP0"""
|
|
menuitem "PRU_ICSSG2_IEP1" "per , ""ICSS_2,PRU_ICSSG_IEP0,PRU_ICSSG2_IEP1"""
|
|
)
|
|
popup "PRU_ICSSG_INTC"
|
|
(
|
|
menuitem "PRU_ICSSG2_PR1_ICSS_INTC_INTC_SLV" "per , ""ICSS_2,PRU_ICSSG_INTC,PRU_ICSSG2_PR1_ICSS_INTC_INTC_SLV"""
|
|
)
|
|
popup "PRU_ICSSG_MDIO"
|
|
(
|
|
menuitem "PRU_ICSSG2_PR1_MDIO_V1P7_MDIO" "per , ""ICSS_2,PRU_ICSSG_MDIO,PRU_ICSSG2_PR1_MDIO_V1P7_MDIO"""
|
|
)
|
|
popup "PRU_ICSSG_MII_G_RT"
|
|
(
|
|
menuitem "PRU_ICSSG2_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G" "per , ""ICSS_2,PRU_ICSSG_MII_G_RT,PRU_ICSSG2_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G"""
|
|
)
|
|
popup "PRU_ICSSG_MII_RT"
|
|
(
|
|
menuitem "PRU_ICSSG2_PR1_MII_RT_PR1_MII_RT_CFG" "per , ""ICSS_2,PRU_ICSSG_MII_RT,PRU_ICSSG2_PR1_MII_RT_PR1_MII_RT_CFG"""
|
|
)
|
|
popup "PRU_ICSSG_PROTECT"
|
|
(
|
|
menuitem "PRU_ICSSG2_PR1_PROT_SLV" "per , ""ICSS_2,PRU_ICSSG_PROTECT,PRU_ICSSG2_PR1_PROT_SLV"""
|
|
)
|
|
popup "PRU_ICSSG_PR1_PDSP0_IRAM"
|
|
(
|
|
menuitem "PRU_ICSSG2_PR1_PDSP0_IRAM" "per , ""ICSS_2,PRU_ICSSG_PR1_PDSP0_IRAM,PRU_ICSSG2_PR1_PDSP0_IRAM"""
|
|
menuitem "PRU_ICSSG2_PR1_RTU0_PR1_RTU0_IRAM" "per , ""ICSS_2,PRU_ICSSG_PR1_PDSP0_IRAM,PRU_ICSSG2_PR1_RTU0_PR1_RTU0_IRAM"""
|
|
menuitem "PRU_ICSSG2_PR1_RTU1_PR1_RTU1_IRAM" "per , ""ICSS_2,PRU_ICSSG_PR1_PDSP0_IRAM,PRU_ICSSG2_PR1_RTU1_PR1_RTU1_IRAM"""
|
|
menuitem "PRU_ICSSG2_PR1_PDSP1_IRAM" "per , ""ICSS_2,PRU_ICSSG_PR1_PDSP0_IRAM,PRU_ICSSG2_PR1_PDSP1_IRAM"""
|
|
)
|
|
popup "PRU_ICSSG_PR1_PDSP0_IRAM_DEBUG"
|
|
(
|
|
menuitem "PRU_ICSSG2_PR1_PDSP0_IRAM_DEBUG" "per , ""ICSS_2,PRU_ICSSG_PR1_PDSP0_IRAM_DEBUG,PRU_ICSSG2_PR1_PDSP0_IRAM_DEBUG"""
|
|
menuitem "PRU_ICSSG2_PR1_RTU0_PR1_RTU0_IRAM_DEBUG" "per , ""ICSS_2,PRU_ICSSG_PR1_PDSP0_IRAM_DEBUG,PRU_ICSSG2_PR1_RTU0_PR1_RTU0_IRAM_DEBUG"""
|
|
menuitem "PRU_ICSSG2_PR1_RTU1_PR1_RTU1_IRAM_DEBUG" "per , ""ICSS_2,PRU_ICSSG_PR1_PDSP0_IRAM_DEBUG,PRU_ICSSG2_PR1_RTU1_PR1_RTU1_IRAM_DEBUG"""
|
|
menuitem "PRU_ICSSG2_PR1_PDSP1_IRAM_DEBUG" "per , ""ICSS_2,PRU_ICSSG_PR1_PDSP0_IRAM_DEBUG,PRU_ICSSG2_PR1_PDSP1_IRAM_DEBUG"""
|
|
)
|
|
popup "PRU_ICSSG_RAM"
|
|
(
|
|
menuitem "PRU_ICSSG2_RAM_SLV_RAM" "per , ""ICSS_2,PRU_ICSSG_RAM,PRU_ICSSG2_RAM_SLV_RAM"""
|
|
)
|
|
popup "PRU_ICSSG_RAT_SLICE"
|
|
(
|
|
menuitem "PRU_ICSSG2_RAT_SLICE0_CFG_CFG" "per , ""ICSS_2,PRU_ICSSG_RAT_SLICE,PRU_ICSSG2_RAT_SLICE0_CFG_CFG"""
|
|
menuitem "PRU_ICSSG2_RAT_SLICE1_CFG" "per , ""ICSS_2,PRU_ICSSG_RAT_SLICE,PRU_ICSSG2_RAT_SLICE1_CFG"""
|
|
)
|
|
popup "PRU_ICSSG_SGMII0"
|
|
(
|
|
menuitem "PRU_ICSSG2_PR1_MII_RT_PR1_SGMII0_CFG_SGMII0" "per , ""ICSS_2,PRU_ICSSG_SGMII0,PRU_ICSSG2_PR1_MII_RT_PR1_SGMII0_CFG_SGMII0"""
|
|
menuitem "PRU_ICSSG2_PR1_MII_RT_PR1_SGMII1_CFG_SGMII1" "per , ""ICSS_2,PRU_ICSSG_SGMII0,PRU_ICSSG2_PR1_MII_RT_PR1_SGMII1_CFG_SGMII1"""
|
|
)
|
|
popup "PRU_ICSSG_TASKS_MGR_PRU"
|
|
(
|
|
menuitem "PRU_ICSSG2_TASKS_MGR_PRU0" "per , ""ICSS_2,PRU_ICSSG_TASKS_MGR_PRU,PRU_ICSSG2_TASKS_MGR_PRU0"""
|
|
menuitem "PRU_ICSSG2_TASKS_MGR_RTU0" "per , ""ICSS_2,PRU_ICSSG_TASKS_MGR_PRU,PRU_ICSSG2_TASKS_MGR_RTU0"""
|
|
menuitem "PRU_ICSSG2_TASKS_MGR_PRU1" "per , ""ICSS_2,PRU_ICSSG_TASKS_MGR_PRU,PRU_ICSSG2_TASKS_MGR_PRU1"""
|
|
menuitem "PRU_ICSSG2_TASKS_MGR_RTU1" "per , ""ICSS_2,PRU_ICSSG_TASKS_MGR_PRU,PRU_ICSSG2_TASKS_MGR_RTU1"""
|
|
)
|
|
popup "PRU_ICSSG_UART"
|
|
(
|
|
menuitem "PRU_ICSSG2_PR1_ICSS_UART_UART_SLV" "per , ""ICSS_2,PRU_ICSSG_UART,PRU_ICSSG2_PR1_ICSS_UART_UART_SLV"""
|
|
)
|
|
)
|
|
)
|
|
)
|
|
)
|