1105 lines
72 KiB
Plaintext
1105 lines
72 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: AM576x Specific Menu
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; @Props: Released
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; @Author: DLI, PIW
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; @Changelog: 2019-08-13 DLI
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; 2022-05-11 PIW
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; @Manufacturer: TI - Texas Instruments
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; @Core: ARM968E, C66x, Cortex-M4, PRU, Cortex-A15MPCore
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; @Chip: AM576XDSP1, AM576XDSP2, AM576XIPU1-CORE0, AM576XIPU1-CORE1,
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; AM576XIPU2-CORE0, AM576XIVA1, AM576x, AM576XIVA2,
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; AM576XIPU2-CORE1, AM576X-ICSS0, AM576X-ICSS1
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: menam576x.men 16339 2023-07-03 13:30:14Z pegold $
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add
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menu
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(
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if (!cpuis("AM574X-ICSS?")&&!cpuis("PRU"))
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(
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if (CPUFAMILY()=="C6000")
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(
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popup "&CPU"
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(
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after "FPU Registers"
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separator
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popup "[:cache]Cache"
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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popup "&Trace"
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(
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("AET")
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(
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menuitem "[:oconfig]AET settings..." "AET.state"
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)
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)
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popup "&Perf"
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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else
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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)
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popup "Peripherals"
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(
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if (cpuis("AM576x"))
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(
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popup "[:chip]Core Registers (Cortex-A15MPCore)"
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(
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menuitem "[:chip]ID Registers" "per , ""Core Registers (Cortex-A15MPCore),ID Registers"""
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menuitem "[:chip]System Control and Configuration" "per , ""Core Registers (Cortex-A15MPCore),System Control and Configuration"""
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menuitem "[:chip]Memory Management Unit" "per , ""Core Registers (Cortex-A15MPCore),Memory Management Unit"""
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menuitem "[:chip]Virtualization Extensions" "per , ""Core Registers (Cortex-A15MPCore),Virtualization Extensions"""
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menuitem "[:chip]Cache Control and Configuration" "per , ""Core Registers (Cortex-A15MPCore),Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor" "per , ""Core Registers (Cortex-A15MPCore),System Performance Monitor"""
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menuitem "[:chip]System Timer Register" "per , ""Core Registers (Cortex-A15MPCore),System Timer Register"""
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separator
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menuitem "[:chip]Debug Registers" "per , ""Core Registers (Cortex-A15MPCore),Debug Registers"""
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menuitem "[:chip]Breakpoint Registers" "per , ""Core Registers (Cortex-A15MPCore),Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Control Registers" "per , ""Core Registers (Cortex-A15MPCore),Watchpoint Control Registers"""
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separator
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menuitem "[:chip]Interrupt Controller" "per , ""Core Registers (Cortex-A15MPCore),Interrupt Controller"""
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)
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)
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else if cpuis("AM576XIPU*")
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(
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popup "[:chip]Core Registers (Cortex-M4)"
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(
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menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M4),System Control"""
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menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M4),Memory Protection Unit"""
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menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M4),Nested Vectored Interrupt Controller"""
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popup "[:chip]Debug"
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(
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menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M4),Debug,Core Debug"""
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menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M4),Debug,Flash Patch and Breakpoint Unit (FPB)"""
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menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M4),Debug,Data Watchpoint and Trace Unit (DWT)"""
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)
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)
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)
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else if cpuis("AM576XDSP?")
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(
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popup "[:chip]Core Registers (c66x)"
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(
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menuitem "[:chip]L1P;L1P Registers" "per , ""Core Registers (c66x),Cache,L1P Cache"""
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menuitem "[:chip]L1D;L1D Registers" "per , ""Core Registers (c66x),Cache,L1D Cache"""
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menuitem "[:chip]L2;L2 Registers" "per , ""Core Registers (c66x),Cache,L2 Cache"""
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menuitem "[:chip]IDMA;IDMA Registers" "per , ""Core Registers (c66x),IDMA (Internal Direct Memory Access Controller)"""
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menuitem "[:chip]XMC;XMC Registers" "per , ""Core Registers (c66x),XMC (Extended Memory Controller)"""
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menuitem "[:chip]BM;BM Registers" "per , ""Core Registers (c66x),Bandwith Management"""
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menuitem "[:chip]IC;IC Registers" "per , ""Core Registers (c66x),Interrupt Controller"""
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menuitem "[:chip]PD;PD Registers" "per , ""Core Registers (c66x),Power-Down Controller"""
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)
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)
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else if cpuis("AM576XIVA?")
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(
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menuitem "[:chip]Core Registers (ARM966)" "per , ""Core Registers (ARM966)"""
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)
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separator
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popup "_32_kHz_Synchronized_Timer__COUNTER_32K"
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(
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menuitem "L4_WKUP_COUNTER_32K" "per , ""_32_kHz_Synchronized_Timer__COUNTER_32K,L4_WKUP_COUNTER_32K"""
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)
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popup "BB2D"
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(
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menuitem "BB2D" "per , ""BB2D,BB2D"""
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)
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popup "CAMSS"
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(
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menuitem "CAL" "per , ""CAMSS,CAL"""
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menuitem "CAMERARX_CORE_0" "per , ""CAMSS,CAMERARX_CORE_0"""
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menuitem "CAMERARX_CORE_1" "per , ""CAMSS,CAMERARX_CORE_1"""
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)
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popup "Control_Module"
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(
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menuitem "CTRL_MODULE_CORE" "per , ""Control_Module,CTRL_MODULE_CORE"""
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menuitem "CTRL_MODULE_WKUP" "per , ""Control_Module,CTRL_MODULE_WKUP"""
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)
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popup "DCAN"
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(
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menuitem "DCAN1" "per , ""DCAN,DCAN1"""
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menuitem "DCAN2" "per , ""DCAN,DCAN2"""
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)
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popup "Display_Controller"
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(
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menuitem "DISPC" "per , ""Display_Controller,DISPC"""
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)
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popup "Display_Subsystem"
|
|
(
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menuitem "DPLL_HDMI_L3_MAIN" "per , ""Display_Subsystem,DPLL_HDMI_L3_MAIN"""
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menuitem "DPLL_HDMI_L4_CFG" "per , ""Display_Subsystem,DPLL_HDMI_L4_CFG"""
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menuitem "DPLL_VIDEO1_L3_MAIN" "per , ""Display_Subsystem,DPLL_VIDEO1_L3_MAIN"""
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menuitem "DPLL_VIDEO1_L4_CFG" "per , ""Display_Subsystem,DPLL_VIDEO1_L4_CFG"""
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menuitem "DPLL_VIDEO2_L3_MAIN" "per , ""Display_Subsystem,DPLL_VIDEO2_L3_MAIN"""
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menuitem "DPLL_VIDEO2_L4_CFG" "per , ""Display_Subsystem,DPLL_VIDEO2_L4_CFG"""
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menuitem "DSI1_A_L3_MAIN" "per , ""Display_Subsystem,DSI1_A_L3_MAIN"""
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menuitem "DSI1_C_L3_MAIN" "per , ""Display_Subsystem,DSI1_C_L3_MAIN"""
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|
menuitem "DSS_L3_MAIN" "per , ""Display_Subsystem,DSS_L3_MAIN"""
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menuitem "HDMI_WP_L3_MAIN" "per , ""Display_Subsystem,HDMI_WP_L3_MAIN"""
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menuitem "OCP2SCP2_L4_CFG" "per , ""Display_Subsystem,OCP2SCP2_L4_CFG"""
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)
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popup "DRM"
|
|
(
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menuitem "DRM" "per , ""DRM,DRM"""
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)
|
|
popup "DSP_Subsystem"
|
|
(
|
|
menuitem "DSP1_FW_L2_NOC_CFG" "per , ""DSP_Subsystem,DSP1_FW_L2_NOC_CFG"""
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|
menuitem "DSP2_FW_L2_NOC_CFG" "per , ""DSP_Subsystem,DSP2_FW_L2_NOC_CFG"""
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|
menuitem "DSP_FW_L2_NOC_CFG" "per , ""DSP_Subsystem,DSP_FW_L2_NOC_CFG"""
|
|
menuitem "DSP1_SYSTEM" "per , ""DSP_Subsystem,DSP1_SYSTEM"""
|
|
menuitem "DSP2_SYSTEM" "per , ""DSP_Subsystem,DSP2_SYSTEM"""
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menuitem "DSP_SYSTEM" "per , ""DSP_Subsystem,DSP_SYSTEM"""
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)
|
|
popup "Dual_Cortex_A15_MPU_Subsystem"
|
|
(
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|
menuitem "MPU_AXI2OCP_MISC" "per , ""Dual_Cortex_A15_MPU_Subsystem,MPU_AXI2OCP_MISC"""
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|
menuitem "MPU_MA_WP" "per , ""Dual_Cortex_A15_MPU_Subsystem,MPU_MA_WP"""
|
|
menuitem "MPU_PRCM_CM_C0" "per , ""Dual_Cortex_A15_MPU_Subsystem,MPU_PRCM_CM_C0"""
|
|
menuitem "MPU_PRCM_CM_C1" "per , ""Dual_Cortex_A15_MPU_Subsystem,MPU_PRCM_CM_C1"""
|
|
menuitem "MPU_PRCM_DEVICE" "per , ""Dual_Cortex_A15_MPU_Subsystem,MPU_PRCM_DEVICE"""
|
|
menuitem "MPU_PRCM_OCP_SOCKET" "per , ""Dual_Cortex_A15_MPU_Subsystem,MPU_PRCM_OCP_SOCKET"""
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|
menuitem "MPU_PRCM_PRM_C0" "per , ""Dual_Cortex_A15_MPU_Subsystem,MPU_PRCM_PRM_C0"""
|
|
menuitem "MPU_PRCM_PRM_C1" "per , ""Dual_Cortex_A15_MPU_Subsystem,MPU_PRCM_PRM_C1"""
|
|
menuitem "REG_Bundle_0" "per , ""Dual_Cortex_A15_MPU_Subsystem,REG_Bundle_0"""
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|
menuitem "REG_Bundle_1" "per , ""Dual_Cortex_A15_MPU_Subsystem,REG_Bundle_1"""
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|
menuitem "MPU_WUGEN" "per , ""Dual_Cortex_A15_MPU_Subsystem,MPU_WUGEN"""
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|
)
|
|
popup "Dual_Cortex_M4_IPU_Subsystem"
|
|
(
|
|
menuitem "IPU1_UNICACHE_CFG" "per , ""Dual_Cortex_M4_IPU_Subsystem,IPU1_UNICACHE_CFG"""
|
|
menuitem "IPU2_UNICACHE_CFG" "per , ""Dual_Cortex_M4_IPU_Subsystem,IPU2_UNICACHE_CFG"""
|
|
menuitem "IPU1_UNICACHE_MMU_AMMU" "per , ""Dual_Cortex_M4_IPU_Subsystem,IPU1_UNICACHE_MMU_AMMU"""
|
|
menuitem "IPU2_UNICACHE_MMU_AMMU" "per , ""Dual_Cortex_M4_IPU_Subsystem,IPU2_UNICACHE_MMU_AMMU"""
|
|
menuitem "IPU1_UNICACHE_SCTM" "per , ""Dual_Cortex_M4_IPU_Subsystem,IPU1_UNICACHE_SCTM"""
|
|
menuitem "IPU2_UNICACHE_SCTM" "per , ""Dual_Cortex_M4_IPU_Subsystem,IPU2_UNICACHE_SCTM"""
|
|
menuitem "IPU1_WUGEN" "per , ""Dual_Cortex_M4_IPU_Subsystem,IPU1_WUGEN"""
|
|
menuitem "IPU2_WUGEN" "per , ""Dual_Cortex_M4_IPU_Subsystem,IPU2_WUGEN"""
|
|
)
|
|
popup "Dynamic_Memory_Manager"
|
|
(
|
|
menuitem "DMM" "per , ""Dynamic_Memory_Manager,DMM"""
|
|
)
|
|
popup "EMIF_Controller"
|
|
(
|
|
menuitem "EMIF1" "per , ""EMIF_Controller,EMIF1"""
|
|
menuitem "EMIF2" "per , ""EMIF_Controller,EMIF2"""
|
|
)
|
|
popup "eMMC_SD_SDIO_Overview"
|
|
(
|
|
menuitem "MMC1" "per , ""eMMC_SD_SDIO_Overview,MMC1"""
|
|
menuitem "MMC2" "per , ""eMMC_SD_SDIO_Overview,MMC2"""
|
|
menuitem "MMC3" "per , ""eMMC_SD_SDIO_Overview,MMC3"""
|
|
menuitem "MMC4" "per , ""eMMC_SD_SDIO_Overview,MMC4"""
|
|
)
|
|
popup "Enhanced_DMA"
|
|
(
|
|
menuitem "DSP1_EDMA_TPCC" "per , ""Enhanced_DMA,DSP1_EDMA_TPCC"""
|
|
menuitem "DSP2_EDMA_TPCC" "per , ""Enhanced_DMA,DSP2_EDMA_TPCC"""
|
|
menuitem "DSP_EDMA_TPCC" "per , ""Enhanced_DMA,DSP_EDMA_TPCC"""
|
|
menuitem "SYS_EDMA_TPTC0" "per , ""Enhanced_DMA,SYS_EDMA_TPTC0"""
|
|
menuitem "SYS_EDMA_TPTC1" "per , ""Enhanced_DMA,SYS_EDMA_TPTC1"""
|
|
menuitem "DSP2_EDMA_TPTC0" "per , ""Enhanced_DMA,DSP2_EDMA_TPTC0"""
|
|
menuitem "DSP2_EDMA_TPTC1" "per , ""Enhanced_DMA,DSP2_EDMA_TPTC1"""
|
|
menuitem "DSP1_EDMA_TPTC0" "per , ""Enhanced_DMA,DSP1_EDMA_TPTC0"""
|
|
menuitem "DSP1_EDMA_TPTC1" "per , ""Enhanced_DMA,DSP1_EDMA_TPTC1"""
|
|
menuitem "DSP_EDMA_TPTC0" "per , ""Enhanced_DMA,DSP_EDMA_TPTC0"""
|
|
menuitem "DSP_EDMA_TPTC1" "per , ""Enhanced_DMA,DSP_EDMA_TPTC1"""
|
|
menuitem "EVE1_EDMA_TPCC" "per , ""Enhanced_DMA,EVE1_EDMA_TPCC"""
|
|
menuitem "EVE2_EDMA_TPCC" "per , ""Enhanced_DMA,EVE2_EDMA_TPCC"""
|
|
menuitem "EVE4_EDMA_TPTC0" "per , ""Enhanced_DMA,EVE4_EDMA_TPTC0"""
|
|
menuitem "EVE4_EDMA_TPTC1" "per , ""Enhanced_DMA,EVE4_EDMA_TPTC1"""
|
|
menuitem "EVE3_EDMA_TPTC0" "per , ""Enhanced_DMA,EVE3_EDMA_TPTC0"""
|
|
menuitem "EVE3_EDMA_TPTC1" "per , ""Enhanced_DMA,EVE3_EDMA_TPTC1"""
|
|
menuitem "EVE2_EDMA_TPTC0" "per , ""Enhanced_DMA,EVE2_EDMA_TPTC0"""
|
|
menuitem "EVE2_EDMA_TPTC1" "per , ""Enhanced_DMA,EVE2_EDMA_TPTC1"""
|
|
menuitem "EVE1_EDMA_TPTC0" "per , ""Enhanced_DMA,EVE1_EDMA_TPTC0"""
|
|
menuitem "EVE1_EDMA_TPTC1" "per , ""Enhanced_DMA,EVE1_EDMA_TPTC1"""
|
|
menuitem "EVE3_EDMA_TPCC" "per , ""Enhanced_DMA,EVE3_EDMA_TPCC"""
|
|
menuitem "EVE4_EDMA_TPCC" "per , ""Enhanced_DMA,EVE4_EDMA_TPCC"""
|
|
menuitem "SYS_EDMA_TPCC" "per , ""Enhanced_DMA,SYS_EDMA_TPCC"""
|
|
)
|
|
popup "Error_Location_Module"
|
|
(
|
|
menuitem "ELM" "per , ""Error_Location_Module,ELM"""
|
|
)
|
|
popup "General_Purpose_Interface"
|
|
(
|
|
menuitem "GPIO1" "per , ""General_Purpose_Interface,GPIO1"""
|
|
menuitem "GPIO2" "per , ""General_Purpose_Interface,GPIO2"""
|
|
menuitem "GPIO3" "per , ""General_Purpose_Interface,GPIO3"""
|
|
menuitem "GPIO4" "per , ""General_Purpose_Interface,GPIO4"""
|
|
menuitem "GPIO5" "per , ""General_Purpose_Interface,GPIO5"""
|
|
menuitem "GPIO6" "per , ""General_Purpose_Interface,GPIO6"""
|
|
menuitem "GPIO7" "per , ""General_Purpose_Interface,GPIO7"""
|
|
menuitem "GPIO8" "per , ""General_Purpose_Interface,GPIO8"""
|
|
)
|
|
popup "General_Purpose_Memory_Controller"
|
|
(
|
|
menuitem "GPMC" "per , ""General_Purpose_Memory_Controller,GPMC"""
|
|
)
|
|
popup "General_Purpose_Timers"
|
|
(
|
|
menuitem "TIMER10_L4_PER1Interconnect" "per , ""General_Purpose_Timers,TIMER10_L4_PER1Interconnect"""
|
|
menuitem "TIMER1_L4_WKUPInterconnect" "per , ""General_Purpose_Timers,TIMER1_L4_WKUPInterconnect"""
|
|
menuitem "TIMER2_L4_PER1Interconnect" "per , ""General_Purpose_Timers,TIMER2_L4_PER1Interconnect"""
|
|
menuitem "TIMER11_L4_PER1Interconnect" "per , ""General_Purpose_Timers,TIMER11_L4_PER1Interconnect"""
|
|
menuitem "TIMER12_L4_WKUPInterconnect" "per , ""General_Purpose_Timers,TIMER12_L4_WKUPInterconnect"""
|
|
menuitem "TIMER13_L4_PER3Interconnect" "per , ""General_Purpose_Timers,TIMER13_L4_PER3Interconnect"""
|
|
menuitem "TIMER14_L4_PER3Interconnect" "per , ""General_Purpose_Timers,TIMER14_L4_PER3Interconnect"""
|
|
menuitem "TIMER15_L4_PER3Interconnect" "per , ""General_Purpose_Timers,TIMER15_L4_PER3Interconnect"""
|
|
menuitem "TIMER16_L4_PER3Interconnect" "per , ""General_Purpose_Timers,TIMER16_L4_PER3Interconnect"""
|
|
menuitem "TIMER3_L4_PER1Interconnect" "per , ""General_Purpose_Timers,TIMER3_L4_PER1Interconnect"""
|
|
menuitem "TIMER4_L4_PER1Interconnect" "per , ""General_Purpose_Timers,TIMER4_L4_PER1Interconnect"""
|
|
menuitem "TIMER5_L4_PER3Interconnect" "per , ""General_Purpose_Timers,TIMER5_L4_PER3Interconnect"""
|
|
menuitem "TIMER6_L4_PER3Interconnect" "per , ""General_Purpose_Timers,TIMER6_L4_PER3Interconnect"""
|
|
menuitem "TIMER7_L4_PER3Interconnect" "per , ""General_Purpose_Timers,TIMER7_L4_PER3Interconnect"""
|
|
menuitem "TIMER8_L4_PER3Interconnect" "per , ""General_Purpose_Timers,TIMER8_L4_PER3Interconnect"""
|
|
menuitem "TIMER9_L4_PER1Interconnect" "per , ""General_Purpose_Timers,TIMER9_L4_PER1Interconnect"""
|
|
)
|
|
popup "Gigabit_Ethernet_Switch__GMAC_SW"
|
|
(
|
|
menuitem "ALE" "per , ""Gigabit_Ethernet_Switch__GMAC_SW,ALE"""
|
|
menuitem "CPDMA" "per , ""Gigabit_Ethernet_Switch__GMAC_SW,CPDMA"""
|
|
menuitem "CPTS" "per , ""Gigabit_Ethernet_Switch__GMAC_SW,CPTS"""
|
|
menuitem "MDIO" "per , ""Gigabit_Ethernet_Switch__GMAC_SW,MDIO"""
|
|
menuitem "PORT" "per , ""Gigabit_Ethernet_Switch__GMAC_SW,PORT"""
|
|
menuitem "SL1" "per , ""Gigabit_Ethernet_Switch__GMAC_SW,SL1"""
|
|
menuitem "SL2" "per , ""Gigabit_Ethernet_Switch__GMAC_SW,SL2"""
|
|
menuitem "SPF1" "per , ""Gigabit_Ethernet_Switch__GMAC_SW,SPF1"""
|
|
menuitem "SPF2" "per , ""Gigabit_Ethernet_Switch__GMAC_SW,SPF2"""
|
|
menuitem "SS" "per , ""Gigabit_Ethernet_Switch__GMAC_SW,SS"""
|
|
menuitem "STATERAM" "per , ""Gigabit_Ethernet_Switch__GMAC_SW,STATERAM"""
|
|
menuitem "STATS" "per , ""Gigabit_Ethernet_Switch__GMAC_SW,STATS"""
|
|
menuitem "WR" "per , ""Gigabit_Ethernet_Switch__GMAC_SW,WR"""
|
|
)
|
|
popup "GPU"
|
|
(
|
|
menuitem "GPU_WRAPPER" "per , ""GPU,GPU_WRAPPER"""
|
|
)
|
|
popup "HDQ_1_Wire"
|
|
(
|
|
menuitem "HDQ1W" "per , ""HDQ_1_Wire,HDQ1W"""
|
|
)
|
|
popup "IODELAYCONFIG_Module"
|
|
(
|
|
menuitem "IODELAYCONFIG" "per , ""IODELAYCONFIG_Module,IODELAYCONFIG"""
|
|
)
|
|
popup "Keyboard_Controller"
|
|
(
|
|
menuitem "KBD" "per , ""Keyboard_Controller,KBD"""
|
|
)
|
|
popup "L3_MAIN_Interconnect"
|
|
(
|
|
menuitem "CLK1_2_BB2D_P1_BW_LIMITER" "per , ""L3_MAIN_Interconnect,CLK1_2_BB2D_P1_BW_LIMITER"""
|
|
menuitem "CLK1_2_BB2D_P2_BW_LIMITER" "per , ""L3_MAIN_Interconnect,CLK1_2_BB2D_P2_BW_LIMITER"""
|
|
menuitem "CLK1_2_GPU_P1_BW_LIMITER" "per , ""L3_MAIN_Interconnect,CLK1_2_GPU_P1_BW_LIMITER"""
|
|
menuitem "CLK1_2_GPU_P2_BW_LIMITER" "per , ""L3_MAIN_Interconnect,CLK1_2_GPU_P2_BW_LIMITER"""
|
|
menuitem "CLK1_2_MMU1_BW_LIMITER" "per , ""L3_MAIN_Interconnect,CLK1_2_MMU1_BW_LIMITER"""
|
|
menuitem "CLK1_2_TPTC1_RD_BW_LIMITER" "per , ""L3_MAIN_Interconnect,CLK1_2_TPTC1_RD_BW_LIMITER"""
|
|
menuitem "CLK1_2_TPTC1_WR_BW_LIMITER" "per , ""L3_MAIN_Interconnect,CLK1_2_TPTC1_WR_BW_LIMITER"""
|
|
menuitem "CLK1_2_TPTC2_RD_BW_LIMITER" "per , ""L3_MAIN_Interconnect,CLK1_2_TPTC2_RD_BW_LIMITER"""
|
|
menuitem "CLK1_2_TPTC2_WR_BW_LIMITER" "per , ""L3_MAIN_Interconnect,CLK1_2_TPTC2_WR_BW_LIMITER"""
|
|
menuitem "CLK1_2_VPE_P1_BW_LIMITER" "per , ""L3_MAIN_Interconnect,CLK1_2_VPE_P1_BW_LIMITER"""
|
|
menuitem "CLK1_2_VPE_P2_BW_LIMITER" "per , ""L3_MAIN_Interconnect,CLK1_2_VPE_P2_BW_LIMITER"""
|
|
menuitem "CLK1_2_BB2D_P1_BW_REGULATOR" "per , ""L3_MAIN_Interconnect,CLK1_2_BB2D_P1_BW_REGULATOR"""
|
|
menuitem "CLK1_2_BB2D_P2_BW_REGULATOR" "per , ""L3_MAIN_Interconnect,CLK1_2_BB2D_P2_BW_REGULATOR"""
|
|
menuitem "CLK1_2_DSP1_EDMA_BW_REGULATOR" "per , ""L3_MAIN_Interconnect,CLK1_2_DSP1_EDMA_BW_REGULATOR"""
|
|
menuitem "CLK1_2_DSP1_MDMA_BW_REGULATOR" "per , ""L3_MAIN_Interconnect,CLK1_2_DSP1_MDMA_BW_REGULATOR"""
|
|
menuitem "CLK1_2_DSP2_EDMA_BW_REGULATOR" "per , ""L3_MAIN_Interconnect,CLK1_2_DSP2_EDMA_BW_REGULATOR"""
|
|
menuitem "CLK1_2_DSP2_MDMA_BW_REGULATOR" "per , ""L3_MAIN_Interconnect,CLK1_2_DSP2_MDMA_BW_REGULATOR"""
|
|
menuitem "CLK1_2_EVE1_TC0_BW_REGULATOR" "per , ""L3_MAIN_Interconnect,CLK1_2_EVE1_TC0_BW_REGULATOR"""
|
|
menuitem "CLK1_2_EVE1_TC1_BW_REGULATOR" "per , ""L3_MAIN_Interconnect,CLK1_2_EVE1_TC1_BW_REGULATOR"""
|
|
menuitem "CLK1_2_EVE2_TC0_BW_REGULATOR" "per , ""L3_MAIN_Interconnect,CLK1_2_EVE2_TC0_BW_REGULATOR"""
|
|
menuitem "CLK1_2_EVE2_TC1_BW_REGULATOR" "per , ""L3_MAIN_Interconnect,CLK1_2_EVE2_TC1_BW_REGULATOR"""
|
|
menuitem "CLK1_2_GMAC_SW_BW_REGULATOR" "per , ""L3_MAIN_Interconnect,CLK1_2_GMAC_SW_BW_REGULATOR"""
|
|
menuitem "CLK1_2_GPU_P1_BW_REGULATOR" "per , ""L3_MAIN_Interconnect,CLK1_2_GPU_P1_BW_REGULATOR"""
|
|
menuitem "CLK1_2_GPU_P2_BW_REGULATOR" "per , ""L3_MAIN_Interconnect,CLK1_2_GPU_P2_BW_REGULATOR"""
|
|
menuitem "CLK1_2_IVA_BW_REGULATOR" "per , ""L3_MAIN_Interconnect,CLK1_2_IVA_BW_REGULATOR"""
|
|
menuitem "CLK1_2_MMU2_BW_REGULATOR" "per , ""L3_MAIN_Interconnect,CLK1_2_MMU2_BW_REGULATOR"""
|
|
menuitem "CLK1_2_PCIESS1_BW_REGULATOR" "per , ""L3_MAIN_Interconnect,CLK1_2_PCIESS1_BW_REGULATOR"""
|
|
menuitem "CLK1_2_PCIESS2_BW_REGULATOR" "per , ""L3_MAIN_Interconnect,CLK1_2_PCIESS2_BW_REGULATOR"""
|
|
menuitem "CLK1_FLAGMUX_CLK1" "per , ""L3_MAIN_Interconnect,CLK1_FLAGMUX_CLK1"""
|
|
menuitem "CLK1_FLAGMUX_CLK1_1" "per , ""L3_MAIN_Interconnect,CLK1_FLAGMUX_CLK1_1"""
|
|
menuitem "CLK1_FLAGMUX_CLK1_2" "per , ""L3_MAIN_Interconnect,CLK1_FLAGMUX_CLK1_2"""
|
|
menuitem "CLK2_FLAGMUX_CLK2_1" "per , ""L3_MAIN_Interconnect,CLK2_FLAGMUX_CLK2_1"""
|
|
menuitem "CLK1_FLAGMUX_CLK1MERGE" "per , ""L3_MAIN_Interconnect,CLK1_FLAGMUX_CLK1MERGE"""
|
|
menuitem "CLK1_HOST_CLK1_1" "per , ""L3_MAIN_Interconnect,CLK1_HOST_CLK1_1"""
|
|
menuitem "CLK1_HOST_CLK1_2" "per , ""L3_MAIN_Interconnect,CLK1_HOST_CLK1_2"""
|
|
menuitem "CLK2_HOST_CLK2_1" "per , ""L3_MAIN_Interconnect,CLK2_HOST_CLK2_1"""
|
|
menuitem "CLK2_FLAGMUX_CLK2" "per , ""L3_MAIN_Interconnect,CLK2_FLAGMUX_CLK2"""
|
|
menuitem "CLK2_FLAGMUX_STATCOLL" "per , ""L3_MAIN_Interconnect,CLK2_FLAGMUX_STATCOLL"""
|
|
menuitem "CLK2_STATCOLL0" "per , ""L3_MAIN_Interconnect,CLK2_STATCOLL0"""
|
|
menuitem "CLK2_STATCOLL1" "per , ""L3_MAIN_Interconnect,CLK2_STATCOLL1"""
|
|
menuitem "CLK2_STATCOLL2" "per , ""L3_MAIN_Interconnect,CLK2_STATCOLL2"""
|
|
menuitem "CLK2_STATCOLL4" "per , ""L3_MAIN_Interconnect,CLK2_STATCOLL4"""
|
|
menuitem "CLK2_STATCOLL5" "per , ""L3_MAIN_Interconnect,CLK2_STATCOLL5"""
|
|
menuitem "CLK2_STATCOLL6" "per , ""L3_MAIN_Interconnect,CLK2_STATCOLL6"""
|
|
menuitem "CLK2_STATCOLL7" "per , ""L3_MAIN_Interconnect,CLK2_STATCOLL7"""
|
|
menuitem "CLK2_STATCOLL8" "per , ""L3_MAIN_Interconnect,CLK2_STATCOLL8"""
|
|
menuitem "CLK2_STATCOLL9" "per , ""L3_MAIN_Interconnect,CLK2_STATCOLL9"""
|
|
menuitem "CLK2_STATCOLL3" "per , ""L3_MAIN_Interconnect,CLK2_STATCOLL3"""
|
|
menuitem "BB2D_FW" "per , ""L3_MAIN_Interconnect,BB2D_FW"""
|
|
menuitem "DEBUGSS_CT_TBR_FW" "per , ""L3_MAIN_Interconnect,DEBUGSS_CT_TBR_FW"""
|
|
menuitem "DSP1_SDMA_FW" "per , ""L3_MAIN_Interconnect,DSP1_SDMA_FW"""
|
|
menuitem "DSP2_SDMA_FW" "per , ""L3_MAIN_Interconnect,DSP2_SDMA_FW"""
|
|
menuitem "EDMA_TPCC_FW" "per , ""L3_MAIN_Interconnect,EDMA_TPCC_FW"""
|
|
menuitem "EVE1_FW" "per , ""L3_MAIN_Interconnect,EVE1_FW"""
|
|
menuitem "EVE2_FW" "per , ""L3_MAIN_Interconnect,EVE2_FW"""
|
|
menuitem "GPU_FW" "per , ""L3_MAIN_Interconnect,GPU_FW"""
|
|
menuitem "IVA_CONFIG_FW" "per , ""L3_MAIN_Interconnect,IVA_CONFIG_FW"""
|
|
menuitem "L3_INSTR_FW" "per , ""L3_MAIN_Interconnect,L3_INSTR_FW"""
|
|
menuitem "MCAN_FW" "per , ""L3_MAIN_Interconnect,MCAN_FW"""
|
|
menuitem "MCASP1_FW" "per , ""L3_MAIN_Interconnect,MCASP1_FW"""
|
|
menuitem "MCASP2_FW" "per , ""L3_MAIN_Interconnect,MCASP2_FW"""
|
|
menuitem "MCASP3_FW" "per , ""L3_MAIN_Interconnect,MCASP3_FW"""
|
|
menuitem "PRUSS1_FW" "per , ""L3_MAIN_Interconnect,PRUSS1_FW"""
|
|
menuitem "PRUSS2_FW" "per , ""L3_MAIN_Interconnect,PRUSS2_FW"""
|
|
menuitem "QSPI_FW" "per , ""L3_MAIN_Interconnect,QSPI_FW"""
|
|
menuitem "VCP1_FW" "per , ""L3_MAIN_Interconnect,VCP1_FW"""
|
|
menuitem "VCP2_FW" "per , ""L3_MAIN_Interconnect,VCP2_FW"""
|
|
menuitem "BB2D_TARG" "per , ""L3_MAIN_Interconnect,BB2D_TARG"""
|
|
menuitem "DEBUGSS_CT_TBR_TARG" "per , ""L3_MAIN_Interconnect,DEBUGSS_CT_TBR_TARG"""
|
|
menuitem "DMM_P1_TARG" "per , ""L3_MAIN_Interconnect,DMM_P1_TARG"""
|
|
menuitem "DMM_P2_TARG" "per , ""L3_MAIN_Interconnect,DMM_P2_TARG"""
|
|
menuitem "DSP1_SDMA_TARG" "per , ""L3_MAIN_Interconnect,DSP1_SDMA_TARG"""
|
|
menuitem "DSP2_SDMA_TARG" "per , ""L3_MAIN_Interconnect,DSP2_SDMA_TARG"""
|
|
menuitem "DSS_TARG" "per , ""L3_MAIN_Interconnect,DSS_TARG"""
|
|
menuitem "EVE1_TARG" "per , ""L3_MAIN_Interconnect,EVE1_TARG"""
|
|
menuitem "EVE2_TARG" "per , ""L3_MAIN_Interconnect,EVE2_TARG"""
|
|
menuitem "GPMC_TARG" "per , ""L3_MAIN_Interconnect,GPMC_TARG"""
|
|
menuitem "GPU_TARG" "per , ""L3_MAIN_Interconnect,GPU_TARG"""
|
|
menuitem "IPU1_TARG" "per , ""L3_MAIN_Interconnect,IPU1_TARG"""
|
|
menuitem "IPU2_TARG" "per , ""L3_MAIN_Interconnect,IPU2_TARG"""
|
|
menuitem "IVA_CONFIG_TARG" "per , ""L3_MAIN_Interconnect,IVA_CONFIG_TARG"""
|
|
menuitem "IVA_SL2IF_TARG" "per , ""L3_MAIN_Interconnect,IVA_SL2IF_TARG"""
|
|
menuitem "L3_INSTR" "per , ""L3_MAIN_Interconnect,L3_INSTR"""
|
|
menuitem "L4_CFG_TARG" "per , ""L3_MAIN_Interconnect,L4_CFG_TARG"""
|
|
menuitem "L4_PER1_P1_TARG" "per , ""L3_MAIN_Interconnect,L4_PER1_P1_TARG"""
|
|
menuitem "L4_PER1_P2_TARG" "per , ""L3_MAIN_Interconnect,L4_PER1_P2_TARG"""
|
|
menuitem "L4_PER1_P3_TARG" "per , ""L3_MAIN_Interconnect,L4_PER1_P3_TARG"""
|
|
menuitem "L4_PER2_P1_TARG" "per , ""L3_MAIN_Interconnect,L4_PER2_P1_TARG"""
|
|
menuitem "L4_PER2_P2_TARG" "per , ""L3_MAIN_Interconnect,L4_PER2_P2_TARG"""
|
|
menuitem "L4_PER2_P3_TARG" "per , ""L3_MAIN_Interconnect,L4_PER2_P3_TARG"""
|
|
menuitem "L4_PER3_P1_TARG" "per , ""L3_MAIN_Interconnect,L4_PER3_P1_TARG"""
|
|
menuitem "L4_PER3_P2_TARG" "per , ""L3_MAIN_Interconnect,L4_PER3_P2_TARG"""
|
|
menuitem "L4_PER3_P3_TARG" "per , ""L3_MAIN_Interconnect,L4_PER3_P3_TARG"""
|
|
menuitem "L4_WKUP_TARG" "per , ""L3_MAIN_Interconnect,L4_WKUP_TARG"""
|
|
menuitem "MCAN_TARG" "per , ""L3_MAIN_Interconnect,MCAN_TARG"""
|
|
menuitem "MCASP1_TARG" "per , ""L3_MAIN_Interconnect,MCASP1_TARG"""
|
|
menuitem "MCASP2_TARG" "per , ""L3_MAIN_Interconnect,MCASP2_TARG"""
|
|
menuitem "MCASP3_TARG" "per , ""L3_MAIN_Interconnect,MCASP3_TARG"""
|
|
menuitem "MMU1_TARG" "per , ""L3_MAIN_Interconnect,MMU1_TARG"""
|
|
menuitem "MMU2_TARG" "per , ""L3_MAIN_Interconnect,MMU2_TARG"""
|
|
menuitem "OCMC_RAM1_TARG" "per , ""L3_MAIN_Interconnect,OCMC_RAM1_TARG"""
|
|
menuitem "OCMC_RAM2_TARG" "per , ""L3_MAIN_Interconnect,OCMC_RAM2_TARG"""
|
|
menuitem "OCMC_RAM3_TARG" "per , ""L3_MAIN_Interconnect,OCMC_RAM3_TARG"""
|
|
menuitem "PCIE1_TARG" "per , ""L3_MAIN_Interconnect,PCIE1_TARG"""
|
|
menuitem "PCIE2_TARG" "per , ""L3_MAIN_Interconnect,PCIE2_TARG"""
|
|
menuitem "PRUSS1_TARG" "per , ""L3_MAIN_Interconnect,PRUSS1_TARG"""
|
|
menuitem "PRUSS2_TARG" "per , ""L3_MAIN_Interconnect,PRUSS2_TARG"""
|
|
menuitem "QSPI_TARG" "per , ""L3_MAIN_Interconnect,QSPI_TARG"""
|
|
menuitem "TPCC_TARG" "per , ""L3_MAIN_Interconnect,TPCC_TARG"""
|
|
menuitem "TPTC1_TARG" "per , ""L3_MAIN_Interconnect,TPTC1_TARG"""
|
|
menuitem "TPTC2_TARG" "per , ""L3_MAIN_Interconnect,TPTC2_TARG"""
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|
menuitem "VCP1_TARG" "per , ""L3_MAIN_Interconnect,VCP1_TARG"""
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|
menuitem "VCP2_TARG" "per , ""L3_MAIN_Interconnect,VCP2_TARG"""
|
|
menuitem "IPU1_FW" "per , ""L3_MAIN_Interconnect,IPU1_FW"""
|
|
menuitem "IPU2_FW" "per , ""L3_MAIN_Interconnect,IPU2_FW"""
|
|
menuitem "IVA_SL2IF_FW" "per , ""L3_MAIN_Interconnect,IVA_SL2IF_FW"""
|
|
menuitem "EMIF_OCP_FW" "per , ""L3_MAIN_Interconnect,EMIF_OCP_FW"""
|
|
menuitem "MA_MPU_NTTP_FW" "per , ""L3_MAIN_Interconnect,MA_MPU_NTTP_FW"""
|
|
menuitem "OCMC_RAM1_FW" "per , ""L3_MAIN_Interconnect,OCMC_RAM1_FW"""
|
|
menuitem "OCMC_RAM2_FW" "per , ""L3_MAIN_Interconnect,OCMC_RAM2_FW"""
|
|
menuitem "OCMC_RAM3_FW" "per , ""L3_MAIN_Interconnect,OCMC_RAM3_FW"""
|
|
menuitem "DSS_FW" "per , ""L3_MAIN_Interconnect,DSS_FW"""
|
|
menuitem "GPMC_FW" "per , ""L3_MAIN_Interconnect,GPMC_FW"""
|
|
menuitem "PCIE1_FW" "per , ""L3_MAIN_Interconnect,PCIE1_FW"""
|
|
menuitem "PCIESS2_FW" "per , ""L3_MAIN_Interconnect,PCIESS2_FW"""
|
|
menuitem "TPTC_FW" "per , ""L3_MAIN_Interconnect,TPTC_FW"""
|
|
)
|
|
popup "L4_Interconnects"
|
|
(
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menuitem "CFG_AP" "per , ""L4_Interconnects,CFG_AP"""
|
|
menuitem "CFG_LA" "per , ""L4_Interconnects,CFG_LA"""
|
|
menuitem "WKUP_LA" "per , ""L4_Interconnects,WKUP_LA"""
|
|
menuitem "MAILBOX_TARG" "per , ""L4_Interconnects,MAILBOX_TARG"""
|
|
menuitem "OCP_WP_NOC_TARG" "per , ""L4_Interconnects,OCP_WP_NOC_TARG"""
|
|
menuitem "SPINLOCK_TARG" "per , ""L4_Interconnects,SPINLOCK_TARG"""
|
|
menuitem "MCASP8_CFG_TARG" "per , ""L4_Interconnects,MCASP8_CFG_TARG"""
|
|
menuitem "OCMC_RAM3_TARG" "per , ""L4_Interconnects,OCMC_RAM3_TARG"""
|
|
menuitem "PER1_AP" "per , ""L4_Interconnects,PER1_AP"""
|
|
menuitem "CFG_IA_IP0" "per , ""L4_Interconnects,CFG_IA_IP0"""
|
|
menuitem "PER1_IA_IP0" "per , ""L4_Interconnects,PER1_IA_IP0"""
|
|
menuitem "PER1_IA_IP1" "per , ""L4_Interconnects,PER1_IA_IP1"""
|
|
menuitem "PER1_IA_IP2" "per , ""L4_Interconnects,PER1_IA_IP2"""
|
|
menuitem "PER2_IA_IP0" "per , ""L4_Interconnects,PER2_IA_IP0"""
|
|
menuitem "PER2_IA_IP1" "per , ""L4_Interconnects,PER2_IA_IP1"""
|
|
menuitem "PER2_IA_IP2" "per , ""L4_Interconnects,PER2_IA_IP2"""
|
|
menuitem "PER3_IA_IP0" "per , ""L4_Interconnects,PER3_IA_IP0"""
|
|
menuitem "PER3_IA_IP1" "per , ""L4_Interconnects,PER3_IA_IP1"""
|
|
menuitem "PER3_IA_IP2" "per , ""L4_Interconnects,PER3_IA_IP2"""
|
|
menuitem "WKUP_IA_IP0" "per , ""L4_Interconnects,WKUP_IA_IP0"""
|
|
menuitem "PER1_LA" "per , ""L4_Interconnects,PER1_LA"""
|
|
menuitem "PER2_LA" "per , ""L4_Interconnects,PER2_LA"""
|
|
menuitem "PER3_LA" "per , ""L4_Interconnects,PER3_LA"""
|
|
menuitem "PER2_AP" "per , ""L4_Interconnects,PER2_AP"""
|
|
menuitem "PER3_AP" "per , ""L4_Interconnects,PER3_AP"""
|
|
menuitem "ATL_TARG" "per , ""L4_Interconnects,ATL_TARG"""
|
|
menuitem "CAL_TARG" "per , ""L4_Interconnects,CAL_TARG"""
|
|
menuitem "CM_CORE_AON_TARG" "per , ""L4_Interconnects,CM_CORE_AON_TARG"""
|
|
menuitem "CM_CORE_TARG" "per , ""L4_Interconnects,CM_CORE_TARG"""
|
|
menuitem "COUNTER_32K_TARG" "per , ""L4_Interconnects,COUNTER_32K_TARG"""
|
|
menuitem "CTRL_MODULE_CORE_TARG" "per , ""L4_Interconnects,CTRL_MODULE_CORE_TARG"""
|
|
menuitem "CTRL_MODULE_WKUP_TARG" "per , ""L4_Interconnects,CTRL_MODULE_WKUP_TARG"""
|
|
menuitem "DCAN1_TARG" "per , ""L4_Interconnects,DCAN1_TARG"""
|
|
menuitem "DCAN2_TARG" "per , ""L4_Interconnects,DCAN2_TARG"""
|
|
menuitem "DEBUGSS_CT_TBR_FW_CFG_TARG" "per , ""L4_Interconnects,DEBUGSS_CT_TBR_FW_CFG_TARG"""
|
|
menuitem "DMA_SYSTEM_TARG" "per , ""L4_Interconnects,DMA_SYSTEM_TARG"""
|
|
menuitem "DSP1_SDMA_FW_CFG_TARG" "per , ""L4_Interconnects,DSP1_SDMA_FW_CFG_TARG"""
|
|
menuitem "DSP2_SDMA_FW_CFG_TARG" "per , ""L4_Interconnects,DSP2_SDMA_FW_CFG_TARG"""
|
|
menuitem "DSS_FW_CFG_TARG" "per , ""L4_Interconnects,DSS_FW_CFG_TARG"""
|
|
menuitem "ELM_TARG" "per , ""L4_Interconnects,ELM_TARG"""
|
|
menuitem "EMIF_OCP_FW_CFG_TARG" "per , ""L4_Interconnects,EMIF_OCP_FW_CFG_TARG"""
|
|
menuitem "EVE1_FW_CFG_TARG" "per , ""L4_Interconnects,EVE1_FW_CFG_TARG"""
|
|
menuitem "EVE2_FW_CFG_TARG" "per , ""L4_Interconnects,EVE2_FW_CFG_TARG"""
|
|
menuitem "GMAC_TARG" "per , ""L4_Interconnects,GMAC_TARG"""
|
|
menuitem "GPIO1_TARG" "per , ""L4_Interconnects,GPIO1_TARG"""
|
|
menuitem "GPIO2_TARG" "per , ""L4_Interconnects,GPIO2_TARG"""
|
|
menuitem "GPIO3_TARG" "per , ""L4_Interconnects,GPIO3_TARG"""
|
|
menuitem "GPIO4_TARG" "per , ""L4_Interconnects,GPIO4_TARG"""
|
|
menuitem "GPIO5_TARG" "per , ""L4_Interconnects,GPIO5_TARG"""
|
|
menuitem "GPIO6_TARG" "per , ""L4_Interconnects,GPIO6_TARG"""
|
|
menuitem "GPIO7_TARG" "per , ""L4_Interconnects,GPIO7_TARG"""
|
|
menuitem "GPIO8_TARG" "per , ""L4_Interconnects,GPIO8_TARG"""
|
|
menuitem "GPMC_FW_CFG_TARG" "per , ""L4_Interconnects,GPMC_FW_CFG_TARG"""
|
|
menuitem "GPU_FW_CFG_TARG" "per , ""L4_Interconnects,GPU_FW_CFG_TARG"""
|
|
menuitem "HDQ1W_TARG" "per , ""L4_Interconnects,HDQ1W_TARG"""
|
|
menuitem "I2C1_TARG" "per , ""L4_Interconnects,I2C1_TARG"""
|
|
menuitem "I2C2_TARG" "per , ""L4_Interconnects,I2C2_TARG"""
|
|
menuitem "I2C3_TARG" "per , ""L4_Interconnects,I2C3_TARG"""
|
|
menuitem "I2C4_TARG" "per , ""L4_Interconnects,I2C4_TARG"""
|
|
menuitem "I2C5_TARG" "per , ""L4_Interconnects,I2C5_TARG"""
|
|
menuitem "IPU1_FW_CFG_TARG" "per , ""L4_Interconnects,IPU1_FW_CFG_TARG"""
|
|
menuitem "IPU2_FW_CFG_TARG" "per , ""L4_Interconnects,IPU2_FW_CFG_TARG"""
|
|
menuitem "IVA_CONFIG_FW_CFG_TARG" "per , ""L4_Interconnects,IVA_CONFIG_FW_CFG_TARG"""
|
|
menuitem "IVA_SL2IF_FW_CFG_TARG" "per , ""L4_Interconnects,IVA_SL2IF_FW_CFG_TARG"""
|
|
menuitem "KBD_TARG" "per , ""L4_Interconnects,KBD_TARG"""
|
|
menuitem "L3_INSTR_FW_CFG_TARG" "per , ""L4_Interconnects,L3_INSTR_FW_CFG_TARG"""
|
|
menuitem "MA_MPU_NTTP_FW_CFG_TARG" "per , ""L4_Interconnects,MA_MPU_NTTP_FW_CFG_TARG"""
|
|
menuitem "MBX10_TARG" "per , ""L4_Interconnects,MBX10_TARG"""
|
|
menuitem "MBX11_TARG" "per , ""L4_Interconnects,MBX11_TARG"""
|
|
menuitem "MBX12_TARG" "per , ""L4_Interconnects,MBX12_TARG"""
|
|
menuitem "MBX13_TARG" "per , ""L4_Interconnects,MBX13_TARG"""
|
|
menuitem "MBX2_TARG" "per , ""L4_Interconnects,MBX2_TARG"""
|
|
menuitem "MBX3_TARG" "per , ""L4_Interconnects,MBX3_TARG"""
|
|
menuitem "MBX4_TARG" "per , ""L4_Interconnects,MBX4_TARG"""
|
|
menuitem "MBX5_TARG" "per , ""L4_Interconnects,MBX5_TARG"""
|
|
menuitem "MBX6_TARG" "per , ""L4_Interconnects,MBX6_TARG"""
|
|
menuitem "MBX7_TARG" "per , ""L4_Interconnects,MBX7_TARG"""
|
|
menuitem "MBX8_TARG" "per , ""L4_Interconnects,MBX8_TARG"""
|
|
menuitem "MBX9_TARG" "per , ""L4_Interconnects,MBX9_TARG"""
|
|
menuitem "MCAN_FW_CFG_TARG" "per , ""L4_Interconnects,MCAN_FW_CFG_TARG"""
|
|
menuitem "MCASP1_CFG_TARG" "per , ""L4_Interconnects,MCASP1_CFG_TARG"""
|
|
menuitem "MCASP1_FW_CFG_TARG" "per , ""L4_Interconnects,MCASP1_FW_CFG_TARG"""
|
|
menuitem "MCASP2_CFG_TARG" "per , ""L4_Interconnects,MCASP2_CFG_TARG"""
|
|
menuitem "MCASP2_FW_CFG_TARG" "per , ""L4_Interconnects,MCASP2_FW_CFG_TARG"""
|
|
menuitem "MCASP3_CFG_TARG" "per , ""L4_Interconnects,MCASP3_CFG_TARG"""
|
|
menuitem "MCASP3_FW_CFG_TARG" "per , ""L4_Interconnects,MCASP3_FW_CFG_TARG"""
|
|
menuitem "MCASP4_CFG_TARG" "per , ""L4_Interconnects,MCASP4_CFG_TARG"""
|
|
menuitem "MCASP4_DAT_TARG" "per , ""L4_Interconnects,MCASP4_DAT_TARG"""
|
|
menuitem "MCASP5_CFG_TARG" "per , ""L4_Interconnects,MCASP5_CFG_TARG"""
|
|
menuitem "MCASP5_DAT_TARG" "per , ""L4_Interconnects,MCASP5_DAT_TARG"""
|
|
menuitem "MCASP6_CFG_TARG" "per , ""L4_Interconnects,MCASP6_CFG_TARG"""
|
|
menuitem "MCASP6_DAT_TARG" "per , ""L4_Interconnects,MCASP6_DAT_TARG"""
|
|
menuitem "MCASP7_CFG_TARG" "per , ""L4_Interconnects,MCASP7_CFG_TARG"""
|
|
menuitem "MCASP7_DAT_TARG" "per , ""L4_Interconnects,MCASP7_DAT_TARG"""
|
|
menuitem "MCASP8_DAT_TARG" "per , ""L4_Interconnects,MCASP8_DAT_TARG"""
|
|
menuitem "MCSPI1_TARG" "per , ""L4_Interconnects,MCSPI1_TARG"""
|
|
menuitem "MCSPI2_TARG" "per , ""L4_Interconnects,MCSPI2_TARG"""
|
|
menuitem "MCSPI3_TARG" "per , ""L4_Interconnects,MCSPI3_TARG"""
|
|
menuitem "MCSPI4_TARG" "per , ""L4_Interconnects,MCSPI4_TARG"""
|
|
menuitem "MLB_TARG" "per , ""L4_Interconnects,MLB_TARG"""
|
|
menuitem "MMC1_TARG" "per , ""L4_Interconnects,MMC1_TARG"""
|
|
menuitem "MMC2_TARG" "per , ""L4_Interconnects,MMC2_TARG"""
|
|
menuitem "MMC3_TARG" "per , ""L4_Interconnects,MMC3_TARG"""
|
|
menuitem "MMC4_TARG" "per , ""L4_Interconnects,MMC4_TARG"""
|
|
menuitem "MMU1_TARG" "per , ""L4_Interconnects,MMU1_TARG"""
|
|
menuitem "MMU2_TARG" "per , ""L4_Interconnects,MMU2_TARG"""
|
|
menuitem "OCMC_RAM1_FW_CFG_TARG" "per , ""L4_Interconnects,OCMC_RAM1_FW_CFG_TARG"""
|
|
menuitem "OCMC_RAM1_TARG" "per , ""L4_Interconnects,OCMC_RAM1_TARG"""
|
|
menuitem "OCMC_RAM2_FW_CFG_TARG" "per , ""L4_Interconnects,OCMC_RAM2_FW_CFG_TARG"""
|
|
menuitem "OCMC_RAM2_TARG" "per , ""L4_Interconnects,OCMC_RAM2_TARG"""
|
|
menuitem "OCMC_RAM3_FW_CFG_TARG" "per , ""L4_Interconnects,OCMC_RAM3_FW_CFG_TARG"""
|
|
menuitem "PCIESS1_FW_CFG_TARG" "per , ""L4_Interconnects,PCIESS1_FW_CFG_TARG"""
|
|
menuitem "PCIESS2_FW_CFG_TARG" "per , ""L4_Interconnects,PCIESS2_FW_CFG_TARG"""
|
|
menuitem "PRM_TARG" "per , ""L4_Interconnects,PRM_TARG"""
|
|
menuitem "PRUSS1_FW_CFG_TARG" "per , ""L4_Interconnects,PRUSS1_FW_CFG_TARG"""
|
|
menuitem "PRUSS2_FW_CFG_TARG" "per , ""L4_Interconnects,PRUSS2_FW_CFG_TARG"""
|
|
menuitem "PWM1_TARG" "per , ""L4_Interconnects,PWM1_TARG"""
|
|
menuitem "PWM2_TARG" "per , ""L4_Interconnects,PWM2_TARG"""
|
|
menuitem "PWM3_TARG" "per , ""L4_Interconnects,PWM3_TARG"""
|
|
menuitem "QSPI_FW_CFG_TARG" "per , ""L4_Interconnects,QSPI_FW_CFG_TARG"""
|
|
menuitem "RTC_TARG" "per , ""L4_Interconnects,RTC_TARG"""
|
|
menuitem "SCP1_TARG" "per , ""L4_Interconnects,SCP1_TARG"""
|
|
menuitem "SCP2_TARG" "per , ""L4_Interconnects,SCP2_TARG"""
|
|
menuitem "SCP3_TARG" "per , ""L4_Interconnects,SCP3_TARG"""
|
|
menuitem "TIMER10_TARG" "per , ""L4_Interconnects,TIMER10_TARG"""
|
|
menuitem "TIMER11_TARG" "per , ""L4_Interconnects,TIMER11_TARG"""
|
|
menuitem "TIMER12_TARG" "per , ""L4_Interconnects,TIMER12_TARG"""
|
|
menuitem "TIMER13_TARG" "per , ""L4_Interconnects,TIMER13_TARG"""
|
|
menuitem "TIMER14_TARG" "per , ""L4_Interconnects,TIMER14_TARG"""
|
|
menuitem "TIMER15_TARG" "per , ""L4_Interconnects,TIMER15_TARG"""
|
|
menuitem "TIMER16_TARG" "per , ""L4_Interconnects,TIMER16_TARG"""
|
|
menuitem "TIMER1_TARG" "per , ""L4_Interconnects,TIMER1_TARG"""
|
|
menuitem "TIMER2_TARG" "per , ""L4_Interconnects,TIMER2_TARG"""
|
|
menuitem "TIMER3_TARG" "per , ""L4_Interconnects,TIMER3_TARG"""
|
|
menuitem "TIMER4_TARG" "per , ""L4_Interconnects,TIMER4_TARG"""
|
|
menuitem "TIMER5_TARG" "per , ""L4_Interconnects,TIMER5_TARG"""
|
|
menuitem "TIMER6_TARG" "per , ""L4_Interconnects,TIMER6_TARG"""
|
|
menuitem "TIMER7_TARG" "per , ""L4_Interconnects,TIMER7_TARG"""
|
|
menuitem "TIMER8_TARG" "per , ""L4_Interconnects,TIMER8_TARG"""
|
|
menuitem "TIMER9_TARG" "per , ""L4_Interconnects,TIMER9_TARG"""
|
|
menuitem "TPCC_FW_CFG_TARG" "per , ""L4_Interconnects,TPCC_FW_CFG_TARG"""
|
|
menuitem "TPTC_FW_CFG_TARG" "per , ""L4_Interconnects,TPTC_FW_CFG_TARG"""
|
|
menuitem "UART10_TARG" "per , ""L4_Interconnects,UART10_TARG"""
|
|
menuitem "UART1_TARG" "per , ""L4_Interconnects,UART1_TARG"""
|
|
menuitem "UART2_TARG" "per , ""L4_Interconnects,UART2_TARG"""
|
|
menuitem "UART3_TARG" "per , ""L4_Interconnects,UART3_TARG"""
|
|
menuitem "UART4_TARG" "per , ""L4_Interconnects,UART4_TARG"""
|
|
menuitem "UART5_TARG" "per , ""L4_Interconnects,UART5_TARG"""
|
|
menuitem "UART6_TARG" "per , ""L4_Interconnects,UART6_TARG"""
|
|
menuitem "UART7_TARG" "per , ""L4_Interconnects,UART7_TARG"""
|
|
menuitem "UART8_TARG" "per , ""L4_Interconnects,UART8_TARG"""
|
|
menuitem "UART9_TARG" "per , ""L4_Interconnects,UART9_TARG"""
|
|
menuitem "USB1_TARG" "per , ""L4_Interconnects,USB1_TARG"""
|
|
menuitem "USB2_TARG" "per , ""L4_Interconnects,USB2_TARG"""
|
|
menuitem "USB3_TARG" "per , ""L4_Interconnects,USB3_TARG"""
|
|
menuitem "USB4_TARG" "per , ""L4_Interconnects,USB4_TARG"""
|
|
menuitem "VCP1_CFG_TARG" "per , ""L4_Interconnects,VCP1_CFG_TARG"""
|
|
menuitem "VCP1_FW_CFG_TARG" "per , ""L4_Interconnects,VCP1_FW_CFG_TARG"""
|
|
menuitem "VCP2_CFG_TARG" "per , ""L4_Interconnects,VCP2_CFG_TARG"""
|
|
menuitem "VCP2_FW_CFG_TARG" "per , ""L4_Interconnects,VCP2_FW_CFG_TARG"""
|
|
menuitem "VIP1_TARG" "per , ""L4_Interconnects,VIP1_TARG"""
|
|
menuitem "VIP2_TARG" "per , ""L4_Interconnects,VIP2_TARG"""
|
|
menuitem "VPE_TARG" "per , ""L4_Interconnects,VPE_TARG"""
|
|
menuitem "WD_TIMER2_TARG" "per , ""L4_Interconnects,WD_TIMER2_TARG"""
|
|
menuitem "WKUP_AP" "per , ""L4_Interconnects,WKUP_AP"""
|
|
)
|
|
popup "MCAN"
|
|
(
|
|
menuitem "MCAN" "per , ""MCAN,MCAN"""
|
|
)
|
|
popup "MMU"
|
|
(
|
|
menuitem "System_MMU1" "per , ""MMU,System_MMU1"""
|
|
menuitem "System_MMU2" "per , ""MMU,System_MMU2"""
|
|
menuitem "DSP1_MMU0" "per , ""MMU,DSP1_MMU0"""
|
|
menuitem "DSP1_MMU1" "per , ""MMU,DSP1_MMU1"""
|
|
menuitem "IPU1_MMU" "per , ""MMU,IPU1_MMU"""
|
|
menuitem "IPU2_MMU" "per , ""MMU,IPU2_MMU"""
|
|
)
|
|
popup "Multichannel_Audio_Serial_Port"
|
|
(
|
|
menuitem "MCASP1_AFIFO" "per , ""Multichannel_Audio_Serial_Port,MCASP1_AFIFO"""
|
|
menuitem "MCASP2_AFIFO" "per , ""Multichannel_Audio_Serial_Port,MCASP2_AFIFO"""
|
|
menuitem "MCASP3_AFIFO" "per , ""Multichannel_Audio_Serial_Port,MCASP3_AFIFO"""
|
|
menuitem "MCASP4_AFIFO" "per , ""Multichannel_Audio_Serial_Port,MCASP4_AFIFO"""
|
|
menuitem "MCASP5_AFIFO" "per , ""Multichannel_Audio_Serial_Port,MCASP5_AFIFO"""
|
|
menuitem "MCASP6_AFIFO" "per , ""Multichannel_Audio_Serial_Port,MCASP6_AFIFO"""
|
|
menuitem "MCASP7_AFIFO" "per , ""Multichannel_Audio_Serial_Port,MCASP7_AFIFO"""
|
|
menuitem "MCASP8_AFIFO" "per , ""Multichannel_Audio_Serial_Port,MCASP8_AFIFO"""
|
|
menuitem "MCASP1_CFG" "per , ""Multichannel_Audio_Serial_Port,MCASP1_CFG"""
|
|
menuitem "MCASP2_CFG" "per , ""Multichannel_Audio_Serial_Port,MCASP2_CFG"""
|
|
menuitem "MCASP3_CFG" "per , ""Multichannel_Audio_Serial_Port,MCASP3_CFG"""
|
|
menuitem "MCASP4_CFG" "per , ""Multichannel_Audio_Serial_Port,MCASP4_CFG"""
|
|
menuitem "MCASP5_CFG" "per , ""Multichannel_Audio_Serial_Port,MCASP5_CFG"""
|
|
menuitem "MCASP6_CFG" "per , ""Multichannel_Audio_Serial_Port,MCASP6_CFG"""
|
|
menuitem "MCASP7_CFG" "per , ""Multichannel_Audio_Serial_Port,MCASP7_CFG"""
|
|
menuitem "MCASP8_CFG" "per , ""Multichannel_Audio_Serial_Port,MCASP8_CFG"""
|
|
menuitem "MCASP1_DAT" "per , ""Multichannel_Audio_Serial_Port,MCASP1_DAT"""
|
|
menuitem "MCASP2_DAT" "per , ""Multichannel_Audio_Serial_Port,MCASP2_DAT"""
|
|
menuitem "MCASP3_DAT" "per , ""Multichannel_Audio_Serial_Port,MCASP3_DAT"""
|
|
menuitem "MCASP4_DAT" "per , ""Multichannel_Audio_Serial_Port,MCASP4_DAT"""
|
|
menuitem "MCASP5_DAT" "per , ""Multichannel_Audio_Serial_Port,MCASP5_DAT"""
|
|
menuitem "MCASP6_DAT" "per , ""Multichannel_Audio_Serial_Port,MCASP6_DAT"""
|
|
menuitem "MCASP7_DAT" "per , ""Multichannel_Audio_Serial_Port,MCASP7_DAT"""
|
|
menuitem "MCASP8_DAT" "per , ""Multichannel_Audio_Serial_Port,MCASP8_DAT"""
|
|
)
|
|
popup "Multichannel_Serial_Peripheral_Interface"
|
|
(
|
|
menuitem "McSPI1" "per , ""Multichannel_Serial_Peripheral_Interface,McSPI1"""
|
|
menuitem "McSPI2" "per , ""Multichannel_Serial_Peripheral_Interface,McSPI2"""
|
|
menuitem "McSPI3" "per , ""Multichannel_Serial_Peripheral_Interface,McSPI3"""
|
|
menuitem "McSPI4" "per , ""Multichannel_Serial_Peripheral_Interface,McSPI4"""
|
|
)
|
|
popup "Multimaster_High_Speed_I2C_Controller"
|
|
(
|
|
menuitem "I2C1" "per , ""Multimaster_High_Speed_I2C_Controller,I2C1"""
|
|
menuitem "I2C2" "per , ""Multimaster_High_Speed_I2C_Controller,I2C2"""
|
|
menuitem "I2C3" "per , ""Multimaster_High_Speed_I2C_Controller,I2C3"""
|
|
menuitem "I2C4" "per , ""Multimaster_High_Speed_I2C_Controller,I2C4"""
|
|
menuitem "I2C5" "per , ""Multimaster_High_Speed_I2C_Controller,I2C5"""
|
|
)
|
|
popup "On_Chip_Memory__OCM__Subsystem"
|
|
(
|
|
menuitem "OCMC_RAM1" "per , ""On_Chip_Memory__OCM__Subsystem,OCMC_RAM1"""
|
|
menuitem "OCMC_RAM2" "per , ""On_Chip_Memory__OCM__Subsystem,OCMC_RAM2"""
|
|
menuitem "OCMC_RAM3" "per , ""On_Chip_Memory__OCM__Subsystem,OCMC_RAM3"""
|
|
)
|
|
popup "PCIe_Controller"
|
|
(
|
|
menuitem "PCIe_SS1_EP_CFG_DBICS" "per , ""PCIe_Controller,PCIe_SS1_EP_CFG_DBICS"""
|
|
menuitem "PCIe_SS2_EP_CFG_DBICS" "per , ""PCIe_Controller,PCIe_SS2_EP_CFG_DBICS"""
|
|
menuitem "PCIe_SS1_EP_CFG_DBICS2" "per , ""PCIe_Controller,PCIe_SS1_EP_CFG_DBICS2"""
|
|
menuitem "PCIe_SS2_EP_CFG_DBICS2" "per , ""PCIe_Controller,PCIe_SS2_EP_CFG_DBICS2"""
|
|
menuitem "PCIe_SS1_EP_CFG_PCIe" "per , ""PCIe_Controller,PCIe_SS1_EP_CFG_PCIe"""
|
|
menuitem "PCIe_SS2_EP_CFG_PCIe" "per , ""PCIe_Controller,PCIe_SS2_EP_CFG_PCIe"""
|
|
menuitem "PCIe_SS1_PL_CONF" "per , ""PCIe_Controller,PCIe_SS1_PL_CONF"""
|
|
menuitem "PCIe_SS2_PL_CONF" "per , ""PCIe_Controller,PCIe_SS2_PL_CONF"""
|
|
menuitem "PCIe_SS1_RC_CFG_DBICS" "per , ""PCIe_Controller,PCIe_SS1_RC_CFG_DBICS"""
|
|
menuitem "PCIe_SS2_RC_CFG_DBICS" "per , ""PCIe_Controller,PCIe_SS2_RC_CFG_DBICS"""
|
|
menuitem "PCIe_SS1_RC_CFG_DBICS2" "per , ""PCIe_Controller,PCIe_SS1_RC_CFG_DBICS2"""
|
|
menuitem "PCIe_SS2_RC_CFG_DBICS2" "per , ""PCIe_Controller,PCIe_SS2_RC_CFG_DBICS2"""
|
|
menuitem "PCIe_SS1_TI_CONF" "per , ""PCIe_Controller,PCIe_SS1_TI_CONF"""
|
|
menuitem "PCIe_SS2_TI_CONF" "per , ""PCIe_Controller,PCIe_SS2_TI_CONF"""
|
|
)
|
|
popup "PCIe_PHY_Subsystem"
|
|
(
|
|
menuitem "OCP2SCP1" "per , ""PCIe_PHY_Subsystem,OCP2SCP1"""
|
|
menuitem "OCP2SCP3" "per , ""PCIe_PHY_Subsystem,OCP2SCP3"""
|
|
menuitem "PCIe1_PHY_RX" "per , ""PCIe_PHY_Subsystem,PCIe1_PHY_RX"""
|
|
menuitem "PCIe2_PHY_RX" "per , ""PCIe_PHY_Subsystem,PCIe2_PHY_RX"""
|
|
menuitem "PCIe1_PHY_TX" "per , ""PCIe_PHY_Subsystem,PCIe1_PHY_TX"""
|
|
menuitem "PCIe2_PHY_TX" "per , ""PCIe_PHY_Subsystem,PCIe2_PHY_TX"""
|
|
)
|
|
popup "PRCM"
|
|
(
|
|
menuitem "CAM_PRM" "per , ""PRCM,CAM_PRM"""
|
|
menuitem "CKGEN_PRM" "per , ""PRCM,CKGEN_PRM"""
|
|
menuitem "CM_CORE__CAM" "per , ""PRCM,CM_CORE__CAM"""
|
|
menuitem "CM_CORE__CKGEN" "per , ""PRCM,CM_CORE__CKGEN"""
|
|
menuitem "CM_CORE__CORE" "per , ""PRCM,CM_CORE__CORE"""
|
|
menuitem "CM_CORE__COREAON" "per , ""PRCM,CM_CORE__COREAON"""
|
|
menuitem "CM_CORE__CUSTEFUSE" "per , ""PRCM,CM_CORE__CUSTEFUSE"""
|
|
menuitem "CM_CORE__DSS" "per , ""PRCM,CM_CORE__DSS"""
|
|
menuitem "CM_CORE__GPU" "per , ""PRCM,CM_CORE__GPU"""
|
|
menuitem "CM_CORE__IVA" "per , ""PRCM,CM_CORE__IVA"""
|
|
menuitem "CM_CORE__L3INIT" "per , ""PRCM,CM_CORE__L3INIT"""
|
|
menuitem "CM_CORE__L4PER" "per , ""PRCM,CM_CORE__L4PER"""
|
|
menuitem "CM_CORE__OCP_SOCKET" "per , ""PRCM,CM_CORE__OCP_SOCKET"""
|
|
menuitem "CM_CORE__RESTORE" "per , ""PRCM,CM_CORE__RESTORE"""
|
|
menuitem "CM_CORE_AON__CKGEN" "per , ""PRCM,CM_CORE_AON__CKGEN"""
|
|
menuitem "CM_CORE_AON__DSP1" "per , ""PRCM,CM_CORE_AON__DSP1"""
|
|
menuitem "CM_CORE_AON__DSP2" "per , ""PRCM,CM_CORE_AON__DSP2"""
|
|
menuitem "CM_CORE_AON__EVE1" "per , ""PRCM,CM_CORE_AON__EVE1"""
|
|
menuitem "CM_CORE_AON__EVE2" "per , ""PRCM,CM_CORE_AON__EVE2"""
|
|
menuitem "CM_CORE_AON__EVE3" "per , ""PRCM,CM_CORE_AON__EVE3"""
|
|
menuitem "CM_CORE_AON__EVE4" "per , ""PRCM,CM_CORE_AON__EVE4"""
|
|
menuitem "CM_CORE_AON__INSTR" "per , ""PRCM,CM_CORE_AON__INSTR"""
|
|
menuitem "CM_CORE_AON__IPU" "per , ""PRCM,CM_CORE_AON__IPU"""
|
|
menuitem "CM_CORE_AON__MPU" "per , ""PRCM,CM_CORE_AON__MPU"""
|
|
menuitem "CM_CORE_AON__OCP_SOCKET" "per , ""PRCM,CM_CORE_AON__OCP_SOCKET"""
|
|
menuitem "CM_CORE_AON__RESTORE" "per , ""PRCM,CM_CORE_AON__RESTORE"""
|
|
menuitem "CM_CORE_AON__RTC" "per , ""PRCM,CM_CORE_AON__RTC"""
|
|
menuitem "CM_CORE_AON__VPE" "per , ""PRCM,CM_CORE_AON__VPE"""
|
|
menuitem "CORE_PRM" "per , ""PRCM,CORE_PRM"""
|
|
menuitem "CUSTEFUSE_PRM" "per , ""PRCM,CUSTEFUSE_PRM"""
|
|
menuitem "DEVICE_PRM" "per , ""PRCM,DEVICE_PRM"""
|
|
menuitem "DSP1_PRM" "per , ""PRCM,DSP1_PRM"""
|
|
menuitem "DSP2_PRM" "per , ""PRCM,DSP2_PRM"""
|
|
menuitem "DSS_PRM" "per , ""PRCM,DSS_PRM"""
|
|
menuitem "EMU_CM" "per , ""PRCM,EMU_CM"""
|
|
menuitem "EVE1_PRM" "per , ""PRCM,EVE1_PRM"""
|
|
menuitem "EVE2_PRM" "per , ""PRCM,EVE2_PRM"""
|
|
menuitem "EVE3_PRM" "per , ""PRCM,EVE3_PRM"""
|
|
menuitem "EVE4_PRM" "per , ""PRCM,EVE4_PRM"""
|
|
menuitem "GPU_PRM" "per , ""PRCM,GPU_PRM"""
|
|
menuitem "INSTR_PRM" "per , ""PRCM,INSTR_PRM"""
|
|
menuitem "IPU_PRM" "per , ""PRCM,IPU_PRM"""
|
|
menuitem "IVA_PRM" "per , ""PRCM,IVA_PRM"""
|
|
menuitem "L3INIT_PRM" "per , ""PRCM,L3INIT_PRM"""
|
|
menuitem "L4PER_PRM" "per , ""PRCM,L4PER_PRM"""
|
|
menuitem "MPU_PRM" "per , ""PRCM,MPU_PRM"""
|
|
menuitem "OCP_SOCKET_PRM" "per , ""PRCM,OCP_SOCKET_PRM"""
|
|
menuitem "RTC_PRM" "per , ""PRCM,RTC_PRM"""
|
|
menuitem "VPE_PRM" "per , ""PRCM,VPE_PRM"""
|
|
menuitem "WKUPAON_CM" "per , ""PRCM,WKUPAON_CM"""
|
|
menuitem "WKUPAON_PRM" "per , ""PRCM,WKUPAON_PRM"""
|
|
)
|
|
popup "PWM_Subsystem_Resources"
|
|
(
|
|
menuitem "PWMSS1_CFG" "per , ""PWM_Subsystem_Resources,PWMSS1_CFG"""
|
|
menuitem "PWMSS2_CFG" "per , ""PWM_Subsystem_Resources,PWMSS2_CFG"""
|
|
menuitem "PWMSS3_CFG" "per , ""PWM_Subsystem_Resources,PWMSS3_CFG"""
|
|
menuitem "PWMSS1_ECAP" "per , ""PWM_Subsystem_Resources,PWMSS1_ECAP"""
|
|
menuitem "PWMSS2_ECAP" "per , ""PWM_Subsystem_Resources,PWMSS2_ECAP"""
|
|
menuitem "PWMSS3_ECAP" "per , ""PWM_Subsystem_Resources,PWMSS3_ECAP"""
|
|
menuitem "PWMSS1_EPWM" "per , ""PWM_Subsystem_Resources,PWMSS1_EPWM"""
|
|
menuitem "PWMSS2_EPWM" "per , ""PWM_Subsystem_Resources,PWMSS2_EPWM"""
|
|
menuitem "PWMSS3_EPWM" "per , ""PWM_Subsystem_Resources,PWMSS3_EPWM"""
|
|
menuitem "PWMSS1_EQEP" "per , ""PWM_Subsystem_Resources,PWMSS1_EQEP"""
|
|
menuitem "PWMSS2_EQEP" "per , ""PWM_Subsystem_Resources,PWMSS2_EQEP"""
|
|
menuitem "PWMSS3_EQEP" "per , ""PWM_Subsystem_Resources,PWMSS3_EQEP"""
|
|
)
|
|
popup "Quad_Serial_Peripheral_Interface"
|
|
(
|
|
menuitem "QSPI" "per , ""Quad_Serial_Peripheral_Interface,QSPI"""
|
|
)
|
|
popup "SATA_Controller"
|
|
(
|
|
menuitem "DWC_ahsata" "per , ""SATA_Controller,DWC_ahsata"""
|
|
menuitem "SATAMAC_wrapper" "per , ""SATA_Controller,SATAMAC_wrapper"""
|
|
)
|
|
popup "Spinlock"
|
|
(
|
|
menuitem "Spinlock" "per , ""Spinlock,Spinlock"""
|
|
)
|
|
popup "System_DMA"
|
|
(
|
|
menuitem "DMA_SYSTEM" "per , ""System_DMA,DMA_SYSTEM"""
|
|
)
|
|
popup "UART_IrDA_CIR"
|
|
(
|
|
menuitem "UART1" "per , ""UART_IrDA_CIR,UART1"""
|
|
menuitem "UART10" "per , ""UART_IrDA_CIR,UART10"""
|
|
menuitem "UART2" "per , ""UART_IrDA_CIR,UART2"""
|
|
menuitem "UART3" "per , ""UART_IrDA_CIR,UART3"""
|
|
menuitem "UART4" "per , ""UART_IrDA_CIR,UART4"""
|
|
menuitem "UART5" "per , ""UART_IrDA_CIR,UART5"""
|
|
menuitem "UART6" "per , ""UART_IrDA_CIR,UART6"""
|
|
menuitem "UART7" "per , ""UART_IrDA_CIR,UART7"""
|
|
menuitem "UART8" "per , ""UART_IrDA_CIR,UART8"""
|
|
menuitem "UART9" "per , ""UART_IrDA_CIR,UART9"""
|
|
)
|
|
popup "USB3_PHY_and_SATA_PHY"
|
|
(
|
|
menuitem "DPLLCTRL_SATA" "per , ""USB3_PHY_and_SATA_PHY,DPLLCTRL_SATA"""
|
|
menuitem "DPLLCTRL_USB_OTG_SS" "per , ""USB3_PHY_and_SATA_PHY,DPLLCTRL_USB_OTG_SS"""
|
|
menuitem "USB3_PHY_RX" "per , ""USB3_PHY_and_SATA_PHY,USB3_PHY_RX"""
|
|
menuitem "USB3_PHY_TX" "per , ""USB3_PHY_and_SATA_PHY,USB3_PHY_TX"""
|
|
)
|
|
popup "VIP"
|
|
(
|
|
menuitem "VIP1_Slice0_csc" "per , ""VIP,VIP1_Slice0_csc"""
|
|
menuitem "VIP1_Slice1_csc" "per , ""VIP,VIP1_Slice1_csc"""
|
|
menuitem "VIP2_Slice0_csc" "per , ""VIP,VIP2_Slice0_csc"""
|
|
menuitem "VIP2_Slice1_csc" "per , ""VIP,VIP2_Slice1_csc"""
|
|
menuitem "VIP1_Slice0_parser" "per , ""VIP,VIP1_Slice0_parser"""
|
|
menuitem "VIP1_Slice1_parser" "per , ""VIP,VIP1_Slice1_parser"""
|
|
menuitem "VIP2_Slice0_parser" "per , ""VIP,VIP2_Slice0_parser"""
|
|
menuitem "VIP2_Slice1_parser" "per , ""VIP,VIP2_Slice1_parser"""
|
|
menuitem "VIP1_Slice0_sc" "per , ""VIP,VIP1_Slice0_sc"""
|
|
menuitem "VIP1_Slice1_sc" "per , ""VIP,VIP1_Slice1_sc"""
|
|
menuitem "VIP2_Slice0_sc" "per , ""VIP,VIP2_Slice0_sc"""
|
|
menuitem "VIP2_Slice1_sc" "per , ""VIP,VIP2_Slice1_sc"""
|
|
menuitem "VIP1_top_level" "per , ""VIP,VIP1_top_level"""
|
|
menuitem "VIP2_top_level" "per , ""VIP,VIP2_top_level"""
|
|
menuitem "VIP1_VPDMA" "per , ""VIP,VIP1_VPDMA"""
|
|
menuitem "VIP2_VPDMA" "per , ""VIP,VIP2_VPDMA"""
|
|
)
|
|
popup "VPE"
|
|
(
|
|
menuitem "VPE_CHR_US_INST_0" "per , ""VPE,VPE_CHR_US_INST_0"""
|
|
menuitem "VPE_CHR_US_INST_1" "per , ""VPE,VPE_CHR_US_INST_1"""
|
|
menuitem "VPE_CHR_US_INST_2" "per , ""VPE,VPE_CHR_US_INST_2"""
|
|
menuitem "VPE_CSC" "per , ""VPE,VPE_CSC"""
|
|
menuitem "VPE_DEI" "per , ""VPE,VPE_DEI"""
|
|
menuitem "VPE_SC" "per , ""VPE,VPE_SC"""
|
|
menuitem "VPE_TOP_LEVEL" "per , ""VPE,VPE_TOP_LEVEL"""
|
|
menuitem "VPE_VPDMA" "per , ""VPE,VPE_VPDMA"""
|
|
)
|
|
popup "Watchdog_Timer"
|
|
(
|
|
menuitem "WD_TIMER2" "per , ""Watchdog_Timer,WD_TIMER2"""
|
|
)
|
|
)
|
|
)
|
|
else
|
|
(
|
|
popup "AM576x-ICSS"
|
|
(
|
|
popup "PRU_ICSS"
|
|
(
|
|
menuitem "PRUSS1_CFG" "per , ""PRU_ICSS,PRUSS1_CFG"""
|
|
menuitem "PRUSS2_CFG" "per , ""PRU_ICSS,PRUSS2_CFG"""
|
|
menuitem "PRUSS1_ECAP" "per , ""PRU_ICSS,PRUSS1_ECAP"""
|
|
menuitem "PRUSS2_ECAP" "per , ""PRU_ICSS,PRUSS2_ECAP"""
|
|
menuitem "PRUSS1_IEP" "per , ""PRU_ICSS,PRUSS1_IEP"""
|
|
menuitem "PRUSS2_IEP" "per , ""PRU_ICSS,PRUSS2_IEP"""
|
|
menuitem "PRUSS1_INTC" "per , ""PRU_ICSS,PRUSS1_INTC"""
|
|
menuitem "PRUSS2_INTC" "per , ""PRU_ICSS,PRUSS2_INTC"""
|
|
menuitem "PRUSS1_MII_MDIO" "per , ""PRU_ICSS,PRUSS1_MII_MDIO"""
|
|
menuitem "PRUSS2_MII_MDIO" "per , ""PRU_ICSS,PRUSS2_MII_MDIO"""
|
|
menuitem "PRUSS1_MII_RT" "per , ""PRU_ICSS,PRUSS1_MII_RT"""
|
|
menuitem "PRUSS2_MII_RT" "per , ""PRU_ICSS,PRUSS2_MII_RT"""
|
|
menuitem "PRUSS1_PRU0_CTRL" "per , ""PRU_ICSS,PRUSS1_PRU0_CTRL"""
|
|
menuitem "PRUSS1_PRU1_CTRL" "per , ""PRU_ICSS,PRUSS1_PRU1_CTRL"""
|
|
menuitem "PRUSS2_PRU0_CTRL" "per , ""PRU_ICSS,PRUSS2_PRU0_CTRL"""
|
|
menuitem "PRUSS2_PRU1_CTRL" "per , ""PRU_ICSS,PRUSS2_PRU1_CTRL"""
|
|
menuitem "PRUSS1_PRU0_DEBUG" "per , ""PRU_ICSS,PRUSS1_PRU0_DEBUG"""
|
|
menuitem "PRUSS1_PRU1_DEBUG" "per , ""PRU_ICSS,PRUSS1_PRU1_DEBUG"""
|
|
menuitem "PRUSS2_PRU0_DEBUG" "per , ""PRU_ICSS,PRUSS2_PRU0_DEBUG"""
|
|
menuitem "PRUSS2_PRU1_DEBUG" "per , ""PRU_ICSS,PRUSS2_PRU1_DEBUG"""
|
|
menuitem "PRUSS1_UART" "per , ""PRU_ICSS,PRUSS1_UART"""
|
|
menuitem "PRUSS2_UART" "per , ""PRU_ICSS,PRUSS2_UART"""
|
|
)
|
|
)
|
|
)
|
|
)
|