332 lines
9.5 KiB
Plaintext
332 lines
9.5 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: AM43xx Specific Menu
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; @Props: Released
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; @Author: AMM
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; @Changelog:
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; 2011-12-14
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; 2013-05-14
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; 2018-10-16 STR
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; @Manufacturer: TI - Texas Instruments
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; @Core: Cortex-A9, PRU
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; @Chip: AM43xx
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; @Copyright: (C) 1989-2018 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: menam43xx.men 16339 2023-07-03 13:30:14Z pegold $
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add
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menu
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(
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if (CPUFAMILY()=="ARM")
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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popup "[:chip]Core Registers (Cortex-A9MPCore)"
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(
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menuitem "[:chip]ID Registers" "per , ""Core Registers (Cortex-A9MPCore),ID Registers"""
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menuitem "[:chip]System Control and Configuration" "per , ""Core Registers (Cortex-A9MPCore),System Control and Configuration"""
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menuitem "[:chip]Memory Management Unit" "per , ""Core Registers (Cortex-A9MPCore),Memory Management Unit"""
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menuitem "[:chip]Cache Control and Configuration" "per , ""Core Registers (Cortex-A9MPCore),Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor" "per , ""Core Registers (Cortex-A9MPCore),System Performance Monitor"""
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menuitem "[:chip]Preload Engine" "per , ""Core Registers (Cortex-A9MPCore),Preload Engine"""
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menuitem "[:chip]NEON" "per , ""Core Registers (Cortex-A9MPCore),NEON"""
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separator
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menuitem "[:chip]Debug Registers" "per , ""Core Registers (Cortex-A9MPCore),Debug Registers"""
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menuitem "[:chip]Breakpoint Registers" "per , ""Core Registers (Cortex-A9MPCore),Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Control Registers" "per , ""Core Registers (Cortex-A9MPCore),Watchpoint Control Registers"""
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separator
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menuitem "[:chip]Snoop Control Unit (SCU)" "per , ""Core Registers (Cortex-A9MPCore),Snoop Control Unit (SCU)"""
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menuitem "[:chip]Timer and Watchdog Blocks" "per , ""Core Registers (Cortex-A9MPCore),Timer and Watchdog Blocks"""
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menuitem "[:chip]Interrupt Controller (PL-390)" "per , ""Core Registers (Cortex-A9MPCore),Interrupt Controller (PL-390)"""
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)
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separator
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menuitem "PRCM" "PER , ""Power, Reset, and Clock Management"""
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menuitem "CM" "PER , ""Control Module"""
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menuitem "MS" "PER , ""MEMORY SUBSYSTEM"""
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menuitem "EDMA" "PER , ""Enhanced Direct Memory Access"""
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menuitem "ADC0" "PER , ""Touchscreen Controller"""
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menuitem "ADC1" "PER , ""Magnetic Card Reader"""
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menuitem "DSS" "PER , ""Display Subsystem"""
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menuitem "VPFE" "PER , ""Camera"""
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menuitem "ES" "PER , ""Ethernet Subsystem Registers"""
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menuitem "MMC" "PER , ""Multimedia Card"""
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menuitem "IC" "PER , ""Interprocessor Communication"""
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menuitem "TIMERS" "PER , ""TIMERS"""
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menuitem "PWMSS" "PER , ""Pulse-Width Modulation Subsystem"""
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menuitem "UART" "PER , ""Universal Asynchronous Receiver/Transmitter"""
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menuitem "I2C" "PER , ""I2C"""
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menuitem "HDQ/1-Wire Interface" "PER , ""HDQ/1-Wire Interface"""
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menuitem "McASP" "PER , ""Multichannel Audio Serial Port"""
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menuitem "CAN" "PER , ""Controller Area Network"""
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menuitem "MCSPI" "PER , ""Multichannel Serial Port Interface"""
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menuitem "QSPI" "PER , ""QSPI"""
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menuitem "GPIO" "PER , ""General-Purpose Input/Output"""
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menuitem "Debug Subsystem" "PER , ""Debug Subsystem"""
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)
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)
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else
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(
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popup "AM43xx-ICSS"
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(
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popup "ICSS_0"
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(
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menuitem "CFG" "PER , ""ICSS_0,CFG"""
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menuitem "PRU0_CTRL" "PER , ""ICSS_0,PRU0_CTRL"""
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menuitem "PRU1_CTRL" "PER , ""ICSS_0,PRU1_CTRL"""
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menuitem "INTC" "PER , ""ICSS_0,INTC"""
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menuitem "MII_RT" "PER , ""ICSS_0,MII_RT"""
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menuitem "MII_MDIO" "PER , ""ICSS_0,MII_MDIO"""
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menuitem "IEP" "PER , ""ICSS_0,IEP"""
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menuitem "PRU0_DEBUG" "PER , ""ICSS_0,PRU0_DEBUG"""
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menuitem "PRU1_DEBUG" "PER , ""ICSS_0,PRU1_DEBUG"""
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)
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popup "ICSS_1"
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(
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menuitem "CFG" "PER , ""ICSS_1,CFG"""
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menuitem "PRU0_CTRL" "PER , ""ICSS_1,PRU0_CTRL"""
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menuitem "PRU1_CTRL" "PER , ""ICSS_1,PRU1_CTRL"""
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menuitem "INTC" "PER , ""ICSS_1,INTC"""
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menuitem "MII_RT" "PER , ""ICSS_1,MII_RT"""
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menuitem "MII_MDIO" "PER , ""ICSS_1,MII_MDIO"""
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menuitem "IEP" "PER , ""ICSS_1,IEP"""
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menuitem "PRU0_DEBUG" "PER , ""ICSS_1,PRU0_DEBUG"""
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menuitem "PRU1_DEBUG" "PER , ""ICSS_1,PRU1_DEBUG"""
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)
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)
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)
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)
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