553 lines
26 KiB
Plaintext
553 lines
26 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: OMAP3517/OMAP3505 Specific Menu
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; @Props: Released
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; @Author: ADI, FIL
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; @Changelog: 2009-10-26
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; @Manufacturer: TI - Texas Instruments
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; @Core: Cortex-A8
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; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: menam3517.men 16340 2023-07-03 14:25:09Z pegold $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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popup "[:chip]Core Registers (Cortex-A8)"
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(
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menuitem "[:chip]ID Registers" "per , ""Core Registers (Cortex-A8),ID Registers"""
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menuitem "[:chip]System Control and Configuration" "per , ""Core Registers (Cortex-A8),System Control and Configuration"""
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menuitem "[:chip]Memory Management Unit" "per , ""Core Registers (Cortex-A8),Memory Management Unit"""
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menuitem "[:chip]Cache Control and Configuration" "per , ""Core Registers (Cortex-A8),Cache Control and Configuration"""
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menuitem "[:chip]L2 Cache Control and Configuration" "per , ""Core Registers (Cortex-A8),L2 Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor" "per , ""Core Registers (Cortex-A8),System Performance Monitor"""
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menuitem "[:chip]Debug Registers" "per , ""Core Registers (Cortex-A8),Debug Registers"""
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menuitem "[:chip]Breakpoint Registers" "per , ""Core Registers (Cortex-A8),Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Control Registers" "per , ""Core Registers (Cortex-A8),Watchpoint Control Registers"""
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)
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separator
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popup "PRCM"
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(
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menuitem "Clock Management" "per , ""PRCM (Power Reset and Clock Management),Clock Management"""
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menuitem "Power Reset Management" "per , ""PRCM (Power Reset and Clock Management),Power Reset Management"""
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)
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popup "L3 Interconnect"
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(
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popup "IA"
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(
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menuitem "IA_MPUSS" "per , ""L3 Interconnect,IA (Initiator Agent Registers),IA_MPUSS"""
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menuitem "IA_SGX" "per , ""L3 Interconnect,IA (Initiator Agent Registers),IA_SGX"""
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menuitem "IA_USB_HS_Host" "per , ""L3 Interconnect,IA (Initiator Agent Registers),IA_USB_HS_Host"""
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menuitem "IA_IPSS" "per , ""L3 Interconnect,IA (Initiator Agent Registers),IA_IPSS"""
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menuitem "IA_sDMA_RD" "per , ""L3 Interconnect,IA (Initiator Agent Registers),IA_sDMA_RD"""
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menuitem "IA_sDMA_WR" "per , ""L3 Interconnect,IA (Initiator Agent Registers),IA_sDMA_WR"""
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menuitem "IA_DSS" "per , ""L3 Interconnect,IA (Initiator Agent Registers),IA_DSS"""
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menuitem "IA_DAP" "per , ""L3 Interconnect,IA (Initiator Agent Registers),IA_DAP"""
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)
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popup "TA"
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(
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menuitem "TA_SMS" "per , ""L3 Interconnect,TA (Target Agent Registers),TA_SMS"""
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menuitem "TA_GPMC" "per , ""L3 Interconnect,TA (Target Agent Registers),TA_GPMC"""
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menuitem "TA_OCM_RAM" "per , ""L3 Interconnect,TA (Target Agent Registers),TA_OCM_RAM"""
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menuitem "TA_OCM_ROM" "per , ""L3 Interconnect,TA (Target Agent Registers),TA_OCM_ROM"""
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menuitem "TA_IPSS" "per , ""L3 Interconnect,TA (Target Agent Registers),TA_IPSS"""
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menuitem "TA_SGX" "per , ""L3 Interconnect,TA (Target Agent Registers),TA_SGX"""
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menuitem "TA_L4_CORE" "per , ""L3 Interconnect,TA (Target Agent Registers),TA_L4_CORE"""
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menuitem "TA_L4_PER" "per , ""L3 Interconnect,TA (Target Agent Registers),TA_L4_PER"""
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menuitem "TA_L4_EMU" "per , ""L3 Interconnect,TA (Target Agent Registers),TA_L4_EMU"""
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)
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menuitem "RT" "per , ""L3 Interconnect,RT (Register Target Registers)"""
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popup "PM"
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(
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menuitem "PM_RT" "per , ""L3 Interconnect,PM (Protection Mechanism Common Registers),PM_RT"""
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menuitem "PM_GPMC" "per , ""L3 Interconnect,PM (Protection Mechanism Common Registers),PM_GPMC"""
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menuitem "PM_OCM_RAM" "per , ""L3 Interconnect,PM (Protection Mechanism Common Registers),PM_OCM_RAM"""
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menuitem "PM_OCM_ROM" "per , ""L3 Interconnect,PM (Protection Mechanism Common Registers),PM_OCM_ROM"""
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menuitem "PM_IPSS" "per , ""L3 Interconnect,PM (Protection Mechanism Common Registers),PM_IPSS"""
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)
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menuitem "SI" "per , ""L3 Interconnect,SI (Sideband Interconnect Registers)"""
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)
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popup "L4 Interconnect"
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(
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popup "L4-Core"
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(
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menuitem "IA" "per , ""L4 Interconnect,L4-Core,IA (Initiator Agent Registers)"""
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menuitem "LA" "per , ""L4 Interconnect,L4-Core,LA (Link Agent Registers)"""
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menuitem "AP" "per , ""L4 Interconnect,L4-Core,AP (Address Protection Registers)"""
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popup "TA"
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(
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menuitem "CORE_TA_CONTROL" "per , ""L4 Interconnect,L4-Core,TA (Target Agent Registers),CORE_TA_CONTROL"""
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menuitem "CORE_TA_CM" "per , ""L4 Interconnect,L4-Core,TA (Target Agent Registers),CORE_TA_CM"""
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menuitem "CORE_TA_DISPLAY_SS" "per , ""L4 Interconnect,L4-Core,TA (Target Agent Registers),CORE_TA_DISPLAY_SS"""
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menuitem "CORE_TA_SDMA" "per , ""L4 Interconnect,L4-Core,TA (Target Agent Registers),CORE_TA_SDMA"""
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menuitem "CORE_TA_I2C3" "per , ""L4 Interconnect,L4-Core,TA (Target Agent Registers),CORE_TA_I2C3"""
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menuitem "CORE_TA_USB_HS_TLL" "per , ""L4 Interconnect,L4-Core,TA (Target Agent Registers),CORE_TA_USB_HS_TLL"""
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menuitem "CORE_TA_USB_HS_Host" "per , ""L4 Interconnect,L4-Core,TA (Target Agent Registers),CORE_TA_USB_HS_Host"""
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menuitem "CORE_TA_UART1" "per , ""L4 Interconnect,L4-Core,TA (Target Agent Registers),CORE_TA_UART1"""
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menuitem "CORE_TA_UART2" "per , ""L4 Interconnect,L4-Core,TA (Target Agent Registers),CORE_TA_UART2"""
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menuitem "CORE_TA_I2C1" "per , ""L4 Interconnect,L4-Core,TA (Target Agent Registers),CORE_TA_I2C1"""
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menuitem "CORE_TA_I2C2" "per , ""L4 Interconnect,L4-Core,TA (Target Agent Registers),CORE_TA_I2C2"""
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menuitem "CORE_TA_MCBSP1" "per , ""L4 Interconnect,L4-Core,TA (Target Agent Registers),CORE_TA_MCBSP1"""
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menuitem "CORE_TA_GPTIMER10" "per , ""L4 Interconnect,L4-Core,TA (Target Agent Registers),CORE_TA_GPTIMER10"""
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menuitem "CORE_TA_GPTIMER11" "per , ""L4 Interconnect,L4-Core,TA (Target Agent Registers),CORE_TA_GPTIMER11"""
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menuitem "CORE_TA_MCBSP5" "per , ""L4 Interconnect,L4-Core,TA (Target Agent Registers),CORE_TA_MCBSP5"""
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menuitem "CORE_TA_SPI1" "per , ""L4 Interconnect,L4-Core,TA (Target Agent Registers),CORE_TA_SPI1"""
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menuitem "CORE_TA_SPI2" "per , ""L4 Interconnect,L4-Core,TA (Target Agent Registers),CORE_TA_SPI2"""
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menuitem "CORE_TA_MMCHS1" "per , ""L4 Interconnect,L4-Core,TA (Target Agent Registers),CORE_TA_MMCHS1"""
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menuitem "CORE_TA_UART4" "per , ""L4 Interconnect,L4-Core,TA (Target Agent Registers),CORE_TA_UART4"""
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menuitem "CORE_TA_MMCHS3" "per , ""L4 Interconnect,L4-Core,TA (Target Agent Registers),CORE_TA_MMCHS3"""
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menuitem "TA_MG" "per , ""L4 Interconnect,L4-Core,TA (Target Agent Registers),TA_MG"""
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menuitem "CORE_TA_HDQ1W" "per , ""L4 Interconnect,L4-Core,TA (Target Agent Registers),CORE_TA_HDQ1W"""
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menuitem "CORE_TA_MMCHS2" "per , ""L4 Interconnect,L4-Core,TA (Target Agent Registers),CORE_TA_MMCHS2"""
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menuitem "CORE_TA_MCSPI3" "per , ""L4 Interconnect,L4-Core,TA (Target Agent Registers),CORE_TA_MCSPI3"""
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menuitem "CORE_TA_MCSPI4" "per , ""L4 Interconnect,L4-Core,TA (Target Agent Registers),CORE_TA_MCSPI4"""
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menuitem "CORE_TA_INTH" "per , ""L4 Interconnect,L4-Core,TA (Target Agent Registers),CORE_TA_INTH"""
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menuitem "CORE_TA_WKUP" "per , ""L4 Interconnect,L4-Core,TA (Target Agent Registers),CORE_TA_WKUP"""
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)
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)
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popup "L4-Per"
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(
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menuitem "IA" "per , ""L4 Interconnect,L4-Per,IA (Initiator Agent Registers)"""
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menuitem "LA" "per , ""L4 Interconnect,L4-Per,LA (Link Agent Registers)"""
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menuitem "AP" "per , ""L4 Interconnect,L4-Per,AP (Address Protection Registers)"""
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popup "TA"
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(
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menuitem "PER_TA_UART3" "per , ""L4 Interconnect,L4-Per,TA (Target Agent Registers),PER_TA_UART3"""
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menuitem "PER_TA_MCBSP2" "per , ""L4 Interconnect,L4-Per,TA (Target Agent Registers),PER_TA_MCBSP2"""
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menuitem "PER_TA_MCBSP3" "per , ""L4 Interconnect,L4-Per,TA (Target Agent Registers),PER_TA_MCBSP3"""
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menuitem "PER_TA_MCBSP4" "per , ""L4 Interconnect,L4-Per,TA (Target Agent Registers),PER_TA_MCBSP4"""
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menuitem "PER_TA_MCBSP2_SIDETONE2" "per , ""L4 Interconnect,L4-Per,TA (Target Agent Registers),PER_TA_MCBSP2_SIDETONE2"""
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menuitem "PER_TA_MCBSP2_SIDETONE3" "per , ""L4 Interconnect,L4-Per,TA (Target Agent Registers),PER_TA_MCBSP2_SIDETONE3"""
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menuitem "PER_TA_WDTIMER3" "per , ""L4 Interconnect,L4-Per,TA (Target Agent Registers),PER_TA_WDTIMER3"""
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menuitem "PER_TA_GPTIMER2" "per , ""L4 Interconnect,L4-Per,TA (Target Agent Registers),PER_TA_GPTIMER2"""
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menuitem "PER_TA_GPTIMER3" "per , ""L4 Interconnect,L4-Per,TA (Target Agent Registers),PER_TA_GPTIMER3"""
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menuitem "PER_TA_GPTIMER4" "per , ""L4 Interconnect,L4-Per,TA (Target Agent Registers),PER_TA_GPTIMER4"""
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menuitem "PER_TA_GPTIMER5" "per , ""L4 Interconnect,L4-Per,TA (Target Agent Registers),PER_TA_GPTIMER5"""
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menuitem "PER_TA_GPTIMER6" "per , ""L4 Interconnect,L4-Per,TA (Target Agent Registers),PER_TA_GPTIMER6"""
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menuitem "PER_TA_GPTIMER7" "per , ""L4 Interconnect,L4-Per,TA (Target Agent Registers),PER_TA_GPTIMER7"""
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menuitem "PER_TA_GPTIMER8" "per , ""L4 Interconnect,L4-Per,TA (Target Agent Registers),PER_TA_GPTIMER8"""
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menuitem "PER_TA_GPTIMER9" "per , ""L4 Interconnect,L4-Per,TA (Target Agent Registers),PER_TA_GPTIMER9"""
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menuitem "PER_TA_GPIO2" "per , ""L4 Interconnect,L4-Per,TA (Target Agent Registers),PER_TA_GPIO2"""
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menuitem "PER_TA_GPIO3" "per , ""L4 Interconnect,L4-Per,TA (Target Agent Registers),PER_TA_GPIO3"""
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menuitem "PER_TA_GPIO4" "per , ""L4 Interconnect,L4-Per,TA (Target Agent Registers),PER_TA_GPIO4"""
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menuitem "PER_TA_GPIO5" "per , ""L4 Interconnect,L4-Per,TA (Target Agent Registers),PER_TA_GPIO5"""
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menuitem "PER_TA_GPIO6" "per , ""L4 Interconnect,L4-Per,TA (Target Agent Registers),PER_TA_GPIO6"""
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)
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)
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popup "L4-Emu"
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(
|
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popup "IA"
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(
|
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menuitem "EMU_IA_L3" "per , ""L4 Interconnect,L4-Emu,IA (Initiator Agent Registers),EMU_IA_L3"""
|
|
menuitem "EMU_IA_DAP" "per , ""L4 Interconnect,L4-Emu,IA (Initiator Agent Registers),EMU_IA_DAP"""
|
|
)
|
|
menuitem "LA" "per , ""L4 Interconnect,L4-Emu,LA (Link Agent Registers)"""
|
|
menuitem "AP" "per , ""L4 Interconnect,L4-Emu,AP (Address Protection Registers)"""
|
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popup "TA"
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|
(
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menuitem "EMU_TA_TEST_TAP" "per , ""L4 Interconnect,L4-Emu,TA (Target Agent Registers),EMU_TA_TEST_TAP"""
|
|
menuitem "EMU_TA_MPU" "per , ""L4 Interconnect,L4-Emu,TA (Target Agent Registers),EMU_TA_MPU"""
|
|
menuitem "EMU_TA_TPIU" "per , ""L4 Interconnect,L4-Emu,TA (Target Agent Registers),EMU_TA_TPIU"""
|
|
menuitem "EMU_TA_ETB" "per , ""L4 Interconnect,L4-Emu,TA (Target Agent Registers),EMU_TA_ETB"""
|
|
menuitem "EMU_TA_DAPCTL" "per , ""L4 Interconnect,L4-Emu,TA (Target Agent Registers),EMU_TA_DAPCTL"""
|
|
menuitem "EMU_TA_SDTI" "per , ""L4 Interconnect,L4-Emu,TA (Target Agent Registers),EMU_TA_SDTI"""
|
|
menuitem "EMU_TA_L4WKUP" "per , ""L4 Interconnect,L4-Emu,TA (Target Agent Registers),EMU_TA_L4WKUP"""
|
|
)
|
|
)
|
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popup "L4-Wakeup"
|
|
(
|
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popup "IA"
|
|
(
|
|
menuitem "L4-Core" "per , ""L4 Interconnect,L4-Wakeup,IA (Initiator Agent Registers),L4-Core"""
|
|
menuitem "L4-Emu" "per , ""L4 Interconnect,L4-Wakeup,IA (Initiator Agent Registers),L4-Emu"""
|
|
)
|
|
menuitem "LA" "per , ""L4 Interconnect,L4-Wakeup,LA (Link Agent Registers)"""
|
|
menuitem "AP" "per , ""L4 Interconnect,L4-Wakeup,AP (Address Protection Registers)"""
|
|
popup "TA"
|
|
(
|
|
menuitem "WKUP_TA_GPTIMER12" "per , ""L4 Interconnect,L4-Wakeup,TA (Target Agent Registers),WKUP_TA_GPTIMER12"""
|
|
menuitem "WKUP_TA_PRM" "per , ""L4 Interconnect,L4-Wakeup,TA (Target Agent Registers),WKUP_TA_PRM"""
|
|
menuitem "WKUP_TA_WDTIMER1" "per , ""L4 Interconnect,L4-Wakeup,TA (Target Agent Registers),WKUP_TA_WDTIMER1"""
|
|
menuitem "WKUP_TA_GPIO1" "per , ""L4 Interconnect,L4-Wakeup,TA (Target Agent Registers),WKUP_TA_GPIO1"""
|
|
menuitem "WKUP_TA_WDTIMER2" "per , ""L4 Interconnect,L4-Wakeup,TA (Target Agent Registers),WKUP_TA_WDTIMER2"""
|
|
menuitem "WKUP_TA_GPTIMER1" "per , ""L4 Interconnect,L4-Wakeup,TA (Target Agent Registers),WKUP_TA_GPTIMER1"""
|
|
menuitem "WKUP_TA_SYNCTIMER32K" "per , ""L4 Interconnect,L4-Wakeup,TA (Target Agent Registers),WKUP_TA_SYNCTIMER32K"""
|
|
)
|
|
)
|
|
)
|
|
popup "SCM"
|
|
(
|
|
menuitem "INTERFACE" "per , ""SCM (System Control Module),INTERFACE"""
|
|
menuitem "PADCONFS" "per , ""SCM (System Control Module),PADCONFS"""
|
|
menuitem "GENERAL" "per , ""SCM (System Control Module),GENERAL"""
|
|
menuitem "MEM_WKUP" "per , ""SCM (System Control Module),MEM_WKUP"""
|
|
menuitem "PADCONFS_WKUP" "per , ""SCM (System Control Module),PADCONFS_WKUP"""
|
|
menuitem "GENERAL_WKUP" "per , ""SCM (System Control Module),GENERAL_WKUP"""
|
|
)
|
|
popup "SDMA"
|
|
(
|
|
menuitem "Common Registers" "per , ""SDMA (System Direct Memory Access),Common Registers"""
|
|
menuitem "Channels Registers" "per , ""SDMA (System Direct Memory Access),Channels Registers"""
|
|
)
|
|
popup "INTC"
|
|
(
|
|
menuitem "MPU subsystem INTC" "per , ""INTC (Interrupt Controller Registers),MPU subsystem INTC"""
|
|
menuitem "Device INTC" "per , ""INTC (Interrupt Controller Registers),Device INTC"""
|
|
)
|
|
popup "Memory Subsystem"
|
|
(
|
|
menuitem "GPMC" "per , ""Memory Subsystem,General Purpose Memory Controller (GPMC)"""
|
|
popup "SDRC"
|
|
(
|
|
menuitem "EMIF4" "per , ""Memory Subsystem,SDRC (SDRAM Controller),EMIF4"""
|
|
menuitem "SMS" "per , ""Memory Subsystem,SDRC (SDRAM Controller),SMS (SDRAM Memory Scheduler)"""
|
|
)
|
|
)
|
|
menuitem "VPFE" "per , ""VPFE (Video Processing Front End)"""
|
|
popup "Display Subsystem"
|
|
(
|
|
menuitem "DISS" "per , ""Display Subsystem,DISS"""
|
|
menuitem "DISPC" "per , ""Display Subsystem,DISPC"""
|
|
menuitem "RFBI" "per , ""Display Subsystem,RFBI"""
|
|
menuitem "VENC" "per , ""Display Subsystem,VENC"""
|
|
popup "DSI"
|
|
(
|
|
menuitem "Protocol Engine Registers" "per , ""Display Subsystem,DSI,Protocol Engine Registers"""
|
|
menuitem "Complex I/O Registers" "per , ""Display Subsystem,DSI,Complex I/O Registers"""
|
|
menuitem "PLL Control Module Registers" "per , ""Display Subsystem,DSI,PLL Control Module Registers"""
|
|
)
|
|
)
|
|
popup "Timers"
|
|
(
|
|
popup "GPT"
|
|
(
|
|
menuitem "GPTIMER1" "per , ""Timers,GPT (General Purpose Timer),GPTIMER1"""
|
|
menuitem "GPTIMER2" "per , ""Timers,GPT (General Purpose Timer),GPTIMER2"""
|
|
menuitem "GPTIMER3" "per , ""Timers,GPT (General Purpose Timer),GPTIMER3"""
|
|
menuitem "GPTIMER4" "per , ""Timers,GPT (General Purpose Timer),GPTIMER4"""
|
|
menuitem "GPTIMER5" "per , ""Timers,GPT (General Purpose Timer),GPTIMER5"""
|
|
menuitem "GPTIMER6" "per , ""Timers,GPT (General Purpose Timer),GPTIMER6"""
|
|
menuitem "GPTIMER7" "per , ""Timers,GPT (General Purpose Timer),GPTIMER7"""
|
|
menuitem "GPTIMER8" "per , ""Timers,GPT (General Purpose Timer),GPTIMER8"""
|
|
menuitem "GPTIMER9" "per , ""Timers,GPT (General Purpose Timer),GPTIMER9"""
|
|
menuitem "GPTIMER10" "per , ""Timers,GPT (General Purpose Timer),GPTIMER10"""
|
|
menuitem "GPTIMER11" "per , ""Timers,GPT (General Purpose Timer),GPTIMER11"""
|
|
menuitem "GPTIMER12" "per , ""Timers,GPT (General Purpose Timer),GPTIMER12"""
|
|
)
|
|
popup "WDT"
|
|
(
|
|
menuitem "WDT1" "per , ""Timers,WDT (Watchdog Timer),WDT1"""
|
|
menuitem "WDT2" "per , ""Timers,WDT (Watchdog Timer),WDT2"""
|
|
menuitem "WDT3" "per , ""Timers,WDT (Watchdog Timer),WDT3"""
|
|
)
|
|
menuitem "32-kHz Sync" "per , ""Timers,32-kHz Sync"""
|
|
)
|
|
popup "UART/IrDA/CIR"
|
|
(
|
|
menuitem "UART1" "per , ""UART/IrDA/CIR,UART1"""
|
|
menuitem "UART2" "per , ""UART/IrDA/CIR,UART2"""
|
|
menuitem "UART3/IrDA/CIR" "per , ""UART/IrDA/CIR,UART3/IrDA/CIR"""
|
|
menuitem "UART4" "per , ""UART/IrDA/CIR,UART4"""
|
|
)
|
|
popup "I2C"
|
|
(
|
|
menuitem "I2C1" "per , ""I2C (Inter-Integrated Circuit),I2C1"""
|
|
menuitem "I2C2" "per , ""I2C (Inter-Integrated Circuit),I2C2"""
|
|
menuitem "I2C3" "per , ""I2C (Inter-Integrated Circuit),I2C3"""
|
|
)
|
|
popup "McSPI"
|
|
(
|
|
menuitem "MCSPI1" "per , ""McSPI (Multichannel Serial Port Interface),MCSPI1"""
|
|
menuitem "MCSPI2" "per , ""McSPI (Multichannel Serial Port Interface),MCSPI2"""
|
|
menuitem "MCSPI3" "per , ""McSPI (Multichannel Serial Port Interface),MCSPI3"""
|
|
menuitem "MCSPI4" "per , ""McSPI (Multichannel Serial Port Interface),MCSPI4"""
|
|
)
|
|
popup "McBSP"
|
|
(
|
|
menuitem "McBSP1" "per , ""McBSP (Multi-Channel Buffered Serial Port),McBSP1"""
|
|
menuitem "McBSP2" "per , ""McBSP (Multi-Channel Buffered Serial Port),McBSP2"""
|
|
menuitem "SIDETONE_McBSP2" "per , ""McBSP (Multi-Channel Buffered Serial Port),SIDETONE_McBSP2"""
|
|
menuitem "McBSP3" "per , ""McBSP (Multi-Channel Buffered Serial Port),McBSP3"""
|
|
menuitem "SIDETONE_McBSP3" "per , ""McBSP (Multi-Channel Buffered Serial Port),SIDETONE_McBSP3"""
|
|
menuitem "McBSP4" "per , ""McBSP (Multi-Channel Buffered Serial Port),McBSP4"""
|
|
menuitem "McBSP5" "per , ""McBSP (Multi-Channel Buffered Serial Port),McBSP5"""
|
|
)
|
|
menuitem "HDQ/1-Wire" "per , ""HDQ/1-Wire"""
|
|
popup "MMC/SD/SDIO"
|
|
(
|
|
menuitem "MMCHS1" "per , ""MMC/SD/SDIO Card Interface,MMCHS1"""
|
|
menuitem "MMCHS2" "per , ""MMC/SD/SDIO Card Interface,MMCHS2"""
|
|
menuitem "MMCHS3" "per , ""MMC/SD/SDIO Card Interface,MMCHS3"""
|
|
)
|
|
popup "USB"
|
|
(
|
|
menuitem "USB 2.0 Controller" "per , ""USB (Universal Serial Bus v2.0),USB 2.0 Controller"""
|
|
popup "High-Speed USB Host Subsystem"
|
|
(
|
|
menuitem "USBTLL" "per , ""USB (Universal Serial Bus v2.0),High-Speed USB Host Subsystem,USBTLL"""
|
|
menuitem "UHH_config" "per , ""USB (Universal Serial Bus v2.0),High-Speed USB Host Subsystem,UHH_config"""
|
|
menuitem "OHCI" "per , ""USB (Universal Serial Bus v2.0),High-Speed USB Host Subsystem,OHCI"""
|
|
menuitem "EHCI" "per , ""USB (Universal Serial Bus v2.0),High-Speed USB Host Subsystem,EHCI"""
|
|
)
|
|
)
|
|
popup "GPIO"
|
|
(
|
|
menuitem "GPIO 1" "per , ""GPIO (General-Purpose Input/Output),GPIO 1"""
|
|
menuitem "GPIO 2" "per , ""GPIO (General-Purpose Input/Output),GPIO 2"""
|
|
menuitem "GPIO 3" "per , ""GPIO (General-Purpose Input/Output),GPIO 3"""
|
|
menuitem "GPIO 4" "per , ""GPIO (General-Purpose Input/Output),GPIO 4"""
|
|
menuitem "GPIO 5" "per , ""GPIO (General-Purpose Input/Output),GPIO 5"""
|
|
menuitem "GPIO 6" "per , ""GPIO (General-Purpose Input/Output),GPIO 6"""
|
|
)
|
|
popup "EMAC/MDIO"
|
|
(
|
|
menuitem "EMAC Control Module" "per , ""EMAC/MDIO (Ethernet Media Access Controller/Management Data Input/Output Module),EMAC Control Module"""
|
|
menuitem "MDIO" "per , ""EMAC/MDIO (Ethernet Media Access Controller/Management Data Input/Output Module),MDIO"""
|
|
menuitem "EMAC Module" "per , ""EMAC/MDIO (Ethernet Media Access Controller/Management Data Input/Output Module),EMAC Module"""
|
|
)
|
|
popup "HECC"
|
|
(
|
|
menuitem "SSC/HECC Control Registers" "per , ""HECC (High-End CAN Controller),SSC/HECC Control Registers"""
|
|
menuitem "Time Stamp Registers" "per , ""HECC (High-End CAN Controller),Time Stamp Registers"""
|
|
menuitem "Time-Out Registers" "per , ""HECC (High-End CAN Controller),Time-Out Registers"""
|
|
menuitem "Message Mailbox Registers" "per , ""HECC (High-End CAN Controller),Message Mailbox Registers"""
|
|
)
|
|
)
|
|
)
|