630 lines
26 KiB
Plaintext
630 lines
26 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: 66AK2Gx Specific Menu
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; @Props: Released
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; @Author: ASK, KRZ
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; @Changelog: 2016-10-14 ASK
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; 2022-04-29 KRZ
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; @Manufacturer: TI - Texas Instruments
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; @Core: Cortex-A15, C646X, PRU
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; @Copyright: 1989-2022 Lauterbach GmbH, licensed for use with TRACE32 only
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; --------------------------------------------------------------------------------
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; $Id: men66ak2gx.men 16339 2023-07-03 13:30:14Z pegold $
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add
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menu
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(
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if (CPUFAMILY()=="C6000")
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(
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popup "&CPU"
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(
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after "FPU Registers"
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separator
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popup "[:cache]Cache"
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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popup "&Trace"
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(
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("AET")
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(
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menuitem "[:oconfig]AET settings..." "AET.state"
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)
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)
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popup "&Perf"
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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if (!cpuis("66AK2G?2-ICSS?")&&cpu()!="PRU")
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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if (CORENAME()=="CORTEXA15MPCORE")
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(
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popup "[:chip]Core Registers (Cortex-A15MPCore)"
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(
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menuitem "[:chip]ID Registers" "per , ""Core Registers (Cortex-A15MPCore),ID Registers"""
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menuitem "[:chip]System Control and Configuration" "per , ""Core Registers (Cortex-A15MPCore),System Control and Configuration"""
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menuitem "[:chip]Memory Management Unit" "per , ""Core Registers (Cortex-A15MPCore),Memory Management Unit"""
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menuitem "[:chip]Virtualization Extensions" "per , ""Core Registers (Cortex-A15MPCore),Virtualization Extensions"""
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menuitem "[:chip]Cache Control and Configuration" "per , ""Core Registers (Cortex-A15MPCore),Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor" "per , ""Core Registers (Cortex-A15MPCore),System Performance Monitor"""
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menuitem "[:chip]System Timer Register" "per , ""Core Registers (Cortex-A15MPCore),System Timer Register"""
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separator
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menuitem "[:chip]Debug Registers" "per , ""Core Registers (Cortex-A15MPCore),Debug Registers"""
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menuitem "[:chip]Breakpoint Registers" "per , ""Core Registers (Cortex-A15MPCore),Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Control Registers" "per , ""Core Registers (Cortex-A15MPCore),Watchpoint Control Registers"""
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)
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)
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else
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(
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popup "[:chip]Core Registers (c66x)"
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(
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menuitem "[:chip]L1P;L1P Registers" "per , ""Core Registers (c66x),Cache,L1P Cache"""
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menuitem "[:chip]L1D;L1D Registers" "per , ""Core Registers (c66x),Cache,L1D Cache"""
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menuitem "[:chip]L2;L2 Registers" "per , ""Core Registers (c66x),Cache,L2 Cache"""
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menuitem "[:chip]IDMA;IDMA Registers" "per , ""Core Registers (c66x),IDMA (Internal Direct Memory Access Controller)"""
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menuitem "[:chip]XMC;XMC Registers" "per , ""Core Registers (c66x),XMC (Extended Memory Controller)"""
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menuitem "[:chip]BM;BM Registers" "per , ""Core Registers (c66x),Bandwith Management"""
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menuitem "[:chip]IC;IC Registers" "per , ""Core Registers (c66x),Interrupt Controller"""
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menuitem "[:chip]PD;PD Registers" "per , ""Core Registers (c66x),Power-Down Controller"""
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)
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)
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separator
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popup "ARM_Cortex_A15_Subsystem"
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(
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menuitem "ARM_VBUSP" "per , ""ARM_Cortex_A15_Subsystem,ARM_VBUSP"""
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menuitem "ARM_VBUSP" "per , ""ARM_Cortex_A15_Subsystem,ARM_VBUSP"""
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menuitem "AXI2VBUS_MASTER" "per , ""ARM_Cortex_A15_Subsystem,AXI2VBUS_MASTER"""
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menuitem "AXI2VBUS_MASTER" "per , ""ARM_Cortex_A15_Subsystem,AXI2VBUS_MASTER"""
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)
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popup "BOOT_CFG"
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(
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menuitem "BOOT_CFG" "per , ""BOOT_CFG,BOOT_CFG"""
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)
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popup "DCAN"
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(
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menuitem "DCAN_0" "per , ""DCAN,DCAN_0"""
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menuitem "DCAN_0_DATA" "per , ""DCAN,DCAN_0_DATA"""
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menuitem "DCAN_1" "per , ""DCAN,DCAN_1"""
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menuitem "DCAN_1_DATA" "per , ""DCAN,DCAN_1_DATA"""
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)
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popup "DISPC_COMMON"
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(
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menuitem "DISPC_COMMON" "per , ""DISPC_COMMON,DISPC_COMMON"""
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)
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popup "DISPC_OVR1"
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(
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menuitem "DISPC_OVR1" "per , ""DISPC_OVR1,DISPC_OVR1"""
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)
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popup "DISPC_VID1"
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(
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menuitem "DISPC_VID1" "per , ""DISPC_VID1,DISPC_VID1"""
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)
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popup "DISPC_VP1"
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(
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menuitem "DISPC_VP1" "per , ""DISPC_VP1,DISPC_VP1"""
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)
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popup "DSSUL_0_CFG"
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(
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menuitem "DSSUL_0_CFG" "per , ""DSSUL_0_CFG,DSSUL_0_CFG"""
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)
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popup "eCAP"
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(
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menuitem "ECAP_0" "per , ""eCAP,ECAP_0"""
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menuitem "ECAP_1" "per , ""eCAP,ECAP_1"""
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)
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popup "EDMA"
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(
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menuitem "EDMACC_0" "per , ""EDMA,EDMACC_0"""
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menuitem "EDMACC_1" "per , ""EDMA,EDMACC_1"""
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menuitem "EDMACC_0" "per , ""EDMA,EDMACC_0"""
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menuitem "EDMACC_1" "per , ""EDMA,EDMACC_1"""
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menuitem "EDMACC_0_TC_0" "per , ""EDMA,EDMACC_0_TC_0"""
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menuitem "EDMACC_0_TC_1" "per , ""EDMA,EDMACC_0_TC_1"""
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menuitem "EDMACC_1_TC_0" "per , ""EDMA,EDMACC_1_TC_0"""
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menuitem "EDMACC_1_TC_1" "per , ""EDMA,EDMACC_1_TC_1"""
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menuitem "EDMACC_0_TC_0" "per , ""EDMA,EDMACC_0_TC_0"""
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menuitem "EDMACC_0_TC_1" "per , ""EDMA,EDMACC_0_TC_1"""
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menuitem "EDMACC_1_TC_0" "per , ""EDMA,EDMACC_1_TC_0"""
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menuitem "EDMACC_1_TC_1" "per , ""EDMA,EDMACC_1_TC_1"""
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)
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popup "ELM"
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(
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menuitem "ELM" "per , ""ELM,ELM"""
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)
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popup "EMIF"
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|
(
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menuitem "DDR_PHY" "per , ""EMIF,DDR_PHY"""
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menuitem "EMIF" "per , ""EMIF,EMIF"""
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)
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popup "ePWM"
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(
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menuitem "EPWM_0" "per , ""ePWM,EPWM_0"""
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menuitem "EPWM_1" "per , ""ePWM,EPWM_1"""
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menuitem "EPWM_2" "per , ""ePWM,EPWM_2"""
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menuitem "EPWM_3" "per , ""ePWM,EPWM_3"""
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menuitem "EPWM_4" "per , ""ePWM,EPWM_4"""
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menuitem "EPWM_5" "per , ""ePWM,EPWM_5"""
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)
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popup "eQEP"
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(
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menuitem "EQEP_0" "per , ""eQEP,EQEP_0"""
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menuitem "EQEP_1" "per , ""eQEP,EQEP_1"""
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menuitem "EQEP_2" "per , ""eQEP,EQEP_2"""
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)
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popup "GPIO"
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(
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menuitem "GPIO_0" "per , ""GPIO,GPIO_0"""
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menuitem "GPIO_1" "per , ""GPIO,GPIO_1"""
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)
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popup "GPMC"
|
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(
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menuitem "GPMC" "per , ""GPMC,GPMC"""
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)
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popup "I2C"
|
|
(
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menuitem "I2C_0" "per , ""I2C,I2C_0"""
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menuitem "I2C_1" "per , ""I2C,I2C_1"""
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menuitem "I2C_2" "per , ""I2C,I2C_2"""
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)
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popup "MPU"
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(
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menuitem "MPU_0" "per , ""MPU,MPU_0"""
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menuitem "MPU_1" "per , ""MPU,MPU_1"""
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menuitem "MPU_2" "per , ""MPU,MPU_2"""
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menuitem "MPU_3" "per , ""MPU,MPU_3"""
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menuitem "MPU_4" "per , ""MPU,MPU_4"""
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menuitem "MPU_5" "per , ""MPU,MPU_5"""
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menuitem "MPU_6" "per , ""MPU,MPU_6"""
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menuitem "MPU_7" "per , ""MPU,MPU_7"""
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menuitem "MPU_8" "per , ""MPU,MPU_8"""
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menuitem "MPU_9" "per , ""MPU,MPU_9"""
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menuitem "MPU_10" "per , ""MPU,MPU_10"""
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menuitem "MPU_11" "per , ""MPU,MPU_11"""
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menuitem "MPU_12" "per , ""MPU,MPU_12"""
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menuitem "MPU_13" "per , ""MPU,MPU_13"""
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menuitem "MPU_14" "per , ""MPU,MPU_14"""
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menuitem "MPU_15" "per , ""MPU,MPU_15"""
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menuitem "MPU_16" "per , ""MPU,MPU_16"""
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)
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popup "MSMC"
|
|
(
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menuitem "MSMC" "per , ""MSMC,MSMC"""
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)
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popup "NSS"
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(
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menuitem "NSS_0_CFG__cppidma0_tx_scheduler" "per , ""NSS,NSS_0_CFG__cppidma0_tx_scheduler"""
|
|
menuitem "NSS_0_CFG__cppidma0_tx_scheduler" "per , ""NSS,NSS_0_CFG__cppidma0_tx_scheduler"""
|
|
menuitem "NSS_0_CFG__cppidma0_tx_scheduler" "per , ""NSS,NSS_0_CFG__cppidma0_tx_scheduler"""
|
|
menuitem "NSS_0_CFG__cppidma0_tx_scheduler" "per , ""NSS,NSS_0_CFG__cppidma0_tx_scheduler"""
|
|
menuitem "NSS_0_CFG_ALE" "per , ""NSS,NSS_0_CFG_ALE"""
|
|
menuitem "NSS_0_CFG_ALE" "per , ""NSS,NSS_0_CFG_ALE"""
|
|
menuitem "NSS_0_CFG_ALE" "per , ""NSS,NSS_0_CFG_ALE"""
|
|
menuitem "NSS_0_CFG_CPPIDMA0_CONFIG" "per , ""NSS,NSS_0_CFG_CPPIDMA0_CONFIG"""
|
|
menuitem "NSS_0_CFG_CPPIDMA0_CONFIG" "per , ""NSS,NSS_0_CFG_CPPIDMA0_CONFIG"""
|
|
menuitem "NSS_0_CFG_CPPIDMA0_CONFIG" "per , ""NSS,NSS_0_CFG_CPPIDMA0_CONFIG"""
|
|
menuitem "NSS_0_CFG_CPPIDMA0_CONFIG" "per , ""NSS,NSS_0_CFG_CPPIDMA0_CONFIG"""
|
|
menuitem "NSS_0_CFG_CPSW" "per , ""NSS,NSS_0_CFG_CPSW"""
|
|
menuitem "NSS_0_CFG_CPSW" "per , ""NSS,NSS_0_CFG_CPSW"""
|
|
menuitem "NSS_0_CFG_CPSW" "per , ""NSS,NSS_0_CFG_CPSW"""
|
|
menuitem "NSS_0_CFG_CPTS" "per , ""NSS,NSS_0_CFG_CPTS"""
|
|
menuitem "NSS_0_CFG_CPTS" "per , ""NSS,NSS_0_CFG_CPTS"""
|
|
menuitem "NSS_0_CFG_CPTS" "per , ""NSS,NSS_0_CFG_CPTS"""
|
|
menuitem "NSS_0_CFG_EMAC" "per , ""NSS,NSS_0_CFG_EMAC"""
|
|
menuitem "NSS_0_CFG_EMAC" "per , ""NSS,NSS_0_CFG_EMAC"""
|
|
menuitem "NSS_0_CFG_EMAC" "per , ""NSS,NSS_0_CFG_EMAC"""
|
|
menuitem "NSS_0_CFG_INTD" "per , ""NSS,NSS_0_CFG_INTD"""
|
|
menuitem "NSS_0_CFG_INTD" "per , ""NSS,NSS_0_CFG_INTD"""
|
|
menuitem "NSS_0_CFG_INTD" "per , ""NSS,NSS_0_CFG_INTD"""
|
|
menuitem "NSS_0_CFG_MDIO" "per , ""NSS,NSS_0_CFG_MDIO"""
|
|
menuitem "NSS_0_CFG_MDIO" "per , ""NSS,NSS_0_CFG_MDIO"""
|
|
menuitem "NSS_0_CFG_MDIO" "per , ""NSS,NSS_0_CFG_MDIO"""
|
|
menuitem "NSS_0_CFG_NAVSS_CFG" "per , ""NSS,NSS_0_CFG_NAVSS_CFG"""
|
|
menuitem "NSS_0_CFG_NAVSS_CFG" "per , ""NSS,NSS_0_CFG_NAVSS_CFG"""
|
|
menuitem "NSS_0_CFG_NAVSS_CFG" "per , ""NSS,NSS_0_CFG_NAVSS_CFG"""
|
|
menuitem "NSS_0_CFG_EMAC_ECC" "per , ""NSS,NSS_0_CFG_EMAC_ECC"""
|
|
menuitem "NSS_0_CFG_NAVSS_ECC" "per , ""NSS,NSS_0_CFG_NAVSS_ECC"""
|
|
menuitem "NSS_0_CFG_EMAC_ECC" "per , ""NSS,NSS_0_CFG_EMAC_ECC"""
|
|
menuitem "NSS_0_CFG_NAVSS_ECC" "per , ""NSS,NSS_0_CFG_NAVSS_ECC"""
|
|
menuitem "NSS_0_CFG_EMAC_ECC" "per , ""NSS,NSS_0_CFG_EMAC_ECC"""
|
|
menuitem "NSS_0_CFG_NAVSS_ECC" "per , ""NSS,NSS_0_CFG_NAVSS_ECC"""
|
|
menuitem "NSS_0_CFG_QMGR0_CFG" "per , ""NSS,NSS_0_CFG_QMGR0_CFG"""
|
|
menuitem "NSS_0_CFG_QMGR0_CFG" "per , ""NSS,NSS_0_CFG_QMGR0_CFG"""
|
|
menuitem "NSS_0_CFG_QMGR0_CFG" "per , ""NSS,NSS_0_CFG_QMGR0_CFG"""
|
|
menuitem "NSS_0_CFG_QMGR0_CFG" "per , ""NSS,NSS_0_CFG_QMGR0_CFG"""
|
|
menuitem "PCIE_0_ECC_CFG" "per , ""NSS,PCIE_0_ECC_CFG"""
|
|
menuitem "PCIE_0_ECC_CFG" "per , ""NSS,PCIE_0_ECC_CFG"""
|
|
menuitem "PCIE_0_PHY_CFG" "per , ""NSS,PCIE_0_PHY_CFG"""
|
|
menuitem "PCIE_0_PHY_CFG" "per , ""NSS,PCIE_0_PHY_CFG"""
|
|
menuitem "PCIE_APPLICATION" "per , ""NSS,PCIE_APPLICATION"""
|
|
menuitem "PCIE_APPLICATION" "per , ""NSS,PCIE_APPLICATION"""
|
|
menuitem "PCIE_CAP_EXT_REGS" "per , ""NSS,PCIE_CAP_EXT_REGS"""
|
|
menuitem "PCIE_CAP_EXT_REGS" "per , ""NSS,PCIE_CAP_EXT_REGS"""
|
|
menuitem "PCIE_CAP_REGS" "per , ""NSS,PCIE_CAP_REGS"""
|
|
menuitem "PCIE_CAP_REGS" "per , ""NSS,PCIE_CAP_REGS"""
|
|
menuitem "PCIE_CFG" "per , ""NSS,PCIE_CFG"""
|
|
menuitem "PCIE_CFG" "per , ""NSS,PCIE_CFG"""
|
|
menuitem "PCIE_CFG_TYPE0" "per , ""NSS,PCIE_CFG_TYPE0"""
|
|
menuitem "PCIE_CFG_TYPE0" "per , ""NSS,PCIE_CFG_TYPE0"""
|
|
menuitem "PCIE_CFG_TYPE1" "per , ""NSS,PCIE_CFG_TYPE1"""
|
|
menuitem "PCIE_CFG_TYPE1" "per , ""NSS,PCIE_CFG_TYPE1"""
|
|
menuitem "PCIE_MSG_IRQ_REGS" "per , ""NSS,PCIE_MSG_IRQ_REGS"""
|
|
menuitem "PCIE_MSG_IRQ_REGS" "per , ""NSS,PCIE_MSG_IRQ_REGS"""
|
|
menuitem "PCIE_PORT_LOGIC_REGS" "per , ""NSS,PCIE_PORT_LOGIC_REGS"""
|
|
menuitem "PCIE_PORT_LOGIC_REGS" "per , ""NSS,PCIE_PORT_LOGIC_REGS"""
|
|
menuitem "PCIE_PWR_REGS" "per , ""NSS,PCIE_PWR_REGS"""
|
|
menuitem "PCIE_PWR_REGS" "per , ""NSS,PCIE_PWR_REGS"""
|
|
menuitem "PSC" "per , ""NSS,PSC"""
|
|
menuitem "QSPI" "per , ""NSS,QSPI"""
|
|
menuitem "SEMAPHORE" "per , ""NSS,SEMAPHORE"""
|
|
)
|
|
popup "PLL_Controller"
|
|
(
|
|
menuitem "PLL" "per , ""PLL_Controller,PLL"""
|
|
)
|
|
popup "PRU_ICSS"
|
|
(
|
|
menuitem "CIC" "per , ""PRU_ICSS,CIC"""
|
|
menuitem "MCASP_0__CFG" "per , ""PRU_ICSS,MCASP_0__CFG"""
|
|
menuitem "MCASP_1__CFG" "per , ""PRU_ICSS,MCASP_1__CFG"""
|
|
menuitem "MCASP_2__CFG" "per , ""PRU_ICSS,MCASP_2__CFG"""
|
|
menuitem "MCASP_0__FIFO_CFG" "per , ""PRU_ICSS,MCASP_0__FIFO_CFG"""
|
|
menuitem "MCASP_1__FIFO_CFG" "per , ""PRU_ICSS,MCASP_1__FIFO_CFG"""
|
|
menuitem "MCASP_2__FIFO_CFG" "per , ""PRU_ICSS,MCASP_2__FIFO_CFG"""
|
|
menuitem "MCASP_0_SLV" "per , ""PRU_ICSS,MCASP_0_SLV"""
|
|
menuitem "MCASP_1_SLV" "per , ""PRU_ICSS,MCASP_1_SLV"""
|
|
menuitem "MCASP_2_SLV" "per , ""PRU_ICSS,MCASP_2_SLV"""
|
|
menuitem "MCBSP" "per , ""PRU_ICSS,MCBSP"""
|
|
menuitem "MLB" "per , ""PRU_ICSS,MLB"""
|
|
menuitem "MMCSD_0" "per , ""PRU_ICSS,MMCSD_0"""
|
|
menuitem "MMCSD_1" "per , ""PRU_ICSS,MMCSD_1"""
|
|
menuitem "PRU_ICSS_0_CFG" "per , ""PRU_ICSS,PRU_ICSS_0_CFG"""
|
|
menuitem "PRU_ICSS_1_CFG" "per , ""PRU_ICSS,PRU_ICSS_1_CFG"""
|
|
menuitem "PRU_ICSS_0_ECAP" "per , ""PRU_ICSS,PRU_ICSS_0_ECAP"""
|
|
menuitem "PRU_ICSS_1_ECAP" "per , ""PRU_ICSS,PRU_ICSS_1_ECAP"""
|
|
menuitem "PRU_ICSS_0_ECC_CFG" "per , ""PRU_ICSS,PRU_ICSS_0_ECC_CFG"""
|
|
menuitem "PRU_ICSS_1_ECC_CFG" "per , ""PRU_ICSS,PRU_ICSS_1_ECC_CFG"""
|
|
menuitem "PRU_ICSS_0_IEP" "per , ""PRU_ICSS,PRU_ICSS_0_IEP"""
|
|
menuitem "PRU_ICSS_1_IEP" "per , ""PRU_ICSS,PRU_ICSS_1_IEP"""
|
|
menuitem "PRU_ICSS_0_INTC" "per , ""PRU_ICSS,PRU_ICSS_0_INTC"""
|
|
menuitem "PRU_ICSS_1_INTC" "per , ""PRU_ICSS,PRU_ICSS_1_INTC"""
|
|
menuitem "PRU_ICSS_0_MII_MDIO" "per , ""PRU_ICSS,PRU_ICSS_0_MII_MDIO"""
|
|
menuitem "PRU_ICSS_1_MII_MDIO" "per , ""PRU_ICSS,PRU_ICSS_1_MII_MDIO"""
|
|
menuitem "PRU_ICSS_0_MII_RT" "per , ""PRU_ICSS,PRU_ICSS_0_MII_RT"""
|
|
menuitem "PRU_ICSS_1_MII_RT" "per , ""PRU_ICSS,PRU_ICSS_1_MII_RT"""
|
|
menuitem "PRU_ICSS_0_PRU0_CTRL" "per , ""PRU_ICSS,PRU_ICSS_0_PRU0_CTRL"""
|
|
menuitem "PRU_ICSS_0_PRU1_CTRL" "per , ""PRU_ICSS,PRU_ICSS_0_PRU1_CTRL"""
|
|
menuitem "PRU_ICSS_1_PRU0_CTRL" "per , ""PRU_ICSS,PRU_ICSS_1_PRU0_CTRL"""
|
|
menuitem "PRU_ICSS_1_PRU1_CTRL" "per , ""PRU_ICSS,PRU_ICSS_1_PRU1_CTRL"""
|
|
menuitem "PRU_ICSS_0_UART" "per , ""PRU_ICSS,PRU_ICSS_0_UART"""
|
|
menuitem "PRU_ICSS_1_UART" "per , ""PRU_ICSS,PRU_ICSS_1_UART"""
|
|
)
|
|
popup "RFBI"
|
|
(
|
|
menuitem "RFBI" "per , ""RFBI,RFBI"""
|
|
)
|
|
popup "SPI"
|
|
(
|
|
menuitem "SPI0" "per , ""SPI,SPI0"""
|
|
menuitem "SPI1" "per , ""SPI,SPI1"""
|
|
menuitem "SPI2" "per , ""SPI,SPI2"""
|
|
menuitem "SPI3" "per , ""SPI,SPI3"""
|
|
)
|
|
popup "Timers"
|
|
(
|
|
menuitem "TIMER_0" "per , ""Timers,TIMER_0"""
|
|
menuitem "TIMER_1" "per , ""Timers,TIMER_1"""
|
|
menuitem "TIMER_2" "per , ""Timers,TIMER_2"""
|
|
menuitem "TIMER_3" "per , ""Timers,TIMER_3"""
|
|
menuitem "TIMER_4" "per , ""Timers,TIMER_4"""
|
|
menuitem "TIMER_5" "per , ""Timers,TIMER_5"""
|
|
menuitem "TIMER_6" "per , ""Timers,TIMER_6"""
|
|
)
|
|
popup "UART"
|
|
(
|
|
menuitem "UART_0" "per , ""UART,UART_0"""
|
|
menuitem "UART_1" "per , ""UART,UART_1"""
|
|
menuitem "UART_2" "per , ""UART,UART_2"""
|
|
)
|
|
popup "USB"
|
|
(
|
|
menuitem "USB_0_CFG" "per , ""USB,USB_0_CFG"""
|
|
menuitem "USB_0_CFG" "per , ""USB,USB_0_CFG"""
|
|
menuitem "USB_1_CFG" "per , ""USB,USB_1_CFG"""
|
|
menuitem "USB_1_CFG" "per , ""USB,USB_1_CFG"""
|
|
menuitem "USB_WRAPPER" "per , ""USB,USB_WRAPPER"""
|
|
)
|
|
)
|
|
)
|
|
else
|
|
(
|
|
popup "66AK2Gx-ICSS"
|
|
(
|
|
popup "ICSS_0"
|
|
(
|
|
menuitem "ECC_CFG" "per , ""ICSS_0,ECC_CFG"""
|
|
menuitem "CFG" "per , ""ICSS_0,CFG"""
|
|
menuitem "PRU0_CTRL" "per , ""ICSS_0,PRU0_CTRL"""
|
|
menuitem "PRU1_CTRL" "per , ""ICSS_0,PRU1_CTRL"""
|
|
menuitem "INTC" "per , ""ICSS_0,INTC"""
|
|
menuitem "UART" "per , ""ICSS_0,UART"""
|
|
menuitem "ECAP" "per , ""ICSS_0,ECAP"""
|
|
menuitem "IEP" "per , ""ICSS_0,IEP"""
|
|
menuitem "MII_RT" "per , ""ICSS_0,MII_RT"""
|
|
menuitem "MII_MDIO" "per , ""ICSS_0,MII_MDIO"""
|
|
menuitem "DEBUG_0" "per , ""ICSS_0,DEBUG_0"""
|
|
menuitem "DEBUG_1" "per , ""ICSS_0,DEBUG_1"""
|
|
)
|
|
popup "ICSS_1"
|
|
(
|
|
menuitem "ECC_CFG" "per , ""ICSS_1,ECC_CFG"""
|
|
menuitem "CFG" "per , ""ICSS_1,CFG"""
|
|
menuitem "PRU0_CTRL" "per , ""ICSS_1,PRU0_CTRL"""
|
|
menuitem "PRU1_CTRL" "per , ""ICSS_1,PRU1_CTRL"""
|
|
menuitem "INTC" "per , ""ICSS_1,INTC"""
|
|
menuitem "UART" "per , ""ICSS_1,UART"""
|
|
menuitem "ECAP" "per , ""ICSS_1,ECAP"""
|
|
menuitem "IEP" "per , ""ICSS_1,IEP"""
|
|
menuitem "MII_RT" "per , ""ICSS_1,MII_RT"""
|
|
menuitem "MII_MDIO" "per , ""ICSS_1,MII_MDIO"""
|
|
menuitem "DEBUG_0" "per , ""ICSS_1,DEBUG_0"""
|
|
menuitem "DEBUG_1" "per , ""ICSS_1,DEBUG_1"""
|
|
)
|
|
)
|
|
)
|
|
)
|