370 lines
7.2 KiB
Plaintext
370 lines
7.2 KiB
Plaintext
.globl _start
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.globl _exit
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#ifdef BOOT_FROM_FLASH
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.text
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.section .rhcw,"a" # Reset configuration half word (RCHW)
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# ifdef __PPC_VLE__
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.long 0x015a0000 # Magic BOOT_ID for Freescale VLE code
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# else
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.long 0x005a0000 # Magic BOOT_ID for Power Architecture code
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# endif
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.long _start
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#endif
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.macro li32 reg,imm
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lis \reg,\imm@h
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ori \reg,\reg,\imm@l
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.endm
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.macro ivor spr,reg,imm
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lis \reg,0
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ori \reg,\reg,\imm@l # "li reg,\imm@l" should work too
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mtspr \spr,\reg
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.endm
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.text
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.section .start,"xa"
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_start:
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li %r0,0
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li %r1,0
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li %r2,0
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li %r3,0
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li %r4,0
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li %r5,0
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li %r6,0
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li %r7,0
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li %r8,0
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li %r9,0
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li %r10,0
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li %r11,0
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li %r12,0
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li %r13,0
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li %r14,0
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li %r15,0
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li %r16,0
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li %r17,0
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li %r18,0
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li %r19,0
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li %r20,0
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li %r21,0
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li %r22,0
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li %r23,0
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li %r24,0
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li %r25,0
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li %r26,0
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li %r27,0
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li %r28,0
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li %r29,0
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li %r30,0
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li %r31,0
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init_stackpointer:
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li32 %sp,__stack_end
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init_int_vector_prefix:
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lis %r3,IVOR0_entry@h
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mtspr 63,%r3 # IVPR
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# ifdef __PPC_VLE__
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check_cpu:
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mfspr %r7,287 # read Processor Version Register (PVR)
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srwi %r7,%r7,20 # get only upper 12 bit, which contain Manuf.ID and processor type fields
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cmpwi %r7,0x817 # check if its an Freescale e200z0 core (0b100000010111)
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beq end_mmu # for e200z0 branch over initialization of Interrupt Vector Offset table (hardwired) and MMU (MMU not available)
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#endif
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init_int_vector_offsets:
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ivor 400,%r3,IVOR0_entry # IVOR0
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ivor 401,%r3,IVOR1_entry # IVOR1
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ivor 402,%r3,IVOR2_entry # IVOR2
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ivor 403,%r3,IVOR3_entry # IVOR3
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ivor 404,%r3,IVOR4_entry # IVOR4
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ivor 405,%r3,IVOR5_entry # IVOR5
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ivor 406,%r3,IVOR6_entry # IVOR6
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ivor 407,%r3,IVOR7_entry # IVOR7
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ivor 408,%r3,IVOR8_entry # IVOR8
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ivor 409,%r3,IVOR9_entry # IVOR9
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ivor 410,%r3,IVOR10_entry # IVOR10
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ivor 411,%r3,IVOR11_entry # IVOR11
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ivor 412,%r3,IVOR12_entry # IVOR12
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ivor 413,%r3,IVOR13_entry # IVOR13
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ivor 414,%r3,IVOR14_entry # IVOR14
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ivor 415,%r3,IVOR15_entry # IVOR15
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ivor 528,%r3,IVOR32_entry # IVOR32
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ivor 529,%r3,IVOR33_entry # IVOR33
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#ifndef QORIQ
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ivor 530,%r3,IVOR34_entry # IVOR34
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#endif
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#ifdef BOOT_FROM_FLASH
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init_mmu:
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li32 %r4,__tlbdata_size
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mtctr %r4
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li32 %r4,__tlbdata_start
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subi %r4,%r4,4
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init_mmu_loop:
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lwzu %r3, 4(%r4)
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mtspr 624,%r3 # MAS0
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lwzu %r3, 4(%r4)
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mtspr 625,%r3 # MAS1
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lwzu %r3, 4(%r4)
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mtspr 626,%r3 # MAS2
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lwzu %r3, 4(%r4)
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mtspr 627,%r3 # MAS3
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tlbwe
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isync
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bdnz init_mmu_loop
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#endif
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end_mmu:
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#ifndef QORIQ
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disable_watchdog:
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li32 %r4,0xFFF38000 #Software Watchdog Timer (SWT) base address
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li32 %r3,0xC520
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stw %r3,0x10(%r4) # SWT_SR : 1st magic word to clear the soft lock bit
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li32 %r3,0xD928
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stw %r3,0x10(%r4) # SWT_SR : 2nd magic word to clear the soft lock bit
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li32 %r3,0xC000011A
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stw %r3,0x00(%r4) # SWT_CR : disable watchdog and set soft lock bit
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#endif
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#ifdef BOOT_FROM_FLASH
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init_sram:
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# Init ECC of SRAM (and clear BSS section at the same time)
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# For ECC we wouldn't care about the content of the registers,
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# but for the BSS section we're lucky that we've set r16-r31 to zero before
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li32 %r3,__SRAM_start
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li32 %r4,__SRAM_size
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srwi %r4,%r4,6 # divide size of SRAM by 64=16*4 (16-Registers with 4 Bytes)
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mtctr %r4
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init_sram_loop:
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stmw %r16,0(%r3) # write r16-r31 to SRAM to initialize ECC
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addi %r3,%r3,64
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bdnz init_sram_loop
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init_data:
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li32 %r3,__data_vaddr
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li32 %r4,__data_laddr
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li32 %r5,__data_size
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bl memcpy
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#else
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init_stack:
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li %r0,0
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stw %r0,0(%sp) # clear Back Chain Word
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bss_clear:
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li32 %r3,__bss_start
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li32 %r4,__bss_size
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cmpwi %r4,0
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beq gomain
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srwi %r4,%r4,2
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mtctr %r4
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subi %r3,%r3,4
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bss_clear_loop:
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stwu %r0,4(%r3)
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bdnz bss_clear_loop
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#endif
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gomain:
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li %r3,0
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li %r4,0
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li %r5,0
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bl main
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_exit:
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b _exit
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_start_background: # very reduced start-sequence for secondary core of a Bolero3M
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li32 %r0,_sp_background
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lwz %sp,0(%r0) # load initial value of stack pointer from memory
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li %r0,0
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stw %r0,0(%sp) # clear Back Chain Word
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bl background
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b _exit
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.align 2
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_sp_background:
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.long 0x40020000
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#ifdef BOOT_FROM_FLASH
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.rodata
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.section .mmudata,"a"
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__tlbdata_start:
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/*** TLB1 entry 0 -> FLASH ***/
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.long 0x10000000 # MAS0: ESL 0
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.long 0x80000600 # MAS1: valid, no-protect, global, 4 MB
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# ifdef __PPC_VLE__
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.long 0x00000020 # MAS2: log.addr.0x00000000, big-endian, VLE
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# else
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.long 0x00000000 # MAS2: log.addr.0x00000000, big-endian
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# endif
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.long 0x0000003F # MAS3: phy.addr.0x00000000, full-access
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/*** TLB1 entry 1 -> SRAM ***/
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.long 0x10010000 # MAS0: ESL 1
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.long 0x80000400 # MAS1: valid, no-protect, global, 256 KBytes
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.long 0x40000000 # MAS2: log.addr.0x40000000, big-endian
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.long 0x4000003F # MAS3: phy.addr.0x40000000, full-access
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/*** TLB1 entry 2 -> Flash configuration ***/
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.long 0x10020000 # MAS0: ESL 2
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.long 0xC0000500 # MAS1: valid, no-protect, global, 1 MB
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.long 0xC3F0000A # MAS2: log.addr.0xC3F00000, cache-inhibited, guarded (no speculative access), big-endian
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.long 0xC3F0003F # MAS3: phy.addr.0xC3F00000, full-access
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/*** TLB1 entry 3 -> Peripherals ***/
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.long 0x10030000 # MAS0: ESL 3
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.long 0xC0000500 # MAS1: valid, no-protect, global, 1 MB
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.long 0xFFF0000A # MAS2: log.addr.0xFFF00000, cache-inhibited, guarded (no speculative access), big-endian
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.long 0xFFF0003F # MAS3: phy.addr.0xFFF00000, full-access
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/*** TLB1 entry 4 -> disable default entry of SPC564A80-V2 ***/
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.long 0x10040000 # MAS0: ESL 4
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.long 0x00000000 # MAS1: invalid
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.long 0x00000000 # MAS2
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.long 0x00000000 # MAS3
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__tlbdata_end:
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.set __tlbdata_size, (__tlbdata_end-__tlbdata_start)/16
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#endif
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.section .ivec,"xa" # for e200z0 cores this section must be aligned to 4096 bytes (since this e200z0 has a hardwired Interrupt Vector Offset table)
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.align 4
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IVOR0_entry: #Critical Input
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nop
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nop
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nop
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b IVOR0_entry
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.align 4
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IVOR1_entry: #Machine Check
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nop
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nop
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nop
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b IVOR1_entry
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.align 4
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IVOR2_entry: #Data Storage
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nop
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nop
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nop
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b IVOR2_entry
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.align 4
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IVOR3_entry: #Instruction Storage
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nop
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nop
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nop
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b IVOR3_entry
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.align 4
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IVOR4_entry: #External Input
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nop
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nop
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nop
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b IVOR4_entry
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.align 4
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IVOR5_entry: #Alignment
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nop
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nop
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nop
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b IVOR5_entry
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.align 4
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IVOR6_entry: #Program
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nop
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nop
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nop
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b IVOR6_entry
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.align 4
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IVOR7_entry: #Floating-Point Unavailable
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nop
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nop
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nop
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b IVOR7_entry
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.align 4
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IVOR8_entry: #System Call
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nop
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nop
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nop
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b IVOR8_entry
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.align 4
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IVOR9_entry: #Auxiliary Processor Unavailable
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nop
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nop
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nop
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b IVOR9_entry
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.align 4
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IVOR10_entry: #Decrementer
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nop
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nop
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nop
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b IVOR10_entry
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.align 4
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IVOR11_entry: #Fixed Interval Timer
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nop
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nop
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nop
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b IVOR11_entry
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.align 4
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IVOR12_entry: #Watchdog
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nop
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nop
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nop
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b IVOR12_entry
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.align 4
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IVOR13_entry: #Data TLB Error
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nop
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nop
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nop
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b IVOR13_entry
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.align 4
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IVOR14_entry: #Instruction TLB Error
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nop
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nop
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nop
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b IVOR14_entry
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.align 4
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IVOR15_entry: #Debug
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nop
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nop
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nop
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b IVOR15_entry
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.align 4
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IVOR32_entry: #SPE APU unavailable
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nop
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nop
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nop
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b IVOR15_entry
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.align 4
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IVOR33_entry: #SPE Floating-point Data
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nop
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nop
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nop
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b IVOR15_entry
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.align 4
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IVOR34_entry: #SPE Floating-point Round
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nop
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nop
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nop
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b IVOR15_entry
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