69 lines
2.3 KiB
Plaintext
69 lines
2.3 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: Readme for FreeRTOS on ARM/ARM64
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; @Description:
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; This file includes necessary patches for FreeRTOS to support Task aware
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; tracing.
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;
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; @Keywords: awareness, RTOS, FreeRTOS
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; @Author: AME
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: readme.txt 18850 2022-01-26 18:41:29Z bschroefel $
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= Debug =
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== Exception Level ==
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Per default the awareness assumes FreeRTOS is running in NonSecure EL1 / Supervisor
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mode. If that is not the case, the parameter "/ACCESS" must be used.
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Example - FreeRTOS in NonSecure EL1
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TASK.CONFIG ~~/demo/arm/kernel/freertos/freertos.t32
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Example - FreeRTOS in EL2 / Hypervisor mode
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TASK.CONFIG ~~/demo/arm/kernel/freertos/freertos.t32 /ACCESS H:
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Example - FreeRTOS in EL3 / Monitor mode (64bit cores only)
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TASK.CONFIG ~~/demo/arm/kernel/freertos/freertos.t32 /ACCESS M:
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== Stack Evaluation ==
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For FreeRTOS-Version>=10 make use of configRECORD_STACK_HIGH_ADDRESS.
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<FreeRTOSConfig.h>
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#define configCHECK_FOR_STACK_OVERFLOW 2
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#define configRECORD_STACK_HIGH_ADDRESS 1
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</FreeRTOSConfig.h>
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= Task aware Trace =
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== CortexA/R without DataTrace ==
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Applicable for ARMv8/v9 cores in 64bit mode e.g. Cortex-A53/R82.
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The C-MACRO traceTASK_SWITCHED_IN is used to write the pxCurrentTCB pointer
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(address of the current task structure) to the CONTEXTIDR_EL1 register.
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<FreeRTOSConfig.h>
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#define traceTASK_SWITCHED_IN() \
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{ \
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__asm volatile ("msr contextidr_el1,%0" : :"r" (pxCurrentTCB)); \
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}
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</FreeRTOSConfig.h>
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Setting within TRACE32:
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ETM.ContextID 32
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ETM.TraceON
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ETM.ON
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= Task aware Trace =
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== CortexA/R without DataTrace ==
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Applicable for ARMv7, ARMv8, ARMv9 cores in 32bit mode, e.g. CortexA32/R52/A7.
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Description: A function T32_Magic_Update is used to write the pxCurrectTCB value to the CONTEXTIDR (C15:0x10d).
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The C-MACRO traceTASK_SWITCHED_IN is used to write the pxCurrentTCB pointer
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(address of the current task structure) to the CONTEXTIDR (C15:0x10d) register.
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<FreeRTOSConfig.h>
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#define traceTASK_SWITCHED_IN() \
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{ \
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__asm volatile ("MCR P15, 0x0,%0,C13,C0,0x1" : :"r" (pxCurrentTCB)); \
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}
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</FreeRTOSConfig.h>
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Setting within TRACE32:
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ETM.ContextID 32
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ETM.TraceON
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ETM.ON
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