131 lines
4.0 KiB
Plaintext
131 lines
4.0 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: S3C2413 NAND FLASH Programming Script
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; @Description:
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; NAND FLASH(SAMSUNG, K9F5608) is connected to CS0
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;
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; SDRAM : 0x30000000
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; Command Register : 0x4E000008
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; AddRESets Register : 0x4E00000C
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; Data Register : 0x4E000010
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;
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; @Author: jjeong
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; @Chip: S3C2410X
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; @Keywords: SAMSUNG K9F5608 NAND
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; --------------------------------------------------------------------------------
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; $Id: s3c2413-nand5608.cmm 10516 2022-02-02 11:39:30Z bschroefel $
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LOCAL &arg1
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ENTRY &arg1
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&arg1=STRing.UPpeR("&arg1") // for example "PREPAREONLY"
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; system controller initialization
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RESet
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SYStem.CPU s3c2413x
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SYStem.JtagClock rtck
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SYStem.Mode Up
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PER.Set.simple C15:0x1 %Long 0x78 ;MMU & Cache disable
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Data.Set SD:0x53000000 %LE %Long 0x0 ; disable watchdog
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Data.Set SD:0x48800004 %LE %Long 0xc0 ; ebi (BANK_CFG : SDRAM)
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; 12MHz
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Data.Set SD:0x4C000014 %LE %Long 0x65 ; set clkdiv, 1:2:4 (UCLK:48M/2, HALFHCLK=HCLK/2)
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Data.Set SD:0x4C000004 %LE %Long 0x0007D041 ; Mpll:266MHz, Pll off(default=1[bit20]), MDIV[19:12]=0x7D, PDIV[9:4]=0x04, SDIV[3:0]=0x1
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Data.Set SD:0x4C00001C %LE %Long 0x00000030 ; Clock source control Fout=mpll, Fout=upll
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Data.Set SD:0x4C000008 %LE %Long 0x0040070 ; Upll:96MHz, MDIV[19:12]=0x40(64), PDIV[9:4]=0x07, SDIV[3:0]=0x0, FOUTupll(96M) = (64+8)*12M/((7+2)*2^0)
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GOSUB sdram_init
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// NAND FLASH Controller setting.
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Data.Set ASD:0x4E000000 %Long 0x80007774
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Data.Set ASD:0x4E000004 %Long 0x00000005 ;NAND boot mode & NAND flash enable
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FLASHFILE.RESet
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//FLASHFILE.Config <cmd_reg> <addr_reg> <io_reg>
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FLASHFILE.CONFIG 0x4E000008 0x4E00000C 0x4E000010
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// FLASHFILE.TARGET <code range> <data range> <Algorithm file>
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FLASHFILE.TARGET 0x30000000++0x1FFF 0x30002000++0x3FFF ~~/demo/arm/flash/byte/nand5608.bin /KEEP
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//Read FLASH Manufacture and Device ID
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FLASHFILE.GETID
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//End of the test prepareonly
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IF "&arg1"=="PREPAREONLY"
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ENDDO
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FLASHFILE.DUMP 0x0
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;FLASHFILE.ERASE 0x0--0x7FFFFFF /EraseBadBlocks
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;FLASHFILE.LOAD * 0x0 /WriteBadBlocks
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;FLASHFILE.LOAD * 0x0 /WriteBadBlocks /ComPare
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ENDDO
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sdram_init:
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;SDRAM Initialization
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; setting the configuration register rBANKCON123
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; assert PALL
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; wait refresh 255 cycle
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; 2 auto-refresh cycle
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; assert MRS
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; normal refresh
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; assert EMRS
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; assert Normal mode
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; now ready sdram operation
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; 1st : configuration register
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Data.Set SD:0x48000000 %LE %Long 0x48904 ; BANKCFG
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; RASBW0[18:17] = 10 : RAS BANK0 13bit
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; RASBW1[15:14] = 10 : RAS BANK1 13bit
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; CASBW0[12:11] = 01 : CAS BANK0 9bit
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; CASBW1[09:08] = 01 : CAS BANK1 9bit
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; ADDRCFG0[07:06] = 00 : BA, RAS, CAS
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; ADDRCFG1[05:04] = 00 : BA, RAS, CAS
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; MEMCFG[03:02] = 01 : mSDR
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; BW[00] = 00 : 32bit
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Data.Set SD:0x48000004 %LE %Long 0x40 ; BANKCON1 - mobile dram controller (WBUF[6]=enable)
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Data.Set SD:0x48000008 %LE %Long 0x57003a ; BANKCON2 - timing parameter
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; tRAS[23:20] = 0101 (6 clock)
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; tRC[19:16] = 0111 (8 clock)
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; CAS La[5:4] = 11 (3 clock)
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; tRCD[3:2] = 10 (3 clock)
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; tRP[1:0] = 10 (3 clock)
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Data.Set SD:0x4800000c %LE %Long 0x80000030 ; BANKCON3 - EMRS register
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; BA[31:30] = 10 (Bank Address for EMRS)
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; CAS Lat[6:4] = 011 (3 clock)
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;1st : issue precharge all command
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Data.Set SD:0x48000004 %LE %Long 0x41 ; BANKCON1 INIT[1:0] = 01 (issue PALL Cmd)
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;2nd : make refresh cycle 32clk
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Data.Set SD:0x48000010 %LE %Long 0xff ; REFRESH REFCYC[15:0]
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;3rd : wait 120clk
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Register.Set r0 r(r0)
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;1st : issue MRS
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Data.Set SD:0x48000004 %LE %Long 0x42 ; BANKCON1 INIT[1:0] = 10 (issue MRS Cmd)
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;4th : set normal operation refresh cycle
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Data.Set SD:0x48000010 %LE %Long 0x313 ; REFRESH REFCYC[15:0]
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;1st : issue EMRS
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Data.Set SD:0x48000004 %LE %Long 0x43 ; BANKCON1 INIT[1:0] = 11 (issue EMRS Cmd)
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;1st : issue Normal mode
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Data.Set SD:0x48000004 %LE %Long 0x40 ; BANKCON1 INIT[1:0] = 00 (Normal Operation)
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RETURN |