298 lines
13 KiB
Plaintext
298 lines
13 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: HYPER FLASH Program script for the S32G274 S32G254 S32G233 S32G234
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; @Description:
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; The S26HS512(Infineon, Hyper) is connected to the QSPI0 controller
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;
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; SRAM: 0x34000000
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; QuadSPI(controller) Base: 0x40134000
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; QuadSPI memory mapped ADDRESS: 0x00000000
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;
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; @Chip: S32G274
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; @Board: S32G274-EVB
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; @Author: JIM
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; @Keywords: Spansion QuadSPI
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: s32g274-cm7-hyper.cmm 12743 2023-11-17 08:11:30Z mschaeffner $
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PRIVATE ¶meters
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ENTRY %LINE ¶meters
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PRIVATE ¶m_prepareonly
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¶meters=STRing.UPpeR("¶meters")
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¶m_prepareonly=(STRing.SCAN("¶meters","PREPAREONLY",0)!=-1)
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LOCAL &QSPI_BASE
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LOCAL &QSPI_Cntl_BASE
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LOCAL &Flash_Mode
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// for QSPI0
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&QSPI_BASE=0x00000000 ;qspi0 memory mapped address, not controller address
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&QSPI_Cntl_BASE=0x40134000 ;qspi0 controller base address
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&Flash_Mode=0 ; 0==spi, 1==opisdr 2==opiddr
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; ------------------------------------------------------------------------------
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; Setup CPU
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SYStem.Down
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IF !SYStem.Up()
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(
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RESet
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SYStem.CPU S32G274A-M7-0
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SYStem.CONFIG.DEBUGPORTTYPE JTAG
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SYStem.Option.DUALPORT ON
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SYStem.MemAccess DAP
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SYStem.JtagClock 10MHz
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Trace.DISable
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ETM.OFF
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ITM.OFF
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LOCAL &pdd
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&pdd=OS.PresentDemoDirectory()
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LOCAL &empty
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&empty=FALSE()
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ON ERROR GOSUB
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(
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ON ERROR DEFault
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DO &pdd/hardware/s32g2/scripts/s32g2_connect_m7_0.cmm
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RETURN
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)
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SYStem.Up
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ON ERROR inherit
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)
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; ------------------------------------------------------------------------------
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; Flash Pin Mux Configuration
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GOSUB QuadSPI_PinMux
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; ------------------------------------------------------------------------------
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; Flash Controller Power & Clock Enable
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Data.Set A:0x40030600 %LE %Long 0x0 ;MUX_12_CSC, Clock Mux 14 Selet Control Register
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Data.Set A:0x40030608 %Long %LE 0x80070000 ;MUX_12_DC_0, Clock Mux 12 divider 0 Control Register, around 10.Mhz
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GOSUB QuadSPI_Init_HYPERBUS
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GOSUB READ_ID_TEST
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; ------------------------------------------------------------------------------
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; Init SRAM (16KB) for the flash algorithm
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Data.Set SD:0x34000000++03FFF %Long 0x00000000
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; ------------------------------------------------------------------------------
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; Flash declaration
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Break.RESet
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FLASH.RESet
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FLASH.Create 0x00000000--0x03FFFFFF 0x40000 TARGET Byte
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FLASH.TARGET 0x34000000 E:0x34002000 0x2000 ~~/demo/arm/flash/word/hyper_s32g274.bin /DualPort
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; Flash script ends here if called with parameter PREPAREONLY
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IF ¶m_prepareonly
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ENDDO PREPAREDONE
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; ------------------------------------------------------------------------------
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; Flash programming example
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DIALOG.YESNO "Program flash memory?"
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LOCAL &progflash
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ENTRY &progflash
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IF &progflash
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(
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FLASH.ReProgram.ALL
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Data.LOAD.auto *
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;Data.LOAD.Binary * 0x0
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FLASH.ReProgram.off
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; Reset device
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PRINT "Please power-cycle the board after flash program is complete"
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)
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ENDDO
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QuadSPI_PinMux:
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(
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;QuadSPI A
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Data.Set A:0x4009C394 %Long 0x00282021 ; PF_05(85),QuadSPI A DATA 0 ; FLASH_DAT0
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Data.Set A:0x4009CAB0 %Long 0x2 ; Input Mux PF_05(540) ,QuadSPI A DATA 0 ; FLASH_DAT0
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Data.Set A:0x4009C398 %Long 0x00282021 ; PF_06(86) ,QuadSPI A DATA 1 ; FLASH_DAT1
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Data.Set A:0x4009CAB4 %Long 0x2 ; Input Mux PF_06(541) ,QuadSPI A DATA 1 ; FLASH_DAT1
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Data.Set A:0x4009C39C %Long 0x00282021 ; PF_07(87) ,QuadSPI A DATA 2 ; FLASH_DAT2
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Data.Set A:0x4009CAB8 %Long 0x2 ; Input Mux PF_07(542) ,QuadSPI A DATA 2 ; FLASH_DAT2
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Data.Set A:0x4009C3A0 %Long 0x00282021 ; PF_08(88) ,QuadSPI A DATA 3 ; FLASH_DAT3
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Data.Set A:0x4009CABC %Long 0x2 ; Input Mux PF_8(543) ,QuadSPI A DATA 3 ; FLASH_DAT3
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Data.Set A:0x4009C3A4 %Long 0x00282021 ; PF_09(89) ,QuadSPI A DATA 4; FLASH_DATA4
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Data.Set A:0x4009CAC0 %Long 0x2 ; PF_09(544) ,QuadSPI A DATA 4 ; FLASH_DATA4
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Data.Set A:0x4009C3A8 %Long 0x00282021 ; PF_10(90) ,QuadSPI A DATA 5 ; FLASH_DATA5
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Data.Set A:0x4009CAC4 %Long 0x2 ; PF10(545) ,QuadSPI A DATA 5 ; FLASH_DATA5
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Data.Set A:0x4009C3AC %Long 0x00282021 ; PF_11(91) ,QuadSPI A DATA 6 ; FLASH_DATA6
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Data.Set A:0x4009CAC8 %Long 0x2 ; PF_11(546) ,QuadSPI A DATA 6 ; FLASH_DATA6
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Data.Set A:0x4009C3B0 %Long 0x00282021 ; PF_12(92) ,QuadSPI A DATA 7 ; FLASH_DATA7
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Data.Set A:0x4009CACC %Long 0x2 ; PF_12(547) ,QuadSPI A DATA 7 ; FLASH_DATA7
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Data.Set A:0x4009C3B4 %Long 0x00282021 ; PF_13(93) ,QuadSPI A Data Strobe Input ; FLASH_DATA_STROBE
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Data.Set A:0x4009CAD0 %Long 0x2 ; PF_13(548) ,QuadSPI A Data Strobe Input ; FLASH_DATA_STROBE
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Data.Set A:0x4009C3B8 %Long 0x00083020 ; PF_14(94) , QuadSPI A Interrupt
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Data.Set A:0x4009CAD4 %Long 0x2 ; PF_14(549) , QuadSPI A Interrupt
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Data.Set A:0x4009C3C0 %Long 0x00202021 ; PG_0(96) ,QuadSPI A CLK + Output ; FLASH_CLK
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Data.Set A:0x4009C3C4 %Long 0x00202021 ; PG_1(97) ,QuadSPI A CLK - Output ; FLASH_CLK
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Data.Set A:0x4009C3C8 %Long 0x00202021 ; PG_2(98) ,QuadSPI A CLK_2 + Output ; FLASH_CLK
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Data.Set A:0x4009C3CC %Long 0x00202021 ; PG_3(99) ,QuadSPI A CLK_2 - Output ; FLASH_CLK
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Data.Set A:0x4009C3D0 %Long 0x00203021 ; PG_04(100) ,QuadSPI A Chip Select 0 Output, ; FLASH_CS0
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Data.Set A:0x4009C3D4 %Long 0x00203021 ; PG_05(101) ,QuadSPI A Chip Select 1 Output, ; FLASH_CS1
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;QuadSPI B is not present
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RETURN
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)
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READ_ID_TEST:
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(
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PRINT "READ_ID_TEST..."
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&temp=Data.Long(A:&QSPI_Cntl_BASE)
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Data.Set A:&QSPI_Cntl_BASE %Long (&temp|0x0c00) //clear Tx/Rx buffer
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Data.Set A:&QSPI_Cntl_BASE+0x300 %Long %LE 0x5AF05AF0 ; LUTKEY
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Data.Set A:&QSPI_Cntl_BASE+0x304 %Long %LE 0x2 ; LCKCR
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Data.Set A:&QSPI_Cntl_BASE+0x100 %Long %LE (&QSPI_BASE+0xAAA) ; SFAR , FLASH BASE ADDRESS
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//SEQID 4, CFI Enter
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Data.Set A:&QSPI_Cntl_BASE+0x360 %Long %LE (0x2B18<<16.)|0x4700 ; ADDR_DDR with 3pad (0x2B) and CMD_DDR with 3pad (0x47)
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Data.Set A:&QSPI_Cntl_BASE+0x364 %Long %LE (0x4700<<16.)|0x4F10 ; CMD_DDR with 3pad (0x47) and CADDR_DDR with 3pad (0x4F)
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Data.Set A:&QSPI_Cntl_BASE+0x368 %Long %LE (0x0300<<16.)|0x4798 ; CMD_DDR 3pad (0x47) , 0x98 read cfi
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Data.Set A:&QSPI_Cntl_BASE+0x36C %Long %LE 0x0
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Data.Set A:&QSPI_Cntl_BASE+0x008 %Long (4.<<24.) ; (4.<<24.) , execute SEQID 4
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WAIT 100.ms
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PER.Set.simple A:&QSPI_Cntl_BASE+0x0160 %Long %LE 0x1 ;clear ipc done flag
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PER.Set.simple A:&QSPI_Cntl_BASE %Long %LE Data.Long(A:&QSPI_Cntl_BASE)|0x800 ; clear tx buffer
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//SEQID 5, CFI Read
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Data.Set A:&QSPI_Cntl_BASE+0x100 %Long %LE &QSPI_BASE+0x0
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Data.Set A:&QSPI_Cntl_BASE+0x374 %Long %LE (0x2B18<<16.)|0x47A0 ; ADDR_DDR with 3pad (0x2B) and CMD_DDR with 3pad (0x47)
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Data.Set A:&QSPI_Cntl_BASE+0x378 %Long %LE (0x0F0F<<16.)|0x4F10 ; dummy 3pad (0x0F) and CMD_DDR with 3pad (0x47)
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Data.Set A:&QSPI_Cntl_BASE+0x37C %Long %LE (0x0300<<16.)|0x3B04 ; stop 3pad (0x03) and READ_DDR 3pad (0x3B) 4bytes read
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Data.Set A:&QSPI_Cntl_BASE+0x380 %Long %LE 0x0
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Data.Set A:&QSPI_Cntl_BASE+0x008 %Long %LE (5.<<24.) ; (5.<<24.) , execute SEQID 5
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WAIT 100.ms
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PER.Set.simple A:&QSPI_Cntl_BASE+0x160 %Long %LE 0x1 ;clear ipc done flag
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PER.Set.simple A:&QSPI_Cntl_BASE %Long %LE Data.Long(A:&QSPI_Cntl_BASE)|0x800 ; clear tx buffer
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PRINT "1st 0x" Data.Long(A:&QSPI_Cntl_BASE+0x200)
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PRINT "2nd 0x" Data.Long(A:&QSPI_Cntl_BASE+0x204)
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PRINT "3rd 0x" Data.Long(A:&QSPI_Cntl_BASE+0x208)
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PRINT "4th 0x" Data.Long(A:&QSPI_Cntl_BASE+0x20C)
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//SEQID 4, Reset command
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Data.Set A:&QSPI_Cntl_BASE+0x360 %Long %LE (0x2B18<<16.)|0x4700 ; ADDR_DDR with 3pad (0x2B) and CMD_DDR with 3pad (0x47)
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Data.Set A:&QSPI_Cntl_BASE+0x364 %Long %LE (0x4700<<16.)|0x4F10 ; CMD_DDR with 3pad (0x47) and CADDR_DDR with 3pad (0x4F)
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Data.Set A:&QSPI_Cntl_BASE+0x368 %Long %LE (0x0300<<16.)|0x47F0 ; CMD_DDR 3pad (0x47) , 0xF0 reset
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Data.Set A:&QSPI_Cntl_BASE+0x36C %Long %LE 0x0
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// assert Read id command
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Data.Set A:&QSPI_Cntl_BASE+0x008 %Long (4.<<24.) ; (4.<<24.) , execute SEQID 4
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WAIT 100.ms
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PER.Set.simple A:&QSPI_Cntl_BASE+0x0160 %Long %LE 0x1 ;clear ipc done flag
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PER.Set.simple A:&QSPI_Cntl_BASE %Long %LE Data.Long(A:&QSPI_Cntl_BASE)|0x800 ; clear tx buffer
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RETURN
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)
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QuadSPI_Init_HYPERBUS:
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(
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Data.Set A:&QSPI_Cntl_BASE+0x300 %LE %Long 0x5AF05AF0 ; LUTKEY
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Data.Set A:&QSPI_Cntl_BASE+0x304 %LE %Long 0x2 ; LCKCR
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;Internal DQS pad loopback, SPI x1 mode, AHB and IP modes configured.
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Data.Set A:&QSPI_Cntl_BASE+0x000 %LE %Long Data.Long(A:&QSPI_Cntl_BASE)|(0x1<<14.) ; QuadSPI0->MCR = QuadSPI_MCR_MDIS_MASK; disable module
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Data.Set A:&QSPI_Cntl_BASE+0x000 %LE %Long Data.Long(A:&QSPI_Cntl_BASE)|0x3 ; SW reset
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Data.Set A:&QSPI_Cntl_BASE+0x30 %LE %Long 0x00000000 ; QuadSPI0->BUF0IND
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Data.Set A:&QSPI_Cntl_BASE+0x100 %LE %Long &QSPI_BASE ; SFAR , FLASH BASE ADDRESS
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Data.Set A:&QSPI_Cntl_BASE+0x104 %LE %Long 0x00030803 ; QuadSPI0->SFACR
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; Setup chip select size
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Data.Set A:&QSPI_Cntl_BASE+0x180 %LE %Long 0x08000000 ; QuadSPI0->SFA1AD; set top address to 256MB
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Data.Set A:&QSPI_Cntl_BASE+0x184 %LE %Long 0x08000000 ; QuadSPI0->SFA2AD; set top address to 256MB
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Data.Set A:&QSPI_Cntl_BASE+0x188 %LE %Long 0x08000000 ; QuadSPI0->SFB1AD; set top address to 256MB
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Data.Set A:&QSPI_Cntl_BASE+0x18C %LE %Long 0x08000000 ; QuadSPI0->SFB2AD; set top address to 256MB
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;Program LUT0 with READ
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Data.Set A:&QSPI_Cntl_BASE+0x310 %LE %Long 0x2B1847A0 ; SEQID 0
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Data.Set A:&QSPI_Cntl_BASE+0x314 %LE %Long 0x0F0F4F10
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Data.Set A:&QSPI_Cntl_BASE+0x318 %LE %Long 0x03003B04
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Data.Set A:&QSPI_Cntl_BASE+0x31C %LE %Long 0x0
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Data.Set A:&QSPI_Cntl_BASE+0x320 %LE %Long 0x0
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Data.Set A:&QSPI_Cntl_BASE+0x0C %LE %Long 0x00030303 ; QuadSPI0->FLSHCR = QuadSPI_FLSHCR_TCSH(3) | QuadSPI_FLSHCR_TCSS(3); Flash specific
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Data.Set A:&QSPI_Cntl_BASE+0x1C %LE %Long 0x80008003 ; QuadSPI0->BUF0CR = 32 bytes prefetch size, all master
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Data.Set A:&QSPI_Cntl_BASE+0x60 %LE %Long 0x41200506 ;QuadSPI0->DLLCRA, SLV_DLY_EN
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Data.Set A:&QSPI_Cntl_BASE+0x108 %LE %Long 0x44000000 ; QuadSPI0->SMPR; DLLFSMPFA = 4, DLLFSMPFB = 4.
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Data.Set A:&QSPI_Cntl_BASE+0x00 %LE %Long 0x170F00EC ; QuadSPI0->MCR
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Data.Set A:&QSPI_Cntl_BASE+0x060 %LE %Long Data.Long(A:&QSPI_Cntl_BASE+0x060)|0x1 ; program DLLCRA[SLV_UPD]
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WAIT 100.ms
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Data.Set A:&QSPI_Cntl_BASE+0x060 %LE %Long Data.Long(A:&QSPI_Cntl_BASE+0x060)&0xFFFFFFFE ; clear DLLCRA[SLV_UPD] after program
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Data.Set A:&QSPI_Cntl_BASE+0x16C %Long Data.Long(A:&QSPI_Cntl_BASE+0x16C)|(0x1<<17.) ; "prefetch disable" to see the flash data directly on AHB after the ipcr execute
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RETURN
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)
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QuadSPI_Init_SPI:
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(
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;Internal DQS pad loopback, SPI x1 mode, AHB and IP modes configured.
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Data.Set A:&QSPI_Cntl_BASE+0x000 %LE %Long 0x000F400F ; QuadSPI0->MCR = QuadSPI_MCR_MDIS_MASK; disable module
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;Program LUT0 with READ (SPI 3B address mode)
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Data.Set A:&QSPI_Cntl_BASE+0x310 %LE %Long 0x08180403 ; SEQID 0
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Data.Set A:&QSPI_Cntl_BASE+0x314 %LE %Long 0x24001C08
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Data.Set A:&QSPI_Cntl_BASE+0x318 %LE %Long 0x0
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Data.Set A:&QSPI_Cntl_BASE+0x0C %LE %Long 0x00000303 ; QuadSPI0->FLSHCR = QuadSPI_FLSHCR_TCSH(3) | QuadSPI_FLSHCR_TCSS(3); Flash specific
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; Data.Set A:&QSPI_Cntl_BASE+0x0C %LONG %LE 0x00010303 ; QuadSPI0->FLSHCR, THD[16], Serial flash data in hold time This is valid only in DDR mode
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Data.Set A:&QSPI_Cntl_BASE+0x10 %LE %Long 0x0000200B ; QuadSPI0->BUF0CR = 32 bytes prefetch size, HSE master ID
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Data.Set A:&QSPI_Cntl_BASE+0x1C %LE %Long 0x80002003 ; QuadSPI0->BUF0CR = 32 bytes prefetch size, all master
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Data.Set A:&QSPI_Cntl_BASE+0x30 %LE %Long 0x00000400 ; QuadSPI0->BUF0IND = 1024 bytes buffer size
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Data.Set A:&QSPI_Cntl_BASE+0x60 %LE %Long 0x41200507 ; QuadSPI0->DLLCRA; DDLEN=0,FREQEN=1,REFCNTR=1,DLLRES=2,SLV_FINE_OFFSET=0,SLV_DLY_OFFSET=0,SLV_DLY_COARSE=5,SLV_DLY_FINE=0,SLAVE_AUTO_UPDT=0,SLV_EN=1,SLV_DLL_BYPASS=1,SLV_UPD=1.
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; Data.Set A:&QSPI_Cntl_BASE+0x60 %LE %Long 0x01200007 ; QuadSPI0->DLLCRA
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Data.Set A:&QSPI_Cntl_BASE+0x100 %LE %Long &QSPI_BASE ; SFAR , FLASH BASE ADDRESS
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Data.Set A:&QSPI_Cntl_BASE+0x104 %LE %Long 0x00000000 ; QuadSPI0->SFACR; PPWB = 0
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Data.Set A:&QSPI_Cntl_BASE+0x108 %LE %Long 0x44000000 ; QuadSPI0->SMPR; DLLFSMPFA = 4, DLLFSMPFB = 4.
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Data.Set A:&QSPI_Cntl_BASE+0x110 %LE %Long 0x00000100 ; QuadSPI0->RBCT; RXBRD = 1, AHB read mode.
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; Setup chip select size
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Data.Set A:&QSPI_Cntl_BASE+0x180 %LE %Long 0x10000000 ; QuadSPI0->SFA1AD; set top address to 256MB
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Data.Set A:&QSPI_Cntl_BASE+0x184 %LE %Long 0x20000000 ; QuadSPI0->SFA2AD; set top address to 256MB
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Data.Set A:&QSPI_Cntl_BASE+0x188 %LE %Long 0x30000000 ; QuadSPI0->SFB1AD; set top address to 256MB
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Data.Set A:&QSPI_Cntl_BASE+0x18C %LE %Long 0x40000000 ; QuadSPI0->SFB2AD; set top address to 256MB
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Data.Set A:&QSPI_Cntl_BASE+0x00 %LE %Long 0x000F0C0C ; QuadSPI0->MCR = QuadSPI_MCR_MDIS_MASK; enable module
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&temp=Data.Long(A:&QSPI_Cntl_BASE)
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Data.Set A:&QSPI_Cntl_BASE %Long (&temp|0x0c00) ;Clear Tx/Rx buffer
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RETURN
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)
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