287 lines
12 KiB
Plaintext
287 lines
12 KiB
Plaintext
; --------------------------------------------------------------------------------
|
|
; @Title: SPI FLASH Program script for the S32G274 S32G254 S32G233 S32G234
|
|
; @Description:
|
|
; The MX25UM51245g (MACRONIX) is connected to the QSPI0 controller
|
|
;
|
|
; SRAM: 0x34000000
|
|
; QuadSPI(controller) Base: 0x40134000
|
|
; QuadSPI memory mapped ADDRESS: 0x00000000
|
|
;
|
|
; Prerequisites: Switch Settings
|
|
; set
|
|
; J36:2&3 for Serial NOR Flash
|
|
; BOOT_CFG1[7:6]: 00 ; BOOT from QuadSPI0 interface
|
|
; BOOT_CFG1[1:0]: 01(HyperFlash Mode) and 00(QuadSPI Mode)
|
|
;
|
|
; @Chip: S32G274
|
|
; @Board: S32G274-EVB
|
|
; @Author: JIM
|
|
; @Keywords: Spansion QuadSPI
|
|
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
|
|
; --------------------------------------------------------------------------------
|
|
; $Id: s32g274-ca53-qspi.cmm 12743 2023-11-17 08:11:30Z mschaeffner $
|
|
|
|
PRIVATE ¶meters
|
|
ENTRY %LINE ¶meters
|
|
|
|
PRIVATE ¶m_prepareonly
|
|
¶meters=STRing.UPpeR("¶meters")
|
|
¶m_prepareonly=(STRing.SCAN("¶meters","PREPAREONLY",0)!=-1)
|
|
|
|
|
|
LOCAL &QSPI_BASE
|
|
LOCAL &QSPI_Cntl_BASE
|
|
LOCAL &Flash_Mode
|
|
|
|
// for QSPI0
|
|
&QSPI_BASE=0x00000000 ;qspi0 memory mapped address, not controller address
|
|
&QSPI_Cntl_BASE=0x40134000 ;qspi0 controller base address
|
|
&Flash_Mode=0 ; 0==spi, 1==opisdr 2==opiddr
|
|
|
|
LOCAL &pdd
|
|
&pdd=OS.PresentDemoDirectory()
|
|
|
|
SYStem.Down
|
|
; ------------------------------------------------------------------------------
|
|
;Check if the QuadSPI AHB is already init
|
|
&IVT_header=Data.Long(A:0x0)
|
|
IF (&IVT_header==0x600001D1)
|
|
(
|
|
GOTO FLASH_DECLARATION
|
|
)
|
|
|
|
//* BEGIN QuadSPI AHB Init *//
|
|
; ------------------------------------------------------------------------------
|
|
; Setup CPU
|
|
DO &pdd/hardware/s32g2/scripts/s32g2_connect_a53_0.cmm
|
|
|
|
; ------------------------------------------------------------------------------
|
|
; Flash Pin Mux Configuration
|
|
GOSUB QuadSPI_PinMux
|
|
|
|
; ------------------------------------------------------------------------------
|
|
; Flash Controller Power & Clock Enable
|
|
Data.Set A:0x40030600 %LE %Long 0x0 ;MUX_12_CSC, Clock Mux 14 Selet Control Register
|
|
Data.Set A:0x40030608 %Long %LE 0x80070000 ;MUX_12_DC_0, Clock Mux 12 divider 0 Control Register, around 10.Mhz
|
|
|
|
; ------------------------------------------------------------------------------
|
|
; Flash Controller init, depends on the flash mode
|
|
GOSUB QuadSPI_Init_SPI
|
|
;GOSUB QuadSPI_Init_OPISDR
|
|
;GOSUB QuadSPI_Init_OPIDDR
|
|
|
|
; ------------------------------------------------------------------------------
|
|
; Initialize SRAM
|
|
Data.Set EAXI:0x4019C000 %Long 0x00000001
|
|
|
|
&pdd=OS.PresentDemoDirectory()
|
|
|
|
//* END QuadSPI AHB Init *//
|
|
|
|
FLASH_DECLARATION:
|
|
; ------------------------------------------------------------------------------
|
|
; Flash declaration
|
|
|
|
Break.RESet
|
|
|
|
FLASH.RESet
|
|
FLASH.Create 0x00000000--0x03FFFFFF 0x10000 TARGET Byte
|
|
FLASH.TARGET 0x34000000 E:0x34002000 0x2000 &pdd/flash/byte/snor_s32g274.bin /DualPort
|
|
|
|
; Flash script ends here if called with parameter PREPAREONLY
|
|
IF ¶m_prepareonly
|
|
ENDDO PREPAREDONE
|
|
|
|
; ------------------------------------------------------------------------------
|
|
; Flash programming example
|
|
|
|
DIALOG.YESNO "Program flash memory?"
|
|
LOCAL &progflash
|
|
ENTRY &progflash
|
|
IF &progflash
|
|
(
|
|
FLASH.ReProgram.ALL
|
|
Data.LOAD.auto *
|
|
;Data.LOAD.Binary * 0x00000000
|
|
FLASH.ReProgram.off
|
|
|
|
; Reset device
|
|
PRINT "Please power-cycle the board after flash program is complete"
|
|
)
|
|
|
|
ENDDO
|
|
|
|
READ_ID_TEST:
|
|
(
|
|
PRINT "READ_ID_TEST..."
|
|
&temp=Data.Long(A:&QSPI_Cntl_BASE)
|
|
Data.Set A:&QSPI_Cntl_BASE %Long (&temp|0x0c00) //clear Tx/Rx buffer
|
|
|
|
Data.Set A:&QSPI_Cntl_BASE+0x300 %LE %Long 0x5AF05AF0 ; LUTKEY
|
|
Data.Set A:&QSPI_Cntl_BASE+0x304 %LE %Long 0x2 ; LCKCR
|
|
|
|
//SEQID 5
|
|
Data.Set A:&QSPI_Cntl_BASE+0x374 %LE %Long 0x1c04049f ; LUT25. SEQID 5. (1SEQ==5ea LUTs)
|
|
Data.Set A:&QSPI_Cntl_BASE+0x378 %LE %Long 0x0
|
|
Data.Set A:&QSPI_Cntl_BASE+0x37C %LE %Long 0x0
|
|
|
|
Data.Set A:&QSPI_Cntl_BASE+0x100 %Long &QSPI_BASE ; SFAR , FLASH BASE ADDRESS
|
|
|
|
// assert Read id command
|
|
Data.Set A:&QSPI_Cntl_BASE+0x08 %Long (5.<<24.)
|
|
WAIT 100.ms
|
|
|
|
&temp=Data.Long(A:&QSPI_Cntl_BASE)
|
|
Data.Set ZSD:&QSPI_Cntl_BASE+0x000 %Long (&temp|0x0800) //clear Tx buffer
|
|
|
|
PRINT "1st 0x" Data.Long(A:&QSPI_Cntl_BASE+0x200)&0xFF " (Manufacturer)"
|
|
PRINT "2nd 0x" (Data.Long(A:&QSPI_Cntl_BASE+0x200)>>8.)&0xFF " (Device ID)"
|
|
PRINT "3rd 0x" (Data.Long(A:&QSPI_Cntl_BASE+0x200)>>16.)&0xFF
|
|
PRINT "4th 0x" (Data.Long(A:&QSPI_Cntl_BASE+0x200)>>24.)&0xFF
|
|
|
|
RETURN
|
|
)
|
|
|
|
QuadSPI_PinMux:
|
|
(
|
|
;QuadSPI A
|
|
Data.Set A:0x4009C394 %Long 0x00282021 ; PF_05(85),QuadSPI A DATA 0 ; FLASH_DAT0
|
|
Data.Set A:0x4009CAB0 %Long 0x2 ; Input Mux PF_05(540) ,QuadSPI A DATA 0 ; FLASH_DAT0
|
|
|
|
Data.Set A:0x4009C398 %Long 0x00282021 ; PF_06(86) ,QuadSPI A DATA 1 ; FLASH_DAT1
|
|
Data.Set A:0x4009CAB4 %Long 0x2 ; Input Mux PF_06(541) ,QuadSPI A DATA 1 ; FLASH_DAT1
|
|
|
|
Data.Set A:0x4009C39C %Long 0x00282021 ; PF_07(87) ,QuadSPI A DATA 2 ; FLASH_DAT2
|
|
Data.Set A:0x4009CAB8 %Long 0x2 ; Input Mux PF_07(542) ,QuadSPI A DATA 2 ; FLASH_DAT2
|
|
|
|
Data.Set A:0x4009C3A0 %Long 0x00282021 ; PF_08(88) ,QuadSPI A DATA 3 ; FLASH_DAT3
|
|
Data.Set A:0x4009CABC %Long 0x2 ; Input Mux PF_8(543) ,QuadSPI A DATA 3 ; FLASH_DAT3
|
|
|
|
Data.Set A:0x4009C3A4 %Long 0x00282021 ; PF_09(89) ,QuadSPI A DATA 4; FLASH_DATA4
|
|
Data.Set A:0x4009CAC0 %Long 0x2 ; PF_09(544) ,QuadSPI A DATA 4 ; FLASH_DATA4
|
|
|
|
Data.Set A:0x4009C3A8 %Long 0x00282021 ; PF_10(90) ,QuadSPI A DATA 5 ; FLASH_DATA5
|
|
Data.Set A:0x4009CAC4 %Long 0x2 ; PF10(545) ,QuadSPI A DATA 5 ; FLASH_DATA5
|
|
|
|
Data.Set A:0x4009C3AC %Long 0x00282021 ; PF_11(91) ,QuadSPI A DATA 6 ; FLASH_DATA6
|
|
Data.Set A:0x4009CAC8 %Long 0x2 ; PF_11(546) ,QuadSPI A DATA 6 ; FLASH_DATA6
|
|
|
|
Data.Set A:0x4009C3B0 %Long 0x00282021 ; PF_12(92) ,QuadSPI A DATA 7 ; FLASH_DATA7
|
|
Data.Set A:0x4009CACC %Long 0x2 ; PF_12(547) ,QuadSPI A DATA 7 ; FLASH_DATA7
|
|
|
|
Data.Set A:0x4009C3B4 %Long 0x00282021 ; PF_13(93) ,QuadSPI A Data Strobe Input ; FLASH_DATA_STROBE
|
|
Data.Set A:0x4009CAD0 %Long 0x2 ; PF_13(548) ,QuadSPI A Data Strobe Input ; FLASH_DATA_STROBE
|
|
|
|
Data.Set A:0x4009C3B8 %Long 0x00083020 ; PF_14(94) , QuadSPI A Interrupt
|
|
Data.Set A:0x4009CAD4 %Long 0x2 ; PF_14(549) , QuadSPI A Interrupt
|
|
|
|
Data.Set A:0x4009C3C0 %Long 0x00202021 ; PG_0(96) ,QuadSPI A CLK + Output ; FLASH_CLK
|
|
Data.Set A:0x4009C3C4 %Long 0x00202021 ; PG_1(97) ,QuadSPI A CLK - Output ; FLASH_CLK
|
|
|
|
Data.Set A:0x4009C3C8 %Long 0x00202021 ; PG_2(98) ,QuadSPI A CLK_2 + Output ; FLASH_CLK
|
|
Data.Set A:0x4009C3CC %Long 0x00202021 ; PG_3(99) ,QuadSPI A CLK_2 - Output ; FLASH_CLK
|
|
|
|
Data.Set A:0x4009C3D0 %Long 0x00203021 ; PG_04(100) ,QuadSPI A Chip Select 0 Output, ; FLASH_CS0
|
|
Data.Set A:0x4009C3D4 %Long 0x00203021 ; PG_05(101) ,QuadSPI A Chip Select 1 Output, ; FLASH_CS1
|
|
|
|
;QuadSPI B is not present
|
|
|
|
RETURN
|
|
)
|
|
|
|
QuadSPI_Init_SPI:
|
|
(
|
|
;Internal DQS pad loopback, SPI x1 mode, AHB and IP modes configured.
|
|
Data.Set A:&QSPI_Cntl_BASE+0x000 %LE %Long 0x000F400F ; QuadSPI0->MCR = QuadSPI_MCR_MDIS_MASK; disable module
|
|
|
|
;Program LUT0 with READ (SPI 3B address mode)
|
|
Data.Set A:&QSPI_Cntl_BASE+0x310 %LE %Long 0x08180403 ; SEQID 0
|
|
Data.Set A:&QSPI_Cntl_BASE+0x314 %LE %Long 0x24001C08
|
|
Data.Set A:&QSPI_Cntl_BASE+0x318 %LE %Long 0x0
|
|
|
|
Data.Set A:&QSPI_Cntl_BASE+0x0C %LE %Long 0x00000303 ; QuadSPI0->FLSHCR = QuadSPI_FLSHCR_TCSH(3) | QuadSPI_FLSHCR_TCSS(3); Flash specific
|
|
; Data.Set A:&QSPI_Cntl_BASE+0x0C %LONG %LE 0x00010303 ; QuadSPI0->FLSHCR, THD[16], Serial flash data in hold time This is valid only in DDR mode
|
|
|
|
Data.Set A:&QSPI_Cntl_BASE+0x10 %LE %Long 0x0000200B ; QuadSPI0->BUF0CR = 32 bytes prefetch size, HSE master ID
|
|
Data.Set A:&QSPI_Cntl_BASE+0x1C %LE %Long 0x80002003 ; QuadSPI0->BUF0CR = 32 bytes prefetch size, all master
|
|
Data.Set A:&QSPI_Cntl_BASE+0x30 %LE %Long 0x00000400 ; QuadSPI0->BUF0IND = 1024 bytes buffer size
|
|
|
|
Data.Set A:&QSPI_Cntl_BASE+0x60 %LE %Long 0x41200507 ; QuadSPI0->DLLCRA; DDLEN=0,FREQEN=1,REFCNTR=1,DLLRES=2,SLV_FINE_OFFSET=0,SLV_DLY_OFFSET=0,SLV_DLY_COARSE=5,SLV_DLY_FINE=0,SLAVE_AUTO_UPDT=0,SLV_EN=1,SLV_DLL_BYPASS=1,SLV_UPD=1.
|
|
; Data.Set A:&QSPI_Cntl_BASE+0x60 %LE %Long 0x01200007 ; QuadSPI0->DLLCRA
|
|
|
|
Data.Set A:&QSPI_Cntl_BASE+0x100 %LE %Long &QSPI_BASE ; SFAR , FLASH BASE ADDRESS
|
|
Data.Set A:&QSPI_Cntl_BASE+0x104 %LE %Long 0x00000000 ; QuadSPI0->SFACR; PPWB = 0
|
|
Data.Set A:&QSPI_Cntl_BASE+0x108 %LE %Long 0x44000000 ; QuadSPI0->SMPR; DLLFSMPFA = 4, DLLFSMPFB = 4.
|
|
Data.Set A:&QSPI_Cntl_BASE+0x110 %LE %Long 0x00000100 ; QuadSPI0->RBCT; RXBRD = 1, AHB read mode.
|
|
|
|
; Setup chip select size
|
|
Data.Set A:&QSPI_Cntl_BASE+0x180 %LE %Long 0x10000000 ; QuadSPI0->SFA1AD; set top address to 256MB
|
|
Data.Set A:&QSPI_Cntl_BASE+0x184 %LE %Long 0x20000000 ; QuadSPI0->SFA2AD; set top address to 256MB
|
|
Data.Set A:&QSPI_Cntl_BASE+0x188 %LE %Long 0x30000000 ; QuadSPI0->SFB1AD; set top address to 256MB
|
|
Data.Set A:&QSPI_Cntl_BASE+0x18C %LE %Long 0x40000000 ; QuadSPI0->SFB2AD; set top address to 256MB
|
|
|
|
Data.Set A:&QSPI_Cntl_BASE+0x00 %LE %Long 0x000F0C0C ; QuadSPI0->MCR = QuadSPI_MCR_MDIS_MASK; enable module
|
|
|
|
&temp=Data.Long(A:&QSPI_Cntl_BASE)
|
|
Data.Set A:&QSPI_Cntl_BASE %Long (&temp|0x0c00) ;Clear Tx/Rx buffer
|
|
|
|
RETURN
|
|
)
|
|
|
|
QuadSPI_Init_OPISDR:
|
|
(
|
|
GOSUB QuadSPI_Init_SPI
|
|
|
|
Data.Set A:&QSPI_Cntl_BASE+0x000 %Long 0x010F404F ;disable MDIS (0x1<<14.) & reset
|
|
|
|
//LUT0
|
|
Data.Set A:&QSPI_Cntl_BASE+0x310 %Long 0x071307EC
|
|
Data.Set A:&QSPI_Cntl_BASE+0x314 %Long 0x0F140B20
|
|
Data.Set A:&QSPI_Cntl_BASE+0x318 %Long 0x00001F01
|
|
|
|
Data.Set A:&QSPI_Cntl_BASE+0x00C %Long 0x303 ;Flash memory configuration register
|
|
Data.Set A:&QSPI_Cntl_BASE+0x060 %Long 0x01200007 ;DLL A configuration register
|
|
Data.Set A:&QSPI_Cntl_BASE+0x108 %Long 0x00000020 ;sampling register
|
|
Data.Set A:&QSPI_Cntl_BASE+0x190 %Long 0xAA553443 ;data learn pattern register
|
|
|
|
Data.Set A:&QSPI_Cntl_BASE+0x000 %Long 0x010F004C ;Module Configuration Register
|
|
|
|
RETURN
|
|
)
|
|
|
|
QuadSPI_Init_OPIDDR:
|
|
(
|
|
|
|
GOSUB QuadSPI_Init_SPI
|
|
|
|
Data.Set A:&QSPI_Cntl_BASE+0x000 %LE %Long 0x030F40CF ;disable MDIS (0x1<<14.)
|
|
|
|
//LUT0
|
|
Data.Set A:&QSPI_Cntl_BASE+0x310 %LE %Long 0x471147EE
|
|
Data.Set A:&QSPI_Cntl_BASE+0x314 %LE %Long 0x0F142B20
|
|
Data.Set A:&QSPI_Cntl_BASE+0x318 %LE %Long 0x00003B80
|
|
Data.Set A:&QSPI_Cntl_BASE+0x31C %LE %Long 0x00000000
|
|
|
|
Data.Set A:&QSPI_Cntl_BASE+0x00C %LE %Long 0x10303 ;Flash memory configuration register
|
|
Data.Set A:&QSPI_Cntl_BASE+0x010 %LE %Long 0x0000000E ; QuadSPI0->BUF0CR = 32 bytes prefetch size, HSE master ID
|
|
Data.Set A:&QSPI_Cntl_BASE+0x01C %LE %Long 0x80080000 ; QuadSPI0->BUF0CR = 32 bytes prefetch size, all master
|
|
Data.Set A:&QSPI_Cntl_BASE+0x030 %LE %Long 0x00000000 ; QuadSPI0->BUF0IND = 1024 bytes buffer size
|
|
|
|
Data.Set A:&QSPI_Cntl_BASE+0x100 %LE %Long 0x0 ; SFAR , FLASH BASE ADDRESS
|
|
Data.Set A:&QSPI_Cntl_BASE+0x104 %LE %Long 0x20000 ; QuadSPI0->SFACR; SWAP n, n+1 order
|
|
Data.Set A:&QSPI_Cntl_BASE+0x108 %LE %Long 0x44000000 ; sampling register
|
|
Data.Set A:&QSPI_Cntl_BASE+0x110 %LE %Long 0x00000000 ; QuadSPI0->RBCT; RXBRD = 1, AHB read mode.
|
|
|
|
Data.Set A:&QSPI_Cntl_BASE+0x180 %LE %Long 0x80000000 ; QuadSPI0->SFA1AD; set top address to 256MB
|
|
Data.Set A:&QSPI_Cntl_BASE+0x184 %LE %Long 0x80000000 ; QuadSPI0->SFA2AD; set top address to 256MB
|
|
Data.Set A:&QSPI_Cntl_BASE+0x188 %LE %Long 0x80000000 ; QuadSPI0->SFB1AD; set top address to 256MB
|
|
Data.Set A:&QSPI_Cntl_BASE+0x18C %LE %Long 0x80000000 ; QuadSPI0->SFB2AD; set top address to 256MB
|
|
|
|
Data.Set A:&QSPI_Cntl_BASE+0x190 %LE %Long 0xAA553443 ;data learn pattern register
|
|
|
|
Data.Set A:&QSPI_Cntl_BASE+0x060 %LE %Long 0x4280000D ;QuadSPI0->DLLCRA DLL A configuration register
|
|
Data.Set A:&QSPI_Cntl_BASE+0x000 %LE %Long 0x030F00CC ;enable MDIS (0x1<<14.)
|
|
|
|
RETURN
|
|
)
|